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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcusat_coverage.vrpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #inc "mcusat_cov_inc.pal"; | |
36 | ||
37 | #include <vera_defines.vrh> | |
38 | #include <ListMacros.vrh> | |
39 | #include "plusArgMacros.vri" | |
40 | #include "mcusat_cov_defines.vrh" | |
41 | #include "mcusat_cov.if.vrh" | |
42 | #include "mcusat_cov_ports_binds.vrh" | |
43 | ||
44 | // extern event dram_diag_done; | |
45 | ||
46 | ||
47 | class ${prefix}dram_coverage { | |
48 | ||
49 | ||
50 | event mcu01_secc_evnt_trig; | |
51 | event mcu01_scb_secc_evnt_trig; | |
52 | event mcu01_mecc_evnt_trig; | |
53 | event mcu01_scb_mecc_evnt_trig; | |
54 | event mcu01_secc_error_evnt_trig; | |
55 | event mcu01_scb_secc_error_evnt_trig; | |
56 | event mcu01_mecc_error_evnt_trig; | |
57 | event mcu01_scb_mecc_error_evnt_trig; | |
58 | event mcu01_secc_scbs_error_evnt_trig; | |
59 | event mcu01_secc_mecc_error_evnt_trig; | |
60 | event mcu01_secc_scbm_error_evnt_trig; | |
61 | event mcu01_scb_mecc1_error_evnt_trig; | |
62 | event mcu01_scb_scbm_error_evnt_trig; | |
63 | event mcu01_mecc_scbm_error_evnt_trig; | |
64 | event mcu012_secc_error_evnt_trig; | |
65 | event mcu012_scb_secc_error_evnt_trig; | |
66 | event mcu0123_secc_error_evnt_trig; | |
67 | event mcu0123_scb_secc_error_evnt_trig; | |
68 | event mcu0123_all_error_evnt_trig; | |
69 | event mcu0_fbd_cmd_a_err_evnt_trig; | |
70 | event mcu0_fbd_cmd_b_err_evnt_trig; | |
71 | event mcu0_fbd_cmd_c_err_evnt_trig; | |
72 | ||
73 | bit mcu_secc0 ; | |
74 | bit mcu_secc1 ; | |
75 | bit mcu_scb_secc0 ; | |
76 | bit mcu_scb_secc1 ; | |
77 | bit mcu_mecc0 ; | |
78 | bit mcu_mecc1 ; | |
79 | bit mcu_scb_mecc0 ; | |
80 | bit mcu_scb_mecc1 ; | |
81 | bit[1:0] mcu_secc_both ; | |
82 | bit[1:0] mcu_mecc_both ; | |
83 | bit[1:0] mcu_scb_secc_both ; | |
84 | bit[1:0] mcu_scb_mecc_both ; | |
85 | bit[3:0] error_bits ; | |
86 | bit[3:0] error_bits_secc ; | |
87 | bit[3:0] error_bits_scb_secc ; | |
88 | bit[3:0] error_bits_mecc ; | |
89 | bit[3:0] error_bits_scb_mecc ; | |
90 | bit[3:0] error_bits_secc_3 ; | |
91 | bit[3:0] error_bits_scb_secc_3 ; | |
92 | bit[3:0] error_bits_secc_4 ; | |
93 | bit[3:0] error_bits_scb_secc_4 ; | |
94 | bit[15:0] error_bits_all ; | |
95 | bit[5:0] a_cmd; | |
96 | ||
97 | ||
98 | integer i; | |
99 | integer start_counter = 0; | |
100 | integer start_counter_secc = 0; | |
101 | integer start_counter_scb_secc = 0; | |
102 | integer start_counter_mecc = 0; | |
103 | integer start_counter_scb_mecc = 0; | |
104 | integer start_counter_secc_3 = 0; | |
105 | integer start_counter_scb_secc_3 = 0; | |
106 | integer start_counter_secc_4 = 0; | |
107 | integer start_counter_scb_secc_4 = 0; | |
108 | integer start_counter_all = 0; | |
109 | integer start_counter_sscbsecc = 0; | |
110 | integer start_counter_smecc = 0; | |
111 | integer start_counter_sscbmecc = 0; | |
112 | integer start_counter_scbsmecc = 0; | |
113 | integer start_counter_scb2smecc = 0; | |
114 | integer start_counter_mscbmecc = 0; | |
115 | integer mcu0_data_vld_1_secc, mcu0_data_vld_2_secc, mcu0_data_vld_3_secc; | |
116 | integer mcu1_data_vld_1_secc, mcu1_data_vld_2_secc, mcu1_data_vld_3_secc; | |
117 | integer mcu2_data_vld_1_secc, mcu2_data_vld_2_secc, mcu2_data_vld_3_secc; | |
118 | integer mcu3_data_vld_1_secc, mcu3_data_vld_2_secc, mcu3_data_vld_3_secc; | |
119 | integer mcu0_data_vld_1_scb_secc, mcu0_data_vld_2_scb_secc, mcu0_data_vld_3_scb_secc; | |
120 | integer mcu1_data_vld_1_scb_secc, mcu1_data_vld_2_scb_secc, mcu1_data_vld_3_scb_secc; | |
121 | integer mcu2_data_vld_1_scb_secc, mcu2_data_vld_2_scb_secc, mcu2_data_vld_3_scb_secc; | |
122 | integer mcu3_data_vld_1_scb_secc, mcu3_data_vld_2_scb_secc, mcu3_data_vld_3_scb_secc; | |
123 | integer mcu0_data_vld_1_mecc, mcu0_data_vld_2_mecc, mcu0_data_vld_3_mecc; | |
124 | integer mcu1_data_vld_1_mecc, mcu1_data_vld_2_mecc, mcu1_data_vld_3_mecc; | |
125 | integer mcu2_data_vld_1_mecc, mcu2_data_vld_2_mecc, mcu2_data_vld_3_mecc; | |
126 | integer mcu3_data_vld_1_mecc, mcu3_data_vld_2_mecc, mcu3_data_vld_3_mecc; | |
127 | integer mcu0_data_vld_1_scb_mecc, mcu0_data_vld_2_scb_mecc, mcu0_data_vld_3_scb_mecc; | |
128 | integer mcu1_data_vld_1_scb_mecc, mcu1_data_vld_2_scb_mecc, mcu1_data_vld_3_scb_mecc; | |
129 | integer mcu2_data_vld_1_scb_mecc, mcu2_data_vld_2_scb_mecc, mcu2_data_vld_3_scb_mecc; | |
130 | integer mcu3_data_vld_1_scb_mecc, mcu3_data_vld_2_scb_mecc, mcu3_data_vld_3_scb_mecc; | |
131 | integer mcu0_data_vld_1_secc_3, mcu0_data_vld_2_secc_3, mcu0_data_vld_3_secc_3; | |
132 | integer mcu1_data_vld_1_secc_3, mcu1_data_vld_2_secc_3, mcu1_data_vld_3_secc_3; | |
133 | integer mcu2_data_vld_1_secc_3, mcu2_data_vld_2_secc_3, mcu2_data_vld_3_secc_3; | |
134 | integer mcu3_data_vld_1_secc_3, mcu3_data_vld_2_secc_3, mcu3_data_vld_3_secc_3; | |
135 | integer mcu0_data_vld_1_scb_secc_3, mcu0_data_vld_2_scb_secc_3, mcu0_data_vld_3_scb_secc_3; | |
136 | integer mcu1_data_vld_1_scb_secc_3, mcu1_data_vld_2_scb_secc_3, mcu1_data_vld_3_scb_secc_3; | |
137 | integer mcu2_data_vld_1_scb_secc_3, mcu2_data_vld_2_scb_secc_3, mcu2_data_vld_3_scb_secc_3; | |
138 | integer mcu3_data_vld_1_scb_secc_3, mcu3_data_vld_2_scb_secc_3, mcu3_data_vld_3_scb_secc_3; | |
139 | integer mcu0_data_vld_1_secc_4, mcu0_data_vld_2_secc_4, mcu0_data_vld_3_secc_4; | |
140 | integer mcu1_data_vld_1_secc_4, mcu1_data_vld_2_secc_4, mcu1_data_vld_3_secc_4; | |
141 | integer mcu2_data_vld_1_secc_4, mcu2_data_vld_2_secc_4, mcu2_data_vld_3_secc_4; | |
142 | integer mcu3_data_vld_1_secc_4, mcu3_data_vld_2_secc_4, mcu3_data_vld_3_secc_4; | |
143 | integer mcu0_data_vld_1_scb_secc_4, mcu0_data_vld_2_scb_secc_4, mcu0_data_vld_3_scb_secc_4; | |
144 | integer mcu1_data_vld_1_scb_secc_4, mcu1_data_vld_2_scb_secc_4, mcu1_data_vld_3_scb_secc_4; | |
145 | integer mcu2_data_vld_1_scb_secc_4, mcu2_data_vld_2_scb_secc_4, mcu2_data_vld_3_scb_secc_4; | |
146 | integer mcu3_data_vld_1_scb_secc_4, mcu3_data_vld_2_scb_secc_4, mcu3_data_vld_3_scb_secc_4; | |
147 | integer mcu0_data_vld_1_all, mcu0_data_vld_2_all, mcu0_data_vld_3_all; | |
148 | integer mcu1_data_vld_1_all, mcu1_data_vld_2_all, mcu1_data_vld_3_all; | |
149 | integer mcu2_data_vld_1_all, mcu2_data_vld_2_all, mcu2_data_vld_3_all; | |
150 | integer mcu3_data_vld_1_all, mcu3_data_vld_2_all, mcu3_data_vld_3_all; | |
151 | integer mcu0_data_vld_1_sscbsecc, mcu0_data_vld_2_sscbsecc, mcu0_data_vld_3_sscbsecc; | |
152 | integer mcu1_data_vld_1_sscbsecc, mcu1_data_vld_2_sscbsecc, mcu1_data_vld_3_sscbsecc; | |
153 | integer mcu2_data_vld_1_sscbsecc, mcu2_data_vld_2_sscbsecc, mcu2_data_vld_3_sscbsecc; | |
154 | integer mcu3_data_vld_1_sscbsecc, mcu3_data_vld_2_sscbsecc, mcu3_data_vld_3_sscbsecc; | |
155 | integer mcu0_data_vld_1_smecc, mcu0_data_vld_2_smecc, mcu0_data_vld_3_smecc; | |
156 | integer mcu1_data_vld_1_smecc, mcu1_data_vld_2_smecc, mcu1_data_vld_3_smecc; | |
157 | integer mcu2_data_vld_1_smecc, mcu2_data_vld_2_smecc, mcu2_data_vld_3_smecc; | |
158 | integer mcu3_data_vld_1_smecc, mcu3_data_vld_2_smecc, mcu3_data_vld_3_smecc; | |
159 | integer mcu0_data_vld_1_sscbmecc, mcu0_data_vld_2_sscbmecc, mcu0_data_vld_3_sscbmecc; | |
160 | integer mcu1_data_vld_1_sscbmecc, mcu1_data_vld_2_sscbmecc, mcu1_data_vld_3_sscbmecc; | |
161 | integer mcu2_data_vld_1_sscbmecc, mcu2_data_vld_2_sscbmecc, mcu2_data_vld_3_sscbmecc; | |
162 | integer mcu3_data_vld_1_sscbmecc, mcu3_data_vld_2_sscbmecc, mcu3_data_vld_3_sscbmecc; | |
163 | integer mcu0_data_vld_1_scbsmecc, mcu0_data_vld_2_scbsmecc, mcu0_data_vld_3_scbsmecc; | |
164 | integer mcu1_data_vld_1_scbsmecc, mcu1_data_vld_2_scbsmecc, mcu1_data_vld_3_scbsmecc; | |
165 | integer mcu2_data_vld_1_scbsmecc, mcu2_data_vld_2_scbsmecc, mcu2_data_vld_3_scbsmecc; | |
166 | integer mcu3_data_vld_1_scbsmecc, mcu3_data_vld_2_scbsmecc, mcu3_data_vld_3_scbsmecc; | |
167 | integer mcu0_data_vld_1_scb2smecc, mcu0_data_vld_2_scb2smecc, mcu0_data_vld_3_scb2smecc; | |
168 | integer mcu1_data_vld_1_scb2smecc, mcu1_data_vld_2_scb2smecc, mcu1_data_vld_3_scb2smecc; | |
169 | integer mcu2_data_vld_1_scb2smecc, mcu2_data_vld_2_scb2smecc, mcu2_data_vld_3_scb2smecc; | |
170 | integer mcu3_data_vld_1_scb2smecc, mcu3_data_vld_2_scb2smecc, mcu3_data_vld_3_scb2smecc; | |
171 | integer mcu0_data_vld_1_mscbmecc, mcu0_data_vld_2_mscbmecc, mcu0_data_vld_3_mscbmecc; | |
172 | integer mcu1_data_vld_1_mscbmecc, mcu1_data_vld_2_mscbmecc, mcu1_data_vld_3_mscbmecc; | |
173 | integer mcu2_data_vld_1_mscbmecc, mcu2_data_vld_2_mscbmecc, mcu2_data_vld_3_mscbmecc; | |
174 | integer mcu3_data_vld_1_mscbmecc, mcu3_data_vld_2_mscbmecc, mcu3_data_vld_3_mscbmecc; | |
175 | ||
176 | integer mcu0_mcu1_secc_scbs_counter = 0; | |
177 | integer mcu0_mcu1_secc_mecc_counter = 0; | |
178 | integer mcu0_mcu1_secc_scbm_counter = 0; | |
179 | integer mcu0_mcu1_scb_mecc1_counter = 0; | |
180 | integer mcu0_mcu1_scb_scbm_counter = 0; | |
181 | integer mcu0_mcu1_mecc_scbm_counter = 0; | |
182 | integer start_count = 0; | |
183 | integer error_count = 0; | |
184 | integer error_count_secc = 0; | |
185 | integer error_count_scb_secc = 0; | |
186 | integer error_count_mecc = 0; | |
187 | integer error_count_scb_mecc = 0; | |
188 | integer error_count_secc_3 = 0; | |
189 | integer error_count_scb_secc_3 = 0; | |
190 | integer error_count_secc_4 = 0; | |
191 | integer error_count_scb_secc_4 = 0; | |
192 | integer error_count_all = 0; | |
193 | ||
194 | integer mcu0_mcu1_secc_counter = 0; | |
195 | integer mcu0_mcu1_scb_secc_counter = 0; | |
196 | integer mcu0_mcu1_mecc_counter = 0; | |
197 | integer mcu0_mcu1_scb_mecc_counter = 0; | |
198 | integer mcu0_mcu1_mcu2_secc_counter = 0; | |
199 | integer mcu0_mcu1_mcu2_scb_secc_counter = 0; | |
200 | integer mcu0_mcu1_mcu2_mcu3_secc_counter = 0; | |
201 | integer mcu0_mcu1_mcu2_mcu3_scb_secc_counter = 0; | |
202 | integer mcu0_mcu1_mcu2_mcu3_all_counter = 0; | |
203 | ||
204 | ||
205 | // ----------- start of coverage object 1 ---------------- | |
206 | // this coverage group samples on dram clock | |
207 | coverage_group dram_coverage_group { | |
208 | ||
209 | const_sample_reference = 1; // ref. to sample vars. is constant | |
210 | sample_event = @(posedge dram_coverage_ifc_dram_clk.dram_gclk); | |
211 | //cov_weight = 0; // default, unless diag_done is true, | |
212 | // i.e. diag. passes | |
213 | #ifndef MCU_INTF_COV | |
214 | ||
215 | . foreach $c (0) { | |
216 | sample ${prefix}mcu_que_fsm_sample_bind_Ch${c}.\$que_pos { | |
217 | #include "mcusat_cntrlfsm_sample.vrh" | |
218 | } | |
219 | sample ${prefix}mcu_que_pick_wr_first_sample_bind_Ch${c}.\$wr_pick { | |
220 | #include "mcusat_wr_q_full_starv_cntr_sample.vrh" | |
221 | } | |
222 | sample ${prefix}mcu_wr_data_rd_mem_sample_bind_Ch${c}_l2b0.\$en_n_addr { | |
223 | #include "mcusat_wr_data_rd_mem_sample.vrh" | |
224 | } | |
225 | sample ${prefix}mcu_wr_data_rd_mem_sample_bind_Ch${c}_l2b1.\$en_n_addr { | |
226 | #include "mcusat_wr_data_rd_mem_sample.vrh" | |
227 | } | |
228 | ||
229 | ||
230 | // #include "dram_ras_cas_pend_cnt_sample.vrh" | |
231 | // } | |
232 | sample ${prefix}mcu_ras_picked_sample_bind_Ch${c}.\$ras_picked{ | |
233 | #include "mcusat_ras_picked_sample.vrh" | |
234 | } | |
235 | ||
236 | // #include "dram_cas_picked_sample.vrh" | |
237 | // } | |
238 | sample ${prefix}mcu_rd_wr_hit_sample_bind_Ch${c}.\$rd_wr_hit{ | |
239 | #include "mcusat_rd_wr_hit_sample.vrh" | |
240 | } | |
241 | sample ${prefix}mcu_scb_req_same_bank_sample_bind_Ch${c}.\$scb_req{ | |
242 | #include "mcusat_scb_req_same_bank_sample.vrh" | |
243 | } | |
244 | sample ${prefix}mcu_refresh_all_clr_mon_state_sample_bind_Ch${c}.\$fsm_state { | |
245 | #include "mcusat_refrsh_issued_all_cas_clr_sample.vrh" | |
246 | } | |
247 | ||
248 | // #include "mcusat_cas_que_sample.vrh" | |
249 | // } | |
250 | sample ${prefix}mcu_rd_wr_scrb_schmoo_sample_bind_Ch${c}_l2b0.\$rd_wr_scrb_vld { | |
251 | #include "mcusat_rd_wr_schmoo_sample.vrh" | |
252 | } | |
253 | sample ${prefix}mcu_rd_wr_scrb_schmoo_sample_bind_Ch${c}_l2b1.\$rd_wr_scrb_vld { | |
254 | #include "mcusat_rd_wr_schmoo_sample.vrh" | |
255 | } | |
256 | ||
257 | ||
258 | // #include "dram_reg_toggle_sample.vrh" | |
259 | // } | |
260 | sample ${prefix}mcu_perf_cntr_sample_bind_Ch${c}.\$perf { | |
261 | #include "mcusat_perf_cntr_sample.vrh" | |
262 | } | |
263 | sample ${prefix}mcu_reg_ack_nack_sample_bind_Ch${c}.\$ack_nack { | |
264 | #include "mcusat_reg_ack_nack_sample.vrh" | |
265 | } | |
266 | /*mb156858, evaluation is commented out in dram_mon | |
267 | sample ${prefix}dram_rank_stack_addr_param_rd_hi_sample_bind_Ch${c}_l2b0.\$addr_etc_info_rd_hi { | |
268 | #include "mcusat_rank_stack_addr_param_rd_hi_sample.vrh" | |
269 | } | |
270 | sample ${prefix}dram_rank_stack_addr_param_wr_hi_sample_bind_Ch${c}_l2b0.\$addr_etc_info_wr_hi { | |
271 | #include "mcusat_rank_stack_addr_param_wr_hi_sample.vrh" | |
272 | } | |
273 | sample ${prefix}dram_rank_stack_addr_param_rd_lo_sample_bind_Ch${c}_l2b0.\$addr_etc_info_rd_lo { | |
274 | #include "mcusat_rank_stack_addr_param_rd_lo_sample.vrh" | |
275 | } | |
276 | sample ${prefix}dram_rank_stack_addr_param_wr_lo_sample_bind_Ch${c}_l2b0.\$addr_etc_info_wr_lo { | |
277 | #include "mcusat_rank_stack_addr_param_wr_lo_sample.vrh" | |
278 | } | |
279 | ||
280 | sample ${prefix}dram_rank_stack_addr_param_rd_hi_sample_bind_Ch${c}_l2b1.\$addr_etc_info_rd_hi { | |
281 | #include "mcusat_rank_stack_addr_param_rd_hi_sample.vrh" | |
282 | } | |
283 | sample ${prefix}dram_rank_stack_addr_param_wr_hi_sample_bind_Ch${c}_l2b1.\$addr_etc_info_wr_hi { | |
284 | #include "mcusat_rank_stack_addr_param_wr_hi_sample.vrh" | |
285 | } | |
286 | sample ${prefix}dram_rank_stack_addr_param_rd_lo_sample_bind_Ch${c}_l2b1.\$addr_etc_info_rd_lo { | |
287 | #include "mcusat_rank_stack_addr_param_rd_lo_sample.vrh" | |
288 | } | |
289 | sample ${prefix}dram_rank_stack_addr_param_wr_lo_sample_bind_Ch${c}_l2b1.\$addr_etc_info_wr_lo { | |
290 | #include "mcusat_rank_stack_addr_param_wr_lo_sample.vrh" | |
291 | } | |
292 | ||
293 | sample ${prefix}dram_dp_pioson_l2_data_sample_bind_Ch${c}.\$dp_pioson_l2_data { | |
294 | #include "mcusat_dp_pioson_l2_data_sample.vrh" | |
295 | } | |
296 | */ | |
297 | ||
298 | // #include "dram_line_cov.vrh" | |
299 | // } | |
300 | . for ( $i = 0; $i < 8; $i++ ) { | |
301 | sample ${prefix}mcu_rd_q_cntr${i}_sample_bind_Ch${c}_l2b0.\$cntr { | |
302 | #include "mcusat_q_cntr_sample.vrh" | |
303 | } | |
304 | sample ${prefix}mcu_rd_q_cntr${i}_sample_bind_Ch${c}_l2b1.\$cntr { | |
305 | #include "mcusat_q_cntr_sample.vrh" | |
306 | } | |
307 | sample ${prefix}mcu_wr_q_cntr${i}_sample_bind_Ch${c}_l2b0.\$cntr { | |
308 | #include "mcusat_q_cntr_sample.vrh" | |
309 | } | |
310 | sample ${prefix}mcu_wr_q_cntr${i}_sample_bind_Ch${c}_l2b1.\$cntr { | |
311 | #include "mcusat_q_cntr_sample.vrh" | |
312 | } | |
313 | sample ${prefix}mcu_rd_req_ack_${i}_sample_bind_Ch${c}_l2b0.\$cntr { | |
314 | #include "mcusat_rd_req_ack_cntr_sample.vrh" | |
315 | } | |
316 | sample ${prefix}mcu_rd_req_ack_${i}_sample_bind_Ch${c}_l2b1.\$cntr { | |
317 | #include "mcusat_rd_req_ack_cntr_sample.vrh" | |
318 | } | |
319 | .} | |
320 | sample ${prefix}mcu_wr_req_ack_sample_bind_Ch${c}_l2b0.\$cntr { | |
321 | #include "mcusat_wr_req_ack_cntr_sample.vrh" | |
322 | } | |
323 | sample ${prefix}mcu_wr_req_ack_sample_bind_Ch${c}_l2b1.\$cntr { | |
324 | #include "mcusat_wr_req_ack_cntr_sample.vrh" | |
325 | } | |
326 | sample ${prefix}mcu_raw_hazard_sample_bind_Ch${c}.\$hazard { | |
327 | #include "mcusat_raw_hazard_sample.vrh" | |
328 | } | |
329 | sample ${prefix}mcu_refresh_sample_bind_Ch${c}.\$refresh { | |
330 | #include "mcusat_refresh_sample.vrh" | |
331 | } | |
332 | sample ${prefix}mcu_single_channel_sample_bind_Ch${c}.\$single_ch { | |
333 | #include "mcusat_single_channel_sample.vrh" | |
334 | } | |
335 | sample ${prefix}mcu_fbd_fast_reset_sample_bind_Ch${c}.\$fast_reset { | |
336 | #include "mcusat_fbd_fast_reset_sample.vrh" | |
337 | } | |
338 | sample ${prefix}mcu_fbd_full_reset_sample_bind_Ch${c}.\$fast_reset { | |
339 | #include "mcusat_fbd_full_reset_sample.vrh" | |
340 | } | |
341 | sample ${prefix}mcu_fbd_l0s_state_sample_bind_Ch${c}.\$l0sstate { | |
342 | #include "mcusat_fbd_l0s_state_sample.vrh" | |
343 | } | |
344 | sample ${prefix}mcu_failover_sample_bind_Ch${c}.\$failover { | |
345 | #include "mcusat_ch${c}_failover_sample.vrh" | |
346 | } | |
347 | sample ${prefix}mcu_fbd0_sb_failover_sample_bind_Ch${c}.\$failover { | |
348 | #include "mcusat_sb_failover_sample.vrh" | |
349 | } | |
350 | sample ${prefix}mcu_fbd1_sb_failover_sample_bind_Ch${c}.\$failover { | |
351 | #include "mcusat_sb_failover_sample.vrh" | |
352 | } | |
353 | sample ${prefix}mcu_fbd0_nb_failover_sample_bind_Ch${c}.\$failover { | |
354 | #include "mcusat_nb_failover_sample.vrh" | |
355 | } | |
356 | sample ${prefix}mcu_fbd1_nb_failover_sample_bind_Ch${c}.\$failover { | |
357 | #include "mcusat_nb_failover_sample.vrh" | |
358 | } | |
359 | sample ${prefix}mcu_wr_mem_poison_sample_bind_Ch${c}.\$poison { | |
360 | state s_wr_8221 (1) if (({dram_coverage_ifc_dram_clk.dram_Ch${c}_wecc0,dram_coverage_ifc_dram_clk.dram_Ch${c}_wecc1,dram_coverage_ifc_dram_clk.dram_Ch${c}_wecc2,dram_coverage_ifc_dram_clk.dram_Ch${c}_wecc3} ^ dram_coverage_ifc_dram_clk.dram_Ch${c}_err_inj_ecc) == 16'h1228); | |
361 | } | |
362 | /*mb156858, evaluation is commented out in dram_mon | |
363 | . for ( $ch = 0; $ch < 4; $ch++ ) { | |
364 | . for ( $i = 0; $i < 8; $i++ ) { | |
365 | sample ${prefix}dram_cs${ch}_bank_req_cntr_${i}_sample_bind_Ch${c}.\$cntr { | |
366 | #include "mcusat_cs_bank_req_cntr_sample.vrh" | |
367 | } | |
368 | .} | |
369 | .} | |
370 | */ | |
371 | #endif | |
372 | ||
373 | // MCU Internal-subset for FC | |
374 | sample ${prefix}mcu_rd_que_status_sample_bind_Ch${c}_l2b0.\$rd_que_status { | |
375 | #include "mcusat_rd_que_sample.vrh" | |
376 | } | |
377 | sample ${prefix}mcu_rd_que_status_sample_bind_Ch${c}_l2b1.\$rd_que_status { | |
378 | #include "mcusat_rd_que_sample.vrh" | |
379 | } | |
380 | ||
381 | sample ${prefix}mcu_wr_que_status_sample_bind_Ch${c}_l2b0.\$wr_que_status { | |
382 | #include "mcusat_wr_que_sample.vrh" | |
383 | } | |
384 | sample ${prefix}mcu_wr_que_status_sample_bind_Ch${c}_l2b1.\$wr_que_status { | |
385 | #include "mcusat_wr_que_sample.vrh" | |
386 | } | |
387 | ||
388 | // added to FC following 3 for Mode 10/25/05 | |
389 | sample ${prefix}mcu_fbd_dimm_cmd_a_sample_bind_Ch${c}.\$frame { | |
390 | #include "mcusat_fbd_dimm_sample.vrh" | |
391 | } | |
392 | sample ${prefix}mcu_fbd_dimm_cmd_b_sample_bind_Ch${c}.\$frame { | |
393 | #include "mcusat_fbd_dimm_sample.vrh" | |
394 | } | |
395 | sample ${prefix}mcu_fbd_dimm_cmd_c_sample_bind_Ch${c}.\$frame { | |
396 | #include "mcusat_fbd_dimm_sample.vrh" | |
397 | } | |
398 | ||
399 | ||
400 | . } # for $c | |
401 | ||
402 | ||
403 | // #ifndef MCU_INTF_COV - use auto refresh signal (drif_refresh_req_picked) | |
404 | ||
405 | // #include "mcusat_pt_refresh_blk_bank_sample.vrh" | |
406 | // } | |
407 | ||
408 | // #include "mcusat_pt_refresh_blk_bank_sample.vrh" | |
409 | // } | |
410 | ||
411 | // #include "mcusat_pt_refresh_blk_bank_sample.vrh" | |
412 | // } | |
413 | ||
414 | // #include "mcusat_pt_refresh_blk_bank_sample.vrh" | |
415 | // } | |
416 | // #endif | |
417 | ||
418 | } // coverage_group | |
419 | ||
420 | // ----------- start of coverage object 2 ---------------- | |
421 | // this coverage group samples on core clock | |
422 | coverage_group dram_coverage_group_l2 { | |
423 | ||
424 | const_sample_reference = 1; // ref. to sample vars. is constant | |
425 | sample_event = @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
426 | //cov_weight = 0; // default, unless diag_done is true, | |
427 | // i.e. diag. passes | |
428 | ||
429 | sample dram_coverage_ifc_core_clk.dram_Ch0_dbg1_crc21 { | |
430 | . &toggle( 1 ); | |
431 | cov_weight = 1; | |
432 | } | |
433 | ||
434 | sample dram_coverage_ifc_core_clk.dram_Ch0_dbg1_err_event { | |
435 | . &toggle( 1 ); | |
436 | cov_weight = 1; | |
437 | } | |
438 | ||
439 | sample dram_coverage_ifc_core_clk.mcu0_drif_refresh_req_picked { | |
440 | . &toggle( 1 ); | |
441 | cov_weight = 1; | |
442 | } | |
443 | ||
444 | sample dram_coverage_ifc_core_clk.mcu1_drif_refresh_req_picked { | |
445 | . &toggle( 1 ); | |
446 | cov_weight = 1; | |
447 | } | |
448 | ||
449 | sample dram_coverage_ifc_core_clk.mcu2_drif_refresh_req_picked { | |
450 | . &toggle( 1 ); | |
451 | cov_weight = 1; | |
452 | } | |
453 | ||
454 | sample dram_coverage_ifc_core_clk.mcu3_drif_refresh_req_picked { | |
455 | . &toggle( 1 ); | |
456 | cov_weight = 1; | |
457 | } | |
458 | ||
459 | sample dram_coverage_ifc_core_clk.l2t0_mcu_addr_38to7[31:2] { | |
460 | . &toggle( 30 ); | |
461 | cov_weight = 1; | |
462 | } | |
463 | ||
464 | sample dram_coverage_ifc_core_clk.l2t1_mcu_addr_38to7[31:2] { | |
465 | . &toggle( 30 ); | |
466 | cov_weight = 1; | |
467 | } | |
468 | ||
469 | sample dram_coverage_ifc_core_clk.l2t0_mcu_rd_req_id[2:0] { | |
470 | state s_1 (3'b000); | |
471 | state s_2 (3'b001); | |
472 | state s_3 (3'b010); | |
473 | state s_4 (3'b011); | |
474 | state s_5 (3'b100); | |
475 | state s_6 (3'b101); | |
476 | state s_7 (3'b110); | |
477 | state s_8 (3'b111); | |
478 | } | |
479 | ||
480 | sample dram_coverage_ifc_core_clk.l2t1_mcu_rd_req_id[2:0] { | |
481 | state s_1 (3'b000); | |
482 | state s_2 (3'b001); | |
483 | state s_3 (3'b010); | |
484 | state s_4 (3'b011); | |
485 | state s_5 (3'b100); | |
486 | state s_6 (3'b101); | |
487 | state s_7 (3'b110); | |
488 | state s_8 (3'b111); | |
489 | } | |
490 | ||
491 | sample dram_coverage_ifc_core_clk.mcu_l2t0_rd_req_id_r0[2:0] { | |
492 | state s_1 (3'b000); | |
493 | state s_2 (3'b001); | |
494 | state s_3 (3'b010); | |
495 | state s_4 (3'b011); | |
496 | state s_5 (3'b100); | |
497 | state s_6 (3'b101); | |
498 | state s_7 (3'b110); | |
499 | state s_8 (3'b111); | |
500 | } | |
501 | ||
502 | sample dram_coverage_ifc_core_clk.mcu_l2t1_rd_req_id_r0[2:0] { | |
503 | state s_1 (3'b000); | |
504 | state s_2 (3'b001); | |
505 | state s_3 (3'b010); | |
506 | state s_4 (3'b011); | |
507 | state s_5 (3'b100); | |
508 | state s_6 (3'b101); | |
509 | state s_7 (3'b110); | |
510 | state s_8 (3'b111); | |
511 | } | |
512 | ||
513 | sample l2_mcu_intf_rd_bank0_rd_bank1 (dram_coverage_ifc_core_clk.mcu_l2t0_rd_ack) | |
514 | { | |
515 | state s_RD_BANK0_RD_BANK1 (1) if (dram_coverage_ifc_core_clk.mcu_l2t0_rd_ack === 1 && | |
516 | dram_coverage_ifc_core_clk.mcu_l2t1_rd_ack === 1); | |
517 | } | |
518 | ||
519 | sample l2_mcu_intf_rd_bank0_wr_bank1 (dram_coverage_ifc_core_clk.mcu_l2t0_rd_ack) | |
520 | { | |
521 | state s_RD_BANK0_WR_BANK1 (1) if (dram_coverage_ifc_core_clk.mcu_l2t0_rd_ack === 1 && | |
522 | dram_coverage_ifc_core_clk.mcu_l2t1_wr_ack === 1); | |
523 | } | |
524 | ||
525 | sample l2_mcu_intf_wr_bank0_rd_bank1 (dram_coverage_ifc_core_clk.mcu_l2t0_wr_ack) | |
526 | { | |
527 | state s_WR_BANK0_RD_BANK1 (1) if (dram_coverage_ifc_core_clk.mcu_l2t0_wr_ack === 1 && | |
528 | dram_coverage_ifc_core_clk.mcu_l2t1_rd_ack === 1); | |
529 | } | |
530 | ||
531 | sample l2_mcu_intf_wr_bank0_wr_bank1 (dram_coverage_ifc_core_clk.mcu_l2t0_wr_ack) | |
532 | { | |
533 | state s_WR_BANK0_WR_BANK1 (1) if (dram_coverage_ifc_core_clk.mcu_l2t0_wr_ack === 1 && | |
534 | dram_coverage_ifc_core_clk.mcu_l2t1_wr_ack === 1); | |
535 | } | |
536 | ||
537 | sample l2_mcu_intf_rd_bank0_req_rd_bank1 (dram_coverage_ifc_core_clk.l2t0_mcu_rd_req) | |
538 | { | |
539 | state s_RD_BANK0_REQ_RD_BANK1 (1) if (dram_coverage_ifc_core_clk.l2t0_mcu_rd_req === 1 && | |
540 | dram_coverage_ifc_core_clk.l2t1_mcu_rd_req === 1); | |
541 | } | |
542 | ||
543 | sample l2_mcu_intf_wr_bank0_req_wr_bank1 (dram_coverage_ifc_core_clk.l2t0_mcu_wr_req) | |
544 | { | |
545 | state s_WR_BANK0_REQ_WR_BANK1 (1) if (dram_coverage_ifc_core_clk.l2t0_mcu_wr_req === 1 && | |
546 | dram_coverage_ifc_core_clk.l2t1_mcu_wr_req === 1); | |
547 | } | |
548 | ||
549 | sample l2_mcu_intf_rd_bank0_req_wr_bank1 (dram_coverage_ifc_core_clk.l2t0_mcu_rd_req) | |
550 | { | |
551 | state s_RD_BANK0_REQ_WR_BANK1 (1) if (dram_coverage_ifc_core_clk.l2t0_mcu_rd_req === 1 && | |
552 | dram_coverage_ifc_core_clk.l2t1_mcu_wr_req === 1); | |
553 | } | |
554 | ||
555 | sample l2_mcu_intf_wr_bank0_req_rd_bank1 (dram_coverage_ifc_core_clk.l2t0_mcu_wr_req) | |
556 | { | |
557 | state s_WR_BANK0_REQ_RD_BANK1 (1) if (dram_coverage_ifc_core_clk.l2t0_mcu_wr_req === 1 && | |
558 | dram_coverage_ifc_core_clk.l2t1_mcu_rd_req === 1); | |
559 | } | |
560 | ||
561 | sample l2_mcu_intf_bank0_data_bank1 (dram_coverage_ifc_core_clk.l2b0_mcu_data_vld_r5) | |
562 | { | |
563 | state s_BANK0_DATA_BANK1 (1) if (dram_coverage_ifc_core_clk.l2b0_mcu_data_vld_r5 === 1 && | |
564 | dram_coverage_ifc_core_clk.l2b1_mcu_data_vld_r5 === 1); | |
565 | } | |
566 | ||
567 | ||
568 | . foreach $c (0) { | |
569 | ||
570 | ||
571 | // #include "mcusat_rd_wr_l2if_sample.vrh" | |
572 | // } | |
573 | ||
574 | // #include "dram_rd_wr_l2if_sample.vrh" | |
575 | // } | |
576 | sample ${prefix}l2_mcu_intf_wr_data_mem_sample_bind_Ch${c}_l2b0.\$en_n_addr { | |
577 | #include "mcusat_wr_data_mem_sample.vrh" | |
578 | } | |
579 | sample ${prefix}l2_mcu_intf_wr_data_mem_sample_bind_Ch${c}_l2b1.\$en_n_addr { | |
580 | #include "mcusat_wr_data_mem_sample.vrh" | |
581 | } | |
582 | /*mb156858, evaluation is commented out in dram_mon | |
583 | sample ${prefix}dram_l2if_data_ret_fifo_en_sample_bind_Ch${c}.\$fifo_en { | |
584 | #include "mcusat_l2if_data_ret_fifo_sample.vrh" | |
585 | } | |
586 | */ | |
587 | sample ${prefix}l2_mcu_intf_rd_sync_schmoo_sample_bind_Ch${c}_l2b0.\$rd_sync { | |
588 | #include "mcusat_rd_sync_schmoo_sample.vrh" | |
589 | } | |
590 | sample ${prefix}l2_mcu_intf_rd_sync_schmoo_sample_bind_Ch${c}_l2b1.\$rd_sync { | |
591 | #include "mcusat_rd_sync_schmoo_sample.vrh" | |
592 | } | |
593 | sample ${prefix}l2_mcu_intf_wr_sync_schmoo_sample_bind_Ch${c}_l2b0.\$wr_sync { | |
594 | #include "mcusat_wr_sync_schmoo_sample.vrh" | |
595 | } | |
596 | sample ${prefix}l2_mcu_intf_wr_sync_schmoo_sample_bind_Ch${c}_l2b1.\$wr_sync { | |
597 | #include "mcusat_wr_sync_schmoo_sample.vrh" | |
598 | } | |
599 | sample ${prefix}l2_mcu_intf_err_sample_bind_Ch${c}_l2b0.\$secc_pa_mecc_scb_secc_mecc { | |
600 | #include "mcusat_err_l2if_sample.vrh" | |
601 | } | |
602 | sample ${prefix}l2_mcu_intf_err_sample_bind_Ch${c}_l2b1.\$secc_pa_mecc_scb_secc_mecc { | |
603 | #include "mcusat_err_l2if_sample.vrh" | |
604 | } | |
605 | /*mb156858, evaluation is commented out in dram_mon | |
606 | sample ${prefix}dram_rd_q_full_n_req_sample_bind_Ch${c}.\$fsm_state { | |
607 | #include "mcusat_rd_q_full_n_req_sample.vrh" | |
608 | } | |
609 | */ | |
610 | sample ${prefix}l2_mcu_intf_wr_q_full_n_req_sample_bind_Ch${c}_l2b0.\$fsm_state { | |
611 | #include "mcusat_wr_q_full_n_req_sample.vrh" | |
612 | } | |
613 | sample ${prefix}l2_mcu_intf_wr_q_full_n_req_sample_bind_Ch${c}_l2b1.\$fsm_state { | |
614 | #include "mcusat_wr_q_full_n_req_sample.vrh" | |
615 | } | |
616 | sample ${prefix}l2_mcu_intf_mem_poison_sample_bind_Ch${c}.\$ecc { | |
617 | #include "mcusat_mem_poison_sample.vrh" | |
618 | } | |
619 | sample ${prefix}mcu_err_sts_sample_bind_Ch${c}_l2b0.\$err_en_n_sts { | |
620 | #include "mcusat_err_sts_sample.vrh" | |
621 | } | |
622 | sample ${prefix}mcu_err_sts_sample_bind_Ch${c}_l2b1.\$err_en_n_sts { | |
623 | #include "mcusat_err_sts_sample.vrh" | |
624 | } | |
625 | /*mb156858, evaluation is commented out in dram_mon | |
626 | sample ${prefix}dram_err_intr_ucb_trig1_sample_bind_Ch${c}.\$err_intr_ucb_trig1 { | |
627 | #include "mcusat_err_intr_ucb_trig1_sample.vrh" | |
628 | } | |
629 | */ | |
630 | /* move from internal to interface */ | |
631 | sample ${prefix}mcu_fbd_cmd_a_sample_bind_Ch${c}.\$cmd { | |
632 | #include "mcusat_ch${c}_fbd_cmd_a_sample.vrh" | |
633 | } | |
634 | sample ${prefix}mcu_fbd_cmd_b_sample_bind_Ch${c}.\$cmd { | |
635 | #include "mcusat_fbd_cmd_b_sample.vrh" | |
636 | } | |
637 | sample ${prefix}mcu_fbd_cmd_c_sample_bind_Ch${c}.\$cmd { | |
638 | #include "mcusat_ch${c}_fbd_cmd_c_sample.vrh" | |
639 | } | |
640 | sample ${prefix}mcu_fbd_nb_ts0_sample_bind_Ch${c}.\$frame { | |
641 | #include "mcusat_fbd_nb_frame_sample.vrh" | |
642 | } | |
643 | sample ${prefix}mcu_fbd_nb_stspar_sample_bind_Ch${c}.\$frame { | |
644 | #include "mcusat_fbd_nb_frame1_sample.vrh" | |
645 | } | |
646 | sample ${prefix}mcu_fbd_nb_idle_sample_bind_Ch${c}.\$frame { | |
647 | #include "mcusat_fbd_nb_frame_sample.vrh" | |
648 | } | |
649 | sample ${prefix}mcu_fbd_nb_alrt_sample_bind_Ch${c}.\$frame { | |
650 | #include "mcusat_fbd_nb_frame_sample.vrh" | |
651 | } | |
652 | sample ${prefix}mcu_fbd_nb_alrt_assrt_sample_bind_Ch${c}.\$frame { | |
653 | #include "mcusat_fbd_nb_frame1_sample.vrh" | |
654 | } | |
655 | sample ${prefix}mcu_fbd_nb_nbde_sample_bind_Ch${c}.\$frame { | |
656 | #include "mcusat_fbd_nb_frame1_sample.vrh" | |
657 | } | |
658 | sample ${prefix}mcu_fbd_sb_frame_sample_bind_Ch${c}.\$frame { | |
659 | #include "mcusat_ch${c}_fbd_sb_frame_sample.vrh" | |
660 | } | |
661 | . } # for $c | |
662 | } // coverage_group 2 | |
663 | ||
664 | ||
665 | ||
666 | // ----------- start of coverage object 3(jbus) ---------------- | |
667 | // this coverage group samples on jbus clock | |
668 | coverage_group dram_coverage_group_jbus { | |
669 | ||
670 | const_sample_reference = 1; // ref. to sample vars. is constant | |
671 | sample_event = @(posedge dram_coverage_ifc_jbus_clk.jbus_gclk); | |
672 | //cov_weight = 0; // default, unless diag_done is true, | |
673 | // i.e. diag. passes | |
674 | ||
675 | . foreach $c (0) { | |
676 | // moved dbg objs to jbus grp from dram_coverage grp -ncr(10/20/05) | |
677 | sample ${prefix}mcu_dbg_err_sample_bind_Ch${c}.\$dbgerr { | |
678 | #include "mcusat_dbg_err_sample.vrh" | |
679 | } | |
680 | sample ${prefix}mcu_dbg_rd_req_sample_bind_Ch${c}.\$dbgrd { | |
681 | #include "mcusat_dbg_rd_req_sample.vrh" | |
682 | } | |
683 | sample ${prefix}mcu_dbg_wr_req_sample_bind_Ch${c}.\$dbgwr { | |
684 | #include "mcusat_dbg_wr_req_sample.vrh" | |
685 | } | |
686 | . } | |
687 | sample ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch0.\$ucb_etc { | |
688 | #include "mcusat_ucb_req_pend_ack_int_busy_sample.vrh" | |
689 | } | |
690 | /*sample ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch1.\$ucb_etc { | |
691 | #include "mcusat_ucb_req_pend_ack_int_busy_sample.vrh" | |
692 | } | |
693 | ||
694 | sample ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch2.\$ucb_etc { | |
695 | #include "mcusat_ucb_req_pend_ack_int_busy_sample.vrh" | |
696 | } | |
697 | sample ${prefix}mcu_ucb_req_pend_ack_int_busy_sample_bind_Ch3.\$ucb_etc { | |
698 | #include "mcusat_ucb_req_pend_ack_int_busy_sample.vrh" | |
699 | }*/ | |
700 | sample ${prefix}mcu_ncu_intf_sample_bind_Ch0.\$intr { | |
701 | #include "mcusat_mcu_ncu_intr_sample.vrh" | |
702 | } | |
703 | /* sample ${prefix}mcu_ncu_intf_sample_bind_Ch1.\$intr { | |
704 | #include "mcusat_mcu_ncu_intr_sample.vrh" | |
705 | } | |
706 | sample ${prefix}mcu_ncu_intf_sample_bind_Ch2.\$intr { | |
707 | #include "mcusat_mcu_ncu_intr_sample.vrh" | |
708 | } | |
709 | sample ${prefix}mcu_ncu_intf_sample_bind_Ch3.\$intr { | |
710 | #include "mcusat_mcu_ncu_intr_sample.vrh" | |
711 | }*/ | |
712 | ||
713 | } // coverage_group 3 | |
714 | ||
715 | // coverage_group mcu_l2t_error_l2t1_coverage_group | |
716 | // { | |
717 | // sample_event = sync (ANY, mcu01_secc_evnt_trig ); | |
718 | // #include "mcu_fc_err_send_l2t0.vrh" | |
719 | ||
720 | // } // mcu_l2t_error_l2t1_coverage_group | |
721 | ||
722 | coverage_group mcu_l2t_error_l2t0_coverage_group | |
723 | { | |
724 | const_sample_reference = 1; // ref. to sample vars. is constant | |
725 | sample_event = sync (ANY, mcu01_secc_error_evnt_trig, mcu01_scb_secc_error_evnt_trig, mcu01_mecc_error_evnt_trig, mcu01_scb_mecc_error_evnt_trig, mcu01_secc_scbs_error_evnt_trig, mcu01_secc_mecc_error_evnt_trig, mcu01_secc_scbm_error_evnt_trig, mcu01_scb_mecc1_error_evnt_trig, mcu01_scb_scbm_error_evnt_trig, mcu01_mecc_scbm_error_evnt_trig, mcu012_scb_secc_error_evnt_trig, mcu012_secc_error_evnt_trig, mcu0123_secc_error_evnt_trig, mcu0123_scb_secc_error_evnt_trig, mcu0123_all_error_evnt_trig ); | |
726 | #include "mcu_fc_err_send_l2t0_window.vrh" | |
727 | ||
728 | } // mcu_l2t_error_l2t0_coverage_group | |
729 | ||
730 | // `ifdef IDT_AMB | |
731 | // coverage_group mcu_fbd_cmda_sb_err_coverage_group | |
732 | // { | |
733 | // sample_event = sync (ANY, mcu0_fbd_cmd_a_err_evnt_trig); //, mcu0_fbd_cmd_b_err_evnt_trig, mcu0_fbd_cmd_c_err_evnt_trig); | |
734 | // #include "mcusat_fbd_cmda_sb_err_sample.vrh" | |
735 | // } //mcu_fbd_cmda_sb_err_coverage_group | |
736 | // `endif | |
737 | ||
738 | task new(); | |
739 | task set_cov_cond_bits (); | |
740 | ||
741 | } | |
742 | ||
743 | ///////////////////////////////////////////////////////////////// | |
744 | // Class creation | |
745 | ///////////////////////////////////////////////////////////////// | |
746 | ||
747 | task ${prefix}dram_coverage::new() { | |
748 | ||
749 | ||
750 | bit coverage_on; | |
751 | integer j; | |
752 | ||
753 | if (get_plus_arg (CHECK, "dram_coverage") || | |
754 | get_plus_arg (CHECK, "coverage_on")) { | |
755 | coverage_on = 1; | |
756 | } else { | |
757 | coverage_on = 0; | |
758 | } | |
759 | ||
760 | if (coverage_on) { | |
761 | ||
762 | dram_coverage_group = new(); | |
763 | dram_coverage_group_l2 = new(); | |
764 | ||
765 | set_cov_cond_bits(); | |
766 | ||
767 | printf("\n\n %d : Coverage turned on for DRAM objects\n\n", get_time(LO)); | |
768 | ||
769 | fork { | |
770 | //@ (posedge dram_coverage_ifc_core_clk.cmp_diag_done); //change this to be based on all cores | |
771 | //@ (posedge dram_diag_done); //change this to be based on all cores | |
772 | //while (dram_diag_done == 0) { } //change this to be based on all cores | |
773 | //printf("\n\n %d : Waiting on dram_diag_done \n\n", get_time(LO)); | |
774 | #ifdef DRAM | |
775 | // sync(ANY,dram_diag_done); | |
776 | #else | |
777 | // @ (posedge dram_coverage_ifc_core_clk.cmp_diag_done); //change this to be based on all cores | |
778 | #endif | |
779 | //printf("\n\n %d : After dram_diag_done \n\n", get_time(LO)); | |
780 | dram_coverage_group.set_cov_weight(1); | |
781 | dram_coverage_group_l2.set_cov_weight(1); | |
782 | coverage_save_database(1); | |
783 | printf("\n\n %d : Coverage for DRAM objects generated\n\n", get_time(LO)); | |
784 | } join none | |
785 | } // if coverage_on | |
786 | } | |
787 | ||
788 | ||
789 | task ${prefix}dram_coverage:: set_cov_cond_bits () | |
790 | { | |
791 | `ifdef IDT_AMB | |
792 | fork | |
793 | { | |
794 | while (1) | |
795 | { | |
796 | @(posedge dram_coverage_ifc_dram_clk.dram_gclk); | |
797 | a_cmd = mcu_fbd_cmd_a_sample_bind_Ch0.\$cmd; | |
798 | //printf("%d: %x CMD_A_1",get_time(LO), a_cmd); | |
799 | //printf("%d: %x PS_IN",get_time(LO), dram_coverage_ifc_dram_clk.ps_in); | |
800 | //printf("%d: %b SCLK",get_time(LO), dram_coverage_ifc_link_clk.sclk); | |
801 | while (dram_coverage_ifc_dram_clk.ps_in == 0)//tb_top.crc_errinject_top.sb_crc_errinj0a_p_ps_in | |
802 | { | |
803 | if (a_cmd == 5'b00000) | |
804 | { | |
805 | if (dram_coverage_ifc_dram_clk.ps_in !== dram_coverage_ifc_dram_clk.ps_out) | |
806 | { | |
807 | // printf("%d: Error trigger",get_time(LO)); | |
808 | trigger (mcu0_fbd_cmd_a_err_evnt_trig); | |
809 | } | |
810 | //@(posedge dram_coverage_ifc_link_clk.sclk); //tb_top.mcu_fmon.sclk | |
811 | //a_cmd = mcu_fbd_cmd_a_sample_bind_Ch0.\$cmd; | |
812 | } | |
813 | @(posedge dram_coverage_ifc_link_clk.sclk); //tb_top.mcu_fmon.sclk | |
814 | } | |
815 | // printf("\n%d: %x CMD_A_2",get_time(LO), a_cmd); | |
816 | // printf("\n%d: %x PS_IN",get_time(LO), dram_coverage_ifc_dram_clk.ps_in); | |
817 | for (i=1; i<5; i++) | |
818 | { | |
819 | if (dram_coverage_ifc_dram_clk.ps_in !== dram_coverage_ifc_dram_clk.ps_out) | |
820 | trigger (mcu0_fbd_cmd_a_err_evnt_trig); | |
821 | @(posedge dram_coverage_ifc_link_clk.sclk); | |
822 | } | |
823 | } | |
824 | } | |
825 | join none | |
826 | `endif | |
827 | ||
828 | fork | |
829 | { | |
830 | while (1) | |
831 | { | |
832 | @(posedge l2_to_mcu0_ras_intf.clk); | |
833 | mcu_secc0 = dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3; | |
834 | mcu_secc1 = dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3; | |
835 | mcu_scb_secc0 = dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err; | |
836 | mcu_scb_secc1 = dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err; | |
837 | mcu_mecc0 = dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3; | |
838 | mcu_mecc1 = dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3; | |
839 | mcu_scb_mecc0 = dram_coverage_ifc_core_clk.mcu0_l2t0_scb_mecc_err; | |
840 | mcu_scb_mecc1 = dram_coverage_ifc_core_clk.mcu1_l2t0_scb_mecc_err; | |
841 | mcu_secc_both = {mcu_secc1,mcu_secc0}; | |
842 | mcu_scb_secc_both = {mcu_scb_secc1,mcu_scb_secc0}; | |
843 | mcu_mecc_both = {mcu_mecc1,mcu_mecc0}; | |
844 | mcu_scb_mecc_both = {mcu_scb_mecc1,mcu_scb_mecc0}; | |
845 | if ( dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_d3 === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_d3 === 1'b1 ) | |
846 | trigger (mcu01_secc_evnt_trig); | |
847 | } | |
848 | } | |
849 | join none | |
850 | ||
851 | fork | |
852 | { | |
853 | integer i ; | |
854 | while (1) | |
855 | { | |
856 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
857 | mcu0_data_vld_3_secc = mcu0_data_vld_2_secc; | |
858 | mcu0_data_vld_2_secc = mcu0_data_vld_1_secc; | |
859 | mcu0_data_vld_1_secc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
860 | mcu1_data_vld_3_secc = mcu1_data_vld_2_secc; | |
861 | mcu1_data_vld_2_secc = mcu1_data_vld_1_secc; | |
862 | mcu1_data_vld_1_secc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
863 | mcu2_data_vld_3_secc = mcu2_data_vld_2_secc; | |
864 | mcu2_data_vld_2_secc = mcu2_data_vld_1_secc; | |
865 | mcu2_data_vld_1_secc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
866 | mcu3_data_vld_3_secc = mcu3_data_vld_2_secc; | |
867 | mcu3_data_vld_2_secc = mcu3_data_vld_1_secc; | |
868 | mcu3_data_vld_1_secc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
869 | { | |
870 | error_bits_secc[0] = ( mcu0_data_vld_3_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1 ); | |
871 | error_bits_secc[1] = ( mcu1_data_vld_3_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1 ); | |
872 | error_bits_secc[2] = ( mcu2_data_vld_3_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1 ); | |
873 | error_bits_secc[3] = ( mcu3_data_vld_3_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1 ); | |
874 | } | |
875 | for (i=0 ; i<4 ; i++) | |
876 | { | |
877 | if (error_bits_secc[i] == 1) | |
878 | error_count_secc = error_count_secc + 1 ; | |
879 | } | |
880 | ||
881 | if (error_bits_secc !==4'b0) | |
882 | start_counter_secc = 1; | |
883 | if (start_counter_secc) | |
884 | mcu0_mcu1_secc_counter++ ; | |
885 | ||
886 | if (mcu0_mcu1_secc_counter <= 20) | |
887 | { | |
888 | if (error_count_secc == 2) | |
889 | { | |
890 | trigger (mcu01_secc_error_evnt_trig ); | |
891 | error_count_secc = 0 ; | |
892 | start_counter_secc = 0; | |
893 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
894 | mcu0_mcu1_secc_counter = 0 ; | |
895 | } | |
896 | } | |
897 | else | |
898 | { | |
899 | error_count_secc = 0 ; | |
900 | start_counter_secc = 0; | |
901 | mcu0_mcu1_secc_counter = 0 ; | |
902 | } | |
903 | } | |
904 | } | |
905 | join none | |
906 | ||
907 | fork | |
908 | { | |
909 | integer i ; | |
910 | while (1) | |
911 | { | |
912 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
913 | mcu0_data_vld_3_scb_secc = mcu0_data_vld_2_scb_secc; | |
914 | mcu0_data_vld_2_scb_secc = mcu0_data_vld_1_scb_secc; | |
915 | mcu0_data_vld_1_scb_secc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
916 | mcu1_data_vld_3_scb_secc = mcu1_data_vld_2_scb_secc; | |
917 | mcu1_data_vld_2_scb_secc = mcu1_data_vld_1_scb_secc; | |
918 | mcu1_data_vld_1_scb_secc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
919 | mcu2_data_vld_3_scb_secc = mcu2_data_vld_2_scb_secc; | |
920 | mcu2_data_vld_2_scb_secc = mcu2_data_vld_1_scb_secc; | |
921 | mcu2_data_vld_1_scb_secc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
922 | mcu3_data_vld_3_scb_secc = mcu3_data_vld_2_scb_secc; | |
923 | mcu3_data_vld_2_scb_secc = mcu3_data_vld_1_scb_secc; | |
924 | mcu3_data_vld_1_scb_secc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
925 | ||
926 | { | |
927 | error_bits_scb_secc[0] = ( mcu0_data_vld_3_scb_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1 ); | |
928 | error_bits_scb_secc[1] = ( mcu1_data_vld_3_scb_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1 ); | |
929 | error_bits_scb_secc[2] = ( mcu2_data_vld_3_scb_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1 ); | |
930 | error_bits_scb_secc[3] = ( mcu3_data_vld_3_scb_secc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1 ); | |
931 | } | |
932 | for (i=0 ; i<4 ; i++) | |
933 | { | |
934 | if (error_bits_scb_secc[i] == 1) | |
935 | error_count_scb_secc = error_count_scb_secc + 1 ; | |
936 | } | |
937 | ||
938 | if (error_bits_scb_secc !==4'b0) | |
939 | start_counter_scb_secc = 1; | |
940 | if (start_counter_scb_secc) | |
941 | mcu0_mcu1_scb_secc_counter++ ; | |
942 | ||
943 | if (mcu0_mcu1_scb_secc_counter <= 20) | |
944 | { | |
945 | if (error_count_scb_secc == 2) | |
946 | { | |
947 | trigger (mcu01_scb_secc_error_evnt_trig ); | |
948 | error_count_scb_secc = 0 ; | |
949 | start_counter_scb_secc = 0; | |
950 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
951 | mcu0_mcu1_scb_secc_counter = 0 ; | |
952 | } | |
953 | } | |
954 | else | |
955 | { | |
956 | error_count_scb_secc = 0 ; | |
957 | start_counter_scb_secc = 0; | |
958 | mcu0_mcu1_scb_secc_counter = 0 ; | |
959 | } | |
960 | ||
961 | } | |
962 | } | |
963 | join none | |
964 | ||
965 | fork | |
966 | { | |
967 | integer i ; | |
968 | while (1) | |
969 | { | |
970 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
971 | mcu0_data_vld_3_mecc = mcu0_data_vld_2_mecc; | |
972 | mcu0_data_vld_2_mecc = mcu0_data_vld_1_mecc; | |
973 | mcu0_data_vld_1_mecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
974 | mcu1_data_vld_3_mecc = mcu1_data_vld_2_mecc; | |
975 | mcu1_data_vld_2_mecc = mcu1_data_vld_1_mecc; | |
976 | mcu1_data_vld_1_mecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
977 | mcu2_data_vld_3_mecc = mcu2_data_vld_2_mecc; | |
978 | mcu2_data_vld_2_mecc = mcu2_data_vld_1_mecc; | |
979 | mcu2_data_vld_1_mecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
980 | mcu3_data_vld_3_mecc = mcu3_data_vld_2_mecc; | |
981 | mcu3_data_vld_2_mecc = mcu3_data_vld_1_mecc; | |
982 | mcu3_data_vld_1_mecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
983 | { | |
984 | error_bits_mecc[0] = ( mcu0_data_vld_3_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3 === 1'b1 ); | |
985 | error_bits_mecc[1] = ( mcu1_data_vld_3_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3 === 1'b1 ); | |
986 | error_bits_mecc[2] = ( mcu2_data_vld_3_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_mecc_err_r3 === 1'b1 ); | |
987 | error_bits_mecc[3] = ( mcu3_data_vld_3_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_mecc_err_r3 === 1'b1 ); | |
988 | } | |
989 | ||
990 | for (i=0 ; i<4 ; i++) | |
991 | { | |
992 | if (error_bits_mecc[i] == 1) | |
993 | error_count_mecc = error_count_mecc + 1 ; | |
994 | } | |
995 | ||
996 | if (error_bits_mecc !==4'b0) | |
997 | start_counter_mecc = 1; | |
998 | if (start_counter_mecc) | |
999 | mcu0_mcu1_mecc_counter++ ; | |
1000 | ||
1001 | if (mcu0_mcu1_mecc_counter <= 20) | |
1002 | { | |
1003 | if (error_count_mecc == 2) | |
1004 | { | |
1005 | trigger (mcu01_mecc_error_evnt_trig ); | |
1006 | error_count_mecc = 0 ; | |
1007 | start_counter_mecc = 0; | |
1008 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1009 | mcu0_mcu1_mecc_counter = 0 ; | |
1010 | } | |
1011 | } | |
1012 | else | |
1013 | { | |
1014 | error_count_mecc = 0 ; | |
1015 | start_counter_mecc = 0; | |
1016 | mcu0_mcu1_mecc_counter = 0 ; | |
1017 | } | |
1018 | ||
1019 | } | |
1020 | } | |
1021 | join none | |
1022 | ||
1023 | fork | |
1024 | { | |
1025 | integer i ; | |
1026 | while (1) | |
1027 | { | |
1028 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1029 | mcu0_data_vld_3_scb_mecc = mcu0_data_vld_2_scb_mecc; | |
1030 | mcu0_data_vld_2_scb_mecc = mcu0_data_vld_1_scb_mecc; | |
1031 | mcu0_data_vld_1_scb_mecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1032 | mcu1_data_vld_3_scb_mecc = mcu1_data_vld_2_scb_mecc; | |
1033 | mcu1_data_vld_2_scb_mecc = mcu1_data_vld_1_scb_mecc; | |
1034 | mcu1_data_vld_1_scb_mecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1035 | mcu2_data_vld_3_scb_mecc = mcu2_data_vld_2_scb_mecc; | |
1036 | mcu2_data_vld_2_scb_mecc = mcu2_data_vld_1_scb_mecc; | |
1037 | mcu2_data_vld_1_scb_mecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1038 | mcu3_data_vld_3_scb_mecc = mcu3_data_vld_2_scb_mecc; | |
1039 | mcu3_data_vld_2_scb_mecc = mcu3_data_vld_1_scb_mecc; | |
1040 | mcu3_data_vld_1_scb_mecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1041 | ||
1042 | { | |
1043 | error_bits_scb_mecc[0] = ( mcu0_data_vld_3_scb_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_mecc_err === 1'b1 ); | |
1044 | error_bits_scb_mecc[1] = ( mcu1_data_vld_3_scb_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_mecc_err === 1'b1 ); | |
1045 | error_bits_scb_mecc[2] = ( mcu2_data_vld_3_scb_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_mecc_err === 1'b1 ); | |
1046 | error_bits_scb_mecc[3] = ( mcu3_data_vld_3_scb_mecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_mecc_err === 1'b1 ); | |
1047 | } | |
1048 | for (i=0 ; i<4 ; i++) | |
1049 | { | |
1050 | if (error_bits_scb_mecc[i] == 1) | |
1051 | error_count_scb_mecc = error_count_scb_mecc + 1 ; | |
1052 | } | |
1053 | ||
1054 | if (error_bits_scb_mecc !==4'b0) | |
1055 | start_counter_scb_mecc = 1; | |
1056 | if (start_counter_scb_mecc) | |
1057 | mcu0_mcu1_scb_mecc_counter++ ; | |
1058 | ||
1059 | if (mcu0_mcu1_scb_mecc_counter <= 20) | |
1060 | { | |
1061 | if (error_count_scb_mecc == 2) | |
1062 | { | |
1063 | trigger (mcu01_scb_mecc_error_evnt_trig ); | |
1064 | error_count_scb_mecc = 0 ; | |
1065 | start_counter_scb_mecc = 0; | |
1066 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1067 | mcu0_mcu1_scb_mecc_counter = 0 ; | |
1068 | } | |
1069 | } | |
1070 | else | |
1071 | { | |
1072 | error_count_scb_mecc = 0 ; | |
1073 | start_counter_scb_mecc = 0; | |
1074 | mcu0_mcu1_scb_mecc_counter = 0 ; | |
1075 | } | |
1076 | ||
1077 | } | |
1078 | } | |
1079 | join none | |
1080 | ||
1081 | fork | |
1082 | { | |
1083 | while (1) | |
1084 | { | |
1085 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1086 | mcu0_data_vld_3_sscbsecc = mcu0_data_vld_2_sscbsecc; | |
1087 | mcu0_data_vld_2_sscbsecc = mcu0_data_vld_1_sscbsecc; | |
1088 | mcu0_data_vld_1_sscbsecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1089 | mcu1_data_vld_3_sscbsecc = mcu1_data_vld_2_sscbsecc; | |
1090 | mcu1_data_vld_2_sscbsecc = mcu1_data_vld_1_sscbsecc; | |
1091 | mcu1_data_vld_1_sscbsecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1092 | mcu2_data_vld_3_sscbsecc = mcu2_data_vld_2_sscbsecc; | |
1093 | mcu2_data_vld_2_sscbsecc = mcu2_data_vld_1_sscbsecc; | |
1094 | mcu2_data_vld_1_sscbsecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1095 | mcu3_data_vld_3_sscbsecc = mcu3_data_vld_2_sscbsecc; | |
1096 | mcu3_data_vld_2_sscbsecc = mcu3_data_vld_1_sscbsecc; | |
1097 | mcu3_data_vld_1_sscbsecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1098 | ||
1099 | if ( (mcu0_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1) | (mcu1_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1) | (mcu2_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1) | (mcu3_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1) && (start_counter_sscbsecc == 0) ) | |
1100 | { | |
1101 | start_counter_sscbsecc = 1; | |
1102 | mcu0_mcu1_secc_scbs_counter = 0; | |
1103 | } | |
1104 | else if ( (mcu0_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1) | (mcu1_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1) | (mcu2_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1) | (mcu3_data_vld_3_sscbsecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1) && (start_counter_sscbsecc == 1) && (mcu0_mcu1_secc_scbs_counter <= 20) ) | |
1105 | { | |
1106 | trigger (mcu01_secc_scbs_error_evnt_trig); | |
1107 | start_counter_sscbsecc = 0; | |
1108 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1109 | mcu0_mcu1_secc_scbs_counter = 0; | |
1110 | } | |
1111 | else if ( (mcu0_data_vld_3_sscbsecc === 1'b0 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b0) && (mcu1_data_vld_3_sscbsecc === 1'b0 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b0) | (mcu2_data_vld_3_sscbsecc === 1'b0 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b0) | (mcu3_data_vld_3_sscbsecc === 1'b0 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b0) && (start_counter_sscbsecc == 1) && (mcu0_mcu1_secc_scbs_counter <= 20) ) | |
1112 | { | |
1113 | mcu0_mcu1_secc_scbs_counter = mcu0_mcu1_secc_scbs_counter + 1; | |
1114 | } | |
1115 | else if (( start_counter_sscbsecc == 1) && (mcu0_mcu1_secc_scbs_counter >= 20)) | |
1116 | { | |
1117 | start_counter_sscbsecc = 0; | |
1118 | mcu0_mcu1_secc_scbs_counter = 0; | |
1119 | } | |
1120 | } | |
1121 | } | |
1122 | join none | |
1123 | ||
1124 | fork | |
1125 | { | |
1126 | while (1) | |
1127 | { | |
1128 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1129 | mcu0_data_vld_3_smecc = mcu0_data_vld_2_smecc; | |
1130 | mcu0_data_vld_2_smecc = mcu0_data_vld_1_smecc; | |
1131 | mcu0_data_vld_1_smecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1132 | mcu1_data_vld_3_smecc = mcu1_data_vld_2_smecc; | |
1133 | mcu1_data_vld_2_smecc = mcu1_data_vld_1_smecc; | |
1134 | mcu1_data_vld_1_smecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1135 | mcu2_data_vld_3_smecc = mcu2_data_vld_2_smecc; | |
1136 | mcu2_data_vld_2_smecc = mcu2_data_vld_1_smecc; | |
1137 | mcu2_data_vld_1_smecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1138 | mcu3_data_vld_3_smecc = mcu3_data_vld_2_smecc; | |
1139 | mcu3_data_vld_2_smecc = mcu3_data_vld_1_smecc; | |
1140 | mcu3_data_vld_1_smecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1141 | ||
1142 | if ( (mcu0_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1) | (mcu1_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1) | (mcu2_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1) | (mcu3_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1) && (start_counter_smecc == 0) ) | |
1143 | { | |
1144 | start_counter_smecc = 1; | |
1145 | mcu0_mcu1_secc_mecc_counter = 0; | |
1146 | } | |
1147 | else if ( (mcu0_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3 === 1'b1) | (mcu1_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3 === 1'b1) | (mcu2_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_mecc_err_r3 === 1'b1) | (mcu3_data_vld_3_smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_mecc_err_r3 === 1'b1) && (start_counter_smecc == 1) && (mcu0_mcu1_secc_mecc_counter <= 20) ) | |
1148 | { | |
1149 | trigger (mcu01_secc_mecc_error_evnt_trig); | |
1150 | // printf("\n%d: %d AFTER_TRIG",get_time(LO), mcu0_mcu1_secc_mecc_counter ); | |
1151 | start_counter_smecc = 0; | |
1152 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1153 | mcu0_mcu1_secc_mecc_counter = 0; | |
1154 | } | |
1155 | else if ( (mcu0_data_vld_3_smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b0) && (mcu1_data_vld_3_smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b0) | (mcu2_data_vld_3_smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b0) | (mcu3_data_vld_3_smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b0) && (start_counter_smecc == 1) && (mcu0_mcu1_secc_mecc_counter <= 20) ) | |
1156 | { | |
1157 | mcu0_mcu1_secc_mecc_counter = mcu0_mcu1_secc_mecc_counter + 1 ; | |
1158 | // printf("\n%d: %d LOOP_MCU_MCU1_SMECC_COUNT",get_time(LO), mcu0_mcu1_secc_mecc_counter ); | |
1159 | } | |
1160 | else if (( start_counter_smecc == 1) && (mcu0_mcu1_secc_mecc_counter >= 20)) | |
1161 | { | |
1162 | start_counter_smecc = 0 ; | |
1163 | mcu0_mcu1_secc_mecc_counter = 0; | |
1164 | } | |
1165 | } | |
1166 | } | |
1167 | join none | |
1168 | ||
1169 | fork | |
1170 | { | |
1171 | while (1) | |
1172 | { | |
1173 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1174 | mcu0_data_vld_3_sscbmecc = mcu0_data_vld_2_sscbmecc; | |
1175 | mcu0_data_vld_2_sscbmecc = mcu0_data_vld_1_sscbmecc; | |
1176 | mcu0_data_vld_1_sscbmecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1177 | mcu1_data_vld_3_sscbmecc = mcu1_data_vld_2_sscbmecc; | |
1178 | mcu1_data_vld_2_sscbmecc = mcu1_data_vld_1_sscbmecc; | |
1179 | mcu1_data_vld_1_sscbmecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1180 | mcu2_data_vld_3_sscbmecc = mcu2_data_vld_2_sscbmecc; | |
1181 | mcu2_data_vld_2_sscbmecc = mcu2_data_vld_1_sscbmecc; | |
1182 | mcu2_data_vld_1_sscbmecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1183 | mcu3_data_vld_3_sscbmecc = mcu3_data_vld_2_sscbmecc; | |
1184 | mcu3_data_vld_2_sscbmecc = mcu3_data_vld_1_sscbmecc; | |
1185 | mcu3_data_vld_1_sscbmecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1186 | ||
1187 | if ( (mcu0_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1) | (mcu1_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1) | (mcu2_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1) | (mcu3_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1) && (start_counter_sscbmecc == 0) ) | |
1188 | { | |
1189 | start_counter_sscbmecc = 1; | |
1190 | mcu0_mcu1_secc_scbm_counter = 0; | |
1191 | } | |
1192 | else if ( (mcu0_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_mecc_err === 1'b1) | (mcu1_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_mecc_err === 1'b1) | (mcu2_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_mecc_err === 1'b1) | (mcu3_data_vld_3_sscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_mecc_err === 1'b1) && (start_counter_sscbmecc == 1) && (mcu0_mcu1_secc_scbm_counter <= 20) ) | |
1193 | { | |
1194 | trigger (mcu01_secc_scbm_error_evnt_trig); | |
1195 | start_counter_sscbmecc = 0; | |
1196 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1197 | mcu0_mcu1_secc_scbm_counter = 0; | |
1198 | } | |
1199 | else if ( (mcu0_data_vld_3_sscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b0) && (mcu1_data_vld_3_sscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b0) | (mcu2_data_vld_3_sscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b0) | (mcu3_data_vld_3_sscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b0) && (start_counter_sscbmecc == 1) && (mcu0_mcu1_secc_scbm_counter <= 20) ) | |
1200 | { | |
1201 | mcu0_mcu1_secc_scbm_counter = mcu0_mcu1_secc_scbm_counter + 1; | |
1202 | } | |
1203 | else if (( start_counter_sscbmecc == 1) && (mcu0_mcu1_secc_scbm_counter >= 20)) | |
1204 | { | |
1205 | start_counter_sscbmecc = 0; | |
1206 | mcu0_mcu1_secc_scbm_counter = 0; | |
1207 | } | |
1208 | } | |
1209 | } | |
1210 | join none | |
1211 | ||
1212 | fork | |
1213 | { | |
1214 | while (1) | |
1215 | { | |
1216 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1217 | mcu0_data_vld_3_scbsmecc = mcu0_data_vld_2_scbsmecc; | |
1218 | mcu0_data_vld_2_scbsmecc = mcu0_data_vld_1_scbsmecc; | |
1219 | mcu0_data_vld_1_scbsmecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1220 | mcu1_data_vld_3_scbsmecc = mcu1_data_vld_2_scbsmecc; | |
1221 | mcu1_data_vld_2_scbsmecc = mcu1_data_vld_1_scbsmecc; | |
1222 | mcu1_data_vld_1_scbsmecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1223 | mcu2_data_vld_3_scbsmecc = mcu2_data_vld_2_scbsmecc; | |
1224 | mcu2_data_vld_2_scbsmecc = mcu2_data_vld_1_scbsmecc; | |
1225 | mcu2_data_vld_1_scbsmecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1226 | mcu3_data_vld_3_scbsmecc = mcu3_data_vld_2_scbsmecc; | |
1227 | mcu3_data_vld_2_scbsmecc = mcu3_data_vld_1_scbsmecc; | |
1228 | mcu3_data_vld_1_scbsmecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1229 | if ( (mcu0_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1) | (mcu1_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1) | (mcu2_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1) | (mcu3_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1) && (start_counter_scbsmecc == 0) ) | |
1230 | { | |
1231 | start_counter_scbsmecc = 1; | |
1232 | mcu0_mcu1_scb_mecc1_counter = 0; | |
1233 | } | |
1234 | else if ( (mcu0_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3 === 1'b1) | (mcu1_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3 === 1'b1) | (mcu2_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_mecc_err_r3 === 1'b1) | (mcu3_data_vld_3_scbsmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_mecc_err_r3 === 1'b1) && (start_counter_scbsmecc == 1) && (mcu0_mcu1_secc_mecc_counter <= 20) ) | |
1235 | { | |
1236 | trigger (mcu01_scb_mecc1_error_evnt_trig); | |
1237 | start_counter_scbsmecc = 0; | |
1238 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1239 | mcu0_mcu1_scb_mecc1_counter = 0; | |
1240 | } | |
1241 | else if ( (mcu0_data_vld_3_scbsmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b0) && (mcu1_data_vld_3_scbsmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b0) | (mcu2_data_vld_3_scbsmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b0) | (mcu3_data_vld_3_scbsmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b0) && (start_counter_scbsmecc == 1) && (mcu0_mcu1_secc_mecc_counter <= 20) ) | |
1242 | { | |
1243 | mcu0_mcu1_scb_mecc1_counter = mcu0_mcu1_scb_mecc1_counter + 1; | |
1244 | } | |
1245 | else if (( start_counter_scbsmecc == 1) && (mcu0_mcu1_scb_mecc1_counter >= 20)) | |
1246 | { | |
1247 | start_counter_scbsmecc = 0; | |
1248 | mcu0_mcu1_scb_mecc1_counter = 0; | |
1249 | } | |
1250 | ||
1251 | ||
1252 | } | |
1253 | } | |
1254 | join none | |
1255 | ||
1256 | fork | |
1257 | { | |
1258 | while (1) | |
1259 | { | |
1260 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1261 | mcu0_data_vld_3_scb2smecc = mcu0_data_vld_2_scb2smecc; | |
1262 | mcu0_data_vld_2_scb2smecc = mcu0_data_vld_1_scb2smecc; | |
1263 | mcu0_data_vld_1_scb2smecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1264 | mcu1_data_vld_3_scb2smecc = mcu1_data_vld_2_scb2smecc; | |
1265 | mcu1_data_vld_2_scb2smecc = mcu1_data_vld_1_scb2smecc; | |
1266 | mcu1_data_vld_1_scb2smecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1267 | mcu2_data_vld_3_scb2smecc = mcu2_data_vld_2_scb2smecc; | |
1268 | mcu2_data_vld_2_scb2smecc = mcu2_data_vld_1_scb2smecc; | |
1269 | mcu2_data_vld_1_scb2smecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1270 | mcu3_data_vld_3_scb2smecc = mcu3_data_vld_2_scb2smecc; | |
1271 | mcu3_data_vld_2_scb2smecc = mcu3_data_vld_1_scb2smecc; | |
1272 | mcu3_data_vld_1_scb2smecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1273 | if ( (mcu0_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1) | (mcu1_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1) | (mcu2_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1) | (mcu3_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1) && (start_counter_scb2smecc == 0) ) | |
1274 | { | |
1275 | start_counter_scb2smecc = 1; | |
1276 | mcu0_mcu1_scb_scbm_counter = 0; | |
1277 | } | |
1278 | else if ( (mcu0_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_mecc_err === 1'b1) | (mcu1_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_mecc_err === 1'b1) | (mcu2_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_mecc_err === 1'b1) | (mcu3_data_vld_3_scb2smecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_mecc_err === 1'b1) && (start_counter_scb2smecc == 1) && (mcu0_mcu1_scb_scbm_counter <= 20) ) | |
1279 | { | |
1280 | trigger (mcu01_scb_scbm_error_evnt_trig); | |
1281 | start_counter_scb2smecc = 0; | |
1282 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1283 | mcu0_mcu1_scb_scbm_counter = 0; | |
1284 | } | |
1285 | else if ( (mcu0_data_vld_3_scb2smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b0) && (mcu1_data_vld_3_scb2smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b0) | (mcu2_data_vld_3_scb2smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b0) | (mcu3_data_vld_3_scb2smecc === 1'b0 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b0) && (start_counter_scb2smecc == 1) && (mcu0_mcu1_secc_mecc_counter <= 20) ) | |
1286 | { | |
1287 | mcu0_mcu1_scb_scbm_counter = mcu0_mcu1_scb_scbm_counter + 1; | |
1288 | } | |
1289 | else if (( start_counter_scb2smecc == 1) && (mcu0_mcu1_scb_scbm_counter >= 20)) | |
1290 | { | |
1291 | start_counter_scb2smecc = 0; | |
1292 | mcu0_mcu1_scb_scbm_counter = 0; | |
1293 | } | |
1294 | } | |
1295 | } | |
1296 | join none | |
1297 | ||
1298 | fork | |
1299 | { | |
1300 | while (1) | |
1301 | { | |
1302 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1303 | mcu0_data_vld_3_mscbmecc = mcu0_data_vld_2_mscbmecc; | |
1304 | mcu0_data_vld_2_mscbmecc = mcu0_data_vld_1_mscbmecc; | |
1305 | mcu0_data_vld_1_mscbmecc = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1306 | mcu1_data_vld_3_mscbmecc = mcu1_data_vld_2_mscbmecc; | |
1307 | mcu1_data_vld_2_mscbmecc = mcu1_data_vld_1_mscbmecc; | |
1308 | mcu1_data_vld_1_mscbmecc = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1309 | mcu2_data_vld_3_mscbmecc = mcu2_data_vld_2_mscbmecc; | |
1310 | mcu2_data_vld_2_mscbmecc = mcu2_data_vld_1_mscbmecc; | |
1311 | mcu2_data_vld_1_mscbmecc = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1312 | mcu3_data_vld_3_mscbmecc = mcu3_data_vld_2_mscbmecc; | |
1313 | mcu3_data_vld_2_mscbmecc = mcu3_data_vld_1_mscbmecc; | |
1314 | mcu3_data_vld_1_mscbmecc = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1315 | ||
1316 | if ( (mcu0_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3 === 1'b1) | (mcu1_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3 === 1'b1) | (mcu2_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_mecc_err_r3 === 1'b1) | (mcu3_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_mecc_err_r3 === 1'b1) && (start_counter_mscbmecc == 0) ) | |
1317 | { | |
1318 | start_counter_mscbmecc = 1; | |
1319 | mcu0_mcu1_mecc_scbm_counter = 0; | |
1320 | } | |
1321 | else if ( (mcu0_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_mecc_err === 1'b1) | (mcu1_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_mecc_err === 1'b1) | (mcu2_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_mecc_err === 1'b1) | (mcu3_data_vld_3_mscbmecc === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_mecc_err === 1'b1) && (start_counter_mscbmecc == 1) && (mcu0_mcu1_mecc_scbm_counter <= 20) ) | |
1322 | { | |
1323 | trigger (mcu01_mecc_scbm_error_evnt_trig); | |
1324 | start_counter_mscbmecc = 0; | |
1325 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1326 | mcu0_mcu1_mecc_scbm_counter = 0; | |
1327 | } | |
1328 | else if ( (mcu0_data_vld_3_mscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3 === 1'b0) && (mcu1_data_vld_3_mscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3 === 1'b0) | (mcu2_data_vld_3_mscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu2_l2t0_mecc_err_r3 === 1'b0) | (mcu3_data_vld_3_mscbmecc === 1'b0 && dram_coverage_ifc_core_clk.mcu3_l2t0_mecc_err_r3 === 1'b0) && (start_counter_mscbmecc == 1) && (mcu0_mcu1_mecc_scbm_counter <= 20) ) | |
1329 | { | |
1330 | mcu0_mcu1_mecc_scbm_counter = mcu0_mcu1_mecc_scbm_counter + 1 ; | |
1331 | } | |
1332 | else if (( start_counter_mscbmecc == 1) && (mcu0_mcu1_mecc_scbm_counter >= 20)) | |
1333 | { | |
1334 | start_counter_mscbmecc = 0; | |
1335 | mcu0_mcu1_mecc_scbm_counter = 0; | |
1336 | } | |
1337 | } | |
1338 | } | |
1339 | join none | |
1340 | ||
1341 | fork | |
1342 | { | |
1343 | integer i ; | |
1344 | while (1) | |
1345 | { | |
1346 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1347 | mcu0_data_vld_3_secc_3 = mcu0_data_vld_2_secc_3 ; | |
1348 | mcu0_data_vld_2_secc_3 = mcu0_data_vld_1_secc_3 ; | |
1349 | mcu0_data_vld_1_secc_3 = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0 ; | |
1350 | mcu1_data_vld_3_secc_3 = mcu1_data_vld_2_secc_3 ; | |
1351 | mcu1_data_vld_2_secc_3 = mcu1_data_vld_1_secc_3 ; | |
1352 | mcu1_data_vld_1_secc_3 = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0 ; | |
1353 | mcu2_data_vld_3_secc_3 = mcu2_data_vld_2_secc_3 ; | |
1354 | mcu2_data_vld_2_secc_3 = mcu2_data_vld_1_secc_3 ; | |
1355 | mcu2_data_vld_1_secc_3 = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0 ; | |
1356 | mcu3_data_vld_3_secc_3 = mcu3_data_vld_2_secc_3 ; | |
1357 | mcu3_data_vld_2_secc_3 = mcu3_data_vld_1_secc_3 ; | |
1358 | mcu3_data_vld_1_secc_3 = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0 ; | |
1359 | { | |
1360 | error_bits_secc_3[0] = ( mcu0_data_vld_3_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1); | |
1361 | error_bits_secc_3[1] = ( mcu1_data_vld_3_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1); | |
1362 | error_bits_secc_3[2] = ( mcu2_data_vld_3_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1); | |
1363 | error_bits_secc_3[3] = ( mcu3_data_vld_3_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1); | |
1364 | } | |
1365 | for (i=0 ; i<4 ; i++) | |
1366 | { | |
1367 | if (error_bits_secc_3[i] == 1) | |
1368 | error_count_secc_3 = error_count_secc_3 + 1 ; | |
1369 | } | |
1370 | ||
1371 | if (error_bits_secc_3 !==4'b0) | |
1372 | start_counter_secc_3 = 1; | |
1373 | if (start_counter_secc_3) | |
1374 | mcu0_mcu1_mcu2_secc_counter++ ; | |
1375 | ||
1376 | if (mcu0_mcu1_mcu2_secc_counter <= 30) | |
1377 | { | |
1378 | if (error_count_secc_3 == 3) | |
1379 | { | |
1380 | trigger (mcu012_secc_error_evnt_trig ); | |
1381 | error_count_secc_3 = 0 ; | |
1382 | start_counter_secc_3 = 0; | |
1383 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1384 | mcu0_mcu1_mcu2_secc_counter = 0; | |
1385 | } | |
1386 | } | |
1387 | else | |
1388 | { | |
1389 | error_count_secc_3 = 0 ; | |
1390 | start_counter_secc_3 = 0; | |
1391 | mcu0_mcu1_mcu2_secc_counter = 0; | |
1392 | } | |
1393 | } | |
1394 | } | |
1395 | join none | |
1396 | ||
1397 | fork | |
1398 | { | |
1399 | integer i ; | |
1400 | while (1) | |
1401 | { | |
1402 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1403 | mcu0_data_vld_3_scb_secc_3 = mcu0_data_vld_2_scb_secc_3 ; | |
1404 | mcu0_data_vld_2_scb_secc_3 = mcu0_data_vld_1_scb_secc_3 ; | |
1405 | mcu0_data_vld_1_scb_secc_3 = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0 ; | |
1406 | mcu1_data_vld_3_scb_secc_3 = mcu1_data_vld_2_scb_secc_3 ; | |
1407 | mcu1_data_vld_2_scb_secc_3 = mcu1_data_vld_1_scb_secc_3 ; | |
1408 | mcu1_data_vld_1_scb_secc_3 = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0 ; | |
1409 | mcu2_data_vld_3_scb_secc_3 = mcu2_data_vld_2_scb_secc_3 ; | |
1410 | mcu2_data_vld_2_scb_secc_3 = mcu2_data_vld_1_scb_secc_3 ; | |
1411 | mcu2_data_vld_1_scb_secc_3 = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0 ; | |
1412 | mcu3_data_vld_3_scb_secc_3 = mcu3_data_vld_2_scb_secc_3 ; | |
1413 | mcu3_data_vld_2_scb_secc_3 = mcu3_data_vld_1_scb_secc_3 ; | |
1414 | mcu3_data_vld_1_scb_secc_3 = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0 ; | |
1415 | ||
1416 | { | |
1417 | error_bits_scb_secc_3[0] = ( mcu0_data_vld_3_scb_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1); | |
1418 | error_bits_scb_secc_3[1] = ( mcu1_data_vld_3_scb_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1); | |
1419 | error_bits_scb_secc_3[2] = ( mcu2_data_vld_3_scb_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1); | |
1420 | error_bits_scb_secc_3[3] = ( mcu3_data_vld_3_scb_secc_3 === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1); | |
1421 | } | |
1422 | for (i=0 ; i<4 ; i++) | |
1423 | { | |
1424 | if (error_bits_scb_secc_3[i] == 1) | |
1425 | error_count_scb_secc_3 = error_count_scb_secc_3 + 1 ; | |
1426 | } | |
1427 | ||
1428 | if (error_bits_scb_secc_3 !==4'b0) | |
1429 | start_counter_scb_secc_3 = 1; | |
1430 | if (start_counter_scb_secc_3) | |
1431 | mcu0_mcu1_mcu2_scb_secc_counter++ ; | |
1432 | ||
1433 | if (mcu0_mcu1_mcu2_scb_secc_counter <= 30) | |
1434 | { | |
1435 | if (error_count_scb_secc_3 == 3) | |
1436 | { | |
1437 | trigger (mcu012_scb_secc_error_evnt_trig ); | |
1438 | error_count_scb_secc_3 = 0 ; | |
1439 | start_counter_scb_secc_3 = 0; | |
1440 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1441 | mcu0_mcu1_mcu2_scb_secc_counter = 0; | |
1442 | } | |
1443 | } | |
1444 | else | |
1445 | { | |
1446 | error_count_scb_secc_3 = 0 ; | |
1447 | start_counter_scb_secc_3 = 0; | |
1448 | mcu0_mcu1_mcu2_scb_secc_counter = 0; | |
1449 | } | |
1450 | ||
1451 | } | |
1452 | } | |
1453 | join none | |
1454 | ||
1455 | fork | |
1456 | { | |
1457 | integer i ; | |
1458 | while (1) | |
1459 | { | |
1460 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1461 | mcu0_data_vld_3_secc_4 = mcu0_data_vld_2_secc_4 ; | |
1462 | mcu0_data_vld_2_secc_4 = mcu0_data_vld_1_secc_4 ; | |
1463 | mcu0_data_vld_1_secc_4 = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0 ; | |
1464 | mcu1_data_vld_3_secc_4 = mcu1_data_vld_2_secc_4 ; | |
1465 | mcu1_data_vld_2_secc_4 = mcu1_data_vld_1_secc_4 ; | |
1466 | mcu1_data_vld_1_secc_4 = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0 ; | |
1467 | mcu2_data_vld_3_secc_4 = mcu2_data_vld_2_secc_4 ; | |
1468 | mcu2_data_vld_2_secc_4 = mcu2_data_vld_1_secc_4 ; | |
1469 | mcu2_data_vld_1_secc_4 = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0 ; | |
1470 | mcu3_data_vld_3_secc_4 = mcu3_data_vld_2_secc_4 ; | |
1471 | mcu3_data_vld_2_secc_4 = mcu3_data_vld_1_secc_4 ; | |
1472 | mcu3_data_vld_1_secc_4 = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0 ; | |
1473 | { | |
1474 | error_bits_secc_4[0] = ( mcu0_data_vld_3_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1 ); | |
1475 | error_bits_secc_4[1] = ( mcu1_data_vld_3_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1 ); | |
1476 | error_bits_secc_4[2] = ( mcu2_data_vld_3_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1 ); | |
1477 | error_bits_secc_4[3] = ( mcu3_data_vld_3_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1 ); | |
1478 | } | |
1479 | for (i=0 ; i<4 ; i++) | |
1480 | { | |
1481 | if (error_bits_secc_4[i] == 1) | |
1482 | error_count_secc_4 = error_count_secc_4 + 1 ; | |
1483 | } | |
1484 | ||
1485 | if (error_bits_secc_4 !==4'b0) | |
1486 | start_counter_secc_4 = 1; | |
1487 | if (start_counter_secc_4) | |
1488 | mcu0_mcu1_mcu2_mcu3_secc_counter++ ; | |
1489 | ||
1490 | if (mcu0_mcu1_mcu2_mcu3_secc_counter <= 50) | |
1491 | { | |
1492 | if (error_count_secc_4 == 4) | |
1493 | { | |
1494 | trigger (mcu0123_secc_error_evnt_trig ); | |
1495 | error_count_secc_4 = 0 ; | |
1496 | start_counter_secc_4 = 0; | |
1497 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1498 | mcu0_mcu1_mcu2_mcu3_secc_counter = 0; | |
1499 | } | |
1500 | } | |
1501 | else | |
1502 | { | |
1503 | error_count_secc_4 = 0 ; | |
1504 | start_counter_secc_4 = 0; | |
1505 | mcu0_mcu1_mcu2_mcu3_secc_counter = 0; | |
1506 | } | |
1507 | ||
1508 | } | |
1509 | } | |
1510 | join none | |
1511 | ||
1512 | fork | |
1513 | { | |
1514 | integer i ; | |
1515 | while (1) | |
1516 | { | |
1517 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1518 | mcu0_data_vld_3_scb_secc_4 = mcu0_data_vld_2_scb_secc_4 ; | |
1519 | mcu0_data_vld_2_scb_secc_4 = mcu0_data_vld_1_scb_secc_4 ; | |
1520 | mcu0_data_vld_1_scb_secc_4 = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0 ; | |
1521 | mcu1_data_vld_3_scb_secc_4 = mcu1_data_vld_2_scb_secc_4 ; | |
1522 | mcu1_data_vld_2_scb_secc_4 = mcu1_data_vld_1_scb_secc_4 ; | |
1523 | mcu1_data_vld_1_scb_secc_4 = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0 ; | |
1524 | mcu2_data_vld_3_scb_secc_4 = mcu2_data_vld_2_scb_secc_4 ; | |
1525 | mcu2_data_vld_2_scb_secc_4 = mcu2_data_vld_1_scb_secc_4 ; | |
1526 | mcu2_data_vld_1_scb_secc_4 = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0 ; | |
1527 | mcu3_data_vld_3_scb_secc_4 = mcu3_data_vld_2_scb_secc_4 ; | |
1528 | mcu3_data_vld_2_scb_secc_4 = mcu3_data_vld_1_scb_secc_4 ; | |
1529 | mcu3_data_vld_1_scb_secc_4 = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0 ; | |
1530 | { | |
1531 | error_bits_scb_secc_4[0] = ( mcu0_data_vld_3_scb_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1 ); | |
1532 | error_bits_scb_secc_4[1] = ( mcu1_data_vld_3_scb_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1 ); | |
1533 | error_bits_scb_secc_4[2] = ( mcu2_data_vld_3_scb_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1 ); | |
1534 | error_bits_scb_secc_4[3] = ( mcu3_data_vld_3_scb_secc_4 === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1 ); | |
1535 | } | |
1536 | for (i=0 ; i<4 ; i++) | |
1537 | { | |
1538 | if (error_bits_scb_secc_4[i] == 1) | |
1539 | error_count_scb_secc_4 = error_count_scb_secc_4 + 1 ; | |
1540 | } | |
1541 | ||
1542 | if (error_bits_scb_secc_4 !==4'b0) | |
1543 | start_counter_scb_secc_4 = 1; | |
1544 | if (start_counter_scb_secc_4) | |
1545 | mcu0_mcu1_mcu2_mcu3_scb_secc_counter++ ; | |
1546 | ||
1547 | if (mcu0_mcu1_mcu2_mcu3_scb_secc_counter <= 50) | |
1548 | { | |
1549 | if (error_count_scb_secc_4 == 4) | |
1550 | { | |
1551 | trigger (mcu0123_scb_secc_error_evnt_trig ); | |
1552 | error_count_scb_secc_4 = 0 ; | |
1553 | start_counter_scb_secc_4 = 0; | |
1554 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1555 | mcu0_mcu1_mcu2_mcu3_scb_secc_counter = 0; | |
1556 | } | |
1557 | } | |
1558 | else | |
1559 | { | |
1560 | error_count_scb_secc_4 = 0 ; | |
1561 | start_counter_scb_secc_4 = 0; | |
1562 | mcu0_mcu1_mcu2_mcu3_scb_secc_counter = 0; | |
1563 | } | |
1564 | ||
1565 | } | |
1566 | } | |
1567 | join none | |
1568 | ||
1569 | fork | |
1570 | { | |
1571 | integer i ; | |
1572 | while (1) | |
1573 | { | |
1574 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1575 | mcu0_data_vld_3_all = mcu0_data_vld_2_all; | |
1576 | mcu0_data_vld_2_all = mcu0_data_vld_1_all; | |
1577 | mcu0_data_vld_1_all = dram_coverage_ifc_core_clk.mcu0_l2t0_data_vld_r0; | |
1578 | mcu1_data_vld_3_all = mcu1_data_vld_2_all; | |
1579 | mcu1_data_vld_2_all = mcu1_data_vld_1_all; | |
1580 | mcu1_data_vld_1_all = dram_coverage_ifc_core_clk.mcu1_l2t0_data_vld_r0; | |
1581 | mcu2_data_vld_3_all = mcu2_data_vld_2_all; | |
1582 | mcu2_data_vld_2_all = mcu2_data_vld_1_all; | |
1583 | mcu2_data_vld_1_all = dram_coverage_ifc_core_clk.mcu2_l2t0_data_vld_r0; | |
1584 | mcu3_data_vld_3_all = mcu3_data_vld_2_all; | |
1585 | mcu3_data_vld_2_all = mcu3_data_vld_1_all; | |
1586 | mcu3_data_vld_1_all = dram_coverage_ifc_core_clk.mcu3_l2t0_data_vld_r0; | |
1587 | ||
1588 | { | |
1589 | error_bits_all[0] = ( mcu0_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_secc_err_r3 === 1'b1 ); | |
1590 | error_bits_all[1] = ( mcu1_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_secc_err_r3 === 1'b1 ); | |
1591 | error_bits_all[2] = ( mcu2_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_secc_err_r3 === 1'b1 ); | |
1592 | error_bits_all[3] = ( mcu3_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_secc_err_r3 === 1'b1 ); | |
1593 | error_bits_all[4] = ( mcu0_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_secc_err === 1'b1 ); | |
1594 | error_bits_all[5] = ( mcu1_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_secc_err === 1'b1 ); | |
1595 | error_bits_all[6] = ( mcu2_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_secc_err === 1'b1 ); | |
1596 | error_bits_all[7] = ( mcu3_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_secc_err === 1'b1 ); | |
1597 | error_bits_all[8] = ( mcu0_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_mecc_err_r3 === 1'b1 ); | |
1598 | error_bits_all[9] = ( mcu1_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_mecc_err_r3 === 1'b1 ); | |
1599 | error_bits_all[10] = ( mcu2_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_mecc_err_r3 === 1'b1 ); | |
1600 | error_bits_all[11] = ( mcu3_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_mecc_err_r3 === 1'b1 ); | |
1601 | error_bits_all[12] = ( mcu0_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu0_l2t0_scb_mecc_err === 1'b1 ); | |
1602 | error_bits_all[13] = ( mcu1_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu1_l2t0_scb_mecc_err === 1'b1 ); | |
1603 | error_bits_all[14] = ( mcu2_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu2_l2t0_scb_mecc_err === 1'b1 ); | |
1604 | error_bits_all[15] = ( mcu3_data_vld_3_all === 1'b1 && dram_coverage_ifc_core_clk.mcu3_l2t0_scb_mecc_err === 1'b1 ); | |
1605 | } | |
1606 | ||
1607 | for (i=0; i< 16; i++) | |
1608 | { | |
1609 | if (error_bits_all[i] == 1) | |
1610 | error_count_all = error_count_all + 1 ; | |
1611 | } | |
1612 | if (error_bits_all !==16'b0) | |
1613 | start_counter_all = 1; | |
1614 | if (start_counter_all) | |
1615 | mcu0_mcu1_mcu2_mcu3_all_counter++ ; | |
1616 | ||
1617 | if (mcu0_mcu1_mcu2_mcu3_all_counter <= 100) | |
1618 | { | |
1619 | if (error_count_all == 16) | |
1620 | { | |
1621 | trigger (mcu0123_all_error_evnt_trig ); | |
1622 | error_count_all = 0 ; | |
1623 | start_counter_all = 0; | |
1624 | @(posedge dram_coverage_ifc_core_clk.cmp_clk); | |
1625 | mcu0_mcu1_mcu2_mcu3_all_counter = 0 ; | |
1626 | } | |
1627 | } | |
1628 | else | |
1629 | { | |
1630 | error_count_all = 0 ; | |
1631 | start_counter_all = 0; | |
1632 | mcu0_mcu1_mcu2_mcu3_all_counter = 0 ; | |
1633 | } | |
1634 | ||
1635 | } | |
1636 | } | |
1637 | join none | |
1638 | ||
1639 | } | |
1640 | ||
1641 | // ******************************************************************************************* | |
1642 | // MCU RAS Coverage objects - MAQ | |
1643 | // ******************************************************************************************* | |
1644 | ||
1645 | class fc_mcu_ras_coverage | |
1646 | { | |
1647 | // for dispmon | |
1648 | // MAQ StandardDisplay dbg; | |
1649 | // MAQ local string myname; | |
1650 | ||
1651 | . for($mcu_no=0; $mcu_no<1; $mcu_no++) | |
1652 | . { | |
1653 | reg l2_to_mcu${mcu_no}_sameclk = 1'b0; | |
1654 | reg l2_to_mcu${mcu_no}_error = 1'b0; | |
1655 | reg mcu${mcu_no}_to_l2t0_err = 1'b0; | |
1656 | reg mcu${mcu_no}_to_l2t1_err = 1'b0; | |
1657 | reg mcu${mcu_no}_to_l2t0_err_seen = 1'b0; | |
1658 | reg mcu${mcu_no}_to_l2t1_err_seen = 1'b0; | |
1659 | reg [3:0] l2_to_mcu${mcu_no}_error_10clk = 'd0; | |
1660 | reg [3:0] l2_to_mcu${mcu_no}_error_count = 'd0; | |
1661 | reg [3:0] mcu${mcu_no}_to_l2_error_10clk = 'd0; | |
1662 | reg [3:0] mcu${mcu_no}_l2t0_scb_secc_err_count = 'd0; | |
1663 | reg [3:0] mcu${mcu_no}_l2t1_scb_secc_err_count = 'd0; | |
1664 | reg [3:0] mcu${mcu_no}_l2t0_secc_err_count = 'd0; | |
1665 | reg [3:0] mcu${mcu_no}_l2t1_secc_err_count = 'd0; | |
1666 | ||
1667 | reg mcu${mcu_no}_l2t0_scb_secc_err_seen = 1'b0; | |
1668 | reg mcu${mcu_no}_l2t1_scb_secc_err_seen = 1'b0; | |
1669 | reg mcu${mcu_no}_l2t0_secc_err_seen = 1'b0; | |
1670 | reg mcu${mcu_no}_l2t1_secc_err_seen = 1'b0; | |
1671 | ||
1672 | reg [4:0] mcu${mcu_no}_l2t0_mecc_err_seen_20clk_count = 'd0; | |
1673 | reg [4:0] mcu${mcu_no}_l2t1_mecc_err_seen_20clk_count = 'd0; | |
1674 | reg [4:0] mcu${mcu_no}_to_l2_error_20clk = 'd0; | |
1675 | reg [4:0] mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_count = 'd0; | |
1676 | reg [4:0] mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_count = 'd0; | |
1677 | reg mcu${mcu_no}_l2t0_secc_err_seen_20clk = 1'b0; | |
1678 | reg mcu${mcu_no}_l2t1_secc_err_seen_20clk = 1'b0; | |
1679 | reg mcu${mcu_no}_l2t0_mecc_err_seen_20clk = 1'b0; | |
1680 | reg mcu${mcu_no}_l2t1_mecc_err_seen_20clk = 1'b0; | |
1681 | reg mcu${mcu_no}_l2t0_scb_secc_err_seen_20clk = 1'b0; | |
1682 | reg mcu${mcu_no}_l2t1_scb_secc_err_seen_20clk = 1'b0; | |
1683 | reg mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk = 1'b0; | |
1684 | reg mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk = 1'b0; | |
1685 | ||
1686 | reg mcu${mcu_no}_rdpctl_dac_error_20clk_seen = 1'b0; | |
1687 | reg mcu${mcu_no}_rdpctl_fbr_error_20clk_seen = 1'b0; | |
1688 | reg mcu${mcu_no}_rdpctl_dsc_error_20clk_seen = 1'b0; | |
1689 | reg mcu${mcu_no}_rdpctl_dac_error_50clk_seen = 1'b0; | |
1690 | reg mcu${mcu_no}_rdpctl_dau_error_50clk_seen = 1'b0; | |
1691 | reg mcu${mcu_no}_rdpctl_dsc_error_50clk_seen = 1'b0; | |
1692 | reg mcu${mcu_no}_rdpctl_fbr_error_50clk_seen = 1'b0; | |
1693 | reg mcu${mcu_no}_rdpctl_fbu_error_50clk_seen = 1'b0; | |
1694 | reg mcu${mcu_no}_rdpctl_dac_error_100clk_seen = 1'b0; | |
1695 | reg mcu${mcu_no}_rdpctl_dau_error_100clk_seen = 1'b0; | |
1696 | reg mcu${mcu_no}_rdpctl_dsc_error_100clk_seen = 1'b0; | |
1697 | reg mcu${mcu_no}_rdpctl_fbr_error_100clk_seen = 1'b0; | |
1698 | reg mcu${mcu_no}_rdpctl_fbu_error_100clk_seen = 1'b0; | |
1699 | ||
1700 | reg [4:0] mcu${mcu_no}_ESR_20clk = 'd0; | |
1701 | reg [5:0] mcu${mcu_no}_ESR_50clk = 'd0; | |
1702 | reg [7:0] mcu${mcu_no}_ESR_100clk = 'd0; | |
1703 | ||
1704 | ||
1705 | event l2_to_mcu${mcu_no}_error_10clk_trig; | |
1706 | event mcu${mcu_no}_to_l2_error_10clk_trig; | |
1707 | event mcu${mcu_no}_l2t0_scb_secc_err_count_trig; | |
1708 | event mcu${mcu_no}_l2t1_scb_secc_err_count_trig; | |
1709 | event mcu${mcu_no}_l2t0_secc_err_count_trig; | |
1710 | event mcu${mcu_no}_l2t1_secc_err_count_trig; | |
1711 | event mcu${mcu_no}_l2t0_secc_and_subsecc_trig; | |
1712 | event mcu${mcu_no}_l2t1_secc_and_subsecc_trig; | |
1713 | ||
1714 | event mcu${mcu_no}_l2t0_secc_mecc_trig; | |
1715 | event mcu${mcu_no}_l2t1_secc_mecc_trig; | |
1716 | event mcu${mcu_no}_l2t0_secc_scbmecc_trig; | |
1717 | event mcu${mcu_no}_l2t1_secc_scbmecc_trig; | |
1718 | event mcu${mcu_no}_l2t0_scbsecc_mecc_trig; | |
1719 | event mcu${mcu_no}_l2t1_scbsecc_mecc_trig; | |
1720 | ||
1721 | event mcu${mcu_no}_l2t0_mecc_err_seen_20clk_trig; | |
1722 | event mcu${mcu_no}_l2t1_mecc_err_seen_20clk_trig; | |
1723 | event mcu${mcu_no}_l2t0_mecc_scbmecc_trig; | |
1724 | event mcu${mcu_no}_l2t1_mecc_scbmecc_trig; | |
1725 | event mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_trig; | |
1726 | event mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_trig; | |
1727 | ||
1728 | event mcu${mcu_no}_rdpctl_dac_fbr_error_20clk_seen_trig; | |
1729 | event mcu${mcu_no}_rdpctl_dac_dsc_error_20clk_seen_trig; | |
1730 | event mcu${mcu_no}_rdpctl_dsc_fbr_error_20clk_seen_trig; | |
1731 | ||
1732 | event mcu${mcu_no}_rdpctl_dac_fbu_error_50clk_seen_trig; | |
1733 | event mcu${mcu_no}_rdpctl_dsc_fbu_error_50clk_seen_trig; | |
1734 | event mcu${mcu_no}_rdpctl_dac_dau_error_50clk_seen_trig; | |
1735 | event mcu${mcu_no}_rdpctl_dsc_dau_error_50clk_seen_trig; | |
1736 | event mcu${mcu_no}_rdpctl_dau_fbr_error_50clk_seen_trig; | |
1737 | event mcu${mcu_no}_rdpctl_dau_fbu_error_50clk_seen_trig; | |
1738 | ||
1739 | event mcu${mcu_no}_rdpctl_dac_dau_fbr_error_100clk_seen_trig; | |
1740 | event mcu${mcu_no}_rdpctl_dac_dau_fbu_error_100clk_seen_trig; | |
1741 | event mcu${mcu_no}_rdpctl_dac_fbr_fbu_error_100clk_seen_trig; | |
1742 | event mcu${mcu_no}_rdpctl_dac_dau_fbr_fbu_error_100clk_seen_trig; | |
1743 | ||
1744 | . } | |
1745 | ||
1746 | . for($mcu_no=0; $mcu_no<1; $mcu_no++) | |
1747 | . { | |
1748 | // ----------- coverage_group ----------------Table 7---------------------- | |
1749 | coverage_group l2_mcu${mcu_no}_err_signal_sameclk | |
1750 | { | |
1751 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1752 | sample_event = @(posedge l2_to_mcu${mcu_no}_ras_intf.clk); | |
1753 | sample l2_mcu${mcu_no}_err_signal_sameclk_sample (l2_to_mcu${mcu_no}_sameclk) | |
1754 | { | |
1755 | state S_l2_mcu${mcu_no}_err_signal_sameclk (1) ; | |
1756 | } | |
1757 | } | |
1758 | // ----------- coverage_group ----------------Table 7---------------------- | |
1759 | coverage_group l2_mcu${mcu_no}_err_signal_window | |
1760 | { | |
1761 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1762 | sample_event = sync (ALL, l2_to_mcu${mcu_no}_error_10clk_trig); | |
1763 | sample l2_mcu${mcu_no}_err_signal_window_sample (l2_to_mcu${mcu_no}_error_count) | |
1764 | { | |
1765 | state S_l2_mcu${mcu_no}_err_signal_window (0:10); | |
1766 | } | |
1767 | } | |
1768 | // ----------- coverage_group ----------------Table 7---------------------- | |
1769 | coverage_group l2_mcu${mcu_no}_err_signal_repeat | |
1770 | { | |
1771 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1772 | sample_event = sync (ALL, l2_to_mcu${mcu_no}_error_10clk_trig); | |
1773 | at_least = 10; | |
1774 | sample l2_mcu${mcu_no}_err_signal_repeat_sample (l2_to_mcu${mcu_no}_error_count) | |
1775 | { | |
1776 | state S_l2_mcu${mcu_no}_err_signal_repeat (0:10); | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | // ************************************************************************************************************************ | |
1781 | ||
1782 | // ----------- coverage_group ----------------Table 8---------------------- | |
1783 | coverage_group mcu${mcu_no}_l2_err_signal_window | |
1784 | { | |
1785 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1786 | sample_event = sync (ALL, mcu${mcu_no}_to_l2_error_10clk_trig); | |
1787 | sample mcu${mcu_no}_l2_err_signal_window_sample ({mcu${mcu_no}_to_l2t0_err_seen, mcu${mcu_no}_to_l2t1_err_seen}) | |
1788 | { | |
1789 | state S_mcu${mcu_no}_l2_err_signal_window (2'b11); | |
1790 | } | |
1791 | } | |
1792 | ||
1793 | // ----------- coverage_group ----------------Table 8---------------------- | |
1794 | coverage_group mcu${mcu_no}_l2t0_ce_ce_err_signal_window | |
1795 | { | |
1796 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1797 | sample_event = sync (ALL, mcu${mcu_no}_l2t0_secc_err_count_trig); | |
1798 | sample mcu${mcu_no}_l2t0_ce_ce_err_signal_window_sample (mcu${mcu_no}_l2t0_secc_err_count) | |
1799 | { | |
1800 | state S_mcu${mcu_no}_l2t0_ce_ce_err_signal_window (0:10); | |
1801 | } | |
1802 | } | |
1803 | ||
1804 | // ----------- coverage_group ----------------Table 8---------------------- | |
1805 | coverage_group mcu${mcu_no}_l2t1_ce_ce_err_signal_window | |
1806 | { | |
1807 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1808 | sample_event = sync (ALL, mcu${mcu_no}_l2t1_secc_err_count_trig); | |
1809 | sample mcu${mcu_no}_l2t1_ce_ce_err_signal_window_sample (mcu${mcu_no}_l2t1_secc_err_count) | |
1810 | { | |
1811 | state S_mcu${mcu_no}_l2t1_ce_ce_err_signal_window (0:10); | |
1812 | } | |
1813 | } | |
1814 | ||
1815 | // ----------- coverage_group ----------------Table 8---------------------- | |
1816 | coverage_group mcu${mcu_no}_l2t0_sce_sce_err_signal_window | |
1817 | { | |
1818 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1819 | sample_event = sync (ALL, mcu${mcu_no}_l2t0_scb_secc_err_count_trig); | |
1820 | sample mcu${mcu_no}_l2t0_sce_sce_err_signal_window_sample (mcu${mcu_no}_l2t0_scb_secc_err_count) | |
1821 | { | |
1822 | state S_mcu${mcu_no}_l2t0_sce_sce_err_signal_window (0:10); | |
1823 | } | |
1824 | } | |
1825 | ||
1826 | // ----------- coverage_group ----------------Table 8---------------------- | |
1827 | coverage_group mcu${mcu_no}_l2t1_sce_sce_err_signal_window | |
1828 | { | |
1829 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1830 | sample_event = sync (ALL, mcu${mcu_no}_l2t1_scb_secc_err_count_trig); | |
1831 | sample mcu${mcu_no}_l2t1_sce_sce_err_signal_window_sample (mcu${mcu_no}_l2t1_scb_secc_err_count) | |
1832 | { | |
1833 | state S_mcu${mcu_no}_l2t1_sce_sce_err_signal_window (0:10); | |
1834 | } | |
1835 | } | |
1836 | ||
1837 | // ----------- coverage_group ----------------Table 8---------------------- | |
1838 | coverage_group mcu${mcu_no}_l2t0_ce_sce_err_signal_window | |
1839 | { | |
1840 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1841 | sample_event = sync (ALL, mcu${mcu_no}_l2t0_secc_and_subsecc_trig); | |
1842 | sample mcu${mcu_no}_l2t0_ce_sce_err_signal_window_sample ({mcu${mcu_no}_l2t0_scb_secc_err_seen, mcu${mcu_no}_l2t0_secc_err_seen}) | |
1843 | { | |
1844 | state S_mcu${mcu_no}_l2t0_ce_sce_err_signal_window (2'b11); | |
1845 | } | |
1846 | } | |
1847 | ||
1848 | // ----------- coverage_group ----------------Table 8---------------------- | |
1849 | coverage_group mcu${mcu_no}_l2t1_ce_sce_err_signal_window | |
1850 | { | |
1851 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1852 | sample_event = sync (ALL, mcu${mcu_no}_l2t1_secc_and_subsecc_trig); | |
1853 | sample mcu${mcu_no}_l2t1_ce_sce_err_signal_window_sample ({mcu${mcu_no}_l2t1_scb_secc_err_seen, mcu${mcu_no}_l2t1_secc_err_seen}) | |
1854 | { | |
1855 | state S_mcu${mcu_no}_l2t1_ce_sce_err_signal_window (2'b11); | |
1856 | } | |
1857 | } | |
1858 | ||
1859 | // ----------- coverage_group ----------------Table 8---------------------- | |
1860 | coverage_group mcu${mcu_no}_l2t0_ue_ue_err_signal_window | |
1861 | { | |
1862 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1863 | sample_event = sync (ALL, mcu${mcu_no}_l2t0_mecc_err_seen_20clk_trig); | |
1864 | sample mcu${mcu_no}_l2t0_ue_ue_err_signal_window_sample (mcu${mcu_no}_l2t0_mecc_err_seen_20clk_count) | |
1865 | { | |
1866 | state S_mcu${mcu_no}_l2t0_ue_ue_err_signal_window (0:10); | |
1867 | } | |
1868 | } | |
1869 | ||
1870 | // ----------- coverage_group ----------------Table 8---------------------- | |
1871 | coverage_group mcu${mcu_no}_l2t1_ue_ue_err_signal_window | |
1872 | { | |
1873 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1874 | sample_event = sync (ALL, mcu${mcu_no}_l2t1_mecc_err_seen_20clk_trig); | |
1875 | sample mcu${mcu_no}_l2t1_ue_ue_err_signal_window_sample (mcu${mcu_no}_l2t1_mecc_err_seen_20clk_count) | |
1876 | { | |
1877 | state S_mcu${mcu_no}_l2t1_ue_ue_err_signal_window (0:10); | |
1878 | } | |
1879 | } | |
1880 | ||
1881 | // ----------- coverage_group ----------------Table 8---------------------- | |
1882 | coverage_group mcu${mcu_no}_l2t0_ue_sue_err_signal_window | |
1883 | { | |
1884 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1885 | sample_event = sync (ALL, mcu${mcu_no}_l2t0_mecc_scbmecc_trig); | |
1886 | sample mcu${mcu_no}_l2t0_ue_sue_err_signal_window_sample ({mcu${mcu_no}_l2t0_mecc_err_seen_20clk, mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk}) | |
1887 | { | |
1888 | state S_mcu${mcu_no}_l2t0_ue_sue_err_signal_window (2'b11); | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | // ----------- coverage_group ----------------Table 8---------------------- | |
1893 | coverage_group mcu${mcu_no}_l2t1_ue_sue_err_signal_window | |
1894 | { | |
1895 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1896 | sample_event = sync (ALL, mcu${mcu_no}_l2t1_mecc_scbmecc_trig); | |
1897 | sample mcu${mcu_no}_l2t1_ue_sue_err_signal_window_sample ({mcu${mcu_no}_l2t1_mecc_err_seen_20clk, mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk}) | |
1898 | { | |
1899 | state S_mcu${mcu_no}_l2t1_ue_sue_err_signal_window (2'b11); | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | // ----------- coverage_group ----------------Table 8---------------------- | |
1904 | coverage_group mcu${mcu_no}_l2t0_sue_sue_err_signal_window | |
1905 | { | |
1906 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1907 | sample_event = sync (ALL, mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_trig); | |
1908 | sample mcu${mcu_no}_l2t0_sue_sue_err_signal_window_sample (mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_count) | |
1909 | { | |
1910 | state S_mcu${mcu_no}_l2t0_sue_sue_err_signal_window (0:10); | |
1911 | } | |
1912 | } | |
1913 | ||
1914 | // ----------- coverage_group ----------------Table 8---------------------- | |
1915 | coverage_group mcu${mcu_no}_l2t1_sue_sue_err_signal_window | |
1916 | { | |
1917 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1918 | sample_event = sync (ALL, mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_trig); | |
1919 | sample mcu${mcu_no}_l2t1_sue_sue_err_signal_window_sample (mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_count) | |
1920 | { | |
1921 | state S_mcu${mcu_no}_l2t1_sue_sue_err_signal_window (0:10); | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | // ************************************************************************************************************************ | |
1926 | ||
1927 | // ----------- coverage_group ----------------Table 10---------------------- | |
1928 | coverage_group mcu${mcu_no}_err_fbd_synd_type | |
1929 | { | |
1930 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1931 | sample_event = @(negedge mcu${mcu_no}_FBD_Error_Synd_intf.clk); | |
1932 | sample mcu${mcu_no}_err_fbd_sync_type_sample ({mcu${mcu_no}_FBD_Error_Synd_intf.fbr_error, | |
1933 | mcu${mcu_no}_FBD_Error_Synd_intf.fbu_error, | |
1934 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_valid, | |
1935 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_aa, | |
1936 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_c, | |
1937 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_sfpe, | |
1938 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_afe | |
1939 | }) | |
1940 | { | |
1941 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbr_aa (7'b1x11xxx); | |
1942 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbr_c (7'b1x1x1xx); | |
1943 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbr_sfpe (7'b1x1xx1x); | |
1944 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbr_afe (7'b1x1xxx1); | |
1945 | ||
1946 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbu_aa (7'bx111xxx); | |
1947 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbu_c (7'bx11x1xx); | |
1948 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbu_sfpe (7'bx11xx1x); | |
1949 | wildcard state S_mcu${mcu_no}_err_fbd_sync_type_fbu_afe (7'bx11xxx1); | |
1950 | } | |
1951 | } | |
1952 | ||
1953 | // ************************************************************************************************************************ | |
1954 | ||
1955 | // ----------- coverage_group ----------------Table 11---------------------- | |
1956 | coverage_group mcu${mcu_no}_err_fbr_mult | |
1957 | { | |
1958 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1959 | sample_event = @(negedge mcu${mcu_no}_FBD_Error_Synd_intf.clk); | |
1960 | sample mcu${mcu_no}_err_fbr_mult_sample ({mcu${mcu_no}_FBD_Error_Synd_intf.fbr_error, | |
1961 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_valid, | |
1962 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_aa, | |
1963 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_c, | |
1964 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_sfpe, | |
1965 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_afe | |
1966 | }) | |
1967 | { | |
1968 | wildcard state S_mcu${mcu_no}_err_fbr_mult_aa_c (6'b1111xx); | |
1969 | wildcard state S_mcu${mcu_no}_err_fbr_mult_aa_sfpe (6'b111x1x); | |
1970 | wildcard state S_mcu${mcu_no}_err_fbr_mult_aa_c_sfpe (6'b11111x); | |
1971 | } | |
1972 | } | |
1973 | ||
1974 | // ----------- coverage_group ----------------Table 11---------------------- | |
1975 | coverage_group mcu${mcu_no}_err_fbu_mult | |
1976 | { | |
1977 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1978 | sample_event = @(negedge mcu${mcu_no}_FBD_Error_Synd_intf.clk); | |
1979 | sample mcu${mcu_no}_err_fbu_mult_sample ({mcu${mcu_no}_FBD_Error_Synd_intf.fbu_error, | |
1980 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_valid, | |
1981 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_aa, | |
1982 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_c, | |
1983 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_sfpe, | |
1984 | mcu${mcu_no}_FBD_Error_Synd_intf.fbdic_mcu_synd_afe | |
1985 | }) | |
1986 | { | |
1987 | wildcard state S_mcu${mcu_no}_err_fbu_mult_aa_c (6'b1111xx); | |
1988 | wildcard state S_mcu${mcu_no}_err_fbu_mult_aa_sfpe (6'b111x1x); | |
1989 | wildcard state S_mcu${mcu_no}_err_fbu_mult_aa_c_sfpe (6'b11111x); | |
1990 | } | |
1991 | } | |
1992 | ||
1993 | // ************************************************************************************************************************ | |
1994 | ||
1995 | // ----------- coverage_group ----------------Table 12---------------------- | |
1996 | coverage_group mcu${mcu_no}_err_fbd_mult | |
1997 | { | |
1998 | const_sample_reference = 1; // ref. to sample vars. is constant | |
1999 | sample_event = sync (ANY, mcu${mcu_no}_rdpctl_dac_fbr_error_20clk_seen_trig, mcu${mcu_no}_rdpctl_dac_dsc_error_20clk_seen_trig, mcu${mcu_no}_rdpctl_dsc_fbr_error_20clk_seen_trig); | |
2000 | sample mcu${mcu_no}_err_fbd_mult_sample ({mcu${mcu_no}_rdpctl_dac_error_20clk_seen, | |
2001 | mcu${mcu_no}_rdpctl_fbr_error_20clk_seen, | |
2002 | mcu${mcu_no}_rdpctl_dsc_error_20clk_seen | |
2003 | }) | |
2004 | { | |
2005 | wildcard state S_mcu${mcu_no}_err_fbd_mult_dac_fbr (3'b11x); | |
2006 | wildcard state S_mcu${mcu_no}_err_fbd_mult_dac_dsc (3'b1x1); | |
2007 | wildcard state S_mcu${mcu_no}_err_fbd_mult_dsc_fbr (3'bx11); | |
2008 | } | |
2009 | } | |
2010 | ||
2011 | // ----------- coverage_group ----------------Table 12---------------------- | |
2012 | coverage_group mcu${mcu_no}_err_fbd_mult_repeat | |
2013 | { | |
2014 | const_sample_reference = 1; // ref. to sample vars. is constant | |
2015 | sample_event = sync (ANY, mcu${mcu_no}_rdpctl_dac_fbr_error_20clk_seen_trig, mcu${mcu_no}_rdpctl_dac_dsc_error_20clk_seen_trig, mcu${mcu_no}_rdpctl_dsc_fbr_error_20clk_seen_trig); | |
2016 | at_least = 10; | |
2017 | sample mcu${mcu_no}_err_fbd_mult_repeat_sample ({mcu${mcu_no}_rdpctl_dac_error_20clk_seen, | |
2018 | mcu${mcu_no}_rdpctl_fbr_error_20clk_seen, | |
2019 | mcu${mcu_no}_rdpctl_dsc_error_20clk_seen | |
2020 | }) | |
2021 | { | |
2022 | wildcard state S_mcu${mcu_no}_err_fbd_mult_repeat_dac_fbr (3'b11x); | |
2023 | wildcard state S_mcu${mcu_no}_err_fbd_mult_repeat_dac_dsc (3'b1x1); | |
2024 | wildcard state S_mcu${mcu_no}_err_fbd_mult_repeat_dsc_fbr (3'bx11); | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | // ----------- coverage_group ----------------Table 12---------------------- | |
2029 | coverage_group mcu${mcu_no}_err_fbd_mult2 | |
2030 | { | |
2031 | const_sample_reference = 1; // ref. to sample vars. is constant | |
2032 | sample_event = sync (ANY, mcu${mcu_no}_rdpctl_dac_fbu_error_50clk_seen_trig, | |
2033 | mcu${mcu_no}_rdpctl_dsc_fbu_error_50clk_seen_trig, | |
2034 | mcu${mcu_no}_rdpctl_dac_dau_error_50clk_seen_trig, | |
2035 | mcu${mcu_no}_rdpctl_dsc_dau_error_50clk_seen_trig, | |
2036 | mcu${mcu_no}_rdpctl_dau_fbr_error_50clk_seen_trig, | |
2037 | mcu${mcu_no}_rdpctl_dau_fbu_error_50clk_seen_trig); | |
2038 | sample mcu${mcu_no}_err_fbd_mult2_sample ({mcu${mcu_no}_rdpctl_dac_error_50clk_seen, | |
2039 | mcu${mcu_no}_rdpctl_dau_error_50clk_seen, | |
2040 | mcu${mcu_no}_rdpctl_dsc_error_50clk_seen, | |
2041 | mcu${mcu_no}_rdpctl_fbr_error_50clk_seen, | |
2042 | mcu${mcu_no}_rdpctl_fbu_error_50clk_seen | |
2043 | }) | |
2044 | { | |
2045 | wildcard state S_mcu${mcu_no}_err_fbd_mult2_dac_fbu (5'b1xxx1); | |
2046 | wildcard state S_mcu${mcu_no}_err_fbd_mult2_dsc_fbu (5'bxx1x1); | |
2047 | wildcard state S_mcu${mcu_no}_err_fbd_mult2_dac_dau (5'b11xxx); | |
2048 | wildcard state S_mcu${mcu_no}_err_fbd_mult2_dsc_dau (5'bx11xx); | |
2049 | wildcard state S_mcu${mcu_no}_err_fbd_mult2_dau_fbr (5'bx1x1x); | |
2050 | wildcard state S_mcu${mcu_no}_err_fbd_mult2_dau_fbu (5'bx1xx1); | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | // ----------- coverage_group ----------------Table 12---------------------- | |
2055 | coverage_group mcu${mcu_no}_err_fbd_mult3 | |
2056 | { | |
2057 | const_sample_reference = 1; // ref. to sample vars. is constant | |
2058 | sample_event = sync (ANY, mcu${mcu_no}_rdpctl_dac_dau_fbr_error_100clk_seen_trig, | |
2059 | mcu${mcu_no}_rdpctl_dac_dau_fbu_error_100clk_seen_trig, | |
2060 | mcu${mcu_no}_rdpctl_dac_fbr_fbu_error_100clk_seen_trig, | |
2061 | mcu${mcu_no}_rdpctl_dac_dau_fbr_fbu_error_100clk_seen_trig); | |
2062 | sample mcu${mcu_no}_err_fbd_mult3_sample ({mcu${mcu_no}_rdpctl_dac_error_100clk_seen, | |
2063 | mcu${mcu_no}_rdpctl_dau_error_100clk_seen, | |
2064 | mcu${mcu_no}_rdpctl_dsc_error_100clk_seen, | |
2065 | mcu${mcu_no}_rdpctl_fbr_error_100clk_seen, | |
2066 | mcu${mcu_no}_rdpctl_fbu_error_100clk_seen | |
2067 | }) | |
2068 | { | |
2069 | wildcard state S_mcu${mcu_no}_err_fbd_mult3_dac_dau_fbr (5'b11x1x); | |
2070 | wildcard state S_mcu${mcu_no}_err_fbd_mult3_dac_dau_fbu (5'b11xx1); | |
2071 | wildcard state S_mcu${mcu_no}_err_fbd_mult3_dac_fbr_fbu (5'b1xx11); | |
2072 | wildcard state S_mcu${mcu_no}_err_fbd_mult3_dac_dau_fbr_fbu (5'b11x11); | |
2073 | } | |
2074 | } | |
2075 | ||
2076 | ||
2077 | ||
2078 | . } | |
2079 | ||
2080 | // MAQ task new(StandardDisplay dbg); | |
2081 | task new(); | |
2082 | task set_cov_cond_bits (); | |
2083 | . for($mcu_no=0; $mcu_no<1; $mcu_no++) | |
2084 | . { | |
2085 | task mcu${mcu_no}_ras_table7(); | |
2086 | task mcu${mcu_no}_ras_table8(); | |
2087 | task mcu${mcu_no}_ras_table12(); | |
2088 | . } | |
2089 | ||
2090 | } //class fc_mcu_ras_coverage | |
2091 | ||
2092 | ///////////////////////////////////////////////////////////////// | |
2093 | // Class creation | |
2094 | ///////////////////////////////////////////////////////////////// | |
2095 | // MAQ task fc_mcu_ras_coverage::new(StandardDisplay dbg) | |
2096 | task fc_mcu_ras_coverage::new() | |
2097 | { | |
2098 | bit coverage_on = 0; | |
2099 | integer j; | |
2100 | ||
2101 | // for dispmon | |
2102 | // MAQ myname = "fc_mcu_ras_coverage"; | |
2103 | // MAQ this.dbg = dbg; | |
2104 | ||
2105 | if (mChkPlusarg(fc_mcu_ras_coverage) || mChkPlusarg(coverage_on)) { | |
2106 | coverage_on = 1; | |
2107 | } | |
2108 | ||
2109 | if (coverage_on) { | |
2110 | // MAQ dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :MCU RAS Coverage Turned ON\n\n", get_time(LO))); | |
2111 | ||
2112 | . for($mcu_no=0; $mcu_no<1; $mcu_no++) | |
2113 | . { | |
2114 | l2_mcu${mcu_no}_err_signal_sameclk = new(); | |
2115 | l2_mcu${mcu_no}_err_signal_window = new(); | |
2116 | l2_mcu${mcu_no}_err_signal_repeat = new(); | |
2117 | ||
2118 | mcu${mcu_no}_l2_err_signal_window = new(); | |
2119 | mcu${mcu_no}_l2t0_ce_ce_err_signal_window = new(); | |
2120 | mcu${mcu_no}_l2t1_ce_ce_err_signal_window = new(); | |
2121 | mcu${mcu_no}_l2t0_sce_sce_err_signal_window = new(); | |
2122 | mcu${mcu_no}_l2t1_sce_sce_err_signal_window = new(); | |
2123 | mcu${mcu_no}_l2t0_ce_sce_err_signal_window = new(); | |
2124 | mcu${mcu_no}_l2t1_ce_sce_err_signal_window = new(); | |
2125 | mcu${mcu_no}_l2t0_ue_ue_err_signal_window = new(); | |
2126 | mcu${mcu_no}_l2t1_ue_ue_err_signal_window = new(); | |
2127 | mcu${mcu_no}_l2t0_ue_sue_err_signal_window = new(); | |
2128 | mcu${mcu_no}_l2t1_ue_sue_err_signal_window = new(); | |
2129 | mcu${mcu_no}_l2t0_sue_sue_err_signal_window = new(); | |
2130 | mcu${mcu_no}_l2t1_sue_sue_err_signal_window = new(); | |
2131 | ||
2132 | mcu${mcu_no}_err_fbd_synd_type = new(); | |
2133 | mcu${mcu_no}_err_fbr_mult = new(); | |
2134 | mcu${mcu_no}_err_fbu_mult = new(); | |
2135 | ||
2136 | mcu${mcu_no}_err_fbd_mult = new(); | |
2137 | mcu${mcu_no}_err_fbd_mult_repeat = new(); | |
2138 | mcu${mcu_no}_err_fbd_mult2 = new(); | |
2139 | mcu${mcu_no}_err_fbd_mult3 = new(); | |
2140 | .} | |
2141 | ||
2142 | set_cov_cond_bits (); | |
2143 | ||
2144 | } // if coverage_on | |
2145 | } // fc_mcu_ras_coverage::new() | |
2146 | ||
2147 | ////////////////////////////////////////////////////////////////////////// | |
2148 | ||
2149 | task fc_mcu_ras_coverage:: set_cov_cond_bits () | |
2150 | { | |
2151 | ||
2152 | fork | |
2153 | . for($mcu_no=0; $mcu_no<1; $mcu_no++) | |
2154 | . { | |
2155 | mcu${mcu_no}_ras_table7(); | |
2156 | mcu${mcu_no}_ras_table8(); | |
2157 | mcu${mcu_no}_ras_table12(); | |
2158 | .} | |
2159 | ||
2160 | join none | |
2161 | ||
2162 | } // task fc_mcu_ras_coverage:: set_cov_cond_bits | |
2163 | ||
2164 | ||
2165 | . for($mcu_no=0; $mcu_no<1; $mcu_no++) | |
2166 | . { | |
2167 | task fc_mcu_ras_coverage:: mcu${mcu_no}_ras_table7() | |
2168 | { | |
2169 | ||
2170 | while(1) | |
2171 | { | |
2172 | @(negedge l2_to_mcu${mcu_no}_ras_intf.clk); | |
2173 | { | |
2174 | l2_to_mcu${mcu_no}_sameclk = (l2_to_mcu${mcu_no}_ras_intf.l2b0_mcu_data_mecc_r5 && l2_to_mcu${mcu_no}_ras_intf.l2b1_mcu_data_mecc_r5); | |
2175 | l2_to_mcu${mcu_no}_error = (l2_to_mcu${mcu_no}_ras_intf.l2b0_mcu_data_mecc_r5 || l2_to_mcu${mcu_no}_ras_intf.l2b1_mcu_data_mecc_r5); | |
2176 | ||
2177 | if(l2_to_mcu${mcu_no}_error_10clk == 'd10) | |
2178 | { | |
2179 | l2_to_mcu${mcu_no}_error_10clk = 'd0; | |
2180 | if(l2_to_mcu${mcu_no}_error_count > 'd1) | |
2181 | trigger(l2_to_mcu${mcu_no}_error_10clk_trig); | |
2182 | l2_to_mcu${mcu_no}_error_count = 1'b0; | |
2183 | } | |
2184 | else | |
2185 | { | |
2186 | if(l2_to_mcu${mcu_no}_error == 1'b1) | |
2187 | { | |
2188 | // MAQ printf ("\n %d :Error_count Inside = %d, \n\n", get_time(LO), l2_to_mcu${mcu_no}_error_count ); | |
2189 | l2_to_mcu${mcu_no}_error_count = l2_to_mcu${mcu_no}_error_count + 'd1; | |
2190 | } | |
2191 | l2_to_mcu${mcu_no}_error_10clk = l2_to_mcu${mcu_no}_error_10clk + 'd1; | |
2192 | } | |
2193 | ||
2194 | } | |
2195 | ||
2196 | ||
2197 | } | |
2198 | } // task fc_mcu_ras_coverage:: mcu${mcu_no}_ras_table7() | |
2199 | ||
2200 | task fc_mcu_ras_coverage:: mcu${mcu_no}_ras_table8() | |
2201 | { | |
2202 | while(1) | |
2203 | { | |
2204 | @(negedge mcu${mcu_no}_to_l2_ras_intf.clk); | |
2205 | { | |
2206 | mcu${mcu_no}_to_l2t0_err = (mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_scb_mecc_err || | |
2207 | mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_scb_secc_err || | |
2208 | mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_mecc_err_r3 || | |
2209 | mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_secc_err_r3 ); | |
2210 | ||
2211 | mcu${mcu_no}_to_l2t1_err = (mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_scb_mecc_err || | |
2212 | mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_scb_secc_err || | |
2213 | mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_mecc_err_r3 || | |
2214 | mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_secc_err_r3 ); | |
2215 | ||
2216 | if(mcu${mcu_no}_to_l2_error_10clk == 'd10) | |
2217 | { | |
2218 | mcu${mcu_no}_to_l2_error_10clk = 'd0; | |
2219 | if((mcu${mcu_no}_to_l2t0_err_seen == 1'b1) && (mcu${mcu_no}_to_l2t1_err_seen == 1'b1)) | |
2220 | trigger(mcu${mcu_no}_to_l2_error_10clk_trig); | |
2221 | ||
2222 | if(mcu${mcu_no}_l2t0_scb_secc_err_count > 'd1) | |
2223 | trigger(mcu${mcu_no}_l2t0_scb_secc_err_count_trig); | |
2224 | if(mcu${mcu_no}_l2t1_scb_secc_err_count > 'd1) | |
2225 | trigger(mcu${mcu_no}_l2t1_scb_secc_err_count_trig); | |
2226 | ||
2227 | if(mcu${mcu_no}_l2t0_secc_err_count > 'd1) | |
2228 | trigger(mcu${mcu_no}_l2t0_secc_err_count_trig); | |
2229 | if(mcu${mcu_no}_l2t1_secc_err_count > 'd1) | |
2230 | trigger(mcu${mcu_no}_l2t1_secc_err_count_trig); | |
2231 | ||
2232 | if((mcu${mcu_no}_l2t0_scb_secc_err_seen == 1'b1) && (mcu${mcu_no}_l2t0_secc_err_seen == 1'b1)) | |
2233 | trigger(mcu${mcu_no}_l2t0_secc_and_subsecc_trig); | |
2234 | ||
2235 | if((mcu${mcu_no}_l2t1_scb_secc_err_seen == 1'b1) && (mcu${mcu_no}_l2t1_secc_err_seen == 1'b1)) | |
2236 | trigger(mcu${mcu_no}_l2t1_secc_and_subsecc_trig); | |
2237 | ||
2238 | } | |
2239 | else if(mcu${mcu_no}_to_l2_error_10clk == 'd1) | |
2240 | { | |
2241 | mcu${mcu_no}_to_l2t0_err_seen = 1'b0; | |
2242 | mcu${mcu_no}_to_l2t1_err_seen = 1'b0; | |
2243 | ||
2244 | mcu${mcu_no}_l2t0_scb_secc_err_count = 'd0; | |
2245 | mcu${mcu_no}_l2t1_scb_secc_err_count = 'd0; | |
2246 | ||
2247 | mcu${mcu_no}_l2t0_secc_err_count = 'd0; | |
2248 | mcu${mcu_no}_l2t1_secc_err_count = 'd0; | |
2249 | ||
2250 | mcu${mcu_no}_l2t0_scb_secc_err_seen = 1'b0; | |
2251 | mcu${mcu_no}_l2t1_scb_secc_err_seen = 1'b0; | |
2252 | mcu${mcu_no}_l2t0_secc_err_seen = 1'b0; | |
2253 | mcu${mcu_no}_l2t1_secc_err_seen = 1'b0; | |
2254 | ||
2255 | mcu${mcu_no}_to_l2_error_10clk = mcu${mcu_no}_to_l2_error_10clk + 'd1; | |
2256 | } | |
2257 | else | |
2258 | { | |
2259 | if(mcu${mcu_no}_to_l2t0_err == 1'b1) | |
2260 | mcu${mcu_no}_to_l2t0_err_seen = 1'b1; | |
2261 | if(mcu${mcu_no}_to_l2t1_err == 1'b1) | |
2262 | mcu${mcu_no}_to_l2t1_err_seen = 1'b1; | |
2263 | ||
2264 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_scb_secc_err) | |
2265 | { | |
2266 | mcu${mcu_no}_l2t0_scb_secc_err_seen = 1'b1; | |
2267 | mcu${mcu_no}_l2t0_scb_secc_err_count = mcu${mcu_no}_l2t0_scb_secc_err_count + 'd1; | |
2268 | } | |
2269 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_scb_secc_err) | |
2270 | { | |
2271 | mcu${mcu_no}_l2t1_scb_secc_err_seen = 1'b1; | |
2272 | mcu${mcu_no}_l2t1_scb_secc_err_count = mcu${mcu_no}_l2t1_scb_secc_err_count + 'd1; | |
2273 | } | |
2274 | ||
2275 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_secc_err_r3) | |
2276 | { | |
2277 | mcu${mcu_no}_l2t0_secc_err_seen = 1'b1; | |
2278 | mcu${mcu_no}_l2t0_secc_err_count = mcu${mcu_no}_l2t0_secc_err_count + 'd1; | |
2279 | } | |
2280 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_secc_err_r3) | |
2281 | { | |
2282 | mcu${mcu_no}_l2t1_secc_err_seen = 1'b1; | |
2283 | mcu${mcu_no}_l2t1_secc_err_count = mcu${mcu_no}_l2t1_secc_err_count + 'd1; | |
2284 | } | |
2285 | ||
2286 | ||
2287 | mcu${mcu_no}_to_l2_error_10clk = mcu${mcu_no}_to_l2_error_10clk + 'd1; | |
2288 | } | |
2289 | ||
2290 | // *********************************************************************************************************************** | |
2291 | if(mcu${mcu_no}_to_l2_error_20clk == 'd20) | |
2292 | { | |
2293 | mcu${mcu_no}_to_l2_error_20clk = 'd0; | |
2294 | ||
2295 | if((mcu${mcu_no}_l2t0_secc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t0_mecc_err_seen_20clk == 1'b1)) | |
2296 | trigger(mcu${mcu_no}_l2t0_secc_mecc_trig); | |
2297 | if((mcu${mcu_no}_l2t1_secc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t1_mecc_err_seen_20clk == 1'b1)) | |
2298 | trigger(mcu${mcu_no}_l2t1_secc_mecc_trig); | |
2299 | ||
2300 | if((mcu${mcu_no}_l2t0_secc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk == 1'b1)) | |
2301 | trigger(mcu${mcu_no}_l2t0_secc_scbmecc_trig); | |
2302 | if((mcu${mcu_no}_l2t1_secc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk == 1'b1)) | |
2303 | trigger(mcu${mcu_no}_l2t1_secc_scbmecc_trig); | |
2304 | ||
2305 | if((mcu${mcu_no}_l2t0_scb_secc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t0_mecc_err_seen_20clk == 1'b1)) | |
2306 | trigger(mcu${mcu_no}_l2t0_scbsecc_mecc_trig); | |
2307 | if((mcu${mcu_no}_l2t1_scb_secc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t1_mecc_err_seen_20clk == 1'b1)) | |
2308 | trigger(mcu${mcu_no}_l2t1_scbsecc_mecc_trig); | |
2309 | ||
2310 | // ******************************************************************************************************* | |
2311 | ||
2312 | if(mcu${mcu_no}_l2t0_mecc_err_seen_20clk_count > 'd1) | |
2313 | trigger(mcu${mcu_no}_l2t0_mecc_err_seen_20clk_trig); | |
2314 | if(mcu${mcu_no}_l2t1_mecc_err_seen_20clk_count > 'd1) | |
2315 | trigger(mcu${mcu_no}_l2t1_mecc_err_seen_20clk_trig); | |
2316 | ||
2317 | if((mcu${mcu_no}_l2t0_mecc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk == 1'b1)) | |
2318 | trigger(mcu${mcu_no}_l2t0_mecc_scbmecc_trig); | |
2319 | if((mcu${mcu_no}_l2t1_mecc_err_seen_20clk == 1'b1) && (mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk == 1'b1)) | |
2320 | trigger(mcu${mcu_no}_l2t1_mecc_scbmecc_trig); | |
2321 | ||
2322 | if(mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_count > 'd1) | |
2323 | trigger(mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_trig); | |
2324 | if(mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_count > 'd1) | |
2325 | trigger(mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_trig); | |
2326 | ||
2327 | } | |
2328 | else if(mcu${mcu_no}_to_l2_error_20clk == 'd1) | |
2329 | { | |
2330 | mcu${mcu_no}_l2t0_secc_err_seen_20clk = 1'b0; | |
2331 | mcu${mcu_no}_l2t1_secc_err_seen_20clk = 1'b0; | |
2332 | mcu${mcu_no}_l2t0_mecc_err_seen_20clk = 1'b0; | |
2333 | mcu${mcu_no}_l2t1_mecc_err_seen_20clk = 1'b0; | |
2334 | mcu${mcu_no}_l2t0_scb_secc_err_seen_20clk = 1'b0; | |
2335 | mcu${mcu_no}_l2t1_scb_secc_err_seen_20clk = 1'b0; | |
2336 | mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk = 1'b0; | |
2337 | mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk = 1'b0; | |
2338 | mcu${mcu_no}_l2t0_mecc_err_seen_20clk_count = 'd0; | |
2339 | mcu${mcu_no}_l2t1_mecc_err_seen_20clk_count = 'd0; | |
2340 | mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_count = 'd0; | |
2341 | mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_count = 'd0; | |
2342 | ||
2343 | mcu${mcu_no}_to_l2_error_20clk = mcu${mcu_no}_to_l2_error_20clk + 'd1; | |
2344 | } | |
2345 | else | |
2346 | { | |
2347 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_secc_err_r3) | |
2348 | mcu${mcu_no}_l2t0_secc_err_seen_20clk = 1'b1; | |
2349 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_secc_err_r3) | |
2350 | mcu${mcu_no}_l2t1_secc_err_seen_20clk = 1'b1; | |
2351 | ||
2352 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_mecc_err_r3) | |
2353 | { | |
2354 | mcu${mcu_no}_l2t0_mecc_err_seen_20clk = 1'b1; | |
2355 | mcu${mcu_no}_l2t0_mecc_err_seen_20clk_count = mcu${mcu_no}_l2t0_mecc_err_seen_20clk_count + 'd1; | |
2356 | } | |
2357 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_mecc_err_r3) | |
2358 | { | |
2359 | mcu${mcu_no}_l2t1_mecc_err_seen_20clk = 1'b1; | |
2360 | mcu${mcu_no}_l2t1_mecc_err_seen_20clk_count = mcu${mcu_no}_l2t1_mecc_err_seen_20clk_count + 'd1; | |
2361 | } | |
2362 | ||
2363 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_scb_secc_err) | |
2364 | mcu${mcu_no}_l2t0_scb_secc_err_seen_20clk = 1'b1; | |
2365 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_scb_secc_err) | |
2366 | mcu${mcu_no}_l2t1_scb_secc_err_seen_20clk = 1'b1; | |
2367 | ||
2368 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t0_scb_mecc_err) | |
2369 | { | |
2370 | mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk = 1'b1; | |
2371 | mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_count = mcu${mcu_no}_l2t0_scb_mecc_err_seen_20clk_count + 'd1; | |
2372 | } | |
2373 | if(mcu${mcu_no}_to_l2_ras_intf.mcu_l2t1_scb_mecc_err) | |
2374 | { | |
2375 | mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk = 1'b1; | |
2376 | mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_count = mcu${mcu_no}_l2t1_scb_mecc_err_seen_20clk_count + 'd1; | |
2377 | } | |
2378 | ||
2379 | mcu${mcu_no}_to_l2_error_20clk = mcu${mcu_no}_to_l2_error_20clk + 'd1; | |
2380 | } | |
2381 | ||
2382 | ||
2383 | } | |
2384 | } | |
2385 | ||
2386 | } // task fc_mcu_ras_coverage:: mcu${mcu_no}_ras_table8() | |
2387 | ||
2388 | task fc_mcu_ras_coverage:: mcu${mcu_no}_ras_table12() | |
2389 | { | |
2390 | while(1) | |
2391 | { | |
2392 | @(negedge mcu${mcu_no}_ESR_intf.clk); | |
2393 | { | |
2394 | if(mcu${mcu_no}_ESR_20clk == 'd20) | |
2395 | { | |
2396 | mcu${mcu_no}_ESR_20clk = 'd0; | |
2397 | ||
2398 | if((mcu${mcu_no}_rdpctl_dac_error_20clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbr_error_20clk_seen == 1'b1)) | |
2399 | trigger(mcu${mcu_no}_rdpctl_dac_fbr_error_20clk_seen_trig); | |
2400 | if((mcu${mcu_no}_rdpctl_dac_error_20clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_dsc_error_20clk_seen == 1'b1)) | |
2401 | trigger(mcu${mcu_no}_rdpctl_dac_dsc_error_20clk_seen_trig); | |
2402 | if((mcu${mcu_no}_rdpctl_dsc_error_20clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbr_error_20clk_seen == 1'b1)) | |
2403 | trigger(mcu${mcu_no}_rdpctl_dsc_fbr_error_20clk_seen_trig); | |
2404 | } | |
2405 | else if(mcu${mcu_no}_ESR_20clk == 'd1) | |
2406 | { | |
2407 | mcu${mcu_no}_rdpctl_dac_error_20clk_seen = 1'b0; | |
2408 | mcu${mcu_no}_rdpctl_fbr_error_20clk_seen = 1'b0; | |
2409 | mcu${mcu_no}_rdpctl_dsc_error_20clk_seen = 1'b0; | |
2410 | ||
2411 | mcu${mcu_no}_ESR_20clk = mcu${mcu_no}_ESR_20clk + 'd1; | |
2412 | } | |
2413 | else | |
2414 | { | |
2415 | if(mcu${mcu_no}_ESR_intf.rdpctl_dac_error) | |
2416 | mcu${mcu_no}_rdpctl_dac_error_20clk_seen = 1'b1; | |
2417 | if(mcu${mcu_no}_ESR_intf.rdpctl_fbr_error) | |
2418 | mcu${mcu_no}_rdpctl_fbr_error_20clk_seen = 1'b1; | |
2419 | if(mcu${mcu_no}_ESR_intf.rdpctl_dsc_error) | |
2420 | mcu${mcu_no}_rdpctl_dsc_error_20clk_seen = 1'b1; | |
2421 | ||
2422 | mcu${mcu_no}_ESR_20clk = mcu${mcu_no}_ESR_20clk + 'd1; | |
2423 | } | |
2424 | ||
2425 | // *********************************************************************************************************************** | |
2426 | if(mcu${mcu_no}_ESR_50clk == 'd50) | |
2427 | { | |
2428 | mcu${mcu_no}_ESR_50clk = 'd0; | |
2429 | if((mcu${mcu_no}_rdpctl_dac_error_50clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbu_error_50clk_seen == 1'b1)) | |
2430 | trigger(mcu${mcu_no}_rdpctl_dac_fbu_error_50clk_seen_trig); | |
2431 | if((mcu${mcu_no}_rdpctl_dsc_error_50clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbu_error_50clk_seen == 1'b1)) | |
2432 | trigger(mcu${mcu_no}_rdpctl_dsc_fbu_error_50clk_seen_trig); | |
2433 | if((mcu${mcu_no}_rdpctl_dac_error_50clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_dau_error_50clk_seen == 1'b1)) | |
2434 | trigger(mcu${mcu_no}_rdpctl_dac_dau_error_50clk_seen_trig); | |
2435 | if((mcu${mcu_no}_rdpctl_dsc_error_50clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_dau_error_50clk_seen == 1'b1)) | |
2436 | trigger(mcu${mcu_no}_rdpctl_dsc_dau_error_50clk_seen_trig); | |
2437 | if((mcu${mcu_no}_rdpctl_dau_error_50clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbr_error_50clk_seen == 1'b1)) | |
2438 | trigger(mcu${mcu_no}_rdpctl_dau_fbr_error_50clk_seen_trig); | |
2439 | if((mcu${mcu_no}_rdpctl_dau_error_50clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbu_error_50clk_seen == 1'b1)) | |
2440 | trigger(mcu${mcu_no}_rdpctl_dau_fbu_error_50clk_seen_trig); | |
2441 | ||
2442 | // printf("\n %d MAQ : mcu0_ESR_50clk : DAU = %b, FBR = %b, FBU = %b\n", get_time(LO), mcu${mcu_no}_rdpctl_dau_error_50clk_seen, mcu${mcu_no}_rdpctl_fbr_error_50clk_seen, mcu${mcu_no}_rdpctl_fbu_error_50clk_seen); | |
2443 | } | |
2444 | else if(mcu${mcu_no}_ESR_50clk == 'd1) | |
2445 | { | |
2446 | // printf("\n %d MAQ d1 : mcu0_ESR_50clk : DAU = %b, FBR = %b, FBU = %b\n", get_time(LO), mcu${mcu_no}_rdpctl_dau_error_50clk_seen, mcu${mcu_no}_rdpctl_fbr_error_50clk_seen, mcu${mcu_no}_rdpctl_fbu_error_50clk_seen); | |
2447 | ||
2448 | mcu${mcu_no}_rdpctl_dac_error_50clk_seen = 1'b0; | |
2449 | mcu${mcu_no}_rdpctl_dau_error_50clk_seen = 1'b0; | |
2450 | mcu${mcu_no}_rdpctl_dsc_error_50clk_seen = 1'b0; | |
2451 | mcu${mcu_no}_rdpctl_fbr_error_50clk_seen = 1'b0; | |
2452 | mcu${mcu_no}_rdpctl_fbu_error_50clk_seen = 1'b0; | |
2453 | ||
2454 | mcu${mcu_no}_ESR_50clk = mcu${mcu_no}_ESR_50clk + 'd1; | |
2455 | } | |
2456 | else | |
2457 | { | |
2458 | if(mcu${mcu_no}_ESR_intf.rdpctl_dac_error) | |
2459 | mcu${mcu_no}_rdpctl_dac_error_50clk_seen = 1'b1; | |
2460 | if(mcu${mcu_no}_ESR_intf.rdpctl_dau_error) | |
2461 | mcu${mcu_no}_rdpctl_dau_error_50clk_seen = 1'b1; | |
2462 | if(mcu${mcu_no}_ESR_intf.rdpctl_dsc_error) | |
2463 | mcu${mcu_no}_rdpctl_dsc_error_50clk_seen = 1'b1; | |
2464 | if(mcu${mcu_no}_ESR_intf.rdpctl_fbr_error) | |
2465 | mcu${mcu_no}_rdpctl_fbr_error_50clk_seen = 1'b1; | |
2466 | if(mcu${mcu_no}_ESR_intf.rdpctl_fbu_error) | |
2467 | mcu${mcu_no}_rdpctl_fbu_error_50clk_seen = 1'b1; | |
2468 | ||
2469 | mcu${mcu_no}_ESR_50clk = mcu${mcu_no}_ESR_50clk + 'd1; | |
2470 | } | |
2471 | // *********************************************************************************************************************** | |
2472 | if(mcu${mcu_no}_ESR_100clk == 'd100) | |
2473 | { | |
2474 | mcu${mcu_no}_ESR_100clk = 'd0; | |
2475 | ||
2476 | if((mcu${mcu_no}_rdpctl_dac_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_dau_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbr_error_100clk_seen == 1'b1)) | |
2477 | trigger(mcu${mcu_no}_rdpctl_dac_dau_fbr_error_100clk_seen_trig); | |
2478 | if((mcu${mcu_no}_rdpctl_dac_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_dau_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbu_error_100clk_seen == 1'b1)) | |
2479 | trigger(mcu${mcu_no}_rdpctl_dac_dau_fbu_error_100clk_seen_trig); | |
2480 | if((mcu${mcu_no}_rdpctl_dac_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbr_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbu_error_100clk_seen == 1'b1)) | |
2481 | trigger(mcu${mcu_no}_rdpctl_dac_fbr_fbu_error_100clk_seen_trig); | |
2482 | if((mcu${mcu_no}_rdpctl_dac_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_dau_error_100clk_seen == 1'b1) && | |
2483 | (mcu${mcu_no}_rdpctl_fbr_error_100clk_seen == 1'b1) && (mcu${mcu_no}_rdpctl_fbu_error_100clk_seen == 1'b1)) | |
2484 | trigger(mcu${mcu_no}_rdpctl_dac_dau_fbr_fbu_error_100clk_seen_trig); | |
2485 | } | |
2486 | else if(mcu${mcu_no}_ESR_100clk == 'd1) | |
2487 | { | |
2488 | ||
2489 | mcu${mcu_no}_rdpctl_dac_error_100clk_seen = 1'b0; | |
2490 | mcu${mcu_no}_rdpctl_dau_error_100clk_seen = 1'b0; | |
2491 | mcu${mcu_no}_rdpctl_dsc_error_100clk_seen = 1'b0; | |
2492 | mcu${mcu_no}_rdpctl_fbr_error_100clk_seen = 1'b0; | |
2493 | mcu${mcu_no}_rdpctl_fbu_error_100clk_seen = 1'b0; | |
2494 | ||
2495 | mcu${mcu_no}_ESR_100clk = mcu${mcu_no}_ESR_100clk + 'd1; | |
2496 | } | |
2497 | else | |
2498 | { | |
2499 | if(mcu${mcu_no}_ESR_intf.rdpctl_dac_error) | |
2500 | mcu${mcu_no}_rdpctl_dac_error_100clk_seen = 1'b1; | |
2501 | if(mcu${mcu_no}_ESR_intf.rdpctl_dau_error) | |
2502 | mcu${mcu_no}_rdpctl_dau_error_100clk_seen = 1'b1; | |
2503 | if(mcu${mcu_no}_ESR_intf.rdpctl_dsc_error) | |
2504 | mcu${mcu_no}_rdpctl_dsc_error_100clk_seen = 1'b1; | |
2505 | if(mcu${mcu_no}_ESR_intf.rdpctl_fbr_error) | |
2506 | mcu${mcu_no}_rdpctl_fbr_error_100clk_seen = 1'b1; | |
2507 | if(mcu${mcu_no}_ESR_intf.rdpctl_fbu_error) | |
2508 | mcu${mcu_no}_rdpctl_fbu_error_100clk_seen = 1'b1; | |
2509 | ||
2510 | mcu${mcu_no}_ESR_100clk = mcu${mcu_no}_ESR_100clk + 'd1; | |
2511 | } | |
2512 | } // @ | |
2513 | } // while | |
2514 | } // task fc_mcu_ras_coverage:: mcu${mcu_no}_ras_table12() | |
2515 | ||
2516 | . } | |
2517 | // ******************************************************************************************* |