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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / mcusat / mcusat_rd_que_sample.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcusat_rd_que_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35 wildcard state s_RD_REQ_DEASSRT (RD_REQ_DEASSRT );
36 wildcard state s_RD_REQ_ASSRT (RD_REQ_ASSRT );
37 wildcard state s_RD_Q_WR_PTR_DEASSRT (RD_Q_WR_PTR_DEASSRT );
38 wildcard state s_RD_Q_WR_PTR_ASSRT0 (RD_Q_WR_PTR_ASSRT0 );
39 wildcard state s_RD_Q_WR_PTR_ASSRT1 (RD_Q_WR_PTR_ASSRT1 );
40 wildcard state s_RD_Q_WR_PTR_ASSRT2 (RD_Q_WR_PTR_ASSRT2 );
41 wildcard state s_RD_Q_WR_PTR_ASSRT3 (RD_Q_WR_PTR_ASSRT3 );
42 wildcard state s_RD_Q_WR_PTR_ASSRT4 (RD_Q_WR_PTR_ASSRT4 );
43 wildcard state s_RD_Q_WR_PTR_ASSRT5 (RD_Q_WR_PTR_ASSRT5 );
44 wildcard state s_RD_Q_WR_PTR_ASSRT6 (RD_Q_WR_PTR_ASSRT6 );
45 wildcard state s_RD_Q_WR_PTR_ASSRT7 (RD_Q_WR_PTR_ASSRT7 );
46 wildcard state s_RD_Q_RD_PTR_DEASSRT (RD_Q_RD_PTR_DEASSRT );
47 wildcard state s_RD_Q_RD_PTR_ASSRT0 (RD_Q_RD_PTR_ASSRT0 );
48 wildcard state s_RD_Q_RD_PTR_ASSRT1 (RD_Q_RD_PTR_ASSRT1 );
49 wildcard state s_RD_Q_RD_PTR_ASSRT2 (RD_Q_RD_PTR_ASSRT2 );
50 wildcard state s_RD_Q_RD_PTR_ASSRT3 (RD_Q_RD_PTR_ASSRT3 );
51 wildcard state s_RD_Q_RD_PTR_ASSRT4 (RD_Q_RD_PTR_ASSRT4 );
52 wildcard state s_RD_Q_RD_PTR_ASSRT5 (RD_Q_RD_PTR_ASSRT5 );
53 wildcard state s_RD_Q_RD_PTR_ASSRT6 (RD_Q_RD_PTR_ASSRT6 );
54 wildcard state s_RD_Q_RD_PTR_ASSRT7 (RD_Q_RD_PTR_ASSRT7 );
55 wildcard state s_RD_Q_CNT0 (RD_Q_CNT0 );
56 wildcard state s_RD_Q_CNT1 (RD_Q_CNT1 );
57 wildcard state s_RD_Q_CNT2 (RD_Q_CNT2 );
58 wildcard state s_RD_Q_CNT3 (RD_Q_CNT3 );
59 wildcard state s_RD_Q_CNT4 (RD_Q_CNT4 );
60 wildcard state s_RD_Q_CNT5 (RD_Q_CNT5 );
61 wildcard state s_RD_Q_CNT6 (RD_Q_CNT6 );
62 wildcard state s_RD_Q_CNT7 (RD_Q_CNT7 );
63 wildcard state s_RD_Q_CNT8 (RD_Q_CNT8 );
64 wildcard state s_RD_Q_NOT_FULL (RD_Q_NOT_FULL );
65 wildcard state s_RD_Q_FULL (RD_Q_FULL );
66 wildcard state s_RD_COLPS_FIFO_CNT0 (RD_COLPS_FIFO_CNT0 );
67 wildcard state s_RD_COLPS_FIFO_CNT1 (RD_COLPS_FIFO_CNT1 );
68 wildcard state s_RD_COLPS_FIFO_CNT2 (RD_COLPS_FIFO_CNT2 );
69 wildcard state s_RD_COLPS_FIFO_CNT3 (RD_COLPS_FIFO_CNT3 );
70 wildcard state s_RD_COLPS_FIFO_CNT4 (RD_COLPS_FIFO_CNT4 );
71 wildcard state s_RD_COLPS_FIFO_CNT5 (RD_COLPS_FIFO_CNT5 );
72 wildcard state s_RD_COLPS_FIFO_CNT6 (RD_COLPS_FIFO_CNT6 );
73 wildcard state s_RD_COLPS_FIFO_CNT7 (RD_COLPS_FIFO_CNT7 );
74 wildcard state s_RD_COLPS_FIFO_CNT8 (RD_COLPS_FIFO_CNT8 );
75 wildcard state s_RD_COLPS_FIFO_NOT_FULL (RD_COLPS_FIFO_NOT_FULL );
76 wildcard state s_RD_COLPS_FIFO_FULL (RD_COLPS_FIFO_FULL );
77 wildcard state s_RD_Q_NOT_EMPTY (RD_Q_NOT_EMPTY );
78 wildcard state s_RD_Q_EMPTY (RD_Q_EMPTY );
79 wildcard state s_RD_COLPS_FIFO_NOT_EMPTY (RD_COLPS_FIFO_NOT_EMPTY);
80 wildcard state s_RD_COLPS_FIFO_EMPTY (RD_COLPS_FIFO_EMPTY );
81
82
83
84 // transitions(to same)
85 wildcard trans t_s_RD_Q_s_RD_Q ( [RD_REQ_DEASSRT, RD_REQ_ASSRT, RD_Q_WR_PTR_DEASSRT, RD_Q_WR_PTR_ASSRT0, RD_Q_WR_PTR_ASSRT1, RD_Q_WR_PTR_ASSRT2, RD_Q_WR_PTR_ASSRT3, RD_Q_WR_PTR_ASSRT4, RD_Q_WR_PTR_ASSRT5, RD_Q_WR_PTR_ASSRT6, RD_Q_WR_PTR_ASSRT7, RD_Q_RD_PTR_DEASSRT, RD_Q_RD_PTR_ASSRT0, RD_Q_RD_PTR_ASSRT1, RD_Q_RD_PTR_ASSRT2, RD_Q_RD_PTR_ASSRT3, RD_Q_RD_PTR_ASSRT4, RD_Q_RD_PTR_ASSRT5, RD_Q_RD_PTR_ASSRT6, RD_Q_RD_PTR_ASSRT7, RD_Q_CNT0, RD_Q_CNT1, RD_Q_CNT2, RD_Q_CNT3, RD_Q_CNT4, RD_Q_CNT5, RD_Q_CNT6, RD_Q_CNT7, RD_Q_CNT8, RD_Q_NOT_FULL, RD_Q_FULL, RD_COLPS_FIFO_CNT0, RD_COLPS_FIFO_CNT1, RD_COLPS_FIFO_CNT2, RD_COLPS_FIFO_CNT3, RD_COLPS_FIFO_CNT4, RD_COLPS_FIFO_CNT5, RD_COLPS_FIFO_CNT6, RD_COLPS_FIFO_CNT7, RD_COLPS_FIFO_CNT8, RD_COLPS_FIFO_NOT_FULL, RD_COLPS_FIFO_FULL, RD_Q_NOT_EMPTY, RD_Q_EMPTY, RD_COLPS_FIFO_NOT_EMPTY, RD_COLPS_FIFO_EMPTY] -> [RD_REQ_DEASSRT, RD_REQ_ASSRT, RD_Q_WR_PTR_DEASSRT, RD_Q_WR_PTR_ASSRT0, RD_Q_WR_PTR_ASSRT1, RD_Q_WR_PTR_ASSRT2, RD_Q_WR_PTR_ASSRT3, RD_Q_WR_PTR_ASSRT4, RD_Q_WR_PTR_ASSRT5, RD_Q_WR_PTR_ASSRT6, RD_Q_WR_PTR_ASSRT7, RD_Q_RD_PTR_DEASSRT, RD_Q_RD_PTR_ASSRT0, RD_Q_RD_PTR_ASSRT1, RD_Q_RD_PTR_ASSRT2, RD_Q_RD_PTR_ASSRT3, RD_Q_RD_PTR_ASSRT4, RD_Q_RD_PTR_ASSRT5, RD_Q_RD_PTR_ASSRT6, RD_Q_RD_PTR_ASSRT7, RD_Q_CNT0, RD_Q_CNT1, RD_Q_CNT2, RD_Q_CNT3, RD_Q_CNT4, RD_Q_CNT5, RD_Q_CNT6, RD_Q_CNT7, RD_Q_CNT8, RD_Q_NOT_FULL, RD_Q_FULL, RD_COLPS_FIFO_CNT0, RD_COLPS_FIFO_CNT1, RD_COLPS_FIFO_CNT2, RD_COLPS_FIFO_CNT3, RD_COLPS_FIFO_CNT4, RD_COLPS_FIFO_CNT5, RD_COLPS_FIFO_CNT6, RD_COLPS_FIFO_CNT7, RD_COLPS_FIFO_CNT8, RD_COLPS_FIFO_NOT_FULL, RD_COLPS_FIFO_FULL, RD_Q_NOT_EMPTY, RD_Q_EMPTY, RD_COLPS_FIFO_NOT_EMPTY, RD_COLPS_FIFO_EMPTY]);
86
87 // transitions(to different)
88 wildcard trans t_s_RD_REQ_DEASSRT_s_RD_REQ_ASSRT (RD_REQ_DEASSRT -> RD_REQ_ASSRT);
89 wildcard trans t_s_RD_REQ_ASSRT_s_RD_REQ_DEASSRT (RD_REQ_ASSRT -> RD_REQ_DEASSRT);
90
91. for ( $i = 0; $i < 8; $i++ ) {
92. print " wildcard trans t_s_RD_Q_WR_PTR_DEASSRT_s_RD_Q_WR_PTR_ASSRT$i\t\t(RD_Q_WR_PTR_DEASSRT -> RD_Q_WR_PTR_ASSRT$i\);\n";
93. print " wildcard trans t_s_RD_Q_WR_PTR_ASSRT$i\_s_RD_Q_WR_PTR_DEASSRT\t\t(RD_Q_WR_PTR_ASSRT$i\ -> RD_Q_WR_PTR_DEASSRT);\n";
94. for ( $j = $i+1; $j < 8; $j++ ) {
95. print " wildcard trans t_s_RD_Q_WR_PTR_ASSRT$i\_s_RD_Q_WR_PTR_ASSRT$j\t\t(RD_Q_WR_PTR_ASSRT$i\ -> RD_Q_WR_PTR_ASSRT$j\);\n";
96. if ( $j eq "7" ) {
97// This can never be achieved since, rd q full <=> no more requests.
98. print " wildcard bad_trans t_s_RD_Q_WR_PTR_ASSRT$j\_s_RD_Q_WR_PTR_ASSRT$i\t\t(RD_Q_WR_PTR_ASSRT$j\ -> RD_Q_WR_PTR_ASSRT$i\);\n";
99. } else {
100. print " wildcard trans t_s_RD_Q_WR_PTR_ASSRT$j\_s_RD_Q_WR_PTR_ASSRT$i\t\t(RD_Q_WR_PTR_ASSRT$j\ -> RD_Q_WR_PTR_ASSRT$i\);\n";
101. }
102. }
103.}
104
105// $i = 7 would not allow this transition coz queue is full
106. for ( $i = 0; $i < 8; $i++ ) {
107. print " wildcard trans t_s_RD_Q_RD_PTR_DEASSRT_s_RD_Q_RD_PTR_ASSRT$i\t\t(RD_Q_RD_PTR_DEASSRT -> RD_Q_RD_PTR_ASSRT$i\);\n";
108. print " wildcard trans t_s_RD_Q_RD_PTR_ASSRT$i\_s_RD_Q_RD_PTR_DEASSRT\t\t(RD_Q_RD_PTR_ASSRT$i\ -> RD_Q_RD_PTR_DEASSRT);\n";
109. for ( $j = $i+1; $j < 8; $j++ ) {
110. print " wildcard bad_trans t_s_RD_Q_RD_PTR_ASSRT$i\_s_RD_Q_RD_PTR_ASSRT$j\t\t(RD_Q_RD_PTR_ASSRT$i\ -> RD_Q_RD_PTR_ASSRT$j\);\n";
111. print " wildcard bad_trans t_s_RD_Q_RD_PTR_ASSRT$j\_s_RD_Q_RD_PTR_ASSRT$i\t\t(RD_Q_RD_PTR_ASSRT$j\ -> RD_Q_RD_PTR_ASSRT$i\);\n";
112. }
113.}
114
115. for ( $i = 0; $i < 8; $i++ ) {
116. $j = $i+1;
117. print " wildcard trans t_s_RD_Q_CNT$i\_s_RD_Q_CNT$j\t\t(RD_Q_CNT$i\ -> RD_Q_CNT$j\);\n";
118. print " wildcard trans t_s_RD_Q_CNT$j\_s_RD_Q_CNT$i\t\t(RD_Q_CNT$j\ -> RD_Q_CNT$i\);\n";
119.}
120
121 wildcard trans t_s_RD_Q_NOT_FULL_s_RD_Q_FULL (RD_Q_NOT_FULL -> RD_Q_FULL);
122 wildcard trans t_s_RD_Q_FULL_s_RD_Q_NOT_FULL (RD_Q_FULL -> RD_Q_NOT_FULL);
123
124. for ( $i = 0; $i < 8; $i++ ) {
125. $j = $i+1;
126. print " wildcard trans t_s_RD_COLPS_FIFO_CNT$i\_s_RD_COLPS_FIFO_CNT$j\t\t(RD_COLPS_FIFO_CNT$i\ -> RD_COLPS_FIFO_CNT$j\);\n";
127. print " wildcard trans t_s_RD_COLPS_FIFO_CNT$j\_s_RD_COLPS_FIFO_CNT$i\t\t(RD_COLPS_FIFO_CNT$j\ -> RD_COLPS_FIFO_CNT$i\);\n";
128.}
129
130 wildcard trans t_s_RD_COLPS_FIFO_NOT_FULL_s_RD_COLPS_FIFO_FULL (RD_COLPS_FIFO_NOT_FULL -> RD_COLPS_FIFO_FULL);
131 wildcard trans t_s_RD_COLPS_FIFO_FULL_s_RD_COLPS_FIFO_NOT_FULL (RD_COLPS_FIFO_FULL -> RD_COLPS_FIFO_NOT_FULL);
132
133 wildcard trans t_s_RD_Q_NOT_EMPTY_s_RD_Q_EMPTY (RD_Q_NOT_EMPTY -> RD_Q_EMPTY);
134 wildcard trans t_s_RD_Q_EMPTY_s_RD_Q_NOT_EMPTY (RD_Q_EMPTY -> RD_Q_NOT_EMPTY);
135 wildcard trans t_s_RD_COLPS_FIFO_NOT_EMPTY_s_RD_COLPS_FIFO_EMPTY (RD_COLPS_FIFO_NOT_EMPTY -> RD_COLPS_FIFO_EMPTY);
136 wildcard trans t_s_RD_COLPS_FIFO_EMPTY_s_RD_COLPS_FIFO_NOT_EMPTY (RD_COLPS_FIFO_EMPTY -> RD_COLPS_FIFO_NOT_EMPTY);
137
138 // transitions(combinations)
139 wildcard trans t_s_0_to_8_b2b_rd (RD_REQ_DEASSRT -> RD_REQ_ASSRT[.1:8.] -> RD_REQ_DEASSRT);
140
141
142 // bad states
143 //bad_state s_not_RD_Q_STATE (not state);
144
145 // bad transitions
146 //bad_trans t_not_RD_Q_TRANS (not trans);
147
148// }
149
Full OpenSPARC design & verification tarball including full HDL.