Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / mcusat / mcusat_rd_wr_schmoo_sample.vrhpal

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// OpenSPARC T2 Processor File: mcusat_rd_wr_schmoo_sample.vrhpal
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     wildcard state s_rd_wr_vld0                 ({2'b00, 1'bx});
     wildcard state s_rd_wr_vld1                 ({2'b01, 1'bx});
     wildcard state s_rd_wr_vld2                 ({2'b10, 1'bx});
     wildcard state s_rd_wr_vld3                 ({2'b11, 1'bx});
     wildcard state s_rd_wr_scrb_vld_011         ({2'b01, 1'b1});
     state s_rd_wr_scrb_vld_101                  ({2'b10, 1'b1});
     state s_rd_wr_scrb_vld_111                  ({2'b11, 1'b1});


  // transitions(to same)
     wildcard trans t_rd_wr_vld0_0                 ({2'b00, 1'bx} -> {2'b00, 1'bx});
     wildcard trans t_rd_wr_vld1_1                 ({2'b01, 1'bx} -> {2'b01, 1'bx});
     wildcard trans t_rd_wr_vld2_2                 ({2'b10, 1'bx} -> {2'b10, 1'bx});
     wildcard trans t_rd_wr_vld3_3                 ({2'b11, 1'bx} -> {2'b11, 1'bx});

  // transitions(to different)
     wildcard trans t_rd_wr_vld0_1                 ({2'b00, 1'bx} -> {2'b01, 1'bx});
     wildcard trans t_rd_wr_vld1_2                 ({2'b01, 1'bx} -> {2'b10, 1'bx});
     wildcard trans t_rd_wr_vld0_3                 ({2'b00, 1'bx} -> {2'b11, 1'bx});
     wildcard trans t_rd_wr_vld1_3                 ({2'b01, 1'bx} -> {2'b11, 1'bx});
     wildcard trans t_rd_wr_vld2_3                 ({2'b10, 1'bx} -> {2'b11, 1'bx});
     wildcard trans t_rd_wr_vld3_2  		   ({2'b11, 1'bx} -> {2'b10, 1'bx});
     trans t_rd_wr_scrb_010_011  		   ({2'b01, 1'b0} -> {2'b01, 1'b1});
     trans t_rd_wr_scrb_100_101  		   ({2'b10, 1'b0} -> {2'b10, 1'b1});
     trans t_rd_wr_scrb_110_111  		   ({2'b11, 1'b0} -> {2'b11, 1'b1});
     trans t_rd_wr_scrb_101_100  		   ({2'b10, 1'b1} -> {2'b10, 1'b0});
     trans t_rd_wr_scrb_111_110  		   ({2'b11, 1'b1} -> {2'b11, 1'b0});
     //trans t_rd_wr_scrb_011_110  		   ({2'b01, 1'b1} -> {2'b11, 1'b0});
     trans t_bad_rd_wr_scrb_011_111       	   ({2'b01, 1'b1} -> {2'b11, 1'b1});


  // transitions(combinations)

  // bad states
  //bad_state s_not_WR_Q_STATE (not state);

  // bad transitions 
  //bad_trans t_not_WR_Q_TRANS (not trans);
//Commenting out following 10 checkers somePerson,08/30/05
//  bad_trans t_bad_rd_wr_vld3_1 		  ({2'b11, 1'bx} -> {2'b01, 1'bx});
//  bad_trans t_bad_rd_wr_vld3_0 		  ({2'b11, 1'bx} -> {2'b00, 1'bx});
//  bad_trans t_bad_rd_wr_scrb_101_001  	  ({2'b10, 1'b1} -> {2'b00, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_101_011  	  ({2'b10, 1'b1} -> {2'b01, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_111_001  	  ({2'b11, 1'b1} -> {2'b00, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_111_011  	  ({2'b11, 1'b1} -> {2'b01, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_111_101  	  ({2'b11, 1'b1} -> {2'b10, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_011_001  	  ({2'b01, 1'b1} -> {2'b00, 1'b1});
//  bad_trans t_bad_rd_wr_scrb_011_101  	  ({2'b01, 1'b1} -> {2'b10, 1'b1});
  // a new write cant be issued to same address if a read is pending
 // bad_trans t_bad_rd_wr_scrb_101_111	  ({2'b10, 1'b1} -> {2'b11, 1'b1});

// }