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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ncu_cov_intf_ver_defines.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #define NCU_PER_REG 40'h8000003028 | |
36 | #define PCX_PKT_LOAD 5'b00000 | |
37 | #define PCX_LOAD_8BYTE 8'h3 | |
38 | #define CPX_PKT_LOAD_RTN 4'b1000 | |
39 | ||
40 | ||
41 | //----------PCX------------------- | |
42 | event ncu_pcx_sample_evnt_trig; | |
43 | reg [31:0] ncu_pcx_b2b; | |
44 | reg [31:0] ncu_pcx_stall_cnt; | |
45 | reg [39:0] ncu_pcx_add; | |
46 | reg [4:0] ncu_pcx_type; | |
47 | reg [5:0] ncu_pcx_cpu; | |
48 | reg [7:0] ncu_pcx_size; | |
49 | reg [1:0] pcx_int_des_reg; | |
50 | reg [63:0] ncu_pcx_adata0_thr_reg; | |
51 | reg [63:0] ncu_pcx_adata1_thr_reg; | |
52 | reg [63:0] ncu_pcx_abusy_thr_reg; | |
53 | reg [10:0] pcx_int_clk_cnt; | |
54 | reg [9:0] ncu_pcx_store_b2b=0; | |
55 | reg [9:0] ncu_pcx_load_b2b=0; | |
56 | reg [9:0] ncu_pcx_niu_b2b=0; | |
57 | reg [9:0] ncu_pcx_ccu_b2b=0; | |
58 | reg [9:0] ncu_pcx_mcu0_b2b=0; | |
59 | reg [9:0] ncu_pcx_mcu1_b2b=0; | |
60 | reg [9:0] ncu_pcx_mcu2_b2b=0; | |
61 | reg [9:0] ncu_pcx_mcu3_b2b=0; | |
62 | reg [9:0] ncu_pcx_tcu_b2b=0; | |
63 | reg [9:0] ncu_pcx_dbg1_b2b=0; | |
64 | reg [9:0] ncu_pcx_rst_b2b=0; | |
65 | reg [9:0] ncu_pcx_ssi_b2b=0; | |
66 | reg [9:0] ncu_pcx_dmu_b2b=0; | |
67 | reg [9:0] ncu_pcx_pio_b2b=0; | |
68 | reg [9:0] ncu_pcx_pkt_gap_cnt=0; | |
69 | ||
70 | //----------CPX------------------- | |
71 | event cpx_sample_evnt_trig; | |
72 | reg ncu_ccx_pkt_flag; | |
73 | reg [3:0] ncu_cpx_int_multi_pkt=0; | |
74 | reg [31:0] ncu_cpx_b2b; | |
75 | reg [3:0] ncu_cpx_type; | |
76 | reg [1:0] ncu_cpx_err; | |
77 | reg [7:0] ncu_cpx_cpu; | |
78 | reg [5:0] ncu_cpx_cpu_thr_id; | |
79 | reg [5:0] ncu_cpx_int_vec; | |
80 | reg [9:0] ncu_cpx_req_to_gnt_cnt=0; | |
81 | ||
82 | //----------SIU------------------- | |
83 | event siu_sample_evnt_trig; | |
84 | reg [31:0] ncu_siu_b2b; | |
85 | reg ncu_siu_pio; | |
86 | reg [5:0] ncu_siu_cpu; | |
87 | reg [1:0] ncu_siu_bufid; | |
88 | reg [3:0] ncu_siu_credid; | |
89 | reg [5:0] ncu_siu_mondid; | |
90 | reg [3:0] ncu_siu_err; | |
91 | reg ncu_siu_type; | |
92 | reg [7:0] siu_ncu_pkt_gap_cnt=0; | |
93 | reg [7:0] ncu_siu_req_cnt=0; | |
94 | ||
95 | ||
96 | //----------PIO------------------- | |
97 | event pio_sample_evnt_trig; | |
98 | reg ncu_pio_type; | |
99 | reg [31:0] ncu_pio_b2b; | |
100 | reg [3:0] ncu_pio_credit; | |
101 | reg [3:0] ncu_pio_size; | |
102 | reg [1:0] ncu_pio_cmap; | |
103 | reg [1:0] ncu_pio_bufid; | |
104 | reg [5:0] ncu_pio_cpu; | |
105 | reg [35:0] ncu_pio_add; | |
106 | reg [4:0] ncu_pio_pkt_gap = 0; | |
107 | reg [2:0] ncu_pio_mmu; | |
108 | ||
109 | ||
110 | //----------TCU->NCU------------------- | |
111 | event tcu_ncu_sample_evnt_trig; | |
112 | reg [31:0] tcu_ncu_b2b; | |
113 | reg [31:0] ncu_tcu_stall_b2b; | |
114 | reg [31:0] tcu_ncu_vld_to_stall_cnt; | |
115 | reg [31:0] tcu_ncu_pkt_gap = 0; | |
116 | reg [2:0] tcu_ncu_size; | |
117 | reg [1:0] tcu_ncu_bufid; | |
118 | reg [5:0] tcu_ncu_cpuid; | |
119 | reg [3:0] tcu_ncu_type; | |
120 | reg [8:0] tcu_ncu_deviceid; | |
121 | reg [5:0] tcu_ncu_int_vec; | |
122 | reg [7:0] tcu_ncu_add; | |
123 | //----------NCU->TCU------------------- | |
124 | event ncu_tcu_sample_evnt_trig; | |
125 | reg [31:0] ncu_tcu_b2b; | |
126 | reg [31:0] tcu_ncu_stall_b2b; | |
127 | reg [31:0] ncu_tcu_vld_to_stall_cnt; | |
128 | reg [31:0] ncu_tcu_pkt_gap = 0; | |
129 | reg [39:0] ncu_tcu_add; | |
130 | reg [2:0] ncu_tcu_size; | |
131 | reg [1:0] ncu_tcu_bufid; | |
132 | reg [5:0] ncu_tcu_cpuid; | |
133 | reg [3:0] ncu_tcu_type; | |
134 | //----------CCU->NCU------------------- | |
135 | event ccu_ncu_sample_evnt_trig; | |
136 | reg [31:0] ccu_ncu_b2b; | |
137 | reg [31:0] ncu_ccu_stall_b2b; | |
138 | reg [31:0] ccu_ncu_vld_to_stall_cnt; | |
139 | reg [31:0] ccu_ncu_pkt_gap = 0; | |
140 | reg [1:0] ccu_ncu_bufid; | |
141 | reg [5:0] ccu_ncu_cpuid; | |
142 | reg [3:0] ccu_ncu_type; | |
143 | reg [8:0] ccu_ncu_deviceid; | |
144 | reg [5:0] ccu_ncu_int_vec; | |
145 | reg [2:0] ccu_ncu_size; | |
146 | //----------NCU->CCU------------------- | |
147 | event ncu_ccu_sample_evnt_trig; | |
148 | reg [31:0] ncu_ccu_b2b; | |
149 | reg [31:0] ccu_ncu_stall_b2b; | |
150 | reg [31:0] ncu_ccu_vld_to_stall_cnt; | |
151 | reg [31:0] ncu_ccu_pkt_gap = 0; | |
152 | reg [39:0] ncu_ccu_add; | |
153 | reg [2:0] ncu_ccu_size; | |
154 | reg [1:0] ncu_ccu_bufid; | |
155 | reg [5:0] ncu_ccu_cpuid; | |
156 | reg [3:0] ncu_ccu_type; | |
157 | //----------DBG1->NCU------------------- | |
158 | event dbg1_ncu_sample_evnt_trig; | |
159 | reg [31:0] dbg1_ncu_b2b; | |
160 | reg [31:0] ncu_dbg1_stall_b2b; | |
161 | reg [31:0] dbg1_ncu_vld_to_stall_cnt; | |
162 | reg [31:0] dbg1_ncu_pkt_gap = 0; | |
163 | reg [1:0] dbg1_ncu_bufid; | |
164 | reg [5:0] dbg1_ncu_cpuid; | |
165 | reg [3:0] dbg1_ncu_type; | |
166 | reg [8:0] dbg1_ncu_deviceid; | |
167 | reg [5:0] dbg1_ncu_int_vec; | |
168 | reg [2:0] dbg1_ncu_size; | |
169 | ||
170 | //----------NCU->DBG1------------------- | |
171 | event ncu_dbg1_sample_evnt_trig; | |
172 | reg [31:0] ncu_dbg1_b2b; | |
173 | reg [31:0] dbg1_ncu_stall_b2b; | |
174 | reg [31:0] ncu_dbg1_vld_to_stall_cnt; | |
175 | reg [31:0] ncu_dbg1_pkt_gap = 0; | |
176 | reg [39:0] ncu_dbg1_add; | |
177 | reg [2:0] ncu_dbg1_size; | |
178 | reg [1:0] ncu_dbg1_bufid; | |
179 | reg [5:0] ncu_dbg1_cpuid; | |
180 | reg [3:0] ncu_dbg1_type; | |
181 | ||
182 | //----------RST->NCU------------------- | |
183 | event rst_ncu_sample_evnt_trig; | |
184 | reg [31:0] rst_ncu_b2b; | |
185 | reg [31:0] ncu_rst_stall_b2b; | |
186 | reg [31:0] rst_ncu_vld_to_stall_cnt; | |
187 | reg [31:0] rst_ncu_pkt_gap = 0; | |
188 | reg [1:0] rst_ncu_bufid; | |
189 | reg [5:0] rst_ncu_cpuid; | |
190 | reg [3:0] rst_ncu_type; | |
191 | reg [8:0] rst_ncu_deviceid; | |
192 | reg [5:0] rst_ncu_int_vec; | |
193 | reg [2:0] rst_ncu_size; | |
194 | ||
195 | //----------NCU->RST------------------- | |
196 | event ncu_rst_sample_evnt_trig; | |
197 | reg [31:0] ncu_rst_b2b; | |
198 | reg [31:0] rst_ncu_stall_b2b; | |
199 | reg [31:0] ncu_rst_vld_to_stall_cnt; | |
200 | reg [31:0] ncu_rst_pkt_gap = 0; | |
201 | reg [39:0] ncu_rst_add; | |
202 | reg [2:0] ncu_rst_size; | |
203 | reg [1:0] ncu_rst_bufid; | |
204 | reg [5:0] ncu_rst_cpuid; | |
205 | reg [3:0] ncu_rst_type; | |
206 | ||
207 | //----------SSI->NCU------------------- | |
208 | event ssi_ncu_sample_evnt_trig; | |
209 | reg [31:0] ssi_ncu_b2b; | |
210 | reg [31:0] ncu_ssi_stall_b2b; | |
211 | reg [31:0] ssi_ncu_vld_to_stall_cnt; | |
212 | reg [31:0] ssi_ncu_pkt_gap = 0; | |
213 | reg [2:0] ssi_ncu_size; | |
214 | reg [1:0] ssi_ncu_bufid; | |
215 | reg [5:0] ssi_ncu_cpuid; | |
216 | reg [3:0] ssi_ncu_type; | |
217 | reg [8:0] ssi_ncu_deviceid; | |
218 | reg [5:0] ssi_ncu_int_vec; | |
219 | ||
220 | //----------NCU->SSI------------------- | |
221 | event ncu_ssi_sample_evnt_trig; | |
222 | reg [31:0] ncu_ssi_b2b; | |
223 | reg [31:0] ssi_ncu_stall_b2b; | |
224 | reg [31:0] ncu_ssi_vld_to_stall_cnt; | |
225 | reg [31:0] ncu_ssi_pkt_gap = 0; | |
226 | reg [39:0] ncu_ssi_add; | |
227 | reg [2:0] ncu_ssi_size; | |
228 | reg [1:0] ncu_ssi_bufid; | |
229 | reg [5:0] ncu_ssi_cpuid; | |
230 | reg [3:0] ncu_ssi_type; | |
231 | ||
232 | //----------MCU0->NCU------------------- | |
233 | event mcu0_ncu_sample_evnt_trig; | |
234 | reg [31:0] mcu0_ncu_b2b; | |
235 | reg [31:0] ncu_mcu0_stall_b2b; | |
236 | reg [31:0] mcu0_ncu_vld_to_stall_cnt; | |
237 | reg [31:0] mcu0_ncu_pkt_gap = 0; | |
238 | reg [1:0] mcu0_ncu_bufid; | |
239 | reg [5:0] mcu0_ncu_cpuid; | |
240 | reg [3:0] mcu0_ncu_type; | |
241 | reg [8:0] mcu0_ncu_deviceid; | |
242 | reg [5:0] mcu0_ncu_int_vec; | |
243 | reg [2:0] mcu0_ncu_size; | |
244 | //----------NCU->MCU0------------------- | |
245 | event ncu_mcu0_sample_evnt_trig; | |
246 | reg [31:0] ncu_mcu0_b2b; | |
247 | reg [31:0] mcu0_ncu_stall_b2b; | |
248 | reg [31:0] ncu_mcu0_vld_to_stall_cnt; | |
249 | reg [31:0] ncu_mcu0_pkt_gap = 0; | |
250 | reg [39:0] ncu_mcu0_add; | |
251 | reg [2:0] ncu_mcu0_size; | |
252 | reg [1:0] ncu_mcu0_bufid; | |
253 | reg [5:0] ncu_mcu0_cpuid; | |
254 | reg [3:0] ncu_mcu0_type; | |
255 | //----------MCU1->NCU------------------- | |
256 | event mcu1_ncu_sample_evnt_trig; | |
257 | reg [31:0] mcu1_ncu_b2b; | |
258 | reg [31:0] ncu_mcu1_stall_b2b; | |
259 | reg [31:0] mcu1_ncu_vld_to_stall_cnt; | |
260 | reg [31:0] mcu1_ncu_pkt_gap = 0; | |
261 | reg [1:0] mcu1_ncu_bufid; | |
262 | reg [5:0] mcu1_ncu_cpuid; | |
263 | reg [3:0] mcu1_ncu_type; | |
264 | reg [8:0] mcu1_ncu_deviceid; | |
265 | reg [5:0] mcu1_ncu_int_vec; | |
266 | reg [2:0] mcu1_ncu_size; | |
267 | //----------NCU->MCU1------------------- | |
268 | event ncu_mcu1_sample_evnt_trig; | |
269 | reg [31:0] ncu_mcu1_b2b; | |
270 | reg [31:0] mcu1_ncu_stall_b2b; | |
271 | reg [31:0] ncu_mcu1_vld_to_stall_cnt; | |
272 | reg [31:0] ncu_mcu1_pkt_gap = 0; | |
273 | reg [39:0] ncu_mcu1_add; | |
274 | reg [2:0] ncu_mcu1_size; | |
275 | reg [1:0] ncu_mcu1_bufid; | |
276 | reg [5:0] ncu_mcu1_cpuid; | |
277 | reg [3:0] ncu_mcu1_type; | |
278 | //----------MCU2->NCU------------------- | |
279 | event mcu2_ncu_sample_evnt_trig; | |
280 | reg [31:0] mcu2_ncu_b2b; | |
281 | reg [31:0] ncu_mcu2_stall_b2b; | |
282 | reg [31:0] mcu2_ncu_vld_to_stall_cnt; | |
283 | reg [31:0] mcu2_ncu_pkt_gap = 0; | |
284 | reg [1:0] mcu2_ncu_bufid; | |
285 | reg [5:0] mcu2_ncu_cpuid; | |
286 | reg [3:0] mcu2_ncu_type; | |
287 | reg [8:0] mcu2_ncu_deviceid; | |
288 | reg [5:0] mcu2_ncu_int_vec; | |
289 | reg [2:0] mcu2_ncu_size; | |
290 | //----------NCU->MCU2------------------- | |
291 | event ncu_mcu2_sample_evnt_trig; | |
292 | reg [31:0] ncu_mcu2_b2b; | |
293 | reg [31:0] mcu2_ncu_stall_b2b; | |
294 | reg [31:0] ncu_mcu2_vld_to_stall_cnt; | |
295 | reg [31:0] ncu_mcu2_pkt_gap = 0; | |
296 | reg [39:0] ncu_mcu2_add; | |
297 | reg [2:0] ncu_mcu2_size; | |
298 | reg [1:0] ncu_mcu2_bufid; | |
299 | reg [5:0] ncu_mcu2_cpuid; | |
300 | reg [3:0] ncu_mcu2_type; | |
301 | //----------MCU3->NCU------------------- | |
302 | event mcu3_ncu_sample_evnt_trig; | |
303 | reg [31:0] mcu3_ncu_b2b; | |
304 | reg [31:0] ncu_mcu3_stall_b2b; | |
305 | reg [31:0] mcu3_ncu_vld_to_stall_cnt; | |
306 | reg [31:0] mcu3_ncu_pkt_gap = 0; | |
307 | reg [1:0] mcu3_ncu_bufid; | |
308 | reg [5:0] mcu3_ncu_cpuid; | |
309 | reg [3:0] mcu3_ncu_type; | |
310 | reg [8:0] mcu3_ncu_deviceid; | |
311 | reg [5:0] mcu3_ncu_int_vec; | |
312 | reg [2:0] mcu3_ncu_size; | |
313 | //----------NCU->MCU3------------------- | |
314 | event ncu_mcu3_sample_evnt_trig; | |
315 | reg [31:0] ncu_mcu3_b2b; | |
316 | reg [31:0] mcu3_ncu_stall_b2b; | |
317 | reg [31:0] ncu_mcu3_vld_to_stall_cnt; | |
318 | reg [31:0] ncu_mcu3_pkt_gap = 0; | |
319 | reg [39:0] ncu_mcu3_add; | |
320 | reg [2:0] ncu_mcu3_size; | |
321 | reg [1:0] ncu_mcu3_bufid; | |
322 | reg [5:0] ncu_mcu3_cpuid; | |
323 | reg [3:0] ncu_mcu3_type; | |
324 | //----------NIU->NCU------------------- | |
325 | event niu_ncu_sample_evnt_trig; | |
326 | reg [31:0] niu_ncu_b2b; | |
327 | reg [31:0] ncu_niu_stall_b2b; | |
328 | reg [31:0] niu_ncu_vld_to_stall_cnt; | |
329 | reg [31:0] niu_ncu_pkt_gap = 0; | |
330 | reg [1:0] niu_ncu_bufid; | |
331 | reg [5:0] niu_ncu_cpuid; | |
332 | reg [3:0] niu_ncu_type; | |
333 | reg [8:0] niu_ncu_deviceid; | |
334 | reg [5:0] niu_ncu_int_vec; | |
335 | reg [4:0] niu_ncu_int_des_reg; | |
336 | reg [2:0] niu_ncu_size; | |
337 | //----------NCU->NIU------------------- | |
338 | event ncu_niu_sample_evnt_trig; | |
339 | reg [31:0] ncu_niu_b2b; | |
340 | reg [31:0] niu_ncu_stall_b2b; | |
341 | reg [31:0] ncu_niu_vld_to_stall_cnt; | |
342 | reg [31:0] ncu_niu_pkt_gap = 0; | |
343 | reg [39:0] ncu_niu_add; | |
344 | reg [2:0] ncu_niu_size; | |
345 | reg [1:0] ncu_niu_bufid; | |
346 | reg [5:0] ncu_niu_cpuid; | |
347 | reg [3:0] ncu_niu_type; | |
348 | //----------DMU->NCU------------------- | |
349 | event dmu_ncu_sample_evnt_trig; | |
350 | reg [31:0] dmu_ncu_b2b; | |
351 | reg [31:0] dmu_ncu_stall_b2b; | |
352 | reg [31:0] dmu_ncu_vld_to_stall_cnt; | |
353 | reg [31:0] dmu_ncu_pkt_gap = 0; | |
354 | reg [1:0] dmu_ncu_bufid; | |
355 | reg [5:0] dmu_ncu_cpuid; | |
356 | reg [3:0] dmu_ncu_type; | |
357 | reg [8:0] dmu_ncu_deviceid; | |
358 | reg [5:0] dmu_ncu_int_vec; | |
359 | reg [2:0] dmu_ncu_size; | |
360 | //----------NCU->DMU------------------- | |
361 | event ncu_dmu_sample_evnt_trig; | |
362 | reg [31:0] ncu_dmu_b2b; | |
363 | reg [31:0] ncu_dmu_stall_b2b; | |
364 | reg [31:0] ncu_dmu_vld_to_stall_cnt; | |
365 | reg [31:0] ncu_dmu_pkt_gap = 0; | |
366 | reg [39:0] ncu_dmu_add; | |
367 | reg [2:0] ncu_dmu_size; | |
368 | reg [1:0] ncu_dmu_bufid; | |
369 | reg [5:0] ncu_dmu_cpuid; | |
370 | reg [3:0] ncu_dmu_type; | |
371 | ||
372 | //--------- NCU_RAS------------------- | |
373 | event ncu_soc_report_sample_evnt_trig; | |
374 | reg [7:0] mcu_err; | |
375 | reg [2:0] mcu_err_b2b; | |
376 | reg [2:0] niu_err; | |
377 | reg [2:0] niu_err_b2b; | |
378 | reg [10:0] siu_err; | |
379 | reg [10:0] siu_err_b2b; | |
380 | reg [5:0] dmu_err; | |
381 | reg [5:0] dmu_err_b2b; | |
382 | reg [7:0] mcu_erri; | |
383 | reg [2:0] niu_erri; | |
384 | reg [10:0] siu_erri; | |
385 | reg [5:0] dmu_erri; | |
386 | reg [37:0] ncu_soc_err; | |
387 | reg [1:0] ncu_ctag_ce; | |
388 | reg [1:0] ncu_ctag_ue; | |
389 | reg [1:0] ncu_data_pe; | |
390 | reg [1:0] ncu_int_tb_pe; | |
391 | reg ncu_ras_esr_err_cnt_flag = 0; | |
392 | reg [5:0] ncu_ras_esr_err_cnt = 0; | |
393 | reg [5:0] mcu_err_cnt = 0; | |
394 | reg [5:0] niu_err_cnt = 0; | |
395 | reg [42:0] raserr_in_ele_off; | |
396 | reg [42:0] raserr_in_eie_off; | |
397 | reg [42:0] raserr_in_fee_off; | |
398 | reg [20:0] multi_err_sign_reg = 0; | |
399 | reg ras_tran_syn = 0; | |
400 | ||
401 | //------- ADVINCE INT --------------- | |
402 | reg spc_int_flag = 0; | |
403 | reg [3:0] spc_niu_int_skew = 4'hf; | |
404 | reg [3:0] spc_ssi_int_skew = 4'hf; | |
405 | reg [3:0] spc_siu_int_skew = 4'hf; | |
406 | ||
407 | reg niu_int_flag = 0; | |
408 | reg [3:0] niu_spc_int_skew = 4'hf; | |
409 | reg [3:0] niu_ssi_int_skew = 4'hf; | |
410 | reg [3:0] niu_siu_int_skew = 4'hf; | |
411 | ||
412 | reg ssi_int_flag = 0; | |
413 | reg [3:0] ssi_niu_int_skew = 4'hf; | |
414 | reg [3:0] ssi_siu_int_skew = 4'hf; | |
415 | reg [3:0] ssi_spc_int_skew = 4'hf; | |
416 | ||
417 | reg siu_int_flag = 0; | |
418 | reg [3:0] siu_ssi_int_skew = 4'hf; | |
419 | reg [3:0] siu_niu_int_skew = 4'hf; | |
420 | reg [3:0] siu_spc_int_skew = 4'hf; | |
421 | ||
422 | reg [2:0] niu_siu_ssi = 0; | |
423 | reg [2:0] siu_ssi_spc = 0; | |
424 | reg [2:0] ssi_spc_niu = 0; | |
425 | reg [2:0] spc_niu_siu = 0; | |
426 | ||
427 | reg [3:0] mondo_wait_id_reg_cov0; | |
428 | reg [3:0] mondo_wait_id_reg_cov1; | |
429 | reg [3:0] mondo_wait_id_reg_cov2; | |
430 | reg [3:0] mondo_wait_id_reg_cov3; | |
431 | event mondo_wait_id_reg_cov_trig; | |
432 | reg mondo_ack_nack_cov_flag = 0; | |
433 | ||
434 | //-------------- SPC -------------- | |
435 | ||
436 | reg [7:0] ncu_spc_core_enable_status; | |
437 | reg [7:0] ncu_spc_core_available; | |
438 | reg [63:0] ncu_spc_core_running; | |
439 | reg [63:0] spc_ncu_core_running_status; | |
440 | reg [4:0] ncu_spc_ba; | |
441 | reg [4:0] ncu_sii_ba; | |
442 | reg [4:0] ncu_l2t_ba; | |
443 | reg [4:0] ncu_mcu_ba; | |
444 | ||
445 | //-------------- EFU -------------- | |
446 | event efu_ncu_evnt_trig; | |
447 | reg [5:0] efu_ncu_intf_hit; | |
448 | reg [63:0] efu_ncu_sernum0 = 0; | |
449 | reg [63:0] efu_ncu_sernum1 = 0; | |
450 | reg [63:0] efu_ncu_sernum2 = 0; | |
451 | reg [63:0] efu_ncu_coreaval = 0; | |
452 | reg [63:0] efu_ncu_bankaval = 0; | |
453 | reg [63:0] efu_ncu_efustat = 0; | |
454 | ||
455 | reg ncu_io_sample_flag = 0; |