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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ncu / ncu_coverage.vrpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ncu_coverage.vrpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include <ListMacros.vrh>
37#include "plusArgMacros.vri"
38#include "std_display_class.vrh"
39#include "std_display_defines.vri"
40#include "ncu_cov.if.vrh"
41#include "ncu_cov_ports_binds.vrh"
42
43
44
45class ncu_intf_cov
46{
47 // for dispmon
48 StandardDisplay dbg;
49 local string myname;
50
51#ifdef FC_COVERAGE
52. for ($bank=0; $bank<8; $bank++)
53. {
54 integer spc${bank}_ncu_thread1_cnt = 0;
55 integer spc${bank}_ncu_thread2_cnt = 0;
56 integer spc${bank}_ncu_thread3_cnt = 0;
57 integer spc${bank}_ncu_thread4_cnt = 0;
58 integer spc${bank}_ncu_thread5_cnt = 0;
59 integer spc${bank}_ncu_thread6_cnt = 0;
60 integer spc${bank}_ncu_thread7_cnt = 0;
61 integer spc${bank}_ncu_thread8_cnt = 0;
62 integer spc${bank}_ncu_thread1_10_cnt = 0;
63 integer spc${bank}_ncu_thread2_10_cnt = 0;
64 integer spc${bank}_ncu_thread3_10_cnt = 0;
65 integer spc${bank}_ncu_thread4_10_cnt = 0;
66 integer spc${bank}_ncu_thread5_10_cnt = 0;
67 integer spc${bank}_ncu_thread6_10_cnt = 0;
68 integer spc${bank}_ncu_thread7_10_cnt = 0;
69 integer spc${bank}_ncu_thread8_10_cnt = 0;
70
71 event spc${bank}_ncu_thread1_evnt_trig;
72 event spc${bank}_ncu_thread2_evnt_trig;
73 event spc${bank}_ncu_thread3_evnt_trig;
74 event spc${bank}_ncu_thread4_evnt_trig;
75 event spc${bank}_ncu_thread5_evnt_trig;
76 event spc${bank}_ncu_thread6_evnt_trig;
77 event spc${bank}_ncu_thread7_evnt_trig;
78 event spc${bank}_ncu_thread8_evnt_trig;
79 event spc${bank}_ncu_thread1_10_evnt_trig;
80 event spc${bank}_ncu_thread2_10_evnt_trig;
81 event spc${bank}_ncu_thread3_10_evnt_trig;
82 event spc${bank}_ncu_thread4_10_evnt_trig;
83 event spc${bank}_ncu_thread5_10_evnt_trig;
84 event spc${bank}_ncu_thread6_10_evnt_trig;
85 event spc${bank}_ncu_thread7_10_evnt_trig;
86 event spc${bank}_ncu_thread8_10_evnt_trig;
87. }
88
89 integer spc_ncu_thread_50_cnt = 0;
90 integer spc_ncu_thread_100_cnt = 0;
91
92
93 event spc_ncu_thread_50_evnt_trig;
94 event spc_ncu_thread_100_evnt_trig;
95 event ncu_spc_enable1_evnt_trig;
96 event ncu_spc_enable2_evnt_trig;
97 event ncu_spc_enable3_evnt_trig;
98 event ncu_spc_enable4_evnt_trig;
99 event ncu_spc_enable5_evnt_trig;
100 event ncu_spc_enable6_evnt_trig;
101 event ncu_spc_enable7_evnt_trig;
102
103#endif
104
105 event ncu_spc_bnk_evnt_trig;
106
107 #include "ncu_cov_intf_ver_defines.vrh"
108
109 // ----------- coverage_group ----------------
110#ifndef IOS_COVERAGE
111 coverage_group efu_ncu_intf_group
112 {
113 const_sample_reference = 1; // ref. to sample vars. is constant
114
115 sample_event = sync (ANY, efu_ncu_evnt_trig );
116 #include "efu_ncu_sample.vrh"
117
118 } // ncu_intf_cov_group
119//----------PCX -> NCU-------------------
120 coverage_group ncu_pcx_intf_cov_group
121 {
122 const_sample_reference = 1; // ref. to sample vars. is constant
123
124 sample_event = sync (ANY, ncu_pcx_sample_evnt_trig );
125 #include "ncu_pcx_sample.vrh"
126
127 } // ncu_intf_cov_group
128
129//----------NCU -> CPX-------------------
130 coverage_group ncu_cpx_intf_cov_group
131 {
132 const_sample_reference = 1; // ref. to sample vars. is constant
133
134 sample_event = sync (ANY, cpx_sample_evnt_trig );
135
136 #include "ncu_cpx_sample.vrh"
137
138 } // ncu_intf_cov_group
139
140//----------SIU -> NCU-------------------
141 coverage_group ncu_siu_intf_cov_group
142 {
143 const_sample_reference = 1; // ref. to sample vars. is constant
144
145 sample_event = sync (ANY, siu_sample_evnt_trig );
146 #include "ncu_siu_sample.vrh"
147
148 } // ncu_intf_cov_group
149
150#ifndef NCU_INTF_COV
151//----------NCU -> PIO-------------------
152 coverage_group ncu_pio_intf_cov_group
153 {
154 const_sample_reference = 1; // ref. to sample vars. is constant
155
156 sample_event = sync (ANY, pio_sample_evnt_trig );
157 #include "ncu_pio_sample.vrh"
158
159 } // ncu_intf_cov_group
160#endif
161
162//----------NCU -> TCU-------------------
163 coverage_group ncu_tcu_intf_cov_group
164 {
165 const_sample_reference = 1; // ref. to sample vars. is constant
166 sample_event = sync (ANY, ncu_tcu_sample_evnt_trig );
167 #include "ncu_tcu_sample.vrh"
168 } // ncu_tcu_intf_cov_group
169
170//----------TCU -> NCU-------------------
171 coverage_group tcu_ncu_intf_cov_group
172 {
173 const_sample_reference = 1; // ref. to sample vars. is constant
174 sample_event = sync (ANY, tcu_ncu_sample_evnt_trig );
175 #include "tcu_ncu_sample.vrh"
176 } // tcu_ncu_intf_cov_group
177
178
179
180//----------NCU -> CCU-------------------
181 coverage_group ncu_ccu_intf_cov_group
182 {
183 const_sample_reference = 1; // ref. to sample vars. is constant
184 sample_event = sync (ANY, ncu_ccu_sample_evnt_trig );
185 #include "ncu_ccu_sample.vrh"
186 } // ncu_nucb_intf_cov_group
187
188//----------CCU -> NCU-------------------
189 coverage_group ccu_ncu_intf_cov_group
190 {
191 const_sample_reference = 1; // ref. to sample vars. is constant
192 sample_event = sync (ANY, ccu_ncu_sample_evnt_trig );
193 #include "ccu_ncu_sample.vrh"
194 } // ccu_ncu_intf_cov_group
195
196//----------NCU -> DBG1-------------------
197 coverage_group ncu_dbg1_intf_cov_group
198 {
199 const_sample_reference = 1; // ref. to sample vars. is constant
200 sample_event = sync (ANY, ncu_dbg1_sample_evnt_trig );
201 #include "ncu_dbg1_sample.vrh"
202 } // ncu_nucb_intf_cov_group
203
204//----------DBG1 -> NCU-------------------
205 coverage_group dbg1_ncu_intf_cov_group
206 {
207 const_sample_reference = 1; // ref. to sample vars. is constant
208 sample_event = sync (ANY, dbg1_ncu_sample_evnt_trig );
209 #include "dbg1_ncu_sample.vrh"
210 } // dbg1_ncu_intf_cov_group
211
212//----------NCU -> SSI-------------------
213 coverage_group ncu_ssi_intf_cov_group
214 {
215 const_sample_reference = 1; // ref. to sample vars. is constant
216 sample_event = sync (ANY, ncu_ssi_sample_evnt_trig );
217 #include "ncu_ssi_sample.vrh"
218 } // ncu_nucb_intf_cov_group
219
220//----------SSI -> NCU-------------------
221 coverage_group ssi_ncu_intf_cov_group
222 {
223 const_sample_reference = 1; // ref. to sample vars. is constant
224 sample_event = sync (ANY, ssi_ncu_sample_evnt_trig );
225 #include "ssi_ncu_sample.vrh"
226 } // ssi_ncu_intf_cov_group
227
228
229//----------NCU -> RST-------------------
230 coverage_group ncu_rst_intf_cov_group
231 {
232 const_sample_reference = 1; // ref. to sample vars. is constant
233 sample_event = sync (ANY, ncu_rst_sample_evnt_trig );
234 #include "ncu_rst_sample.vrh"
235 } // ncu_nucb_intf_cov_group
236
237//----------RST -> NCU-------------------
238 coverage_group rst_ncu_intf_cov_group
239 {
240 const_sample_reference = 1; // ref. to sample vars. is constant
241 sample_event = sync (ANY, rst_ncu_sample_evnt_trig );
242 #include "rst_ncu_sample.vrh"
243 } // rst_ncu_intf_cov_group
244
245.for($b=0; $b<4; $b++) {
246//----------NCU -> MCU${b}-------------------
247 coverage_group ncu_mcu${b}_intf_cov_group
248 {
249 const_sample_reference = 1; // ref. to sample vars. is constant
250 sample_event = sync (ANY, ncu_mcu${b}_sample_evnt_trig );
251 #include "ncu_mcu${b}_sample.vrh"
252 } // ncu_nucb_intf_cov_group
253
254//----------MCU${b} -> NCU-------------------
255 coverage_group mcu${b}_ncu_intf_cov_group
256 {
257 const_sample_reference = 1; // ref. to sample vars. is constant
258 sample_event = sync (ANY, mcu${b}_ncu_sample_evnt_trig );
259 #include "mcu${b}_ncu_sample.vrh"
260 } // ncu_mcu_intf_cov_group
261
262.}
263
264//----------NCU -> NIU-------------------
265 coverage_group ncu_niu_intf_cov_group
266 {
267 const_sample_reference = 1; // ref. to sample vars. is constant
268 sample_event = sync (ANY, ncu_niu_sample_evnt_trig );
269 #include "ncu_niu_sample.vrh"
270 } // ncu_nucb_intf_cov_group
271
272//----------NIU -> NCU-------------------
273 coverage_group niu_ncu_intf_cov_group
274 {
275 const_sample_reference = 1; // ref. to sample vars. is constant
276 sample_event = sync (ANY, niu_ncu_sample_evnt_trig );
277 #include "niu_ncu_sample.vrh"
278 } // niu_ncu_intf_cov_group
279
280//----------NCU -> DMU-------------------
281 coverage_group ncu_dmu_intf_cov_group
282 {
283 const_sample_reference = 1; // ref. to sample vars. is constant
284 sample_event = sync (ANY, ncu_dmu_sample_evnt_trig );
285 #include "ncu_dmu_sample.vrh"
286 } // ncu_nucb_intf_cov_group
287
288//----------DMU -> NCU-------------------
289 coverage_group dmu_ncu_intf_cov_group
290 {
291 const_sample_reference = 1; // ref. to sample vars. is constant
292 sample_event = sync (ANY, dmu_ncu_sample_evnt_trig );
293 #include "dmu_ncu_sample.vrh"
294 } // dmu_ncu_intf_cov_group
295
296 coverage_group ncu_io_int_cov_group
297 {
298 const_sample_reference = 1; // ref. to sample vars. is constant
299 sample_event = @(posedge ncu_rtl_io_cov.int_vld);
300 sample ncu_intr_dev_id_cov (ncu_rtl_io_cov.io_intman_addr)
301 {
302 m_state DEVICE_ID0 (1:2) ;
303 m_state DEVICE_ID1 (64:127) ;
304 }
305
306 } // ncu_io_int_cov_group
307
308#endif
309//-------------- NCU RAS ----------------------
310 coverage_group ncu_ras_cov_group
311 {
312 const_sample_reference = 1; // ref. to sample vars. is constant
313 sample_event = @(negedge ncu_ras_cov.clk );
314 #include "ncu_ras_intf_sample.vrh"
315 } // ncu_ras_cov_group
316
317 coverage_group ncu_ras_report_cov_group
318 {
319 const_sample_reference = 1; // ref. to sample vars. is constant
320 sample_event = sync (ANY, ncu_soc_report_sample_evnt_trig);
321 #include "ncu_ras_report_sample.vrh"
322 } // ncu_ras_report_cov_group
323
324//-------------- Advance NCU interrupt ------------------------
325 coverage_group ncu_ios_cov_group
326 {
327 const_sample_reference = 1; // ref. to sample vars. is constant
328 sample_event = @(negedge ncu_cov_ios.clk);
329 #include "ncu_io_sample.vrh"
330 } // ncu_ios_cov_group
331
332#ifndef IOS_COVERAGE
333//-------------- Advance NCU interrupt ------------------------
334 coverage_group ncu_intr_pairs_cov
335 {
336 const_sample_reference = 1; // ref. to sample vars. is constant
337 sample_event = @(negedge ncu_cov_ccx.clk);
338 #include "ncu_int_sample.vrh"
339 } // ncu_intr_pairs_cov
340
341/*
342 coverage_group ncu_intr_pairs_cov2
343 {
344 const_sample_reference = 1; // ref. to sample vars. is constant
345 sample_event = @(negedge ncu_rtl_io_cov.clk);
346 #include "ncu_int2_sample.vrh"
347 } // ncu_intr_pairs_cov2
348*/
349
350//-------------- vald counter before stall assert ------------------------
351 coverage_group ncu_dbg1_vld_to_stall_group
352 {
353 const_sample_reference = 1; // ref. to sample vars. is constant
354 sample_event = @(posedge ncu_cov_ios.dbg1_ncu_stall);
355 sample ncu_dbg1_intf_vld_to_stall_cnt_cov (ncu_dbg1_vld_to_stall_cnt) {
356 m_state VLD2STALL_CNT (1:31);
357 }
358 } // ncu_nucb_intf_cov_group
359/*
360 coverage_group dbg1_ncu_vld_to_stall_group
361 {
362 const_sample_reference = 1; // ref. to sample vars. is constant
363 sample_event = @(posedge ncu_cov_ios.ncu_dbg1_stall);
364 sample dbg1_ncu_intf_vld_to_stall_cnt_cov (dbg1_ncu_vld_to_stall_cnt) {
365 m_state VLD2STALL_CNT (1:31);
366 }
367 } // dbg1_ncu_intf_cov_group1
368*/
369 coverage_group ncu_tcu_vld_to_stall_group
370 {
371 const_sample_reference = 1; // ref. to sample vars. is constant
372 sample_event = @(posedge ncu_cov_ios.tcu_ncu_stall);
373 sample ncu_tcu_intf_vld_to_stall_cnt_cov (ncu_tcu_vld_to_stall_cnt) {
374 m_state VLD2STALL_CNT (1:15);
375 }
376 } // ncu_nucb_intf_cov_group
377/*
378 coverage_group tcu_ncu_vld_to_stall_group
379 {
380 const_sample_reference = 1; // ref. to sample vars. is constant
381 sample_event = @(posedge ncu_cov_ios.ncu_tcu_stall);
382 sample tcu_ncu_intf_vld_to_stall_cnt_cov (tcu_ncu_vld_to_stall_cnt) {
383 m_state VLD2STALL_CNT (1:15);
384 }
385 } // tcu_ncu_intf_cov_group1
386*/
387
388 coverage_group ncu_ccu_vld_to_stall_group
389 {
390 const_sample_reference = 1; // ref. to sample vars. is constant
391 sample_event = @(posedge ncu_cov_ios.ccu_ncu_stall);
392 sample ncu_ccu_intf_vld_to_stall_cnt_cov (ncu_ccu_vld_to_stall_cnt) {
393 m_state VLD2STALL_CNT (1:31);
394 }
395 } // ncu_nucb_intf_cov_group
396/*
397 coverage_group ccu_ncu_vld_to_stall_group
398 {
399 const_sample_reference = 1; // ref. to sample vars. is constant
400 sample_event = @(posedge ncu_cov_ios.ncu_ccu_stall);
401 sample ccu_ncu_intf_vld_to_stall_cnt_cov (ccu_ncu_vld_to_stall_cnt) {
402 m_state VLD2STALL_CNT (1:31);
403 }
404 } // ccu_ncu_intf_cov_group1
405*/
406 coverage_group ncu_rst_vld_to_stall_group
407 {
408 const_sample_reference = 1; // ref. to sample vars. is constant
409 sample_event = @(posedge ncu_cov_ios.rst_ncu_stall);
410 sample ncu_rst_intf_vld_to_stall_cnt_cov (ncu_rst_vld_to_stall_cnt) {
411 m_state VLD2STALL_CNT (1:31);
412 }
413 } // ncu_nucb_intf_cov_group
414/*
415 coverage_group rst_ncu_vld_to_stall_group
416 {
417 const_sample_reference = 1; // ref. to sample vars. is constant
418 sample_event = @(posedge ncu_cov_ios.ncu_rst_stall);
419 sample rst_ncu_intf_vld_to_stall_cnt_cov (rst_ncu_vld_to_stall_cnt) {
420 m_state VLD2STALL_CNT (1:31);
421 }
422 } // rst_ncu_intf_cov_group1
423*/
424
425.for($b=0; $b<4; $b++) {
426 coverage_group ncu_mcu${b}_vld_to_stall_group
427 {
428 const_sample_reference = 1; // ref. to sample vars. is constant
429 sample_event = @(posedge ncu_cov_ios.mcu${b}_ncu_stall);
430 sample ncu_mcu${b}_intf_vld_to_stall_cnt_cov (ncu_mcu${b}_vld_to_stall_cnt) {
431 m_state VLD2STALL_CNT (1:31);
432 }
433 } // ncu_mcu_intf_cov_group
434.}
435
436/*
437.for($b=0; $b<4; $b++) {
438 coverage_group mcu${b}_ncu_vld_to_stall_group
439 {
440 const_sample_reference = 1; // ref. to sample vars. is constant
441 sample_event = @(posedge ncu_cov_ios.ncu_mcu${b}_stall);
442 sample mcu${b}_ncu_intf_vld_to_stall_cnt_cov (mcu${b}_ncu_vld_to_stall_cnt) {
443 m_state VLD2STALL_CNT (1:31);
444 }
445 } // mcu_ncu_intf_cov_group
446.}
447*/
448
449 coverage_group ncu_niu_vld_to_stall_group
450 {
451 const_sample_reference = 1; // ref. to sample vars. is constant
452 sample_event = @(posedge ncu_cov_ios.niu_ncu_stall);
453 sample ncu_niu_intf_vld_to_stall_cnt_cov (ncu_niu_vld_to_stall_cnt) {
454 m_state VLD2STALL_CNT (1:3);
455 }
456 } // ncu_nucb_intf_cov_group
457/*
458 coverage_group niu_ncu_vld_to_stall_group
459 {
460 const_sample_reference = 1; // ref. to sample vars. is constant
461 sample_event = @(posedge ncu_cov_ios.ncu_niu_stall);
462 sample niu_ncu_intf_vld_to_stall_cnt_cov (niu_ncu_vld_to_stall_cnt) {
463 m_state VLD2STALL_CNT (1:3);
464 }
465 } // niu_ncu_intf_cov_group1
466*/
467
468 coverage_group ncu_dmu_vld_to_stall_group
469 {
470 const_sample_reference = 1; // ref. to sample vars. is constant
471 sample_event = @(posedge ncu_cov_ios.dmu_ncu_stall);
472 sample ncu_dmu_intf_vld_to_stall_cnt_cov (ncu_dmu_vld_to_stall_cnt) {
473 m_state VLD2STALL_CNT (1:3);
474 }
475 } // ncu_nucb_intf_cov_group
476/*
477 coverage_group dmu_ncu_vld_to_stall_group
478 {
479 const_sample_reference = 1; // ref. to sample vars. is constant
480 sample_event = @(posedge ncu_cov_ios.ncu_dmu_stall);
481 sample dmu_ncu_intf_vld_to_stall_cnt_cov (dmu_ncu_vld_to_stall_cnt) {
482 m_state VLD2STALL_CNT (1:3);
483 }
484 } // dmu_ncu_intf_cov_group1
485*/
486
487 coverage_group ncu_spc_bnk_intf_cov_group
488 {
489 const_sample_reference = 1; // ref. to sample vars. is constant
490 sample_event = sync (ANY, ncu_spc_bnk_evnt_trig);
491 #include "ncu_spc_bnk_intf_sample.vrh"
492 } // ncu_spc_bnk_intf_cov_group
493
494#ifdef FC_COVERAGE
495/*
496//----------NCU -> SPC-------------------
497 coverage_group ncu_spc_intf_enable_cov_group
498 {
499 const_sample_reference = 1; // ref. to sample vars. is constant
500 sample_event = sync (ANY, ncu_spc_enable1_evnt_trig, ncu_spc_enable2_evnt_trig, ncu_spc_enable3_evnt_trig, ncu_spc_enable4_evnt_trig, ncu_spc_enable5_evnt_trig, ncu_spc_enable6_evnt_trig, ncu_spc_enable7_evnt_trig );
501 #include "ncu_spc_intf_enable_sample.vrh"
502 } // ncu_spc_intf_enable_cov_group
503*/
504//----------SPC -> NCU-------------------
505 coverage_group spc0_ncu_intf_thread_cov_group
506 {
507 const_sample_reference = 1; // ref. to sample vars. is constant
508 sample_event = sync (ANY, spc0_ncu_thread1_evnt_trig, spc1_ncu_thread1_evnt_trig, spc2_ncu_thread1_evnt_trig, spc3_ncu_thread1_evnt_trig, spc4_ncu_thread1_evnt_trig, spc5_ncu_thread1_evnt_trig, spc6_ncu_thread1_evnt_trig, spc7_ncu_thread1_evnt_trig );
509 #include "spc0_ncu_intf_thread_sample.vrh"
510 } // spc0_ncu_intf_thread_cov_group
511
512//----------SPC -> NCU-------------------
513 coverage_group spc1_ncu_intf_thread_cov_group
514 {
515 const_sample_reference = 1; // ref. to sample vars. is constant
516 sample_event = sync (ANY, spc0_ncu_thread2_evnt_trig, spc1_ncu_thread2_evnt_trig, spc2_ncu_thread2_evnt_trig, spc3_ncu_thread2_evnt_trig, spc4_ncu_thread2_evnt_trig, spc5_ncu_thread2_evnt_trig, spc6_ncu_thread2_evnt_trig, spc7_ncu_thread2_evnt_trig );
517 #include "spc1_ncu_intf_thread_sample.vrh"
518 } // spc1_ncu_intf_thread_cov_group
519
520//----------SPC -> NCU-------------------
521 coverage_group spc2_ncu_intf_thread_cov_group
522 {
523 const_sample_reference = 1; // ref. to sample vars. is constant
524 sample_event = sync (ANY, spc0_ncu_thread3_evnt_trig, spc1_ncu_thread3_evnt_trig, spc2_ncu_thread3_evnt_trig, spc3_ncu_thread3_evnt_trig, spc4_ncu_thread3_evnt_trig, spc5_ncu_thread3_evnt_trig, spc6_ncu_thread3_evnt_trig, spc7_ncu_thread3_evnt_trig );
525 #include "spc2_ncu_intf_thread_sample.vrh"
526 } // spc2_ncu_intf_thread_cov_group
527
528//----------SPC -> NCU-------------------
529 coverage_group spc3_ncu_intf_thread_cov_group
530 {
531 const_sample_reference = 1; // ref. to sample vars. is constant
532 sample_event = sync (ANY, spc0_ncu_thread4_evnt_trig, spc1_ncu_thread4_evnt_trig, spc2_ncu_thread4_evnt_trig, spc3_ncu_thread4_evnt_trig, spc4_ncu_thread4_evnt_trig, spc5_ncu_thread4_evnt_trig, spc6_ncu_thread4_evnt_trig, spc7_ncu_thread4_evnt_trig );
533 #include "spc3_ncu_intf_thread_sample.vrh"
534 } // spc3_ncu_intf_thread_cov_group
535
536//----------SPC -> NCU-------------------
537 coverage_group spc4_ncu_intf_thread_cov_group
538 {
539 const_sample_reference = 1; // ref. to sample vars. is constant
540 sample_event = sync (ANY, spc0_ncu_thread5_evnt_trig, spc1_ncu_thread5_evnt_trig, spc2_ncu_thread5_evnt_trig, spc3_ncu_thread5_evnt_trig, spc4_ncu_thread5_evnt_trig, spc5_ncu_thread5_evnt_trig, spc6_ncu_thread5_evnt_trig, spc7_ncu_thread5_evnt_trig );
541 #include "spc4_ncu_intf_thread_sample.vrh"
542 } // spc4_ncu_intf_thread_cov_group
543
544//----------SPC -> NCU-------------------
545 coverage_group spc5_ncu_intf_thread_cov_group
546 {
547 const_sample_reference = 1; // ref. to sample vars. is constant
548 sample_event = sync (ANY, spc0_ncu_thread6_evnt_trig, spc1_ncu_thread6_evnt_trig, spc2_ncu_thread6_evnt_trig, spc3_ncu_thread6_evnt_trig, spc4_ncu_thread6_evnt_trig, spc5_ncu_thread6_evnt_trig, spc6_ncu_thread6_evnt_trig, spc7_ncu_thread6_evnt_trig );
549 #include "spc5_ncu_intf_thread_sample.vrh"
550 } // spc5_ncu_intf_thread_cov_group
551
552//----------SPC -> NCU-------------------
553 coverage_group spc6_ncu_intf_thread_cov_group
554 {
555 const_sample_reference = 1; // ref. to sample vars. is constant
556 sample_event = sync (ANY, spc0_ncu_thread7_evnt_trig, spc1_ncu_thread7_evnt_trig, spc2_ncu_thread7_evnt_trig, spc3_ncu_thread7_evnt_trig, spc4_ncu_thread7_evnt_trig, spc5_ncu_thread7_evnt_trig, spc6_ncu_thread7_evnt_trig, spc7_ncu_thread7_evnt_trig );
557 #include "spc6_ncu_intf_thread_sample.vrh"
558 } // spc6_ncu_intf_thread_cov_group
559
560//----------SPC -> NCU-------------------
561 coverage_group spc7_ncu_intf_thread_cov_group
562 {
563 const_sample_reference = 1; // ref. to sample vars. is constant
564 sample_event = sync (ANY, spc0_ncu_thread8_evnt_trig, spc1_ncu_thread8_evnt_trig, spc2_ncu_thread8_evnt_trig, spc3_ncu_thread8_evnt_trig, spc4_ncu_thread8_evnt_trig, spc5_ncu_thread8_evnt_trig, spc6_ncu_thread8_evnt_trig, spc7_ncu_thread8_evnt_trig );
565 #include "spc7_ncu_intf_thread_sample.vrh"
566 } // spc7_ncu_intf_thread_cov_group
567
568//----------SPC -> NCU-------------------
569 coverage_group spc0_ncu_intf_thread_10_cov_group
570 {
571 const_sample_reference = 1; // ref. to sample vars. is constant
572 sample_event = sync (ANY, spc0_ncu_thread1_10_evnt_trig, spc1_ncu_thread1_10_evnt_trig, spc2_ncu_thread1_10_evnt_trig, spc3_ncu_thread1_10_evnt_trig, spc4_ncu_thread1_10_evnt_trig, spc5_ncu_thread1_10_evnt_trig, spc6_ncu_thread1_10_evnt_trig, spc7_ncu_thread1_10_evnt_trig );
573 #include "spc0_ncu_intf_thread_10_sample.vrh"
574 } // spc0_ncu_intf_thread_10_cov_group
575
576//----------SPC -> NCU-------------------
577 coverage_group spc1_ncu_intf_thread_10_cov_group
578 {
579 const_sample_reference = 1; // ref. to sample vars. is constant
580 sample_event = sync (ANY, spc0_ncu_thread2_10_evnt_trig, spc1_ncu_thread2_10_evnt_trig, spc2_ncu_thread2_10_evnt_trig, spc3_ncu_thread2_10_evnt_trig, spc4_ncu_thread2_10_evnt_trig, spc5_ncu_thread2_10_evnt_trig, spc6_ncu_thread2_10_evnt_trig, spc7_ncu_thread2_evnt_trig );
581 #include "spc1_ncu_intf_thread_10_sample.vrh"
582 } // spc1_ncu_intf_thread_10_cov_group
583
584//----------SPC -> NCU-------------------
585 coverage_group spc2_ncu_intf_thread_10_cov_group
586 {
587 const_sample_reference = 1; // ref. to sample vars. is constant
588 sample_event = sync (ANY, spc0_ncu_thread3_10_evnt_trig, spc1_ncu_thread3_10_evnt_trig, spc2_ncu_thread3_10_evnt_trig, spc3_ncu_thread3_10_evnt_trig, spc4_ncu_thread3_10_evnt_trig, spc5_ncu_thread3_10_evnt_trig, spc6_ncu_thread3_10_evnt_trig, spc7_ncu_thread3_10_evnt_trig );
589 #include "spc2_ncu_intf_thread_10_sample.vrh"
590 } // spc2_ncu_intf_thread_10_cov_group
591
592//----------SPC -> NCU-------------------
593 coverage_group spc3_ncu_intf_thread_10_cov_group
594 {
595 const_sample_reference = 1; // ref. to sample vars. is constant
596 sample_event = sync (ANY, spc0_ncu_thread4_10_evnt_trig, spc1_ncu_thread4_10_evnt_trig, spc2_ncu_thread4_10_evnt_trig, spc3_ncu_thread4_10_evnt_trig, spc4_ncu_thread4_10_evnt_trig, spc5_ncu_thread4_10_evnt_trig, spc6_ncu_thread4_10_evnt_trig, spc7_ncu_thread4_10_evnt_trig );
597 #include "spc3_ncu_intf_thread_10_sample.vrh"
598 } // spc3_ncu_intf_thread_10_cov_group
599
600//----------SPC -> NCU-------------------
601 coverage_group spc4_ncu_intf_thread_10_cov_group
602 {
603 const_sample_reference = 1; // ref. to sample vars. is constant
604 sample_event = sync (ANY, spc0_ncu_thread5_10_evnt_trig, spc1_ncu_thread5_10_evnt_trig, spc2_ncu_thread5_10_evnt_trig, spc3_ncu_thread5_10_evnt_trig, spc4_ncu_thread5_10_evnt_trig, spc5_ncu_thread5_10_evnt_trig, spc6_ncu_thread5_10_evnt_trig, spc7_ncu_thread5_10_evnt_trig );
605 #include "spc4_ncu_intf_thread_10_sample.vrh"
606 } // spc4_ncu_intf_thread_10_cov_group
607
608//----------SPC -> NCU-------------------
609 coverage_group spc5_ncu_intf_thread_10_cov_group
610 {
611 const_sample_reference = 1; // ref. to sample vars. is constant
612 sample_event = sync (ANY, spc0_ncu_thread6_10_evnt_trig, spc1_ncu_thread6_10_evnt_trig, spc2_ncu_thread6_10_evnt_trig, spc3_ncu_thread6_10_evnt_trig, spc4_ncu_thread6_10_evnt_trig, spc5_ncu_thread6_10_evnt_trig, spc6_ncu_thread6_10_evnt_trig, spc7_ncu_thread6_10_evnt_trig );
613 #include "spc5_ncu_intf_thread_10_sample.vrh"
614 } // spc5_ncu_intf_thread_10_cov_group
615
616//----------SPC -> NCU-------------------
617 coverage_group spc6_ncu_intf_thread_10_cov_group
618 {
619 const_sample_reference = 1; // ref. to sample vars. is constant
620 sample_event = sync (ANY, spc0_ncu_thread7_10_evnt_trig, spc1_ncu_thread7_10_evnt_trig, spc2_ncu_thread7_10_evnt_trig, spc3_ncu_thread7_10_evnt_trig, spc4_ncu_thread7_10_evnt_trig, spc5_ncu_thread7_10_evnt_trig, spc6_ncu_thread7_10_evnt_trig, spc7_ncu_thread7_10_evnt_trig );
621 #include "spc6_ncu_intf_thread_10_sample.vrh"
622 } // spc6_ncu_intf_thread_10_cov_group
623
624//----------SPC -> NCU-------------------
625 coverage_group spc7_ncu_intf_thread_10_cov_group
626 {
627 const_sample_reference = 1; // ref. to sample vars. is constant
628 sample_event = sync (ANY, spc0_ncu_thread8_10_evnt_trig, spc1_ncu_thread8_10_evnt_trig, spc2_ncu_thread8_10_evnt_trig, spc3_ncu_thread8_10_evnt_trig, spc4_ncu_thread8_10_evnt_trig, spc5_ncu_thread8_10_evnt_trig, spc6_ncu_thread8_10_evnt_trig, spc7_ncu_thread8_10_evnt_trig );
629 #include "spc7_ncu_intf_thread_10_sample.vrh"
630 } // spc7_ncu_intf_thread_10_cov_group
631
632//----------SPC -> NCU-------------------
633 coverage_group spc_ncu_intf_thread_50_cov_group
634 {
635 const_sample_reference = 1; // ref. to sample vars. is constant
636 sample_event = sync (ANY, spc_ncu_thread_50_evnt_trig, spc_ncu_thread_100_evnt_trig );
637 #include "spc_ncu_intf_thread_50_sample.vrh"
638 } // spc_ncu_intf_thread_50_cov_group
639
640#endif
641#endif
642
643//----------SPC -> NCU-------------------
644 coverage_group dmu_ncu_intf_intr_all_ic_waiting_cov_group
645 {
646 const_sample_reference = 1; // ref. to sample vars. is constant
647 sample_event = sync (ANY, mondo_wait_id_reg_cov_trig);
648 sample dmu_ncu_intf_intr_all_ic_waiting_cov ({mondo_wait_id_reg_cov3, mondo_wait_id_reg_cov2, mondo_wait_id_reg_cov1, mondo_wait_id_reg_cov0})
649 {
650 wildcard state MONDOID0 ( 16'bxxxxxxxxxxxx1111);
651 wildcard state MONDOID1 ( 16'bxxxxxxxx1111xxxx);
652 wildcard state MONDOID2 ( 16'bxxxx1111xxxxxxxx);
653 wildcard state MONDOID3 ( 16'b1111xxxxxxxxxxxx);
654 }
655 } // spc_ncu_intf_thread_50_cov_group
656
657
658
659
660
661
662 task new(string myname, StandardDisplay dbg);
663
664 task set_ncu_ras_cov_point (string myname);
665 task set_ncu_io_mix_points (string myname);
666 task set_efu_ncu_points (string myname, reg [6:0] tran_cnt, var reg [63:0] data, ncu_cov_efu_port efu);
667 task set_int_pkt_points (string myname);
668 function reg count_pkt_num(string myname, reg [1000:0] base_reg, reg [9:0] pkt_num);
669#ifdef FC_COVERAGE
670 task set_ncu_spc_intf_cov_point (string myname);
671#endif
672 task set_ncu_ras_soc_report_point (string myname, ncu_cov_com_io_port ncu_pcxpt, ncu_cov_cpx_port cpxpt);
673 task set_ncu_pcx_cov_point (string myname, ncu_cov_com_io_port ncu_pcxpt);
674 task set_cpx_cov_point (string myname, ncu_cov_cpx_port cpxpt);
675 task set_siu_cov_point (string myname, ncu_cov_siu_port siupt);
676 task set_pio_cov_point (string myname, ncu_cov_pio_port piopt);
677 task set_mondo_cov_point (string myname, reg [1:0] mondo_id, var reg [3:0] mondo_wait_id_reg, reg mondo_type=0);
678 task detect_other_mondo_int (string myname, reg [1:0] mondo_id, reg [1:0] detect_mondo_id, var reg mondo_req_ack_hit);
679 task set_err_cnt_cov_point (string myname, reg [19:0] intf_err, reg [7:0] multi_err_sign_reg_idx, reg which_type = 0);
680
681 task set_ncu_ucb_cov_point(string myname,
682 reg [5:0] ucb_data_width,
683 var reg [3:0] ncu_ucb_type,
684 var reg [5:0] ncu_ucb_cpuid ,
685 var reg [1:0] ncu_ucb_bufid ,
686 var reg [39:0] ncu_ucb_add ,
687 var reg [2:0] ncu_ucb_size ,
688 var reg [31:0] b2b_cnt,
689 var reg [31:0] stall_b2b_cnt,
690 var reg [31:0] vld_to_stall_cnt,
691 var reg [31:0] ucb_pkt_gap,
692 ncu_cov_com_io_port1 dw_ucbpt,
693 var event ncu_ucb_sample_evnt_trig);
694
695 task set_ucb_ncu_cov_point(string myname,
696 reg [5:0] ucb_data_width,
697 var reg [3:0] ucb_ncu_type,
698 var reg [5:0] ucb_ncu_cpuid,
699 var reg [1:0] ucb_ncu_bufid,
700 var reg [8:0] ucb_ncu_deviceid,
701 var reg [5:0] ucb_ncu_int_vec,
702 var reg [2:0] ucb_ncu_size,
703 var reg [31:0] b2b_cnt,
704 var reg [31:0] stall_b2b_cnt,
705 var reg [31:0] vld_to_stall_cnt,
706 var reg [31:0] ucb_pkt_gap,
707 ncu_cov_com_io_port up_ucbpt,
708 var event ucb_ncu_sample_evnt_trig);
709
710} //class ncu_intf_cov
711
712
713/////////////////////////////////////////////////////////////////
714// Class creation
715/////////////////////////////////////////////////////////////////
716task ncu_intf_cov::new(string myname, StandardDisplay dbg)
717{
718
719 // for dispmon
720 reg [3:0] dummy_data;
721
722 this.myname = myname;
723 this.dbg = dbg;
724
725
726
727 dmu_ncu_intf_intr_all_ic_waiting_cov_group = new();
728 ncu_ras_report_cov_group = new();
729 ncu_ios_cov_group = new();
730 ncu_ras_cov_group = new();
731#ifndef IOS_COVERAGE
732 ncu_niu_intf_cov_group = new();
733 niu_ncu_intf_cov_group = new();
734 ncu_dmu_intf_cov_group = new();
735 dmu_ncu_intf_cov_group = new();
736 ncu_pcx_intf_cov_group = new();
737 ncu_cpx_intf_cov_group = new();
738 ncu_tcu_intf_cov_group = new();
739 tcu_ncu_intf_cov_group = new();
740 ncu_rst_intf_cov_group = new();
741 rst_ncu_intf_cov_group = new();
742 ncu_ccu_intf_cov_group = new();
743 ccu_ncu_intf_cov_group = new();
744 ncu_spc_bnk_intf_cov_group = new();
745 #ifdef FC_COVERAGE
746 //ncu_spc_intf_enable_cov_group = new();
747 spc0_ncu_intf_thread_cov_group = new();
748 spc1_ncu_intf_thread_cov_group = new();
749 spc2_ncu_intf_thread_cov_group = new();
750 spc3_ncu_intf_thread_cov_group = new();
751 spc4_ncu_intf_thread_cov_group = new();
752 spc5_ncu_intf_thread_cov_group = new();
753 spc6_ncu_intf_thread_cov_group = new();
754 spc7_ncu_intf_thread_cov_group = new();
755 spc0_ncu_intf_thread_10_cov_group = new();
756 spc1_ncu_intf_thread_10_cov_group = new();
757 spc2_ncu_intf_thread_10_cov_group = new();
758 spc3_ncu_intf_thread_10_cov_group = new();
759 spc4_ncu_intf_thread_10_cov_group = new();
760 spc5_ncu_intf_thread_10_cov_group = new();
761 spc6_ncu_intf_thread_10_cov_group = new();
762 spc7_ncu_intf_thread_10_cov_group = new();
763 spc_ncu_intf_thread_50_cov_group = new();
764 #endif
765.for($b=0; $b<4; $b++) {
766 ncu_mcu${b}_intf_cov_group = new();
767 mcu${b}_ncu_intf_cov_group = new();
768.}
769#endif
770
771 fork
772 set_int_pkt_points("ncu_intf_cov");
773 set_ncu_ras_soc_report_point ({myname, ".sco_report"}, ncu_cov_ccx_exp_bind, ncu_cov_ccx_up_bind);
774 set_ncu_ras_cov_point ({myname, ".ncu_ras_intf"});
775#ifndef IOS_COVERAGE
776 set_ncu_io_mix_points ({myname, ".ncu_spc_intf"});
777 set_efu_ncu_points ("EFU_SERNUM0", 22, efu_ncu_sernum0, ncu_cov_sernum_bind0);
778 set_efu_ncu_points ("EFU_SERNUM1", 22, efu_ncu_sernum1, ncu_cov_sernum_bind1);
779 set_efu_ncu_points ("EFU_SERNUM2", 22, efu_ncu_sernum2, ncu_cov_sernum_bind2);
780 set_efu_ncu_points ("EFU_COREAVAIL", 22, efu_ncu_coreaval, ncu_cov_coreavail_bind);
781 set_efu_ncu_points ("EFU_BANKAVAIL", 22, efu_ncu_bankaval, ncu_cov_bankavail_bind);
782 set_efu_ncu_points ("EFU_FUSESTAT", 64, efu_ncu_efustat, ncu_cov_fuestat_bind);
783#ifdef FC_COVERAGE
784 set_ncu_spc_intf_cov_point ({myname, ".ncu_spc_intf"});
785#endif
786 set_ncu_pcx_cov_point ({myname, ".ncu_pcx"}, ncu_cov_ccx_exp_bind);
787 set_cpx_cov_point ({myname, ".cpx"}, ncu_cov_ccx_up_bind);
788 set_siu_cov_point ({myname, ".siu"}, ncu_cov_siu_exp_bind);
789 set_pio_cov_point ({myname, ".pio"}, ncu_cov_pio_dw_bind);
790
791 set_mondo_cov_point (myname, 0, mondo_wait_id_reg_cov0);
792 set_mondo_cov_point (myname, 1, mondo_wait_id_reg_cov1);
793 set_mondo_cov_point (myname, 2, mondo_wait_id_reg_cov2);
794 set_mondo_cov_point (myname, 3, mondo_wait_id_reg_cov3);
795 set_mondo_cov_point (myname, 0, dummy_data,1);
796
797 set_ncu_ucb_cov_point({myname, ".ncu_niu"},
798 32,
799 ncu_niu_type,
800 ncu_niu_cpuid ,
801 ncu_niu_bufid ,
802 ncu_niu_add ,
803 ncu_niu_size ,
804 ncu_niu_b2b,
805 niu_ncu_stall_b2b,
806 ncu_niu_vld_to_stall_cnt,
807 ncu_niu_pkt_gap,
808 ncu_cov_niu_dw_bind,
809 ncu_niu_sample_evnt_trig);
810
811 set_ucb_ncu_cov_point({myname, ".niu_ncu"} ,
812 32,
813 niu_ncu_type,
814 niu_ncu_cpuid,
815 niu_ncu_bufid,
816 niu_ncu_deviceid,
817 niu_ncu_int_vec,
818 niu_ncu_size,
819 niu_ncu_b2b,
820 ncu_niu_stall_b2b,
821 niu_ncu_vld_to_stall_cnt,
822 niu_ncu_pkt_gap,
823 ncu_cov_niu_exp_bind ,
824 niu_ncu_sample_evnt_trig);
825
826 set_ncu_ucb_cov_point({myname, ".ncu_dmu"},
827 32,
828 ncu_dmu_type,
829 ncu_dmu_cpuid ,
830 ncu_dmu_bufid ,
831 ncu_dmu_add ,
832 ncu_dmu_size ,
833 ncu_dmu_b2b,
834 dmu_ncu_stall_b2b,
835 ncu_dmu_vld_to_stall_cnt,
836 ncu_dmu_pkt_gap,
837 ncu_cov_dmu_dw_bind,
838 ncu_dmu_sample_evnt_trig);
839
840 set_ucb_ncu_cov_point({myname, ".dmu_ncu"} ,
841 32,
842 dmu_ncu_type,
843 dmu_ncu_cpuid,
844 dmu_ncu_bufid,
845 dmu_ncu_deviceid,
846 dmu_ncu_int_vec,
847 dmu_ncu_size,
848 dmu_ncu_b2b,
849 ncu_dmu_stall_b2b,
850 dmu_ncu_vld_to_stall_cnt,
851 dmu_ncu_pkt_gap,
852 ncu_cov_dmu_exp_bind ,
853 dmu_ncu_sample_evnt_trig);
854
855 set_ncu_ucb_cov_point({myname, ".ncu_dbg1"},
856 4,
857 ncu_dbg1_type,
858 ncu_dbg1_cpuid ,
859 ncu_dbg1_bufid ,
860 ncu_dbg1_add ,
861 ncu_dbg1_size ,
862 ncu_dbg1_b2b,
863 dbg1_ncu_stall_b2b,
864 ncu_dbg1_vld_to_stall_cnt,
865 ncu_dbg1_pkt_gap,
866 ncu_cov_dbg1_dw_bind,
867 ncu_dbg1_sample_evnt_trig);
868
869 set_ucb_ncu_cov_point({myname, ".dbg1_ncu"} ,
870 4,
871 dbg1_ncu_type,
872 dbg1_ncu_cpuid,
873 dbg1_ncu_bufid,
874 dbg1_ncu_deviceid,
875 dbg1_ncu_int_vec,
876 dbg1_ncu_size,
877 dbg1_ncu_b2b,
878 ncu_dbg1_stall_b2b,
879 dbg1_ncu_vld_to_stall_cnt,
880 dbg1_ncu_pkt_gap,
881 ncu_cov_dbg1_exp_bind ,
882 dbg1_ncu_sample_evnt_trig);
883
884 set_ncu_ucb_cov_point({myname, ".ncu_rst"},
885 4,
886 ncu_rst_type,
887 ncu_rst_cpuid ,
888 ncu_rst_bufid ,
889 ncu_rst_add ,
890 ncu_rst_size ,
891 ncu_rst_b2b,
892 rst_ncu_stall_b2b,
893 ncu_rst_vld_to_stall_cnt,
894 ncu_rst_pkt_gap,
895 ncu_cov_rst_dw_bind,
896 ncu_rst_sample_evnt_trig);
897
898
899 set_ucb_ncu_cov_point({myname, ".rst_ncu"} ,
900 4,
901 rst_ncu_type,
902 rst_ncu_cpuid,
903 rst_ncu_bufid,
904 rst_ncu_deviceid,
905 rst_ncu_int_vec,
906 rst_ncu_size,
907 rst_ncu_b2b,
908 ncu_rst_stall_b2b,
909 rst_ncu_vld_to_stall_cnt,
910 rst_ncu_pkt_gap,
911 ncu_cov_rst_exp_bind ,
912 rst_ncu_sample_evnt_trig);
913
914
915 set_ncu_ucb_cov_point({myname, ".ncu_ccu"},
916 4,
917 ncu_ccu_type,
918 ncu_ccu_cpuid ,
919 ncu_ccu_bufid ,
920 ncu_ccu_add ,
921 ncu_ccu_size ,
922 ncu_ccu_b2b,
923 ccu_ncu_stall_b2b,
924 ncu_ccu_vld_to_stall_cnt,
925 ncu_ccu_pkt_gap,
926 ncu_cov_ccu_dw_bind,
927 ncu_ccu_sample_evnt_trig);
928
929 set_ucb_ncu_cov_point({myname, ".ccu_ncu"} ,
930 4,
931 ccu_ncu_type,
932 ccu_ncu_cpuid,
933 ccu_ncu_bufid,
934 ccu_ncu_deviceid,
935 ccu_ncu_int_vec,
936 ccu_ncu_size,
937 ccu_ncu_b2b,
938 ncu_ccu_stall_b2b,
939 ccu_ncu_vld_to_stall_cnt,
940 ccu_ncu_pkt_gap,
941 ncu_cov_ccu_exp_bind ,
942 ccu_ncu_sample_evnt_trig);
943
944
945.for($b=0; $b<4; $b++) {
946 set_ncu_ucb_cov_point({myname, ".ncu_mcu{$b}"},
947 4,
948 ncu_mcu${b}_type,
949 ncu_mcu${b}_cpuid ,
950 ncu_mcu${b}_bufid ,
951 ncu_mcu${b}_add ,
952 ncu_mcu${b}_size ,
953 ncu_mcu${b}_b2b,
954 mcu${b}_ncu_stall_b2b,
955 ncu_mcu${b}_vld_to_stall_cnt,
956 ncu_mcu${b}_pkt_gap,
957 ncu_cov_mcu_dw_bind${b},
958 ncu_mcu${b}_sample_evnt_trig);
959
960 set_ucb_ncu_cov_point({myname, ".mcu${b}_ncu"} ,
961 4,
962 mcu${b}_ncu_type,
963 mcu${b}_ncu_cpuid,
964 mcu${b}_ncu_bufid,
965 mcu${b}_ncu_deviceid,
966 mcu${b}_ncu_int_vec,
967 mcu${b}_ncu_size,
968 mcu${b}_ncu_b2b,
969 ncu_mcu${b}_stall_b2b,
970 mcu${b}_ncu_vld_to_stall_cnt,
971 mcu${b}_ncu_pkt_gap,
972 ncu_cov_mcu_exp_bind${b} ,
973 mcu${b}_ncu_sample_evnt_trig);
974.}
975
976
977 set_ncu_ucb_cov_point({myname, ".ncu_ssi"},
978 4,
979 ncu_ssi_type,
980 ncu_ssi_cpuid ,
981 ncu_ssi_bufid ,
982 ncu_ssi_add ,
983 ncu_ssi_size ,
984 ncu_ssi_b2b,
985 ssi_ncu_stall_b2b,
986 ncu_ssi_vld_to_stall_cnt,
987 ncu_ssi_pkt_gap,
988 ncu_cov_ssi_dw_bind,
989 ncu_ssi_sample_evnt_trig);
990
991 set_ucb_ncu_cov_point({myname, ".ssi_ncu"} ,
992 4,
993 ssi_ncu_type,
994 ssi_ncu_cpuid,
995 ssi_ncu_bufid,
996 ssi_ncu_deviceid,
997 ssi_ncu_int_vec,
998 ssi_ncu_size,
999 ssi_ncu_b2b,
1000 ncu_ssi_stall_b2b,
1001 ssi_ncu_vld_to_stall_cnt,
1002 ssi_ncu_pkt_gap,
1003 ncu_cov_ssi_exp_bind ,
1004 ssi_ncu_sample_evnt_trig);
1005
1006 set_ncu_ucb_cov_point({myname, ".ncu_tcu"},
1007 8,
1008 ncu_tcu_type,
1009 ncu_tcu_cpuid ,
1010 ncu_tcu_bufid ,
1011 ncu_tcu_add ,
1012 ncu_tcu_size ,
1013 ncu_tcu_b2b,
1014 tcu_ncu_stall_b2b,
1015 ncu_tcu_vld_to_stall_cnt,
1016 ncu_tcu_pkt_gap,
1017 ncu_cov_tcu_dw_bind,
1018 ncu_tcu_sample_evnt_trig);
1019
1020 set_ucb_ncu_cov_point({myname, ".tcu_ncu"} ,
1021 8,
1022 tcu_ncu_type,
1023 tcu_ncu_cpuid,
1024 tcu_ncu_bufid,
1025 tcu_ncu_deviceid,
1026 tcu_ncu_int_vec,
1027 tcu_ncu_size,
1028 tcu_ncu_b2b,
1029 ncu_tcu_stall_b2b,
1030 tcu_ncu_vld_to_stall_cnt,
1031 tcu_ncu_pkt_gap,
1032 ncu_cov_tcu_exp_bind ,
1033 tcu_ncu_sample_evnt_trig);
1034#endif // IOS_COVERAGE
1035
1036
1037 join none
1038
1039
1040} // ncu_intf_cov::new()
1041
1042task ncu_intf_cov::set_err_cnt_cov_point (string myname, reg [19:0] intf_err, reg [7:0] multi_err_sign_reg_idx, reg which_type = 0)
1043{
1044reg [6:0] merr_cnt = 0;
1045reg [5:0] err_idx=0;
1046
1047myname = {myname, ".set_err_cnt_cov_point"};
1048
1049 if (|intf_err){
1050 merr_cnt = 0;
1051 for (err_idx=0; err_idx <20; err_idx++){
1052 if (intf_err[err_idx]){
1053 merr_cnt++;
1054 }
1055 }
1056 if (!which_type){
1057 if (merr_cnt >=2){
1058 multi_err_sign_reg[multi_err_sign_reg_idx+0] = 1'b1;
1059 }
1060 } else {
1061 if (merr_cnt >=3 ) {
1062 multi_err_sign_reg[multi_err_sign_reg_idx+0] = 1'b1;
1063 }
1064 if (merr_cnt >=5 ) {
1065 multi_err_sign_reg[multi_err_sign_reg_idx+1] = 1'b1;
1066 }
1067 }
1068
1069 dbg.dispmon(myname, MON_INFO, psprintf("intf_err %h, merr_cnt %0d, which_type %h, err_sgn_reg %0b", intf_err, merr_cnt, which_type, multi_err_sign_reg));
1070 }
1071}
1072
1073///////////////////////////////////////////////////////////////////////////
1074// This task is a psuedo coverage object that combines a few conditions
1075// so that the actual coverage objects' state space doesn't get too big
1076//////////////////////////////////////////////////////////////////////////
1077task ncu_intf_cov::set_ncu_ras_cov_point (string myname)
1078{
1079 reg mondo_flag = 0;
1080 reg pio_flag = 0;
1081 reg [10:0] ncu_err = 0;
1082 reg [5:0] ue_err = 0;
1083 reg [5:0] ce_err = 0;
1084 reg [6:0] merr_cnt = 0;
1085 reg [5:0] err_idx=0;
1086 reg err_sig_flag1 = 0;
1087 reg [5:0] ras_clk_cnt=0;
1088 reg [5:0] ras_clk_cnt1=0;
1089 reg [42:0] accum_err_in = 0;
1090 reg [19:0] dmu_err1=0;
1091 reg [19:0] mcu_err1=0;
1092 reg [19:0] niu_err1=0;
1093 reg [19:0] siu_err1=0;
1094
1095 reg [19:0] ce_err1=0;
1096 reg [19:0] ue_err1=0;
1097 reg [5:0] clk_idx=0;
1098 reg [15:0] pkt_tran_cyc=0;
1099 reg [15:0] ras_tran_cyc=0;
1100 reg [3:0] pkt_tran_cyc_idx=0;
1101 reg [3:0] ras_tran_cyc_idx=0;
1102
1103
1104 multi_err_sign_reg = 0;
1105 myname = {myname, ".set_ncu_ras_cov_point"};
1106 while (1) {
1107 @ (posedge ncu_ras_cov.clk);
1108 pkt_tran_cyc[pkt_tran_cyc_idx] = ncu_ras_cov.c2i_packet_vld;
1109 ras_tran_cyc[ras_tran_cyc_idx] = |ncu_ras_cov.raserr_in;
1110 ras_tran_syn = |pkt_tran_cyc && |ras_tran_cyc;
1111 pkt_tran_cyc_idx++;
1112 ras_tran_cyc_idx++;
1113
1114 if (err_sig_flag1 && ras_clk_cnt1 < 20){
1115 ras_clk_cnt1++;
1116 } else {
1117 ras_clk_cnt1 = 0;
1118 err_sig_flag1= 0;
1119 }
1120
1121
1122 if (|ncu_ras_cov.ncu_ras_esr){
1123 for (err_idx = 0; err_idx<43; err_idx++){
1124 if (ncu_ras_cov.ncu_ras_esr[err_idx]){
1125 ncu_ras_esr_err_cnt++;
1126 }
1127 }
1128 ncu_ras_esr_err_cnt_flag = 1;
1129 } else {
1130 ncu_ras_esr_err_cnt_flag = 0;
1131 }
1132 mcu_err = {ncu_ras_cov.mcu3_ncu_ecc,ncu_ras_cov.mcu3_ncu_fbr,
1133 ncu_ras_cov.mcu2_ncu_ecc,ncu_ras_cov.mcu2_ncu_fbr,
1134 ncu_ras_cov.mcu1_ncu_ecc,ncu_ras_cov.mcu1_ncu_fbr,
1135 ncu_ras_cov.mcu0_ncu_ecc,ncu_ras_cov.mcu0_ncu_fbr};
1136
1137 set_err_cnt_cov_point(myname, mcu_err, 0, 0); // count smae error at same cycle
1138 mcu_err1[clk_idx] = |mcu_err;
1139 set_err_cnt_cov_point(myname, mcu_err1, 1, 1); // count error in 20 cycles
1140
1141
1142 niu_err = {ncu_ras_cov.niu_ncu_ctag_ue,ncu_ras_cov.niu_ncu_ctag_ce,
1143 ncu_ras_cov.niu_ncu_d_pe};
1144
1145 set_err_cnt_cov_point(myname, niu_err, 3, 0);
1146 niu_err1[clk_idx] = |niu_err;
1147 set_err_cnt_cov_point(myname, niu_err1, 4, 1);
1148
1149 siu_err = {1'b0,ncu_ras_cov.sio_ncu_ctag_ce,
1150 ncu_ras_cov.sio_ncu_ctag_ue,ncu_ras_cov.sii_ncu_dmud_pe,
1151 ncu_ras_cov.sii_ncu_dmuctag_ce,ncu_ras_cov.sii_ncu_dmuctag_ue,
1152 ncu_ras_cov.sii_ncu_dmua_pe,ncu_ras_cov.sii_ncu_niud_pe,
1153 ncu_ras_cov.sii_ncu_niuctag_ce,ncu_ras_cov.sii_ncu_niuctag_ue,
1154 ncu_ras_cov.sii_ncu_niua_pe};
1155
1156 set_err_cnt_cov_point(myname, siu_err, 6, 0);
1157 siu_err1 = {accum_err_in[26:25], accum_err_in[7:0]};
1158 set_err_cnt_cov_point(myname, siu_err1, 7, 1);
1159
1160
1161 dmu_err = {ncu_ras_cov.dmu_ncu_ctag_ue,ncu_ras_cov.dmu_ncu_ctag_ce,
1162 ncu_ras_cov.dmu_ncu_d_pe,ncu_ras_cov.dmu_ncu_siicr_pe,
1163 ncu_ras_cov.dmu_ncu_ncucr_pe,ncu_ras_cov.dmu_ncu_ie};
1164
1165
1166 dbg.dispmon(myname, MON_INFO, psprintf("dmu_err %h", dmu_err));
1167
1168 set_err_cnt_cov_point(myname, dmu_err, 9, 0);
1169 dmu_err1 = {accum_err_in[26:25], accum_err_in[7:0]};
1170 set_err_cnt_cov_point(myname, dmu_err1, 10, 1);
1171
1172
1173 ncu_err = {ncu_ras_cov.raserr_in[42], ncu_ras_cov.raserr_in[23:14]};
1174 set_err_cnt_cov_point(myname, dmu_err1, 12, 0);
1175 dmu_err1 = {accum_err_in[42], accum_err_in[23:14]};
1176 set_err_cnt_cov_point(myname, dmu_err1, 13, 1);
1177
1178 ue_err = {
1179 ncu_ras_cov.niu_ncu_ctag_ue,
1180 ncu_ras_cov.sio_ncu_ctag_ue,
1181 ncu_ras_cov.raserr_in[22],
1182 ncu_ras_cov.sii_ncu_dmuctag_ue,
1183 ncu_ras_cov.sii_ncu_niuctag_ue,
1184 ncu_ras_cov.dmu_ncu_ctag_ue
1185 };
1186
1187 set_err_cnt_cov_point(myname, ue_err, 15, 0);
1188 ue_err = {accum_err_in[28], accum_err_in[25], accum_err_in[22], accum_err_in[11], accum_err_in[1], accum_err_in[0]};
1189 set_err_cnt_cov_point(myname, ue_err, 16, 1);
1190
1191 ce_err = {
1192 ncu_ras_cov.niu_ncu_ctag_ce,
1193 ncu_ras_cov.sio_ncu_ctag_ce,
1194 ncu_ras_cov.raserr_in[22],
1195 ncu_ras_cov.sii_ncu_dmuctag_ce,
1196 ncu_ras_cov.sii_ncu_niuctag_ce,
1197 ncu_ras_cov.dmu_ncu_ctag_ce
1198 };
1199
1200 set_err_cnt_cov_point(myname, ce_err, 18, 0);
1201 ce_err1 = {accum_err_in[27], accum_err_in[26], accum_err_in[23], accum_err_in[10], accum_err_in[3], accum_err_in[2]};
1202 set_err_cnt_cov_point(myname, ce_err, 19, 1);
1203
1204
1205 mcu_erri = {ncu_ras_cov.ncu_mcu3_ecci,ncu_ras_cov.ncu_mcu3_fbri,
1206 ncu_ras_cov.ncu_mcu2_ecci,ncu_ras_cov.ncu_mcu2_fbri,
1207 ncu_ras_cov.ncu_mcu1_ecci,ncu_ras_cov.ncu_mcu1_fbri,
1208 ncu_ras_cov.ncu_mcu0_ecci,ncu_ras_cov.ncu_mcu0_fbri};
1209
1210 niu_erri = {ncu_ras_cov.ncu_niu_ctag_uei,ncu_ras_cov.ncu_niu_ctag_cei,
1211 ncu_ras_cov.ncu_niu_d_pei};
1212 siu_erri = {ncu_ras_cov.ncu_sio_d_pei,ncu_ras_cov.ncu_sio_ctag_cei,
1213 ncu_ras_cov.ncu_sio_ctag_uei,ncu_ras_cov.ncu_sii_dmud_pei,
1214 ncu_ras_cov.ncu_sii_dmuctag_cei,ncu_ras_cov.ncu_sii_dmuctag_uei,
1215 ncu_ras_cov.ncu_sii_dmua_pei,ncu_ras_cov.ncu_sii_niud_pei,
1216 ncu_ras_cov.ncu_sii_niuctag_cei,ncu_ras_cov.ncu_sii_niuctag_uei,
1217 ncu_ras_cov.ncu_sii_niua_pei};
1218 dmu_erri = {ncu_ras_cov.ncu_dmu_ctag_uei,ncu_ras_cov.ncu_dmu_ctag_cei,
1219 ncu_ras_cov.ncu_dmu_d_pei,ncu_ras_cov.ncu_dmu_siicr_pei,
1220 ncu_ras_cov.ncu_dmu_ncucr_pei,ncu_ras_cov.ncu_dmu_iei};
1221
1222
1223 if (ncu_ras_cov.mondo_hdr_vld){
1224 mondo_flag = 1;
1225 }
1226 if (ncu_ras_cov.pio_hdr_vld){
1227 pio_flag = 1;
1228 }
1229 if (mondo_flag && ncu_ras_cov.pldvld){
1230
1231 ncu_data_pe [0] = ncu_ras_cov.dperr;
1232 mondo_flag = 0;
1233 } else if (pio_flag && ncu_ras_cov.pldvld){
1234 ncu_data_pe [1] = ncu_ras_cov.dperr;
1235 pio_flag = 0;
1236 }
1237
1238 ncu_ctag_ce = {ncu_ras_cov.ncuctag_ce & ncu_ras_cov.pio_hdr_vld,
1239 ncu_ras_cov.ncuctag_ce & ncu_ras_cov.mondo_hdr_vld};
1240
1241 ncu_ctag_ue = {ncu_ras_cov.ncuctag_ue & ncu_ras_cov.pio_hdr_vld,
1242 ncu_ras_cov.ncuctag_ue & ncu_ras_cov.mondo_hdr_vld};
1243
1244 dbg.dispmon(myname, MON_INFO, psprintf("ncu_ctag_ce %h ncu_ctag_ue %h, hdr_vld %h, mondo_vld %h", ncu_ras_cov.ncuctag_ce, ncu_ras_cov.ncuctag_ue, ncu_ras_cov.pio_hdr_vld, ncu_ras_cov.mondo_hdr_vld));
1245
1246 ncu_int_tb_pe = {ncu_ras_cov.c2i_rd_intman & ncu_ras_cov.intman_pe_n,
1247 ncu_ras_cov.io_rd_intman_d2 & ncu_ras_cov.intman_pe_n};
1248 if (ras_clk_cnt1 > 0){
1249 accum_err_in = accum_err_in | ncu_ras_cov.raserr_in;
1250 } else {
1251 accum_err_in = 0;
1252 }
1253
1254 if (|ncu_ras_cov.raserr_in){
1255 err_sig_flag1 = 1;
1256 }
1257 raserr_in_ele_off = ncu_ras_cov.raserr_in & (~ncu_ras_cov.ncu_ras_ele);
1258 raserr_in_eie_off = ncu_ras_cov.raserr_in & (~ncu_ras_cov.ncu_ras_eie);
1259 raserr_in_fee_off = ncu_ras_cov.raserr_in & (~ncu_ras_cov.ncu_ras_fee);
1260 clk_idx++;
1261 if (clk_idx >=20){
1262 clk_idx=0;
1263 }
1264 }
1265
1266} // task set_ncu_ras_cov_point
1267
1268task ncu_intf_cov::set_efu_ncu_points (string myname, reg [6:0] tran_cnt_max, var reg [63:0] data, ncu_cov_efu_port efu)
1269{
1270 reg [6:0] index;
1271 reg efu_flag = 0;
1272 string efu_name;
1273 reg [6:0] tran_cnt;
1274 efu_name=myname;
1275 myname = {myname, ".set_efu_ncu_points"};
1276 tran_cnt = tran_cnt_max-1;
1277 while (1) {
1278 @(posedge efu.\$clk);
1279 if (efu.\$vld){
1280 if (index >tran_cnt_max){
1281 dbg.dispmon(myname, MON_ERR, psprintf("valid assert longer then %0d cycles", index));
1282 }
1283 data[tran_cnt] = efu.\$data;
1284 dbg.dispmon(myname, MON_INFO, psprintf("1. data %0h tran_cnt %0d",data, tran_cnt));
1285 tran_cnt--;
1286 index++;
1287 efu_flag = 1;
1288 } else if (efu_flag){
1289 case (efu_name){
1290 "EFU_SERNUM0" : efu_ncu_intf_hit[0] = 1'b1;
1291 "EFU_SERNUM1" : efu_ncu_intf_hit[1] = 1'b1;
1292 "EFU_SERNUM2" : efu_ncu_intf_hit[2] = 1'b1;
1293 "EFU_COREAVAIL" : efu_ncu_intf_hit[3] = 1'b1;
1294 "EFU_BANKAVAIL" : efu_ncu_intf_hit[4] = 1'b1;
1295 "EFU_FUSESTAT" : efu_ncu_intf_hit[5] = 1'b1;
1296
1297 }
1298 dbg.dispmon(myname, MON_INFO, psprintf("2. data %0h efu_ncu_intf_hit %b", data,efu_ncu_intf_hit));
1299 trigger (efu_ncu_evnt_trig);
1300 efu_flag = 0;
1301 index = 0;
1302 tran_cnt = tran_cnt_max-1;
1303 } else {
1304 data = 0;
1305 }
1306
1307 }
1308}
1309task ncu_intf_cov::set_ncu_io_mix_points (string myname){
1310 myname = {myname, ".set_ncu_io_mix_points"};
1311 while (1) {
1312 @ (posedge ncu_cov_ios.clk);
1313 ncu_spc_core_enable_status = {
1314 ncu_cov_ios.ncu_spc7_core_enable_status,
1315 ncu_cov_ios.ncu_spc6_core_enable_status,
1316 ncu_cov_ios.ncu_spc5_core_enable_status,
1317 ncu_cov_ios.ncu_spc4_core_enable_status,
1318 ncu_cov_ios.ncu_spc3_core_enable_status,
1319 ncu_cov_ios.ncu_spc2_core_enable_status,
1320 ncu_cov_ios.ncu_spc1_core_enable_status,
1321 ncu_cov_ios.ncu_spc0_core_enable_status
1322 } ;
1323 ncu_spc_core_available = { ncu_cov_ios.ncu_spc7_core_available,
1324 ncu_cov_ios.ncu_spc6_core_available,
1325 ncu_cov_ios.ncu_spc5_core_available,
1326 ncu_cov_ios.ncu_spc4_core_available,
1327 ncu_cov_ios.ncu_spc3_core_available,
1328 ncu_cov_ios.ncu_spc2_core_available,
1329 ncu_cov_ios.ncu_spc1_core_available,
1330 ncu_cov_ios.ncu_spc0_core_available
1331 };
1332 ncu_spc_core_running = { ncu_cov_ios.ncu_spc7_core_running,
1333 ncu_cov_ios.ncu_spc6_core_running,
1334 ncu_cov_ios.ncu_spc5_core_running,
1335 ncu_cov_ios.ncu_spc4_core_running,
1336 ncu_cov_ios.ncu_spc3_core_running,
1337 ncu_cov_ios.ncu_spc2_core_running,
1338 ncu_cov_ios.ncu_spc1_core_running,
1339 ncu_cov_ios.ncu_spc0_core_running
1340 };
1341
1342 ncu_spc_core_running = { ncu_cov_ios.ncu_spc7_core_running,
1343 ncu_cov_ios.ncu_spc6_core_running,
1344 ncu_cov_ios.ncu_spc5_core_running,
1345 ncu_cov_ios.ncu_spc4_core_running,
1346 ncu_cov_ios.ncu_spc3_core_running,
1347 ncu_cov_ios.ncu_spc2_core_running,
1348 ncu_cov_ios.ncu_spc1_core_running,
1349 ncu_cov_ios.ncu_spc0_core_running
1350 };
1351
1352 spc_ncu_core_running_status = {
1353 ncu_cov_ios.spc7_ncu_core_running_status,
1354 ncu_cov_ios.spc6_ncu_core_running_status,
1355 ncu_cov_ios.spc5_ncu_core_running_status,
1356 ncu_cov_ios.spc4_ncu_core_running_status,
1357 ncu_cov_ios.spc3_ncu_core_running_status,
1358 ncu_cov_ios.spc2_ncu_core_running_status,
1359 ncu_cov_ios.spc1_ncu_core_running_status,
1360 ncu_cov_ios.spc0_ncu_core_running_status
1361 };
1362
1363 ncu_spc_ba = {
1364 ncu_cov_ios.ncu_spc_pm,
1365 ncu_cov_ios.ncu_spc_ba67,
1366 ncu_cov_ios.ncu_spc_ba45,
1367 ncu_cov_ios.ncu_spc_ba23,
1368 ncu_cov_ios.ncu_spc_ba01
1369 };
1370
1371
1372 ncu_sii_ba = {
1373 ncu_cov_ios.ncu_sii_pm,
1374 ncu_cov_ios.ncu_sii_ba67,
1375 ncu_cov_ios.ncu_sii_ba45,
1376 ncu_cov_ios.ncu_sii_ba23,
1377 ncu_cov_ios.ncu_sii_ba01
1378 };
1379
1380 ncu_l2t_ba = {
1381 ncu_cov_ios.ncu_l2t_pm,
1382 ncu_cov_ios.ncu_l2t_ba67,
1383 ncu_cov_ios.ncu_l2t_ba45,
1384 ncu_cov_ios.ncu_l2t_ba23,
1385 ncu_cov_ios.ncu_l2t_ba01
1386 };
1387
1388 ncu_mcu_ba = {
1389 ncu_cov_ios.ncu_mcu_pm,
1390 ncu_cov_ios.ncu_mcu_ba67,
1391 ncu_cov_ios.ncu_mcu_ba45,
1392 ncu_cov_ios.ncu_mcu_ba23,
1393 ncu_cov_ios.ncu_mcu_ba01
1394 };
1395
1396 if ( (|ncu_spc_core_enable_status) || (|ncu_spc_core_available ) ||
1397 (|ncu_spc_core_running) || (|spc_ncu_core_running_status ) ||
1398 (|ncu_spc_ba) || (|ncu_sii_ba ) ||
1399 (|ncu_mcu_ba) || (|ncu_l2t_ba )
1400
1401 ){
1402 trigger (ncu_spc_bnk_evnt_trig);
1403 }
1404
1405 }
1406}
1407///////////////////////////////////////////////////////////////////////////
1408// This task is a ncu-spc coverage object
1409//////////////////////////////////////////////////////////////////////////
1410// task ncu_intf_cov::set_ncu_spc_intf_cov_point (string myname )
1411#ifdef FC_COVERAGE
1412task ncu_intf_cov::set_ncu_spc_intf_cov_point (string myname)
1413{
1414
1415 myname = {myname, ".set_ncu_spc_intf_cov_point"};
1416 fork
1417 while (1) {
1418 @(posedge ncu_cov_ios.clk);
1419 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b1)
1420 trigger (ncu_spc_enable1_evnt_trig);
1421
1422 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc2_core_enable_status === 1'b1)
1423 trigger (ncu_spc_enable2_evnt_trig);
1424 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc2_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc3_core_enable_status === 1'b1)
1425 trigger (ncu_spc_enable3_evnt_trig);
1426
1427 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc2_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc3_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc4_core_enable_status === 1'b1)
1428 trigger (ncu_spc_enable4_evnt_trig);
1429
1430 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc2_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc3_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc4_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc5_core_enable_status === 1'b1)
1431 trigger (ncu_spc_enable5_evnt_trig);
1432
1433 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc2_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc3_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc4_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc5_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc6_core_enable_status === 1'b1)
1434 trigger (ncu_spc_enable6_evnt_trig);
1435
1436 if (ncu_cov_ios.ncu_spc0_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc1_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc2_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc3_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc4_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc5_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc6_core_enable_status === 1'b0 && ncu_cov_ios.ncu_spc7_core_enable_status === 1'b1)
1437 trigger (ncu_spc_enable7_evnt_trig);
1438 }
1439join none
1440
1441fork
1442. for ($bank=0; $bank<8; $bank++)
1443. {
1444{
1445while(1)
1446{
1447 @(posedge ncu_cov_ios.clk);
1448 if (spc${bank}_ncu_thread1_cnt === 'd5)
1449 {
1450
1451 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0)
1452 spc${bank}_ncu_thread1_cnt = 1;
1453 else
1454 spc${bank}_ncu_thread1_cnt = 0;
1455 }
1456 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0)
1457 {
1458 spc${bank}_ncu_thread1_cnt = spc${bank}_ncu_thread1_cnt + 1;
1459 @(posedge ncu_cov_ios.clk);
1460 if (spc${bank}_ncu_thread1_cnt === 'd5)
1461 trigger (spc${bank}_ncu_thread1_evnt_trig);
1462 }
1463 else
1464 spc${bank}_ncu_thread1_cnt = 0;
1465}
1466}
1467. }
1468join none
1469
1470fork
1471. for ($bank=0; $bank<8; $bank++)
1472. {
1473{
1474while(1)
1475{
1476 @ (posedge ncu_cov_ios.clk);
1477 if (spc${bank}_ncu_thread2_cnt === 'd5)
1478 {
1479
1480 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0)
1481 spc${bank}_ncu_thread2_cnt = 1;
1482 else
1483 spc${bank}_ncu_thread2_cnt = 0;
1484 }
1485 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0)
1486 {
1487 spc${bank}_ncu_thread2_cnt = spc${bank}_ncu_thread2_cnt + 1;
1488 @(posedge ncu_cov_ios.clk);
1489 if (spc${bank}_ncu_thread2_cnt === 'd5)
1490 trigger (spc${bank}_ncu_thread2_evnt_trig);
1491 }
1492 else
1493 spc${bank}_ncu_thread2_cnt = 0;
1494}
1495}
1496. }
1497join none
1498
1499fork
1500. for ($bank=0; $bank<8; $bank++)
1501. {
1502{
1503while(1)
1504{
1505 @ (posedge ncu_cov_ios.clk);
1506 if (spc${bank}_ncu_thread3_cnt === 'd5)
1507 {
1508
1509 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0)
1510 spc${bank}_ncu_thread3_cnt = 1;
1511 else
1512 spc${bank}_ncu_thread3_cnt = 0;
1513 }
1514 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0)
1515 {
1516 spc${bank}_ncu_thread3_cnt = spc${bank}_ncu_thread3_cnt + 1;
1517 @(posedge ncu_cov_ios.clk);
1518 if (spc${bank}_ncu_thread3_cnt === 'd5)
1519 trigger (spc${bank}_ncu_thread3_evnt_trig);
1520 }
1521 else
1522 spc${bank}_ncu_thread3_cnt = 0;
1523}
1524}
1525. }
1526join none
1527
1528fork
1529. for ($bank=0; $bank<8; $bank++)
1530. {
1531{
1532while(1)
1533{
1534 @ (posedge ncu_cov_ios.clk);
1535 if (spc${bank}_ncu_thread4_cnt === 'd5)
1536 {
1537
1538 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0)
1539 spc${bank}_ncu_thread4_cnt = 1;
1540 else
1541 spc${bank}_ncu_thread4_cnt = 0;
1542 }
1543 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0)
1544 {
1545 spc${bank}_ncu_thread4_cnt = spc${bank}_ncu_thread4_cnt + 1;
1546 @(posedge ncu_cov_ios.clk);
1547 if (spc${bank}_ncu_thread4_cnt === 'd5)
1548 trigger (spc${bank}_ncu_thread4_evnt_trig);
1549 }
1550 else
1551 spc${bank}_ncu_thread4_cnt = 0;
1552}
1553}
1554. }
1555join none
1556
1557fork
1558. for ($bank=0; $bank<8; $bank++)
1559. {
1560{
1561while(1)
1562{
1563 @ (posedge ncu_cov_ios.clk);
1564 if (spc${bank}_ncu_thread5_cnt === 'd5)
1565 {
1566
1567 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0)
1568 spc${bank}_ncu_thread5_cnt = 1;
1569 else
1570 spc${bank}_ncu_thread5_cnt = 0;
1571 }
1572 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0)
1573 {
1574 spc${bank}_ncu_thread5_cnt = spc${bank}_ncu_thread5_cnt + 1;
1575 @(posedge ncu_cov_ios.clk);
1576 if (spc${bank}_ncu_thread5_cnt === 'd5)
1577 trigger (spc${bank}_ncu_thread5_evnt_trig);
1578 }
1579 else
1580 spc${bank}_ncu_thread5_cnt = 0;
1581}
1582}
1583. }
1584join none
1585
1586fork
1587. for ($bank=0; $bank<8; $bank++)
1588. {
1589{
1590while(1)
1591{
1592 @ (posedge ncu_cov_ios.clk);
1593 if (spc${bank}_ncu_thread6_cnt === 'd5)
1594 {
1595
1596 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0)
1597 spc${bank}_ncu_thread6_cnt = 1;
1598 else
1599 spc${bank}_ncu_thread6_cnt = 0;
1600 }
1601 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0)
1602 {
1603 spc${bank}_ncu_thread6_cnt = spc${bank}_ncu_thread6_cnt + 1;
1604 @(posedge ncu_cov_ios.clk);
1605 if (spc${bank}_ncu_thread6_cnt === 'd5)
1606 trigger (spc${bank}_ncu_thread6_evnt_trig);
1607 }
1608 else
1609 spc${bank}_ncu_thread6_cnt = 0;
1610}
1611}
1612. }
1613join none
1614
1615fork
1616. for ($bank=0; $bank<8; $bank++)
1617. {
1618{
1619while(1)
1620{
1621 @ (posedge ncu_cov_ios.clk);
1622 if (spc${bank}_ncu_thread7_cnt === 'd5)
1623 {
1624
1625 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0)
1626 spc${bank}_ncu_thread7_cnt = 1;
1627 else
1628 spc${bank}_ncu_thread7_cnt = 0;
1629 }
1630 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0)
1631 {
1632 spc${bank}_ncu_thread7_cnt = spc${bank}_ncu_thread7_cnt + 1;
1633 @(posedge ncu_cov_ios.clk);
1634 if (spc${bank}_ncu_thread7_cnt === 'd5)
1635 trigger (spc${bank}_ncu_thread7_evnt_trig);
1636 }
1637 else
1638 spc${bank}_ncu_thread7_cnt = 0;
1639}
1640}
1641. }
1642join none
1643
1644fork
1645. for ($bank=0; $bank<8; $bank++)
1646. {
1647{
1648while(1)
1649{
1650 @ (posedge ncu_cov_ios.clk);
1651 if (spc${bank}_ncu_thread8_cnt === 'd5)
1652 {
1653
1654 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1655 spc${bank}_ncu_thread8_cnt = 1;
1656 else
1657 spc${bank}_ncu_thread8_cnt = 0;
1658 }
1659 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1660 {
1661 spc${bank}_ncu_thread8_cnt = spc${bank}_ncu_thread8_cnt + 1;
1662 @(posedge ncu_cov_ios.clk);
1663 if (spc${bank}_ncu_thread8_cnt === 'd5)
1664 trigger (spc${bank}_ncu_thread8_evnt_trig);
1665 }
1666 else
1667 spc${bank}_ncu_thread8_cnt = 0;
1668}
1669}
1670. }
1671join none
1672
1673fork
1674. for ($bank=0; $bank<8; $bank++)
1675. {
1676{
1677while(1)
1678{
1679 @ (posedge ncu_cov_ios.clk);
1680 if (spc${bank}_ncu_thread1_10_cnt === 'd10)
1681 {
1682
1683 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0)
1684 spc${bank}_ncu_thread1_10_cnt = 1;
1685 else
1686 spc${bank}_ncu_thread1_10_cnt = 0;
1687 }
1688 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0)
1689 {
1690 spc${bank}_ncu_thread1_10_cnt = spc${bank}_ncu_thread1_10_cnt + 1;
1691 @(posedge ncu_cov_ios.clk);
1692 if (spc${bank}_ncu_thread1_10_cnt === 'd10)
1693 trigger (spc${bank}_ncu_thread1_10_evnt_trig);
1694 }
1695 else
1696 spc${bank}_ncu_thread1_10_cnt = 0;
1697}
1698}
1699. }
1700join none
1701
1702fork
1703. for ($bank=0; $bank<8; $bank++)
1704. {
1705{
1706while(1)
1707{
1708 @ (posedge ncu_cov_ios.clk);
1709 if (spc${bank}_ncu_thread2_10_cnt === 'd10)
1710 {
1711
1712 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0)
1713 spc${bank}_ncu_thread2_10_cnt = 1;
1714 else
1715 spc${bank}_ncu_thread2_10_cnt = 0;
1716 }
1717 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0)
1718 {
1719 spc${bank}_ncu_thread2_10_cnt = spc${bank}_ncu_thread2_10_cnt + 1;
1720 @(posedge ncu_cov_ios.clk);
1721 if (spc${bank}_ncu_thread2_10_cnt === 'd10)
1722 trigger (spc${bank}_ncu_thread2_10_evnt_trig);
1723 }
1724 else
1725 spc${bank}_ncu_thread2_10_cnt = 0;
1726}
1727}
1728. }
1729join none
1730
1731fork
1732. for ($bank=0; $bank<8; $bank++)
1733. {
1734{
1735while(1)
1736{
1737 @ (posedge ncu_cov_ios.clk);
1738 if (spc${bank}_ncu_thread3_10_cnt === 'd10)
1739 {
1740
1741 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0)
1742 spc${bank}_ncu_thread3_10_cnt = 1;
1743 else
1744 spc${bank}_ncu_thread3_10_cnt = 0;
1745 }
1746 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0)
1747 {
1748 spc${bank}_ncu_thread3_10_cnt = spc${bank}_ncu_thread3_10_cnt + 1;
1749 @(posedge ncu_cov_ios.clk);
1750 if (spc${bank}_ncu_thread3_10_cnt === 'd10)
1751 trigger (spc${bank}_ncu_thread3_10_evnt_trig);
1752 }
1753 else
1754 spc${bank}_ncu_thread3_10_cnt = 0;
1755}
1756}
1757. }
1758join none
1759
1760fork
1761. for ($bank=0; $bank<8; $bank++)
1762. {
1763{
1764while(1)
1765{
1766 @ (posedge ncu_cov_ios.clk);
1767 if (spc${bank}_ncu_thread4_10_cnt === 'd10)
1768 {
1769
1770 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0)
1771 spc${bank}_ncu_thread4_10_cnt = 1;
1772 else
1773 spc${bank}_ncu_thread4_10_cnt = 0;
1774 }
1775 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0)
1776 {
1777 spc${bank}_ncu_thread4_10_cnt = spc${bank}_ncu_thread4_10_cnt + 1;
1778 @(posedge ncu_cov_ios.clk);
1779 if (spc${bank}_ncu_thread4_10_cnt === 'd10)
1780 trigger (spc${bank}_ncu_thread4_10_evnt_trig);
1781 }
1782 else
1783 spc${bank}_ncu_thread4_10_cnt = 0;
1784}
1785}
1786. }
1787join none
1788
1789fork
1790. for ($bank=0; $bank<8; $bank++)
1791. {
1792{
1793while(1)
1794{
1795 @ (posedge ncu_cov_ios.clk);
1796 if (spc${bank}_ncu_thread5_10_cnt === 'd10)
1797 {
1798
1799 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0)
1800 spc${bank}_ncu_thread5_10_cnt = 1;
1801 else
1802 spc${bank}_ncu_thread5_10_cnt = 0;
1803 }
1804 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0)
1805 {
1806 spc${bank}_ncu_thread5_10_cnt = spc${bank}_ncu_thread5_10_cnt + 1;
1807 @(posedge ncu_cov_ios.clk);
1808 if (spc${bank}_ncu_thread5_10_cnt === 'd10)
1809 trigger (spc${bank}_ncu_thread5_10_evnt_trig);
1810 }
1811 else
1812 spc${bank}_ncu_thread5_10_cnt = 0;
1813}
1814}
1815. }
1816join none
1817
1818fork
1819. for ($bank=0; $bank<8; $bank++)
1820. {
1821{
1822while(1)
1823{
1824 @ (posedge ncu_cov_ios.clk);
1825 if (spc${bank}_ncu_thread6_10_cnt === 'd10)
1826 {
1827
1828 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0)
1829 spc${bank}_ncu_thread6_10_cnt = 1;
1830 else
1831 spc${bank}_ncu_thread6_10_cnt = 0;
1832 }
1833 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0)
1834 {
1835 spc${bank}_ncu_thread6_10_cnt = spc${bank}_ncu_thread6_10_cnt + 1;
1836 @(posedge ncu_cov_ios.clk);
1837 if (spc${bank}_ncu_thread6_10_cnt === 'd10)
1838 trigger (spc${bank}_ncu_thread6_10_evnt_trig);
1839 }
1840 else
1841 spc${bank}_ncu_thread6_10_cnt = 0;
1842}
1843}
1844. }
1845join none
1846
1847fork
1848. for ($bank=0; $bank<8; $bank++)
1849. {
1850{
1851while(1)
1852{
1853 @ (posedge ncu_cov_ios.clk);
1854 if (spc${bank}_ncu_thread7_10_cnt === 'd10)
1855 {
1856
1857 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0)
1858 spc${bank}_ncu_thread7_10_cnt = 1;
1859 else
1860 spc${bank}_ncu_thread7_10_cnt = 0;
1861 }
1862 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0)
1863 {
1864 spc${bank}_ncu_thread7_10_cnt = spc${bank}_ncu_thread7_10_cnt + 1;
1865 @(posedge ncu_cov_ios.clk);
1866 if (spc${bank}_ncu_thread7_10_cnt === 'd10)
1867 trigger (spc${bank}_ncu_thread7_10_evnt_trig);
1868 }
1869 else
1870 spc${bank}_ncu_thread7_10_cnt = 0;
1871}
1872}
1873. }
1874join none
1875
1876fork
1877. for ($bank=0; $bank<8; $bank++)
1878. {
1879{
1880while(1)
1881{
1882 @ (posedge ncu_cov_ios.clk);
1883 if (spc${bank}_ncu_thread8_10_cnt === 'd10)
1884 {
1885
1886 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1887 spc${bank}_ncu_thread8_10_cnt = 1;
1888 else
1889 spc${bank}_ncu_thread8_10_cnt = 0;
1890 }
1891 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1892 {
1893 spc${bank}_ncu_thread8_10_cnt = spc${bank}_ncu_thread8_10_cnt + 1;
1894 @(posedge ncu_cov_ios.clk);
1895 if (spc${bank}_ncu_thread8_10_cnt === 'd10)
1896 trigger (spc${bank}_ncu_thread8_10_evnt_trig);
1897 }
1898 else
1899 spc${bank}_ncu_thread8_10_cnt = 0;
1900}
1901}
1902. }
1903join none
1904
1905fork
1906. for ($bank=0; $bank<8; $bank++)
1907. {
1908{
1909while(1)
1910{
1911 @ (posedge ncu_cov_ios.clk);
1912 if (spc_ncu_thread_50_cnt === 'd50)
1913 {
1914
1915 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1916 spc_ncu_thread_50_cnt = 1;
1917 else
1918 spc_ncu_thread_50_cnt = 0;
1919 }
1920 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1921 {
1922 spc_ncu_thread_50_cnt = spc_ncu_thread_50_cnt + 1;
1923 @(posedge ncu_cov_ios.clk);
1924 if (spc_ncu_thread_50_cnt === 'd50)
1925 trigger (spc_ncu_thread_50_evnt_trig);
1926 }
1927 else
1928 spc_ncu_thread_50_cnt = 0;
1929}
1930}
1931. }
1932join none
1933
1934fork
1935. for ($bank=0; $bank<8; $bank++)
1936. {
1937{
1938while(1)
1939{
1940 @ (posedge ncu_cov_ios.clk);
1941 if (spc_ncu_thread_100_cnt === 'd100)
1942 {
1943
1944 if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0 | | ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1945 spc_ncu_thread_100_cnt = 1;
1946 else
1947 spc_ncu_thread_100_cnt = 0;
1948 }
1949 else if (ncu_cov_ios.spc${bank}_ncu_core_running_status[0] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[1] === 1'b0 | | ncu_cov_ios.spc${bank}_ncu_core_running_status[2] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[3] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[4] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[5] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[6] === 1'b0 | ncu_cov_ios.spc${bank}_ncu_core_running_status[7] === 1'b0)
1950 {
1951 spc_ncu_thread_100_cnt = spc_ncu_thread_100_cnt + 1;
1952 @(posedge ncu_cov_ios.clk);
1953 if (spc_ncu_thread_100_cnt === 'd100)
1954 trigger (spc_ncu_thread_100_evnt_trig);
1955 }
1956 else
1957 spc_ncu_thread_100_cnt = 0;
1958}
1959}
1960. }
1961join none
1962
1963
1964} // task set_ncu_spc_intf_cov_point
1965#endif
1966
1967
1968
1969task ncu_intf_cov::set_ncu_pcx_cov_point (string myname, ncu_cov_com_io_port ncu_pcxpt)
1970{
1971 reg ncu_pcx_pkt_gap_cnt_flag = 0;
1972 reg [31:0] pcx_32_int_in_32clk=0;
1973 reg [63:0] pcx_32_int_in_64clk=0;
1974 reg [4:0] pcx_32_int_in_32clk_idx=0;
1975 reg [5:0] pcx_32_int_in_64clk_idx=0;
1976
1977 myname = {myname, ".set_ncu_pcx_cov_point"};
1978 pcx_int_clk_cnt = 0;
1979 ncu_pcx_pkt_gap_cnt = 0;
1980 while (1) {
1981 @ (posedge ncu_pcxpt.\$clk);
1982 if ( ncu_pcxpt.\$valid) {
1983 trigger (ncu_pcx_sample_evnt_trig);
1984 fork
1985 {
1986 @(posedge ncu_cov_ccx.clk);
1987 ncu_pcx_pkt_gap_cnt = 0;
1988 ncu_pcx_pkt_gap_cnt_flag = 1;
1989 }
1990 join none
1991 } else {
1992 if (ncu_pcx_pkt_gap_cnt_flag){
1993 ncu_pcx_pkt_gap_cnt++;
1994 }
1995 }
1996 //=============================
1997 if (ncu_pcxpt.\$stall) {
1998 ncu_pcx_stall_cnt++;
1999 trigger (ncu_pcx_sample_evnt_trig);
2000 } else {
2001 ncu_pcx_stall_cnt = 0;
2002 }
2003 //=============================
2004 if (spc_int_flag ){
2005 spc_niu_int_skew++;
2006 spc_ssi_int_skew++;
2007 spc_siu_int_skew++;
2008 spc_int_flag = 0;
2009 } else if (spc_niu_int_skew <= 10){
2010 spc_niu_int_skew++;
2011 spc_ssi_int_skew++;
2012 spc_siu_int_skew++;
2013 } else {
2014 spc_niu_int_skew = 4'hf;
2015 spc_ssi_int_skew = 4'hf;
2016 spc_siu_int_skew = 4'hf;
2017 }
2018 //=============================
2019
2020
2021
2022 pcx_32_int_in_32clk[pcx_32_int_in_32clk_idx] = ncu_pcxpt.\$valid &&
2023 ((ncu_pcxpt.\$data[103:64] & 40'hff03ffffff) == 40'h9001cc0000) &&
2024 (ncu_pcxpt.\$data[128:124] == 5'b00001);
2025
2026 pcx_32_int_in_64clk[pcx_32_int_in_64clk_idx] = ncu_pcxpt.\$valid &&
2027 ((ncu_pcxpt.\$data[103:64] & 40'hff03ffffff) == 40'h9001cc0000) &&
2028 (ncu_pcxpt.\$data[128:124] == 5'b00001);
2029
2030 pcx_32_int_in_32clk_idx++;
2031 pcx_32_int_in_64clk_idx++;
2032
2033 pcx_int_des_reg[0] = &pcx_32_int_in_32clk;
2034 pcx_int_des_reg[1] = count_pkt_num(myname, pcx_32_int_in_64clk, 32);
2035 if (|pcx_int_des_reg){
2036 trigger (ncu_pcx_sample_evnt_trig);
2037 }
2038 if (ncu_pcxpt.\$valid && ((ncu_pcxpt.\$data[103:64] & 40'hff03ffffff)==40'h9001cc0000)){
2039 dbg.dispmon(myname, MON_INFO, psprintf("pcx_int_des_reg %h pcx_32_int_in_32clk %h pcx_32_int_in_64clk %h, pcx_32_int_in_32clk_idx, %0d, pcx_32_int_in_64clk %0", pcx_int_des_reg, pcx_32_int_in_32clk, pcx_32_int_in_64clk, pcx_32_int_in_32clk_idx, pcx_32_int_in_64clk_idx));
2040 spc_int_flag = 1;
2041 }
2042
2043
2044 if (!ncu_pcxpt.\$stall && ncu_pcxpt.\$valid) {
2045 ncu_io_sample_flag = 1;
2046 ncu_pcx_add = ncu_pcxpt.\$data[103:64];
2047 ncu_pcx_type = ncu_pcxpt.\$data[128:124];
2048 ncu_pcx_cpu = ncu_pcxpt.\$data[122:117];
2049 ncu_pcx_size = ncu_pcxpt.\$data[111:104];
2050 ncu_pcx_b2b++;
2051 if (ncu_pcx_type == 5'b00001){
2052 ncu_pcx_store_b2b++;
2053 }
2054 if (ncu_pcx_type == 5'b00000){
2055 ncu_pcx_load_b2b++;
2056 }
2057 if (ncu_pcx_add[39:32] == 8'h81){
2058 ncu_pcx_niu_b2b++;
2059 }
2060 if (ncu_pcx_add[39:32] == 8'h83){
2061 ncu_pcx_ccu_b2b++;
2062 }
2063 if (ncu_pcx_add[39:32] == 8'h84){
2064 if (ncu_pcx_add[31:30] == 0){
2065 ncu_pcx_mcu0_b2b++;
2066 }
2067 if (ncu_pcx_add[31:30] == 1){
2068 ncu_pcx_mcu1_b2b++;
2069 }
2070 if (ncu_pcx_add[31:30] == 2){
2071 ncu_pcx_mcu2_b2b++;
2072 }
2073 if (ncu_pcx_add[31:30] == 3){
2074 ncu_pcx_mcu3_b2b++;
2075 }
2076 }
2077 if (ncu_pcx_add[39:32] == 8'h85){
2078 ncu_pcx_tcu_b2b++;
2079 }
2080 if (ncu_pcx_add[39:32] == 8'h86){
2081 ncu_pcx_dbg1_b2b++;
2082 }
2083 if (ncu_pcx_add[39:32] == 8'h88){
2084 ncu_pcx_dmu_b2b++;
2085 }
2086 if (ncu_pcx_add[39:32] == 8'hff){
2087 ncu_pcx_ssi_b2b++;
2088 }
2089 if (ncu_pcx_add[39:32] == 8'h89){
2090 ncu_pcx_rst_b2b++;
2091 }
2092 if (ncu_pcx_add[39:36] == 4'hc){
2093 ncu_pcx_pio_b2b++;
2094 }
2095
2096 if (ncu_pcx_add == 40'h8000040400) {
2097 ncu_pcx_adata0_thr_reg[ncu_pcx_cpu] = 1'b1;
2098
2099 }
2100 if (ncu_pcx_add == 40'h8000040600) {
2101 ncu_pcx_adata1_thr_reg[ncu_pcx_cpu] = 1'b1;
2102
2103 }
2104 if (ncu_pcx_add == 40'h8000040a00) {
2105 ncu_pcx_abusy_thr_reg[ncu_pcx_cpu] = 1'b1;
2106
2107 }
2108 trigger (ncu_pcx_sample_evnt_trig);
2109 dbg.dispmon(myname, MON_INFO, psprintf("ncu_pcx_add %h ncu_pcx_type %h id %h size %h b2b cnt %0d", ncu_pcx_add, ncu_pcx_type, ncu_pcx_cpu, ncu_pcx_size, ncu_pcx_b2b));
2110 } else {
2111 ncu_pcx_adata0_thr_reg = 0;
2112 ncu_pcx_adata1_thr_reg = 0;
2113 ncu_pcx_add = 40'hxxxxxxxxxx;
2114 ncu_pcx_type = 5'hxx;
2115 ncu_pcx_cpu = 6'hxx;
2116 ncu_pcx_size = 8'hxx;
2117 ncu_pcx_b2b = 0;
2118 ncu_pcx_pio_b2b=0;
2119 ncu_pcx_ssi_b2b=0;
2120 ncu_pcx_rst_b2b=0;
2121 ncu_pcx_dmu_b2b=0;
2122 ncu_pcx_dbg1_b2b=0;
2123 ncu_pcx_tcu_b2b=0;
2124 ncu_pcx_mcu3_b2b=0;
2125 ncu_pcx_mcu2_b2b=0;
2126 ncu_pcx_mcu1_b2b=0;
2127 ncu_pcx_mcu0_b2b=0;
2128 ncu_pcx_ccu_b2b=0;
2129 ncu_pcx_niu_b2b=0;
2130 ncu_pcx_load_b2b=0;
2131 ncu_pcx_store_b2b=0;
2132 }
2133 }
2134} // task set_ncu_pcx_cov_point
2135
2136
2137
2138task ncu_intf_cov::set_ucb_ncu_cov_point(string myname,
2139 reg [5:0] ucb_data_width,
2140 var reg [3:0] ucb_ncu_type,
2141 var reg [5:0] ucb_ncu_cpuid,
2142 var reg [1:0] ucb_ncu_bufid,
2143 var reg [8:0] ucb_ncu_deviceid,
2144 var reg [5:0] ucb_ncu_int_vec,
2145 var reg [2:0] ucb_ncu_size,
2146 var reg [31:0] b2b_cnt,
2147 var reg [31:0] stall_b2b_cnt,
2148 var reg [31:0] vld_to_stall_cnt,
2149 var reg [31:0] ucb_pkt_gap,
2150 ncu_cov_com_io_port up_ucbpt,
2151 var event ucb_ncu_sample_evnt_trig
2152){
2153
2154 reg [127:0] rev_pkt;
2155 reg [5:0] rev_cyc_cnt;
2156 reg get_pkt_flag;
2157 reg case1_flag;
2158 reg [31:0] niu_ncu_int_des_clk_cnt = 0;
2159 reg [31:0] niu_ncu_int_des_cnt = 0;
2160 reg niu_ncu_int_des_flag = 0;
2161 reg ucb_pkt_gap_flag = 0;
2162 reg [4:0] niu_int_in_5cyc=0;
2163 reg [19:0] niu_int_in_20cyc=0;
2164 reg [49:0] niu_int_in_50cyc=0;
2165 reg [149:0] niu_int_in_150cyc=0;
2166 reg [799:0] niu_int_in_800cyc=0;
2167 reg [31:0] niu_int_in_800cyc_idx=0;
2168 reg [31:0] niu_int_in_5cyc_idx=0;
2169 reg [31:0] niu_int_in_20cyc_idx=0;
2170 reg [31:0] niu_int_in_50cyc_idx=0;
2171 reg [31:0] niu_int_in_150cyc_idx=0;
2172 reg niu_vld_flag = 0;
2173
2174
2175
2176 ucb_pkt_gap= 0;
2177 get_pkt_flag = 0;
2178 rev_cyc_cnt = 0;
2179 case1_flag = 0;
2180 myname = {myname, ".set_ucb_ncu_cov_pont"};
2181 b2b_cnt=0;
2182 vld_to_stall_cnt=0;
2183 while (1) {
2184 @(posedge up_ucbpt.\$clk);
2185
2186 //--------------------------
2187 fork
2188 if (up_ucbpt.\$valid && !up_ucbpt.\$stall){
2189 vld_to_stall_cnt++;
2190 } else if (~up_ucbpt.\$valid || up_ucbpt.\$stall){
2191 if (up_ucbpt.\$stall){
2192 @(posedge up_ucbpt.\$clk);
2193 }
2194 vld_to_stall_cnt = 0;
2195 }
2196 join none
2197 if (up_ucbpt.\$valid) {
2198 if (ucb_pkt_gap >0){
2199 dbg.dispmon(myname, MON_INFO, psprintf("ucb_pkt_gap %0d", ucb_pkt_gap));
2200 trigger (ucb_ncu_sample_evnt_trig);
2201 }
2202 fork
2203 {
2204 @(negedge up_ucbpt.\$clk);
2205 ucb_pkt_gap = 0;
2206 ucb_pkt_gap_flag = 1;
2207 }
2208 join none
2209 } else {
2210 if (ucb_pkt_gap_flag){
2211 ucb_pkt_gap++;
2212 }
2213 }
2214
2215 //--------------------------
2216 if (up_ucbpt.\$stall){
2217 stall_b2b_cnt++;
2218 trigger (ucb_ncu_sample_evnt_trig);
2219 } else {
2220 stall_b2b_cnt = 0;
2221 }
2222 //=============================
2223
2224 if (myname.match("ssi_ncu") ){
2225 if (ssi_int_flag ){
2226 ssi_spc_int_skew++;
2227 ssi_siu_int_skew++;
2228 ssi_niu_int_skew++;
2229 ssi_int_flag = 0;
2230 } else if (ssi_spc_int_skew <= 10){
2231 ssi_spc_int_skew++;
2232 ssi_siu_int_skew++;
2233 ssi_niu_int_skew++;
2234 } else {
2235 ssi_spc_int_skew = 4'hf;
2236 ssi_niu_int_skew = 4'hf;
2237 ssi_siu_int_skew = 4'hf;
2238 }
2239 }
2240 if (myname.match("niu_ncu") ){
2241 //=============================
2242 if (niu_int_flag ){
2243 niu_spc_int_skew++;
2244 niu_siu_int_skew++;
2245 niu_ssi_int_skew++;
2246 niu_int_flag = 0;
2247 } else if (niu_spc_int_skew <= 10){
2248 niu_spc_int_skew++;
2249 niu_siu_int_skew++;
2250 niu_ssi_int_skew++;
2251 } else {
2252 niu_spc_int_skew = 4'hf;
2253 niu_ssi_int_skew = 4'hf;
2254 niu_siu_int_skew = 4'hf;
2255 }
2256 niu_int_in_5cyc[niu_int_in_5cyc_idx] = (up_ucbpt.\$valid && (up_ucbpt.\$data[3:0] ==4'b1000) && (!niu_vld_flag));
2257 if (|niu_int_in_5cyc){
2258 niu_ncu_int_des_reg[0] = count_pkt_num (myname, niu_int_in_5cyc, 2);
2259 }
2260
2261 niu_int_in_20cyc[niu_int_in_20cyc_idx] = (up_ucbpt.\$valid && (up_ucbpt.\$data[3:0] ==4'b1000) && (!niu_vld_flag));
2262 if (|niu_int_in_20cyc){
2263 niu_ncu_int_des_reg[1] = count_pkt_num (myname, niu_int_in_20cyc, 4);
2264 }
2265
2266 niu_int_in_50cyc[niu_int_in_50cyc_idx] = (up_ucbpt.\$valid && (up_ucbpt.\$data[3:0] ==4'b1000) && (!niu_vld_flag));
2267 if (|niu_int_in_50cyc){
2268 niu_ncu_int_des_reg[2] = count_pkt_num (myname, niu_int_in_50cyc, 8);
2269 }
2270
2271 niu_int_in_150cyc[niu_int_in_150cyc_idx] = (up_ucbpt.\$valid && (up_ucbpt.\$data[3:0] ==4'b1000) && (!niu_vld_flag));
2272 if (|niu_int_in_150cyc){
2273 niu_ncu_int_des_reg[3] = count_pkt_num (myname, niu_int_in_150cyc, 16);
2274 }
2275
2276 niu_int_in_800cyc[niu_int_in_800cyc_idx] = (up_ucbpt.\$valid && (up_ucbpt.\$data[3:0] ==4'b1000) && (!niu_vld_flag));
2277 if (|niu_int_in_800cyc){
2278 niu_ncu_int_des_reg[4] = count_pkt_num (myname, niu_int_in_800cyc, 32);
2279 }
2280
2281 if (|niu_int_in_5cyc || |niu_int_in_20cyc || |niu_int_in_150cyc || |niu_int_in_800cyc){
2282 dbg.dispmon(myname, MON_INFO, psprintf("NIU_INT:: vld %0h data %0h vld_flag %0h, des%0h, in_5c%0h, in_20c %0h, in_50c %0h in_150c %0h,in_800c %0hidx %0d",
2283 up_ucbpt.\$valid, up_ucbpt.\$data[3:0], niu_vld_flag, niu_ncu_int_des_reg, niu_int_in_5cyc,niu_int_in_20cyc,niu_int_in_50cyc,niu_int_in_150cyc,niu_int_in_800cyc, niu_int_in_5cyc_idx));
2284 }
2285 niu_int_in_5cyc_idx++;
2286 if (niu_int_in_5cyc_idx>4) niu_int_in_5cyc_idx =0;
2287 niu_int_in_20cyc_idx++;
2288 if (niu_int_in_20cyc_idx>19) niu_int_in_20cyc_idx = 0;
2289 niu_int_in_50cyc_idx++;
2290 if (niu_int_in_50cyc_idx>49) niu_int_in_50cyc_idx = 0;
2291 niu_int_in_150cyc_idx++;
2292 if (niu_int_in_150cyc_idx>149) niu_int_in_150cyc_idx = 0;
2293 niu_int_in_800cyc_idx++;
2294 if (niu_int_in_800cyc_idx>799) niu_int_in_800cyc_idx = 0;
2295 if (up_ucbpt.\$valid){
2296 niu_vld_flag=1;
2297 } else {
2298 niu_vld_flag=0;
2299 }
2300 }
2301 //=============================
2302 if (up_ucbpt.\$valid && !up_ucbpt.\$stall && !case1_flag){
2303 reg [8:0] up_bits;
2304 reg [8:0] low_bits;
2305 up_bits = (ucb_data_width*(rev_cyc_cnt+1)) -1;
2306 low_bits = ucb_data_width*rev_cyc_cnt;
2307 rev_pkt[up_bits:low_bits] = up_ucbpt.\$data;
2308 //rev_pkt[(ucb_data_width*(rev_cyc_cnt+1))-1:ucb_data_width*rev_cyc_cnt] = up_ucbpt.\$data;
2309 dbg.dispmon(myname, MON_INFO, psprintf("rev_pkt %0h, rev_pkt[%0d:%0d] %0h ucb_data_width %0d rev_cyc_cnt %0d get_pkt_flag %h",
2310 rev_pkt, up_bits, low_bits, rev_pkt[up_bits:low_bits], ucb_data_width,rev_cyc_cnt,get_pkt_flag));
2311 get_pkt_flag = 1;
2312 rev_cyc_cnt++;
2313 }
2314 else if (up_ucbpt.\$valid && up_ucbpt.\$stall && !case1_flag ) {
2315 reg [8:0] up_bits;
2316 reg [8:0] low_bits;
2317 up_bits = (ucb_data_width*(rev_cyc_cnt+1)) -1;
2318 low_bits = ucb_data_width*rev_cyc_cnt;
2319 rev_pkt[up_bits:low_bits] = up_ucbpt.\$data;
2320 dbg.dispmon(myname, MON_INFO, psprintf("rev_pkt %0h, rev_pkt[%0d:%0d] %0h ucb_data_width %0d rev_cyc_cnt %0d get_pkt_flag %h",
2321 rev_pkt, up_bits, low_bits, rev_pkt[up_bits:low_bits], ucb_data_width,rev_cyc_cnt,get_pkt_flag));
2322 //rev_pkt[(ucb_data_width*(rev_cyc_cnt+1))-1:ucb_data_width*rev_cyc_cnt] = up_ucbpt.\$data;
2323 get_pkt_flag = 1;
2324 rev_cyc_cnt++;
2325 case1_flag = 1;
2326 } else if (up_ucbpt.\$valid && !up_ucbpt.\$stall && case1_flag){
2327 case1_flag = 0;
2328 } else if (!up_ucbpt.\$valid ){
2329 if (get_pkt_flag) { // get one pakcet for check
2330 ucb_ncu_type = rev_pkt[3:0];
2331 ucb_ncu_cpuid = rev_pkt[9:4];
2332 ucb_ncu_bufid = rev_pkt[11:10];
2333 ucb_ncu_deviceid = rev_pkt[18:10];
2334 ucb_ncu_int_vec = rev_pkt[56:51];
2335 ucb_ncu_size = rev_pkt[14:12];
2336 if (myname.match("tcu_ncu") ){
2337 tcu_ncu_add = rev_pkt[54:47];
2338 }
2339 b2b_cnt++;
2340 //==============================
2341 if (ucb_ncu_type ===4'b1000){ //UCB_PKT_INT 4'b1000
2342 if (myname.match("niu_ncu") ){
2343 niu_int_flag = 1;
2344 dbg.dispmon(myname, MON_INFO, psprintf("niu_ncu_int_des_cnt %0d niu_ncu_int_des_clk_cnt %0d ",
2345 niu_ncu_int_des_cnt, niu_ncu_int_des_clk_cnt ));
2346 }
2347 if (myname.match("ssi_ncu") ){
2348 ssi_int_flag = 1;
2349 }
2350 }
2351 dbg.dispmon(myname, MON_INFO, psprintf("type %h cpu id %h buffer id %h, b2b_cnt %0d",
2352 ucb_ncu_type, ucb_ncu_cpuid, ucb_ncu_bufid, b2b_cnt));
2353 trigger (ucb_ncu_sample_evnt_trig);
2354 } else {
2355 b2b_cnt=0;
2356 }
2357 rev_pkt = {32{4'hx}};
2358 get_pkt_flag = 0;
2359 rev_cyc_cnt = 0;
2360 case1_flag = 0;
2361 case1_flag = 0;
2362 }
2363 }
2364}
2365
2366task ncu_intf_cov::set_ncu_ucb_cov_point(string myname,
2367 reg [5:0] ucb_data_width,
2368 var reg [3:0] ncu_ucb_type,
2369 var reg [5:0] ncu_ucb_cpuid ,
2370 var reg [1:0] ncu_ucb_bufid ,
2371 var reg [39:0] ncu_ucb_add ,
2372 var reg [2:0] ncu_ucb_size ,
2373 var reg [31:0] b2b_cnt,
2374 var reg [31:0] stall_b2b_cnt,
2375 var reg [31:0] vld_to_stall_cnt,
2376 var reg [31:0] ucb_pkt_gap,
2377 ncu_cov_com_io_port1 dw_ucbpt,
2378 var event ncu_ucb_sample_evnt_trig
2379){
2380
2381 reg [127:0] rev_pkt;
2382 reg [5:0] rev_cyc_cnt;
2383 reg get_pkt_flag;
2384 reg ucb_pkt_gap_flag = 0;
2385
2386 get_pkt_flag = 0;
2387 rev_cyc_cnt = 0;
2388
2389 ucb_pkt_gap= 0;
2390
2391
2392 myname = {myname, ".set_ncu_ucb_cov_point"};
2393 //dbg.dispmon(myname, MON_DEBUG, psprintf("receive_pkts() task is on"));
2394 b2b_cnt=0;
2395 stall_b2b_cnt = 0;
2396 vld_to_stall_cnt = 0;
2397 while (1) {
2398 @(posedge dw_ucbpt.\$clk);
2399//----------------
2400 fork
2401 if (dw_ucbpt.\$valid && !dw_ucbpt.\$stall_in){
2402 vld_to_stall_cnt++;
2403 } else if (~dw_ucbpt.\$valid || dw_ucbpt.\$stall_in){
2404 if (dw_ucbpt.\$stall_in){
2405 @(posedge dw_ucbpt.\$clk);
2406 }
2407 vld_to_stall_cnt = 0;
2408 }
2409 join none
2410
2411 if (dw_ucbpt.\$valid) {
2412 if (ucb_pkt_gap>0){
2413 dbg.dispmon(myname, MON_INFO, psprintf("ucb_pkt_gap %0d", ucb_pkt_gap));
2414 trigger (ncu_ucb_sample_evnt_trig);
2415 }
2416 fork {
2417 @(negedge dw_ucbpt.\$clk);
2418 ucb_pkt_gap = 0;
2419 ucb_pkt_gap_flag = 1;
2420 } join none
2421 } else {
2422 if (ucb_pkt_gap_flag) {
2423 ucb_pkt_gap++;
2424 }
2425 }
2426//----------------
2427 if (dw_ucbpt.\$stall_in){
2428 stall_b2b_cnt++;
2429 trigger (ncu_ucb_sample_evnt_trig);
2430 } else {
2431 stall_b2b_cnt = 0;
2432 }
2433
2434//----------------
2435 if (dw_ucbpt.\$valid && !dw_ucbpt.\$stall_in){
2436 reg [8:0] up_bits;
2437 reg [8:0] low_bits;
2438 up_bits = (ucb_data_width*(rev_cyc_cnt+1)) -1;
2439 low_bits = ucb_data_width*rev_cyc_cnt;
2440 rev_pkt[up_bits:low_bits] = dw_ucbpt.\$data;
2441 //rev_pkt[(ucb_data_width*(rev_cyc_cnt+1))-1:ucb_data_width*rev_cyc_cnt] = up_ucbpt.\$data;
2442 get_pkt_flag = 1;
2443 dbg.dispmon(myname, MON_INFO, psprintf("rev_pkt %0h, rev_pkt[%0d:%0d] %0h ucb_data_width %0d rev_cyc_cnt %0d get_pkt_flag %h",
2444 rev_pkt, up_bits, low_bits, rev_pkt[up_bits:low_bits], ucb_data_width,rev_cyc_cnt,get_pkt_flag));
2445 rev_cyc_cnt++;
2446 } else if (!dw_ucbpt.\$valid && get_pkt_flag) { // get one pakcet for check
2447 rev_cyc_cnt = 0;
2448 get_pkt_flag = 0;
2449 ncu_ucb_type = rev_pkt[3:0];
2450 ncu_ucb_cpuid = rev_pkt[9:4];
2451 ncu_ucb_bufid = rev_pkt[11:10];
2452 ncu_ucb_add = rev_pkt[54:15];
2453 ncu_ucb_size = rev_pkt[14:12];
2454 b2b_cnt++;
2455 dbg.dispmon(myname, MON_INFO, psprintf("type %h cpu id %h buffer id %h, b2b_cnt %0d",
2456 ncu_ucb_type, ncu_ucb_cpuid, ncu_ucb_bufid, b2b_cnt));
2457 trigger (ncu_ucb_sample_evnt_trig);
2458 } else if (!get_pkt_flag) {
2459 b2b_cnt = 0;
2460 }
2461 }
2462 //dbg.dispmon(myname, MON_DEBUG, psprintf("task is off"));
2463}
2464task ncu_intf_cov::set_cpx_cov_point (string myname, ncu_cov_cpx_port cpxpt)
2465{
2466 myname = {myname, ".set_cpx_cov_point"};
2467
2468 //dbg.dispmon(myname, MON_DEBUG, psprintf("Task is on"));
2469 ncu_cpx_b2b=0;
2470 while (1) {
2471 @(posedge cpxpt.\$clk);
2472 if (|cpxpt.\$gnt ){
2473 if (ncu_cpx_cpu == cpxpt.\$gnt){
2474 ncu_cpx_req_to_gnt_cnt = 0;
2475 }
2476 }
2477
2478 if (| cpxpt.\$req) {
2479 reg [4:0] idx;
2480 ncu_cpx_cpu = cpxpt.\$req;
2481 ncu_cpx_req_to_gnt_cnt++;
2482 for (idx=0; idx <8; idx++){
2483 if (ncu_cpx_cpu[idx] ){
2484 ncu_cpx_cpu_thr_id[5:3] = idx;
2485 }
2486 }
2487 ncu_cpx_type = cpxpt.\$data[144:141];
2488 ncu_cpx_err = cpxpt.\$data[139:138];
2489 ncu_cpx_cpu_thr_id[2:0] = cpxpt.\$data[136:134];
2490 ncu_cpx_b2b++;
2491 if(ncu_cpx_type === 4'b0111){
2492 ncu_cpx_int_vec = cpxpt.\$data[5:0];
2493 }
2494
2495 ncu_io_sample_flag = 1;
2496 trigger (cpx_sample_evnt_trig);
2497 dbg.dispmon(myname, MON_INFO, psprintf("type %h cpu %h err %h, thr_id %h b2b_cnt %0d",
2498 ncu_cpx_type, ncu_cpx_cpu, ncu_cpx_err, ncu_cpx_cpu_thr_id, ncu_cpx_b2b));
2499 } else {
2500
2501 ncu_cpx_cpu = 8'hxx;
2502 ncu_cpx_type = 4'hx;
2503 ncu_cpx_err = 2'hx;
2504 ncu_cpx_cpu_thr_id = 6'hxx;
2505 ncu_cpx_int_vec = 6'hxx;
2506 ncu_cpx_b2b=0;
2507 }
2508 }
2509
2510}
2511
2512task ncu_intf_cov::set_siu_cov_point (string myname, ncu_cov_siu_port siupt)
2513{
2514 reg [6:0] index;
2515 reg rev_pkt_flag;
2516 reg [159:0] rev_pkt;
2517 reg siu_ncu_pkt_gap_cnt_flag = 0;
2518 bit [127:0] siu_playload ;
2519
2520
2521 myname = {myname, ".set_siu_cov_point"};
2522
2523 index = 0;
2524 rev_pkt_flag = 0;
2525 ncu_siu_b2b=0;
2526 //dbg.dispmon(myname, MON_DEBUG, psprintf(" task is on"));
2527 while (1) {
2528 @ (posedge siupt.\$clk);
2529
2530 //=============================
2531 if (siu_int_flag ){
2532 siu_spc_int_skew++;
2533 siu_niu_int_skew++;
2534 siu_ssi_int_skew++;
2535 siu_int_flag = 0;
2536 } else if (siu_spc_int_skew <= 10){
2537 siu_spc_int_skew++;
2538 siu_niu_int_skew++;
2539 siu_ssi_int_skew++;
2540 } else {
2541 siu_spc_int_skew = 4'hf;
2542 siu_ssi_int_skew = 4'hf;
2543 siu_niu_int_skew = 4'hf;
2544 }
2545
2546 if (rev_pkt_flag) {
2547 reg [8:0] up_bits;
2548 reg [8:0] low_bits;
2549 if (index >0){
2550 up_bits = index*32-1;
2551 low_bits = (index-1)*32;
2552 rev_pkt[up_bits:low_bits] = siupt.\$data;
2553 dbg.dispmon(myname, MON_INFO, psprintf("rev_pkt %0h, rev_pkt[%0d:%0d] %h", rev_pkt, up_bits, low_bits, rev_pkt[up_bits:low_bits]));
2554 }
2555 if (index == 0 && ~rev_pkt[15]){
2556 siu_int_flag = 1;
2557
2558 }
2559 if (siupt.\$req){
2560 ncu_siu_req_cnt++;
2561 }
2562 index++;
2563 if (index >5) {
2564 index=0;
2565 rev_pkt_flag = 0;
2566 ncu_siu_err = rev_pkt[31:28];
2567 ncu_siu_pio = rev_pkt[15];
2568 if (rev_pkt[15]){
2569 ncu_siu_credid = rev_pkt[11:8];
2570 ncu_siu_cpu = rev_pkt[5:0];
2571 ncu_siu_bufid = rev_pkt[7:6];
2572 } else {
2573 siu_playload = rev_pkt[159:32];
2574
2575 ncu_siu_cpu = siu_playload[43:38];
2576 ncu_siu_mondid = {rev_pkt[14:11],rev_pkt[2:1]};
2577 }
2578 ncu_siu_b2b++;
2579 trigger (siu_sample_evnt_trig);
2580 dbg.dispmon(myname, MON_INFO, psprintf("rev_pkt %0h, siu_playload %h", rev_pkt,siu_playload ));
2581 dbg.dispmon(myname, MON_INFO, psprintf("err %h credid %h mondid %h, bufid %h b2b_cnt %0d, cpu %0d, pio %b", ncu_siu_err, ncu_siu_credid, ncu_siu_mondid, ncu_siu_bufid, ncu_siu_b2b, ncu_siu_cpu, ncu_siu_pio));
2582
2583 }
2584 } else {
2585 ncu_siu_cpu = 6'hxx;
2586 ncu_siu_bufid = 2'hx;
2587 ncu_siu_credid = 4'hx;
2588 ncu_siu_mondid = 6'hxx;
2589 ncu_siu_type = 1'bx;
2590 ncu_siu_err = 3'hx;
2591 ncu_siu_b2b = 0;
2592 ncu_siu_pio = 1'bx;
2593 }
2594 if (siupt.\$gnt){
2595 rev_pkt_flag = 1;
2596 trigger (siu_sample_evnt_trig);
2597 siu_ncu_pkt_gap_cnt_flag = 1;
2598
2599 fork
2600 {
2601 @(posedge siupt.\$clk);
2602 siu_ncu_pkt_gap_cnt = 0;
2603 }
2604 join none
2605 ncu_siu_req_cnt = 0;
2606
2607 } else {
2608 if (siu_ncu_pkt_gap_cnt_flag){
2609 siu_ncu_pkt_gap_cnt++;
2610 }
2611 }
2612 }
2613
2614}
2615task ncu_intf_cov::set_pio_cov_point (string myname, ncu_cov_pio_port piopt)
2616{
2617
2618 reg [63:0] rev_hdr;
2619 reg data_valid =0;
2620 reg mmu_vld_flag = 0;
2621 reg pio_vld_flag = 0;
2622 ncu_pio_b2b=0;
2623 myname = {myname, ".set_pio_cov_point"};
2624 while (1) {
2625 @(posedge piopt.\$clk);
2626 if (ncu_cov_ios.dmu_ncu_wrack_vld){
2627 trigger (pio_sample_evnt_trig);
2628 }
2629///---------for pkt_gap-----------
2630 if (pio_vld_flag && piopt.\$mmu_vld){
2631 ncu_pio_mmu[1] = 1'b1;
2632 trigger (pio_sample_evnt_trig);
2633 } else if (piopt.\$hdr_vld) {
2634 pio_vld_flag = 1;
2635 dbg.dispmon(myname, MON_INFO, psprintf("mmu_vld_flag %h pio_vld_flag %h ncu_pio_mmu %b, mmu_vld %h",mmu_vld_flag,pio_vld_flag,ncu_pio_mmu, piopt.\$mmu_vld));
2636 trigger (pio_sample_evnt_trig);
2637 } else {
2638 pio_vld_flag = 0;
2639 }
2640 if (mmu_vld_flag && piopt.\$hdr_vld){
2641 ncu_pio_mmu[2] = 1'b1;
2642 trigger (pio_sample_evnt_trig);
2643 } else if (piopt.\$mmu_vld){
2644 ncu_pio_mmu[0] = 1'b1;
2645 mmu_vld_flag = 1;
2646 dbg.dispmon(myname, MON_INFO, psprintf("mmu_vld_flag %h pio_vld_flag %h ncu_pio_mmu %b, mmu_vld %h",mmu_vld_flag,pio_vld_flag,ncu_pio_mmu, piopt.\$mmu_vld));
2647 trigger (pio_sample_evnt_trig);
2648 } else {
2649 mmu_vld_flag = 0;
2650 }
2651
2652
2653///---------for pkt_gap-----------
2654 if (piopt.\$hdr_vld) {
2655 if (ncu_pio_pkt_gap>0){
2656 trigger (pio_sample_evnt_trig);
2657 }
2658 ncu_pio_pkt_gap = 0;
2659 } else {
2660 ncu_pio_pkt_gap++;
2661 }
2662
2663///---------for pio_pkt-----------
2664 if (piopt.\$hdr_vld) {
2665 rev_hdr = piopt.\$data;
2666 ncu_pio_type = rev_hdr[60];
2667 ncu_pio_credit = rev_hdr[58:55];
2668 ncu_pio_size = rev_hdr[53:50];
2669 ncu_pio_bufid = rev_hdr[47:46];
2670 ncu_pio_cpu = rev_hdr[45:40];
2671 ncu_pio_cmap = rev_hdr[49:48];
2672 ncu_pio_add = rev_hdr[35:0];
2673 ncu_pio_b2b++;
2674 if (!rev_hdr[60]){ data_valid = 1; }
2675 trigger (pio_sample_evnt_trig);
2676 dbg.dispmon(myname, MON_INFO, psprintf("type %h credid %h size %h, bufid %h cpuid %h b2b_cnt %0d",
2677 ncu_pio_type, ncu_pio_credit, ncu_pio_size, ncu_pio_bufid, ncu_pio_cpu, ncu_pio_b2b));
2678 } else if (data_valid){
2679 data_valid = 0;
2680 ncu_pio_type = 1'bx;
2681 ncu_pio_credit = 4'hx;
2682 ncu_pio_size = 4'hx;
2683 ncu_pio_cmap = 2'hx;
2684 ncu_pio_bufid = 2'hx;
2685 ncu_pio_cpu = 5'hxx;
2686 ncu_pio_add = 35'hxxxxxxxxx;
2687 dbg.dispmon(myname, MON_INFO, psprintf("type %h credid %h size %h, bufid %h cpuid %h b2b_cnt %0d",
2688 ncu_pio_type, ncu_pio_credit, ncu_pio_size, ncu_pio_bufid, ncu_pio_cpu, ncu_pio_b2b));
2689 } else {
2690 ncu_pio_b2b = 0;
2691 }
2692 }
2693}
2694task ncu_intf_cov::set_mondo_cov_point (string myname, reg [1:0] mondo_id, var reg [3:0] mondo_wait_id_reg, reg mondo_type=0)
2695{
2696reg [1:0] mondo_id0;
2697reg [1:0] mondo_id1;
2698reg [1:0] mondo_id2;
2699reg mondo_req_ack_hit0;
2700reg mondo_req_ack_hit1;
2701reg mondo_req_ack_hit2;
2702reg [5:0] mondo_id_nack;
2703reg mondo_id_nack_flag = 0;
2704
2705 myname = {myname, ".set_mondo_cov_point"};
2706 mondo_id0 = mondo_id+1;
2707 mondo_id1 = mondo_id+2;
2708 mondo_id2 = mondo_id+3;
2709
2710 while (1){
2711 @(posedge ncu_cov_ios.clk);
2712 if (mondo_type){
2713 if (ncu_cov_ios.ncu_dmu_mondo_nack ){
2714 mondo_id_nack = ncu_cov_ios.ncu_dmu_mondo_id;
2715 mondo_id_nack_flag = 1;
2716 } else if (mondo_id_nack_flag && (ncu_cov_ios.ncu_dmu_mondo_id !== mondo_id_nack) && ncu_cov_ios.ncu_dmu_mondo_ack){
2717 mondo_ack_nack_cov_flag = 1;
2718 mondo_id_nack_flag = 0;
2719 trigger (mondo_wait_id_reg_cov_trig);
2720 } else if (mondo_id_nack_flag && (ncu_cov_ios.ncu_dmu_mondo_id == mondo_id_nack) && ncu_cov_ios.ncu_dmu_mondo_ack){
2721 mondo_id_nack_flag = 0;
2722 }
2723 } else {
2724 if (ncu_cov_ios.ncu_dmu_mondo_nack && (ncu_cov_ios.ncu_dmu_mondo_id[1:0] == mondo_id)){
2725
2726 fork
2727 detect_other_mondo_int(myname, mondo_id, mondo_id0,mondo_req_ack_hit0);
2728 detect_other_mondo_int(myname, mondo_id, mondo_id1,mondo_req_ack_hit1);
2729 detect_other_mondo_int(myname, mondo_id, mondo_id2,mondo_req_ack_hit2);
2730 join
2731
2732 mondo_wait_id_reg[mondo_id0] = mondo_req_ack_hit0;
2733 mondo_wait_id_reg[mondo_id1] = mondo_req_ack_hit1;
2734 mondo_wait_id_reg[mondo_id2] = mondo_req_ack_hit2;
2735 mondo_wait_id_reg[mondo_id] = 1'b1;
2736 dbg.dispmon(myname, MON_INFO, psprintf(" %0d mondo pending and other monod ack. mondo_wait_id_reg %0h", mondo_id, mondo_wait_id_reg));
2737 trigger (mondo_wait_id_reg_cov_trig);
2738 }
2739 }
2740 }
2741}
2742
2743task ncu_intf_cov::detect_other_mondo_int (string myname, reg [1:0] mondo_id, reg [1:0] detect_mondo_id, var reg mondo_req_ack_hit)
2744{
2745reg main_mondo_ack = 1;
2746reg ncu_siu_hdr_flag = 0;
2747 myname = {myname, ".detect_other_mondo_int"};
2748 mondo_req_ack_hit = 0;
2749 dbg.dispmon(myname, MON_INFO, psprintf(" %0d mondo pending and waiting monod %0d complete.", mondo_id, detect_mondo_id));
2750 while (main_mondo_ack){
2751 @(posedge ncu_cov_ios.clk);
2752 if ( ncu_cov_ios.ncu_dmu_mondo_ack && (ncu_cov_ios.ncu_dmu_mondo_id[1:0] == mondo_id)){
2753 main_mondo_ack = 0;
2754 dbg.dispmon(myname, MON_INFO, psprintf(" Get %0d mondo ack for mondo %0d. Exist routine ", mondo_id, detect_mondo_id));
2755 }
2756 if (ncu_cov_ios.ncu_dmu_mondo_ack && (ncu_cov_ios.ncu_dmu_mondo_id[1:0] === detect_mondo_id)){
2757 mondo_req_ack_hit = 1;
2758 main_mondo_ack = 0;
2759 dbg.dispmon(myname, MON_INFO, psprintf(" pending mondo %0d get %0d mondo interrupt ack .", mondo_id, detect_mondo_id));
2760 }
2761 }
2762 dbg.dispmon(myname, MON_INFO, psprintf(" %0d mondo pending and waiting monod %0d complete done.", mondo_id, detect_mondo_id));
2763}
2764
2765
2766task ncu_intf_cov::set_ncu_ras_soc_report_point (string myname, ncu_cov_com_io_port ncu_pcxpt, ncu_cov_cpx_port cpxpt)
2767{
2768 reg [39:0] pcx_add;
2769 reg [7:0] pcx_size;
2770 reg [4:0] pcx_type;
2771 reg [2:0] pcx_cpu;
2772 reg [2:0] pcx_thr;
2773 reg [7:0] cpx_cpu;
2774 reg [2:0] cpx_thr;
2775 reg [3:0] cpx_type;
2776 reg per_read_flag;
2777
2778 myname = {myname, ".set_ncu_ras_soc_report_point"};
2779 per_read_flag = 0;
2780
2781 fork
2782 while (1) {
2783 @ (posedge ncu_pcxpt.\$clk);
2784 if (!ncu_pcxpt.\$stall && ncu_pcxpt.\$valid) {
2785 pcx_add = ncu_pcxpt.\$data[103:64];
2786 pcx_type = ncu_pcxpt.\$data[128:124];
2787 pcx_size = ncu_pcxpt.\$data[111:104];
2788
2789 dbg.dispmon(myname, MON_INFO, psprintf("pcx_add %h pcx_type %h size %h ", pcx_add, pcx_type, pcx_size));
2790 if ((pcx_add == NCU_PER_REG) && (pcx_type == PCX_PKT_LOAD) && (pcx_size == PCX_LOAD_8BYTE)){
2791 pcx_cpu = ncu_pcxpt.\$data[122:120];
2792 pcx_thr = ncu_pcxpt.\$data[119:117];
2793 per_read_flag = 1;
2794 //dbg.dispmon(myname, MON_INFO, psprintf(" PER read"));
2795 dbg.dispmon(myname, MON_INFO, psprintf("pcx_cpu %h pcx_thr %h per_read_flag %h ", pcx_cpu, pcx_thr, per_read_flag));
2796 }
2797
2798 }
2799 }
2800
2801 while (1) {
2802 @(posedge cpxpt.\$clk);
2803 if (per_read_flag){
2804 dbg.dispmon(myname, MON_INFO, psprintf(" cpx_pcu %0h cpx_type %0h, cpx_thr %h ", cpx_cpu, cpx_type, cpx_thr));
2805 if (|cpxpt.\$req) {
2806 cpx_cpu = cpxpt.\$req;
2807
2808 cpx_type = cpxpt.\$data[144:141];
2809 cpx_thr = cpxpt.\$data[136:134];
2810
2811 dbg.dispmon(myname, MON_INFO, psprintf(" cpx_cpu %0h cpx_type %0h, pcx_thr %h , pcx_cpu %0d", cpx_cpu, cpx_type, cpx_thr, pcx_cpu));
2812 if ((cpx_cpu[pcx_cpu]) && (pcx_thr == cpx_thr) && (cpx_type == CPX_PKT_LOAD_RTN)){
2813 ncu_soc_err[23:0] = cpxpt.\$data[23:0];
2814 ncu_soc_err[28:24] = cpxpt.\$data[29:25];
2815 ncu_soc_err[30:29] = cpxpt.\$data[32:31];
2816 ncu_soc_err[32:31] = cpxpt.\$data[35:34];
2817 ncu_soc_err[34:33] = cpxpt.\$data[38:37];
2818 ncu_soc_err[37:35] = cpxpt.\$data[42:40];
2819 per_read_flag = 0;
2820 trigger (ncu_soc_report_sample_evnt_trig);
2821 dbg.dispmon(myname, MON_INFO, psprintf(" ncu_soc_report_sample_evnt_trig is trigger data %0h, ncu_soc_err %0h", cpxpt.\$data, ncu_soc_err));
2822
2823 }
2824
2825 }
2826 }
2827
2828 }
2829
2830 join
2831
2832
2833}
2834
2835function reg ncu_intf_cov::count_pkt_num(string myname, reg [1000:0] base_reg, reg [9:0] pkt_num)
2836{
2837reg [9:0] reg_1_cnt = 0;
2838reg [31:0] base_reg_idx = 0;
2839reg multi_pkt_hit = 0;
2840
2841 myname={myname, ".count_pkt_num"};
2842 dbg.dispmon(myname, MON_INFO, psprintf("base_reg %0h, pkt_num %0d", base_reg, pkt_num));
2843 while (|base_reg){
2844 if (base_reg[base_reg_idx]){
2845 base_reg[base_reg_idx]=0;
2846 reg_1_cnt++;
2847 }
2848 base_reg_idx++;
2849 }
2850 if (reg_1_cnt >= pkt_num){
2851 multi_pkt_hit = 1;
2852 }
2853 dbg.dispmon(myname, MON_INFO, psprintf("reg_1_cnt %0d multi_pkt_hit %b\n", reg_1_cnt, multi_pkt_hit));
2854 count_pkt_num = multi_pkt_hit;
2855}
2856
2857task ncu_intf_cov::set_int_pkt_points (string myname)
2858{
2859reg [9:0] niu_int_reg = 0;
2860reg [9:0] spc_int_reg = 0;
2861reg [9:0] siu_int_reg = 0;
2862reg [9:0] ssi_int_reg = 0;
2863reg [39:0] cpx_int_reg =0;
2864reg niu_multi_pkt_hit;
2865reg siu_multi_pkt_hit;
2866reg ssi_multi_pkt_hit;
2867reg spc_multi_pkt_hit;
2868reg [3:0] trip_int_reg_idx = 0;
2869reg [5:0] cpx_int_reg_idx = 0;
2870 myname = {myname, ".set_int_pkt_points"};
2871 while (1){
2872
2873 @(posedge ncu_cov_ios.clk);
2874 niu_int_reg[trip_int_reg_idx] = ncu_cov_ios.niu_int_vld ;
2875 siu_int_reg[trip_int_reg_idx] = ncu_cov_ios.sii_mondo_vld;
2876 ssi_int_reg[trip_int_reg_idx] = ncu_cov_ios.ssi_int_vld ;
2877 spc_int_reg[trip_int_reg_idx] = ncu_cov_ios.spc_int_vld;
2878 cpx_int_reg[cpx_int_reg_idx] = ncu_cov_ios.spc_int_vld;
2879
2880 if (ncu_cov_ios.spc_int_vld | ncu_cov_ios.niu_int_vld |ncu_cov_ios.sii_mondo_vld |ncu_cov_ios.ssi_int_vld)
2881 {
2882
2883 ncu_cpx_int_multi_pkt[0] = count_pkt_num(myname, cpx_int_reg, 5);
2884 ncu_cpx_int_multi_pkt[1] = count_pkt_num(myname, cpx_int_reg, 10);
2885 ncu_cpx_int_multi_pkt[2] = count_pkt_num(myname, cpx_int_reg, 15);
2886 ncu_cpx_int_multi_pkt[3] = count_pkt_num(myname, cpx_int_reg, 20);
2887
2888 niu_siu_ssi[0] = ncu_cov_ios.niu_int_vld && ncu_cov_ios.sii_mondo_vld && ncu_cov_ios.ssi_int_vld;
2889
2890 siu_ssi_spc[0] = ncu_cov_ios.sii_mondo_vld && ncu_cov_ios.ssi_int_vld && ncu_cov_ios.spc_int_vld;
2891
2892 ssi_spc_niu[0] = ncu_cov_ios.ssi_int_vld && ncu_cov_ios.spc_int_vld && ncu_cov_ios.niu_int_vld;
2893
2894 spc_niu_siu[0] = ncu_cov_ios.spc_int_vld && ncu_cov_ios.niu_int_vld && ncu_cov_ios.sii_mondo_vld;
2895
2896
2897 niu_multi_pkt_hit = count_pkt_num(myname, niu_int_reg, 5);
2898 siu_multi_pkt_hit = count_pkt_num(myname, siu_int_reg, 5);
2899 ssi_multi_pkt_hit = count_pkt_num(myname, ssi_int_reg, 5);
2900 spc_multi_pkt_hit = count_pkt_num(myname, spc_int_reg, 5);
2901
2902 niu_siu_ssi[1] = niu_multi_pkt_hit && siu_multi_pkt_hit && ssi_multi_pkt_hit;
2903
2904 siu_ssi_spc[1] = siu_multi_pkt_hit && ssi_multi_pkt_hit && spc_multi_pkt_hit;
2905
2906 ssi_spc_niu[1] = ssi_multi_pkt_hit && spc_multi_pkt_hit && niu_multi_pkt_hit;
2907
2908 spc_niu_siu[1] = spc_multi_pkt_hit && niu_multi_pkt_hit && siu_multi_pkt_hit;
2909
2910 niu_siu_ssi[2] = |niu_int_reg && |siu_int_reg && |ssi_int_reg;
2911
2912 siu_ssi_spc[2] = |siu_int_reg && |ssi_int_reg && |spc_int_reg;
2913
2914 ssi_spc_niu[2] = |ssi_int_reg && |spc_int_reg && |niu_int_reg;
2915
2916 spc_niu_siu[2] = |spc_int_reg && |niu_int_reg && |siu_int_reg;
2917
2918 dbg.dispmon(myname, MON_INFO, psprintf(" niu_int_reg %b, siu_int_reg %b ssi_int_reg %b spc_int_reg %b cpx_int_reg %b",
2919 niu_int_reg, siu_int_reg, ssi_int_reg, spc_int_reg, cpx_int_reg));
2920
2921 dbg.dispmon(myname, MON_INFO, psprintf(" niu_siu_ssi %b, siu_ssi_spc %b ssi_spc_niu %b spc_niu_siu %b,spc_multi_pkt_hit %b",
2922 niu_siu_ssi, siu_ssi_spc, ssi_spc_niu, spc_niu_siu, spc_multi_pkt_hit));
2923 }
2924 trip_int_reg_idx++;
2925 if (trip_int_reg_idx >9){
2926 trip_int_reg_idx=0;
2927 }
2928 cpx_int_reg_idx++;
2929 if (cpx_int_reg_idx >39){
2930 cpx_int_reg_idx=0;
2931 }
2932
2933 }
2934}
2935
Full OpenSPARC design & verification tarball including full HDL.