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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ncu / ncu_rtl_cov.vrpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ncu_rtl_cov.vrpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include <ListMacros.vrh>
37#include "plusArgMacros.vri"
38#include "std_display_class.vrh"
39#include "std_display_defines.vri"
40#include "ncu_cov.if.vrh"
41#include "ncu_cov_ports_binds.vrh"
42
43
44class ncu_rtl_cov {
45
46string myname;
47StandardDisplay dbg;
48
49
50#include "ncu_rtl_cov_ver_defines.vrh"
51 reg [1:0] cpu_niu_acc_intman =0;
52
53 #ifndef NCU_INTF_COV
54 coverage_group ncu_intman_tbl_cov
55 {
56 const_sample_reference = 1; // ref. to sample vars. is constant
57 sample_event = sync (ANY, intman_sample_evnt_trig );
58 sample intman_tbl_waddr { m_state ADD (0:127) if (intman_tbl_wr); }
59 sample intman_tbl_raddr { m_state ADD (0:127) if (intman_tbl_rd); }
60 sample intman_tbl_wr_b2b { state b2b (1) if (intman_tbl_wr); }
61 sample intman_tbl_rd_b2b { m_state b2b (1:2) if (intman_tbl_rd); }
62 sample intman_tbl_rd_b2b_same_add { m_state b2b_same_add (1:2) if (intman_tbl_rd); }
63
64 sample cpu_niu_acc_intman {
65 wildcard state cpu_niu_read_same_add_of_intman (2'bx1) if (ncu_cov_ios.int_vld && ncu_cov_ios.lhs_intman_acc);
66 wildcard state cpu_niu_read_diff_add_of_intman (2'b1x) if (ncu_cov_ios.int_vld && ncu_cov_ios.lhs_intman_acc);
67 }
68 }
69
70
71 coverage_group ncu_cpu_buf_cov
72 {
73 const_sample_reference = 1; // ref. to sample vars. is constant
74 sample_event = sync (ANY, cpu_buf_sample_evnt_trig );
75 sample cpu_buf_waddr { m_state ADD (0:31) if (cpu_buf_wr);
76 trans ADD_TRAN (31->0->1) if (cpu_buf_wr);
77 }
78 sample cpu_buf_raddr { m_state ADD (0:31) if (cpu_buf_rd);
79 trans ADD_TRAN (31->0->1) if (cpu_buf_rd);
80 }
81 sample cpu_buf_wr_b2b { m_state b2b (1:2) if (cpu_buf_wr); }
82 sample cpu_buf_rd_b2b { m_state b2b (1:2) if (cpu_buf_rd); }
83 }
84 #endif
85
86 coverage_group ncu_io_buf_cov
87 {
88 const_sample_reference = 1; // ref. to sample vars. is constant
89 sample_event = sync (ANY, io_buf_sample_evnt_trig );
90 #ifndef NCU_INTF_COV
91 sample io_buf_wr_b2b { m_state b2b (1:2) if (io_buf_wr); }
92 sample io_buf_rd_b2b { m_state b2b (1:2) if (io_buf_rd); }
93 #endif
94 sample io_buf_waddr { m_state ADD (0:31) if (io_buf_wr);
95 trans ADD_TRAN (31->0->1) if (io_buf_wr);
96 }
97 sample io_buf_raddr { m_state ADD (0:31) if (io_buf_rd);
98 trans ADD_TRAN (31->0->1) if (io_buf_rd);
99 }
100 }
101
102 coverage_group ncu_int_buf_cov
103 {
104 const_sample_reference = 1; // ref. to sample vars. is constant
105 sample_event = sync (ANY, int_buf_sample_evnt_trig );
106 #ifndef NCU_INTF_COV
107 sample int_buf_wr_b2b { m_state b2b (1:2) if (int_buf_wr); }
108 sample int_buf_rd_b2b { m_state b2b (1:2) if (int_buf_rd); }
109 #endif
110 sample int_buf_waddr { m_state ADD (0:31) if (int_buf_wr);
111 trans ADD_TRAN (31->0->1) if (int_buf_wr);
112 }
113 sample int_buf_raddr { m_state ADD (0:31) if (int_buf_rd);
114 trans ADD_TRAN (31->0->1) if (int_buf_rd);
115 }
116 }
117
118 coverage_group ncu_mondo_data_tbl_cov
119 {
120 const_sample_reference = 1; // ref. to sample vars. is constant
121 sample_event = sync (ANY, mondo_data_tbl_sample_evnt_trig );
122 #ifndef NCU_INTF_COV
123 sample mondo_data1_tbl_waddr { m_state ADD (0:63) if (mondo_data1_tbl_wr); }
124 sample mondo_data0_tbl_wr_b2b { m_state b2b (1:2) if (mondo_data0_tbl_wr); }
125 sample mondo_data1_tbl_wr_b2b { m_state b2b (1:2) if (mondo_data1_tbl_wr); }
126 sample mondo_data_tbl_rd_b2b { m_state b2b (1:2) if (mondo_data_tbl_rd); }
127 sample mondo_data_tbl_rd_b2b_same_add { m_state b2b_same_add (0:1) if (mondo_data_tbl_rd); }
128 #endif
129 sample mondo_data0_tbl_waddr { m_state ADD (0:63) if (mondo_data0_tbl_wr); }
130 sample mondo_data_tbl_raddr { m_state ADD (0:63) if (mondo_data_tbl_rd); }
131 }
132 task new(string myname, StandardDisplay dbg);
133 task set_intman_tbl_point(string myname);
134 task set_mondo_tbl_point(string myname);
135 task set_cpu_buf_point(string myname);
136 task set_io_buf_point(string myname);
137 task set_int_buf_point(string myname);
138}
139task ncu_rtl_cov :: new(string myname, StandardDisplay dbg){
140 this.myname = myname;
141 this.dbg = dbg;
142 fork
143 set_intman_tbl_point(myname);
144 set_mondo_tbl_point(myname);
145 set_cpu_buf_point(myname);
146 set_io_buf_point(myname);
147 set_int_buf_point(myname);
148 join none
149}
150task ncu_rtl_cov :: set_io_buf_point(string myname)
151{
152
153 myname = {myname, ".set_io_buf_point"};
154 io_buf_wr_b2b = 0;
155 io_buf_rd_b2b = 0;
156
157fork
158 while (1) {
159 @(posedge ncu_rtl_ccx_cov.clk);
160 io_buf_rd = ncu_rtl_ccx_cov.io_buf_rd;
161 if ( io_buf_rd ){
162 io_buf_rd_b2b++;
163 io_buf_raddr = ncu_rtl_ccx_cov.io_buf_raddr;
164
165 dbg.dispmon(myname, MON_INFO, psprintf("IOBUFFERR read triggered. io_buf_raddr %0d, io_buf_rd_b2b %0d\n",io_buf_raddr, io_buf_rd_b2b));
166 trigger (io_buf_sample_evnt_trig);
167 } else {
168 io_buf_rd_b2b = 0;
169 }
170 }
171 while (1){
172 @(posedge ncu_rtl_io_cov.clk);
173 io_buf_wr = ncu_rtl_io_cov.io_buf_wr;
174 if (io_buf_wr){
175 io_buf_waddr = ncu_rtl_io_cov.io_buf_waddr;
176 io_buf_wr_b2b++;
177 dbg.dispmon(myname, MON_INFO, psprintf("IOBUFFERR Write triggered. io_buf_wr %0d, io_buf_wr_b2b %0d\n",io_buf_wr, io_buf_wr_b2b));
178 trigger (io_buf_sample_evnt_trig);
179 } else {
180 io_buf_wr_b2b = 0;
181 }
182 }
183 join
184
185}
186task ncu_rtl_cov :: set_cpu_buf_point(string myname)
187{
188
189 myname = {myname, ".set_cpu_buf_point"};
190 cpu_buf_wr_b2b = 0;
191 cpu_buf_rd_b2b = 0;
192
193fork
194 while (1) {
195 @(posedge ncu_rtl_io_cov.clk);
196 cpu_buf_rd = ncu_rtl_io_cov.cpu_buf_rd && ncu_rtl_io_cov.cpu_buf_rd_sel;
197 if ( cpu_buf_rd ){
198 cpu_buf_rd_b2b++;
199 cpu_buf_raddr = ncu_rtl_io_cov.cpu_buf_raddr;
200 dbg.dispmon(myname, MON_INFO, psprintf("CPU BUFFER read triggered. cpu_buf_raddr %0d, cpu_buf_rd_b2b %0d\n",cpu_buf_raddr, cpu_buf_rd_b2b));
201 trigger (cpu_buf_sample_evnt_trig);
202 } else {
203 cpu_buf_rd_b2b = 0;
204 }
205 }
206 while (1){
207 @(posedge ncu_rtl_ccx_cov.clk);
208 cpu_buf_wr = ncu_rtl_ccx_cov.cpu_buf_wr;
209 if (cpu_buf_wr){
210 cpu_buf_waddr = ncu_rtl_ccx_cov.cpu_buf_waddr;
211 cpu_buf_wr_b2b++;
212 dbg.dispmon(myname, MON_INFO, psprintf("CPU BUFFER Write triggered. cpu_buf_wr %0d, cpu_buf_wr_b2b %0d\n",cpu_buf_wr, cpu_buf_wr_b2b));
213 trigger (cpu_buf_sample_evnt_trig);
214 } else {
215 cpu_buf_wr_b2b = 0;
216 }
217 }
218 join
219
220
221}
222
223task ncu_rtl_cov :: set_mondo_tbl_point(string myname)
224{
225
226 myname = {myname, ".set_mondo_tbl_point"};
227 mondo_data0_tbl_wr_b2b = 0;
228 mondo_data1_tbl_wr_b2b = 0;
229 mondo_data_tbl_rd_b2b = 0;
230
231 while (1){
232 @(posedge ncu_rtl_ccx_cov.clk);
233 mondo_data_tbl_rd = ncu_rtl_ccx_cov.mondo_data_tbl_rd ;
234 mondo_data0_tbl_wr = ncu_rtl_ccx_cov.mondo_data0_tbl_wr ;
235 mondo_data1_tbl_wr = ncu_rtl_ccx_cov.mondo_data1_tbl_wr ;
236 mondo_data0_tbl_waddr = ncu_rtl_ccx_cov.mondo_data_tbl_waddr;
237 mondo_data1_tbl_waddr = ncu_rtl_ccx_cov.mondo_data_tbl_waddr;
238 if (mondo_data0_tbl_wr){
239 mondo_data0_tbl_wr_b2b++;
240 } else {
241 mondo_data0_tbl_wr_b2b = 0;
242 mondo_data0_tbl_waddr = 0;
243 }
244 if (mondo_data1_tbl_wr){
245 mondo_data1_tbl_wr_b2b++;
246 } else {
247 mondo_data1_tbl_wr_b2b = 0;
248 mondo_data1_tbl_waddr = 0;
249 }
250
251 if ( mondo_data_tbl_rd ){
252 if (mondo_data_tbl_raddr === ncu_rtl_ccx_cov.mondo_data_tbl_raddr){
253 mondo_data_tbl_rd_b2b_same_add++;
254 }
255 mondo_data_tbl_rd_b2b++;
256 mondo_data_tbl_raddr = ncu_rtl_ccx_cov.mondo_data_tbl_raddr;
257 } else {
258 mondo_data_tbl_rd_b2b = 0;
259 mondo_data_tbl_raddr = 0;
260 mondo_data_tbl_rd_b2b_same_add=0;
261 }
262
263 if (mondo_data0_tbl_wr || mondo_data0_tbl_wr || mondo_data_tbl_rd){
264 trigger (mondo_data_tbl_sample_evnt_trig);
265// printf ("222222 wadd %h radd %h b2b %0d b2b_same %0d\n", mondo_data_tbl_waddr,mondo_data_tbl_raddr,intman_tbl_rd_b2b,intman_tbl_rd_b2b_same_add);
266 }
267 }
268
269
270}
271
272task ncu_rtl_cov :: set_int_buf_point(string myname)
273{
274
275 myname = {myname, ".set_int_buf_point"};
276 int_buf_wr_b2b = 0;
277 int_buf_rd_b2b = 0;
278
279 while (1){
280 @(posedge ncu_rtl_ccx_cov.clk);
281 int_buf_rd = ncu_rtl_ccx_cov.int_buf_rd_sel ;
282 int_buf_wr = ncu_rtl_ccx_cov.int_buf_wr;
283 if (int_buf_wr){
284 int_buf_waddr = ncu_rtl_ccx_cov.int_buf_waddr;
285 int_buf_wr_b2b++;
286 } else {
287 int_buf_wr_b2b = 0;
288 }
289
290 if ( int_buf_rd ){
291 int_buf_rd_b2b++;
292 int_buf_raddr = ncu_rtl_ccx_cov.int_buf_raddr;
293 } else {
294 int_buf_rd_b2b = 0;
295 }
296
297 if (int_buf_wr || int_buf_rd){
298 trigger (int_buf_sample_evnt_trig);
299// printf ("222222 wadd %h radd %h b2b %0d b2b_same %0d\n", int_buf_waddr,int_buf_raddr,int_buf_rd_b2b,int_buf_rd_b2b_same_add);
300 }
301 }
302
303
304}
305
306task ncu_rtl_cov :: set_intman_tbl_point(string myname)
307{
308
309 myname = {myname, ".set_intman_point"};
310 intman_tbl_wr_b2b = 0;
311 intman_tbl_rd_b2b = 0;
312
313 while (1){
314 @(posedge ncu_rtl_io_cov.clk);
315 //intman_tbl_rd = ncu_rtl_io_cov.intman_tbl_rd && (|ncu_rtl_io_cov.int_sel);
316 intman_tbl_rd = ncu_rtl_io_cov.intman_tbl_rd;
317 intman_tbl_wr = ncu_rtl_io_cov.intman_tbl_wr;
318 if (intman_tbl_wr){
319 intman_tbl_waddr = ncu_rtl_io_cov.intman_tbl_waddr;
320 intman_tbl_wr_b2b++;
321 } else {
322 intman_tbl_wr_b2b = 0;
323 intman_tbl_waddr = 0;
324 }
325
326 if ( intman_tbl_rd ){
327 if (intman_tbl_raddr === ncu_rtl_io_cov.intman_tbl_raddr){
328 intman_tbl_rd_b2b_same_add++;
329 }
330 intman_tbl_rd_b2b++;
331
332 intman_tbl_raddr = ncu_rtl_io_cov.intman_tbl_raddr;
333 } else {
334 intman_tbl_rd_b2b = 0;
335 intman_tbl_raddr = 0;
336 intman_tbl_rd_b2b_same_add=0;
337 }
338
339 if (ncu_cov_ios.int_vld && ncu_cov_ios.lhs_intman_acc && (ncu_cov_ios.lhs_intman_addr != ncu_cov_ios.io_intman_addr))
340 {
341 cpu_niu_acc_intman[1] = 1;
342 trigger (intman_sample_evnt_trig);
343 }
344 else if (ncu_cov_ios.int_vld && ncu_cov_ios.lhs_intman_acc && (ncu_cov_ios.lhs_intman_addr == ncu_cov_ios.io_intman_addr))
345 {
346 cpu_niu_acc_intman[0] = 1;
347 trigger (intman_sample_evnt_trig);
348 }
349
350
351
352 if (intman_tbl_wr || intman_tbl_rd){
353 trigger (intman_sample_evnt_trig);
354// printf ("222222 wadd %h radd %h b2b %0d b2b_same %0d\n", intman_tbl_waddr,intman_tbl_raddr,intman_tbl_rd_b2b,intman_tbl_rd_b2b_same_add);
355 }
356 }
357
358
359}
360
361
362/****************************************************************/
363/* Coverage Objects for FC MAQ: */
364/****************************************************************/
365class fc_ncu_internal_coverage
366{
367 // for dispmon
368 StandardDisplay dbg;
369 local string myname;
370
371 reg [5:0] cpx_to_ncu_fifo_cpu_buf_count = 6'd0;
372 reg [5:0] ncu_to_cpx_fifo_iobuf_count = 6'd0;
373 reg [5:0] ncu_to_cpx_fifo_intbuf_count = 6'd0;
374 reg [5:0] old_rd_adr = 6'd0;
375 reg [5:0] old_wr_adr = 6'd0;
376
377 // ----------- coverage_group ----------------
378 coverage_group ncu_in_cpubuf_coverage_group
379 {
380 const_sample_reference = 1; // ref. to sample vars. is constant
381 sample_event = @(negedge cpx_to_ncu_fifo_cpu_buf.wrclk );
382 sample ncu_in_cpubuf_filled (cpx_to_ncu_fifo_cpu_buf_count) // cpx_to_ncu_fifo_cpu_buf_count
383 {
384 m_state fifo_filled (0:31);
385 }
386 }
387
388 // ----------- coverage_group ----------------
389 coverage_group ncu_out_iobuf_coverage_group
390 {
391 const_sample_reference = 1; // ref. to sample vars. is constant
392 sample_event = @(posedge ncu_to_cpx_fifo_iobuf.rdclk );
393 sample ncu_out_iobuf_filled (ncu_to_cpx_fifo_iobuf_count) // ncu_to_cpx_fifo_iobuf_count
394 {
395 m_state fifo_filled (0:31);
396 }
397 }
398
399 // ----------- coverage_group ----------------
400 coverage_group ncu_out_intbuf_coverage_group
401 {
402 const_sample_reference = 1; // ref. to sample vars. is constant
403 sample_event = @(negedge ncu_to_cpx_fifo_intbuf.rdclk);
404 sample ncu_out_intbuf_filled (ncu_to_cpx_fifo_intbuf_count) // ncu_to_cpx_fifo_intbuf_count
405 {
406 m_state fifo_filled (0:31);
407 }
408 }
409
410 task new(StandardDisplay dbg);
411 task set_cov_cond_bits ();
412 task cpx_to_ncu_fifo_cpubuf();
413 task cpx_to_ncu_fifo_iobuffer();
414 task cpx_to_ncu_fifo_intbuffer();
415} //class fc_ncu_internal_coverage
416
417task fc_ncu_internal_coverage::new(StandardDisplay dbg)
418{
419 bit coverage_on = 0;
420 integer j;
421
422 // for dispmon
423 myname = "fc_ncu_internal_coverage";
424 this.dbg = dbg;
425
426 if (mChkPlusarg(fc_ncu_internal_coverage) || mChkPlusarg(coverage_on)) {
427 coverage_on = 1;
428// printf("MAQ-Debug: CPU Internal Coverage Turned On \n");
429 }
430
431 if (coverage_on) {
432 dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Internal Coverage turned on for NCU objects\n\n", get_time(LO)));
433
434 ncu_in_cpubuf_coverage_group = new();
435 ncu_out_iobuf_coverage_group = new();
436 ncu_out_intbuf_coverage_group = new();
437
438 set_cov_cond_bits ();
439 } // if coverage_on
440} // fc_ncu_internal_coverage::new()
441///////////////////////////////////////////////////////////////////////////
442// This task is a psuedo coverage object that combines a few conditions
443// so that the actual coverage objects' state space doesn't get too big
444//////////////////////////////////////////////////////////////////////////
445
446task fc_ncu_internal_coverage:: set_cov_cond_bits ()
447{
448
449fork
450 cpx_to_ncu_fifo_cpubuf();
451 cpx_to_ncu_fifo_iobuffer();
452 cpx_to_ncu_fifo_intbuffer();
453
454join none
455
456} // task fc_ncu_internal_coverage:: set_cov_cond_bits
457
458task fc_ncu_internal_coverage::cpx_to_ncu_fifo_cpubuf()
459{
460
461 while(1)
462 {
463 @(negedge cpx_to_ncu_fifo_cpu_buf.wrclk);
464 if(cpx_to_ncu_fifo_cpu_buf.wr_en == 1)
465 {
466 cpx_to_ncu_fifo_cpu_buf_count = cpx_to_ncu_fifo_cpu_buf_count + 1;
467 dbg.dispmon(myname, MON_INFO, psprintf("\n %d :MAQ-Debug cpx_to_ncu_fifo_cpu_buf.wr_en Seen \n", get_time(LO)));
468 }
469 if(cpx_to_ncu_fifo_cpu_buf.rd_en == 1)
470 {
471 if (cpx_to_ncu_fifo_cpu_buf.rd_adr != old_rd_adr)
472 {
473 dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :B4-Coverage-count for cpx_to_ncu_fifo_cpu_buf_count = %d\n\n", get_time(LO), cpx_to_ncu_fifo_cpu_buf_count));
474 cpx_to_ncu_fifo_cpu_buf_count = cpx_to_ncu_fifo_cpu_buf_count - 1;
475 dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :AFter Coverage-count for cpx_to_ncu_fifo_cpu_buf_count = %d\n\n", get_time(LO), cpx_to_ncu_fifo_cpu_buf_count));
476 }
477 old_rd_adr = cpx_to_ncu_fifo_cpu_buf.rd_adr;
478 }
479 } // while
480}
481task fc_ncu_internal_coverage::cpx_to_ncu_fifo_iobuffer()
482{
483 while(1)
484 {
485 @(negedge ncu_to_cpx_fifo_iobuf.rdclk);
486 {
487 if (ncu_to_cpx_fifo_iobuf.wr_adr != old_wr_adr)
488 {
489 dbg.dispmon(myname, MON_INFO, psprintf("\n %d :MAQ-Debug ncu_to_cpx_fifo_iobuf.wr_en Seen \n", get_time(LO)));
490 ncu_to_cpx_fifo_iobuf_count = ncu_to_cpx_fifo_iobuf_count + 1;
491 }
492 old_wr_adr = ncu_to_cpx_fifo_iobuf.wr_adr;
493
494 if(ncu_to_cpx_fifo_iobuf.rd_en == 1)
495 {
496 dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :B4-Coverage-count for ncu_to_cpx_fifo_iobuf_count = %d\n\n", get_time(LO), ncu_to_cpx_fifo_iobuf_count));
497 @(negedge ncu_to_cpx_fifo_iobuf.rdclk);
498 ncu_to_cpx_fifo_iobuf_count = ncu_to_cpx_fifo_iobuf_count - 1;
499 dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for ncu_to_cpx_fifo_iobuf_count = %d\n\n", get_time(LO), ncu_to_cpx_fifo_iobuf_count));
500 }
501 } // @posedge
502 } // while
503}
504
505task fc_ncu_internal_coverage::cpx_to_ncu_fifo_intbuffer()
506{
507 while(1)
508 {
509 @(negedge ncu_to_cpx_fifo_intbuf.rdclk);
510 {
511 if(ncu_to_cpx_fifo_intbuf.wr_en == 1)
512 ncu_to_cpx_fifo_intbuf_count = ncu_to_cpx_fifo_intbuf_count + 1;
513
514 if(ncu_to_cpx_fifo_intbuf.rd_en == 1)
515 {
516 ncu_to_cpx_fifo_intbuf_count = ncu_to_cpx_fifo_intbuf_count - 1;
517 dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for ncu_to_cpx_fifo_intbuf_count = %d\n\n", get_time(LO), ncu_to_cpx_fifo_intbuf_count));
518 }
519 } // @posedge
520 } // while
521}
522
523/****************************************************************/
Full OpenSPARC design & verification tarball including full HDL.