Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / ncu / ncu_rtl_cov_ver_defines.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ncu_rtl_cov_ver_defines.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
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// choice is available it will apply instead, Sun elects to use only 
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// ========== Copyright Header End ============================================
reg [6:0]   int_sel;
reg [6:0]   intman_tbl_waddr;
reg [6:0]   intman_tbl_raddr;
reg intman_tbl_wr;
reg intman_tbl_rd;

reg [15:0] intman_tbl_wr_b2b;
reg [15:0] intman_tbl_rd_b2b;
reg [15:0] intman_tbl_rd_b2b_same_add;
event intman_sample_evnt_trig;

//----------CPU_FIFO------------------- 
reg         cpu_buf_rd_sel;
reg [4:0]   cpu_buf_waddr;
reg [4:0]   cpu_buf_raddr;
reg cpu_buf_wr;
reg cpu_buf_rd;

reg [15:0] cpu_buf_wr_b2b;
reg [15:0] cpu_buf_rd_b2b;
event cpu_buf_sample_evnt_trig;

//----------IO_FIFO------------------- 
reg         io_buf_rd_sel;
reg [4:0]   io_buf_waddr;
reg [4:0]   io_buf_raddr;
reg io_buf_wr;
reg io_buf_rd;

reg [15:0] io_buf_wr_b2b;
reg [15:0] io_buf_rd_b2b;
event io_buf_sample_evnt_trig;

//----------INT_FIFO------------------- 
reg         int_buf_rd_sel;
reg [4:0]   int_buf_waddr;
reg [4:0]   int_buf_raddr;
reg int_buf_wr;
reg int_buf_rd;

reg [15:0] int_buf_wr_b2b;
reg [15:0] int_buf_rd_b2b;
event int_buf_sample_evnt_trig;

//----------MONDO_DATA0_TBL ------------------- 
reg [5:0]   mondo_data0_tbl_waddr;
reg [5:0]   mondo_data1_tbl_waddr;
reg [5:0]   mondo_data_tbl_raddr;
reg mondo_data0_tbl_wr;
reg mondo_data1_tbl_wr;
reg mondo_data_tbl_rd;

reg [15:0] mondo_data0_tbl_wr_b2b;
reg [15:0] mondo_data1_tbl_wr_b2b;
reg [15:0] mondo_data_tbl_rd_b2b;
reg [15:0] mondo_data_tbl_rd_b2b_same_add;
event mondo_data_tbl_sample_evnt_trig;