Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / ncu / tcu_ncu_sample.vrhpal
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tcu_ncu_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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34// ========== Copyright Header End ============================================
35sample tcu_ncu_intf_add (tcu_ncu_add)
36{
37 state NCU_ADD ( 8'h80 );
38 state NIU_ADD ( 8'h81 );
39 state CCU_ADD ( 8'h83 );
40 state MCU_ADD ( 8'h84 );
41 state DBG1_ADD ( 8'h86 );
42 state DMU_ADD ( 8'h88 );
43 state RST_ADD ( 8'h89 );
44 state ASI_ADD ( 8'h90 );
45wildcard state PIO_ADD ( 8'Hcx );
46 state SSI_ADD ( 8'hff );
47
48}
49
50
51sample tcu_ncu_intf_type_sample (tcu_ncu_type)
52{
53 state READ_REQ ( 4'b0100 );
54 state WRITE_REQ ( 4'b0101 );
55}
56sample tcu_ncu_intf_type_ack (tcu_ncu_type)
57{
58 state READ_ACK ( 4'b0001 );
59}
60cross tcu_ncu_intf_add_type_cross (tcu_ncu_intf_add,tcu_ncu_intf_type_sample );
61
62
63sample tcu_ncu_intf_size (tcu_ncu_size)
64{
65 state SIZE1 (3'b000);
66 wildcard state SIZE2 (3'b0xx); // When tcu respons bask, size is ignored,
67 wildcard state SIZE4 (3'b0xx); //for avoid change the test plan, just modified to make it be wildcard
68 wildcard state SIZE8 (3'b0xx);
69}
70
71
72sample tcu_ncu_intf_bufid_sample (tcu_ncu_bufid)
73{
74 m_state BUFFID (0:1);
75}
76
77sample tcu_ncu_intf_cpuid_sample (tcu_ncu_cpuid)
78{
79 m_state CPU_ID ( 0:63 );
80}
81
82
83sample tcu_ncu_intf_type_trans (tcu_ncu_type)
84{
85
86 state READ_REQ ( 4'b0100 );
87 state WRITE_REQ ( 4'b0101 );
88 state IFILL_REQ ( 4'b0110 );
89
90
91 state READ_NACK ( 4'b0000 );
92 state READ_ACK ( 4'b0001 );
93
94
95 trans TYPE_TRAN00 ("READ_REQ" -> "READ_REQ");
96 trans TYPE_TRAN01 ("READ_REQ" -> "WRITE_REQ");
97 trans TYPE_TRAN02 ("READ_REQ" -> "IFILL_REQ");
98
99 trans TYPE_TRAN10 ("WRITE_REQ" -> "READ_REQ");
100 trans TYPE_TRAN11 ("WRITE_REQ" -> "WRITE_REQ");
101 trans TYPE_TRAN12 ("WRITE_REQ" -> "IFILL_REQ");
102
103 trans TYPE_TRAN20 ("IFILL_REQ" -> "READ_REQ");
104 trans TYPE_TRAN21 ("IFILL_REQ" -> "WRITE_REQ");
105 trans TYPE_TRAN22 ("IFILL_REQ" -> "IFILL_REQ");
106
107
108 trans TYPE_TRAN30 ("READ_ACK" -> "READ_ACK");
109 trans TYPE_TRAN31 ("READ_ACK" -> "READ_NACK");
110
111 trans TYPE_TRAN40 ("READ_NACK" -> "READ_ACK");
112 trans TYPE_TRAN41 ("READ_NACK" -> "READ_NACK");
113
114
115
116}
117
118
119
120
121
122sample tcu_ncu_intf_stall_b2b_sample (ncu_tcu_stall_b2b)
123{
124 m_state STALL ( 1:30 ) ;
125}
126sample tcu_ncu_intf_pkt_gap (tcu_ncu_pkt_gap)
127{
128 m_state PKT_GAP ( 1:10 ) ;
129}
130
131
132sample tcu_ncu_intf_b2b_sample (tcu_ncu_b2b)
133{
134 m_state B2B ( 2:5 ) ;
135}