projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: siu_coverage.vrpal | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #include <vera_defines.vrh> | |
| 36 | #include <ListMacros.vrh> | |
| 37 | #include "plusArgMacros.vri" | |
| 38 | #include "std_display_class.vrh" | |
| 39 | #include "std_display_defines.vri" | |
| 40 | #include "siu_defines.vrh" | |
| 41 | ||
| 42 | #include "siu_cov.if.vrh" | |
| 43 | //#include "siu_cov_ports_binds.vrh" | |
| 44 | //extern bit siu_RDDord_pass_niuord_diffbank; | |
| 45 | //extern bit siu_RDDord_not_pass_niuord_samebank; | |
| 46 | //extern bit siu_WRIord_not_pass_niuord; | |
| 47 | //extern bit siu_niubyp_pass_niubyp_diffbank; | |
| 48 | //extern bit siu_niubyp_not_pass_niubyp_samebank; | |
| 49 | //extern bit siu_niubyp_pass_niuord_diffbank; | |
| 50 | //extern bit siu_RDDbyp_pass_RDDord_samebank; | |
| 51 | //extern bit siu_WRIbyp_not_pass_niuord_samebank; | |
| 52 | ||
| 53 | //#ifndef SIU_INTF_COV | |
| 54 | #include "siu_order_checker.vrh" | |
| 55 | extern siu_order_checker order_chk; | |
| 56 | //#endif | |
| 57 | ||
| 58 | class siu_intf_coverage | |
| 59 | { | |
| 60 | // for dispmon | |
| 61 | StandardDisplay dbg; | |
| 62 | local string myname; | |
| 63 | ||
| 64 | event dmu_sample_evnt_trig; | |
| 65 | event dmu_be_sample_evnt_trig; | |
| 66 | event siu_dmu_wra_b2b_sample_evnt_trig; | |
| 67 | event dmu_siu_rdd_b2b_sample_evnt_trig; | |
| 68 | event dmu_siu_wri_b2b_sample_evnt_trig; | |
| 69 | event dmu_siu_wrm_b2b_sample_evnt_trig; | |
| 70 | event niu_sample_evnt_trig; | |
| 71 | event niu_b2b_sample_evnt_trig; | |
| 72 | event niu_b2b_wri_nonpost_sample_evnt_trig; | |
| 73 | event niu_b2b_wri_post_sample_evnt_trig; | |
| 74 | event l2_sample_evnt_trig; | |
| 75 | event sio_niu_sample_evnt_trig; | |
| 76 | event sio_niu_b2b_sample_evnt_trig; | |
| 77 | event sio_niu_b2b_wri_sample_evnt_trig; | |
| 78 | event sio_dmu_sample_evnt_trig; | |
| 79 | event siu_l2_vld_sample_evnt_trig; | |
| 80 | event siu_l2_iq_deq_sample_evnt_trig ; | |
| 81 | event siu_l2_wib_deq_sample_evnt_trig; | |
| 82 | event siu_l2_data_sio_sample_evnt_trig; | |
| 83 | event siu_l2_trans_sample_evnt_trig; | |
| 84 | event siu_fc_err_wri_sample_evnt_trig; | |
| 85 | event siu_fc_err_wr8_sample_evnt_trig; | |
| 86 | event siu_fc_err_rdd_sample_evnt_trig; | |
| 87 | event l2_ob_sample_evnt_trig; | |
| 88 | event niu_sw_evnt_trig; | |
| 89 | bit siu_intf_cov_debug = 1'b0; | |
| 90 | ||
| 91 | //----------DMU------------------- | |
| 92 | integer dmu_back_to_back; | |
| 93 | ||
| 94 | bit [5:0] dmu_cmd; | |
| 95 | bit dmubypass; | |
| 96 | bit dmudatareq; | |
| 97 | bit dmudatareq16; | |
| 98 | bit [127:0] dmudata; | |
| 99 | bit [15:0] dmc_tag; | |
| 100 | bit [3:0] last_dmu_wrack; | |
| 101 | ||
| 102 | bit [15:0] dmu_id_out; | |
| 103 | ||
| 104 | bit sio_dmu_req; | |
| 105 | bit [127:0] sio_dmu_data; | |
| 106 | integer sio_dmu_back_to_back; | |
| 107 | ||
| 108 | // concatinate {dmu_cmd,dmubypass} | |
| 109 | bit [6:0] this_dmu_cmd, last_dmu_cmd; | |
| 110 | bit last_dmu_cmd_valid = 1'b0; | |
| 111 | ||
| 112 | bit [5:0] sio_dmu_this_cmd, sio_dmu_last_cmd; | |
| 113 | bit sio_dmu_last_cmd_valid = 1'b0; | |
| 114 | bit [15:0] dmu_be; | |
| 115 | bit [3:0] dmuwracktag; | |
| 116 | bit sio_dmu_wra_back_to_back = 1'b0; | |
| 117 | bit last_siodmu_cmd_valid = 1'b0; | |
| 118 | bit siodmu_b2b_cnt; | |
| 119 | integer dmusiu_wra_b2b = 0; | |
| 120 | integer dmusiu_wra_b2b_state = 0; | |
| 121 | integer siudmu_wrack_b2b_cnt = 0; | |
| 122 | integer dmusiu_rdd_b2b_cnt = 0; | |
| 123 | integer dmusiu_wri_b2b_cnt = 0; | |
| 124 | integer dmusiu_wrm_b2b_cnt = 0; | |
| 125 | ||
| 126 | ||
| 127 | //----------NIU------------------- | |
| 128 | integer niu_back_to_back; | |
| 129 | integer niu_back_to_back1; | |
| 130 | ||
| 131 | bit [5:0] niu_cmd; | |
| 132 | bit niubypass; | |
| 133 | bit niudatareq; | |
| 134 | bit niudatareq16; | |
| 135 | bit [127:0] niudata; | |
| 136 | bit [15:0] niu_id; | |
| 137 | ||
| 138 | bit [15:0] niu_id_out; | |
| 139 | ||
| 140 | bit sio_niu_req; | |
| 141 | bit [127:0] sio_niu_data; | |
| 142 | integer sio_niu_back_to_back; | |
| 143 | integer sio_niu_dmu_back_to_back = 100; | |
| 144 | integer niu_dmu_back_to_back = 100; | |
| 145 | ||
| 146 | // concatinate {niu_cmd,niubypass} | |
| 147 | bit [6:0] this_niu_cmd, last_niu_cmd; | |
| 148 | bit [6:0] this_niusiu_b2b_cnt, last_niusiu_b2b_cnt; | |
| 149 | bit last_niu_cmd_valid = 1'b0; | |
| 150 | ||
| 151 | bit [5:0] sio_niu_this_cmd, sio_niu_last_cmd; | |
| 152 | bit [5:0] sio_niu_last1_cmd; | |
| 153 | bit sio_niu_last_cmd_valid = 1'b0; | |
| 154 | bit niusiu_b2b_cnt; | |
| 155 | integer niusiu_b2b1_cnt; | |
| 156 | integer niusiu_b2b_wri_nonpost_cnt; | |
| 157 | integer niusiu_b2b_wri_post_cnt; | |
| 158 | bit niusiu_b2b_trans; | |
| 159 | bit siuniu_b2b_cnt; | |
| 160 | integer siuniu_b2b1_cnt; | |
| 161 | integer siuniu_b2b_wri_cnt; | |
| 162 | bit siuniu_b2b_trans; | |
| 163 | integer niusiu_b2b = 0; | |
| 164 | integer niusiu_b2b_state = 0; | |
| 165 | integer sioniu_b2b = 0; | |
| 166 | integer sioniu_b2b_state = 0; | |
| 167 | ||
| 168 | //----------L2------------------- | |
| 169 | integer counter_vld, counter0_vld, counter1_vld, counter2_vld; | |
| 170 | integer counter3_vld, counter4_vld, counter5_vld, counter6_vld, counter7_vld; | |
| 171 | bit l2t0, l2t1, l2t2, l2t3; | |
| 172 | bit l2t4, l2t5, l2t6, l2t7; | |
| 173 | bit last_siu_l2_cmd_valid = 1'b0; | |
| 174 | bit [2:0] siu_l2_wib_deq_this_cmd, siu_l2_wib_deq_last_cmd; | |
| 175 | integer counter_iq, counter0_iq, counter1_iq, counter2_iq; | |
| 176 | integer counter3_iq, counter4_iq, counter5_iq, counter6_iq, counter7_iq; | |
| 177 | bit l2t0_iq_deq, l2t1_iq_deq, l2t2_iq_deq, l2t3_iq_deq; | |
| 178 | bit l2t4_iq_deq, l2t5_iq_deq, l2t6_iq_deq, l2t7_iq_deq; | |
| 179 | integer counter_wib, counter0_wib, counter1_wib, counter2_wib; | |
| 180 | integer counter3_wib, counter4_wib, counter5_wib, counter6_wib, counter7_wib; | |
| 181 | bit l2t0_wib_deq, l2t1_wib_deq, l2t2_wib_deq, l2t3_wib_deq; | |
| 182 | bit l2t4_wib_deq, l2t5_wib_deq, l2t6_wib_deq, l2t7_wib_deq; | |
| 183 | integer counter_data, counter0_data, counter1_data, counter2_data; | |
| 184 | integer counter3_data, counter4_data, counter5_data, counter6_data, counter7_data; | |
| 185 | bit l2t0_data_sio, l2t1_data_sio, l2t2_data_sio, l2t3_data_sio; | |
| 186 | bit l2t4_data_sio, l2t5_data_sio, l2t6_data_sio, l2t7_data_sio; | |
| 187 | bit [31:0] l2t0_data, l2t1_data, l2t2_data, l2t3_data; | |
| 188 | bit [31:0] l2t4_data, l2t5_data, l2t6_data, l2t7_data; | |
| 189 | bit last_siu_l2_data_sio_cmd_valid = 1'b0; | |
| 190 | bit sii_l2t0_trans, sii_l2t1_trans, sii_l2t2_trans, sii_l2t3_trans; | |
| 191 | bit sii_l2t4_trans, sii_l2t5_trans, sii_l2t6_trans, sii_l2t7_trans; | |
| 192 | ||
| 193 | . for ($bank=0; $bank<8; $bank++) | |
| 194 | . { | |
| 195 | bit l2t${bank}_iq_dq; | |
| 196 | bit l2t${bank}_wib_dq; | |
| 197 | bit sii_l2t${bank}; | |
| 198 | bit [31:0] sii_l2t${bank}_data; | |
| 199 | bit [5:0] this_l2${bank}_cmd, last_l2${bank}_cmd; | |
| 200 | bit last_l2${bank}_cmd_valid = 1'b0; | |
| 201 | bit l2${bank}_back_to_back = 1'b0; | |
| 202 | ||
| 203 | bit l2b${bank}_sio_ctag_vld; | |
| 204 | bit [6:0] this_l2${bank}_ob_cmd, last_l2${bank}_ob_cmd; | |
| 205 | bit last_l2${bank}_ob_cmd_valid = 1'b0; | |
| 206 | bit l2${bank}_ob_back_to_back = 1'b0; | |
| 207 | bit [31:0] l2b${bank}_sio_data; | |
| 208 | . } | |
| 209 | ||
| 210 | bit [7:0] switch_banks; | |
| 211 | bit bank0, bank1, bank2, bank3, bank4, bank5, bank6, bank7; | |
| 212 | ||
| 213 | bit [5:0] this_l2_cmd; | |
| 214 | ||
| 215 | integer siu_l2_back_to_back; | |
| 216 | ||
| 217 | ||
| 218 | // ----------- coverage_group ---------------- | |
| 219 | coverage_group siu_intf_coverage_group | |
| 220 | { | |
| 221 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 222 | sample_event = sync (ANY, l2_sample_evnt_trig, l2_ob_sample_evnt_trig); | |
| 223 | ||
| 224 | #include "siu_l2intf_cmd_sample.vrh" | |
| 225 | #include "siu_l2intf_ob_cmd_sample.vrh" | |
| 226 | ||
| 227 | } // siu_intf_coverage_group | |
| 228 | ||
| 229 | ||
| 230 | // ----------- coverage_group ---------------- | |
| 231 | ||
| 232 | coverage_group siu_niu_intf_coverage_group | |
| 233 | { | |
| 234 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 235 | sample_event = sync (ANY, niu_sample_evnt_trig ,niu_b2b_sample_evnt_trig ,niu_b2b_wri_nonpost_sample_evnt_trig, niu_b2b_wri_post_sample_evnt_trig); | |
| 236 | ||
| 237 | #include "siu_niucmd_sample.vrh" | |
| 238 | #include "siu_niucmd_intf_sample.vrh" | |
| 239 | #include "siu_niu_dmu_cmd_sample.vrh" | |
| 240 | ||
| 241 | } // siu_niu_intf_coverage_group | |
| 242 | ||
| 243 | ||
| 244 | // ----------- coverage_group ---------------- | |
| 245 | ||
| 246 | coverage_group siu_niu_out_intf_coverage_group | |
| 247 | { | |
| 248 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 249 | sample_event = sync (ANY, sio_niu_sample_evnt_trig, sio_niu_b2b_sample_evnt_trig, sio_niu_b2b_wri_sample_evnt_trig ); | |
| 250 | ||
| 251 | #include "siu_niu_out_sample.vrh" | |
| 252 | #include "siu_niu_out_intf_sample.vrh" | |
| 253 | #include "siu_niu_dmu_out_sample.vrh" | |
| 254 | ||
| 255 | } // siu_niu_out_intf_coverage_group | |
| 256 | ||
| 257 | ||
| 258 | ||
| 259 | // ----------- coverage_group ---------------- | |
| 260 | ||
| 261 | coverage_group siu_dmu_intf_coverage_group | |
| 262 | { | |
| 263 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 264 | sample_event = sync (ANY, dmu_sample_evnt_trig ); | |
| 265 | ||
| 266 | #include "siu_dmucmd_sample.vrh" | |
| 267 | ||
| 268 | } // siu_dmu_intf_coverage_group | |
| 269 | ||
| 270 | coverage_group siu_dmu_intf_be_coverage_group | |
| 271 | { | |
| 272 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 273 | sample_event = sync (ANY, dmu_be_sample_evnt_trig ); | |
| 274 | ||
| 275 | #include "siu_dmu_intf_be_sample.vrh" | |
| 276 | ||
| 277 | } | |
| 278 | ||
| 279 | ||
| 280 | ||
| 281 | // ----------- coverage_group ---------------- | |
| 282 | ||
| 283 | coverage_group siu_dmu_out_intf_coverage_group | |
| 284 | { | |
| 285 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 286 | sample_event = sync (ANY, sio_dmu_sample_evnt_trig ); | |
| 287 | ||
| 288 | #include "siu_dmu_out_sample.vrh" | |
| 289 | ||
| 290 | } // siu_dmu_out_intf_coverage_group | |
| 291 | ||
| 292 | ||
| 293 | coverage_group siu_dmu_out_intf_wra_coverage_group | |
| 294 | { | |
| 295 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 296 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 297 | ||
| 298 | #include "siu_dmu_out_wra_sample.vrh" | |
| 299 | } // siu_dmu_out_intf_wra_coverage_group | |
| 300 | ||
| 301 | coverage_group siu_dmu_out_intf_wra_b2b_coverage_group | |
| 302 | { | |
| 303 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 304 | sample_event = sync (ANY, siu_dmu_wra_b2b_sample_evnt_trig ); | |
| 305 | ||
| 306 | #include "siu_dmu_out_wra_b2b_sample.vrh" | |
| 307 | } // siu_dmu_out_intf_wra_coverage_group | |
| 308 | ||
| 309 | coverage_group dmu_siu_out_intf_hdr_b2b_coverage_group | |
| 310 | { | |
| 311 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 312 | sample_event = sync (ANY, dmu_siu_rdd_b2b_sample_evnt_trig, dmu_siu_wri_b2b_sample_evnt_trig, dmu_siu_wrm_b2b_sample_evnt_trig ); | |
| 313 | ||
| 314 | #include "dmu_siu_intf_hdr_b2b_sample.vrh" | |
| 315 | } // dmu_siu_out_intf_hdr_coverage_group | |
| 316 | ||
| 317 | ||
| 318 | ||
| 319 | // ----------- coverage_group ---------------- | |
| 320 | coverage_group siu_l2_intf_vld_coverage_group | |
| 321 | { | |
| 322 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 323 | sample_event = sync (ANY, siu_l2_vld_sample_evnt_trig ); | |
| 324 | ||
| 325 | #include "siu_l2_intf_vld_sample.vrh" | |
| 326 | ||
| 327 | } | |
| 328 | ||
| 329 | // ----------- coverage_group ---------------- | |
| 330 | coverage_group siu_l2_intf_iq_deq_coverage_group | |
| 331 | { | |
| 332 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 333 | sample_event = sync (ANY, siu_l2_iq_deq_sample_evnt_trig ); | |
| 334 | ||
| 335 | #include "siu_l2_intf_iq_deq_sample.vrh" | |
| 336 | ||
| 337 | } | |
| 338 | ||
| 339 | // ----------- coverage_group ---------------- | |
| 340 | coverage_group siu_l2_intf_wib_deq_coverage_group | |
| 341 | { | |
| 342 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 343 | sample_event = sync (ANY, siu_l2_wib_deq_sample_evnt_trig ); | |
| 344 | ||
| 345 | #include "siu_l2_intf_wib_deq_sample.vrh" | |
| 346 | ||
| 347 | } | |
| 348 | ||
| 349 | // ----------- coverage_group ---------------- | |
| 350 | coverage_group siu_l2_intf_data_sio_coverage_group | |
| 351 | { | |
| 352 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 353 | sample_event = sync (ANY, siu_l2_data_sio_sample_evnt_trig ); | |
| 354 | ||
| 355 | #include "siu_l2_intf_data_sio_sample.vrh" | |
| 356 | ||
| 357 | } | |
| 358 | ||
| 359 | ||
| 360 | // ----------- coverage_group ---------------- | |
| 361 | coverage_group siu_l2_intf_trans_coverage_group | |
| 362 | { | |
| 363 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 364 | sample_event = sync (ANY, siu_l2_trans_sample_evnt_trig ); | |
| 365 | ||
| 366 | #include "siu_l2_intf_trans_sample.vrh" | |
| 367 | ||
| 368 | } | |
| 369 | ||
| 370 | // ----------- coverage_group ---------------- | |
| 371 | coverage_group siu_fc_error_wri_coverage_group | |
| 372 | { | |
| 373 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 374 | sample_event = sync (ANY, siu_fc_err_wri_sample_evnt_trig ); | |
| 375 | ||
| 376 | #include "siu_fc_err_wri_sample.vrh" | |
| 377 | ||
| 378 | } | |
| 379 | ||
| 380 | // ----------- coverage_group ---------------- | |
| 381 | coverage_group siu_fc_error_wr8_coverage_group | |
| 382 | { | |
| 383 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 384 | sample_event = sync (ANY, siu_fc_err_wr8_sample_evnt_trig ); | |
| 385 | ||
| 386 | #include "siu_fc_err_wr8_sample.vrh" | |
| 387 | ||
| 388 | } | |
| 389 | ||
| 390 | // ----------- coverage_group ---------------- | |
| 391 | coverage_group siu_fc_error_rdd_coverage_group | |
| 392 | { | |
| 393 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 394 | sample_event = sync (ANY, siu_fc_err_rdd_sample_evnt_trig ); | |
| 395 | ||
| 396 | #include "siu_fc_err_rdd_sample.vrh" | |
| 397 | ||
| 398 | } | |
| 399 | ||
| 400 | // ----------- coverage_group ---------------- | |
| 401 | coverage_group siu_l2intf_switchbanks_coverage_group | |
| 402 | { | |
| 403 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 404 | sample_event = wait_var (switch_banks); | |
| 405 | ||
| 406 | #include "siu_l2intf_switchbanks_sample.vrh" | |
| 407 | } | |
| 408 | ||
| 409 | #ifndef IOS_COVERAGE | |
| 410 | ////// SII-TCU ////// | |
| 411 | coverage_group siu_tcu_rdwr_coverage_group | |
| 412 | { | |
| 413 | const_sample_reference = 1; | |
| 414 | sample_event = @(posedge siu_coverage_tcu_pkt.clk); | |
| 415 | sample siu_coverage_tcu_pkt.jtag_cov | |
| 416 | { | |
| 417 | state s_TCU_RD (1) if (siu_coverage_tcu_pkt.tcurdwr === 3'b001); | |
| 418 | state s_TCU_WR (1) if (siu_coverage_tcu_pkt.tcurdwr === 3'b010); | |
| 419 | } | |
| 420 | } | |
| 421 | coverage_group siu_tcu_niu_dmu_coverage_group | |
| 422 | { | |
| 423 | sample_event = @(posedge siu_coverage_tcu_pkt.tcureq or | |
| 424 | posedge siu_coverage_ifc.dmureq or | |
| 425 | posedge siu_coverage_ifc.niureq); | |
| 426 | sample siu_coverage_tcu_pkt.tcureq | |
| 427 | { | |
| 428 | state s_TCU_NIU_DMU (1) if (siu_coverage_ifc.dmureq === 1 && | |
| 429 | siu_coverage_tcu_pkt.tcureq === 1 && | |
| 430 | siu_coverage_ifc.niureq === 1); | |
| 431 | } | |
| 432 | } | |
| 433 | #endif | |
| 434 | ||
| 435 | task new(StandardDisplay dbg); | |
| 436 | task set_cov_cond_bits (); | |
| 437 | ||
| 438 | } //class siu_intf_coverage | |
| 439 | ||
| 440 | ||
| 441 | ///////////////////////////////////////////////////////////////// | |
| 442 | // Class creation | |
| 443 | ///////////////////////////////////////////////////////////////// | |
| 444 | task siu_intf_coverage::new(StandardDisplay dbg) | |
| 445 | { | |
| 446 | bit coverage_on; | |
| 447 | integer j; | |
| 448 | ||
| 449 | // for dispmon | |
| 450 | myname = "siu_intf_coverage"; | |
| 451 | this.dbg = dbg; | |
| 452 | ||
| 453 | if (mChkPlusarg(siu_intf_coverage) || mChkPlusarg(coverage_on)) { | |
| 454 | coverage_on = 1; | |
| 455 | if (mChkPlusarg(siu_intf_cov_debug)) { | |
| 456 | siu_intf_cov_debug = 1'b1; | |
| 457 | } | |
| 458 | } else { | |
| 459 | coverage_on = 0; | |
| 460 | } | |
| 461 | ||
| 462 | if (coverage_on) { | |
| 463 | siu_intf_coverage_group = new(); | |
| 464 | siu_l2intf_switchbanks_coverage_group = new(); | |
| 465 | siu_niu_intf_coverage_group = new(); | |
| 466 | siu_niu_out_intf_coverage_group = new(); | |
| 467 | siu_dmu_intf_coverage_group = new(); | |
| 468 | siu_dmu_intf_be_coverage_group = new(); | |
| 469 | siu_dmu_out_intf_coverage_group = new(); | |
| 470 | siu_l2_intf_vld_coverage_group = new(); | |
| 471 | #ifndef IOS_COVERAGE | |
| 472 | siu_tcu_rdwr_coverage_group = new(); | |
| 473 | #endif | |
| 474 | ||
| 475 | set_cov_cond_bits (); | |
| 476 | ||
| 477 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage turned on for SIU objects\n\n", get_time(LO))); | |
| 478 | ||
| 479 | fork { | |
| 480 | @ (posedge siu_coverage_ifc.cmp_diag_done); | |
| 481 | siu_intf_coverage_group.set_cov_weight(1); | |
| 482 | coverage_save_database(1); | |
| 483 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage for SIU objects generated\n\n", get_time(LO))); | |
| 484 | } join none | |
| 485 | } // if coverage_on | |
| 486 | } // siu_intf_coverage::new() | |
| 487 | ||
| 488 | ||
| 489 | /////////////////////////////////////////////////////////////////////////// | |
| 490 | // This task is a psuedo coverage object that combines a few conditions | |
| 491 | // so that the actual coverage objects' state space doesn't get too big | |
| 492 | ////////////////////////////////////////////////////////////////////////// | |
| 493 | ||
| 494 | task siu_intf_coverage:: set_cov_cond_bits () | |
| 495 | { | |
| 496 | bit any_sii_req; | |
| 497 | bit l20_req, l21_req, l22_req, l23_req, l24_req, l25_req, l26_req, l27_req; | |
| 498 | ||
| 499 | ||
| 500 | . for ($bank=0; $bank<8; $bank++) | |
| 501 | . { | |
| 502 | integer this_l2${bank}_cycle; | |
| 503 | integer last_l2${bank}_cycle; | |
| 504 | ||
| 505 | integer this_l2${bank}_ob_cycle; | |
| 506 | integer last_l2${bank}_ob_cycle; | |
| 507 | . } | |
| 508 | ||
| 509 | //------------------- DMU_INTERFACE and NIU_INTERFACE -------------------------- | |
| 510 | bit dmureq, niureq; | |
| 511 | integer dmu_this_cmd_cycle, dmu_last_cmd_cycle, niu_this_cmd_cycle, niu_last_cmd_cycle; | |
| 512 | ||
| 513 | integer sio_niu_last_cmd_cycle, sio_niu_this_cmd_cycle; | |
| 514 | ||
| 515 | integer sio_dmu_last_cmd_cycle, sio_dmu_this_cmd_cycle; | |
| 516 | ||
| 517 | dmu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 518 | niu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 519 | ||
| 520 | sio_niu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 521 | ||
| 522 | sio_dmu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 523 | ||
| 524 | ||
| 525 | //L2 | |
| 526 | . for ($bank=0; $bank<8; $bank++) | |
| 527 | . { | |
| 528 | this_l2${bank}_cycle = get_cycle(siu_coverage_ifc_l2.clk); | |
| 529 | this_l2${bank}_ob_cycle = get_cycle(siu_coverage_ifc_l2.clk); | |
| 530 | . } | |
| 531 | ||
| 532 | niusiu_b2b_cnt = 0; | |
| 533 | niusiu_b2b_trans = 0; | |
| 534 | siuniu_b2b_cnt = 0; | |
| 535 | siuniu_b2b_trans = 0; | |
| 536 | ||
| 537 | ||
| 538 | fork | |
| 539 | { | |
| 540 | ||
| 541 | integer dmusiu_wra_last_cycle = 0; | |
| 542 | integer dmusiu_wra_start_cycle = 0; | |
| 543 | integer dmusiu_wra_value = 0; | |
| 544 | integer niusiu_last_cycle = 0; | |
| 545 | integer niusiu_start_cycle = 0; | |
| 546 | integer niusiu_value = 0; | |
| 547 | integer sioniu_last_cycle = 0; | |
| 548 | integer sioniu_start_cycle = 0; | |
| 549 | integer sioniu_value = 0; | |
| 550 | integer dmusiu_dmareq_cycle = 5; | |
| 551 | ||
| 552 | while (1) | |
| 553 | { | |
| 554 | integer dmusiu_wra_this_cycle = 0; | |
| 555 | integer niusiu_this_cycle = 0; | |
| 556 | integer sioniu_this_cycle = 0; | |
| 557 | @ (posedge siu_coverage_ifc.clk); | |
| 558 | ||
| 559 | ||
| 560 | ||
| 561 | //---------------DMU-SII--------------------- | |
| 562 | if( siu_coverage_ifc.dmureq ) | |
| 563 | { | |
| 564 | ||
| 565 | dmubypass = siu_coverage_ifc.dmubypass; | |
| 566 | dmudata = siu_coverage_ifc.dmudata; | |
| 567 | ||
| 568 | dmu_last_cmd_cycle = dmu_this_cmd_cycle; | |
| 569 | dmu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 570 | ||
| 571 | dmu_back_to_back = dmu_this_cmd_cycle - dmu_last_cmd_cycle; | |
| 572 | ||
| 573 | dmu_cmd = dmudata[127:122]; | |
| 574 | dmc_tag = dmudata[79:64]; | |
| 575 | ||
| 576 | last_dmu_cmd = this_dmu_cmd; | |
| 577 | this_dmu_cmd = {dmu_cmd,dmubypass}; | |
| 578 | ||
| 579 | if(last_dmu_cmd_valid) { | |
| 580 | // only sample when both "last_dmu_cmd" and "this_dmu_cmd" | |
| 581 | // contain valid data, so the first command is never sampled | |
| 582 | trigger (dmu_sample_evnt_trig); | |
| 583 | } | |
| 584 | else | |
| 585 | { | |
| 586 | last_dmu_cmd_valid = 1'b1; | |
| 587 | } | |
| 588 | dmusiu_dmareq_cycle = 0; | |
| 589 | } //siu_coverage_ifc.dmureq | |
| 590 | ||
| 591 | // dmube bits are only valid in the 4 cycles after dmareq is assertted. | |
| 592 | if ( (dmusiu_dmareq_cycle>0) && (dmusiu_dmareq_cycle<5) ) | |
| 593 | { | |
| 594 | dmu_be = siu_coverage_ifc.dmube; | |
| 595 | trigger (dmu_be_sample_evnt_trig); | |
| 596 | } | |
| 597 | dmusiu_dmareq_cycle++; | |
| 598 | ||
| 599 | } // while (1) | |
| 600 | } // fork | |
| 601 | join none | |
| 602 | ||
| 603 | ||
| 604 | fork | |
| 605 | { | |
| 606 | while(1) | |
| 607 | { | |
| 608 | @(posedge siu_coverage_ifc.clk); | |
| 609 | if (siudmu_wrack_b2b_cnt === 'd4) | |
| 610 | { | |
| 611 | ||
| 612 | if (siu_coverage_ifc.dmuwrack_vld === 1'b1) | |
| 613 | siudmu_wrack_b2b_cnt = 1; | |
| 614 | else | |
| 615 | siudmu_wrack_b2b_cnt = 0; | |
| 616 | } | |
| 617 | else if (siu_coverage_ifc.dmuwrack_vld === 1'b1) | |
| 618 | { | |
| 619 | trigger (siu_dmu_wra_b2b_sample_evnt_trig); | |
| 620 | repeat (8) @(posedge siu_coverage_ifc.clk); | |
| 621 | siudmu_wrack_b2b_cnt = siudmu_wrack_b2b_cnt + 1; | |
| 622 | } | |
| 623 | else | |
| 624 | siudmu_wrack_b2b_cnt = 0; | |
| 625 | } // while (1) | |
| 626 | } // fork | |
| 627 | join none | |
| 628 | ||
| 629 | ||
| 630 | ||
| 631 | fork | |
| 632 | { | |
| 633 | while(1) | |
| 634 | { | |
| 635 | @(posedge siu_coverage_ifc.clk); | |
| 636 | if (dmusiu_rdd_b2b_cnt === 'd200) | |
| 637 | { | |
| 638 | ||
| 639 | if (siu_coverage_ifc.dmureq === 1'b1 && siu_coverage_ifc.dmudata[125] === 1'b1) | |
| 640 | dmusiu_rdd_b2b_cnt = 1; | |
| 641 | else | |
| 642 | dmusiu_rdd_b2b_cnt = 0; | |
| 643 | } | |
| 644 | else if (siu_coverage_ifc.dmureq === 1'b1 && siu_coverage_ifc.dmudata[125] === 1'b1) | |
| 645 | { | |
| 646 | dmusiu_rdd_b2b_cnt = dmusiu_rdd_b2b_cnt + 1; | |
| 647 | if (dmusiu_rdd_b2b_cnt === 'd200) | |
| 648 | trigger (dmu_siu_rdd_b2b_sample_evnt_trig); | |
| 649 | } | |
| 650 | else | |
| 651 | dmusiu_rdd_b2b_cnt = 0; | |
| 652 | } // while (1) | |
| 653 | } // fork | |
| 654 | join none | |
| 655 | ||
| 656 | ||
| 657 | fork | |
| 658 | { | |
| 659 | while(1) | |
| 660 | { | |
| 661 | @(posedge siu_coverage_ifc.clk); | |
| 662 | if (dmusiu_wri_b2b_cnt === 'd40) | |
| 663 | { | |
| 664 | ||
| 665 | if (siu_coverage_ifc.dmureq === 1'b1 && siu_coverage_ifc.dmudata[126] === 1'b1 && siu_coverage_ifc.dmudata[124] === 1'b0) | |
| 666 | dmusiu_wri_b2b_cnt = 1; | |
| 667 | else | |
| 668 | dmusiu_wri_b2b_cnt = 0; | |
| 669 | } | |
| 670 | else if (siu_coverage_ifc.dmureq === 1'b1 && siu_coverage_ifc.dmudata[126] === 1'b0 && siu_coverage_ifc.dmudata[124] === 1'b0) | |
| 671 | { | |
| 672 | dmusiu_wri_b2b_cnt = dmusiu_wri_b2b_cnt + 1; | |
| 673 | if (dmusiu_wri_b2b_cnt === 'd40) | |
| 674 | trigger (dmu_siu_wri_b2b_sample_evnt_trig); | |
| 675 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 676 | } | |
| 677 | else | |
| 678 | dmusiu_wri_b2b_cnt = 0; | |
| 679 | } // while (1) | |
| 680 | } // fork | |
| 681 | join none | |
| 682 | ||
| 683 | fork | |
| 684 | { | |
| 685 | while(1) | |
| 686 | { | |
| 687 | @(posedge siu_coverage_ifc.clk); | |
| 688 | if (dmusiu_wrm_b2b_cnt === 'd40) | |
| 689 | { | |
| 690 | ||
| 691 | if (siu_coverage_ifc.dmureq === 1'b1 && siu_coverage_ifc.dmudata[126] === 1'b1 && siu_coverage_ifc.dmudata[124] === 1'b1) | |
| 692 | dmusiu_wrm_b2b_cnt = 1; | |
| 693 | else | |
| 694 | dmusiu_wrm_b2b_cnt = 0; | |
| 695 | } | |
| 696 | else if (siu_coverage_ifc.dmureq === 1'b1 && siu_coverage_ifc.dmudata[126] === 1'b0 && siu_coverage_ifc.dmudata[124] === 1'b1) | |
| 697 | { | |
| 698 | dmusiu_wrm_b2b_cnt = dmusiu_wrm_b2b_cnt + 1; | |
| 699 | if (dmusiu_wrm_b2b_cnt === 'd40) | |
| 700 | trigger (dmu_siu_wri_b2b_sample_evnt_trig); | |
| 701 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 702 | } | |
| 703 | else | |
| 704 | dmusiu_wrm_b2b_cnt = 0; | |
| 705 | } // while (1) | |
| 706 | } // fork | |
| 707 | join none | |
| 708 | ||
| 709 | ||
| 710 | ||
| 711 | /************** SIO-DMU *****************/ | |
| 712 | fork | |
| 713 | { | |
| 714 | while(1) | |
| 715 | { | |
| 716 | @ (posedge siu_coverage_ifc.clk); | |
| 717 | if( siu_coverage_ifc.sio_dmu_req ) | |
| 718 | { | |
| 719 | sio_dmu_data = siu_coverage_ifc.sio_dmu_data; | |
| 720 | ||
| 721 | dmu_id_out = sio_dmu_data[79:64]; | |
| 722 | ||
| 723 | sio_dmu_last_cmd_cycle = sio_dmu_this_cmd_cycle; | |
| 724 | sio_dmu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 725 | ||
| 726 | sio_dmu_back_to_back = sio_dmu_this_cmd_cycle - sio_dmu_last_cmd_cycle; | |
| 727 | ||
| 728 | sio_dmu_last_cmd = sio_dmu_this_cmd; | |
| 729 | sio_dmu_this_cmd = sio_dmu_data[127:122]; | |
| 730 | ||
| 731 | if(sio_dmu_last_cmd_valid) { | |
| 732 | // only sample when both "last_dmu_cmd" and "this_dmu_cmd" | |
| 733 | // contain valid data, so the first command is never sampled | |
| 734 | trigger (sio_dmu_sample_evnt_trig); | |
| 735 | } | |
| 736 | else | |
| 737 | { | |
| 738 | sio_dmu_last_cmd_valid = 1'b1; | |
| 739 | } | |
| 740 | } // siu_coverage_ifc.sio_dmu_req | |
| 741 | } // while (1) | |
| 742 | } // fork | |
| 743 | join none | |
| 744 | ||
| 745 | ||
| 746 | ||
| 747 | ||
| 748 | //---------------------NIU-SII----------------------------------- | |
| 749 | fork | |
| 750 | { | |
| 751 | while(1) | |
| 752 | { | |
| 753 | @ (posedge siu_coverage_ifc.clk); | |
| 754 | if( siu_coverage_ifc.niureq ) { | |
| 755 | // sample other interface signals | |
| 756 | niubypass = siu_coverage_ifc.niubypass; | |
| 757 | niudatareq = siu_coverage_ifc.niudatareq; | |
| 758 | niudatareq16 = siu_coverage_ifc.niudatareq16; | |
| 759 | niudata = siu_coverage_ifc.niudata; | |
| 760 | ||
| 761 | niu_last_cmd_cycle = niu_this_cmd_cycle; | |
| 762 | niu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 763 | ||
| 764 | niu_back_to_back = niu_this_cmd_cycle - niu_last_cmd_cycle; | |
| 765 | ||
| 766 | niu_cmd = niudata[127:122]; | |
| 767 | niu_id = niudata[79:64]; | |
| 768 | niusiu_b2b_cnt++; | |
| 769 | niusiu_b2b_trans++; | |
| 770 | ||
| 771 | last_niu_cmd = this_niu_cmd; | |
| 772 | this_niu_cmd = {niu_cmd,niubypass}; | |
| 773 | ||
| 774 | if(last_niu_cmd_valid) { | |
| 775 | // only sample when both "last_niu_cmd" and "this_niu_cmd" | |
| 776 | // contain valid data, so the first command is never sampled | |
| 777 | trigger (niu_sample_evnt_trig); | |
| 778 | } | |
| 779 | else | |
| 780 | { | |
| 781 | last_niu_cmd_valid = 1'b1; | |
| 782 | niusiu_b2b_cnt = 0; | |
| 783 | } | |
| 784 | ||
| 785 | // for niu-dmu | |
| 786 | niu_dmu_back_to_back = niu_this_cmd_cycle - dmu_this_cmd_cycle; | |
| 787 | ||
| 788 | } //siu_coverage_ifc.niureq | |
| 789 | } // while (1) | |
| 790 | } // fork | |
| 791 | join none | |
| 792 | ||
| 793 | ||
| 794 | ||
| 795 | fork | |
| 796 | { | |
| 797 | while(1) | |
| 798 | { | |
| 799 | @(posedge siu_coverage_ifc.clk); | |
| 800 | if (niusiu_b2b1_cnt === 'd200) | |
| 801 | { | |
| 802 | ||
| 803 | if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b1) | |
| 804 | niusiu_b2b1_cnt = 1; | |
| 805 | else | |
| 806 | niusiu_b2b1_cnt = 0; | |
| 807 | } | |
| 808 | else if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b1) | |
| 809 | { | |
| 810 | niusiu_b2b1_cnt = niusiu_b2b1_cnt + 1; | |
| 811 | if (niusiu_b2b1_cnt === 'd200) | |
| 812 | trigger (niu_b2b_sample_evnt_trig); | |
| 813 | } | |
| 814 | else | |
| 815 | niusiu_b2b1_cnt = 0; | |
| 816 | } // while (1) | |
| 817 | } // fork | |
| 818 | join none | |
| 819 | ||
| 820 | fork | |
| 821 | { | |
| 822 | while(1) | |
| 823 | { | |
| 824 | @(posedge siu_coverage_ifc.clk); | |
| 825 | if (niusiu_b2b_wri_nonpost_cnt === 'd40) | |
| 826 | { | |
| 827 | ||
| 828 | if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b0 && siu_coverage_ifc.niudata[125] === 1'b0) | |
| 829 | niusiu_b2b_wri_nonpost_cnt = 1; | |
| 830 | else | |
| 831 | niusiu_b2b_wri_nonpost_cnt = 0; | |
| 832 | } | |
| 833 | else if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b0 && siu_coverage_ifc.niudata[125] === 1'b0) | |
| 834 | { | |
| 835 | niusiu_b2b_wri_nonpost_cnt = niusiu_b2b_wri_nonpost_cnt + 1; | |
| 836 | if (niusiu_b2b_wri_nonpost_cnt === 'd40) | |
| 837 | trigger (niu_b2b_wri_nonpost_sample_evnt_trig); | |
| 838 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 839 | } | |
| 840 | else | |
| 841 | niusiu_b2b_wri_nonpost_cnt = 0; | |
| 842 | } // while (1) | |
| 843 | } // fork | |
| 844 | join none | |
| 845 | ||
| 846 | fork | |
| 847 | { | |
| 848 | while(1) | |
| 849 | { | |
| 850 | @(posedge siu_coverage_ifc.clk); | |
| 851 | if (niusiu_b2b_wri_post_cnt === 'd40) | |
| 852 | { | |
| 853 | ||
| 854 | if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b0) | |
| 855 | niusiu_b2b_wri_post_cnt = 1; | |
| 856 | else | |
| 857 | niusiu_b2b_wri_post_cnt = 0; | |
| 858 | } | |
| 859 | else if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b0) | |
| 860 | { | |
| 861 | niusiu_b2b_wri_post_cnt = niusiu_b2b_wri_post_cnt + 1; | |
| 862 | if (niusiu_b2b_wri_post_cnt === 'd40) | |
| 863 | trigger (niu_b2b_wri_post_sample_evnt_trig); | |
| 864 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 865 | } | |
| 866 | else | |
| 867 | niusiu_b2b_wri_post_cnt = 0; | |
| 868 | } // while (1) | |
| 869 | } // fork | |
| 870 | join none | |
| 871 | ||
| 872 | ||
| 873 | /************** SIO-NIU *****************/ | |
| 874 | fork | |
| 875 | { | |
| 876 | while(1) | |
| 877 | { | |
| 878 | @ (posedge siu_coverage_ifc.clk); | |
| 879 | if( siu_coverage_ifc.sio_niu_req ) | |
| 880 | { | |
| 881 | sio_niu_data = siu_coverage_ifc.sio_niu_data; | |
| 882 | ||
| 883 | niu_id_out = sio_niu_data[79:64]; | |
| 884 | ||
| 885 | sio_niu_last_cmd_cycle = sio_niu_this_cmd_cycle; | |
| 886 | sio_niu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 887 | ||
| 888 | sio_niu_back_to_back = sio_niu_this_cmd_cycle - sio_niu_last_cmd_cycle; | |
| 889 | ||
| 890 | sio_niu_last_cmd = sio_niu_this_cmd; | |
| 891 | sio_niu_this_cmd = sio_niu_data[127:122]; | |
| 892 | siuniu_b2b_cnt++; | |
| 893 | siuniu_b2b_trans++; | |
| 894 | ||
| 895 | if(sio_niu_last_cmd_valid) { | |
| 896 | // only sample when both "last_niu_cmd" and "this_niu_cmd" | |
| 897 | // contain valid data, so the first command is never sampled | |
| 898 | trigger (sio_niu_sample_evnt_trig); | |
| 899 | } | |
| 900 | else | |
| 901 | { | |
| 902 | sio_niu_last_cmd_valid = 1'b1; | |
| 903 | siuniu_b2b_cnt = 0; | |
| 904 | } | |
| 905 | ||
| 906 | // for niu-dmu | |
| 907 | sio_niu_dmu_back_to_back = sio_niu_this_cmd_cycle - sio_dmu_this_cmd_cycle; | |
| 908 | ||
| 909 | } // siu_coverage_ifc.sio_niu_req | |
| 910 | } // while (1) | |
| 911 | } // fork | |
| 912 | join none | |
| 913 | ||
| 914 | ||
| 915 | fork | |
| 916 | { | |
| 917 | while(1) | |
| 918 | { | |
| 919 | @(posedge siu_coverage_ifc.clk); | |
| 920 | if (siuniu_b2b1_cnt === 'd40) | |
| 921 | { | |
| 922 | ||
| 923 | if (siu_coverage_ifc.sio_niu_req === 1'b1 && siu_coverage_ifc.sio_niu_data[127] === 1'b1 && siu_coverage_ifc.sio_niu_data[125] === 1'b1) | |
| 924 | siuniu_b2b1_cnt = 1; | |
| 925 | else | |
| 926 | siuniu_b2b1_cnt = 0; | |
| 927 | } | |
| 928 | else if (siu_coverage_ifc.sio_niu_req === 1'b1 && siu_coverage_ifc.sio_niu_data[127] === 1'b1 && siu_coverage_ifc.sio_niu_data[125] === 1'b1) | |
| 929 | { | |
| 930 | siuniu_b2b1_cnt = siuniu_b2b1_cnt + 1; | |
| 931 | if (siuniu_b2b1_cnt === 'd40) | |
| 932 | trigger (sio_niu_b2b_sample_evnt_trig); | |
| 933 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 934 | } | |
| 935 | else | |
| 936 | siuniu_b2b1_cnt = 0; | |
| 937 | } // while (1) | |
| 938 | } // fork | |
| 939 | join none | |
| 940 | ||
| 941 | fork | |
| 942 | { | |
| 943 | while(1) | |
| 944 | { | |
| 945 | @(posedge siu_coverage_ifc.clk); | |
| 946 | if (siuniu_b2b_wri_cnt === 'd200) | |
| 947 | { | |
| 948 | ||
| 949 | if (siu_coverage_ifc.sio_niu_req === 1'b1 && siu_coverage_ifc.sio_niu_data[127] === 1'b1 && siu_coverage_ifc.sio_niu_data[125] === 1'b0) | |
| 950 | siuniu_b2b_wri_cnt = 1; | |
| 951 | else | |
| 952 | siuniu_b2b_wri_cnt = 0; | |
| 953 | } | |
| 954 | else if (siu_coverage_ifc.sio_niu_data === 1'b1 && siu_coverage_ifc.sio_niu_data[127] === 1'b1 && siu_coverage_ifc.sio_niu_data[125] === 1'b0) | |
| 955 | { | |
| 956 | siuniu_b2b_wri_cnt = siuniu_b2b_wri_cnt + 1; | |
| 957 | if (siuniu_b2b_wri_cnt === 'd200) | |
| 958 | trigger (sio_niu_b2b_wri_sample_evnt_trig); | |
| 959 | } | |
| 960 | else | |
| 961 | siuniu_b2b_wri_cnt = 0; | |
| 962 | } // while (1) | |
| 963 | } // fork | |
| 964 | join none | |
| 965 | ||
| 966 | ||
| 967 | ||
| 968 | ||
| 969 | ||
| 970 | //----------------- SII-L2 ----------------------- | |
| 971 | ||
| 972 | fork | |
| 973 | { | |
| 974 | integer i ; | |
| 975 | while (1) | |
| 976 | { | |
| 977 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 978 | counter_vld = 0; | |
| 979 | counter0_vld = 0; | |
| 980 | counter1_vld = 0; | |
| 981 | counter2_vld = 0; | |
| 982 | counter3_vld = 0; | |
| 983 | counter4_vld = 0; | |
| 984 | counter5_vld = 0; | |
| 985 | counter6_vld = 0; | |
| 986 | counter7_vld = 0; | |
| 987 | ||
| 988 | for (i=0 ; i<5 ; i++) { | |
| 989 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 990 | l2t0 = siu_coverage_ifc_l2.sii_l2t0; | |
| 991 | l2t1 = siu_coverage_ifc_l2.sii_l2t1; | |
| 992 | l2t2 = siu_coverage_ifc_l2.sii_l2t2; | |
| 993 | l2t3 = siu_coverage_ifc_l2.sii_l2t3; | |
| 994 | l2t4 = siu_coverage_ifc_l2.sii_l2t4; | |
| 995 | l2t5 = siu_coverage_ifc_l2.sii_l2t5; | |
| 996 | l2t6 = siu_coverage_ifc_l2.sii_l2t6; | |
| 997 | l2t7 = siu_coverage_ifc_l2.sii_l2t7; | |
| 998 | counter0_vld += (l2t0 ==1) ? 1:0 ; | |
| 999 | counter1_vld += (l2t1 ==1) ? 1:0 ; | |
| 1000 | counter2_vld += (l2t2 ==1) ? 1:0 ; | |
| 1001 | counter3_vld += (l2t3 ==1) ? 1:0 ; | |
| 1002 | counter4_vld += (l2t4 ==1) ? 1:0 ; | |
| 1003 | counter5_vld += (l2t5 ==1) ? 1:0 ; | |
| 1004 | counter6_vld += (l2t6 ==1) ? 1:0 ; | |
| 1005 | counter7_vld += (l2t7 ==1) ? 1:0 ; | |
| 1006 | } | |
| 1007 | counter_vld = ((counter0_vld >= 1) + (counter1_vld >= 1) + (counter2_vld >= 1) + (counter3_vld >= 1) + (counter4_vld >= 1) + (counter5_vld >= 1) +(counter6_vld >= 1) + (counter7_vld >= 1)); | |
| 1008 | if (counter_vld > 1) | |
| 1009 | trigger (siu_l2_vld_sample_evnt_trig); | |
| 1010 | ||
| 1011 | } // while (1) | |
| 1012 | } // fork | |
| 1013 | join none | |
| 1014 | ||
| 1015 | fork | |
| 1016 | { | |
| 1017 | integer i ; | |
| 1018 | while (1) | |
| 1019 | { | |
| 1020 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1021 | counter_iq = 0; | |
| 1022 | counter0_iq = 0; | |
| 1023 | counter1_iq = 0; | |
| 1024 | counter2_iq = 0; | |
| 1025 | counter3_iq = 0; | |
| 1026 | counter4_iq = 0; | |
| 1027 | counter5_iq = 0; | |
| 1028 | counter6_iq = 0; | |
| 1029 | counter7_iq = 0; | |
| 1030 | ||
| 1031 | for (i=0 ; i<5 ; i++) { | |
| 1032 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1033 | ||
| 1034 | l2t0_iq_deq = siu_coverage_ifc_l2.l2t0_iq_dq; | |
| 1035 | l2t1_iq_deq = siu_coverage_ifc_l2.l2t1_iq_dq; | |
| 1036 | l2t2_iq_deq = siu_coverage_ifc_l2.l2t2_iq_dq; | |
| 1037 | l2t3_iq_deq = siu_coverage_ifc_l2.l2t3_iq_dq; | |
| 1038 | l2t4_iq_deq = siu_coverage_ifc_l2.l2t4_iq_dq; | |
| 1039 | l2t5_iq_deq = siu_coverage_ifc_l2.l2t5_iq_dq; | |
| 1040 | l2t6_iq_deq = siu_coverage_ifc_l2.l2t6_iq_dq; | |
| 1041 | l2t7_iq_deq = siu_coverage_ifc_l2.l2t7_iq_dq; | |
| 1042 | ||
| 1043 | counter0_iq += (l2t0_iq_deq ==1) ? 1:0 ; | |
| 1044 | counter1_iq += (l2t1_iq_deq ==1) ? 1:0 ; | |
| 1045 | counter2_iq += (l2t2_iq_deq ==1) ? 1:0 ; | |
| 1046 | counter3_iq += (l2t3_iq_deq ==1) ? 1:0 ; | |
| 1047 | counter4_iq += (l2t4_iq_deq ==1) ? 1:0 ; | |
| 1048 | counter5_iq += (l2t5_iq_deq ==1) ? 1:0 ; | |
| 1049 | counter6_iq += (l2t6_iq_deq ==1) ? 1:0 ; | |
| 1050 | counter7_iq += (l2t7_iq_deq ==1) ? 1:0 ; | |
| 1051 | ||
| 1052 | } | |
| 1053 | counter_iq = ((counter0_iq >= 1) + (counter1_iq >= 1) + (counter2_iq >= 1) + (counter3_iq >= 1) + (counter4_iq >= 1) + (counter5_iq >= 1) +(counter6_iq >= 1) + (counter7_iq >= 1)); | |
| 1054 | if (counter_iq > 1) | |
| 1055 | trigger (siu_l2_iq_deq_sample_evnt_trig); | |
| 1056 | } // while (1) | |
| 1057 | } // fork | |
| 1058 | join none | |
| 1059 | ||
| 1060 | fork | |
| 1061 | { | |
| 1062 | integer i ; | |
| 1063 | while (1) | |
| 1064 | { | |
| 1065 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1066 | counter_wib = 0; | |
| 1067 | counter0_wib = 0; | |
| 1068 | counter1_wib = 0; | |
| 1069 | counter2_wib = 0; | |
| 1070 | counter3_wib = 0; | |
| 1071 | counter4_wib = 0; | |
| 1072 | counter5_wib = 0; | |
| 1073 | counter6_wib = 0; | |
| 1074 | counter7_wib = 0; | |
| 1075 | ||
| 1076 | for (i=0 ; i<5 ; i++) { | |
| 1077 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1078 | l2t0_wib_deq = siu_coverage_ifc_l2.l2t0_wib_dq; | |
| 1079 | l2t1_wib_deq = siu_coverage_ifc_l2.l2t1_wib_dq; | |
| 1080 | l2t2_wib_deq = siu_coverage_ifc_l2.l2t2_wib_dq; | |
| 1081 | l2t3_wib_deq = siu_coverage_ifc_l2.l2t3_wib_dq; | |
| 1082 | l2t4_wib_deq = siu_coverage_ifc_l2.l2t4_wib_dq; | |
| 1083 | l2t5_wib_deq = siu_coverage_ifc_l2.l2t5_wib_dq; | |
| 1084 | l2t6_wib_deq = siu_coverage_ifc_l2.l2t6_wib_dq; | |
| 1085 | l2t7_wib_deq = siu_coverage_ifc_l2.l2t7_wib_dq; | |
| 1086 | ||
| 1087 | counter0_wib += (l2t0_wib_deq ==1) ? 1:0 ; | |
| 1088 | counter1_wib += (l2t1_wib_deq ==1) ? 1:0 ; | |
| 1089 | counter2_wib += (l2t2_wib_deq ==1) ? 1:0 ; | |
| 1090 | counter3_wib += (l2t3_wib_deq ==1) ? 1:0 ; | |
| 1091 | counter4_wib += (l2t4_wib_deq ==1) ? 1:0 ; | |
| 1092 | counter5_wib += (l2t5_wib_deq ==1) ? 1:0 ; | |
| 1093 | counter6_wib += (l2t6_wib_deq ==1) ? 1:0 ; | |
| 1094 | counter7_wib += (l2t7_wib_deq ==1) ? 1:0 ; | |
| 1095 | } | |
| 1096 | counter_wib = ((counter0_wib >= 1) + (counter1_wib >= 1) + (counter2_wib >= 1) + (counter3_wib >= 1) + (counter4_wib >= 1) + (counter5_wib >= 1) +(counter6_wib >= 1) + (counter7_wib >= 1)); | |
| 1097 | if (counter_wib > 1) | |
| 1098 | trigger (siu_l2_wib_deq_sample_evnt_trig); | |
| 1099 | } // while (1) | |
| 1100 | } // fork | |
| 1101 | join none | |
| 1102 | ||
| 1103 | fork | |
| 1104 | { | |
| 1105 | integer i ; | |
| 1106 | while (1) | |
| 1107 | { | |
| 1108 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1109 | counter_data = 0; | |
| 1110 | counter0_data = 0; | |
| 1111 | counter1_data = 0; | |
| 1112 | counter2_data = 0; | |
| 1113 | counter3_data = 0; | |
| 1114 | counter4_data = 0; | |
| 1115 | counter5_data = 0; | |
| 1116 | counter6_data = 0; | |
| 1117 | counter7_data = 0; | |
| 1118 | ||
| 1119 | for (i=0 ; i<5 ; i++) { | |
| 1120 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1121 | l2t0_data_sio = siu_coverage_ifc_l2.l2b0_sio_ctag_vld; | |
| 1122 | l2t1_data_sio = siu_coverage_ifc_l2.l2b1_sio_ctag_vld; | |
| 1123 | l2t2_data_sio = siu_coverage_ifc_l2.l2b2_sio_ctag_vld; | |
| 1124 | l2t3_data_sio = siu_coverage_ifc_l2.l2b3_sio_ctag_vld; | |
| 1125 | l2t4_data_sio = siu_coverage_ifc_l2.l2b4_sio_ctag_vld; | |
| 1126 | l2t5_data_sio = siu_coverage_ifc_l2.l2b5_sio_ctag_vld; | |
| 1127 | l2t6_data_sio = siu_coverage_ifc_l2.l2b6_sio_ctag_vld; | |
| 1128 | l2t7_data_sio = siu_coverage_ifc_l2.l2b7_sio_ctag_vld; | |
| 1129 | l2t0_data = siu_coverage_ifc_l2.l2b0_sio_data[16]; | |
| 1130 | l2t1_data = siu_coverage_ifc_l2.l2b1_sio_data[16]; | |
| 1131 | l2t2_data = siu_coverage_ifc_l2.l2b2_sio_data[16]; | |
| 1132 | l2t3_data = siu_coverage_ifc_l2.l2b3_sio_data[16]; | |
| 1133 | l2t4_data = siu_coverage_ifc_l2.l2b4_sio_data[16]; | |
| 1134 | l2t5_data = siu_coverage_ifc_l2.l2b5_sio_data[16]; | |
| 1135 | l2t6_data = siu_coverage_ifc_l2.l2b6_sio_data[16]; | |
| 1136 | l2t7_data = siu_coverage_ifc_l2.l2b7_sio_data[16]; | |
| 1137 | ||
| 1138 | counter0_data += (l2t0_data_sio ==1 && l2t0_data ==1) ? 1:0 ; | |
| 1139 | counter1_data += (l2t1_data_sio ==1 && l2t1_data ==1) ? 1:0 ; | |
| 1140 | counter2_data += (l2t2_data_sio ==1 && l2t2_data ==1) ? 1:0 ; | |
| 1141 | counter3_data += (l2t3_data_sio ==1 && l2t3_data ==1) ? 1:0 ; | |
| 1142 | counter4_data += (l2t4_data_sio ==1 && l2t4_data ==1) ? 1:0 ; | |
| 1143 | counter5_data += (l2t5_data_sio ==1 && l2t5_data ==1) ? 1:0 ; | |
| 1144 | counter6_data += (l2t6_data_sio ==1 && l2t6_data ==1) ? 1:0 ; | |
| 1145 | counter7_data += (l2t7_data_sio ==1 && l2t7_data ==1) ? 1:0 ; | |
| 1146 | } | |
| 1147 | counter_data = ((counter0_data >= 1) + (counter1_data >= 1) + (counter2_data >= 1) + (counter3_data >= 1) + (counter4_data >= 1) + (counter5_data >= 1) +(counter6_data >= 1) + (counter7_data >= 1)); | |
| 1148 | if (counter_data > 1) | |
| 1149 | trigger (siu_l2_data_sio_sample_evnt_trig); | |
| 1150 | } // while (1) | |
| 1151 | } // fork | |
| 1152 | join none | |
| 1153 | ||
| 1154 | //----------------- SII-L2 ----------------------- | |
| 1155 | ||
| 1156 | fork | |
| 1157 | { | |
| 1158 | ||
| 1159 | integer siu_l2_wib_deq_last_cmd_cycle, siu_l2_wib_deq_this_cmd_cycle; | |
| 1160 | integer siu_l2_data_sio_last_cmd_cycle, siu_l2_data_sio_this_cmd_cycle; | |
| 1161 | siu_l2_wib_deq_this_cmd_cycle = get_cycle(siu_coverage_ifc_l2.clk); | |
| 1162 | ||
| 1163 | while (1) | |
| 1164 | { | |
| 1165 | @ (posedge siu_coverage_ifc_l2.clk); | |
| 1166 | ||
| 1167 | bank0 = siu_coverage_ifc_l2.sii_l2t0; | |
| 1168 | bank1 = siu_coverage_ifc_l2.sii_l2t1; | |
| 1169 | bank2 = siu_coverage_ifc_l2.sii_l2t2; | |
| 1170 | bank3 = siu_coverage_ifc_l2.sii_l2t3; | |
| 1171 | bank4 = siu_coverage_ifc_l2.sii_l2t4; | |
| 1172 | bank5 = siu_coverage_ifc_l2.sii_l2t5; | |
| 1173 | bank6 = siu_coverage_ifc_l2.sii_l2t6; | |
| 1174 | bank7 = siu_coverage_ifc_l2.sii_l2t7; | |
| 1175 | ||
| 1176 | switch_banks = {bank7, bank6, bank5, bank4, bank3, bank2, bank1, bank0}; | |
| 1177 | ||
| 1178 | ||
| 1179 | . for ($bank=0; $bank<8; $bank++) | |
| 1180 | . { | |
| 1181 | ||
| 1182 | if( siu_coverage_ifc_l2.sii_l2t${bank} ) | |
| 1183 | { | |
| 1184 | sii_l2t${bank} = siu_coverage_ifc_l2.sii_l2t${bank}; | |
| 1185 | l2t${bank}_iq_dq = siu_coverage_ifc_l2.l2t${bank}_iq_dq; | |
| 1186 | l2t${bank}_wib_dq = siu_coverage_ifc_l2.l2t${bank}_wib_dq; | |
| 1187 | sii_l2t${bank}_data = siu_coverage_ifc_l2.sii_l2t${bank}_data; | |
| 1188 | ||
| 1189 | last_l2${bank}_cycle = this_l2${bank}_cycle; | |
| 1190 | this_l2${bank}_cycle = get_cycle(siu_coverage_ifc_l2.clk); | |
| 1191 | ||
| 1192 | if (last_l2${bank}_cmd[2:0]==3'b100) // WRI | |
| 1193 | { | |
| 1194 | if((this_l2${bank}_cycle - last_l2${bank}_cycle) <= SII_L2_WRI_B2B_DELAY ) //18; minimum gap=17cycle | |
| 1195 | l2${bank}_back_to_back = 1'b1; | |
| 1196 | else | |
| 1197 | l2${bank}_back_to_back = 1'b0; | |
| 1198 | } | |
| 1199 | ||
| 1200 | else | |
| 1201 | if (last_l2${bank}_cmd[2:0]==3'b001) // RDD | |
| 1202 | { | |
| 1203 | if((this_l2${bank}_cycle - last_l2${bank}_cycle) == SII_L2_RDD_B2B_DELAY ) // 5 cycle | |
| 1204 | l2${bank}_back_to_back = 1'b1; | |
| 1205 | else | |
| 1206 | l2${bank}_back_to_back = 1'b0; | |
| 1207 | } | |
| 1208 | ||
| 1209 | else | |
| 1210 | if (last_l2${bank}_cmd[2:0]==3'b010) // WR8 | |
| 1211 | { | |
| 1212 | if((this_l2${bank}_cycle - last_l2${bank}_cycle) == SII_L2_WR8_B2B_DELAY ) // 4 cycle | |
| 1213 | l2${bank}_back_to_back = 1'b1; | |
| 1214 | else | |
| 1215 | l2${bank}_back_to_back = 1'b0; | |
| 1216 | } | |
| 1217 | ||
| 1218 | last_l2${bank}_cmd = this_l2${bank}_cmd; | |
| 1219 | this_l2${bank}_cmd = {sii_l2t${bank}_data[30:29], | |
| 1220 | sii_l2t${bank}_data[27:24]}; | |
| 1221 | // <30>=O, <29>P, <27>=S | |
| 1222 | ||
| 1223 | ||
| 1224 | //for switchbank | |
| 1225 | this_l2_cmd = this_l2${bank}_cmd; | |
| 1226 | ||
| 1227 | if(last_l2${bank}_cmd_valid) | |
| 1228 | { | |
| 1229 | // only sample when both "last_l2${bank}_cmd" and "this_l2${bank}_cmd" | |
| 1230 | // contain valid data, so the first command is never sampled | |
| 1231 | trigger (l2_sample_evnt_trig); | |
| 1232 | } | |
| 1233 | else | |
| 1234 | last_l2${bank}_cmd_valid = 1'b1; | |
| 1235 | } // if( siu_coverage_ifc_l2.sii_l2t${bank} ) | |
| 1236 | ||
| 1237 | ||
| 1238 | if( siu_coverage_ifc_l2.sii_l2t${bank} ) | |
| 1239 | { | |
| 1240 | sii_l2t${bank}_trans = siu_coverage_ifc_l2.sii_l2t${bank}_data[27]; | |
| 1241 | trigger (siu_l2_trans_sample_evnt_trig); | |
| 1242 | } // siu_coverage_ifc | |
| 1243 | ||
| 1244 | if( siu_coverage_ifc_l2.sii_l2t${bank} && sii_l2t${bank}_data[26:24] === 3'b100) | |
| 1245 | { | |
| 1246 | trigger (siu_fc_err_wri_sample_evnt_trig); | |
| 1247 | } // siu_coverage_ifc | |
| 1248 | ||
| 1249 | if( siu_coverage_ifc_l2.sii_l2t${bank} && sii_l2t${bank}_data[26:24] === 3'b010) | |
| 1250 | { | |
| 1251 | trigger (siu_fc_err_wr8_sample_evnt_trig); | |
| 1252 | } // siu_coverage_ifc | |
| 1253 | ||
| 1254 | if( siu_coverage_ifc_l2.sii_l2t${bank} && sii_l2t${bank}_data[26:24] === 3'b001) | |
| 1255 | { | |
| 1256 | trigger (siu_fc_err_rdd_sample_evnt_trig); | |
| 1257 | } // siu_coverage_ifc | |
| 1258 | ||
| 1259 | ||
| 1260 | ||
| 1261 | /************** L2-SIO *****************/ | |
| 1262 | ||
| 1263 | if( siu_coverage_ifc_l2.l2b${bank}_sio_ctag_vld ) | |
| 1264 | { | |
| 1265 | l2b${bank}_sio_ctag_vld = siu_coverage_ifc_l2.l2b${bank}_sio_ctag_vld; | |
| 1266 | l2b${bank}_sio_data = siu_coverage_ifc_l2.l2b${bank}_sio_data; | |
| 1267 | ||
| 1268 | last_l2${bank}_ob_cycle = this_l2${bank}_ob_cycle; | |
| 1269 | this_l2${bank}_ob_cycle = get_cycle(siu_coverage_ifc_l2.clk); | |
| 1270 | ||
| 1271 | if (last_l2${bank}_ob_cmd[3:0]==4'b0001) // RDD | |
| 1272 | { | |
| 1273 | if((this_l2${bank}_ob_cycle - last_l2${bank}_ob_cycle) <= L2_SIO_RDD_B2B_DELAY ) // 17 cyc min | |
| 1274 | { | |
| 1275 | l2${bank}_ob_back_to_back = 1'b1; | |
| 1276 | } | |
| 1277 | else | |
| 1278 | l2${bank}_ob_back_to_back = 1'b0; | |
| 1279 | } | |
| 1280 | ||
| 1281 | else | |
| 1282 | if (last_l2${bank}_ob_cmd[3:0]==4'b0000) // WRI or WR8 | |
| 1283 | { | |
| 1284 | if((this_l2${bank}_ob_cycle - last_l2${bank}_ob_cycle) <= L2_SIO_WR_B2B_DELAY) // 9 cyc min | |
| 1285 | l2${bank}_ob_back_to_back = 1'b1; | |
| 1286 | else | |
| 1287 | l2${bank}_ob_back_to_back = 1'b0; | |
| 1288 | } | |
| 1289 | ||
| 1290 | ||
| 1291 | last_l2${bank}_ob_cmd = this_l2${bank}_ob_cmd; | |
| 1292 | this_l2${bank}_ob_cmd = {l2b${bank}_sio_data[23:22], | |
| 1293 | l2b${bank}_sio_data[20:16]} ; | |
| 1294 | ||
| 1295 | if(last_l2${bank}_ob_cmd_valid) | |
| 1296 | { | |
| 1297 | // only sample when both "last_l2${bank}_ob_cmd" and "this_l2${bank}_ob_cmd" | |
| 1298 | // contain valid data, so the first command is never sampled | |
| 1299 | trigger (l2_ob_sample_evnt_trig); | |
| 1300 | } | |
| 1301 | else | |
| 1302 | last_l2${bank}_ob_cmd_valid = 1'b1; | |
| 1303 | ||
| 1304 | ||
| 1305 | } // if( siu_coverage_ifc_l2.l2b${bank}_sio_ctag_vld) | |
| 1306 | ||
| 1307 | . } | |
| 1308 | } // while (1) | |
| 1309 | } // fork | |
| 1310 | join none | |
| 1311 | } // task siu_intf_coverage | |
| 1312 | ||
| 1313 | ||
| 1314 | //////////////////////////////////////////////////////////////////////// | |
| 1315 | // siu interface schmoo | |
| 1316 | //////////////////////////////////////////////////////////////////////// | |
| 1317 | class siu_intf_schmoo_coverage | |
| 1318 | { | |
| 1319 | StandardDisplay dbg; | |
| 1320 | local string myname; | |
| 1321 | ||
| 1322 | bit siu_intf_schmoo_cov_debug = 1'b0; | |
| 1323 | bit niu_bqdq; | |
| 1324 | bit niu_oqdq; | |
| 1325 | bit niu_bqdq_al; | |
| 1326 | bit niu_bqdq_que; | |
| 1327 | bit niusiu_oqdq_value; | |
| 1328 | bit niusiu_bqdq_value; | |
| 1329 | bit niusiu_bqdq_al; | |
| 1330 | bit niusiu_bqdq_al_value; | |
| 1331 | bit [6:0] last_niu_cmd; | |
| 1332 | bit [6:0] this_niu_cmd, last2_niu_cmd; | |
| 1333 | bit [5:0] niu_cmd; | |
| 1334 | bit niubypass; | |
| 1335 | bit niudatareq; | |
| 1336 | bit [127:0] niudata; | |
| 1337 | bit [15:0] niu_id; | |
| 1338 | bit [3:0] partial_mode; | |
| 1339 | bit [3:0] partial_mode1; | |
| 1340 | bit ncu_ba01; | |
| 1341 | bit ncu_ba23; | |
| 1342 | bit ncu_ba45; | |
| 1343 | bit ncu_ba67; | |
| 1344 | ||
| 1345 | bit [2:0] dmu_data_876; | |
| 1346 | bit [2:0] dmu_data_876_2; | |
| 1347 | bit [2:0] dmu_data_876_3; | |
| 1348 | bit [2:0] dmu_data_876_4; | |
| 1349 | bit [2:0] dmu_data_876_5; | |
| 1350 | bit [2:0] dmu_data_876_6; | |
| 1351 | bit [2:0] dmu_data_876_7; | |
| 1352 | bit [2:0] dmu_data_876_8; | |
| 1353 | bit [2:0] dmu_data_876_9; | |
| 1354 | bit [2:0] dmu_data_876_10; | |
| 1355 | bit [2:0] dmu_data_876_11; | |
| 1356 | bit dmu_data_6; | |
| 1357 | bit dmu_data_7; | |
| 1358 | bit dmu_data_8; | |
| 1359 | bit [2:0] niu_data_876; | |
| 1360 | bit [2:0] niu_data_876_2; | |
| 1361 | bit [2:0] niu_data_876_3; | |
| 1362 | bit [2:0] niu_data_876_4; | |
| 1363 | bit [2:0] niu_data_876_5; | |
| 1364 | bit [2:0] niu_data_876_6; | |
| 1365 | bit [2:0] niu_data_876_7; | |
| 1366 | bit [2:0] niu_data_876_8; | |
| 1367 | bit [2:0] niu_data_876_9; | |
| 1368 | bit [2:0] niu_data_876_10; | |
| 1369 | bit [2:0] niu_data_876_11; | |
| 1370 | bit niu_data_6; | |
| 1371 | bit niu_data_7; | |
| 1372 | bit niu_data_8; | |
| 1373 | ||
| 1374 | integer niusiu_oqdq_b2b = 0; | |
| 1375 | integer niusiu_bqdq_b2b = 0; | |
| 1376 | integer niusiu_bqdq_al_b2b = 0; | |
| 1377 | integer niusiu_oqdq_b2b_state = 0; | |
| 1378 | integer niusiu_bqdq_b2b_state = 0; | |
| 1379 | integer niusiu_bqdq_b2b_cnt = 0; | |
| 1380 | integer niusiu_oqdq_b2b_cnt = 0; | |
| 1381 | integer niusiu_bqdq_al_b2b_cnt = 0; | |
| 1382 | integer niusiu_bqdq_que_b2b_cnt = 0; | |
| 1383 | integer niusiu_bqdq_que_b2b_wri_nonpost_cnt = 0; | |
| 1384 | integer niusiu_bqdq_que_b2b_wri_post_cnt = 0; | |
| 1385 | integer niusiu_bqdq_al_b2b_state = 0; | |
| 1386 | integer siuncu_gnt_del_cnt = 0; | |
| 1387 | integer siu_ncu_gnt_req; | |
| 1388 | ||
| 1389 | event dmureq_evnt_trig; | |
| 1390 | event niureq_evnt_trig; | |
| 1391 | event niureq_oqdq_evnt_trig; | |
| 1392 | event niureq_bqdq_evnt_trig; | |
| 1393 | event niureq_bqdq_al_evnt_trig; | |
| 1394 | event niureq_bqdq_que_evnt_trig; | |
| 1395 | event niureq_bqdq_wri_nonpost_que_evnt_trig; | |
| 1396 | event niureq_bqdq_wri_post_que_evnt_trig; | |
| 1397 | event ncu_gnt_req_evnt_trig; | |
| 1398 | event ncu_gnt_req_del_evnt_trig; | |
| 1399 | event ncu_gnt_req_del_10_evnt_trig; | |
| 1400 | event ncu_pm_1_evnt_trig; | |
| 1401 | event ncu_pm1_1_evnt_trig; | |
| 1402 | event ncu_pm1_2_evnt_trig; | |
| 1403 | event ncu_pm1_3_evnt_trig; | |
| 1404 | event ncu_pm1_4_evnt_trig; | |
| 1405 | event ncu_pm1_5_evnt_trig; | |
| 1406 | event ncu_pm1_6_evnt_trig; | |
| 1407 | event ncu_pm1_7_evnt_trig; | |
| 1408 | event ncu_pm1_8_evnt_trig; | |
| 1409 | event ncu_pm1_9_evnt_trig; | |
| 1410 | event ncu_pm1_10_evnt_trig; | |
| 1411 | event ncu_pm1_11_evnt_trig; | |
| 1412 | event ncu_pm1_niu_1_evnt_trig; | |
| 1413 | event ncu_pm1_niu_2_evnt_trig; | |
| 1414 | event ncu_pm1_niu_3_evnt_trig; | |
| 1415 | event ncu_pm1_niu_4_evnt_trig; | |
| 1416 | event ncu_pm1_niu_5_evnt_trig; | |
| 1417 | event ncu_pm1_niu_6_evnt_trig; | |
| 1418 | event ncu_pm1_niu_7_evnt_trig; | |
| 1419 | event ncu_pm1_niu_8_evnt_trig; | |
| 1420 | event ncu_pm1_niu_9_evnt_trig; | |
| 1421 | event ncu_pm1_niu_10_evnt_trig; | |
| 1422 | event ncu_pm1_niu_11_evnt_trig; | |
| 1423 | ||
| 1424 | // ----------- coverage_group ---------------- | |
| 1425 | ||
| 1426 | coverage_group siu_niu_intf_oqdq_coverage_group | |
| 1427 | { | |
| 1428 | sample_event = sync (ANY, niureq_oqdq_evnt_trig ); | |
| 1429 | #include "siu_niu_oqdq_sample.vrh" | |
| 1430 | ||
| 1431 | } // siu_niu_intf_coverage_group | |
| 1432 | ||
| 1433 | coverage_group siu_niu_intf_bqdq_coverage_group | |
| 1434 | { | |
| 1435 | sample_event = sync (ANY, niureq_bqdq_evnt_trig ); | |
| 1436 | #include "siu_niu_bqdq_sample.vrh" | |
| 1437 | ||
| 1438 | } // siu_niu_intf_coverage_group | |
| 1439 | ||
| 1440 | coverage_group siu_niu_intf_bqdq_al_coverage_group | |
| 1441 | { | |
| 1442 | sample_event = sync (ANY, niureq_bqdq_al_evnt_trig ); | |
| 1443 | #include "siu_niu_bqdq_al_sample.vrh" | |
| 1444 | ||
| 1445 | } // siu_niu_intf_coverage_group | |
| 1446 | ||
| 1447 | coverage_group siu_niu_intf_bqdq_que_coverage_group | |
| 1448 | { | |
| 1449 | sample_event = sync (ANY, niureq_bqdq_que_evnt_trig, niureq_bqdq_wri_nonpost_que_evnt_trig, niureq_bqdq_wri_post_que_evnt_trig ); | |
| 1450 | #include "siu_niu_bqdq_que_sample.vrh" | |
| 1451 | ||
| 1452 | } // siu_niu_intf_coverage_group | |
| 1453 | ||
| 1454 | coverage_group siu_ncu_intf_gnt_min_coverage_group | |
| 1455 | { | |
| 1456 | sample_event = sync (ANY, ncu_gnt_req_evnt_trig, ncu_gnt_req_del_evnt_trig, ncu_gnt_req_del_10_evnt_trig ); | |
| 1457 | #include "siu_ncu_intf_gnt_min_sample.vrh" | |
| 1458 | ||
| 1459 | } // siu_ncu_intf_coverage_group | |
| 1460 | ||
| 1461 | coverage_group siu_ncu_intf_partial_coverage_group | |
| 1462 | { | |
| 1463 | sample_event = sync (ANY, ncu_pm_1_evnt_trig ); | |
| 1464 | #include "siu_ncu_intf_pm_sample.vrh" | |
| 1465 | ||
| 1466 | } // siu_ncu_intf_coverage_group | |
| 1467 | ||
| 1468 | coverage_group siu_ncu_intf_partial_bank_coverage_group | |
| 1469 | { | |
| 1470 | sample_event = sync (ANY, ncu_pm1_1_evnt_trig, ncu_pm1_2_evnt_trig, ncu_pm1_3_evnt_trig, ncu_pm1_4_evnt_trig, ncu_pm1_5_evnt_trig, ncu_pm1_6_evnt_trig, ncu_pm1_7_evnt_trig, ncu_pm1_8_evnt_trig, ncu_pm1_9_evnt_trig, ncu_pm1_10_evnt_trig, ncu_pm1_11_evnt_trig ); | |
| 1471 | #include "siu_ncu_intf_pm_bank_sample.vrh" | |
| 1472 | ||
| 1473 | } // siu_ncu_intf_coverage_group | |
| 1474 | ||
| 1475 | coverage_group siu_ncu_intf_partial_bank_niu_coverage_group | |
| 1476 | { | |
| 1477 | sample_event = sync (ANY, ncu_pm1_niu_1_evnt_trig, ncu_pm1_niu_2_evnt_trig, ncu_pm1_niu_3_evnt_trig, ncu_pm1_niu_4_evnt_trig, ncu_pm1_niu_5_evnt_trig, ncu_pm1_niu_6_evnt_trig, ncu_pm1_niu_7_evnt_trig, ncu_pm1_niu_8_evnt_trig, ncu_pm1_niu_9_evnt_trig, ncu_pm1_niu_10_evnt_trig, ncu_pm1_niu_11_evnt_trig ); | |
| 1478 | #include "siu_ncu_intf_pm_bank1_sample.vrh" | |
| 1479 | ||
| 1480 | } // siu_ncu_intf_coverage_group | |
| 1481 | ||
| 1482 | ||
| 1483 | . for ($bank=0; $bank<8; $bank++) | |
| 1484 | . { | |
| 1485 | event l2${bank}req_evnt_trig; | |
| 1486 | . } | |
| 1487 | ||
| 1488 | ////// SII-NIU ////// | |
| 1489 | coverage_group sii_niu_req_ack_cov | |
| 1490 | { | |
| 1491 | sample_event = sync (ANY, niureq_evnt_trig ); | |
| 1492 | sample siu_coverage_ifc.niureq | |
| 1493 | { | |
| 1494 | state s_SIINIU_REQ_OQDQ (1) if (siu_coverage_ifc.niuoqdq === 1'b1); | |
| 1495 | state s_SIINIU_REQ_BQDQ (1) if (siu_coverage_ifc.niubqdq === 1'b1); | |
| 1496 | } | |
| 1497 | } | |
| 1498 | ||
| 1499 | ////// SII-DMU ////// | |
| 1500 | coverage_group sii_dmu_req_wack_cov | |
| 1501 | { | |
| 1502 | sample_event = sync (ANY, dmureq_evnt_trig ); | |
| 1503 | sample siu_coverage_ifc.dmureq | |
| 1504 | { | |
| 1505 | state s_SIIDMU_REQ_WACK (1) if (siu_coverage_ifc.dmuwrack_vld === 1'b1); | |
| 1506 | } | |
| 1507 | } | |
| 1508 | ////// SII-NCU ////// | |
| 1509 | coverage_group siu_ncugnt_req_cov | |
| 1510 | { | |
| 1511 | sample_event = @(posedge siu_coverage_ifc.ncu_gnt); | |
| 1512 | sample siu_coverage_ifc.ncu_gnt | |
| 1513 | { | |
| 1514 | state s_SIINCU_GNT_REQ (1) if (siu_coverage_ifc.ncu_req === 1'b1); | |
| 1515 | } | |
| 1516 | } | |
| 1517 | ||
| 1518 | ////// SII-L2 ////// | |
| 1519 | . for ($bank=0; $bank<8; $bank++) | |
| 1520 | . { | |
| 1521 | coverage_group sii_l2${bank}_req_ack_cov | |
| 1522 | { | |
| 1523 | sample_event = sync (ANY, l2${bank}req_evnt_trig ); | |
| 1524 | sample siu_coverage_ifc_l2.sii_l2t${bank} | |
| 1525 | { | |
| 1526 | state s_SIIL2${bank}_REQ_DQ (1) if (siu_coverage_ifc_l2.l2t${bank}_iq_dq === 1'b1); | |
| 1527 | state s_SIIL2${bank}_REQ_WIB (1) if (siu_coverage_ifc_l2.l2t${bank}_wib_dq === 1'b1); | |
| 1528 | state s_SIIL2${bank}_REQ_CTAG (1) if (siu_coverage_ifc_l2.l2b${bank}_sio_ctag_vld === 1'b1); | |
| 1529 | } | |
| 1530 | } | |
| 1531 | . } | |
| 1532 | ||
| 1533 | ////// declare functions & tasks ////// | |
| 1534 | task new(StandardDisplay dbg); | |
| 1535 | task set_cov_cond_bits (); | |
| 1536 | } // class siu_intf_schmoo_coverage | |
| 1537 | ||
| 1538 | ////// siu_intf_schmoo class | |
| 1539 | task siu_intf_schmoo_coverage::new(StandardDisplay dbg) | |
| 1540 | { | |
| 1541 | bit coverage_on; | |
| 1542 | ||
| 1543 | ||
| 1544 | ||
| 1545 | myname = "siu_intf_schmoo_coverage"; | |
| 1546 | this.dbg = dbg; | |
| 1547 | ||
| 1548 | if (mChkPlusarg(siu_intf_schmoo_coverage) || mChkPlusarg(coverage_on)) { | |
| 1549 | coverage_on = 1; | |
| 1550 | if (mChkPlusarg(siu_intf_schmoo_cov_debug)) { | |
| 1551 | siu_intf_schmoo_cov_debug = 1'b1; | |
| 1552 | } | |
| 1553 | } else { | |
| 1554 | coverage_on = 0; | |
| 1555 | } | |
| 1556 | ||
| 1557 | if (coverage_on) | |
| 1558 | { | |
| 1559 | sii_niu_req_ack_cov = new(); | |
| 1560 | ||
| 1561 | fork { | |
| 1562 | @(posedge siu_coverage_ifc.cmp_diag_done); | |
| 1563 | coverage_save_database(1); | |
| 1564 | } join none | |
| 1565 | ||
| 1566 | set_cov_cond_bits(); | |
| 1567 | } // coverage_on | |
| 1568 | } // siu_intf_schmoo_coverage new | |
| 1569 | ||
| 1570 | task siu_intf_schmoo_coverage::set_cov_cond_bits() | |
| 1571 | { | |
| 1572 | integer siu_ncu_this_cmd_cycle; | |
| 1573 | integer siu_ncu_last_cmd_cycle; | |
| 1574 | ||
| 1575 | siu_ncu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 1576 | ||
| 1577 | fork | |
| 1578 | { | |
| 1579 | while(1) | |
| 1580 | { | |
| 1581 | @(posedge siu_coverage_ifc.clk); | |
| 1582 | if (niusiu_oqdq_b2b_cnt === 'd8) | |
| 1583 | { | |
| 1584 | ||
| 1585 | if (siu_coverage_ifc.niuoqdq === 1'b1) | |
| 1586 | niusiu_oqdq_b2b_cnt = 1; | |
| 1587 | else | |
| 1588 | niusiu_oqdq_b2b_cnt = 0; | |
| 1589 | } | |
| 1590 | else if (siu_coverage_ifc.niuoqdq === 1'b1) | |
| 1591 | { | |
| 1592 | niusiu_oqdq_b2b_cnt = niusiu_oqdq_b2b_cnt + 1; | |
| 1593 | @(posedge siu_coverage_ifc.clk); | |
| 1594 | if (niusiu_oqdq_b2b_cnt === 'd8) | |
| 1595 | trigger (niureq_oqdq_evnt_trig); | |
| 1596 | } | |
| 1597 | else | |
| 1598 | niusiu_oqdq_b2b_cnt = 0; | |
| 1599 | } | |
| 1600 | } | |
| 1601 | join none | |
| 1602 | ||
| 1603 | ||
| 1604 | fork | |
| 1605 | { | |
| 1606 | while(1) | |
| 1607 | { | |
| 1608 | @(posedge siu_coverage_ifc.clk); | |
| 1609 | if (niusiu_bqdq_b2b_cnt === 'd8) | |
| 1610 | { | |
| 1611 | ||
| 1612 | if (siu_coverage_ifc.niubqdq === 1'b1) | |
| 1613 | niusiu_bqdq_b2b_cnt = 1; | |
| 1614 | else | |
| 1615 | niusiu_bqdq_b2b_cnt = 0; | |
| 1616 | } | |
| 1617 | else if (siu_coverage_ifc.niubqdq === 1'b1) | |
| 1618 | { | |
| 1619 | niusiu_bqdq_b2b_cnt = niusiu_bqdq_b2b_cnt + 1; | |
| 1620 | @(posedge siu_coverage_ifc.clk); | |
| 1621 | if (niusiu_bqdq_b2b_cnt === 'd8) | |
| 1622 | trigger (niureq_bqdq_evnt_trig); | |
| 1623 | } | |
| 1624 | else | |
| 1625 | niusiu_bqdq_b2b_cnt = 0; | |
| 1626 | } | |
| 1627 | } | |
| 1628 | join none | |
| 1629 | ||
| 1630 | ||
| 1631 | fork | |
| 1632 | { | |
| 1633 | while(1) | |
| 1634 | { | |
| 1635 | @(posedge siu_coverage_ifc.clk); | |
| 1636 | if (niusiu_bqdq_al_b2b_cnt === 'd5) | |
| 1637 | { | |
| 1638 | ||
| 1639 | if (siu_coverage_ifc.niubqdq === 1'b1 && siu_coverage_ifc.niuoqdq === 1'b0) | |
| 1640 | niusiu_bqdq_al_b2b_cnt = 1; | |
| 1641 | else | |
| 1642 | niusiu_bqdq_al_b2b_cnt = 0; | |
| 1643 | } | |
| 1644 | else if (siu_coverage_ifc.niubqdq === 1'b1 && siu_coverage_ifc.niuoqdq === 1'b0) | |
| 1645 | { | |
| 1646 | niusiu_bqdq_al_b2b_cnt = niusiu_bqdq_al_b2b_cnt + 1; | |
| 1647 | @(posedge siu_coverage_ifc.clk); | |
| 1648 | if (siu_coverage_ifc.niuoqdq === 1'b1 && siu_coverage_ifc.niubqdq === 1'b0) | |
| 1649 | niusiu_bqdq_al_b2b_cnt = niusiu_bqdq_al_b2b_cnt + 1; | |
| 1650 | @(posedge siu_coverage_ifc.clk); | |
| 1651 | if (siu_coverage_ifc.niubqdq === 1'b1 && siu_coverage_ifc.niuoqdq === 1'b0) | |
| 1652 | niusiu_bqdq_al_b2b_cnt = niusiu_bqdq_al_b2b_cnt + 1; | |
| 1653 | @(posedge siu_coverage_ifc.clk); | |
| 1654 | if (siu_coverage_ifc.niuoqdq === 1'b1 && siu_coverage_ifc.niubqdq === 1'b0) | |
| 1655 | niusiu_bqdq_al_b2b_cnt = niusiu_bqdq_al_b2b_cnt + 1; | |
| 1656 | @(posedge siu_coverage_ifc.clk); | |
| 1657 | if (siu_coverage_ifc.niubqdq === 1'b1 && siu_coverage_ifc.niuoqdq === 1'b0) | |
| 1658 | niusiu_bqdq_al_b2b_cnt = niusiu_bqdq_al_b2b_cnt + 1; | |
| 1659 | if (niusiu_bqdq_al_b2b_cnt === 'd5) | |
| 1660 | trigger (niureq_bqdq_al_evnt_trig); | |
| 1661 | } | |
| 1662 | else | |
| 1663 | niusiu_bqdq_al_b2b_cnt = 0; | |
| 1664 | } | |
| 1665 | } | |
| 1666 | join none | |
| 1667 | ||
| 1668 | ||
| 1669 | fork | |
| 1670 | { | |
| 1671 | while(1) | |
| 1672 | { | |
| 1673 | @(posedge siu_coverage_ifc.clk); | |
| 1674 | if (niusiu_bqdq_que_b2b_cnt === 'd15) | |
| 1675 | { | |
| 1676 | ||
| 1677 | if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b1 && siu_coverage_ifc.niubqdq === 1'b0 && siu_coverage_ifc.niuoqdq === 1'b0 ) | |
| 1678 | niusiu_bqdq_que_b2b_cnt = 1; | |
| 1679 | else | |
| 1680 | niusiu_bqdq_que_b2b_cnt = 0; | |
| 1681 | } | |
| 1682 | else if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b1 && siu_coverage_ifc.niubqdq === 1'b0 && siu_coverage_ifc.niuoqdq === 1'b0 ) | |
| 1683 | { | |
| 1684 | niusiu_bqdq_que_b2b_cnt = niusiu_bqdq_que_b2b_cnt + 1; | |
| 1685 | if (niusiu_bqdq_que_b2b_cnt >= 11) | |
| 1686 | trigger (niureq_bqdq_que_evnt_trig); | |
| 1687 | } | |
| 1688 | else | |
| 1689 | niusiu_bqdq_que_b2b_cnt = 0; | |
| 1690 | } | |
| 1691 | } | |
| 1692 | join none | |
| 1693 | ||
| 1694 | fork | |
| 1695 | { | |
| 1696 | while(1) | |
| 1697 | { | |
| 1698 | @(posedge siu_coverage_ifc.clk); | |
| 1699 | if (niusiu_bqdq_que_b2b_wri_nonpost_cnt === 'd15) | |
| 1700 | { | |
| 1701 | ||
| 1702 | if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b0 && siu_coverage_ifc.niudata[125] === 1'b0 && siu_coverage_ifc.niubqdq === 1'b0 && siu_coverage_ifc.niuoqdq === 1'b0 ) | |
| 1703 | niusiu_bqdq_que_b2b_wri_nonpost_cnt = 1; | |
| 1704 | else | |
| 1705 | niusiu_bqdq_que_b2b_wri_nonpost_cnt = 0; | |
| 1706 | } | |
| 1707 | else if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b0 && siu_coverage_ifc.niudata[125] === 1'b0 && siu_coverage_ifc.niubqdq === 1'b0 && siu_coverage_ifc.niuoqdq === 1'b0 ) | |
| 1708 | { | |
| 1709 | niusiu_bqdq_que_b2b_wri_nonpost_cnt = niusiu_bqdq_que_b2b_wri_nonpost_cnt + 1; | |
| 1710 | if (niusiu_bqdq_que_b2b_wri_nonpost_cnt >= 11) | |
| 1711 | trigger (niureq_bqdq_wri_nonpost_que_evnt_trig); | |
| 1712 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 1713 | } | |
| 1714 | else | |
| 1715 | niusiu_bqdq_que_b2b_wri_nonpost_cnt = 0; | |
| 1716 | } | |
| 1717 | } | |
| 1718 | join none | |
| 1719 | ||
| 1720 | fork | |
| 1721 | { | |
| 1722 | while(1) | |
| 1723 | { | |
| 1724 | @(posedge siu_coverage_ifc.clk); | |
| 1725 | if (niusiu_bqdq_que_b2b_wri_post_cnt === 'd15) | |
| 1726 | { | |
| 1727 | ||
| 1728 | if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b0 && siu_coverage_ifc.niubqdq === 1'b0 && siu_coverage_ifc.niuoqdq === 1'b0 ) | |
| 1729 | niusiu_bqdq_que_b2b_wri_post_cnt = 1; | |
| 1730 | else | |
| 1731 | niusiu_bqdq_que_b2b_wri_post_cnt = 0; | |
| 1732 | } | |
| 1733 | else if (siu_coverage_ifc.niureq === 1'b1 && siu_coverage_ifc.niudata[127] === 1'b0 && siu_coverage_ifc.niudata[126] === 1'b1 && siu_coverage_ifc.niudata[125] === 1'b0 && siu_coverage_ifc.niubqdq === 1'b0 && siu_coverage_ifc.niuoqdq === 1'b0 ) | |
| 1734 | { | |
| 1735 | niusiu_bqdq_que_b2b_wri_post_cnt = niusiu_bqdq_que_b2b_wri_post_cnt + 1; | |
| 1736 | if (niusiu_bqdq_que_b2b_wri_post_cnt >= 11) | |
| 1737 | trigger (niureq_bqdq_wri_post_que_evnt_trig); | |
| 1738 | repeat (4) @(posedge siu_coverage_ifc.clk); | |
| 1739 | } | |
| 1740 | else | |
| 1741 | niusiu_bqdq_que_b2b_wri_post_cnt = 0; | |
| 1742 | } | |
| 1743 | } | |
| 1744 | join none | |
| 1745 | ||
| 1746 | fork | |
| 1747 | { | |
| 1748 | while (1) | |
| 1749 | { | |
| 1750 | @(posedge siu_coverage_ifc.clk); | |
| 1751 | if ( siu_coverage_ifc.ncu_req === 1'b1 ) | |
| 1752 | @(posedge siu_coverage_ifc.clk); | |
| 1753 | trigger (ncu_gnt_req_evnt_trig); | |
| 1754 | } | |
| 1755 | } | |
| 1756 | join none | |
| 1757 | ||
| 1758 | fork | |
| 1759 | { | |
| 1760 | while (1) | |
| 1761 | { | |
| 1762 | @(posedge siu_coverage_ifc.clk); | |
| 1763 | if ( siu_coverage_ifc.ncu_req === 1'b1 ) | |
| 1764 | repeat (2) @(posedge siu_coverage_ifc.clk); | |
| 1765 | trigger (ncu_gnt_req_del_evnt_trig); | |
| 1766 | } | |
| 1767 | } | |
| 1768 | join none | |
| 1769 | ||
| 1770 | fork | |
| 1771 | { | |
| 1772 | while (1) | |
| 1773 | { | |
| 1774 | @(posedge siu_coverage_ifc.clk); | |
| 1775 | if ( siu_coverage_ifc.ncu_req === 1'b1 ) | |
| 1776 | { | |
| 1777 | siu_ncu_last_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 1778 | @(posedge siu_coverage_ifc.ncu_gnt); | |
| 1779 | siu_ncu_this_cmd_cycle = get_cycle(siu_coverage_ifc.clk); | |
| 1780 | siu_ncu_gnt_req = siu_ncu_this_cmd_cycle - siu_ncu_last_cmd_cycle; | |
| 1781 | if (siu_ncu_gnt_req == 10) { | |
| 1782 | trigger (ncu_gnt_req_del_10_evnt_trig); | |
| 1783 | } | |
| 1784 | else siu_ncu_gnt_req = 0; | |
| 1785 | } | |
| 1786 | } | |
| 1787 | } | |
| 1788 | join none | |
| 1789 | ||
| 1790 | ||
| 1791 | fork | |
| 1792 | { | |
| 1793 | while (1) | |
| 1794 | { | |
| 1795 | @(posedge siu_coverage_ifc.clk); | |
| 1796 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1797 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1798 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1799 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1800 | partial_mode = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1801 | if ( siu_coverage_ifc.ncu_pm === 1'b1 ) | |
| 1802 | trigger (ncu_pm_1_evnt_trig); | |
| 1803 | } | |
| 1804 | } | |
| 1805 | join none | |
| 1806 | ||
| 1807 | fork | |
| 1808 | { | |
| 1809 | while (1) | |
| 1810 | { | |
| 1811 | @(posedge siu_coverage_ifc.clk); | |
| 1812 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1813 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1814 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1815 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1816 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1817 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1818 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1819 | dmu_data_876 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1820 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1821 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0001 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1822 | trigger (ncu_pm1_1_evnt_trig); | |
| 1823 | } | |
| 1824 | } | |
| 1825 | join none | |
| 1826 | ||
| 1827 | fork | |
| 1828 | { | |
| 1829 | while (1) | |
| 1830 | { | |
| 1831 | @(posedge siu_coverage_ifc.clk); | |
| 1832 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1833 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1834 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1835 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1836 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1837 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1838 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1839 | dmu_data_876_2 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1840 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1841 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0010 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1842 | trigger (ncu_pm1_2_evnt_trig); | |
| 1843 | } | |
| 1844 | } | |
| 1845 | join none | |
| 1846 | ||
| 1847 | fork | |
| 1848 | { | |
| 1849 | while (1) | |
| 1850 | { | |
| 1851 | @(posedge siu_coverage_ifc.clk); | |
| 1852 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1853 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1854 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1855 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1856 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1857 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1858 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1859 | dmu_data_876_3 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1860 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1861 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0011 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1862 | trigger (ncu_pm1_3_evnt_trig); | |
| 1863 | } | |
| 1864 | } | |
| 1865 | join none | |
| 1866 | ||
| 1867 | fork | |
| 1868 | { | |
| 1869 | while (1) | |
| 1870 | { | |
| 1871 | @(posedge siu_coverage_ifc.clk); | |
| 1872 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1873 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1874 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1875 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1876 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1877 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1878 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1879 | dmu_data_876_4 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1880 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1881 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0100 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1882 | trigger (ncu_pm1_4_evnt_trig); | |
| 1883 | } | |
| 1884 | } | |
| 1885 | join none | |
| 1886 | ||
| 1887 | fork | |
| 1888 | { | |
| 1889 | while (1) | |
| 1890 | { | |
| 1891 | @(posedge siu_coverage_ifc.clk); | |
| 1892 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1893 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1894 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1895 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1896 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1897 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1898 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1899 | dmu_data_876_5 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1900 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1901 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0101 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1902 | trigger (ncu_pm1_5_evnt_trig); | |
| 1903 | } | |
| 1904 | } | |
| 1905 | join none | |
| 1906 | ||
| 1907 | fork | |
| 1908 | { | |
| 1909 | while (1) | |
| 1910 | { | |
| 1911 | @(posedge siu_coverage_ifc.clk); | |
| 1912 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1913 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1914 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1915 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1916 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1917 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1918 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1919 | dmu_data_876_6 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1920 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1921 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0110 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1922 | trigger (ncu_pm1_6_evnt_trig); | |
| 1923 | } | |
| 1924 | } | |
| 1925 | join none | |
| 1926 | ||
| 1927 | fork | |
| 1928 | { | |
| 1929 | while (1) | |
| 1930 | { | |
| 1931 | @(posedge siu_coverage_ifc.clk); | |
| 1932 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1933 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1934 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1935 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1936 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1937 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1938 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1939 | dmu_data_876_7 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1940 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1941 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1000 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1942 | trigger (ncu_pm1_7_evnt_trig); | |
| 1943 | } | |
| 1944 | } | |
| 1945 | join none | |
| 1946 | ||
| 1947 | fork | |
| 1948 | { | |
| 1949 | while (1) | |
| 1950 | { | |
| 1951 | @(posedge siu_coverage_ifc.clk); | |
| 1952 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1953 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1954 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1955 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1956 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1957 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1958 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1959 | dmu_data_876_8 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1960 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1961 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1001 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1962 | trigger (ncu_pm1_8_evnt_trig); | |
| 1963 | } | |
| 1964 | } | |
| 1965 | join none | |
| 1966 | ||
| 1967 | fork | |
| 1968 | { | |
| 1969 | while (1) | |
| 1970 | { | |
| 1971 | @(posedge siu_coverage_ifc.clk); | |
| 1972 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1973 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1974 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1975 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1976 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1977 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1978 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1979 | dmu_data_876_9 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 1980 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 1981 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1010 && siu_coverage_ifc.dmureq === 1'b1) | |
| 1982 | trigger (ncu_pm1_9_evnt_trig); | |
| 1983 | } | |
| 1984 | } | |
| 1985 | join none | |
| 1986 | ||
| 1987 | fork | |
| 1988 | { | |
| 1989 | while (1) | |
| 1990 | { | |
| 1991 | @(posedge siu_coverage_ifc.clk); | |
| 1992 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 1993 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 1994 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 1995 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 1996 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 1997 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 1998 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 1999 | dmu_data_876_10 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 2000 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2001 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1100 && siu_coverage_ifc.dmureq === 1'b1) | |
| 2002 | trigger (ncu_pm1_10_evnt_trig); | |
| 2003 | } | |
| 2004 | } | |
| 2005 | join none | |
| 2006 | ||
| 2007 | fork | |
| 2008 | { | |
| 2009 | while (1) | |
| 2010 | { | |
| 2011 | @(posedge siu_coverage_ifc.clk); | |
| 2012 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2013 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2014 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2015 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2016 | dmu_data_6 = siu_coverage_ifc.dmudata[6]; | |
| 2017 | dmu_data_7 = siu_coverage_ifc.dmudata[7]; | |
| 2018 | dmu_data_8 = siu_coverage_ifc.dmudata[8]; | |
| 2019 | dmu_data_876_11 = {dmu_data_8,dmu_data_7,dmu_data_6}; | |
| 2020 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2021 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1111 && siu_coverage_ifc.dmureq === 1'b1) | |
| 2022 | trigger (ncu_pm1_11_evnt_trig); | |
| 2023 | } | |
| 2024 | } | |
| 2025 | join none | |
| 2026 | ||
| 2027 | fork | |
| 2028 | { | |
| 2029 | while (1) | |
| 2030 | { | |
| 2031 | @(posedge siu_coverage_ifc.clk); | |
| 2032 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2033 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2034 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2035 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2036 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2037 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2038 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2039 | niu_data_876 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2040 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2041 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0001 && siu_coverage_ifc.niureq === 1'b1) | |
| 2042 | trigger (ncu_pm1_niu_1_evnt_trig); | |
| 2043 | } | |
| 2044 | } | |
| 2045 | join none | |
| 2046 | ||
| 2047 | fork | |
| 2048 | { | |
| 2049 | while (1) | |
| 2050 | { | |
| 2051 | @(posedge siu_coverage_ifc.clk); | |
| 2052 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2053 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2054 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2055 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2056 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2057 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2058 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2059 | niu_data_876_2 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2060 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2061 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0010 && siu_coverage_ifc.niureq === 1'b1) | |
| 2062 | trigger (ncu_pm1_niu_2_evnt_trig); | |
| 2063 | } | |
| 2064 | } | |
| 2065 | join none | |
| 2066 | ||
| 2067 | fork | |
| 2068 | { | |
| 2069 | while (1) | |
| 2070 | { | |
| 2071 | @(posedge siu_coverage_ifc.clk); | |
| 2072 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2073 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2074 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2075 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2076 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2077 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2078 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2079 | niu_data_876_3 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2080 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2081 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0011 && siu_coverage_ifc.niureq === 1'b1) | |
| 2082 | trigger (ncu_pm1_niu_3_evnt_trig); | |
| 2083 | } | |
| 2084 | } | |
| 2085 | join none | |
| 2086 | ||
| 2087 | fork | |
| 2088 | { | |
| 2089 | while (1) | |
| 2090 | { | |
| 2091 | @(posedge siu_coverage_ifc.clk); | |
| 2092 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2093 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2094 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2095 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2096 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2097 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2098 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2099 | niu_data_876_4 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2100 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2101 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0100 && siu_coverage_ifc.niureq === 1'b1) | |
| 2102 | trigger (ncu_pm1_niu_4_evnt_trig); | |
| 2103 | } | |
| 2104 | } | |
| 2105 | join none | |
| 2106 | ||
| 2107 | fork | |
| 2108 | { | |
| 2109 | while (1) | |
| 2110 | { | |
| 2111 | @(posedge siu_coverage_ifc.clk); | |
| 2112 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2113 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2114 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2115 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2116 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2117 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2118 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2119 | niu_data_876_5 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2120 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2121 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0101 && siu_coverage_ifc.niureq === 1'b1) | |
| 2122 | trigger (ncu_pm1_niu_5_evnt_trig); | |
| 2123 | } | |
| 2124 | } | |
| 2125 | join none | |
| 2126 | ||
| 2127 | fork | |
| 2128 | { | |
| 2129 | while (1) | |
| 2130 | { | |
| 2131 | @(posedge siu_coverage_ifc.clk); | |
| 2132 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2133 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2134 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2135 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2136 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2137 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2138 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2139 | niu_data_876_6 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2140 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2141 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b0110 && siu_coverage_ifc.niureq === 1'b1) | |
| 2142 | trigger (ncu_pm1_niu_6_evnt_trig); | |
| 2143 | } | |
| 2144 | } | |
| 2145 | join none | |
| 2146 | ||
| 2147 | fork | |
| 2148 | { | |
| 2149 | while (1) | |
| 2150 | { | |
| 2151 | @(posedge siu_coverage_ifc.clk); | |
| 2152 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2153 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2154 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2155 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2156 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2157 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2158 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2159 | niu_data_876_7 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2160 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2161 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1000 && siu_coverage_ifc.niureq === 1'b1) | |
| 2162 | trigger (ncu_pm1_niu_7_evnt_trig); | |
| 2163 | } | |
| 2164 | } | |
| 2165 | join none | |
| 2166 | ||
| 2167 | fork | |
| 2168 | { | |
| 2169 | while (1) | |
| 2170 | { | |
| 2171 | @(posedge siu_coverage_ifc.clk); | |
| 2172 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2173 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2174 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2175 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2176 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2177 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2178 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2179 | niu_data_876_8 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2180 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2181 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1001 && siu_coverage_ifc.niureq === 1'b1) | |
| 2182 | trigger (ncu_pm1_niu_8_evnt_trig); | |
| 2183 | } | |
| 2184 | } | |
| 2185 | join none | |
| 2186 | ||
| 2187 | fork | |
| 2188 | { | |
| 2189 | while (1) | |
| 2190 | { | |
| 2191 | @(posedge siu_coverage_ifc.clk); | |
| 2192 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2193 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2194 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2195 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2196 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2197 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2198 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2199 | niu_data_876_9 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2200 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2201 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1010 && siu_coverage_ifc.niureq === 1'b1) | |
| 2202 | trigger (ncu_pm1_niu_9_evnt_trig); | |
| 2203 | } | |
| 2204 | } | |
| 2205 | join none | |
| 2206 | ||
| 2207 | fork | |
| 2208 | { | |
| 2209 | while (1) | |
| 2210 | { | |
| 2211 | @(posedge siu_coverage_ifc.clk); | |
| 2212 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2213 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2214 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2215 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2216 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2217 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2218 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2219 | niu_data_876_10 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2220 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2221 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1100 && siu_coverage_ifc.niureq === 1'b1) | |
| 2222 | trigger (ncu_pm1_niu_10_evnt_trig); | |
| 2223 | } | |
| 2224 | } | |
| 2225 | join none | |
| 2226 | ||
| 2227 | fork | |
| 2228 | { | |
| 2229 | while (1) | |
| 2230 | { | |
| 2231 | @(posedge siu_coverage_ifc.clk); | |
| 2232 | ncu_ba01 = siu_coverage_ifc.ncu_ba01; | |
| 2233 | ncu_ba23 = siu_coverage_ifc.ncu_ba23; | |
| 2234 | ncu_ba45 = siu_coverage_ifc.ncu_ba45; | |
| 2235 | ncu_ba67 = siu_coverage_ifc.ncu_ba67; | |
| 2236 | niu_data_6 = siu_coverage_ifc.niudata[6]; | |
| 2237 | niu_data_7 = siu_coverage_ifc.niudata[7]; | |
| 2238 | niu_data_8 = siu_coverage_ifc.niudata[8]; | |
| 2239 | niu_data_876_11 = {niu_data_8,niu_data_7,niu_data_6}; | |
| 2240 | partial_mode1 = {ncu_ba67,ncu_ba45,ncu_ba23,ncu_ba01}; | |
| 2241 | if ( siu_coverage_ifc.ncu_pm === 1'b1 && partial_mode1 === 4'b1111 && siu_coverage_ifc.niureq === 1'b1) | |
| 2242 | trigger (ncu_pm1_niu_11_evnt_trig); | |
| 2243 | } | |
| 2244 | } | |
| 2245 | join none | |
| 2246 | ||
| 2247 | fork | |
| 2248 | { | |
| 2249 | while (1) | |
| 2250 | { | |
| 2251 | @(posedge siu_coverage_ifc.clk); | |
| 2252 | if ( siu_coverage_ifc.niureq === 1'b1 ) | |
| 2253 | trigger (niureq_evnt_trig); | |
| 2254 | } | |
| 2255 | } | |
| 2256 | join none | |
| 2257 | ||
| 2258 | fork | |
| 2259 | { | |
| 2260 | while (1) | |
| 2261 | { | |
| 2262 | @(posedge siu_coverage_ifc.clk); | |
| 2263 | if ( siu_coverage_ifc.dmureq === 1'b1 ) | |
| 2264 | trigger (dmureq_evnt_trig); | |
| 2265 | } | |
| 2266 | } | |
| 2267 | join none | |
| 2268 | ||
| 2269 | fork | |
| 2270 | . for ($bank=0; $bank<8; $bank++) | |
| 2271 | . { | |
| 2272 | { | |
| 2273 | while (1) | |
| 2274 | { | |
| 2275 | @(posedge siu_coverage_ifc_l2.clk); | |
| 2276 | if ( siu_coverage_ifc_l2.sii_l2t${bank} === 1'b1 ) | |
| 2277 | trigger (l2${bank}req_evnt_trig); | |
| 2278 | } | |
| 2279 | } | |
| 2280 | . } | |
| 2281 | join none | |
| 2282 | ||
| 2283 | } // siu_intf_schmoo_coverage set_cov_cond_bits | |
| 2284 | ||
| 2285 | ||
| 2286 | //////////////////////////////////////////////////////////////////////// | |
| 2287 | // sii internal coverage objects | |
| 2288 | //////////////////////////////////////////////////////////////////////// | |
| 2289 | class siu_ipcs_coverage | |
| 2290 | { | |
| 2291 | StandardDisplay dbg; | |
| 2292 | local string myname; | |
| 2293 | ||
| 2294 | bit siu_ipcs_cov_debug = 1'b0; | |
| 2295 | ||
| 2296 | event ipcc_err_det_trig; | |
| 2297 | event ipcc_ecc_err_trig; | |
| 2298 | ||
| 2299 | // siu wb coverage | |
| 2300 | . for ($q=0; $q<2; $q++) | |
| 2301 | . { | |
| 2302 | // sii | |
| 2303 | bit [3:0] ipdohq${q}_wr_adr = 4'b0; | |
| 2304 | bit [3:0] ipdbhq${q}_wr_adr = 4'b0; | |
| 2305 | bit [3:0] ipdohq${q}_rd_adr = 4'b0; | |
| 2306 | bit [3:0] ipdbhq${q}_rd_adr = 4'b0; | |
| 2307 | bit [5:0] ipdodq${q}_wr_adr = 6'b0; | |
| 2308 | bit [5:0] ipdbdq${q}_wr_adr = 6'b0; | |
| 2309 | bit [5:0] ipdodq${q}_rd_adr = 6'b0; | |
| 2310 | bit [5:0] ipdbdq${q}_rd_adr = 6'b0; | |
| 2311 | ||
| 2312 | integer ipdohq${q}_size = 0; | |
| 2313 | integer ipdbhq${q}_size = 0; | |
| 2314 | integer ipdodq${q}_size = 0; | |
| 2315 | integer ipdbdq${q}_size = 0; | |
| 2316 | integer ipdoq${q}_d_wr_b2b = 0; | |
| 2317 | integer ipdbq${q}_d_wr_b2b = 0; | |
| 2318 | integer ipdoq${q}_d_rd_b2b = 0; | |
| 2319 | integer ipdbq${q}_d_rd_b2b = 0; | |
| 2320 | ||
| 2321 | event ipcc_ipcs${q}_orgo_evnt_trig; | |
| 2322 | event ipcc_ipcs${q}_bygo_evnt_trig; | |
| 2323 | ||
| 2324 | . } | |
| 2325 | ||
| 2326 | . for ($q=0; $q<8; $q++) | |
| 2327 | . { | |
| 2328 | bit [4:0] ildq${q}_rd_adr = 5'b0; | |
| 2329 | bit [4:0] ildq${q}_wr_adr = 5'b0; | |
| 2330 | integer ildq${q}_wr_b2b = 0; | |
| 2331 | integer ildq${q}_rd_b2b = 0; | |
| 2332 | integer ildq${q}_size = 0; | |
| 2333 | .} | |
| 2334 | ||
| 2335 | bit [5:0] indq_rd_adr = 6'b0; | |
| 2336 | bit [5:0] indq_wr_adr = 6'b0; | |
| 2337 | integer indq_wr_b2b = 0; | |
| 2338 | integer indq_rd_b2b = 0; | |
| 2339 | integer indq_size = 0; | |
| 2340 | ||
| 2341 | bit [4:0] dmu_or_cnt_r = 5'b0; | |
| 2342 | bit [4:0] dmu_by_cnt_r = 5'b0; | |
| 2343 | bit [4:0] niu_or_cnt_r = 5'b0; | |
| 2344 | bit [4:0] niu_by_cnt_r = 5'b0; | |
| 2345 | bit [2:0] sio_cnt_r = 2'b0; | |
| 2346 | bit [3:0] dmu_wrm_cnt_r = 4'b0; | |
| 2347 | bit [2:0] wrm_cnt_r = 3'b0; | |
| 2348 | ||
| 2349 | event ipcc_arb_evnt_trig; | |
| 2350 | ||
| 2351 | #ifndef SIU_WB_COV | |
| 2352 | ////// indq ////// | |
| 2353 | coverage_group indq_wr_cov | |
| 2354 | { | |
| 2355 | sample_event = wait_var(indq_wr_adr); | |
| 2356 | #include "siu_indq_wr_sample.vrh" | |
| 2357 | } | |
| 2358 | coverage_group indq_rd_cov | |
| 2359 | { | |
| 2360 | sample_event = wait_var(indq_rd_adr); | |
| 2361 | #include "siu_indq_rd_sample.vrh" | |
| 2362 | } | |
| 2363 | ||
| 2364 | ////// ildq ////// | |
| 2365 | . for ($q=0; $q<8; $q++) | |
| 2366 | . { | |
| 2367 | coverage_group ildq${q}_wr_cov | |
| 2368 | { | |
| 2369 | sample_event = wait_var(ildq${q}_wr_adr); | |
| 2370 | #include "siu_ildq${q}_wr_sample.vrh" | |
| 2371 | } | |
| 2372 | coverage_group ildq${q}_rd_cov | |
| 2373 | { | |
| 2374 | sample_event = wait_var(ildq${q}_rd_adr); | |
| 2375 | #include "siu_ildq${q}_rd_sample.vrh" | |
| 2376 | } | |
| 2377 | . } | |
| 2378 | #endif // not in siu_wb_cov | |
| 2379 | ||
| 2380 | ////// ipd(o,b)hq(0,1) | |
| 2381 | . for ($q=0; $q<2; $q++) | |
| 2382 | . { | |
| 2383 | // header queue = ${q} | |
| 2384 | coverage_group ipdohq${q}_wr_cov | |
| 2385 | { | |
| 2386 | sample_event = wait_var(ipdohq${q}_wr_adr); | |
| 2387 | #include "siu_ipdohq${q}_wr_sample.vrh" | |
| 2388 | } | |
| 2389 | coverage_group ipdbhq${q}_wr_cov | |
| 2390 | { | |
| 2391 | sample_event = wait_var(ipdbhq${q}_wr_adr); | |
| 2392 | #include "siu_ipdbhq${q}_wr_sample.vrh" | |
| 2393 | } | |
| 2394 | coverage_group ipdohq${q}_rd_cov | |
| 2395 | { | |
| 2396 | sample_event = wait_var(ipdohq${q}_rd_adr); | |
| 2397 | #include "siu_ipdohq${q}_rd_sample.vrh" | |
| 2398 | } | |
| 2399 | coverage_group ipdbhq${q}_rd_cov | |
| 2400 | { | |
| 2401 | sample_event = wait_var(ipdbhq${q}_rd_adr); | |
| 2402 | #include "siu_ipdbhq${q}_rd_sample.vrh" | |
| 2403 | } | |
| 2404 | ||
| 2405 | // data queue = ${q} | |
| 2406 | coverage_group ipdodq${q}_wr_cov | |
| 2407 | { | |
| 2408 | sample_event = wait_var(ipdodq${q}_wr_adr); | |
| 2409 | #include "siu_ipdodq${q}_wr_sample.vrh" | |
| 2410 | } | |
| 2411 | coverage_group ipdbdq${q}_wr_cov | |
| 2412 | { | |
| 2413 | sample_event = wait_var(ipdbdq${q}_wr_adr); | |
| 2414 | #include "siu_ipdbdq${q}_wr_sample.vrh" | |
| 2415 | } | |
| 2416 | coverage_group ipdodq${q}_rd_cov | |
| 2417 | { | |
| 2418 | sample_event = wait_var(ipdodq${q}_rd_adr); | |
| 2419 | #include "siu_ipdodq${q}_rd_sample.vrh" | |
| 2420 | } | |
| 2421 | coverage_group ipdbdq${q}_rd_cov | |
| 2422 | { | |
| 2423 | sample_event = wait_var(ipdbdq${q}_rd_adr); | |
| 2424 | #include "siu_ipdbdq${q}_rd_sample.vrh" | |
| 2425 | } | |
| 2426 | . } | |
| 2427 | ||
| 2428 | #ifndef SIU_WB_COV | |
| 2429 | ////// ipcc to ipcs ptr | |
| 2430 | . for ($q=0; $q<2; $q++) | |
| 2431 | . { | |
| 2432 | coverage_group ipcc_ipcs${q}_or_cov | |
| 2433 | { | |
| 2434 | sample_event = sync (ANY, ipcc_ipcs${q}_orgo_evnt_trig); | |
| 2435 | #include "siu_ipcc_ipcs${q}_or_sample.vrh" | |
| 2436 | } | |
| 2437 | coverage_group ipcc_ipcs${q}_by_cov | |
| 2438 | { | |
| 2439 | sample_event = sync (ANY, ipcc_ipcs${q}_bygo_evnt_trig); | |
| 2440 | #include "siu_ipcc_ipcs${q}_by_sample.vrh" | |
| 2441 | } | |
| 2442 | .} | |
| 2443 | ||
| 2444 | // ----------- coverage_group ---------------- | |
| 2445 | coverage_group check_cnt_dmu_or_cov | |
| 2446 | { | |
| 2447 | //sample_event = wait_var (dmu_or_cnt_r); | |
| 2448 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2449 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2450 | ||
| 2451 | #include "siu_check_cnt_dmu_or_sample.vrh" | |
| 2452 | } | |
| 2453 | ||
| 2454 | coverage_group check_cnt_dmu_by_cov | |
| 2455 | { | |
| 2456 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2457 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2458 | ||
| 2459 | #include "siu_check_cnt_dmu_by_sample.vrh" | |
| 2460 | } | |
| 2461 | ||
| 2462 | coverage_group check_cnt_niu_or_cov | |
| 2463 | { | |
| 2464 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2465 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2466 | ||
| 2467 | #include "siu_check_cnt_niu_or_sample.vrh" | |
| 2468 | } | |
| 2469 | ||
| 2470 | coverage_group check_cnt_niu_by_cov | |
| 2471 | { | |
| 2472 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2473 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2474 | ||
| 2475 | #include "siu_check_cnt_niu_by_sample.vrh" | |
| 2476 | } | |
| 2477 | ||
| 2478 | . for ($q=0; $q<8; $q++) | |
| 2479 | . { | |
| 2480 | coverage_group buffer_cnt_ilc${q} | |
| 2481 | { | |
| 2482 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2483 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2484 | ||
| 2485 | #include "siu_buff_cnt_ilc${q}_sample.vrh" | |
| 2486 | } | |
| 2487 | . } | |
| 2488 | ||
| 2489 | coverage_group siu_ipcc_wrm_cov | |
| 2490 | { | |
| 2491 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2492 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2493 | ||
| 2494 | #include "siu_ipcc_wrm_cnt_sample.vrh" | |
| 2495 | } | |
| 2496 | ||
| 2497 | . for ($q=0; $q<8; $q++) | |
| 2498 | . { | |
| 2499 | coverage_group siu_ilc${q}_wrm_cov | |
| 2500 | { | |
| 2501 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2502 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2503 | ||
| 2504 | #include "siu_ilc${q}_wrm_cnt_sample.vrh" | |
| 2505 | } | |
| 2506 | . } | |
| 2507 | #endif // not in siu_wb_cov | |
| 2508 | ||
| 2509 | coverage_group siu_order_rule_match0 | |
| 2510 | { | |
| 2511 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2512 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2513 | ||
| 2514 | #include "siu_ipcs0_match.vrh" | |
| 2515 | } | |
| 2516 | ||
| 2517 | ||
| 2518 | coverage_group siu_order_rule_match1 | |
| 2519 | { | |
| 2520 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2521 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2522 | ||
| 2523 | #include "siu_ipcs1_match.vrh" | |
| 2524 | } | |
| 2525 | ||
| 2526 | ||
| 2527 | coverage_group siu_order_rule_dep0 | |
| 2528 | { | |
| 2529 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2530 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2531 | ||
| 2532 | #include "siu_ipcs0_dep.vrh" | |
| 2533 | } | |
| 2534 | ||
| 2535 | coverage_group siu_order_rule_dep1 | |
| 2536 | { | |
| 2537 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2538 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2539 | ||
| 2540 | #include "siu_ipcs1_dep.vrh" | |
| 2541 | } | |
| 2542 | ||
| 2543 | #ifndef SIU_WB_COV | |
| 2544 | coverage_group siu_order_rule_niu | |
| 2545 | { | |
| 2546 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2547 | sample order_chk.siu_RDDord_pass_niuord_diffbank, | |
| 2548 | order_chk.siu_RDDord_not_pass_niuord_samebank, | |
| 2549 | order_chk.siu_WRIord_not_pass_niuord, | |
| 2550 | order_chk.siu_niubyp_pass_niubyp_diffbank, | |
| 2551 | order_chk.siu_niubyp_not_pass_niubyp_samebank, | |
| 2552 | order_chk.siu_niubyp_pass_niuord_diffbank, | |
| 2553 | order_chk.siu_RDDbyp_pass_RDDord_samebank, | |
| 2554 | order_chk.siu_WRIbyp_not_pass_niuord_samebank; | |
| 2555 | } | |
| 2556 | ||
| 2557 | . for ($q=0; $q<8; $q++) | |
| 2558 | . { | |
| 2559 | coverage_group siu_state_ilc${q} | |
| 2560 | { | |
| 2561 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2562 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2563 | ||
| 2564 | #include "siu_ilc${q}_state.vrh" | |
| 2565 | } | |
| 2566 | . } | |
| 2567 | ||
| 2568 | coverage_group siu_state_ipcc | |
| 2569 | { | |
| 2570 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2571 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2572 | ||
| 2573 | #include "siu_ipcc_state.vrh" | |
| 2574 | } | |
| 2575 | ||
| 2576 | coverage_group siu_state_inc | |
| 2577 | { | |
| 2578 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2579 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2580 | ||
| 2581 | #include "siu_inc_state.vrh" | |
| 2582 | } | |
| 2583 | ||
| 2584 | . for ($q=0; $q<2; $q++) | |
| 2585 | . { | |
| 2586 | coverage_group siu_state_ipcs${q} | |
| 2587 | { | |
| 2588 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 2589 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 2590 | ||
| 2591 | #include "siu_ipcs${q}_state.vrh" | |
| 2592 | } | |
| 2593 | . } | |
| 2594 | ||
| 2595 | ||
| 2596 | coverage_group ipcc_arb_cov | |
| 2597 | { | |
| 2598 | sample_event = sync (ANY, ipcc_arb_evnt_trig); | |
| 2599 | sample siu_coverage_ipcc_arb.niu_by_go, siu_coverage_ipcc_arb.niu_or_go, | |
| 2600 | siu_coverage_ipcc_arb.dmu_by_go, siu_coverage_ipcc_arb.dmu_or_go; | |
| 2601 | cross siu_ipcc_cross_arb ( | |
| 2602 | siu_coverage_ipcc_arb.niu_by_go, siu_coverage_ipcc_arb.niu_or_go, | |
| 2603 | siu_coverage_ipcc_arb.dmu_by_go, siu_coverage_ipcc_arb.dmu_or_go) | |
| 2604 | { | |
| 2605 | ignored IgnoreIpccarb (siu_coverage_ipcc_arb.niu_by_go == 0 && siu_coverage_ipcc_arb.niu_or_go == 0 && siu_coverage_ipcc_arb.dmu_by_go == 0 && siu_coverage_ipcc_arb.dmu_or_go == 0); | |
| 2606 | } | |
| 2607 | } | |
| 2608 | ||
| 2609 | #endif // not in siu_wb_cov | |
| 2610 | ||
| 2611 | ////// RAS coverage for sii side | |
| 2612 | ||
| 2613 | coverage_group sii_io_err_det_cov | |
| 2614 | { | |
| 2615 | //sample_event = sync (ANY, ipcc_err_det_trig); | |
| 2616 | sample_event = @(posedge siu_coverage_err_det.clk); | |
| 2617 | sample siu_coverage_err_det.cp_err, siu_coverage_err_det.ap_err, | |
| 2618 | siu_coverage_err_det.dp_err, siu_coverage_err_det.cecc_ce, | |
| 2619 | siu_coverage_err_det.cecc_ue; | |
| 2620 | cross siu_sii_err_cross_cov ( | |
| 2621 | siu_coverage_err_det.cp_err, siu_coverage_err_det.ap_err, | |
| 2622 | siu_coverage_err_det.cecc_ce) | |
| 2623 | { | |
| 2624 | ignored IgnoreErr (siu_coverage_err_det.ap_err == 0 && siu_coverage_err_det.cp_err == 0 && siu_coverage_err_det.cecc_ce == 0); | |
| 2625 | } | |
| 2626 | } | |
| 2627 | coverage_group sii_ecc_err_cov | |
| 2628 | { | |
| 2629 | //sample_event = sync (ANY, ipcc_ecc_err_trig); | |
| 2630 | sample_event = @(siu_coverage_err_det.id or siu_coverage_err_det.c); | |
| 2631 | sample siu_coverage_err_det.e | |
| 2632 | { | |
| 2633 | state s_CE (0:63) if ((siu_coverage_err_det.e[4:0] < 5'b10110) && (siu_coverage_err_det.e[5] === 1'b1)); | |
| 2634 | state s_NO_ERR (0:63) if (siu_coverage_err_det.e === 6'b000000); | |
| 2635 | state s_UE (0:63) if ((siu_coverage_err_det.e[4:0] !== 5'b00000) && ((siu_coverage_err_det.e[5] === 1'b0) || (siu_coverage_err_det.e[4:0] > 5'b10101))); | |
| 2636 | } | |
| 2637 | } | |
| 2638 | coverage_group sii_ebit_cov | |
| 2639 | { | |
| 2640 | sample_event = @(negedge siu_coverage_ifc.ncu_gnt); | |
| 2641 | sample siu_coverage_err_det.ebits_piortn | |
| 2642 | { | |
| 2643 | state s_0 (4'b0001); | |
| 2644 | state s_1 (4'b0010); | |
| 2645 | state s_2 (4'b0100); | |
| 2646 | state s_3 (4'b1000); | |
| 2647 | state s_4 (4'b1111); | |
| 2648 | } | |
| 2649 | } | |
| 2650 | coverage_group sii_syndrom_cov | |
| 2651 | { | |
| 2652 | sample_event = @(siu_coverage_err_det.sending_r or siu_ipcc_state_machine.cstate); | |
| 2653 | sample siu_coverage_err_det.err_sig_l | |
| 2654 | { | |
| 2655 | state s_niud_pe (0:63) if (siu_coverage_err_det.err_sig_l[5] === 1'b1); | |
| 2656 | state s_niua_pe (0:63) if (siu_coverage_err_det.err_sig_l[4] === 1'b1); | |
| 2657 | state s_niuctag_ue (0:63) if (siu_coverage_err_det.err_sig_l[3] === 1'b1); | |
| 2658 | state s_dmud_pe (0:63) if (siu_coverage_err_det.err_sig_l[2] === 1'b1); | |
| 2659 | state s_dmua_pe (0:63) if (siu_coverage_err_det.err_sig_l[1] === 1'b1); | |
| 2660 | state s_dmuctag_ue (0:63) if (siu_coverage_err_det.err_sig_l[0] === 1'b1); | |
| 2661 | } | |
| 2662 | } | |
| 2663 | // RAS_COVERAGE sii side | |
| 2664 | ||
| 2665 | ||
| 2666 | task new(StandardDisplay dbg); | |
| 2667 | task set_cov_cond_bits (); | |
| 2668 | ||
| 2669 | } // class siu_ipcs_coverage | |
| 2670 | ||
| 2671 | ////// siu_ipcs_coverage class | |
| 2672 | task siu_ipcs_coverage::new(StandardDisplay dbg) | |
| 2673 | { | |
| 2674 | bit coverage_on; | |
| 2675 | ||
| 2676 | myname = "siu_ipcs_coverage"; | |
| 2677 | this.dbg = dbg; | |
| 2678 | ||
| 2679 | if (mChkPlusarg(siu_ipcs_coverage) || mChkPlusarg(coverage_on)) { | |
| 2680 | coverage_on = 1; | |
| 2681 | if (mChkPlusarg(siu_ipcs_cov_debug)) { | |
| 2682 | siu_ipcs_cov_debug = 1'b1; | |
| 2683 | } | |
| 2684 | } else { | |
| 2685 | coverage_on = 0; | |
| 2686 | } | |
| 2687 | ||
| 2688 | if (coverage_on) | |
| 2689 | { | |
| 2690 | // ipdohq0_wr_cov = new(); | |
| 2691 | ||
| 2692 | fork { | |
| 2693 | @(posedge siu_coverage_ipdoq0_rd.cmp_diag_done); | |
| 2694 | coverage_save_database(1); | |
| 2695 | } join none | |
| 2696 | ||
| 2697 | set_cov_cond_bits(); | |
| 2698 | } // coverage_on | |
| 2699 | } // ipcs_coverage new | |
| 2700 | ||
| 2701 | task siu_ipcs_coverage::set_cov_cond_bits() | |
| 2702 | { | |
| 2703 | fork | |
| 2704 | #ifndef SIU_WB_COV | |
| 2705 | ||
| 2706 | { | |
| 2707 | integer indq_wr_last_cycle = 0; | |
| 2708 | while(1) | |
| 2709 | { | |
| 2710 | integer indq_wr_this_cycle = 0; | |
| 2711 | @(posedge siu_coverage_indq.clk); | |
| 2712 | if (siu_coverage_indq.wr_en === 1'b1) | |
| 2713 | { | |
| 2714 | indq_size++; | |
| 2715 | ||
| 2716 | indq_wr_this_cycle = get_cycle(siu_coverage_indq.clk); | |
| 2717 | indq_wr_b2b = indq_wr_this_cycle - indq_wr_last_cycle; | |
| 2718 | indq_wr_last_cycle = indq_wr_this_cycle; | |
| 2719 | indq_wr_adr = siu_coverage_indq.wr_adr; | |
| 2720 | } | |
| 2721 | } | |
| 2722 | } | |
| 2723 | { | |
| 2724 | integer indq_rd_last_cycle = 0; | |
| 2725 | while(1) | |
| 2726 | { | |
| 2727 | integer indq_rd_this_cycle = 0; | |
| 2728 | @(posedge siu_coverage_indq.clk); | |
| 2729 | if (siu_coverage_indq.rd_adr !== indq_rd_adr && siu_coverage_indq.rd_en === 1'b1 ) | |
| 2730 | { | |
| 2731 | indq_size--; | |
| 2732 | indq_rd_this_cycle = get_cycle(siu_coverage_indq.clk); | |
| 2733 | indq_rd_b2b = indq_rd_this_cycle - indq_rd_last_cycle; | |
| 2734 | indq_rd_last_cycle = indq_rd_this_cycle; | |
| 2735 | indq_rd_adr = siu_coverage_indq.rd_adr; | |
| 2736 | } | |
| 2737 | } | |
| 2738 | } | |
| 2739 | ||
| 2740 | . for ($q=0; $q<8; $q++) | |
| 2741 | . { | |
| 2742 | { | |
| 2743 | integer ildq${q}_wr_last_cycle = 0; | |
| 2744 | while(1) | |
| 2745 | { | |
| 2746 | integer ildq${q}_wr_this_cycle = 0; | |
| 2747 | @(posedge siu_coverage_ildq${q}.clk); | |
| 2748 | if (siu_coverage_ildq${q}.wr_en === 1'b1) | |
| 2749 | { | |
| 2750 | ildq${q}_size++; | |
| 2751 | ||
| 2752 | ildq${q}_wr_this_cycle = get_cycle(siu_coverage_ildq${q}.clk); | |
| 2753 | ildq${q}_wr_b2b = ildq${q}_wr_this_cycle - ildq${q}_wr_last_cycle; | |
| 2754 | ildq${q}_wr_last_cycle = ildq${q}_wr_this_cycle; | |
| 2755 | ildq${q}_wr_adr = siu_coverage_ildq${q}.wr_adr; | |
| 2756 | } | |
| 2757 | } | |
| 2758 | } | |
| 2759 | { | |
| 2760 | integer ildq${q}_rd_last_cycle = 0; | |
| 2761 | while(1) | |
| 2762 | { | |
| 2763 | integer ildq${q}_rd_this_cycle = 0; | |
| 2764 | @(posedge siu_coverage_ildq${q}.clk); | |
| 2765 | if (siu_coverage_ildq${q}.rd_adr !== ildq${q}_rd_adr && siu_coverage_ildq${q}.rd_en === 1'b1 ) | |
| 2766 | { | |
| 2767 | ildq${q}_size--; | |
| 2768 | ildq${q}_rd_this_cycle = get_cycle(siu_coverage_ildq${q}.clk); | |
| 2769 | ildq${q}_rd_b2b = ildq${q}_rd_this_cycle - ildq${q}_rd_last_cycle; | |
| 2770 | ildq${q}_rd_last_cycle = ildq${q}_rd_this_cycle; | |
| 2771 | ildq${q}_rd_adr = siu_coverage_ildq${q}.rd_adr; | |
| 2772 | } | |
| 2773 | } | |
| 2774 | } | |
| 2775 | .} | |
| 2776 | ||
| 2777 | #endif // not in siu_wb_cov | |
| 2778 | ||
| 2779 | . for ($q=0; $q<2; $q++) | |
| 2780 | . { | |
| 2781 | { | |
| 2782 | while(1) | |
| 2783 | { | |
| 2784 | @(posedge siu_coverage_ipdoq${q}_wr.clk); | |
| 2785 | if (siu_coverage_ipdoq${q}_wr.h_en === 1'b1) | |
| 2786 | { | |
| 2787 | ipdohq${q}_size ++; | |
| 2788 | ipdohq${q}_wr_adr = siu_coverage_ipdoq${q}_wr.h_adr; | |
| 2789 | } | |
| 2790 | } | |
| 2791 | } | |
| 2792 | { | |
| 2793 | while(1) | |
| 2794 | { | |
| 2795 | @(posedge siu_coverage_ipdbq${q}_wr.clk); | |
| 2796 | if (siu_coverage_ipdbq${q}_wr.h_en === 1'b1) | |
| 2797 | { | |
| 2798 | ipdbhq${q}_size ++; | |
| 2799 | ipdbhq${q}_wr_adr = siu_coverage_ipdbq${q}_wr.h_adr; | |
| 2800 | } | |
| 2801 | } | |
| 2802 | } | |
| 2803 | { | |
| 2804 | while(1) | |
| 2805 | { | |
| 2806 | @(posedge siu_coverage_ipdoq${q}_rd.clk); | |
| 2807 | if (siu_coverage_ipdoq${q}_rd.h_adr !== ipdohq${q}_rd_adr && siu_coverage_ipdoq${q}_rd.h_en === 1'b1 ) | |
| 2808 | { | |
| 2809 | ipdohq${q}_size --; | |
| 2810 | ipdohq${q}_rd_adr = siu_coverage_ipdoq${q}_rd.h_adr; | |
| 2811 | } | |
| 2812 | } | |
| 2813 | } | |
| 2814 | { | |
| 2815 | while(1) | |
| 2816 | { | |
| 2817 | @(posedge siu_coverage_ipdbq${q}_rd.clk); | |
| 2818 | if (siu_coverage_ipdbq${q}_rd.h_adr !== ipdbhq${q}_rd_adr && siu_coverage_ipdbq${q}_rd.h_en === 1'b1) | |
| 2819 | { | |
| 2820 | ipdbhq${q}_size --; | |
| 2821 | ipdbhq${q}_rd_adr = siu_coverage_ipdbq${q}_rd.h_adr; | |
| 2822 | } | |
| 2823 | } | |
| 2824 | } | |
| 2825 | ||
| 2826 | { | |
| 2827 | integer ipdoq${q}_d_wr_last_cycle = 0; | |
| 2828 | while(1) | |
| 2829 | { | |
| 2830 | integer ipdoq${q}_d_wr_this_cycle; | |
| 2831 | @(posedge siu_coverage_ipdoq${q}_wr.clk); | |
| 2832 | if (siu_coverage_ipdoq${q}_wr.d_en === 1'b1) | |
| 2833 | { | |
| 2834 | ipdodq${q}_size ++; | |
| 2835 | ipdoq${q}_d_wr_this_cycle = get_cycle(siu_coverage_ipdoq${q}_wr.clk); | |
| 2836 | ipdoq${q}_d_wr_b2b = ipdoq${q}_d_wr_this_cycle - ipdoq${q}_d_wr_last_cycle; | |
| 2837 | ipdoq${q}_d_wr_last_cycle = ipdoq${q}_d_wr_this_cycle; | |
| 2838 | ipdodq${q}_wr_adr = siu_coverage_ipdoq${q}_wr.d_adr; | |
| 2839 | } | |
| 2840 | } | |
| 2841 | } | |
| 2842 | { | |
| 2843 | integer ipdbq${q}_d_wr_last_cycle = 0; | |
| 2844 | while(1) | |
| 2845 | { | |
| 2846 | integer ipdbq${q}_d_wr_this_cycle; | |
| 2847 | @(posedge siu_coverage_ipdbq${q}_wr.clk); | |
| 2848 | if (siu_coverage_ipdbq${q}_wr.d_en === 1'b1) | |
| 2849 | { | |
| 2850 | ipdbdq${q}_size ++; | |
| 2851 | ipdbq${q}_d_wr_this_cycle = get_cycle(siu_coverage_ipdbq${q}_wr.clk); | |
| 2852 | ipdbq${q}_d_wr_b2b = ipdbq${q}_d_wr_this_cycle - ipdbq${q}_d_wr_last_cycle; | |
| 2853 | ipdbq${q}_d_wr_last_cycle = ipdbq${q}_d_wr_this_cycle; | |
| 2854 | ipdbdq${q}_wr_adr = siu_coverage_ipdbq${q}_wr.d_adr; | |
| 2855 | } | |
| 2856 | } | |
| 2857 | } | |
| 2858 | { | |
| 2859 | integer ipdoq${q}_d_rd_last_cycle = 0; | |
| 2860 | while(1) | |
| 2861 | { | |
| 2862 | integer ipdoq${q}_d_rd_this_cycle; | |
| 2863 | @(posedge siu_coverage_ipdoq${q}_rd.clk); | |
| 2864 | if (siu_coverage_ipdoq${q}_rd.d_adr !== ipdodq${q}_rd_adr) | |
| 2865 | { | |
| 2866 | ipdodq${q}_size --; | |
| 2867 | ipdoq${q}_d_rd_this_cycle = get_cycle(siu_coverage_ipdoq${q}_rd.clk); | |
| 2868 | ipdoq${q}_d_rd_b2b = ipdoq${q}_d_rd_this_cycle - ipdoq${q}_d_rd_last_cycle; | |
| 2869 | ipdoq${q}_d_rd_last_cycle = ipdoq${q}_d_rd_this_cycle; | |
| 2870 | ipdodq${q}_rd_adr = siu_coverage_ipdoq${q}_rd.d_adr; | |
| 2871 | } | |
| 2872 | } | |
| 2873 | } | |
| 2874 | { | |
| 2875 | integer ipdbq${q}_d_rd_last_cycle = 0; | |
| 2876 | while(1) | |
| 2877 | { | |
| 2878 | integer ipdbq${q}_d_rd_this_cycle; | |
| 2879 | @(posedge siu_coverage_ipdbq${q}_rd.clk); | |
| 2880 | if (siu_coverage_ipdbq${q}_rd.d_adr !== ipdbdq${q}_rd_adr) | |
| 2881 | { | |
| 2882 | ipdbdq${q}_size --; | |
| 2883 | ipdbq${q}_d_rd_this_cycle = get_cycle(siu_coverage_ipdbq${q}_rd.clk); | |
| 2884 | ipdbq${q}_d_rd_b2b = ipdbq${q}_d_rd_this_cycle - ipdbq${q}_d_rd_last_cycle; | |
| 2885 | ipdbq${q}_d_rd_last_cycle = ipdbq${q}_d_rd_this_cycle; | |
| 2886 | ipdbdq${q}_rd_adr = siu_coverage_ipdbq${q}_rd.d_adr; | |
| 2887 | } | |
| 2888 | } | |
| 2889 | } | |
| 2890 | . } | |
| 2891 | ||
| 2892 | . for ($q=0; $q<2; $q++) | |
| 2893 | . { | |
| 2894 | { | |
| 2895 | while (1) | |
| 2896 | { | |
| 2897 | @(posedge siu_coverage_ipcc_ipcs.clk); | |
| 2898 | if ( siu_coverage_ipcc_ipcs.by${q}_go === 1'b1 ) | |
| 2899 | trigger (ipcc_ipcs${q}_bygo_evnt_trig); | |
| 2900 | if ( siu_coverage_ipcc_ipcs.or${q}_go === 1'b1 ) | |
| 2901 | trigger (ipcc_ipcs${q}_orgo_evnt_trig); | |
| 2902 | } | |
| 2903 | } | |
| 2904 | . } | |
| 2905 | ||
| 2906 | { | |
| 2907 | while (1) | |
| 2908 | { | |
| 2909 | @(posedge siu_coverage_ipcc_arb.clk); | |
| 2910 | if ( siu_coverage_ipcc_arb.niu_by_go === 1'b1 || | |
| 2911 | siu_coverage_ipcc_arb.niu_or_go === 1'b1 || | |
| 2912 | siu_coverage_ipcc_arb.dmu_by_go === 1'b1 || | |
| 2913 | siu_coverage_ipcc_arb.dmu_or_go === 1'b1) | |
| 2914 | trigger (ipcc_arb_evnt_trig); | |
| 2915 | } | |
| 2916 | } | |
| 2917 | // RAS_COVERAGE | |
| 2918 | ||
| 2919 | { | |
| 2920 | while (1) | |
| 2921 | { | |
| 2922 | @(posedge siu_coverage_err_det.clk); | |
| 2923 | if ( siu_coverage_err_det.cp_err === 1'b1 || | |
| 2924 | siu_coverage_err_det.ap_err === 1'b1 || | |
| 2925 | siu_coverage_err_det.dp_err === 1'b1 || | |
| 2926 | siu_coverage_err_det.cecc_ue === 1'b1 || | |
| 2927 | siu_coverage_err_det.cecc_ce === 1'b1) | |
| 2928 | trigger (ipcc_err_det_trig); | |
| 2929 | } | |
| 2930 | } | |
| 2931 | ||
| 2932 | { | |
| 2933 | while (1) | |
| 2934 | { | |
| 2935 | @(siu_coverage_err_det.id or siu_coverage_err_det.c); | |
| 2936 | trigger (ipcc_ecc_err_trig); | |
| 2937 | } | |
| 2938 | } | |
| 2939 | // ras coverage end | |
| 2940 | ||
| 2941 | join none | |
| 2942 | } | |
| 2943 | ||
| 2944 | ||
| 2945 | //////////////////////////////////////////////////////////////////////// | |
| 2946 | // sio internal coverage objects | |
| 2947 | //////////////////////////////////////////////////////////////////////// | |
| 2948 | class siu_opcs_coverage | |
| 2949 | { | |
| 2950 | StandardDisplay dbg; | |
| 2951 | local string myname; | |
| 2952 | ||
| 2953 | bit siu_opcs_cov_debug = 1'b0; | |
| 2954 | bit [2:0] sio_sii_opcc_ipcc_dmu_by_cnt = 3'b0; | |
| 2955 | bit [2:0] sio_sii_opcc_ipcc_niu_by_cnt = 3'b0; | |
| 2956 | ||
| 2957 | ||
| 2958 | . for ($bank=0; $bank<8; $bank++) | |
| 2959 | . { | |
| 2960 | . for ($q=0; $q<2; $q++) | |
| 2961 | . { | |
| 2962 | bit [4:0] olddq${bank}${q}_rd_adr = 5'b0; | |
| 2963 | bit [4:0] olddq${bank}${q}_wr_adr = 5'b0; | |
| 2964 | integer olddq${bank}${q}_wr_b2b = 1; | |
| 2965 | integer olddq${bank}${q}_rd_b2b = 0; | |
| 2966 | integer olddq${bank}${q}_size = 0; | |
| 2967 | .} | |
| 2968 | .} | |
| 2969 | ||
| 2970 | . for ($q=0; $q<2; $q++) | |
| 2971 | . { | |
| 2972 | // opdhq | |
| 2973 | bit [3:0] opdhq${q}_rd_adr = 4'b0; | |
| 2974 | bit [3:0] opdhq${q}_wr_adr = 4'b0; | |
| 2975 | integer opdhq${q}_size = 0; | |
| 2976 | integer opdhq${q}_wr_b2b = 0; | |
| 2977 | integer opdhq${q}_rd_b2b = 0; | |
| 2978 | .} | |
| 2979 | ||
| 2980 | . for ($q=0; $q<2; $q++) | |
| 2981 | . { | |
| 2982 | . for ($p=0; $p<2; $p++) | |
| 2983 | . { | |
| 2984 | // opdhq | |
| 2985 | bit [5:0] opddq${q}${p}_rd_adr = 6'b0; | |
| 2986 | bit [5:0] opddq${q}${p}_wr_adr = 6'b0; | |
| 2987 | integer opddq${q}${p}_size = 0; | |
| 2988 | integer opddq${q}${p}_wr_b2b = 1; | |
| 2989 | integer opddq${q}${p}_rd_b2b = 0; | |
| 2990 | .} | |
| 2991 | .} | |
| 2992 | ||
| 2993 | event opcc_arb_evnt_trig; | |
| 2994 | ||
| 2995 | ////// olddq ////// | |
| 2996 | . for ($bank=0; $bank<8; $bank++) | |
| 2997 | . { | |
| 2998 | . for ($q=0; $q<2; $q++) | |
| 2999 | . { | |
| 3000 | coverage_group olddq${bank}${q}_wr_cov | |
| 3001 | { | |
| 3002 | sample_event = wait_var(olddq${bank}${q}_wr_adr); | |
| 3003 | #include "siu_olddq${bank}${q}_wr_sample.vrh" | |
| 3004 | } | |
| 3005 | coverage_group olddq${bank}${q}_rd_cov | |
| 3006 | { | |
| 3007 | sample_event = wait_var(olddq${bank}${q}_rd_adr); | |
| 3008 | #include "siu_olddq${bank}${q}_rd_sample.vrh" | |
| 3009 | } | |
| 3010 | .} | |
| 3011 | .} | |
| 3012 | ||
| 3013 | ////// opdhq(0,1) | |
| 3014 | . for ($q=0; $q<2; $q++) | |
| 3015 | . { | |
| 3016 | coverage_group opdhq${q}_rd_cov | |
| 3017 | { | |
| 3018 | sample_event = wait_var(opdhq${q}_rd_adr); | |
| 3019 | #include "siu_opdhq${q}_rd_sample.vrh" | |
| 3020 | } | |
| 3021 | coverage_group opdhq${q}_wr_cov | |
| 3022 | { | |
| 3023 | sample_event = wait_var(opdhq${q}_wr_adr); | |
| 3024 | #include "siu_opdhq${q}_wr_sample.vrh" | |
| 3025 | } | |
| 3026 | .} | |
| 3027 | ||
| 3028 | ////// opddq(0,1)(0,1) | |
| 3029 | . for ($q=0; $q<2; $q++) | |
| 3030 | . { | |
| 3031 | . for ($p=0; $p<2; $p++) | |
| 3032 | . { | |
| 3033 | coverage_group opddq${q}${p}_rd_cov | |
| 3034 | { | |
| 3035 | sample_event = wait_var(opddq${q}${p}_rd_adr); | |
| 3036 | #include "siu_opddq${q}${p}_rd_sample.vrh" | |
| 3037 | } | |
| 3038 | coverage_group opddq${q}${p}_wr_cov | |
| 3039 | { | |
| 3040 | sample_event = wait_var(opddq${q}${p}_wr_adr); | |
| 3041 | #include "siu_opddq${q}${p}_wr_sample.vrh" | |
| 3042 | } | |
| 3043 | .} | |
| 3044 | .} | |
| 3045 | ||
| 3046 | . for ($q=0; $q<2; $q++) | |
| 3047 | . { | |
| 3048 | coverage_group siu_state_opcs${q} | |
| 3049 | { | |
| 3050 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3051 | sample_event = @(posedge siu_coverage_ifc_l2.clk); | |
| 3052 | ||
| 3053 | #include "siu_opcs${q}_state.vrh" | |
| 3054 | } | |
| 3055 | . } | |
| 3056 | ||
| 3057 | ||
| 3058 | #ifndef SIU_WB_COV | |
| 3059 | coverage_group communicate_cnt_niu_by_cov | |
| 3060 | { | |
| 3061 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3062 | sample_event = @(posedge siu_coverage_opcc_arb.clk); | |
| 3063 | ||
| 3064 | #include "siu_commun_niu_by_sample.vrh" | |
| 3065 | } | |
| 3066 | ||
| 3067 | ||
| 3068 | coverage_group opcc_arb_cov | |
| 3069 | { | |
| 3070 | sample_event = sync (ANY, opcc_arb_evnt_trig); | |
| 3071 | sample siu_coverage_opcc_arb.olc0_req, | |
| 3072 | siu_coverage_opcc_arb.olc1_req, | |
| 3073 | siu_coverage_opcc_arb.olc2_req, | |
| 3074 | siu_coverage_opcc_arb.olc3_req, | |
| 3075 | siu_coverage_opcc_arb.olc4_req, | |
| 3076 | siu_coverage_opcc_arb.olc5_req, | |
| 3077 | siu_coverage_opcc_arb.olc6_req, | |
| 3078 | siu_coverage_opcc_arb.olc7_req; | |
| 3079 | cross siu_opcc_cross_arb ( | |
| 3080 | siu_coverage_opcc_arb.olc0_req, | |
| 3081 | siu_coverage_opcc_arb.olc1_req, | |
| 3082 | siu_coverage_opcc_arb.olc2_req, | |
| 3083 | siu_coverage_opcc_arb.olc3_req, | |
| 3084 | siu_coverage_opcc_arb.olc4_req, | |
| 3085 | siu_coverage_opcc_arb.olc5_req, | |
| 3086 | siu_coverage_opcc_arb.olc6_req, | |
| 3087 | siu_coverage_opcc_arb.olc7_req) | |
| 3088 | { | |
| 3089 | ignored IgnoreOpccarb ( | |
| 3090 | siu_coverage_opcc_arb.olc0_req == 1'b0 && | |
| 3091 | siu_coverage_opcc_arb.olc1_req == 1'b0 && | |
| 3092 | siu_coverage_opcc_arb.olc2_req == 1'b0 && | |
| 3093 | siu_coverage_opcc_arb.olc3_req == 1'b0 && | |
| 3094 | siu_coverage_opcc_arb.olc4_req == 1'b0 && | |
| 3095 | siu_coverage_opcc_arb.olc5_req == 1'b0 && | |
| 3096 | siu_coverage_opcc_arb.olc6_req == 1'b0 && | |
| 3097 | siu_coverage_opcc_arb.olc7_req == 1'b0); | |
| 3098 | } | |
| 3099 | } | |
| 3100 | #endif // not in the siu_wb_cov | |
| 3101 | ||
| 3102 | // RAS_COVERAGE | |
| 3103 | ////// opcs_err(0,1) | |
| 3104 | . for ($q=0; $q<2; $q++) | |
| 3105 | . { | |
| 3106 | coverage_group sio_opcs${q}_err_cov | |
| 3107 | { | |
| 3108 | sample_event = @(siu_coverage_opcs${q}_err.ctag_ue or | |
| 3109 | siu_coverage_opcs${q}_err.ctag_ce); | |
| 3110 | sample siu_coverage_opcs${q}_err.ctag_ue | |
| 3111 | { | |
| 3112 | state S_UE (1); | |
| 3113 | } | |
| 3114 | sample siu_coverage_opcs${q}_err.ctag_ce | |
| 3115 | { | |
| 3116 | state S_CE (1); | |
| 3117 | } | |
| 3118 | } | |
| 3119 | coverage_group sio_opcs${q}_ecc_err_cov | |
| 3120 | { | |
| 3121 | sample_event = @(siu_coverage_opcs${q}_err.id); | |
| 3122 | sample siu_coverage_opcs${q}_err.e | |
| 3123 | { | |
| 3124 | ||
| 3125 | state s_CECC (0:63) if ((siu_coverage_opcs${q}_err.e[4:0] < 5'b10110) && (siu_coverage_opcs${q}_err.e[5] === 1'b1)); | |
| 3126 | state s_NO_ERR (0:63) if (siu_coverage_opcs${q}_err.e === 6'b000000); | |
| 3127 | state s_UECC (0:63) if ((siu_coverage_opcs${q}_err.e[4:0] !== 5'b00000) && ((siu_coverage_opcs${q}_err.e[5] === 1'b0) || (siu_coverage_opcs${q}_err.e[4:0] > 5'b10101))); | |
| 3128 | } | |
| 3129 | } | |
| 3130 | .} | |
| 3131 | ||
| 3132 | ////// E bit on from 8 L2 banks | |
| 3133 | . for ($q=0; $q<8; $q++) | |
| 3134 | . { | |
| 3135 | coverage_group sio_ebit_cov${q} | |
| 3136 | { | |
| 3137 | sample_event = @(posedge siu_coverage_ifc_l2.l2b${q}_sio_ctag_vld); | |
| 3138 | sample siu_coverage_ifc_l2.l2b${q}_sio_data[21]; | |
| 3139 | } | |
| 3140 | .} | |
| 3141 | // RAS_COVERAGE end | |
| 3142 | ||
| 3143 | // for sio-niu interface coverage | |
| 3144 | ||
| 3145 | ||
| 3146 | coverage_group siu_niudq_req_cov | |
| 3147 | { | |
| 3148 | sample_event = @(posedge siu_coverage_ifc.niu_sio_dq); | |
| 3149 | sample siu_coverage_ifc.niu_sio_dq | |
| 3150 | { | |
| 3151 | state s_SI0NIU_DQ_REQ (1) if (siu_coverage_ifc.sio_niu_req === 1'b1); | |
| 3152 | } | |
| 3153 | } | |
| 3154 | // | |
| 3155 | ||
| 3156 | task new(StandardDisplay dbg); | |
| 3157 | task set_cov_cond_bits (); | |
| 3158 | ||
| 3159 | } // class siu_opcs_coverage | |
| 3160 | ||
| 3161 | ////// siu_opcs_coverage class | |
| 3162 | task siu_opcs_coverage::new(StandardDisplay dbg) | |
| 3163 | { | |
| 3164 | bit coverage_on; | |
| 3165 | ||
| 3166 | myname = "siu_opcs_coverage"; | |
| 3167 | this.dbg = dbg; | |
| 3168 | ||
| 3169 | if (mChkPlusarg(siu_opcs_coverage) || mChkPlusarg(coverage_on)) { | |
| 3170 | coverage_on = 1; | |
| 3171 | if (mChkPlusarg(siu_opcs_cov_debug)) { | |
| 3172 | siu_opcs_cov_debug = 1'b1; | |
| 3173 | } | |
| 3174 | } else { | |
| 3175 | coverage_on = 0; | |
| 3176 | } | |
| 3177 | ||
| 3178 | if (coverage_on) | |
| 3179 | { | |
| 3180 | //opdohq0_wr_cov = new(); | |
| 3181 | ||
| 3182 | fork { | |
| 3183 | @(posedge siu_coverage_olddq00.cmp_diag_done); | |
| 3184 | coverage_save_database(1); | |
| 3185 | } join none | |
| 3186 | ||
| 3187 | set_cov_cond_bits(); | |
| 3188 | } // coverage_on | |
| 3189 | } // opcs_coverage new | |
| 3190 | ||
| 3191 | task siu_opcs_coverage::set_cov_cond_bits() | |
| 3192 | { | |
| 3193 | fork | |
| 3194 | ||
| 3195 | . for ($bank=0; $bank<8; $bank++) | |
| 3196 | . { | |
| 3197 | . for ($q=0; $q<2; $q++) | |
| 3198 | . { | |
| 3199 | { | |
| 3200 | integer olddq_wr_last_cycle = 0; | |
| 3201 | while(1) | |
| 3202 | { | |
| 3203 | integer olddq_wr_this_cycle = 0; | |
| 3204 | @(posedge siu_coverage_olddq${bank}${q}.clk); | |
| 3205 | if (siu_coverage_olddq${bank}${q}.wr_en === 1'b1) | |
| 3206 | { | |
| 3207 | olddq${bank}${q}_size++; | |
| 3208 | ||
| 3209 | olddq_wr_this_cycle = get_cycle(siu_coverage_olddq${bank}${q}.clk); | |
| 3210 | olddq${bank}${q}_wr_b2b = olddq_wr_this_cycle - olddq_wr_last_cycle; | |
| 3211 | olddq_wr_last_cycle = olddq_wr_this_cycle; | |
| 3212 | olddq${bank}${q}_wr_adr = siu_coverage_olddq${bank}${q}.wr_adr; | |
| 3213 | } | |
| 3214 | } | |
| 3215 | } | |
| 3216 | { | |
| 3217 | integer olddq_rd_last_cycle = 0; | |
| 3218 | while(1) | |
| 3219 | { | |
| 3220 | integer olddq_rd_this_cycle = 0; | |
| 3221 | @(posedge siu_coverage_olddq${bank}${q}.clk); | |
| 3222 | if (siu_coverage_olddq${bank}${q}.rd_en === 1'b1) | |
| 3223 | { | |
| 3224 | olddq${bank}${q}_size--; | |
| 3225 | ||
| 3226 | olddq_rd_this_cycle = get_cycle(siu_coverage_olddq${bank}${q}.clk); | |
| 3227 | olddq${bank}${q}_rd_b2b = olddq_rd_this_cycle - olddq_rd_last_cycle; | |
| 3228 | olddq_rd_last_cycle = olddq_rd_this_cycle; | |
| 3229 | olddq${bank}${q}_rd_adr = siu_coverage_olddq${bank}${q}.rd_adr; | |
| 3230 | } | |
| 3231 | } | |
| 3232 | } | |
| 3233 | .} | |
| 3234 | .} | |
| 3235 | . for ($q=0; $q<2; $q++) | |
| 3236 | . { | |
| 3237 | { | |
| 3238 | integer opdhq${q}_rd_last_cycle = 0; | |
| 3239 | while(1) | |
| 3240 | { | |
| 3241 | integer opdhq${q}_rd_this_cycle = 0; | |
| 3242 | @(posedge siu_coverage_opdhq${q}_rd.clk); | |
| 3243 | if (siu_coverage_opdhq${q}_rd.rd_en === 1'b1 ) | |
| 3244 | { | |
| 3245 | opdhq${q}_size --; | |
| 3246 | opdhq${q}_rd_this_cycle = get_cycle(siu_coverage_opdhq${q}_rd.clk); | |
| 3247 | opdhq${q}_rd_b2b = opdhq${q}_rd_this_cycle - opdhq${q}_rd_last_cycle; | |
| 3248 | opdhq${q}_rd_last_cycle = opdhq${q}_rd_this_cycle; | |
| 3249 | ||
| 3250 | opdhq${q}_rd_adr = siu_coverage_opdhq${q}_rd.rd_adr; | |
| 3251 | } | |
| 3252 | } | |
| 3253 | } | |
| 3254 | { | |
| 3255 | integer opdhq${q}_wr_last_cycle = 0; | |
| 3256 | while(1) | |
| 3257 | { | |
| 3258 | integer opdhq${q}_wr_this_cycle = 0; | |
| 3259 | @(posedge siu_coverage_opdhq${q}_wr.clk); | |
| 3260 | if (siu_coverage_opdhq${q}_wr.wr_en === 1'b1 ) | |
| 3261 | { | |
| 3262 | opdhq${q}_size ++; | |
| 3263 | opdhq${q}_wr_this_cycle = get_cycle(siu_coverage_opdhq${q}_wr.clk); | |
| 3264 | opdhq${q}_wr_b2b = opdhq${q}_wr_this_cycle - opdhq${q}_wr_last_cycle; | |
| 3265 | opdhq${q}_wr_last_cycle = opdhq${q}_wr_this_cycle; | |
| 3266 | ||
| 3267 | opdhq${q}_wr_adr = siu_coverage_opdhq${q}_wr.wr_adr; | |
| 3268 | } | |
| 3269 | } | |
| 3270 | } | |
| 3271 | . } | |
| 3272 | ||
| 3273 | . for ($q=0; $q<2; $q++) | |
| 3274 | . { | |
| 3275 | . for ($p=0; $p<2; $p++) | |
| 3276 | . { | |
| 3277 | { | |
| 3278 | integer opddq${q}${p}_rd_last_cycle = 0; | |
| 3279 | while(1) | |
| 3280 | { | |
| 3281 | integer opddq${q}${p}_rd_this_cycle = 0; | |
| 3282 | @(posedge siu_coverage_opddq${q}${p}_rd.clk); | |
| 3283 | if (siu_coverage_opddq${q}${p}_rd.rd_en === 1'b1 ) | |
| 3284 | { | |
| 3285 | opddq${q}${p}_size --; | |
| 3286 | opddq${q}${p}_rd_this_cycle = get_cycle(siu_coverage_opddq${q}${p}_rd.clk); | |
| 3287 | opddq${q}${p}_rd_b2b = opddq${q}${p}_rd_this_cycle - opddq${q}${p}_rd_last_cycle; | |
| 3288 | opddq${q}${p}_rd_last_cycle = opddq${q}${p}_rd_this_cycle; | |
| 3289 | ||
| 3290 | opddq${q}${p}_rd_adr = siu_coverage_opddq${q}${p}_rd.rd_adr; | |
| 3291 | } | |
| 3292 | } | |
| 3293 | } | |
| 3294 | { | |
| 3295 | integer opddq${q}${p}_wr_last_cycle = 0; | |
| 3296 | while(1) | |
| 3297 | { | |
| 3298 | integer opddq${q}${p}_wr_this_cycle = 0; | |
| 3299 | @(posedge siu_coverage_opddq${q}${p}_wr.clk); | |
| 3300 | if (siu_coverage_opddq${q}${p}_wr.wr_en === 1'b1 ) | |
| 3301 | { | |
| 3302 | opddq${q}${p}_size ++; | |
| 3303 | opddq${q}${p}_wr_this_cycle = get_cycle(siu_coverage_opddq${q}${p}_wr.clk); | |
| 3304 | opddq${q}${p}_wr_b2b = opddq${q}${p}_wr_this_cycle - opddq${q}${p}_wr_last_cycle; | |
| 3305 | opddq${q}${p}_wr_last_cycle = opddq${q}${p}_wr_this_cycle; | |
| 3306 | ||
| 3307 | opddq${q}${p}_wr_adr = siu_coverage_opddq${q}${p}_wr.wr_adr; | |
| 3308 | } | |
| 3309 | } | |
| 3310 | } | |
| 3311 | . } | |
| 3312 | . } | |
| 3313 | #ifndef SIU_WB_COV | |
| 3314 | { | |
| 3315 | while (1) | |
| 3316 | { | |
| 3317 | @(posedge siu_coverage_opcc_arb.clk); | |
| 3318 | if ( siu_coverage_opcc_arb.olc0_req === 1'b1 || | |
| 3319 | siu_coverage_opcc_arb.olc1_req === 1'b1 || | |
| 3320 | siu_coverage_opcc_arb.olc2_req === 1'b1 || | |
| 3321 | siu_coverage_opcc_arb.olc3_req === 1'b1 || | |
| 3322 | siu_coverage_opcc_arb.olc4_req === 1'b1 || | |
| 3323 | siu_coverage_opcc_arb.olc5_req === 1'b1 || | |
| 3324 | siu_coverage_opcc_arb.olc6_req === 1'b1 || | |
| 3325 | siu_coverage_opcc_arb.olc7_req === 1'b1) | |
| 3326 | trigger (opcc_arb_evnt_trig); | |
| 3327 | } | |
| 3328 | } | |
| 3329 | #endif | |
| 3330 | ||
| 3331 | join none | |
| 3332 | ||
| 3333 | } | |
| 3334 | ||
| 3335 | // *********************************************************************************** | |
| 3336 | // SIU coverage Objects for FC MAQ | |
| 3337 | // *********************************************************************************** | |
| 3338 | ||
| 3339 | class fc_siu_internal_coverage | |
| 3340 | { | |
| 3341 | // for dispmon | |
| 3342 | StandardDisplay dbg; | |
| 3343 | local string myname; | |
| 3344 | ||
| 3345 | . for ($bank=0; $bank<8; $bank++) | |
| 3346 | . { | |
| 3347 | event sii_ildq${bank}_evnt_trig; | |
| 3348 | ||
| 3349 | . for ($q=0; $q<2; $q++) | |
| 3350 | . { | |
| 3351 | reg [5:0] sio_fifo_depth_olddq${bank}${q}_count_new = 6'd0; | |
| 3352 | reg [5:0] sio_fifo_depth_olddq${bank}${q}_count_old = 6'd0; | |
| 3353 | .} | |
| 3354 | reg [5:0] sii_fifo_depth_ildq${bank}_count_new = 6'd0; | |
| 3355 | reg [5:0] sii_fifo_depth_ildq${bank}_count_old = 6'd0; | |
| 3356 | .} | |
| 3357 | ||
| 3358 | reg [5:0] old_rd_adr = 6'd0; | |
| 3359 | reg [5:0] old_wr_adr = 6'd0; | |
| 3360 | ||
| 3361 | // ----------- coverage_group ---------------- | |
| 3362 | . for ($bank=0; $bank<8; $bank++) | |
| 3363 | . { | |
| 3364 | . for ($q=0; $q<2; $q++) | |
| 3365 | . { | |
| 3366 | coverage_group sio_fifo_depth_coverage_group_olddq${bank}${q} | |
| 3367 | { | |
| 3368 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3369 | sample_event = @(negedge sio_fifo_depth_olddq${bank}${q}.wr_en or | |
| 3370 | negedge sio_fifo_depth_olddq${bank}${q}.rd_en); | |
| 3371 | sample sio_fifo_depth_olddq${bank}${q}_count_new | |
| 3372 | { | |
| 3373 | . for ($z=0; $z <=32; $z++) | |
| 3374 | . { | |
| 3375 | state sio_fifo_count_olddq${bank}${q}_${z} (${z}) if(sio_fifo_depth_olddq${bank}${q}_count_new == 'd${z}); | |
| 3376 | . } | |
| 3377 | } | |
| 3378 | } | |
| 3379 | .} | |
| 3380 | .} | |
| 3381 | ||
| 3382 | // ----------- coverage_group ---------------- | |
| 3383 | . for ($bank=0; $bank<8; $bank++) { | |
| 3384 | coverage_group sii_fifo_depth_coverage_group_ildq${bank} | |
| 3385 | { | |
| 3386 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3387 | sample_event = sync (ANY, sii_ildq${bank}_evnt_trig); | |
| 3388 | sample sii_fifo_depth_ildq${bank}_count_new | |
| 3389 | { | |
| 3390 | . for ($z=0; $z <=32; $z++) { | |
| 3391 | state sii_fifo_depth_ildq${bank}_${z} (${z}) if(sii_fifo_depth_ildq${bank}_count_new == 'd${z}); | |
| 3392 | . } | |
| 3393 | } | |
| 3394 | } | |
| 3395 | .} | |
| 3396 | ||
| 3397 | ||
| 3398 | task new(StandardDisplay dbg); | |
| 3399 | task set_cov_cond_bits (); | |
| 3400 | . for ($bank=0; $bank<8; $bank++) | |
| 3401 | . { | |
| 3402 | . for ($q=0; $q<2; $q++) | |
| 3403 | . { | |
| 3404 | task sio_fifo_olddq${bank}${q}(); | |
| 3405 | .} | |
| 3406 | .} | |
| 3407 | ||
| 3408 | . for ($bank=0; $bank<8; $bank++) | |
| 3409 | . { | |
| 3410 | task sii_fifo_ildq${bank}(); | |
| 3411 | .} | |
| 3412 | ||
| 3413 | } //class fc_siu_internal_coverage | |
| 3414 | ||
| 3415 | ||
| 3416 | ///////////////////////////////////////////////////////////////// | |
| 3417 | // Class creation | |
| 3418 | ///////////////////////////////////////////////////////////////// | |
| 3419 | task fc_siu_internal_coverage::new(StandardDisplay dbg) | |
| 3420 | { | |
| 3421 | bit coverage_on = 0; | |
| 3422 | integer j; | |
| 3423 | ||
| 3424 | // for dispmon | |
| 3425 | myname = "fc_siu_internal_coverage"; | |
| 3426 | this.dbg = dbg; | |
| 3427 | ||
| 3428 | if (mChkPlusarg(fc_siu_internal_coverage) || mChkPlusarg(coverage_on)) { | |
| 3429 | coverage_on = 1; | |
| 3430 | } | |
| 3431 | ||
| 3432 | if (coverage_on) { | |
| 3433 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Internal Coverage turned on for SIU objects\n\n", get_time(LO))); | |
| 3434 | . for ($bank=0; $bank<8; $bank++) | |
| 3435 | . { | |
| 3436 | . for ($q=0; $q<2; $q++) | |
| 3437 | . { | |
| 3438 | ||
| 3439 | sio_fifo_depth_coverage_group_olddq${bank}${q} = new(); | |
| 3440 | .} | |
| 3441 | sii_fifo_depth_coverage_group_ildq${bank} = new(); | |
| 3442 | .} | |
| 3443 | ||
| 3444 | set_cov_cond_bits (); | |
| 3445 | ||
| 3446 | } // if coverage_on | |
| 3447 | } // fc_siu_internal_coverage::new() | |
| 3448 | ||
| 3449 | ||
| 3450 | /////////////////////////////////////////////////////////////////////////// | |
| 3451 | // This task is a psuedo coverage object that combines a few conditions | |
| 3452 | // so that the actual coverage objects' state space doesn't get too big | |
| 3453 | ////////////////////////////////////////////////////////////////////////// | |
| 3454 | ||
| 3455 | task fc_siu_internal_coverage:: set_cov_cond_bits () | |
| 3456 | { | |
| 3457 | ||
| 3458 | fork | |
| 3459 | . for ($bank=0; $bank<8; $bank++) | |
| 3460 | . { | |
| 3461 | . for ($q=0; $q<2; $q++) | |
| 3462 | . { | |
| 3463 | sio_fifo_olddq${bank}${q}(); | |
| 3464 | .} | |
| 3465 | .} | |
| 3466 | ||
| 3467 | . for ($bank=0; $bank<8; $bank++) | |
| 3468 | . { | |
| 3469 | sii_fifo_ildq${bank}(); | |
| 3470 | .} | |
| 3471 | ||
| 3472 | join none | |
| 3473 | ||
| 3474 | } // task fc_siu_internal_coverage:: set_cov_cond_bits | |
| 3475 | ||
| 3476 | . for ($bank=0; $bank<8; $bank++) | |
| 3477 | . { | |
| 3478 | task fc_siu_internal_coverage::sio_fifo_olddq${bank}0() | |
| 3479 | { | |
| 3480 | while(1) | |
| 3481 | { | |
| 3482 | @(negedge sio_fifo_depth_olddq${bank}0.clk); | |
| 3483 | { | |
| 3484 | if((sio_fifo_depth_olddq${bank}0.wr_en == 1) && (sio_fifo_depth_olddq${bank}0.rd_en == 0)) | |
| 3485 | { | |
| 3486 | @(negedge sio_fifo_depth_olddq${bank}0.clk); | |
| 3487 | sio_fifo_depth_olddq${bank}0_count_new = sio_fifo_depth_olddq${bank}0_count_new + 1; | |
| 3488 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sio_fifo_depth_olddq${bank}0_count_new = %d\n\n", get_time(LO), sio_fifo_depth_olddq${bank}0_count_new)); | |
| 3489 | } | |
| 3490 | else | |
| 3491 | if((sio_fifo_depth_olddq${bank}0.wr_en == 1) && (sio_fifo_depth_olddq${bank}0.rd_en == 1)) | |
| 3492 | { | |
| 3493 | sio_fifo_depth_olddq${bank}0_count_new = sio_fifo_depth_olddq${bank}0_count_new; | |
| 3494 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sio_fifo_depth_olddq${bank}0_count_new = %d\n\n", get_time(LO), sio_fifo_depth_olddq${bank}0_count_new)); | |
| 3495 | } | |
| 3496 | else | |
| 3497 | if((sio_fifo_depth_olddq${bank}0.wr_en == 0) && (sio_fifo_depth_olddq${bank}0.rd_en == 1)) | |
| 3498 | { | |
| 3499 | sio_fifo_depth_olddq${bank}0_count_new = sio_fifo_depth_olddq${bank}0_count_new - 1; | |
| 3500 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sio_fifo_depth_olddq${bank}0_count_new = %d\n\n", get_time(LO), sio_fifo_depth_olddq${bank}0_count_new)); | |
| 3501 | } | |
| 3502 | ||
| 3503 | } | |
| 3504 | } // while | |
| 3505 | } | |
| 3506 | task fc_siu_internal_coverage::sio_fifo_olddq${bank}1() | |
| 3507 | { | |
| 3508 | while(1) | |
| 3509 | { | |
| 3510 | @(negedge sio_fifo_depth_olddq${bank}1.clk); | |
| 3511 | { | |
| 3512 | if((sio_fifo_depth_olddq${bank}1.wr_en == 1) && (sio_fifo_depth_olddq${bank}1.rd_en == 0)) | |
| 3513 | { | |
| 3514 | sio_fifo_depth_olddq${bank}1_count_new = sio_fifo_depth_olddq${bank}1_count_new + 1; | |
| 3515 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sio_fifo_depth_olddq${bank}1_count_new = %d\n\n", get_time(LO), sio_fifo_depth_olddq${bank}1_count_new)); | |
| 3516 | } | |
| 3517 | else | |
| 3518 | if((sio_fifo_depth_olddq${bank}1.wr_en == 1) && (sio_fifo_depth_olddq${bank}1.rd_en == 1)) | |
| 3519 | { | |
| 3520 | sio_fifo_depth_olddq${bank}1_count_new = sio_fifo_depth_olddq${bank}1_count_new; | |
| 3521 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sio_fifo_depth_olddq${bank}1_count_new = %d\n\n", get_time(LO), sio_fifo_depth_olddq${bank}1_count_new)); | |
| 3522 | } | |
| 3523 | else | |
| 3524 | if((sio_fifo_depth_olddq${bank}1.wr_en == 0) && (sio_fifo_depth_olddq${bank}1.rd_en == 1)) | |
| 3525 | { | |
| 3526 | sio_fifo_depth_olddq${bank}1_count_new = sio_fifo_depth_olddq${bank}1_count_new - 1; | |
| 3527 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sio_fifo_depth_olddq${bank}1_count_new = %d\n\n", get_time(LO), sio_fifo_depth_olddq${bank}1_count_new)); | |
| 3528 | } | |
| 3529 | ||
| 3530 | } | |
| 3531 | } // while | |
| 3532 | } | |
| 3533 | ||
| 3534 | .} | |
| 3535 | ||
| 3536 | . for ($bank=0; $bank<8; $bank++) { | |
| 3537 | task fc_siu_internal_coverage::sii_fifo_ildq${bank}() | |
| 3538 | { | |
| 3539 | integer ildq${q}_rd_adr = 0; | |
| 3540 | while(1) | |
| 3541 | { | |
| 3542 | @(posedge sii_fifo_depth_ildq${q}.clk); | |
| 3543 | sii_fifo_depth_ildq${bank}_count_old = sii_fifo_depth_ildq${bank}_count_new; | |
| 3544 | if (sii_fifo_depth_ildq${q}.wr_en === 1'b1) | |
| 3545 | { | |
| 3546 | sii_fifo_depth_ildq${bank}_count_new++; | |
| 3547 | } | |
| 3548 | ||
| 3549 | if (sii_fifo_depth_ildq${q}.rd_adr !== ildq${q}_rd_adr && | |
| 3550 | sii_fifo_depth_ildq${q}.rd_en === 1'b1 ) | |
| 3551 | { | |
| 3552 | sii_fifo_depth_ildq${bank}_count_new--; | |
| 3553 | ildq${q}_rd_adr = sii_fifo_depth_ildq${q}.rd_adr; | |
| 3554 | } | |
| 3555 | if (sii_fifo_depth_ildq${bank}_count_old != sii_fifo_depth_ildq${bank}_count_new) { | |
| 3556 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Coverage-count for sii_fifo_depth_ildq${bank}_count_new = %d\n\n", get_time(LO), sii_fifo_depth_ildq${bank}_count_new)); | |
| 3557 | trigger( sii_ildq${bank}_evnt_trig ); | |
| 3558 | } | |
| 3559 | } | |
| 3560 | } | |
| 3561 | .} | |
| 3562 | ||
| 3563 | // *********************************************************************************** | |
| 3564 | // FC SIU RAS coverage Objects for MAQ | |
| 3565 | // *********************************************************************************** | |
| 3566 | ||
| 3567 | class fc_siu_ras_coverage | |
| 3568 | { | |
| 3569 | // for dispmon | |
| 3570 | StandardDisplay dbg; | |
| 3571 | local string myname; | |
| 3572 | integer i; | |
| 3573 | ||
| 3574 | . for ($bank=0; $bank<8; $bank++) | |
| 3575 | . { | |
| 3576 | reg sii_to_l2_Ebit_RDD_O_NP_DMU_bank${bank} = 1'b0; | |
| 3577 | reg sii_to_l2_Ebit_wr8_O_P_DMU_bank${bank} = 1'b0; | |
| 3578 | reg sii_to_l2_Ebit_wri_O_P_DMU_bank${bank} = 1'b0; | |
| 3579 | reg sii_to_l2_Ebit_RDD_B_NIU_bank${bank} = 1'b0; | |
| 3580 | reg sii_to_l2_Ebit_wri_O_NP_NIU_bank${bank} = 1'b0; | |
| 3581 | reg sii_to_l2_Ebit_wri_B_P_NIU_bank${bank} = 1'b0; | |
| 3582 | ||
| 3583 | reg sii_to_l2_Ebit_PA39_wr8_O_P_DMU_bank${bank} = 1'b0; | |
| 3584 | reg sii_to_l2_Ebit_PA39_wri_O_P_DMU_bank${bank} = 1'b0; | |
| 3585 | reg sii_to_l2_Ebit_PA39_wri_O_NP_NIU_bank${bank} = 1'b0; | |
| 3586 | reg sii_to_l2_Ebit_PA39_wri_B_P_NIU_bank${bank} = 1'b0; | |
| 3587 | reg l2_to_sio_Ebit_bank${bank} = 1'b0; | |
| 3588 | event l2b${bank}_sio_ue_err_trig; | |
| 3589 | . } | |
| 3590 | reg sio_to_niu_header81 = 1'b0; | |
| 3591 | reg sio_to_niu_header80 = 1'b0; | |
| 3592 | reg sio_to_dmu_header81 = 1'b0; | |
| 3593 | reg sio_to_dmu_header80 = 1'b0; | |
| 3594 | reg sii_ncu_dmuctag_ce_seen = 1'b0; | |
| 3595 | reg sii_ncu_niuctag_ce_seen = 1'b0; | |
| 3596 | reg sio_ncu_ctag_ce_seen = 1'b0; | |
| 3597 | ||
| 3598 | event siu_ncu_ctag_ce_seen_trig; | |
| 3599 | ||
| 3600 | // ----------- coverage_group ---------------- | |
| 3601 | . for ($bank=0; $bank<8; $bank++) | |
| 3602 | . { | |
| 3603 | coverage_group soc_err_Ebit_bank${bank} | |
| 3604 | { | |
| 3605 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3606 | sample_event = @(negedge siu_coverage_ifc_l2.sii_l2t${bank}); | |
| 3607 | sample soc_err_Ebit_RDD_O_NP_DMU_bank${bank} (sii_to_l2_Ebit_RDD_O_NP_DMU_bank${bank}) | |
| 3608 | { | |
| 3609 | state S_soc_err_Ebit_RDD_O_NP_DMU_bank${bank} (1'b1); | |
| 3610 | } | |
| 3611 | sample soc_err_Ebit_wr8_O_P_DMU_bank${bank} (sii_to_l2_Ebit_wr8_O_P_DMU_bank${bank}) | |
| 3612 | { | |
| 3613 | state S_soc_err_Ebit_wr8_O_P_DMU_bank${bank} (1'b1); | |
| 3614 | } | |
| 3615 | sample soc_err_Ebit_wri_O_P_DMU_bank${bank} (sii_to_l2_Ebit_wri_O_P_DMU_bank${bank}) | |
| 3616 | { | |
| 3617 | state S_soc_err_Ebit_wri_O_P_DMU_bank${bank} (1'b1); | |
| 3618 | } | |
| 3619 | sample soc_err_Ebit_RDD_B_NIU_bank${bank} (sii_to_l2_Ebit_RDD_B_NIU_bank${bank}) | |
| 3620 | { | |
| 3621 | state S_soc_err_Ebit_RDD_B_NIU_bank${bank} (1'b1); | |
| 3622 | } | |
| 3623 | sample soc_err_Ebit_wri_O_NP_NIU_bank${bank} (sii_to_l2_Ebit_wri_O_NP_NIU_bank${bank}) | |
| 3624 | { | |
| 3625 | state S_soc_err_Ebit_wri_O_NP_NIU_bank${bank} (1'b1); | |
| 3626 | } | |
| 3627 | sample soc_err_Ebit_wri_B_P_NIU_bank${bank} (sii_to_l2_Ebit_wri_B_P_NIU_bank${bank}) | |
| 3628 | { | |
| 3629 | state S_soc_err_Ebit_wri_B_P_NIU_bank${bank} (1'b1); | |
| 3630 | } | |
| 3631 | } | |
| 3632 | . } | |
| 3633 | // ----------- coverage_group ---------------- | |
| 3634 | . for ($bank=0; $bank<8; $bank++) | |
| 3635 | . { | |
| 3636 | coverage_group soc_err_Ebit_PA39_bank${bank} | |
| 3637 | { | |
| 3638 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3639 | sample_event = @(negedge siu_coverage_ifc_l2.sii_l2t${bank}); | |
| 3640 | sample soc_err_Ebit_PA39_wr8_O_P_DMU_bank${bank} (sii_to_l2_Ebit_PA39_wr8_O_P_DMU_bank${bank}) | |
| 3641 | { | |
| 3642 | state S_soc_err_Ebit_PA39_wr8_O_P_DMU_bank${bank} (1'b1); | |
| 3643 | } | |
| 3644 | sample soc_err_Ebit_PA39_wri_O_P_DMU_bank${bank} (sii_to_l2_Ebit_PA39_wri_O_P_DMU_bank${bank}) | |
| 3645 | { | |
| 3646 | state S_soc_err_Ebit_PA39_wri_O_P_DMU_bank${bank} (1'b1); | |
| 3647 | } | |
| 3648 | sample soc_err_Ebit_PA39_wri_O_NP_NIU_bank${bank} (sii_to_l2_Ebit_PA39_wri_O_NP_NIU_bank${bank}) | |
| 3649 | { | |
| 3650 | state S_soc_err_Ebit_PA39_wri_O_NP_NIU_bank${bank} (1'b1); | |
| 3651 | } | |
| 3652 | sample soc_err_Ebit_PA39_wri_B_P_NIU_bank${bank} (sii_to_l2_Ebit_PA39_wri_B_P_NIU_bank${bank}) | |
| 3653 | { | |
| 3654 | state S_soc_err_Ebit_PA39_wri_B_P_NIU_bank${bank} (1'b1); | |
| 3655 | } | |
| 3656 | } | |
| 3657 | . } | |
| 3658 | // ----------- coverage_group ---------------- | |
| 3659 | . for ($bank=0; $bank<8; $bank++) | |
| 3660 | . { | |
| 3661 | coverage_group soc_err_l2sioUe_bank${bank} | |
| 3662 | { | |
| 3663 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3664 | sample_event = @(negedge l2b_to_sio_UEs.clk); | |
| 3665 | sample soc_err_l2sioUe_err_bank${bank} (l2b_to_sio_UEs.l2b${bank}_to_sio_ue_err) | |
| 3666 | { | |
| 3667 | state S_soc_err_l2sioUe_err_bank${bank} (1'b1); | |
| 3668 | } | |
| 3669 | } | |
| 3670 | . } | |
| 3671 | ||
| 3672 | // ----------- coverage_group ---------------- | |
| 3673 | . for ($bank=0; $bank<8; $bank++) | |
| 3674 | . { | |
| 3675 | coverage_group soc_err_l2sioUe_Ebit_bank${bank} | |
| 3676 | { | |
| 3677 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3678 | sample_event = sync (ANY, l2b${bank}_sio_ue_err_trig); | |
| 3679 | sample soc_err_l2sioUe_err_Ebit_bank${bank} (l2_to_sio_Ebit_bank${bank}) | |
| 3680 | { | |
| 3681 | state S_soc_err_l2sioUe_err_Ebit_bank${bank} (1'b1); | |
| 3682 | } | |
| 3683 | } | |
| 3684 | . } | |
| 3685 | ||
| 3686 | // ----------- coverage_group ---------------- | |
| 3687 | coverage_group soc_err_sioIoErrSignals | |
| 3688 | { | |
| 3689 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3690 | sample_event = @(negedge siu_coverage_ifc.clk); | |
| 3691 | sample soc_err_sioIoErrSignals_NIU ({sio_to_niu_header81, sio_to_niu_header80}) | |
| 3692 | { | |
| 3693 | state S_soc_err_sioIoErrSignals_NIU_01 (2'b01); | |
| 3694 | state S_soc_err_sioIoErrSignals_NIU_10 (2'b10); | |
| 3695 | state S_soc_err_sioIoErrSignals_NIU_11 (2'b11); | |
| 3696 | } | |
| 3697 | sample soc_err_sioIoErrSignals_DMU ({sio_to_dmu_header81, sio_to_dmu_header80}) | |
| 3698 | { | |
| 3699 | state S_soc_err_sioIoErrSignals_DMU_01 (2'b01); | |
| 3700 | state S_soc_err_sioIoErrSignals_DMU_10 (2'b10); | |
| 3701 | state S_soc_err_sioIoErrSignals_DMU_11 (2'b11); | |
| 3702 | } | |
| 3703 | } | |
| 3704 | // ----------- coverage_group ---------------- | |
| 3705 | coverage_group soc_err_multiCE_10cycle | |
| 3706 | { | |
| 3707 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3708 | sample_event = sync (ANY, siu_ncu_ctag_ce_seen_trig); | |
| 3709 | sample soc_err_multiCE_10cycle_niu_n_dmu ({sii_ncu_dmuctag_ce_seen,sii_ncu_niuctag_ce_seen,sio_ncu_ctag_ce_seen}) | |
| 3710 | { | |
| 3711 | state S_soc_err_multiCE_10cycle_niu_n_dmu (3'b111); | |
| 3712 | } | |
| 3713 | } | |
| 3714 | // ----------- coverage_group ---------------- | |
| 3715 | coverage_group soc_err_multiCE_10times | |
| 3716 | { | |
| 3717 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 3718 | sample_event = sync (ANY, siu_ncu_ctag_ce_seen_trig); | |
| 3719 | at_least = 10; | |
| 3720 | sample soc_err_multiCE_10times_niu_n_dmu ({sii_ncu_dmuctag_ce_seen,sii_ncu_niuctag_ce_seen,sio_ncu_ctag_ce_seen}) | |
| 3721 | { | |
| 3722 | state S_soc_err_multiCE_10times_niu_n_dmu (3'b111); | |
| 3723 | } | |
| 3724 | } | |
| 3725 | // ----------- coverage_group ---------------- | |
| 3726 | ||
| 3727 | ||
| 3728 | ||
| 3729 | task new(StandardDisplay dbg); | |
| 3730 | task set_cov_cond_bits (); | |
| 3731 | ||
| 3732 | . for ($bank=0; $bank<8; $bank++) | |
| 3733 | . { | |
| 3734 | task sii_to_l2_Ebit_bank${bank}(); | |
| 3735 | task sii_to_l2_Ebit_PA39_bank${bank}(); | |
| 3736 | task l2_to_sio_Ebit_UE_bank${bank}(); | |
| 3737 | . } | |
| 3738 | task sio_to_niu_Err(); | |
| 3739 | task soc_niu_n_dmu_multi_ce_Err(); | |
| 3740 | ||
| 3741 | } | |
| 3742 | ||
| 3743 | task fc_siu_ras_coverage::new(StandardDisplay dbg) | |
| 3744 | { | |
| 3745 | bit coverage_on = 0; | |
| 3746 | integer j; | |
| 3747 | ||
| 3748 | // for dispmon | |
| 3749 | myname = "fc_siu_ras_coverage"; | |
| 3750 | this.dbg = dbg; | |
| 3751 | ||
| 3752 | if (mChkPlusarg(fc_siu_ras_coverage) || mChkPlusarg(coverage_on)) { | |
| 3753 | coverage_on = 1; | |
| 3754 | } | |
| 3755 | ||
| 3756 | if (coverage_on) { | |
| 3757 | dbg.dispmon(myname, MON_ALWAYS, psprintf("\n\n %d :fc_siu_ras_coverage Coverage turned on for SIU objects\n\n", get_time(LO))); | |
| 3758 | ||
| 3759 | . for ($bank=0; $bank<8; $bank++) | |
| 3760 | . { | |
| 3761 | soc_err_Ebit_bank${bank} = new(); | |
| 3762 | soc_err_Ebit_PA39_bank${bank} = new(); | |
| 3763 | soc_err_l2sioUe_bank${bank} = new(); | |
| 3764 | soc_err_l2sioUe_Ebit_bank${bank} = new(); | |
| 3765 | . } | |
| 3766 | soc_err_sioIoErrSignals = new(); | |
| 3767 | soc_err_multiCE_10cycle = new(); | |
| 3768 | soc_err_multiCE_10times = new(); | |
| 3769 | set_cov_cond_bits (); | |
| 3770 | ||
| 3771 | } // if coverage_on | |
| 3772 | } // fc_siu_ras_coverage::new() | |
| 3773 | ||
| 3774 | task fc_siu_ras_coverage:: set_cov_cond_bits () | |
| 3775 | { | |
| 3776 | ||
| 3777 | fork | |
| 3778 | . for ($bank=0; $bank<8; $bank++) | |
| 3779 | . { | |
| 3780 | sii_to_l2_Ebit_bank${bank}(); | |
| 3781 | sii_to_l2_Ebit_PA39_bank${bank}(); | |
| 3782 | l2_to_sio_Ebit_UE_bank${bank}(); | |
| 3783 | . } | |
| 3784 | sio_to_niu_Err(); | |
| 3785 | soc_niu_n_dmu_multi_ce_Err(); | |
| 3786 | join none | |
| 3787 | ||
| 3788 | } // task fc_siu_ras_coverage:: set_cov_cond_bits | |
| 3789 | ||
| 3790 | . for ($bank=0; $bank<8; $bank++) | |
| 3791 | . { | |
| 3792 | task fc_siu_ras_coverage::sii_to_l2_Ebit_bank${bank}() | |
| 3793 | { | |
| 3794 | while(1) | |
| 3795 | { | |
| 3796 | @(negedge siu_coverage_ifc_l2.clk); | |
| 3797 | { | |
| 3798 | if(siu_coverage_ifc_l2.sii_l2t${bank}) | |
| 3799 | { | |
| 3800 | sii_to_l2_Ebit_RDD_O_NP_DMU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b001) && | |
| 3801 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3802 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3803 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b1)) ; | |
| 3804 | ||
| 3805 | sii_to_l2_Ebit_wr8_O_P_DMU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b010) && | |
| 3806 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3807 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b1) && | |
| 3808 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3809 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b1)) ; | |
| 3810 | ||
| 3811 | sii_to_l2_Ebit_wri_O_P_DMU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b100) && | |
| 3812 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3813 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b1) && | |
| 3814 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3815 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b1)) ; | |
| 3816 | ||
| 3817 | ||
| 3818 | sii_to_l2_Ebit_RDD_B_NIU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b001) && | |
| 3819 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b0) && | |
| 3820 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3821 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b0)) ; | |
| 3822 | ||
| 3823 | sii_to_l2_Ebit_wri_O_NP_NIU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b100) && | |
| 3824 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3825 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b0) && | |
| 3826 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3827 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b0)) ; | |
| 3828 | ||
| 3829 | sii_to_l2_Ebit_wri_B_P_NIU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b100) && | |
| 3830 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b0) && | |
| 3831 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b1) && | |
| 3832 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3833 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b0)) ; | |
| 3834 | ||
| 3835 | } // if | |
| 3836 | } | |
| 3837 | }// while | |
| 3838 | ||
| 3839 | } | |
| 3840 | . } | |
| 3841 | . for ($bank=0; $bank<8; $bank++) | |
| 3842 | . { | |
| 3843 | task fc_siu_ras_coverage::sii_to_l2_Ebit_PA39_bank${bank}() | |
| 3844 | { | |
| 3845 | while(1) | |
| 3846 | { | |
| 3847 | @(negedge siu_coverage_ifc_l2.clk); | |
| 3848 | { | |
| 3849 | if(siu_coverage_ifc_l2.sii_l2t${bank}) | |
| 3850 | { | |
| 3851 | sii_to_l2_Ebit_PA39_wr8_O_P_DMU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b010) && | |
| 3852 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3853 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b1) && | |
| 3854 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3855 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b1) && | |
| 3856 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[7] == 1'b1)) ; | |
| 3857 | ||
| 3858 | sii_to_l2_Ebit_PA39_wri_O_P_DMU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b100) && | |
| 3859 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3860 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b1) && | |
| 3861 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3862 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b1) && | |
| 3863 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[7] == 1'b1)) ; | |
| 3864 | ||
| 3865 | ||
| 3866 | sii_to_l2_Ebit_PA39_wri_O_NP_NIU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b100) && | |
| 3867 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b1) && | |
| 3868 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b0) && | |
| 3869 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3870 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b0) && | |
| 3871 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[7] == 1'b1)) ; | |
| 3872 | ||
| 3873 | sii_to_l2_Ebit_PA39_wri_B_P_NIU_bank${bank} = ((siu_coverage_ifc_l2.sii_l2t${bank}_data[26:24] == 3'b100) && | |
| 3874 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[30] == 1'b0) && | |
| 3875 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[29] == 1'b1) && | |
| 3876 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[28] == 1'b1) && | |
| 3877 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[27] == 1'b0) && | |
| 3878 | (siu_coverage_ifc_l2.sii_l2t${bank}_data[7] == 1'b1)) ; | |
| 3879 | ||
| 3880 | } // if | |
| 3881 | } | |
| 3882 | }// while | |
| 3883 | ||
| 3884 | } | |
| 3885 | . } | |
| 3886 | ||
| 3887 | . for ($bank=0; $bank<8; $bank++) | |
| 3888 | . { | |
| 3889 | task fc_siu_ras_coverage::l2_to_sio_Ebit_UE_bank${bank}() | |
| 3890 | { | |
| 3891 | while(1) | |
| 3892 | { | |
| 3893 | @(negedge l2b_to_sio_UEs.clk); | |
| 3894 | { | |
| 3895 | if(l2b_to_sio_UEs.l2b${bank}_to_sio_ctag_vld) | |
| 3896 | { | |
| 3897 | l2_to_sio_Ebit_bank${bank} = ((l2b_to_sio_UEs.l2b${bank}_to_sio_data[21] == 1'b1) && // E-bit | |
| 3898 | (l2b_to_sio_UEs.l2b${bank}_to_sio_data[16] == 1'b1)); // RDD | |
| 3899 | for(i=0; i< 16; i++) | |
| 3900 | { | |
| 3901 | @(negedge l2b_to_sio_UEs.clk); | |
| 3902 | if(l2b_to_sio_UEs.l2b${bank}_to_sio_ue_err) | |
| 3903 | trigger (l2b${bank}_sio_ue_err_trig); | |
| 3904 | } | |
| 3905 | } | |
| 3906 | else | |
| 3907 | l2_to_sio_Ebit_bank${bank} = 1'b0; | |
| 3908 | } | |
| 3909 | } | |
| 3910 | ||
| 3911 | } | |
| 3912 | . } | |
| 3913 | ||
| 3914 | task fc_siu_ras_coverage::sio_to_niu_Err() | |
| 3915 | { | |
| 3916 | while(1) | |
| 3917 | { | |
| 3918 | @(posedge siu_coverage_ifc.clk); | |
| 3919 | { | |
| 3920 | sio_to_niu_header81 = ((siu_coverage_ifc.sio_niu_req == 1'b1) && // hdr vld. | |
| 3921 | (siu_coverage_ifc.sio_niu_data[127] == 1'b1) && // Response Bit | |
| 3922 | (siu_coverage_ifc.sio_niu_data[81] == 1'b1)); | |
| 3923 | ||
| 3924 | sio_to_niu_header80 = ((siu_coverage_ifc.sio_niu_req == 1'b1) && // hdr vld. | |
| 3925 | (siu_coverage_ifc.sio_niu_data[127] == 1'b1) && // Response Bit | |
| 3926 | (siu_coverage_ifc.sio_niu_data[80] == 1'b1)); | |
| 3927 | ||
| 3928 | sio_to_dmu_header81 = ((siu_coverage_ifc.sio_dmu_req == 1'b1) && // hdr vld | |
| 3929 | (siu_coverage_ifc.sio_dmu_data[127:122] == 6'b101010) && // DMA Read Response | |
| 3930 | (siu_coverage_ifc.sio_dmu_data[81] == 1'b1)); | |
| 3931 | ||
| 3932 | sio_to_dmu_header80 = ((siu_coverage_ifc.sio_dmu_req == 1'b1) && // hdr vld | |
| 3933 | (siu_coverage_ifc.sio_dmu_data[127:122] == 6'b101010) && // DMA Read Response | |
| 3934 | (siu_coverage_ifc.sio_dmu_data[80] == 1'b1)); | |
| 3935 | ||
| 3936 | } | |
| 3937 | } | |
| 3938 | } | |
| 3939 | ||
| 3940 | ||
| 3941 | task fc_siu_ras_coverage::soc_niu_n_dmu_multi_ce_Err() | |
| 3942 | { | |
| 3943 | while(1) | |
| 3944 | { | |
| 3945 | @(negedge siu_ncu_ctag_ce.clk); | |
| 3946 | { | |
| 3947 | if((siu_ncu_ctag_ce.sii_ncu_dmuctag_ce == 1'b1) || (siu_ncu_ctag_ce.sii_ncu_niuctag_ce == 1'b1) || (siu_ncu_ctag_ce.sio_ncu_ctag_ce == 1'b1)) | |
| 3948 | { | |
| 3949 | sii_ncu_dmuctag_ce_seen = 1'b0; | |
| 3950 | sii_ncu_niuctag_ce_seen = 1'b0; | |
| 3951 | sio_ncu_ctag_ce_seen = 1'b0; | |
| 3952 | for(i=0; i< 10; i++) | |
| 3953 | { | |
| 3954 | @(posedge siu_ncu_ctag_ce.clk); | |
| 3955 | { | |
| 3956 | if(siu_ncu_ctag_ce.sii_ncu_dmuctag_ce == 1'b1) | |
| 3957 | { | |
| 3958 | sii_ncu_dmuctag_ce_seen = 1'b1; | |
| 3959 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :sii_ncu_dmuctag_ce_seen\n\n", get_time(LO))); | |
| 3960 | } | |
| 3961 | if(siu_ncu_ctag_ce.sii_ncu_niuctag_ce == 1'b1) | |
| 3962 | { | |
| 3963 | sii_ncu_niuctag_ce_seen = 1'b1; | |
| 3964 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :sii_ncu_niuctag_ce_seen\n\n", get_time(LO))); | |
| 3965 | } | |
| 3966 | if(siu_ncu_ctag_ce.sio_ncu_ctag_ce == 1'b1) | |
| 3967 | { | |
| 3968 | sio_ncu_ctag_ce_seen = 1'b1; | |
| 3969 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :sio_ncu_ctag_ce_seen\n\n", get_time(LO))); | |
| 3970 | } | |
| 3971 | } | |
| 3972 | } // for | |
| 3973 | if(sii_ncu_dmuctag_ce_seen && sii_ncu_niuctag_ce_seen && sio_ncu_ctag_ce_seen) | |
| 3974 | trigger(siu_ncu_ctag_ce_seen_trig); | |
| 3975 | ||
| 3976 | } // if | |
| 3977 | } // @ | |
| 3978 | }// while | |
| 3979 | ||
| 3980 | ||
| 3981 | ||
| 3982 | } | |
| 3983 | ||
| 3984 | // *********************************************************************************** | |
| 3985 | // FC NIU coverage Objects for MAQ | |
| 3986 | // *********************************************************************************** | |
| 3987 | ||
| 3988 | class fc_niu_coverage | |
| 3989 | { | |
| 3990 | // for dispmon | |
| 3991 | StandardDisplay dbg; | |
| 3992 | local string myname; | |
| 3993 | reg niu_npt_wr = 1'b0; | |
| 3994 | reg niu_npt_wr_count_en = 1'b0; | |
| 3995 | integer niu_npt_wr_count = 0; | |
| 3996 | integer window_1000 = 0; | |
| 3997 | integer niu_npt_wr_bw = 0; | |
| 3998 | reg niu_npt_wr_latency = 1'b0; | |
| 3999 | integer niu_npt_wr_latency_count = 0; | |
| 4000 | reg niu_npt_wr_latency_count_en = 1'b0; | |
| 4001 | ||
| 4002 | event niu_npt_wr_bandwith_trig; | |
| 4003 | event niu_npt_wr_latency_trig; | |
| 4004 | ||
| 4005 | // ----------- coverage_group ---------------- | |
| 4006 | coverage_group niu_npt_wr_bandwidth_1000cycles | |
| 4007 | { | |
| 4008 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 4009 | sample_event = sync (ANY, niu_npt_wr_bandwith_trig); | |
| 4010 | at_least = 1; | |
| 4011 | sample niu_npt_wr_bandwidth_1000cycles_window (niu_npt_wr_bw) | |
| 4012 | { | |
| 4013 | state S_niu_npt_wr_bandwidth_1000cycles_window (0:1000); | |
| 4014 | } | |
| 4015 | } | |
| 4016 | // ----------- coverage_group ---------------- | |
| 4017 | coverage_group niu_npt_wr_latency_cycles | |
| 4018 | { | |
| 4019 | const_sample_reference = 1; // ref. to sample vars. is constant | |
| 4020 | sample_event = sync (ANY, niu_npt_wr_latency_trig); | |
| 4021 | at_least = 1; | |
| 4022 | sample niu_npt_wr_latency_count | |
| 4023 | { | |
| 4024 | state S_niu_npt_wr_latency_5cycles (0:5) if ((niu_npt_wr_latency_count > 0) && (niu_npt_wr_latency_count <= 5)); | |
| 4025 | state S_niu_npt_wr_latency_10cycles (6:10) if ((niu_npt_wr_latency_count > 5) && (niu_npt_wr_latency_count <= 10)); | |
| 4026 | state S_niu_npt_wr_latency_15cycles (11:15) if ((niu_npt_wr_latency_count > 10) && (niu_npt_wr_latency_count <= 15)); | |
| 4027 | state S_niu_npt_wr_latency_20cycles (16:20) if ((niu_npt_wr_latency_count > 15) && (niu_npt_wr_latency_count <= 20)); | |
| 4028 | } | |
| 4029 | } | |
| 4030 | // ----------- coverage_group ---------------- | |
| 4031 | ||
| 4032 | ||
| 4033 | ||
| 4034 | ||
| 4035 | task new(StandardDisplay dbg); | |
| 4036 | task set_cov_cond_bits (); | |
| 4037 | ||
| 4038 | task niu_npt_wr_bandwith(); | |
| 4039 | task niu_npt_wr_latency_fn(); | |
| 4040 | ||
| 4041 | } | |
| 4042 | ||
| 4043 | task fc_niu_coverage::new(StandardDisplay dbg) | |
| 4044 | { | |
| 4045 | bit coverage_on = 0; | |
| 4046 | integer j; | |
| 4047 | ||
| 4048 | // for dispmon | |
| 4049 | myname = "fc_niu_coverage"; | |
| 4050 | this.dbg = dbg; | |
| 4051 | ||
| 4052 | if (mChkPlusarg(fc_niu_coverage) || mChkPlusarg(coverage_on)) { | |
| 4053 | coverage_on = 1; | |
| 4054 | } | |
| 4055 | ||
| 4056 | if (coverage_on) { | |
| 4057 | dbg.dispmon(myname, MON_ALWAYS, psprintf("\n\n %d :fc_niu_coverage Coverage turned \n\n", get_time(LO))); | |
| 4058 | ||
| 4059 | niu_npt_wr_bandwidth_1000cycles = new(); | |
| 4060 | niu_npt_wr_latency_cycles = new(); | |
| 4061 | set_cov_cond_bits (); | |
| 4062 | ||
| 4063 | } // if coverage_on | |
| 4064 | } // fc_niu_coverage::new() | |
| 4065 | ||
| 4066 | task fc_niu_coverage:: set_cov_cond_bits () | |
| 4067 | { | |
| 4068 | ||
| 4069 | fork | |
| 4070 | niu_npt_wr_bandwith(); | |
| 4071 | niu_npt_wr_latency_fn(); | |
| 4072 | join none | |
| 4073 | ||
| 4074 | } // task fc_niu_coverage:: set_cov_cond_bits | |
| 4075 | ||
| 4076 | task fc_niu_coverage::niu_npt_wr_bandwith() | |
| 4077 | { | |
| 4078 | while(1) | |
| 4079 | { | |
| 4080 | @(negedge siu_coverage_ifc.clk); | |
| 4081 | { | |
| 4082 | niu_npt_wr = ((siu_coverage_ifc.niudatareq == 1'b1) && | |
| 4083 | (siu_coverage_ifc.niureq == 1'b1) && | |
| 4084 | (siu_coverage_ifc.niubypass == 1'b0) && | |
| 4085 | (siu_coverage_ifc.niudata[127:122] == 6'b000010)); | |
| 4086 | ||
| 4087 | if((niu_npt_wr == 1'b1) && (niu_npt_wr_count_en == 1'b0)) | |
| 4088 | { | |
| 4089 | niu_npt_wr_count_en = 1'b1; | |
| 4090 | niu_npt_wr_count = 1; | |
| 4091 | window_1000 = 1; | |
| 4092 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Non-Posted Write Seen = \n\n", get_time(LO), niu_npt_wr_bw)); | |
| 4093 | } | |
| 4094 | else if((niu_npt_wr == 1'b1) && (niu_npt_wr_count_en == 1'b1) && (window_1000 < 'd1000)) | |
| 4095 | { | |
| 4096 | niu_npt_wr_count = niu_npt_wr_count + 1; | |
| 4097 | window_1000 = window_1000 + 1; | |
| 4098 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Non-Posted Write Again = \n\n", get_time(LO), niu_npt_wr_bw)); | |
| 4099 | } | |
| 4100 | else if((niu_npt_wr_count_en == 1'b1) && (window_1000 == 'd1000)) | |
| 4101 | { | |
| 4102 | niu_npt_wr_bw = (window_1000/niu_npt_wr_count); | |
| 4103 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Non-Posted Write Band-width = %d \n\n", get_time(LO), niu_npt_wr_bw)); | |
| 4104 | trigger(niu_npt_wr_bandwith_trig); | |
| 4105 | niu_npt_wr_count_en = 1'b0; | |
| 4106 | niu_npt_wr_count = 0; | |
| 4107 | window_1000 = 0; | |
| 4108 | } | |
| 4109 | else if((niu_npt_wr == 1'b0) && (niu_npt_wr_count_en == 1'b1) && (window_1000 < 'd1000)) | |
| 4110 | { | |
| 4111 | window_1000 = window_1000 + 1; | |
| 4112 | } | |
| 4113 | } | |
| 4114 | } | |
| 4115 | } | |
| 4116 | ||
| 4117 | task fc_niu_coverage::niu_npt_wr_latency_fn() | |
| 4118 | { | |
| 4119 | while(1) | |
| 4120 | { | |
| 4121 | @(negedge siu_coverage_ifc.clk); | |
| 4122 | { | |
| 4123 | niu_npt_wr_latency = ((siu_coverage_ifc.niudatareq == 1'b1) && | |
| 4124 | (siu_coverage_ifc.niureq == 1'b1) && | |
| 4125 | (siu_coverage_ifc.niubypass == 1'b0) && | |
| 4126 | (siu_coverage_ifc.niudata[127:122] == 6'b000010)); | |
| 4127 | ||
| 4128 | if((niu_npt_wr_latency == 1'b1) && (niu_npt_wr_latency_count_en == 1'b0)) | |
| 4129 | { | |
| 4130 | niu_npt_wr_latency_count = 1; | |
| 4131 | niu_npt_wr_latency_count_en = 1'b1; | |
| 4132 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Non-Posted Write Latency seen \n\n", get_time(LO))); | |
| 4133 | } | |
| 4134 | else if((niu_npt_wr_latency == 1'b1) && (niu_npt_wr_latency_count_en == 1'b1)) | |
| 4135 | { | |
| 4136 | niu_npt_wr_latency_count = 1; | |
| 4137 | niu_npt_wr_latency_count_en = 1'b1; | |
| 4138 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Non-Posted Write Latency seen again \n\n", get_time(LO))); | |
| 4139 | } | |
| 4140 | else if((niu_npt_wr_latency == 1'b0) && (niu_npt_wr_latency_count_en == 1'b1) && (siu_coverage_ifc.niuoqdq == 1'b0)) | |
| 4141 | { | |
| 4142 | niu_npt_wr_latency_count = niu_npt_wr_latency_count + 1; | |
| 4143 | niu_npt_wr_latency_count_en = 1'b1; | |
| 4144 | } | |
| 4145 | else if((niu_npt_wr_latency == 1'b0) && (niu_npt_wr_latency_count_en == 1'b1) && (siu_coverage_ifc.niuoqdq == 1'b1)) | |
| 4146 | { | |
| 4147 | dbg.dispmon(myname, MON_INFO, psprintf("\n\n %d :Non-Posted Write Latency = %d \n\n", get_time(LO), niu_npt_wr_latency_count)); | |
| 4148 | trigger(niu_npt_wr_latency_trig); | |
| 4149 | niu_npt_wr_latency_count_en = 1'b0; | |
| 4150 | } | |
| 4151 | } | |
| 4152 | } | |
| 4153 | ||
| 4154 | } | |
| 4155 |