Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_ildq6_rd_sample.vrhpal
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: siu_ildq6_rd_sample.vrhpal
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34// ========== Copyright Header End ============================================
35sample siu_coverage_ildq6.rd_adr
36{
37 state s_ILDQ6_EMPTY (0:31) if (ildq6_size == 0);
38 state s_ILDQ6_BACK_TO_BACK_RD (0:31) if (ildq6_rd_b2b == 2);
39 // this happens in 2 cycles since each
40 // cycle take 32 bits and its reading 64 bits
41 state s_ILDQ6_RD_WR (0:31) if (siu_coverage_ildq6.wr_en === 1'b1);
42
43 trans t_ILDQ6_RD_ADR_00 ( 0 -> 1);
44 trans t_ILDQ6_RD_ADR_01 ( 1 -> 2);
45 trans t_ILDQ6_RD_ADR_02 ( 2 -> 3);
46 trans t_ILDQ6_RD_ADR_03 ( 3 -> 4);
47 trans t_ILDQ6_RD_ADR_04 ( 4 -> 5);
48 trans t_ILDQ6_RD_ADR_05 ( 5 -> 6);
49 trans t_ILDQ6_RD_ADR_06 ( 6 -> 7);
50 trans t_ILDQ6_RD_ADR_07 ( 7 -> 8);
51 trans t_ILDQ6_RD_ADR_08 ( 8 -> 9);
52 trans t_ILDQ6_RD_ADR_09 ( 9 -> 10);
53 trans t_ILDQ6_RD_ADR_10 (10 -> 11);
54 trans t_ILDQ6_RD_ADR_11 (11 -> 12);
55 trans t_ILDQ6_RD_ADR_12 (12 -> 13);
56 trans t_ILDQ6_RD_ADR_13 (13 -> 14);
57 trans t_ILDQ6_RD_ADR_14 (14 -> 15);
58 trans t_ILDQ6_RD_ADR_15 (15 -> 16);
59 trans t_ILDQ6_RD_ADR_16 (16 -> 17);
60 trans t_ILDQ6_RD_ADR_17 (17 -> 18);
61 trans t_ILDQ6_RD_ADR_18 (18 -> 19);
62 trans t_ILDQ6_RD_ADR_19 (19 -> 20);
63 trans t_ILDQ6_RD_ADR_20 (20 -> 21);
64 trans t_ILDQ6_RD_ADR_21 (21 -> 22);
65 trans t_ILDQ6_RD_ADR_22 (22 -> 23);
66 trans t_ILDQ6_RD_ADR_23 (23 -> 24);
67 trans t_ILDQ6_RD_ADR_24 (24 -> 25);
68 trans t_ILDQ6_RD_ADR_25 (25 -> 26);
69 trans t_ILDQ6_RD_ADR_26 (26 -> 27);
70 trans t_ILDQ6_RD_ADR_27 (27 -> 28);
71 trans t_ILDQ6_RD_ADR_28 (28 -> 29);
72 trans t_ILDQ6_RD_ADR_29 (29 -> 30);
73 trans t_ILDQ6_RD_ADR_30 (30 -> 31);
74 trans t_ILDQ6_RD_ADR_31 (31 -> 0);
75}