Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_niu_dmu_cmd_sample.vrhpal

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// 
// OpenSPARC T2 Processor File: siu_niu_dmu_cmd_sample.vrhpal
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#inc "siu_cov_inc.pal";

#ifndef SIU_INTF_COV
. for ($i=0; $i<5; $i++)
. {
sample arb_niu_cmd_sample_${i}_clk_this (this_niu_cmd)
{
  state RDD_ord        ( 7'b0010_100 ) if (niu_dmu_back_to_back==$i);
  state RDD_byp        ( 7'b0010_101 ) if (niu_dmu_back_to_back==$i);
  state WRI_npt_ord    ( 7'b0000_100 ) if (niu_dmu_back_to_back==$i);
  state WRI_npt_byp    ( 7'b0000_101 ) if (niu_dmu_back_to_back==$i);
  state WRI_pst_ord    ( 7'b0100_100 ) if (niu_dmu_back_to_back==$i);
  state WRI_pst_byp    ( 7'b0100_101 ) if (niu_dmu_back_to_back==$i);

  cov_weight = 0;
}
. }

sample arb_dmu_cmd_sample_this (this_dmu_cmd)
{
  state RDD_ord          ( 7'b0010_100 );
  state WRI_pstd_ord     ( 7'b0100_100 );
  state WRM_pstd_ord     ( 7'b0101_100 );
  state PIO_RD_RET       ( 7'b1010_011 );
  state INT              ( 7'b0000_010 );

  cov_weight = 0;
}


. for ($i=0; $i<5; $i++)
. {
    cross siu_arb_niu_dmu_${i}_clk_cross (arb_niu_cmd_sample_${i}_clk_this, arb_dmu_cmd_sample_this); 
. }


#else
// FC
. for ($i=0; $i<3; $i++)
. {
sample arb_niu_cmd_sample_${i}_clk_this (this_niu_cmd)
{
  state RDD_byp        ( 7'b0010_101 ) if (niu_dmu_back_to_back==$i);
  state WRI_npt_ord    ( 7'b0000_100 ) if (niu_dmu_back_to_back==$i);
  state WRI_pst_byp    ( 7'b0100_101 ) if (niu_dmu_back_to_back==$i);

  cov_weight = 0;
}
. }

sample arb_dmu_cmd_sample_this (this_dmu_cmd)
{
  state RDD_ord          ( 7'b0010_100 );
  state WRI_pstd_ord     ( 7'b0100_100 );
  state WRM_pstd_ord     ( 7'b0101_100 );
  state PIO_RD_RET       ( 7'b1010_011 );
  state INT              ( 7'b0000_010 );

  cov_weight = 0;
}

. for ($i=0; $i<3; $i++)
. {
    cross siu_arb_niu_dmu_${i}_clk_cross (arb_niu_cmd_sample_${i}_clk_this, arb_dmu_cmd_sample_this);
. }
#endif


//FC: another Flexible version
sample arb_niu_cmd_sample_this_fc (this_niu_cmd)
{
  state RDD_byp        ( 7'b0010_101 ) if ((niu_dmu_back_to_back==0) || (niu_dmu_back_to_back==1) || (niu_dmu_back_to_back==2) || (niu_dmu_back_to_back==3));
  state WRI_npt_ord    ( 7'b0000_100 ) if ((niu_dmu_back_to_back==0) || (niu_dmu_back_to_back==1) || (niu_dmu_back_to_back==2) || (niu_dmu_back_to_back==3));
  state WRI_pst_byp    ( 7'b0100_101 ) if ((niu_dmu_back_to_back==0) || (niu_dmu_back_to_back==1) || (niu_dmu_back_to_back==2) || (niu_dmu_back_to_back==3));

  cov_weight = 0;
}

sample arb_dmu_cmd_sample_this_fc (this_dmu_cmd)
{
  state RDD_ord          ( 7'b0010_100 );
  state WRI_pstd_ord     ( 7'b0100_100 );
  state WRM_pstd_ord     ( 7'b0101_100 );
  state PIO_RD_RET       ( 7'b1010_011 );
  state INT              ( 7'b0000_010 );

  cov_weight = 0;
}

cross siu_arb_niu_dmu_fc_cross (arb_niu_cmd_sample_this_fc, arb_dmu_cmd_sample_this_fc);