Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / coverage / siu / siu_opddq00_wr_sample.vrh

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// 
// OpenSPARC T2 Processor File: siu_opddq00_wr_sample.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
sample siu_coverage_opddq00_wr.wr_adr
{

state s_OPDDQ00_RD_WR		(0:63) if (siu_coverage_opddq00_rd.rd_en === 1'b1 );
state s_OPDDQ00_BACK_TO_BACK_WR	(0:63) if (opddq00_wr_b2b == 2);

trans t_OPDDQ00_WR_ADR_00 	( 0 ->  1);
trans t_OPDDQ00_WR_ADR_01 	( 1 ->  2);
trans t_OPDDQ00_WR_ADR_02 	( 2 ->  3);
trans t_OPDDQ00_WR_ADR_03 	( 3 ->  4);
trans t_OPDDQ00_WR_ADR_04 	( 4 ->  5);
trans t_OPDDQ00_WR_ADR_05 	( 5 ->  6);
trans t_OPDDQ00_WR_ADR_06 	( 6 ->  7);
trans t_OPDDQ00_WR_ADR_07 	( 7 ->  8);
trans t_OPDDQ00_WR_ADR_08 	( 8 ->  9);
trans t_OPDDQ00_WR_ADR_09 	( 9 -> 10);
trans t_OPDDQ00_WR_ADR_10 	(10 -> 11);
trans t_OPDDQ00_WR_ADR_11 	(11 -> 12);
trans t_OPDDQ00_WR_ADR_12 	(12 -> 13);
trans t_OPDDQ00_WR_ADR_13 	(13 -> 14);
trans t_OPDDQ00_WR_ADR_14 	(14 -> 15);
trans t_OPDDQ00_WR_ADR_15 	(15 -> 16);
trans t_OPDDQ00_WR_ADR_16 	(16 -> 17);
trans t_OPDDQ00_WR_ADR_17 	(17 -> 18);
trans t_OPDDQ00_WR_ADR_18 	(18 -> 19);
trans t_OPDDQ00_WR_ADR_19 	(19 -> 20);
trans t_OPDDQ00_WR_ADR_20 	(20 -> 21);
trans t_OPDDQ00_WR_ADR_21 	(21 -> 22);
trans t_OPDDQ00_WR_ADR_22 	(22 -> 23);
trans t_OPDDQ00_WR_ADR_23 	(23 -> 24);
trans t_OPDDQ00_WR_ADR_24 	(24 -> 25);
trans t_OPDDQ00_WR_ADR_25 	(25 -> 26);
trans t_OPDDQ00_WR_ADR_26 	(26 -> 27);
trans t_OPDDQ00_WR_ADR_27 	(27 -> 28);
trans t_OPDDQ00_WR_ADR_28 	(28 -> 29);
trans t_OPDDQ00_WR_ADR_29 	(29 -> 30);
trans t_OPDDQ00_WR_ADR_30 	(30 -> 31);
trans t_OPDDQ00_WR_ADR_31 	(31 -> 32);
trans t_OPDDQ00_WR_ADR_32 	(32 -> 33);
trans t_OPDDQ00_WR_ADR_33 	(33 -> 34);
trans t_OPDDQ00_WR_ADR_34 	(34 -> 35);
trans t_OPDDQ00_WR_ADR_35 	(35 -> 36);
trans t_OPDDQ00_WR_ADR_36 	(36 -> 37);
trans t_OPDDQ00_WR_ADR_37 	(37 -> 38);
trans t_OPDDQ00_WR_ADR_38 	(38 -> 39);
trans t_OPDDQ00_WR_ADR_39 	(39 -> 40);
trans t_OPDDQ00_WR_ADR_40 	(40 -> 41);
trans t_OPDDQ00_WR_ADR_41 	(41 -> 42);
trans t_OPDDQ00_WR_ADR_42 	(42 -> 43);
trans t_OPDDQ00_WR_ADR_43 	(43 -> 44);
trans t_OPDDQ00_WR_ADR_44 	(44 -> 45);
trans t_OPDDQ00_WR_ADR_45 	(45 -> 46);
trans t_OPDDQ00_WR_ADR_46 	(46 -> 47);
trans t_OPDDQ00_WR_ADR_47 	(47 -> 48);
trans t_OPDDQ00_WR_ADR_48 	(48 -> 49);
trans t_OPDDQ00_WR_ADR_49 	(49 -> 50);
trans t_OPDDQ00_WR_ADR_50 	(50 -> 51);
trans t_OPDDQ00_WR_ADR_51 	(51 -> 52);
trans t_OPDDQ00_WR_ADR_52 	(52 -> 53);
trans t_OPDDQ00_WR_ADR_53 	(53 -> 54);
trans t_OPDDQ00_WR_ADR_54 	(54 -> 55);
trans t_OPDDQ00_WR_ADR_55 	(55 -> 56);
trans t_OPDDQ00_WR_ADR_56 	(56 -> 57);
trans t_OPDDQ00_WR_ADR_57 	(57 -> 58);
trans t_OPDDQ00_WR_ADR_58 	(58 -> 59);
trans t_OPDDQ00_WR_ADR_59 	(59 -> 60);
trans t_OPDDQ00_WR_ADR_60 	(60 -> 61);
trans t_OPDDQ00_WR_ADR_61 	(61 -> 62);
trans t_OPDDQ00_WR_ADR_62 	(62 -> 63);
trans t_OPDDQ00_WR_ADR_63 	(63 ->  0);

// bad state
bad_state s_OPDDQ00_FULL	(0:63) if (opddq00_size == 64);

}