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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / pli / global_chkr / c / src / global_chkr.c
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: global_chkr.c
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#include "global_chkr.h"
39
40void global_chkr_l1dump()
41{
42 s_tfnodeinfo node_info;
43 int core;
44 int dc_way;
45 int ic_way;
46 int arg = 3;
47 int cores_in_model;
48
49 core_present = tf_getp(1);
50 cores_in_model = tf_getp(2);
51
52 sample_plusargs();
53
54 if (gchkr_debug)
55 io_printf("core_present = %0x, cores_in_model = %0x\n", core_present, cores_in_model);
56 for (core = 0; core < 8; core++)
57 {
58 if (cores_in_model >> core & 1)
59 {
60 for (dc_way = 0; dc_way < 4; dc_way++)
61 {
62 if (!tf_nodeinfo(arg, &node_info))
63 io_printf("ERROR: DC%0d, way %0d getting node_info.\n", core, dc_way);
64 /*
65 switch (node_info.node_type)
66 {
67 case TF_MEMORY_NODE:
68 io_printf("DC%0d, way %0d is memory node\n", core, dc_way); break;
69 default:
70 io_printf("ERROR: DC%0d, way %0d. Unexpected node_type = %0d.\n", core, dc_way, node_info.node_type); break;
71 }
72
73 io_printf("dc_array node_ngroups = %d\n", node_info.node_ngroups);
74 io_printf("dc_array node_mem_size = %d\n", node_info.node_mem_size);
75 */
76
77 l1vars.dtag[core][dc_way] = node_info.node_value.memoryval_p;
78 l1vars.dtag_ngroups = node_info.node_ngroups;
79 l1vars.dtag_mem_size = node_info.node_mem_size;
80 arg++;
81 }
82
83 for (ic_way = 0; ic_way < 8; ic_way++)
84 {
85 if (!tf_nodeinfo(arg, &node_info))
86 io_printf("ERROR: IC%0d, way %0d getting node_info.\n", core, ic_way);
87
88 /*
89 switch (node_info.node_type)
90 {
91 case TF_MEMORY_NODE:
92 io_printf("IC%0d, way %0d is memory node\n", core, ic_way); break;
93 default:
94 io_printf("ERROR: IC%0d, way %0d. Unexpected node_type = %0d.\n", core, ic_way, node_info.node_type); break;
95 }
96
97 io_printf("ic_array node_ngroups = %d\n", node_info.node_ngroups);
98 io_printf("ic_array node_mem_size = %d\n", node_info.node_mem_size);
99 */
100
101 l1vars.itag[core][ic_way] = node_info.node_value.memoryval_p;
102 l1vars.itag_ngroups = node_info.node_ngroups;
103 l1vars.itag_mem_size = node_info.node_mem_size;
104 arg++;
105 }
106
107 if (!tf_nodeinfo(arg++, &node_info))
108 io_printf("ERROR: DC%0d getting node_info for vld array\n", core);
109 l1vars.dvld[core] = node_info.node_value.memoryval_p;
110 l1vars.dvld_ngroups = node_info.node_ngroups;
111 l1vars.dvld_mem_size = node_info.node_mem_size;
112
113 //io_printf("dvld_array node_ngroups = %d\n", node_info.node_ngroups);
114 //io_printf("dvld_array node_mem_size = %d\n", node_info.node_mem_size);
115
116 if (!tf_nodeinfo(arg++, &node_info))
117 io_printf("ERROR: IC%0d getting node_info for vld array\n", core);
118 l1vars.ivld[core] = node_info.node_value.memoryval_p;
119 l1vars.ivld_ngroups = node_info.node_ngroups;
120 l1vars.ivld_mem_size = node_info.node_mem_size;
121
122 //io_printf("ivld_array node_ngroups = %d\n", node_info.node_ngroups);
123 //io_printf("ivld_array node_mem_size = %d\n", node_info.node_mem_size);
124 }
125 }
126}
127
128void global_chkr_read_l2_tag()
129{
130 s_tfnodeinfo node_info;
131 int arg = 1;
132 int bank;
133 int way_bank;
134
135 for (bank = 0; bank < 8; bank++)
136 {
137 for (way_bank = 0; way_bank < 8; way_bank++)
138 {
139 if (!tf_nodeinfo(arg++, &node_info))
140 io_printf("ERROR: L2T: Bank=%0d, left way_bank=%0d getting node_info.\n", bank, way_bank);
141 if (node_info.node_type != TF_MEMORY_NODE)
142 io_printf("ERROR: L2T: Bank=%0d, left way_bank=%0d. Unexpected node_type = %0d.\n", bank, way_bank, node_info.node_type);
143
144 //io_printf("l2t_array node_ngroups = %d\n", node_info.node_ngroups);
145 //io_printf("l2t_array node_mem_size = %d\n", node_info.node_mem_size);
146
147 l2vars.l2t_lft[bank][way_bank] = node_info.node_value.memoryval_p;
148 if (l2vars.l2t_lft_ngroups == 0)
149 l2vars.l2t_lft_ngroups = node_info.node_ngroups;
150 else
151 { if (l2vars.l2t_lft_ngroups != node_info.node_ngroups)
152 io_printf("ERROR: L2T: Bank=%0d, left way_bank=%0d. l2vars.l2t_lft_ngroups(%0d) != node_info.node_ngroups(%0d).\n", bank, way_bank, l2vars.l2t_lft_ngroups, node_info.node_ngroups);
153 }
154
155 if (l2vars.l2t_lft_mem_size == 0)
156 l2vars.l2t_lft_mem_size = node_info.node_mem_size;
157 else
158 { if (l2vars.l2t_lft_mem_size != node_info.node_mem_size)
159 io_printf("ERROR: L2T: Bank=%0d, left way_bank=%0d. l2vars.l2t_lft_mem_size(%0d) != node_info.node_mem_size(%0d).\n", bank, way_bank, l2vars.l2t_lft_mem_size, node_info.node_mem_size);
160 }
161
162 if (!tf_nodeinfo(arg++, &node_info))
163 io_printf("ERROR: L2T: Bank=%0d, rt way_bank=%0d getting node_info.\n", bank, way_bank);
164 if (node_info.node_type != TF_MEMORY_NODE)
165 io_printf("ERROR: L2T: Bank=%0d, rt way_bank=%0d. Unexpected node_type = %0d.\n", bank, way_bank, node_info.node_type);
166
167 //io_printf("l2t_array node_ngroups = %d\n", node_info.node_ngroups);
168 //io_printf("l2t_array node_mem_size = %d\n", node_info.node_mem_size);
169
170 l2vars.l2t_rgt[bank][way_bank] = node_info.node_value.memoryval_p;
171 if (l2vars.l2t_rgt_ngroups == 0)
172 l2vars.l2t_rgt_ngroups = node_info.node_ngroups;
173 else
174 { if (l2vars.l2t_rgt_ngroups != node_info.node_ngroups)
175 io_printf("ERROR: L2T: Bank=%0d, rt way_bank=%0d. l2vars.l2t_rgt_ngroups(%0d) != node_info.node_ngroups(%0d).\n", bank, way_bank, l2vars.l2t_rgt_ngroups, node_info.node_ngroups);
176 }
177
178 if (l2vars.l2t_rgt_mem_size == 0)
179 l2vars.l2t_rgt_mem_size = node_info.node_mem_size;
180 else
181 { if (l2vars.l2t_rgt_mem_size != node_info.node_mem_size)
182 io_printf("ERROR: L2T: Bank=%0d, rt way_bank=%0d. l2vars.l2t_rgt_mem_size(%0d) != node_info.node_mem_size(%0d).\n", bank, way_bank, l2vars.l2t_rgt_mem_size, node_info.node_mem_size);
183 }
184 } //for way_bank
185 } //for bank
186}
187
188void global_chkr_read_l2_dc_dir()
189{
190 s_tfnodeinfo node_info;
191 int arg = 1;
192 int bank;
193 int panel;
194
195 for (bank = 0; bank < 8; bank++)
196 {
197 for (panel = 0; panel < 8; panel++)
198 {
199 if (!tf_nodeinfo(arg++, &node_info))
200 io_printf("ERROR: L2_ddir: Bank=%0d, panel=%0d getting node_info.\n", bank, panel);
201 if (node_info.node_type != TF_MEMORY_NODE)
202 io_printf("ERROR: L2_ddir: Bank=%0d, panel=%0d. Unexpected node_type = %0d.\n", bank, panel, node_info.node_type);
203
204 //io_printf("l2_ddir node_ngroups = %d\n", node_info.node_ngroups);
205 //io_printf("l2_ddir node_mem_size = %d\n", node_info.node_mem_size);
206
207 l2vars.l2_ddir[bank][panel] = node_info.node_value.memoryval_p;
208 if (l2vars.l2ddir_ngroups == 0)
209 l2vars.l2ddir_ngroups = node_info.node_ngroups;
210 else
211 { if (l2vars.l2ddir_ngroups != node_info.node_ngroups)
212 io_printf("ERROR: L2T: Bank=%0d, panel=%0d. l2vars.l2ddir_ngroups(%0d) != node_info.node_ngroups(%0d).\n", bank, panel, l2vars.l2ddir_ngroups, node_info.node_ngroups);
213 }
214
215 if (l2vars.l2ddir_mem_size == 0)
216 l2vars.l2ddir_mem_size = node_info.node_mem_size;
217 else
218 { if (l2vars.l2ddir_mem_size != node_info.node_mem_size)
219 io_printf("ERROR: L2T: Bank=%0d, panel=%0d. l2vars.l2ddir_mem_size(%0d) != node_info.node_mem_size(%0d).\n", bank, panel, l2vars.l2ddir_mem_size, node_info.node_mem_size);
220 }
221
222 if (!tf_nodeinfo(arg++, &node_info))
223 io_printf("ERROR: L2_dvld: Bank=%0d, panel=%0d getting node_info.\n", bank, panel);
224 if (node_info.node_type != TF_REG_NODE)
225 io_printf("ERROR: L2_dvld: Bank=%0d, panel=%0d. Unexpected node_type = %0d.\n", bank, panel, node_info.node_type);
226
227 //io_printf("l2_dvld node_ngroups = %d\n", node_info.node_ngroups);
228
229 l2vars.l2_dvld[bank][panel] = node_info.node_value.vecval_p;
230 if (l2vars.l2dvld_ngroups == 0)
231 l2vars.l2dvld_ngroups = node_info.node_ngroups;
232 else
233 { if (l2vars.l2dvld_ngroups != node_info.node_ngroups)
234 io_printf("ERROR: L2T: Bank=%0d, panel=%0d. l2vars.l2dvld_ngroups(%0d) != node_info.node_ngroups(%0d).\n", bank, panel, l2vars.l2dvld_ngroups, node_info.node_ngroups);
235 }
236 } //panel
237 } //bank
238}
239
240void global_chkr_read_l2_ic_dir()
241{
242 s_tfnodeinfo node_info;
243 int arg = 1;
244 int bank;
245 int panel;
246
247 for (bank = 0; bank < 8; bank++)
248 {
249 for (panel = 0; panel < 8; panel++)
250 {
251 if (!tf_nodeinfo(arg++, &node_info))
252 io_printf("ERROR: L2_idir: Bank=%0d, panel=%0d getting node_info.\n", bank, panel);
253 if (node_info.node_type != TF_MEMORY_NODE)
254 io_printf("ERROR: L2_idir: Bank=%0d, panel=%0d. Unexpected node_type = %0d.\n", bank, panel, node_info.node_type);
255
256 //io_printf("l2_idir node_ngroups = %d\n", node_info.node_ngroups);
257 //io_printf("l2_idir node_mem_size = %d\n", node_info.node_mem_size);
258
259 l2vars.l2_idir[bank][panel] = node_info.node_value.memoryval_p;
260 if (l2vars.l2idir_ngroups == 0)
261 l2vars.l2idir_ngroups = node_info.node_ngroups;
262 else
263 { if (l2vars.l2idir_ngroups != node_info.node_ngroups)
264 io_printf("ERROR: L2T: Bank=%0d, panel=%0d. l2vars.l2idir_ngroups(%0d) != node_info.node_ngroups(%0d).\n", bank, panel, l2vars.l2idir_ngroups, node_info.node_ngroups);
265 }
266
267 if (l2vars.l2idir_mem_size == 0)
268 l2vars.l2idir_mem_size = node_info.node_mem_size;
269 else
270 { if (l2vars.l2idir_mem_size != node_info.node_mem_size)
271 io_printf("ERROR: L2T: Bank=%0d, panel=%0d. l2vars.l2idir_mem_size(%0d) != node_info.node_mem_size(%0d).\n", bank, panel, l2vars.l2idir_mem_size, node_info.node_mem_size);
272 }
273
274 if (!tf_nodeinfo(arg++, &node_info))
275 io_printf("ERROR: L2_ivld: Bank=%0d, panel=%0d getting node_info.\n", bank, panel);
276 if (node_info.node_type != TF_REG_NODE)
277 io_printf("ERROR: L2_ivld: Bank=%0d, panel=%0d. Unexpected node_type = %0d.\n", bank, panel, node_info.node_type);
278
279 //io_printf("l2_ivld node_ngroups = %d\n", node_info.node_ngroups);
280 //io_printf("l2_ivld node_mem_size = %d\n", node_info.node_mem_size);
281
282 l2vars.l2_ivld[bank][panel] = node_info.node_value.vecval_p;
283 if (l2vars.l2ivld_ngroups == 0)
284 l2vars.l2ivld_ngroups = node_info.node_ngroups;
285 else
286 { if (l2vars.l2ivld_ngroups != node_info.node_ngroups)
287 io_printf("ERROR: L2T: Bank=%0d, panel=%0d. l2vars.l2ivld_ngroups(%0d) != node_info.node_ngroups(%0d).\n", bank, panel, l2vars.l2ivld_ngroups, node_info.node_ngroups);
288 }
289
290 } //panel
291 } //bank
292}
293
294void global_chkr_cmp_l1_data()
295{
296 int bank = 0;
297 int panel = 0;
298 int dc_err_cnt = 0;
299 int ic_err_cnt = 0;
300 int exc_err = 0;
301
302 bank = tf_getp(1);
303
304 for (panel = 0; panel < 8; panel++)
305 {
306 init_chkr_caches(bank, panel);
307 //if (gchkr_debug) disp_chkr_caches();
308 create_dcdir(bank, panel);
309 dc_err_cnt = dc_err_cnt + cmp_dcdir(bank, panel);
310 create_icdir(bank, panel);
311 ic_err_cnt = ic_err_cnt + cmp_icdir(bank, panel);
312 exc_err = exc_err + chk_ic_dc_exclusion(bank, panel);
313 }
314
315 tf_putp(2, dc_err_cnt);
316 tf_putp(3, ic_err_cnt);
317 tf_putp(4, exc_err);
318
319}
320
321void init_chkr_caches(int bank, int panel)
322{
323 int core;
324 int entry;
325
326 for (core = 0; core < 8; core++)
327 {
328 if (core_present >> core & 1)
329 {
330 for (entry = 0; entry < DC_ENTRIES_PER_PANEL; entry++)
331 {
332 l1vars.dc[core][entry].valid = 0;
333 l1vars.dc[core][entry].l2_index = 0;
334 l1vars.dc[core][entry].l2_way = 0;
335 l1vars.dc[core][entry].l2_pa = 0;
336 }
337 for (entry = 0; entry < IC_ENTRIES_PER_PANEL; entry++)
338 {
339 l1vars.ic[core][entry].valid = 0;
340 l1vars.ic[core][entry].l2_index = 0;
341 l1vars.ic[core][entry].l2_way = 0;
342 l1vars.ic[core][entry].l2_pa = 0;
343 }
344 }
345 }
346 if (gchkr_debug)
347 io_printf("L2Bank%0d, Panel%0d: Caches are init.\n", bank, panel);
348}
349
350void disp_chkr_caches(void)
351{
352 int core;
353 int entry;
354
355 io_printf("I AM CALLED\n");
356
357
358 for (core = 0; core < 8; core++)
359 {
360 io_printf("core = %0d \n", core);
361 if (core_present >> core & 1)
362 {
363 io_printf("CHKR L2D DATA\n");
364 io_printf("ENT\tVLD\tL2_IND\tWAY\tPA\n");
365 for (entry = 0; entry < DC_ENTRIES_PER_PANEL; entry++)
366 {
367 l1vars.dc[core][entry].valid = 0;
368 l1vars.dc[core][entry].l2_index = 0;
369 l1vars.dc[core][entry].l2_way = 0;
370 l1vars.dc[core][entry].l2_pa = 0;
371 io_printf("%0x\t%0x\t%0x\t%0x\t%0x\n", entry, l1vars.dc[core][entry].valid, l1vars.dc[core][entry].l2_index, l1vars.dc[core][entry].l2_way, l1vars.dc[core][entry].l2_pa);
372 }
373 io_printf("CHKR L2I DATA\n");
374 io_printf("ENT\tVLD\tL2_IND\tWAY\tPA\n");
375 for (entry = 0; entry < IC_ENTRIES_PER_PANEL; entry++)
376 {
377 l1vars.ic[core][entry].valid = 0;
378 l1vars.ic[core][entry].l2_index = 0;
379 l1vars.ic[core][entry].l2_way = 0;
380 l1vars.ic[core][entry].l2_pa = 0;
381 io_printf("%0x\t%0x\t%0x\t%0x\t%0x\n", entry, l1vars.ic[core][entry].valid, l1vars.ic[core][entry].l2_index, l1vars.ic[core][entry].l2_way, l1vars.ic[core][entry].l2_pa);
382 }
383 }
384 } //core
385}
386
387void create_dcdir(int bank, int panel)
388{
389 int addr;
390 int group_num;
391 int vld;
392 int word;
393 int core;
394 int caddr = 0;
395 char *aval_ptr;
396 int bit_5 = 0;
397 int bit_4 = 0;
398 int l2way, l2index, l2tag;
399 int word_increment;
400
401 for (addr = 0; addr < l2vars.l2ddir_mem_size; addr++)
402 {
403 word_increment = l2vars.l2ddir_ngroups * 2;
404 aval_ptr = l2vars.l2_ddir[bank][panel] + (word_increment * addr);
405 vld = get_l2dir_vld(bank, panel, addr, DC);
406 if (vld)
407 {
408 word = 0;
409 for (group_num = l2vars.l2ddir_ngroups - 1; group_num >= 0; group_num--)
410 {
411 word <<= 8;
412 word |= aval_ptr[group_num] & 0xff;
413 }
414 l2way = word & 0xf;
415 l2index = word >> 4 & 0x1ff;
416 l2tag = get_l2tag(bank, l2index, l2way);
417 if (panel > 3)
418 bit_5 = 1;
419 bit_4 = addr >> 5 & 1;
420
421 //cache_addr = bits 10:9, bits 5:4, way [1:0]
422 //To access the directory L2$ uses a 6 bits address decodes as:
423 //bit 4, cpuid[2:0], way [1:0]
424
425 caddr = bit_4 << 2 | (addr & 0x3);
426 core = addr >> 2 & 0x7;
427 //io_printf("L2D_DIR: ENTRY: Bank = %0x, panel = %0x, core = %0x, dir_addr = %0x, l2tag = %x, l2_index = %x, l2way = %x, caddr = %x\n", bank, panel, core, addr, l2tag, l2index, l2way, caddr);
428
429 if ((core_present & 1 << core) == 0)
430 io_printf("L2D_DIR: ERROR: Core not present while entry present in l2d_dir. Bank = %0x, panel = %0x, dir_addr = %0x, l2tag = %x, l2_index = %x, l2way = %x, caddr = %x\n", bank, panel, addr, l2tag, l2index, l2way, caddr);
431
432 l1vars.dc[core][caddr].valid = 1;
433 l1vars.dc[core][caddr].l2_index = l2index;
434 l1vars.dc[core][caddr].l2_way = l2way;
435 l1vars.dc[core][caddr].l2_pa = l2tag;
436
437 } //if vld
438 } //for adr
439 if (gchkr_debug)
440 {
441 dump_l2dcdir(bank, panel);
442 }
443}
444
445void create_icdir(int bank, int panel)
446{
447 int addr;
448 int group_num;
449 int vld;
450 int word;
451 int core;
452 int caddr;
453 char *aval_ptr;
454 int bit_5 = 0;
455 int l2way, l2index, l2tag;
456 int word_increment;
457 int way_2 = 0;
458
459 for (addr = 0; addr < l2vars.l2idir_mem_size; addr++)
460 {
461 word_increment = l2vars.l2idir_ngroups * 2;
462 aval_ptr = l2vars.l2_idir[bank][panel] + (word_increment * addr);
463 vld = get_l2dir_vld(bank, panel, addr, IC);
464 if (vld)
465 {
466 word = 0;
467 for (group_num = l2vars.l2idir_ngroups - 1; group_num >= 0; group_num--)
468 {
469 word <<= 8;
470 word |= aval_ptr[group_num] & 0xff;
471 }
472 l2way = word & 0xf;
473 l2index = word >> 4 & 0x1ff;
474 l2tag = get_l2tag(bank, l2index, l2way);
475 if (panel > 3)
476 bit_5 = 1;
477
478 //cache_addr = bits 10:9, bits 5, way [2:0]
479 //To access the directory L2$ uses a 6 bits address decodes as:
480 //way[2] cpuid[2:0], way [1:0]
481 way_2 = addr >> 5 & 1;
482 caddr = way_2 << 2 | (addr & 0x3);
483 core = addr >> 2 & 0x7;
484 if ((core_present & 1 << core) == 0)
485 io_printf("L2I_DIR: ERROR: Core = %0d not present while entry present in l2i_dir. Bank = %0x, panel = %0x, dir_addr = %0x, l2tag = %x, l2_index = %x, l2way = %x, caddr = %x\n", core, bank, panel, addr, l2tag, l2index, l2way, caddr);
486
487 if (gchkr_debug)
488 io_printf("L2I_DIR: ENTRY: Bank = %0x, panel = %0x, core = %0x, dir_addr = %0x, l2tag = %x, l2_index = %x, l2way = %x, caddr = %x\n", bank, panel, core, addr, l2tag, l2index, l2way, caddr);
489
490 l1vars.ic[core][caddr].valid = 1;
491 l1vars.ic[core][caddr].l2_index = l2index;
492 l1vars.ic[core][caddr].l2_way = l2way;
493 l1vars.ic[core][caddr].l2_pa = l2tag;
494 } //if vld
495 } //for adr
496 if (gchkr_debug)
497 {
498 dump_l2icdir(bank, panel);
499 }
500}
501
502
503int get_l2dir_vld(int bank, int panel, int addr, int type)
504{
505 int gidx;
506 int sidx;
507 int vld = 0;
508 int avld;
509
510 gidx = addr / 32;
511 sidx = addr % 32;
512
513 if (gchkr_debug & (addr == 0)) //print it only for the first access to panel
514 {
515 if (type)
516 io_printf("\nL2D_DIR: Bank%0x:Panel%0x: addr = %0x, vld = %x:%x\n", bank, panel, addr, l2vars.l2_dvld[bank][panel][1].avalbits, l2vars.l2_dvld[bank][panel][0].avalbits);
517 else
518 io_printf("\nL2I_DIR: bank%0x:Panel%0x: addr = %0x, vld = %0x:%0x\n", bank, panel, addr, l2vars.l2_ivld[bank][panel][1].avalbits, l2vars.l2_ivld[bank][panel][0].avalbits);
519 }
520
521 if (type)
522 avld = l2vars.l2_dvld[bank][panel][gidx].avalbits;
523 else
524 avld = l2vars.l2_ivld[bank][panel][gidx].avalbits;
525
526 if (avld & (1 << sidx))
527 vld = 1;
528
529 //if (type) io_printf("L2D_DIR: <%0x:%0x:%0d> vld = %d\n", bank, panel, addr, vld);
530 //else io_printf("L2I_DIR: <%0x:%0x:%0d> vld = %d\n", bank, panel, addr, vld);
531
532 return vld;
533}
534
535int get_l2tag(int bank, int l2index, int l2way)
536{
537 char *lt_ptr;
538 char *rt_ptr;
539 int lt_word_increment;
540 int rt_word_increment;
541 char *aval_lt_ptr;
542 char *aval_rt_ptr;
543 int even = 0;
544 int lword = 0;
545 int rword = 0;
546 int ldata = 0;
547 int rdata = 0;
548 int group_num;
549 int tag = 0;
550
551 switch (l2way)
552 {
553 case 0:
554 case 4: lt_ptr = l2vars.l2t_lft[bank][0]; rt_ptr = l2vars.l2t_rgt[bank][0]; break;
555 case 1:
556 case 5: lt_ptr = l2vars.l2t_lft[bank][1]; rt_ptr = l2vars.l2t_rgt[bank][1]; break;
557 case 8:
558 case 12: lt_ptr = l2vars.l2t_lft[bank][2]; rt_ptr = l2vars.l2t_rgt[bank][2]; break;
559 case 9:
560 case 13: lt_ptr = l2vars.l2t_lft[bank][3]; rt_ptr = l2vars.l2t_rgt[bank][3]; break;
561 case 2:
562 case 6: lt_ptr = l2vars.l2t_lft[bank][4]; rt_ptr = l2vars.l2t_rgt[bank][4]; break;
563 case 3:
564 case 7: lt_ptr = l2vars.l2t_lft[bank][5]; rt_ptr = l2vars.l2t_rgt[bank][5]; break;
565 case 10:
566 case 14: lt_ptr = l2vars.l2t_lft[bank][6]; rt_ptr = l2vars.l2t_rgt[bank][6]; break;
567 case 11:
568 case 15: lt_ptr = l2vars.l2t_lft[bank][7]; rt_ptr = l2vars.l2t_rgt[bank][7]; break;
569 }
570
571 lt_word_increment = l2vars.l2t_lft_ngroups * 2;
572 aval_lt_ptr = lt_ptr + (l2index * lt_word_increment);
573
574 rt_word_increment = l2vars.l2t_rgt_ngroups * 2;
575 aval_rt_ptr = rt_ptr + (l2index * rt_word_increment);
576
577//even is the higher way
578
579 switch (l2way)
580 {
581 case 4:
582 case 5:
583 case 12:
584 case 13:
585 case 6:
586 case 7:
587 case 14:
588 case 15: even = 1;break;
589 default: even = 0; break;
590 }
591
592 for (group_num = l2vars.l2t_lft_ngroups - 1; group_num >= 0; group_num--)
593 {
594 lword <<= 8;
595 lword |= aval_lt_ptr[group_num] & 0xff;
596 }
597
598 for (group_num = l2vars.l2t_rgt_ngroups - 1; group_num >= 0; group_num--)
599 {
600 rword <<= 8;
601 rword |= aval_rt_ptr[group_num] & 0xff;
602 }
603
604 if (gchkr_debug) io_printf("L2TAG: <bank[%0x]:index[%0x]:way[%0d]> lword = %x, rword = %x\n", bank, l2index, l2way, lword, rword);
605
606 switch (even)
607 {
608 case 1: ldata = get_lword(lword >> 2); rdata = get_rword(rword); break;
609 case 0: ldata = get_lword(lword >> 1); rdata = get_rword(rword >> 1); break;
610 }
611
612 if (gchkr_debug) io_printf("L2TAG: <bank[%0x]:index[%0x]:way[%0d]> lword = %x, rword = %x, ldata=%x, rdata=%x\n", bank, l2index, l2way, lword, rword, ldata, rdata);
613
614//15 bits are received from left side and 13 bits from the right side.
615
616 tag = ldata << 7 | rdata >> 6;
617 return tag;
618}
619
620
621//Lft array is 31 bits. Rightmost bit is the redundancy bit which is removed.
622//So, this function is passed 30 bits, out of which we extract 15 bits.
623//left array is 30:0
624//29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 <= odd sequence
625//30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 <= even sequence
626
627
628//for this to work bit 0 shd have the lsb of data we want to extract
629
630int get_lword (int in_val)
631{
632 int new_val = 0;
633 int i;
634
635 //io_printf("get_lword: in_val = %x, new_val = %x\n", in_val, new_val);
636 for (i = 0; i < 15; i++)
637 {
638 new_val |= (in_val & 1) << i;
639 in_val >>= 2;
640 }
641 //io_printf("get_lword: in_val = %x, new_val = %x\n", in_val, new_val);
642 return new_val;
643}
644
645//for rt array, the redundancy bits are on left. No need to
646//remove them, just don't grab them. We still need to make sure
647//that bit in the lsb position is valid;
648
649//rt array is: 0:26
650//1 3 5 7 9 11 13 15 17 19 21 23 25 <= odd sequence
651//2 4 6 8 10 12 14 16 18 20 22 24 26 <= even sequence
652
653int get_rword (int in_val)
654{
655 int new_val = 0;
656 int i;
657
658 //io_printf("get_rword: in_val = %x, new_val = %x\n", in_val, new_val);
659 for (i = 0; i < 13; i++)
660 {
661 new_val |= (in_val & 1) << i;
662 in_val >>= 2;
663 }
664 //io_printf("get_rword: in_val = %x, new_val = %x\n", in_val, new_val);
665 return new_val;
666}
667
668int cmp_dcdir(int bank, int panel)
669{
670 int core;
671 int word_increment;
672 int group_num;
673 int bit_10_9 = 0;
674 int bit_5 = 0;
675 int bit_4 = 0;
676 int way;
677 int dtag_addr;
678 int caddr = 0;
679 int tag = 0;
680 int dc_way_vld, i;
681 char *aval_ptr;
682 struct cache dc_tmp[8];
683 int err = 0;
684 int err_cnt = 0;
685
686 for (i = 0; i < 8; i++)
687 {
688 dc_tmp[i].valid = 0;
689 dc_tmp[i].way = 0;
690 dc_tmp[i].l1_tag = 0;
691 dc_tmp[i].l1_index = 0;
692 }
693 for (core = 0; core < 8; core++)
694 {
695 if (core_present >> core & 1)
696 {
697 word_increment = l1vars.dtag_ngroups * 2;
698 switch (panel)
699 {
700 case 0: bit_10_9 = 0; bit_5 = 0; break;
701 case 1: bit_10_9 = 1; bit_5 = 0; break;
702 case 2: bit_10_9 = 2; bit_5 = 0; break;
703 case 3: bit_10_9 = 3; bit_5 = 0; break;
704 case 4: bit_10_9 = 0; bit_5 = 1; break;
705 case 5: bit_10_9 = 1; bit_5 = 1; break;
706 case 6: bit_10_9 = 2; bit_5 = 1; break;
707 case 7: bit_10_9 = 3; bit_5 = 1; break;
708 }
709 for (bit_4 = 0; bit_4 < 2; bit_4++)
710 {
711 dtag_addr = bit_10_9 << 5 | bank << 2 | bit_5 << 1 | bit_4;
712 dc_way_vld = get_dc_vld_data(core, dtag_addr);
713 //io_printf("DC%0d\tINDEX\t\tWAY\t\tTAG\t\t\t dc_way_vld = %0x\n", core, dc_way_vld);
714
715 for (way = 0; way < 4; way++)
716 {
717 aval_ptr = l1vars.dtag[core][way] + (word_increment * dtag_addr);
718 tag = 0;
719 for (group_num = l1vars.dtag_ngroups - 1; group_num >= 0; group_num--)
720 {
721 tag <<= 8;
722 tag |= aval_ptr[group_num] & 0xff;
723 }
724 //Only tag bits 29:0 are valid and bit 29 is parity bit.
725 //remove parity bit
726 tag = (tag << 3 ) >> 3;
727 //io_printf("L1D: index = %x, way%0d, tag = %x\n", dtag_addr, way, tag);
728
729 caddr = bit_4 << 2 | way;
730 if (dc_way_vld >> way & 1)
731 {
732 dc_tmp[caddr].valid = 1;
733 dc_tmp[caddr].way = way;
734 dc_tmp[caddr].l1_tag = tag;
735 dc_tmp[caddr].l1_index = dtag_addr;
736 }
737 }
738 } //bit 4
739 if (gchkr_debug) dump_dc(core, bank, panel, dc_tmp);
740
741 err = cmp_dc_core_data(core, bank, panel, dc_tmp);
742 if (err)
743 io_printf("ERROR: L2D_DIR: core<%0x>:bank<%0x>:panel<%0x>: %0d mismatches.\n", core, bank, panel, err);
744 err_cnt += err;
745 for (i = 0; i < 8; i++)
746 {
747 dc_tmp[i].valid = 0;
748 dc_tmp[i].way = 0;
749 dc_tmp[i].l1_tag = 0;
750 dc_tmp[i].l1_index = 0;
751 }
752 }
753 } // core
754 return err_cnt;
755}
756
757int cmp_dc_core_data(int core, int bank, int panel, struct cache dc[])
758{
759 long long l1pa, l1tmp_pa;
760 long long l2pa, l2tmp_pa;
761 int mismatch = 0;
762 int i;
763 int l2dir_index = 0;
764 int dtag_addr = 0;
765 int bit_5 = 0;
766 int bit_4 = 0;
767 int l2_ind_unhash = 0;
768
769 if (panel > 3) bit_5 = 1;
770 for (i = 0; i < 8; i++)
771 {
772 l2dir_index = (i >> 2 & 0x1) << 5 | core << 2 | (i & 0x3); //bit_4, core, way
773 dtag_addr = dc[i].l1_index;
774 l1tmp_pa = dc[i].l1_tag;
775 l2tmp_pa = l1vars.dc[core][i].l2_pa;
776 l1pa = l1tmp_pa << 11 | dtag_addr << 4;
777 bit_4 = i >> 2 & 1;
778
779 if (hash_on)
780 l2_ind_unhash = get_unhashed_index(l1vars.dc[core][i].l2_pa, l1vars.dc[core][i].l2_index);
781 else
782 l2_ind_unhash = l1vars.dc[core][i].l2_index;
783
784 l2pa = l2tmp_pa << 18 | l2_ind_unhash << 9 | bank << 6 | bit_5 << 5 | bit_4 << 4;
785
786 if (l1vars.dc[core][i].valid != dc[i].valid)
787 {
788 io_printf("\nERROR: L2D_DIR: core<%0x>:bank<%0x>:panel<%0x> Vld bit mismatch between L2$_ddir(vld=%0d) and L1_D$(vld=%0d).\n", core, bank, panel, l1vars.dc[core][i].valid, dc[i].valid);
789
790 io_printf("l2_dir_index<%0x>:l2_index<%0x>:l2_way<%0x>: L2_tag[39:18] = %0x, L2_tag[39:0] = %0llx\n", l2dir_index, l1vars.dc[core][i].l2_index, l1vars.dc[core][i].l2_way, l1vars.dc[core][i].l2_pa, l2pa);
791
792 io_printf("\nl1_D$_index<%0x>:l1_way<%0x>: L1_tag[39:11] = %0x, L1_tag[39:0] = %0llx\n", dtag_addr, dc[i].way, dc[i].l1_tag, l1pa);
793 mismatch = mismatch + 1;
794 }
795 else if (dc[i].valid)
796 {
797 if (l1pa != l2pa)
798 {
799 io_printf("\nERROR: L2D_DIR: core<%0x>:bank<%0x>:panel<%0x> PA mismatch between L2$_ddir(PA=%0llx) and L1_D$(PA=%0llx).\n", core, bank, panel, l2pa, l1pa);
800
801 io_printf("l2_dir_index<%0x>:l2_way<%0x>:l2_index<%0x>: L2_tag[39:18] = %0x, L2_tag[39:0] = %0llx\n", l2dir_index, l1vars.dc[core][i].l2_way, l1vars.dc[core][i].l2_index, l1vars.dc[core][i].l2_pa, l2pa);
802
803 io_printf("\nl1_D$_index<%0x>:l1_way<%0x>: L1_tag[39:11] = %0x, L1_tag[39:0] = %0llx\n", dtag_addr, dc[i].way, dc[i].l1_tag, l1pa);
804 mismatch = mismatch + 1;
805 }
806 }
807 }
808 return mismatch;
809}
810
811
812int get_dc_vld_data(int core, int addr)
813{
814 char *aval_ptr;
815 int group_num;
816 int vld = 0;
817 int vld1, vld2;
818
819 group_num = l1vars.dvld_ngroups;
820 aval_ptr = l1vars.dvld[core] + (l1vars.dvld_ngroups * 2) * (addr >> 2);
821
822 for (--group_num; group_num >= 0; group_num--)
823 {
824 vld <<= 8;
825 vld |= aval_ptr[group_num] & 0xff;
826 }
827 //io_printf("addr = %0x, vld = %0x\n", addr, vld);
828
829 switch(addr & 0x3)
830 {
831 case 0: vld1 = vld & 0xf; vld2 = vld >> 16 & 0xf; break;
832 case 1: vld1 = vld >> 4 & 0xf; vld2 = vld >> 20 & 0xf; break;
833 case 2: vld1 = vld >> 8 & 0xf; vld2 = vld >> 24 & 0xf; break;
834 case 3: vld1 = vld >> 12 & 0xf; vld2 = vld >> 28 & 0xf; break;
835 }
836 //if (gchkr_debug)
837 //io_printf("addr = %0x, vld = %0x, vld1 = %0x, vld2 = %0x\n", addr, vld, vld1, vld2);
838
839 if (vld1 != vld2)
840 io_printf("ERROR: DC%0d, vld1 (%x) != vld2 (%x) for index %x.\n", core, vld1, vld2, addr);
841
842 return vld1;
843}
844
845int cmp_icdir(int bank, int panel)
846{
847 int core;
848 int word_increment;
849 int group_num;
850 int bit_10_9 = 0;
851 int bit_5 = 0;
852 int way;
853 int itag_addr;
854 int caddr;
855 int tag = 0;
856 int ic_way_vld, i;
857 char *aval_ptr;
858 struct cache ic_tmp[8];
859 int err = 0;
860 int err_cnt = 0;
861
862 for (i = 0; i < 8; i++)
863 {
864 ic_tmp[i].valid = 0;
865 ic_tmp[i].way = 0;
866 ic_tmp[i].l1_tag = 0;
867 ic_tmp[i].l1_index = 0;
868 }
869 switch (panel)
870 {
871 case 0: bit_10_9 = 0; bit_5 = 0; break;
872 case 1: bit_10_9 = 1; bit_5 = 0; break;
873 case 2: bit_10_9 = 2; bit_5 = 0; break;
874 case 3: bit_10_9 = 3; bit_5 = 0; break;
875 case 4: bit_10_9 = 0; bit_5 = 1; break;
876 case 5: bit_10_9 = 1; bit_5 = 1; break;
877 case 6: bit_10_9 = 2; bit_5 = 1; break;
878 case 7: bit_10_9 = 3; bit_5 = 1; break;
879 }
880 for (core = 0; core < 8; core++)
881 {
882 if (core_present >> core & 1)
883 {
884 word_increment = l1vars.itag_ngroups * 2;
885 itag_addr = bit_10_9 << 4 | bank << 1 | bit_5;
886 ic_way_vld = get_ic_vld_data(core, itag_addr);
887 //io_printf("DC%0d\tINDEX\t\tWAY\t\tTAG\t\t\t ic_way_vld = %0x\n", core, ic_way_vld);
888
889 for (way = 0; way < 8; way++)
890 {
891 aval_ptr = l1vars.itag[core][way] + (word_increment * itag_addr);
892 tag = 0;
893 for (group_num = l1vars.itag_ngroups - 1; group_num >= 0; group_num--)
894 {
895 tag <<= 8;
896 tag |= aval_ptr[group_num] & 0xff;
897 }
898 //Only tag bits 29:0 are valid and bit 29 is parity bit.
899 //remove parity bit
900 //if (ic_way_vld >> way & 1)
901 //io_printf("L1I: index = %x, way%0d, tag = %x\n", itag_addr, way, tag);
902 tag = (tag << 3 ) >> 3;
903
904 caddr = way;
905 if (ic_way_vld >> way & 1)
906 {
907 ic_tmp[caddr].valid = 1;
908 ic_tmp[caddr].way = way;
909 ic_tmp[caddr].l1_tag = tag;
910 ic_tmp[caddr].l1_index = itag_addr;
911 }
912 }
913 if (gchkr_debug) dump_ic(core, bank, panel, ic_tmp);
914
915 err = cmp_ic_core_data(core, bank, panel, ic_tmp);
916 if (err)
917 io_printf("ERROR: L2I_DIR: core<%0x>:bank<%0x>:panel<%0d>: %0d mismatches.\n", core, bank, panel, err);
918 err_cnt += err;
919 for (i = 0; i < 8; i++)
920 {
921 ic_tmp[i].valid = 0;
922 ic_tmp[i].way = 0;
923 ic_tmp[i].l1_tag = 0;
924 ic_tmp[i].l1_index = 0;
925 }
926 }
927 } // core
928 return err_cnt;
929}
930
931int cmp_ic_core_data(int core, int bank, int panel, struct cache ic[])
932{
933 long long l1pa, l1tmp_pa;
934 long long l2pa, l2tmp_pa;
935 int mismatch = 0;
936 int i;
937 int bit_5 = 0;
938 int l2dir_index, itag_addr;
939 int l2_ind_unhash = 0;
940
941 if (panel > 3) bit_5 = 1;
942 for (i = 0; i < 8; i++)
943 {
944 l2dir_index = (i >> 2 & 0x1) << 5 | core << 2 | (i & 0x3); //way[2], core, way
945 itag_addr = ic[i].l1_index;
946 l1tmp_pa = ic[i].l1_tag;
947 l2tmp_pa = l1vars.ic[core][i].l2_pa;
948 l1pa = l1tmp_pa << 11 | itag_addr << 5;
949 if (hash_on)
950 l2_ind_unhash = get_unhashed_index(l1vars.ic[core][i].l2_pa, l1vars.ic[core][i].l2_index);
951 else
952 l2_ind_unhash = l1vars.ic[core][i].l2_index;
953
954 l2pa = l2tmp_pa << 18 | l2_ind_unhash << 9 | bank << 6 | bit_5 << 5;
955
956 if (l1vars.ic[core][i].valid != ic[i].valid)
957 {
958 if (l1vars.ic[core][i].valid & is_reset_addr(l2pa))
959 {
960 io_printf("\nL2I_DIR: core<%0x>:bank<%0x>:panel<%0x> Vld bit mismatch between L2$_idir(vld=%0d) and L1_I$(vld=%0d). Ignoring the mismatch as L2$ addr is good trap addr.\n", core, bank, panel, l1vars.ic[core][i].valid, ic[i].valid);
961 }
962 else
963 {
964 io_printf("\nERROR: L2I_DIR: core<%0x>:bank<%0x>:panel<%0x> Vld bit mismatch between L2$_idir(vld=%0d) and L1_I$(vld=%0d).\n", core, bank, panel, l1vars.ic[core][i].valid, ic[i].valid);
965
966 io_printf("l2_dir_index<%0x>:l2_index<%0x>:l2_way<%0x>: L2_tag[39:18] = %0x, L2_tag[39:0] = %0llx\n", l2dir_index, l1vars.ic[core][i].l2_index, l1vars.ic[core][i].l2_way, l1vars.ic[core][i].l2_pa, l2pa);
967
968 io_printf("\nl1_I$_index<%0x>:l1_way<%0x>: L1_tag[39:11] = %0x, L1_tag[39:0] = %0llx\n", itag_addr, ic[i].way, ic[i].l1_tag, l1pa);
969 mismatch = mismatch + 1;
970 }
971 }
972 else if (ic[i].valid) //if valid then only chkr for pa match
973 {
974 if (l1pa != l2pa)
975 {
976 if (is_reset_addr(l2pa))
977 {
978 io_printf("\nL2I_DIR: core<%0x>:bank<%0x>:panel<%0x> PA mismatch between L2$_idir(PA=%0llx) and L1_I$(PA=%0llx).Ignoring the mismatch as L2$ addr is good trap addr.\n", core, bank, panel, l2pa, l1pa);
979 }
980 else
981 {
982 io_printf("\nERROR: L2I_DIR: core<%0x>:bank<%0x>:panel<%0x> PA mismatch between L2$_idir(PA=%0llx) and L1_I$(PA=%0llx).\n", core, bank, panel, l2pa, l1pa);
983
984 io_printf("l2_dir_index<%0x>:l2_way<%0x>:l2_index<%0x>: L2_tag[39:18] = %0x, L2_tag[39:0] = %0llx\n", l2dir_index, l1vars.ic[core][i].l2_way, l1vars.ic[core][i].l2_index, l1vars.ic[core][i].l2_pa, l2pa);
985
986 io_printf("\nl1_I$_index<%0x>:l1_way<%0x>: L1_tag[39:11] = %0x, L1_tag[39:0] = %0llx\n", itag_addr, ic[i].way, ic[i].l1_tag, l1pa);
987 mismatch = mismatch + 1;
988 }
989 }
990 }
991 }
992 return mismatch;
993}
994
995
996int get_ic_vld_data(int core, int addr)
997{
998 char *aval_ptr;
999 int group_num;
1000 int vld = 0;
1001 int vld1 = 0;
1002 int vld2 = 0;
1003
1004 group_num = l1vars.ivld_ngroups;
1005 aval_ptr = l1vars.ivld[core] + (l1vars.ivld_ngroups * 2) * (addr >> 1);
1006
1007 for (--group_num; group_num >= 0; group_num--)
1008 {
1009 vld <<= 8;
1010 vld |= aval_ptr[group_num] & 0xff;
1011 }
1012
1013 switch(addr & 0x1)
1014 {
1015 case 0: vld1 = vld & 0xff; vld2 = vld >> 16 & 0xff; break;
1016 case 1: vld1 = vld >> 8 & 0xff; vld2 = vld >> 24 & 0xff; break;
1017 }
1018
1019 //if (gchkr_debug)
1020 //io_printf("addr = %0x, vld = %0x, vld1 = %0x, vld2 = %0x\n", addr, vld, vld1, vld2);
1021
1022 if (vld1 != vld2)
1023 io_printf("ERROR: IC%0d, vld1 (%x) != vld2 (%x) for index %x.\n", core, vld1, vld2, addr);
1024
1025 return vld1;
1026}
1027
1028int chk_ic_dc_exclusion(int bank, int panel)
1029{
1030 int i, j;
1031 int err = 0;
1032 int core = 0;
1033
1034 for (core= 0; core< 8; core++)
1035 {
1036 for (i= 0; i< 8; i++)
1037 {
1038 if (l1vars.ic[core][i].valid)
1039 {
1040 for (j = 0; j < 8; j++)
1041 {
1042 if (l1vars.dc[core][j].valid & (l1vars.ic[core][i].l2_index == l1vars.dc[core][j].l2_index) & (l1vars.ic[core][i].l2_way == l1vars.dc[core][j].l2_way))
1043 {
1044 err = err + 1;
1045 io_printf("ERROR: D$-I$ mutual exclusion violation. L2bank = %0d, Panel = %0d, core=%0d, I$_entry=%0d, D$_entry=%0d\n", bank, panel, core, i, j);
1046 }
1047 }
1048 }
1049 }
1050 }
1051
1052 return err;
1053}
1054
1055void display_cache_entry(int core, int entry, int type)
1056{
1057 long long full_pa;
1058 if (type)
1059 {
1060 full_pa = l1vars.dc[core][entry].l2_pa;
1061 full_pa = l1vars.dc[core][entry].l2_pa << 11 | l1vars.dc[core][entry].l2_index << 4;
1062 io_printf("DC%0d, entry = %x, way = %x, index = %x, pa = %llx\n", core, entry, l1vars.dc[core][entry].l2_way, l1vars.dc[core][entry].l2_index, full_pa);
1063 }
1064 else
1065 {
1066 full_pa = l1vars.ic[core][entry].l2_pa;
1067 full_pa = l1vars.ic[core][entry].l2_pa << 11 | l1vars.ic[core][entry].l2_index << 4;
1068 io_printf("ic%0d, entry = %x, way = %x, index = %x, pa = %llx\n", core, entry, l1vars.ic[core][entry].l2_way, l1vars.ic[core][entry].l2_index, full_pa);
1069 }
1070}
1071
1072void dump_l2dcdir(int bank, int panel)
1073{
1074 int bit_5 = 0;
1075 int core = 0;
1076 int i;
1077 long long l2pa, l2tmp_pa;
1078 int bit_4 = 0;
1079 int caddr = 0;
1080 int l1_index = 0;
1081 int l1_way = 0;
1082 int l2_ind_unhash = 0;
1083
1084 io_printf("L2D_dir Bank%0d, Panel%0d valid Data.\n", bank, panel);
1085 if (hash_on)
1086 io_printf("INDEX\tCORE\tL1_INDEX\tL1_WAY\tL2_INDEX\tL2_INDEX_UNHASH\tL2_WAY\tL2_Tag[39:18]\t\tL2_PA[39:0]\n");
1087 else
1088 io_printf("INDEX\tCORE\tL1_INDEX\tL1_WAY\tL2_INDEX\tL2_WAY\tL2_Tag[39:18]\t\tL2_PA[39:0]\n");
1089
1090 for (i = 0; i < 64; i++)
1091 {
1092 core = i >> 2 & 0x7;
1093 if (panel > 3) bit_5 = 1;
1094 bit_4 = i >> 5 & 1;
1095 l1_index = (panel & 0x3) << 5 | bank << 2 | bit_5 << 1 | bit_4;
1096 l1_way = i & 0x3;
1097 caddr = bit_4 << 2 | (i & 0x3);
1098
1099 if (l1vars.dc[core][caddr].valid)
1100 {
1101 l2tmp_pa = l1vars.dc[core][caddr].l2_pa;
1102 if (hash_on)
1103 l2_ind_unhash = get_unhashed_index(l1vars.dc[core][caddr].l2_pa, l1vars.dc[core][caddr].l2_index);
1104 else
1105 l2_ind_unhash = l1vars.dc[core][caddr].l2_index;
1106
1107 l2pa = l2tmp_pa << 18 | l2_ind_unhash << 9 | bank << 6 | bit_5 << 5 | ((i >> 1) & 0x10);
1108 if (hash_on)
1109 io_printf("%0x\t%0x\t%0x\t\t%0x\t%0x\t\t%0x\t\t%0x\t%0x\t\t%0llx\n", i, core, l1_index, l1_way, l1vars.dc[core][caddr].l2_index, l2_ind_unhash, l1vars.dc[core][caddr].l2_way, l1vars.dc[core][caddr].l2_pa, l2pa);
1110 else
1111 io_printf("%0x\t%0x\t%0x\t\t%0x\t%0x\t\t%0x\t%0x\t\t%0llx\n", i, core, l1_index, l1_way, l1vars.dc[core][caddr].l2_index, l1vars.dc[core][caddr].l2_way, l1vars.dc[core][caddr].l2_pa, l2pa);
1112 }
1113 }
1114}
1115
1116void dump_l2icdir(int bank, int panel)
1117{
1118 int bit_5 = 0;
1119 int core = 0;
1120 int i;
1121 long long l2pa, l2tmp_pa;
1122 int caddr = 0;
1123 int way_2 = 0;
1124 int l1_index = 0;
1125 int l1_way = 0;
1126 int l2_ind_unhash = 0;
1127
1128 io_printf("L2I_dir Bank%0d, Panel%0d valid Data.\n", bank, panel);
1129 if (hash_on)
1130 io_printf("INDEX\tCORE\tL1_INDEX\tL1_WAY\tL2_INDEX\tL2_INDEX_UNHASH\tL2_WAY\tL2_Tag[39:18]\t\tL2_PA[39:0]\n");
1131 else
1132 io_printf("INDEX\tCORE\tL1_INDEX\tL1_WAY\tL2_INDEX\tL2_WAY\tL2_Tag[39:18]\t\tL2_PA[39:0]\n");
1133
1134 for (i = 0; i < 64; i++)
1135 {
1136 core = i >> 2 & 0x7;
1137 if (panel > 3) bit_5 = 1;
1138 way_2 = i >> 5 & 1;
1139 l1_index = (panel & 0x3) << 4 | bank << 1 | bit_5;
1140 l1_way = way_2 << 2 | (i & 0x3);
1141 caddr = l1_way;
1142 if (l1vars.ic[core][caddr].valid)
1143 {
1144 l2tmp_pa = l1vars.ic[core][caddr].l2_pa;
1145 if (hash_on)
1146 l2_ind_unhash = get_unhashed_index(l1vars.ic[core][caddr].l2_pa, l1vars.ic[core][caddr].l2_index);
1147 else
1148 l2_ind_unhash = l1vars.ic[core][caddr].l2_index;
1149
1150 l2pa = l2tmp_pa << 18 | l2_ind_unhash << 9 | bank << 6 | bit_5 << 5;
1151 if (hash_on)
1152 io_printf("%0x\t%0x\t%0x\t\t%0x\t%0x\t\t%0x\t\t%0x\t%0x\t\t%0llx\n", i, core, l1_index, l1_way, l1vars.ic[core][caddr].l2_index, l2_ind_unhash, l1vars.ic[core][caddr].l2_way, l1vars.ic[core][caddr].l2_pa, l2pa);
1153 else
1154 io_printf("%0x\t%0x\t%0x\t\t%0x\t%0x\t\t%0x\t%0x\t\t%0llx\n", i, core, l1_index, l1_way, l1vars.ic[core][caddr].l2_index, l1vars.ic[core][caddr].l2_way, l1vars.ic[core][caddr].l2_pa, l2pa);
1155 }
1156 }
1157}
1158
1159void dump_dc(int core, int bank, int panel, struct cache dc[])
1160{
1161 int i;
1162 long long l1pa, l1tmp_pa;
1163 int index;
1164
1165 io_printf("\nL1D Core%0d, Bank%0d Panel %0d valid Data.\n", core, bank, panel);
1166 io_printf("INDEX\tWAY\tL1_Tag[39:11]\t\tL1_PA[39:0]\n");
1167
1168 for (i = 0; i < 8; i++)
1169 {
1170 if (dc[i].valid)
1171 {
1172 index = dc[i].l1_index;
1173 l1tmp_pa = dc[i].l1_tag;
1174 l1pa = l1tmp_pa << 11 | index << 4;
1175 io_printf("%0x\t%0x\t%0x\t\t%0llx\n", index, (i & 0x3), dc[i].l1_tag, l1pa);
1176 }
1177 }
1178}
1179
1180void dump_ic(int core, int bank, int panel, struct cache ic[])
1181{
1182
1183 int i;
1184 long long l1pa, l1tmp_pa;
1185 int index;
1186
1187 io_printf("\nL1I Core%0d, Bank%0d Panel%0d valid Data.\n", core, bank, panel);
1188 io_printf("INDEX\tWAY\tL1_Tag[39:11]\t\tL1_PA[39:0]\n");
1189
1190 for (i = 0; i < 8; i++)
1191 {
1192 if (ic[i].valid)
1193 {
1194 index = ic[i].l1_index;
1195 l1tmp_pa = ic[i].l1_tag;
1196 l1pa = l1tmp_pa << 11 | index << 5;
1197 io_printf("%0x\t%0x\t%0x\t\t%0llx\n", index, (i & 0x7), ic[i].l1_tag, l1pa);
1198 }
1199 }
1200}
1201
1202int get_unhashed_index(int l2_pa, int l2_ind)
1203{
1204 int unhashed_index = 0;
1205 unhashed_index = ((((l2_pa >> 10 & 0x1f) ^ (l2_ind >> 4 & 0x1f)) << 4) | (((l2_pa & 0x3) ^ (l2_ind >> 2 & 0x3)) << 2) | (l2_ind & 0x3));
1206 return unhashed_index;
1207}
1208
1209void sample_plusargs(void)
1210{
1211 int i = 0;
1212 char *gtrap;
1213 char *tok;
1214
1215 for (i = 0; i < 8; i++) good_trap_addr[i] = 0;
1216
1217
1218 if (mc_scan_plusargs("gchkr_debug"))
1219 gchkr_debug = 1;
1220 else
1221 gchkr_debug = 0;
1222
1223 if (mc_scan_plusargs("hash_on"))
1224 hash_on = 1;
1225 else
1226 hash_on = 0;
1227 i = 0;
1228
1229 if ((gtrap = mc_scan_plusargs("good_trap=")) != NULL)
1230 {
1231 //io_printf("good_trap = %s\n", gtrap);
1232 if (strchr(gtrap, ':') == NULL)
1233 {
1234 good_trap_addr[i] = strtoll(gtrap,NULL,16);
1235 //io_printf("gtrap = %s, addr=%0llx\n", gtrap, good_trap_addr[i]);
1236 }
1237 else
1238 {
1239 tok = strtok(gtrap, ":");
1240 good_trap_addr[i] = strtoll(tok,NULL,16);
1241 //io_printf("tok = %s, addr=%0llx\n", tok, good_trap_addr[i]);
1242 while ((tok = strtok(NULL, ":")) != NULL)
1243 {
1244 i++;
1245 good_trap_addr[i] = strtoll(tok,NULL,16);
1246 //io_printf("tok = %s, addr=%0llx\n", tok, good_trap_addr[i]);
1247 }
1248 }
1249 }
1250 if (gchkr_debug)
1251 {
1252 io_printf("gchkr_debug = %0d, hash_on = %0d\n", gchkr_debug, hash_on);
1253 for (i = 0; i < 8; i++)
1254 io_printf("good_trap_addr[%0d] = %0llx\n", i, good_trap_addr[i]);
1255 }
1256}
1257
1258int is_reset_addr(long long l2pa)
1259{
1260
1261 int match = 0;
1262 int i = 0;
1263
1264 for (i = 0; i < 8; i++)
1265 {
1266 //io_printf("good_trap_addr[%0d] = %0llx, l2pa = %0llx\n", i, good_trap_addr[i], l2pa);
1267 if (good_trap_addr[i] == l2pa)
1268 match = 1;
1269 //io_printf("good_trap_addr[%0d] = %0llx, l2pa = %0llx, match = %0x\n", i, good_trap_addr[i], l2pa, match);
1270 }
1271 return match;
1272}
1273
1274
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