Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / ccxDevices / basePktClass.vr
CommitLineData
86530b38
AT
1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: basePktClass.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36
37
38// Generic CCX Packet. Yes, there is no code in here.
39
40virtual class BasePkt {
41
42 protected string name = "Name Me";
43
44 public reg [16:0] sendPorts=0; // pkt will be sent from this/these ports (start at)
45 public reg [16:0] targetPorts=0; // pkt is going to these ports (end at)
46 public integer arrivalPort=99; // this packet arrived at this port
47 public integer arrivalTime=0;
48 public reg pktArrived=0; // set by BFM when the anticipated pkt arrives.
49 public integer senderPort; // initiating port for this arriving pkt
50 public reg ccxSourced = 0; // req pkt came in from CCX, not backdoor initiated
51 public reg ccxSourced2 = 0; // cas/swap req pkt came in from CCX, not backdoor initiated
52 public integer decGntTarget; // serviceSends task uses this for multicast gnt tracking
53 public reg [2:0] tid = 0;
54 public reg [3:0] rtntyp = 4'b1111;
55 public reg [4:0] rqtyp = 5'b11111;
56 public integer rtntypU = 0; // identifies specific packet type using defines
57 public integer rqtypU = 0; // identifies specific packet type using defines
58 public reg [39:0] addr = 0;
59 public reg CASstore = 0; // holds true when a CAS request stores to L2. (for ld st sync)
60 public reg [2:0] atomic = 0; // 1 for CAS1, 2 for CAS2 or ifill response 1=1,2=2
61 public reg [8:0] atm_wire = 0;
62 public reg [8:0] req_wire = 9'bxxxxxxxxx;
63 public integer reqTime;
64 public integer reqId;
65 public reg [3:0] lineWay = 4'hf;
66 public reg [28:0] tag = ~0;
67 public reg [127:0] signature;
68
69 virtual task print(integer atPort);
70 virtual task loadPkt(reg [145:0] dataIn, integer atPort);
71 virtual task send(integer fastResp=0);
72 virtual task recv();
73// virtual task cancelRecv();
74 virtual function reg [145:0] makeSignature();
75 virtual function reg [145:0] getVector();
76
77
78
79 // how many bits set?
80 protected function integer manyHot(reg [63:0] vec) {
81 manyHot = 0;
82 while (vec) {
83 manyHot += vec[0];
84 vec >>= 1;
85 }
86 }
87
88 // which bit set? if return is 99, there was 0 or > 1 hot.
89 // returns the lowest bit number set.
90 protected function integer whichHot(reg [63:0] vec, reg check=1) {
91 whichHot = 0;
92
93 while(vec[whichHot] !== 1) whichHot++;
94
95 // none hot
96 if (check && vec == 0) whichHot=99;
97 // >1 hot
98 if (check && manyHot(vec) > 1) whichHot=99;
99
100 }
101
102}