projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ccxDevicesDefines.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef INC__TMP_CCXDEVICEDEFINES_VRI | |
| 36 | #define INC__TMP_CCXDEVICEDEFINES_VRI | |
| 37 | ||
| 38 | ||
| 39 | #define STD_DISP gDbg | |
| 40 | ||
| 41 | //---------------------------------------------------------- | |
| 42 | // PCX Packet rqtyp Defines, actual - request | |
| 43 | #define PCX_LD 5'b00000 | |
| 44 | #define PCX_PREF 5'b00000 | |
| 45 | #define PCX_PREF_ICE 5'b00000 | |
| 46 | #define PCX_DIAG_LD 5'b00000 | |
| 47 | #define PCX_D_INVAL 5'b00000 | |
| 48 | #define PCX_IFILL 5'b10000 | |
| 49 | #define PCX_I_INVAL 5'b10000 | |
| 50 | #define PCX_ST 5'b00001 | |
| 51 | #define PCX_BLK_ST 5'b00001 | |
| 52 | #define PCX_BLK_INIT_ST 5'b00001 | |
| 53 | #define PCX_DIAG_ST 5'b00001 | |
| 54 | #define PCX_CAS1 5'b00010 | |
| 55 | #define PCX_CAS2 5'b00011 | |
| 56 | #define PCX_SWAP 5'b00111 | |
| 57 | #define PCX_STR_LD 5'b00100 | |
| 58 | #define PCX_STR_ST 5'b00101 | |
| 59 | #define PCX_MMU_LD 5'b01000 | |
| 60 | ||
| 61 | #define PCX_FLUSH 5'b01001 | |
| 62 | ||
| 63 | ||
| 64 | // PCX Packet rqtyp Defines, unique | |
| 65 | #define U_PCX_LD 1 | |
| 66 | #define U_PCX_PREF 2 | |
| 67 | #define U_PCX_DIAG_LD 3 | |
| 68 | #define U_PCX_D_INVAL 4 | |
| 69 | #define U_PCX_IFILL 5 | |
| 70 | #define U_PCX_I_INVAL 6 | |
| 71 | #define U_PCX_ST 7 | |
| 72 | #define U_PCX_BLK_ST 8 | |
| 73 | #define U_PCX_DIAG_ST 9 | |
| 74 | #define U_PCX_CAS1 10 | |
| 75 | #define U_PCX_CAS2 11 | |
| 76 | #define U_PCX_SWAP 12 | |
| 77 | #define U_PCX_STR_LD 13 | |
| 78 | #define U_PCX_STR_ST 14 | |
| 79 | #define U_PCX_MMU_LD 15 | |
| 80 | #define U_PCX_PREF_ICE 16 | |
| 81 | #define U_PCX_BLK_INIT_ST 17 | |
| 82 | ||
| 83 | // CPX Packet rtntyp Defines, actual - return | |
| 84 | #define CPX_LD 4'b0000 | |
| 85 | #define CPX_PREF 4'b0000 | |
| 86 | #define CPX_PREF_ICE 4'b0000 | |
| 87 | #define CPX_DIAG_LD 4'b0000 | |
| 88 | #define CPX_NCU_LD 4'b1000 | |
| 89 | #define CPX_D_INVAL 4'b0100 | |
| 90 | #define CPX_IFILL 4'b0001 | |
| 91 | #define CPX_NCU_IFILL 4'b1001 | |
| 92 | #define CPX_I_INVAL 4'b0100 | |
| 93 | #define CPX_ST 4'b0100 | |
| 94 | #define CPX_DIAG_ST 4'b0100 | |
| 95 | #define CPX_CAS_RTN 4'b0000 | |
| 96 | #define CPX_CAS_ACK 4'b0100 | |
| 97 | #define CPX_SWAP_RTN 4'b0000 | |
| 98 | #define CPX_SWAP_ACK 4'b0100 | |
| 99 | #define CPX_STR_LD 4'b0010 | |
| 100 | #define CPX_STR_ST 4'b0110 | |
| 101 | #define CPX_MMU_RTN 4'b0101 | |
| 102 | #define CPX_INTR 4'b0111 | |
| 103 | #define CPX_EVICT 4'b0011 | |
| 104 | #define CPX_ERROR_L2 4'b1100 | |
| 105 | #define CPX_ERROR_SOC 4'b1101 | |
| 106 | ||
| 107 | #define CPX_BLK_ST 4'b0100 | |
| 108 | #define CPX_FLUSH 4'b0111 | |
| 109 | ||
| 110 | // CPX Packet rtntyp Defines, unique | |
| 111 | #define U_CPX_LD 1 | |
| 112 | #define U_CPX_PREF 2 | |
| 113 | #define U_CPX_DIAG_LD 3 | |
| 114 | #define U_CPX_D_INVAL 4 | |
| 115 | #define U_CPX_IFILL 5 | |
| 116 | #define U_CPX_I_INVAL 6 | |
| 117 | #define U_CPX_ST 7 | |
| 118 | #define U_CPX_DIAG_ST 8 | |
| 119 | #define U_CPX_CAS_RTN 9 | |
| 120 | #define U_CPX_CAS_ACK 10 | |
| 121 | #define U_CPX_SWAP_RTN 11 | |
| 122 | #define U_CPX_SWAP_ACK 12 | |
| 123 | #define U_CPX_STR_LD 13 | |
| 124 | #define U_CPX_STR_ST 14 | |
| 125 | #define U_CPX_MMU_RTN 15 | |
| 126 | #define U_CPX_INTR 16 | |
| 127 | #define U_CPX_EVICT 17 | |
| 128 | #define U_CPX_ERROR_L2 18 | |
| 129 | #define U_CPX_BIS 19 | |
| 130 | #define U_CPX_NCU_LD 20 | |
| 131 | #define U_CPX_ERROR_SOC 21 | |
| 132 | #define U_CPX_NCU_IFILL 22 | |
| 133 | #define U_CPX_PREF_ICE 23 | |
| 134 | #define U_CPX_BLK_ST 24 | |
| 135 | ||
| 136 | // Interrupt types | |
| 137 | #define INTR_HW 2'b00 | |
| 138 | #define INTR_RESET 2'b01 | |
| 139 | #define INTR_IDLE 2'b10 | |
| 140 | #define INTR_RESUME 2'b11 | |
| 141 | ||
| 142 | // Interrupt vectors | |
| 143 | #define INTR_POR 6'b000001 | |
| 144 | #define INTR_XIR 6'b000011 | |
| 145 | ||
| 146 | ||
| 147 | // I/O Addresses | |
| 148 | // CMP ASI Registers | |
| 149 | ||
| 150 | // #define IO_ASI_ADDR 8'h90 | |
| 151 | // #define ASI_CMP_CORE 8'h41 | |
| 152 | // #define ASI_CMP_CORE_AVAIL 18'h000 | |
| 153 | // #define ASI_CMP_CORE_ENABLED 18'h010 | |
| 154 | // #define ASI_CMP_CORE_ENABLE 18'h020 | |
| 155 | // #define ASI_CMP_XIR_STEERING 18'h030 | |
| 156 | // #define ASI_CMP_ERROR_STEERING 18'h040 | |
| 157 | // #define ASI_CMP_CORE_RUNNING_RW 18'h050 | |
| 158 | // #define ASI_CMP_CORE_RUNNING_STATUS 18'h058 | |
| 159 | // #define ASI_CMP_CORE_RUNNING_W1S 18'h060 | |
| 160 | // #define ASI_CMP_CORE_RUNNING_W1C 18'h068 | |
| 161 | ||
| 162 | ||
| 163 | // Tag Table defines | |
| 164 | #define DATA_TAG 1 | |
| 165 | #define INSTR_TAG 0 | |
| 166 | #define TAG_VAL 1'b1 | |
| 167 | #define TAG_INVAL 1'b0 | |
| 168 | #define EVICT_D 2'b00 | |
| 169 | #define EVICT_I 2'b01 | |
| 170 | #define EVICT_DI 2'b10 | |
| 171 | #define EVICT_ID 2'b11 | |
| 172 | #define D_INVAL 2'b01 | |
| 173 | #define I_INVAL 2'b10 | |
| 174 | ||
| 175 | ||
| 176 | #define PP_CPX 0 | |
| 177 | #define PP_PCX 1 | |
| 178 | #define PP_MEM 2 | |
| 179 | #define PP_SPC 3 | |
| 180 | #define PP_TRG 4 | |
| 181 | ||
| 182 | #define READ 0 | |
| 183 | #define WRITE 1 | |
| 184 | ||
| 185 | #define PASSIVE 1 | |
| 186 | #define ACTIVE 0 | |
| 187 | ||
| 188 | // ccx devices | |
| 189 | #define DEV_SPC0 0 | |
| 190 | #define DEV_SPC1 1 | |
| 191 | #define DEV_SPC2 2 | |
| 192 | #define DEV_SPC3 3 | |
| 193 | #define DEV_SPC4 4 | |
| 194 | #define DEV_SPC5 5 | |
| 195 | #define DEV_SPC6 6 | |
| 196 | #define DEV_SPC7 7 | |
| 197 | #define DEV_MEM0 8 | |
| 198 | #define DEV_MEM1 9 | |
| 199 | #define DEV_MEM2 10 | |
| 200 | #define DEV_MEM3 11 | |
| 201 | #define DEV_MEM4 12 | |
| 202 | #define DEV_MEM5 13 | |
| 203 | #define DEV_MEM6 14 | |
| 204 | #define DEV_MEM7 15 | |
| 205 | ||
| 206 | #define DEV_MEM8 16 | |
| 207 | #define DEV_NCU 16 | |
| 208 | ||
| 209 | ||
| 210 | // "same cache line address". | |
| 211 | #define CACHE_LINE_MASK 64'h0000007fffffffc0 | |
| 212 | ||
| 213 | ||
| 214 | //#define IDLE_DATA {urandom(),urandom(),urandom(),urandom()} | |
| 215 | #define IDLE_DATA 128'hDEAD_BEEF_DEAD_BEEF_DEAD_BEEF_DEAD_BEEF | |
| 216 | ||
| 217 | ||
| 218 | #endif | |
| 219 | ||
| 220 | //---------------------------------------------------------- | |
| 221 | // END OF FILE | |
| 222 | //---------------------------------------------------------- |