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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / classes / FcMcuMon.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: FcMcuMon.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include <ListMacros.vrh>
37#include "FcMcuMonPort.if.vrh"
38#define STD_DISP gDbg
39#include <std_display_defines.vri>
40#include <std_display_class.vrh>
41
42extern bit [63:0] FCMemoryAddress_A[4];
43extern bit [63:0] FCMemoryAddress_B[4];
44extern bit [63:0] FCMemoryAddress_C[4];
45extern event FCMemorySync_A[4];
46extern event FCMemorySync_B[4];
47extern event FCMemorySync_C[4];
48extern StandardDisplay gDbg;
49
50
51class FcMcuMon {
52
53dram_write_MCU write_mcu;
54//local StandardDisplay dbg;
55bit [1:0] mcu_port_no;
56
57 task new(dram_write_MCU write_mcu, bit [1:0] mcu_port_no);
58 task DramWrite (dram_write_MCU write_mcu, bit [1:0] mcu_port_no);
59
60}
61
62
63task FcMcuMon:: new (dram_write_MCU write_mcu, bit [1:0] mcu_port_no) {
64
65 fork
66 {
67 DramWrite (write_mcu, mcu_port_no);
68 }
69 join none
70
71}
72
73
74task FcMcuMon:: DramWrite (dram_write_MCU write_mcu, bit [1:0] mcu_port_no) {
75
76
77bit CLK;
78bit [2:0] CMD_A, CMD_B, CMD_C;
79bit [15:0] ADDR_A, ADDR_B, ADDR_C;
80bit [2:0] BANK_A, BANK_B, BANK_C;
81bit RANK_A, RANK_B, RANK_C;
82bit [2:0] DIMM_A, DIMM_B, DIMM_C;
83
84bit [2:0] State_A, State_B, State_C;
85bit [2:0] Idle_State_A, Idle_State_B, Idle_State_C;
86bit [2:0] Active_State_A, Active_State_B, Active_State_C;
87bit [2:0] Write_State_A, Write_State_B, Write_State_C;
88bit Idle_A, Idle_B, Idle_C;
89bit Active_A, Active_B, Active_C;
90bit Write_A, Write_B, Write_C;
91bit [15:0] RAS_A, RAS_B, RAS_C;
92bit [15:0] CAS_A, CAS_B, CAS_C;
93
94bit [39:0] physical_addr_A, physical_addr_B, physical_addr_C;
95
96bit BA01, BA23, BA45, BA67;
97
98integer i;
99
100State_A = 3'b001;
101Idle_State_A = 3'b001;
102Active_State_A = 3'b010;
103Write_State_A = 3'b100;
104
105State_B = 3'b001;
106Idle_State_B = 3'b001;
107Active_State_B = 3'b010;
108Write_State_B = 3'b100;
109
110State_C = 3'b001;
111Idle_State_C = 3'b001;
112Active_State_C = 3'b010;
113Write_State_C = 3'b100;
114
115CLK = write_mcu.$drl2clk;
116
117
118 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf("MCU[%0d] Inside DramWrite Task\n", mcu_port_no));
119 while(1) {
120 @(posedge write_mcu.$drl2clk);
121
122 CMD_A = write_mcu.$drif_dram_cmd_a;
123 ADDR_A = write_mcu.$drif_dram_addr_a;
124 BANK_A = write_mcu.$drif_dram_bank_a;
125 RANK_A = write_mcu.$drif_dram_rank_a;
126 DIMM_A = write_mcu.$drif_dram_dimm_a;
127
128 CMD_B = write_mcu.$drif_dram_cmd_b;
129 ADDR_B = write_mcu.$drif_dram_addr_b;
130 BANK_B = write_mcu.$drif_dram_bank_b;
131 RANK_B = write_mcu.$drif_dram_rank_b;
132 DIMM_B = write_mcu.$drif_dram_dimm_b;
133
134 CMD_C = write_mcu.$drif_dram_cmd_c;
135 ADDR_C = write_mcu.$drif_dram_addr_c;
136 BANK_C = write_mcu.$drif_dram_bank_c;
137 RANK_C = write_mcu.$drif_dram_rank_c;
138 DIMM_C = write_mcu.$drif_dram_dimm_c;
139
140 BA01 = write_mcu.$ncu_mcu_ba01;
141 BA23 = write_mcu.$ncu_mcu_ba23;
142 BA45 = write_mcu.$ncu_mcu_ba45;
143 BA67 = write_mcu.$ncu_mcu_ba67;
144
145
146 Idle_A = State_A[0];
147 Active_A = State_A[1];
148 Write_A = State_A[2];
149
150 Idle_B = State_B[0];
151 Active_B = State_B[1];
152 Write_B = State_B[2];
153
154 Idle_C = State_C[0];
155 Active_C = State_C[1];
156 Write_C = State_C[2];
157
158 case(1'b1)
159 {
160 Idle_A : {
161 if (CMD_A == 3'b100)
162 {
163// printf ("%0d : MAQ-Debug[%0d] : Active_A RAS = %h \n",{get_time(HI), get_time(LO)}, mcu_port_no, ADDR_A);
164 State_A = Active_State_A;
165 RAS_A = ADDR_A;
166 }
167 }
168 Active_A : {
169 if (CMD_A == 3'b011)
170 {
171 State_A = Write_State_A;
172 CAS_A = ADDR_A;
173 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf("%0d MCU[%0d] Write_A DIMM = %h, RANK = %h, BANK = %h, RAS = %h, CAS = %h\n",
174 {get_time(HI), get_time(LO)}, mcu_port_no, DIMM_A, RANK_A, BANK_A, RAS_A, CAS_A));
175 physical_addr_A = {2'b00, DIMM_A, CAS_A[2], RAS_A[14:0], CAS_A[11], CAS_A[9:3], BANK_A[2:1], mcu_port_no, BANK_A[0], CAS_A[1], 5'b00000};
176// printf("JAMES1 addr = %h ba01=%0d ba23=%0d, ba45=%0d, ba67=%0d\n", physical_addr_A, BA01, BA23, BA45, BA67);
177 physical_addr_A = saddr(physical_addr_A, BA01, BA23, BA45, BA67);
178 if (write_mcu.$index_hashing)
179 physical_addr_A = { physical_addr_A[39:18], physical_addr_A[32:28] ^ physical_addr_A[17:13], physical_addr_A[19:18] ^ physical_addr_A[12:11], physical_addr_A[10:0] };
180// printf("JAMES2 addr = %h ba01=%0d ba23=%0d, ba45=%0d, ba67=%0d\n", physical_addr_A, BA01, BA23, BA45, BA67);
181 for(i=0;i<8; i++)
182 {
183 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf (" %0d MCU[%0d] : physical :Addr = %h \n", {get_time(HI), get_time(LO)}, mcu_port_no, (physical_addr_A + 8*i)));
184 FCMemoryAddress_A[mcu_port_no] = (physical_addr_A + 8*i);
185 trigger(FCMemorySync_A[mcu_port_no]);
186 sync(ALL,FCMemorySync_A[mcu_port_no]);
187 }
188
189 }
190 else
191 {
192// printf ("%0d : MAQ-Debug[%0d] : Active CMD was not for Write \n", {get_time(HI), get_time(LO)}, mcu_port_no);
193 if (CMD_A == 3'b100)
194 State_A = Active_State_A; //Idle_State_A;
195 else
196 State_A = Idle_State_A;
197 }
198 }
199 Write_A : {
200// printf ("%0d : MAQ-Debug[%0d] : Idle_A \n",{get_time(HI), get_time(LO)}, mcu_port_no);
201 State_A = Idle_State_A;
202 }
203 default : State_A = Idle_State_A;
204 } // case
205// ****************************************************************************************************************************
206 case(1'b1)
207 {
208 Idle_B : {
209 if (CMD_B == 3'b100)
210 {
211// printf ("%0d : MAQ-Debug[%0d] : Active_B RAS = %h \n",{get_time(HI), get_time(LO)}, mcu_port_no, ADDR_B);
212 State_B = Active_State_B;
213 RAS_B = ADDR_B;
214 }
215 }
216 Active_B : {
217 if (CMD_B == 3'b011)
218 {
219 State_B = Write_State_B;
220 CAS_B = ADDR_B;
221 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf ("%0d : MAQ-Debug[%0d] : Write_B DIMM = %h, RANK = %h, BANK = %h, RAS = %h, CAS = %h \n",
222 {get_time(HI), get_time(LO)}, mcu_port_no, DIMM_B, RANK_B, BANK_B, RAS_B, CAS_B));
223 physical_addr_B = {2'b00, DIMM_B, CAS_B[2], RAS_B[14:0], CAS_B[11], CAS_B[9:3], BANK_B[2:1], mcu_port_no, BANK_B[0], CAS_B[1], 5'b00000};
224 //printf("JAMES3 addr = %h ba01=%0d ba23=%0d, ba45=%0d, ba67=%0d\n", physical_addr_B, BA01, BA23, BA45, BA67);
225 physical_addr_B = saddr(physical_addr_B, BA01, BA23, BA45, BA67);
226 if (write_mcu.$index_hashing)
227 physical_addr_B = { physical_addr_B[39:18], physical_addr_B[32:28] ^ physical_addr_B[17:13], physical_addr_B[19:18] ^ physical_addr_B[12:11], physical_addr_B[10:0] };
228// printf("JAMES4 addr = %h ba01=%0d ba23=%0d, ba45=%0d, ba67=%0d\n", physical_addr_B, BA01, BA23, BA45, BA67);
229 for(i=0;i<8; i++)
230 {
231 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf ("%0d : MAQ-Debug[%0d] : physical :Addr = %h \n",{get_time(HI), get_time(LO)}, mcu_port_no, (physical_addr_B + 8*i)));
232 FCMemoryAddress_B[mcu_port_no] = (physical_addr_B + 8*i);
233 trigger(FCMemorySync_B[mcu_port_no]);
234 sync(ALL,FCMemorySync_B[mcu_port_no]);
235 }
236 }
237 else
238 {
239// printf (" %0d : MAQ-Debug[%0d] : Active CMD was not for Write \n", {get_time(HI), get_time(LO)}, mcu_port_no);
240 if (CMD_B == 3'b100)
241 State_B = Active_State_B;
242 else
243 State_B = Idle_State_B;
244 }
245 }
246 Write_B : {
247// printf ("%0d : MAQ-Debug[%0d] : Idle_B \n",{get_time(HI), get_time(LO)}, mcu_port_no);
248 State_B = Idle_State_B;
249 }
250 default : State_B = Idle_State_B;
251 } // case
252
253// ****************************************************************************************************************************
254 case(1'b1)
255 {
256 Idle_C : {
257 if (CMD_C == 3'b100)
258 {
259// printf ("%0d : MAQ-Debug[%0d] : Active_C RAS = %h \n",{get_time(HI), get_time(LO)}, mcu_port_no, ADDR_C);
260 State_C = Active_State_C;
261 RAS_C = ADDR_C;
262 }
263 }
264 Active_C : {
265 if (CMD_C == 3'b011)
266 {
267 State_C = Write_State_C;
268 CAS_C = ADDR_C;
269 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf ("%0d : MAQ-Debug[%0d] : Write_C DIMM = %h, RANK = %h, BANK = %h, RAS = %h, CAS = %h \n",
270 {get_time(HI), get_time(LO)}, mcu_port_no, DIMM_C, RANK_C, BANK_C, RAS_C, CAS_C));
271 physical_addr_C = {2'b00, DIMM_C, CAS_C[2], RAS_C[14:0], CAS_C[11], CAS_C[9:3], BANK_C[2:1], mcu_port_no, BANK_C[0], CAS_C[1], 5'b00000};
272 //printf("JAMES5 addr = %h ba01=%0d ba23=%0d, ba45=%0d, ba67=%0d\n", physical_addr_A, BA01, BA23, BA45, BA67);
273 physical_addr_C = saddr(physical_addr_C, BA01, BA23, BA45, BA67);
274 if (write_mcu.$index_hashing)
275 physical_addr_C = { physical_addr_C[39:18], physical_addr_C[32:28] ^ physical_addr_C[17:13], physical_addr_C[19:18] ^ physical_addr_C[12:11], physical_addr_C[10:0] };
276// printf("JAMES6 addr = %h ba01=%0d ba23=%0d, ba45=%0d, ba67=%0d\n", physical_addr_C, BA01, BA23, BA45, BA67);
277 for(i=0;i<8; i++)
278 {
279 PR_DEBUG("FcMcuMon", MON_DEBUG, psprintf ("%0d : MAQ-Debug[%0d] : physical :Addr = %h \n",{get_time(HI), get_time(LO)}, mcu_port_no, (physical_addr_C + 8*i)));
280 FCMemoryAddress_C[mcu_port_no] = (physical_addr_C + 8*i);
281 trigger(FCMemorySync_C[mcu_port_no]);
282 sync(ALL,FCMemorySync_C[mcu_port_no]);
283 }
284
285 }
286 else
287 {
288// printf (" %0d : MAQ-Debug[%0d] : Active CMD was not for Write \n", {get_time(HI), get_time(LO)}, mcu_port_no);
289 if (CMD_C == 3'b100)
290 State_C = Active_State_C;
291 else
292 State_C = Idle_State_C;
293 }
294 }
295 Write_C : {
296// printf ("%0d : MAQ-Debug[%0d] : Idle_C \n",{get_time(HI), get_time(LO)}, mcu_port_no);
297 State_C = Idle_State_C;
298 }
299 default : State_C = Idle_State_C;
300 } // case
301
302// ****************************************************************************************************************************
303 } // while
304}
305
306
307// PM Shifting function
308function bit [39:0] saddr (bit[39:0] addr, bit ba01, bit ba23, bit ba45, bit ba67)
309{
310 integer shift;
311 integer pa6, pa7, pa8;
312
313 case({ba67, ba45, ba23, ba01}) {
314 4'b0000: shift = 0;
315 4'b0001: shift = 2;
316 4'b0010: shift = 2;
317 4'b0011: shift = 1;
318 4'b0100: shift = 2;
319 4'b0101: shift = 1;
320 4'b0110: shift = 1;
321 4'b1000: shift = 2;
322 4'b1001: shift = 1;
323 4'b1010: shift = 1;
324 4'b1100: shift = 1;
325 4'b1111: shift = 0;
326 }
327
328 if(shift > 0){
329 saddr = addr >> 9;
330 if(shift == 1){
331 saddr = saddr << 8;
332 saddr = saddr | (addr & 8'b11111111);
333 }
334 if(shift == 2){
335 saddr = saddr << 7;
336 saddr = saddr | (addr & 7'b1111111);
337 }
338 }
339 else
340 saddr = addr;
341}
Full OpenSPARC design & verification tarball including full HDL.