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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: systemTap.if.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_SYSTEMTAP_IF_VRI | |
36 | #define INC_SYSTEMTAP_IF_VRI | |
37 | ||
38 | #include <vera_defines.vrh> | |
39 | ||
40 | // #define OUTPUT_EDGE_N NHOLD | |
41 | // #define INPUT_EDGE PSAMPLE | |
42 | // #define INPUT_SKEW #-3 | |
43 | ||
44 | interface tb_top_tck { // to support on-demand TCK | |
45 | input TCK CLOCK verilog_node "tb_top.tck"; | |
46 | inout TCK2DUT PSAMPLE NHOLD verilog_node "tb_top.tck2dut"; | |
47 | output TRST_L NHOLD verilog_node "`CPU.TRST_L"; | |
48 | } | |
49 | ||
50 | interface jtag { | |
51 | input TCK CLOCK verilog_node "`CPU.TCK"; | |
52 | input TDO PSAMPLE #-3 verilog_node "`CPU.TDO"; | |
53 | output TEST_MODE NHOLD verilog_node "`CPU.TESTMODE"; | |
54 | output TDI NHOLD verilog_node "`CPU.TDI"; | |
55 | output TMS NHOLD verilog_node "`CPU.TMS"; | |
56 | output SSI_MISO NHOLD verilog_node "`CPU.SSI_MISO"; | |
57 | } | |
58 | ||
59 | interface l2clk_if { | |
60 | #ifdef TCU_GATE | |
61 | input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp__cclk"; | |
62 | #else | |
63 | input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp.l2clk"; | |
64 | #endif | |
65 | } | |
66 | ||
67 | port tap__port { | |
68 | tck; | |
69 | tck2dut; | |
70 | trst_n; | |
71 | test_mode; | |
72 | tms; | |
73 | tdi; | |
74 | tdo; | |
75 | ssi_miso; | |
76 | l2clk; | |
77 | } | |
78 | ||
79 | bind tap__port tap_bind { | |
80 | tck tb_top_tck.TCK; | |
81 | tck2dut tb_top_tck.TCK2DUT; | |
82 | trst_n tb_top_tck.TRST_L; | |
83 | test_mode jtag.TEST_MODE; | |
84 | tms jtag.TMS; | |
85 | tdi jtag.TDI; | |
86 | tdo jtag.TDO; | |
87 | ssi_miso jtag.SSI_MISO; | |
88 | l2clk l2clk_if.l2clk; | |
89 | } | |
90 | ||
91 | ||
92 | #endif | |
93 | ||
94 |