projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: cmp.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `ifdef INC__TMP_CMP_VRI | |
| 36 | ||
| 37 | `else | |
| 38 | `define INC__TMP_CMP_VRI | |
| 39 | ||
| 40 | //---------------------------------------------------------- | |
| 41 | // I/O Addresses | |
| 42 | // addr[39:0] = {8'h90, cpuid[2:0], tid[2:0], 8'h45, va[17:0]}; | |
| 43 | // addr[39:32] = 8'h90 | |
| 44 | // addr[31:26] = {cpuid[2:0], tid[2:0]} | |
| 45 | // addr[25:18] = ASI_SWVR_UDB_INTR_W | |
| 46 | // addr[17:0] = VA | |
| 47 | ||
| 48 | `define IO_ASI_ADDR 8'h90 | |
| 49 | `define IO_ASI_CPU 8'h90 | |
| 50 | `define IO_ASI_NCU 8'h80 | |
| 51 | ||
| 52 | `define IO_ASI_ADDR_NCU 39:32 | |
| 53 | `define IO_ASI_ADDR_CT 31:26 | |
| 54 | `define IO_ASI_ADDR_REG 25:18 | |
| 55 | `define IO_ASI_ADDR_VA 17:0 | |
| 56 | `define IO_ASI_ADDR_ADR 25:0 | |
| 57 | ||
| 58 | ||
| 59 | // CMP ASI Registers | |
| 60 | // addr[39:0] = | |
| 61 | // {IO_ASI_CPU[39:32],IO_ASI_ADDR_CT[31:26],IO_ASI_ADDR_REG[25:18],IO_ASI_ADDR_VA[17:0]}; | |
| 62 | // {90, | |
| 63 | `define ASI_CMP_CORE 8'h41 | |
| 64 | `define ASI_CMP_CORE_AVAIL 18'h000 | |
| 65 | `define ASI_CMP_CORE_ENABLED 18'h010 | |
| 66 | `define ASI_CMP_CORE_ENABLE 18'h020 | |
| 67 | `define ASI_CMP_XIR_STEERING 18'h030 | |
| 68 | `define ASI_CMP_TICK_ENABLE 18'h038 | |
| 69 | `define ASI_CMP_ERROR_STEERING 18'h040 | |
| 70 | `define ASI_CMP_CORE_RUNNING_RW 18'h050 | |
| 71 | `define ASI_CMP_CORE_RUNNING_STATUS 18'h058 | |
| 72 | `define ASI_CMP_CORE_RUNNING_W1S 18'h060 | |
| 73 | `define ASI_CMP_CORE_RUNNING_W1C 18'h068 | |
| 74 | ||
| 75 | `define ASI_CMP_CORE_AVAIL_ADR {8'h41,18'h000} | |
| 76 | `define ASI_CMP_CORE_ENABLED_ADR {8'h41,18'h010} | |
| 77 | `define ASI_CMP_CORE_ENABLE_ADR {8'h41,18'h020} | |
| 78 | `define ASI_CMP_XIR_STEERING_ADR {8'h41,18'h030} | |
| 79 | `define ASI_CMP_TICK_ENABLE_ADR {8'h41,18'h038} | |
| 80 | `define ASI_CMP_ERROR_STEERING_ADR {8'h41,18'h040} | |
| 81 | `define ASI_CMP_CORE_RUNNING_RW_ADR {8'h41,18'h050} | |
| 82 | `define ASI_CMP_CORE_RUNNING_STATUS_ADR {8'h41,18'h058} | |
| 83 | `define ASI_CMP_CORE_RUNNING_W1S_ADR {8'h41,18'h060} | |
| 84 | `define ASI_CMP_CORE_RUNNING_W1C_ADR {8'h41,18'h068} | |
| 85 | ||
| 86 | `define ASI_SWVR_UDB_INTR_W 8'h73 | |
| 87 | ||
| 88 | // power throttle, [2:0] is encoded number of stalls in 8 cycle window | |
| 89 | // 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls | |
| 90 | // this is a reserved address! | |
| 91 | // Chip CPU Throttle Control CPU_THROTTLE_CTL (0x98-0000-0828) | |
| 92 | `define ASI_POWER_THROTTLE_ADR {8'h00,18'h828} | |
| 93 | ||
| 94 | `define ASI_LSU_MISC 8'h45 | |
| 95 | `define ASI_WMR_VEC_MASK_ADR {8'h45,18'h18} | |
| 96 | `define ASI_OVERLAP_MODE_ADR {8'h45,18'h10} | |
| 97 | `define ASI_L2_IDX_HASH_EN_ADR {8'h45,18'h1030} | |
| 98 | `define ASI_RESET_STAT 64'h8900000810 | |
| 99 | `define TID_ADDR 40'h9a00000000 | |
| 100 | `define INT_VEC_DIS_ADDR 40'h9001cc0000 | |
| 101 | ||
| 102 | ||
| 103 | ||
| 104 | `endif | |
| 105 | ||
| 106 | //---------------------------------------------------------- | |
| 107 | // END OF FILE | |
| 108 | //---------------------------------------------------------- |