Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / vera / mac_monitor / include / mac_mon_if.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mac_mon_if.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
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// ========== Copyright Header End ============================================
#ifndef _MAC_INTERFFACE_
#define _MAC_INTERFFACE_

#include "neptune_defines.vri"

#define MAC_CK_IN_TIMING PSAMPLE #-1
#define MAC_CK_OUT_TIMING PHOLD #0
#define MAC_CK_CLK_TIMING  CLOCK



//*******************************************************************************
//************ INTERFACE ********************************************************
//*******************************************************************************

interface mac_m0_rx_mon_if {
input 		clk 		MAC_CK_CLK_TIMING verilog_node TOP.m0_rx_clk"; // "
//input [7:0]	data 		MAC_CK_IN_TIMING  verilog_node TOP.m0_rx_data"; // "
input 		dv 		MAC_CK_IN_TIMING  verilog_node TOP.m0_rx_dv"; // "
}

interface mac_m1_rx_mon_if {
input 		clk 		MAC_CK_CLK_TIMING verilog_node TOP.m1_rx_clk"; // "
//input [7:0]	data 		MAC_CK_IN_TIMING  verilog_node TOP.m1_rx_data"; // "
input 		dv 		MAC_CK_IN_TIMING  verilog_node TOP.m1_rx_dv"; // "
}

interface mac_m0_tx_mon_if {
input 		clk 		MAC_CK_CLK_TIMING verilog_node TOP.m0_tx_clk"; // "
//input [7:0]	data 		MAC_CK_IN_TIMING  verilog_node TOP.m0_tx_data"; // "
input 		dv 		MAC_CK_IN_TIMING  verilog_node TOP.m0_tx_en"; // "
}

interface mac_m1_tx_mon_if {
input 		clk 		MAC_CK_CLK_TIMING verilog_node TOP.m1_tx_clk"; // "
//input [7:0]	data 		MAC_CK_IN_TIMING  verilog_node TOP.m1_tx_data"; // "
input 		dv 		MAC_CK_IN_TIMING  verilog_node TOP.m1_tx_en"; // "
}


//**************************************************************************************************
//******** PORTS*************************************************************************************
//**************************************************************************************************

port mac_mon_port {
 clk;
 //data;
 dv;
}

//**************************************************************************************************
//******** BIND*************************************************************************************
//**************************************************************************************************

bind mac_mon_port mac_mon_m0_rx_bind {
 clk		mac_m0_rx_mon_if.clk;
// data		mac_m0_rx_mon_if.data;
 dv		mac_m0_rx_mon_if.dv;
}

bind mac_mon_port mac_mon_m1_rx_bind {
 clk		mac_m1_rx_mon_if.clk;
// data		mac_m1_rx_mon_if.data;
 dv		mac_m1_rx_mon_if.dv;
}

bind mac_mon_port mac_mon_m0_tx_bind {
 clk		mac_m0_tx_mon_if.clk;
// data		mac_m0_tx_mon_if.data;
 dv		mac_m0_tx_mon_if.dv;
}

bind mac_mon_port mac_mon_m1_tx_bind {
 clk		mac_m1_tx_mon_if.clk;
// data		mac_m1_tx_mon_if.data;
 dv		mac_m1_tx_mon_if.dv;
}


//****************************************************************************
//****************************************************************************
//****************************************************************************

#endif