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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_rx_cov_if.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #include <vera_defines.vrh> | |
36 | ||
37 | #include "neptune_defines.vri" | |
38 | ||
39 | #define CF_CK_IN_TIMING PSAMPLE #-1 | |
40 | #define CF_CK_OUT_TIMING PHOLD #0 | |
41 | #define CF_CK_CLK_TIMING CLOCK | |
42 | ||
43 | /*******************************************************************************************/ | |
44 | /* */ | |
45 | /* Coverage Object Interface for Control FIFO */ | |
46 | /* */ | |
47 | /*******************************************************************************************/ | |
48 | ||
49 | interface control_fifo_port0_cov_if { | |
50 | input [129:0] control_fifo_data CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat0"; | |
51 | input control_fifo_ful_pkt CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt0"; | |
52 | input control_fifo_err CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err0"; | |
53 | input control_fifo_ack CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack0"; | |
54 | output control_fifo_req CF_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req0"; | |
55 | input clk CF_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; | |
56 | } | |
57 | ||
58 | interface control_fifo_port1_cov_if { | |
59 | input [129:0] control_fifo_data CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat1"; | |
60 | input control_fifo_ful_pkt CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt1"; | |
61 | input control_fifo_err CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err1"; | |
62 | input control_fifo_ack CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack1"; | |
63 | output control_fifo_req CF_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req1"; | |
64 | input clk CF_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; | |
65 | } | |
66 | ||
67 | port control_fifo_cov_port{ | |
68 | control_fifo_data; | |
69 | control_fifo_ful_pkt; | |
70 | control_fifo_err; | |
71 | control_fifo_ack; | |
72 | control_fifo_req; | |
73 | clk; | |
74 | } | |
75 | ||
76 | bind control_fifo_cov_port control_fifo_p0{ | |
77 | control_fifo_data control_fifo_port0_cov_if.control_fifo_data; | |
78 | control_fifo_ful_pkt control_fifo_port0_cov_if.control_fifo_ful_pkt; | |
79 | control_fifo_err control_fifo_port0_cov_if.control_fifo_err; | |
80 | control_fifo_ack control_fifo_port0_cov_if.control_fifo_ack; | |
81 | control_fifo_req control_fifo_port0_cov_if.control_fifo_req; | |
82 | clk control_fifo_port0_cov_if.clk; | |
83 | } | |
84 | ||
85 | bind control_fifo_cov_port control_fifo_p1{ | |
86 | control_fifo_data control_fifo_port1_cov_if.control_fifo_data; | |
87 | control_fifo_ful_pkt control_fifo_port1_cov_if.control_fifo_ful_pkt; | |
88 | control_fifo_err control_fifo_port1_cov_if.control_fifo_err; | |
89 | control_fifo_ack control_fifo_port1_cov_if.control_fifo_ack; | |
90 | control_fifo_req control_fifo_port1_cov_if.control_fifo_req; | |
91 | clk control_fifo_port1_cov_if.clk; | |
92 | } | |
93 | ||
94 | ||
95 | /*******************************************************************************************/ | |
96 | /* */ | |
97 | /* Coverage Object Interface for Tx FIFO */ | |
98 | /* */ | |
99 | /*******************************************************************************************/ | |
100 | ||
101 | interface niu_coverage_txc_1024_port0_RO_RAM | |
102 | { | |
103 | input clk CLOCK verilog_node TXC_DUV_PATH_P0_RO_RAM.clk"; | |
104 | input cmp_diag_done PSAMPLE; | |
105 | ||
106 | input read_sig CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.cs_rd"; | |
107 | input [9:0] read_ptr CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.addr_rd"; | |
108 | input write_sig CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.wt_enable"; | |
109 | input [9:0] write_ptr CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_RO_RAM.addr_wt"; | |
110 | } | |
111 | ||
112 | interface niu_coverage_txc_1024_port0_SF_RAM | |
113 | { | |
114 | input clk CLOCK verilog_node TXC_DUV_PATH_P0_SF_RAM.clk"; | |
115 | input cmp_diag_done PSAMPLE; | |
116 | ||
117 | input read_sig CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.cs_rd"; | |
118 | input [9:0] read_ptr CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.addr_rd"; | |
119 | input write_sig CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.wt_enable"; | |
120 | input [9:0] write_ptr CF_CK_IN_TIMING verilog_node TXC_DUV_PATH_P0_SF_RAM.addr_wt"; | |
121 | } | |
122 | ||
123 | interface niu_coverage_mac_xpcs_state_machine | |
124 | { | |
125 | input clk CLOCK verilog_node MAC_DUV_PATH.mac_core.mac_2ports.xmac_2pcs_core_port0.xpcs.xpcs_rxio.rx_clk"; | |
126 | input [7:0] cs_state CF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_core.mac_2ports.xmac_2pcs_core_port0.xpcs.xpcs_pio.csr_ebuffer_state"; | |
127 | } | |
128 | ||
129 | /*******************************************************************************************/ | |
130 | /* */ | |
131 | /* Coverage Object Interface for Errors */ | |
132 | /* */ | |
133 | /*******************************************************************************************/ | |
134 | ||
135 | interface niu_coverage_err_det | |
136 | { | |
137 | input clk CF_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; | |
138 | input cmp_diag_done PSAMPLE; | |
139 | input control_fifo_err0 CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err0"; | |
140 | input control_fifo_err1 CF_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err1"; | |
141 | } |