projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / niu_coverage / niu_rx_coverage.vr
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_rx_coverage.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "niu_rx_cov_if.vri"
37
38enum PortNum {Port0, Port1, Port2, Port3};
39
40class niu_intf_coverage
41{
42 integer txc_p0_ro_ram_size = 0;
43 integer txc_p0_ro_ram_rd_b2b = 0;
44 integer txc_p0_ro_ram_wr_b2b = 0;
45 bit [4:0] txc_p0_ro_ram_rd_addr = 0;
46 bit [4:0] txc_p0_ro_ram_wr_addr = 0;
47 bit txc_p0_ro_ram_trig = 0;
48 reg [129:0] control_fifo_data;
49 bit control_fifo_data_port0_1st_cycle_cov = 0;
50 bit control_fifo_data_port0_2nd_cycle_cov = 0;
51 bit control_fifo_data_port1_1st_cycle_cov = 0;
52 bit control_fifo_data_port1_2nd_cycle_cov = 0;
53 bit control_fifo_data_port2_1st_cycle_cov = 0;
54 bit control_fifo_data_port2_2nd_cycle_cov = 0;
55 bit control_fifo_data_port3_1st_cycle_cov = 0;
56 bit control_fifo_data_port3_2nd_cycle_cov = 0;
57 event niu_coverage_err_trig;
58 event niu_rx_control_fifo_trig;
59
60 // 1st cycle:
61 reg se_bit;
62 reg drop_pkt;
63 reg fflp_hw_err;
64 reg mac_promiscuous;
65 reg tt_err;
66 reg tt_succeed;
67 reg [2:0] hash_sub_index;
68 reg hzfvld;
69 reg exact;
70 reg hash_hit;
71 reg [4:0] table_rdc;
72 reg [7:0] tcam_m_index;
73 reg [4:0] default_rdc;
74 reg tzfvld;
75 reg [1:0] tres;
76 reg tcam_hit;
77 reg bad_ip;
78 reg no_port;
79 reg llc_snap;
80 reg vlan;
81 reg [4:0] classs;
82 reg mac_check;
83 reg sop;
84 reg [1:0] mac_port;
85 reg eop;
86 // 2nd cycle:
87 reg [31:0] tcp_seq;
88 reg [3:0] tcp_hdr_len;
89 reg [3:0] ipv4_hdr_len;
90 reg [15:0] l3_pkt_len;
91 reg [4:0] zc_rdc;
92 reg [1:0] dmaw_type;
93 reg [1:0] ulp_type;
94 reg [3:0] pkt_id;
95 reg ip_ver;
96 reg [5:0] usr_data;
97 reg sop_2;
98 reg eop_2;
99
100 coverage_group niu_rx_control_fifo_group_1st_cycle_port0
101 {
102 //sample_event = wait_var(control_fifo_data_port0_1st_cycle_cov);
103 sample_event = wait_var(control_fifo_data_port0_2nd_cycle_cov); // use 2nd cycle for now to get eop
104 // and not add a new coverage group
105
106 sample drop_pkt { state fifo_data_drop_pkt(0:1)
107 if (drop_pkt == 1); }
108 sample fflp_hw_err { state fifo_data_fflp_hw_err(0:1)
109 if (fflp_hw_err == 1); }
110 sample mac_promiscuous { state fifo_data_mac_promiscuous(0:1)
111 if (mac_promiscuous == 1); }
112 sample tcam_hit { state fifo_data_tcam_hit(0:1)
113 if (tcam_hit == 1); }
114 //No test yet for bad_ip so comment out to confirm remaining coverage to 100%
115 //sample bad_ip { state fifo_data_bad_ip(0:1)
116 // if (bad_ip == 1); }
117 sample no_port { state fifo_data_no_port(0:1)
118 if (no_port == 1); }
119 sample llc_snap { state fifo_data_llc_snap(0:1)
120 if (llc_snap == 1); }
121 sample vlan { state fifo_data_vlan(0:1)
122 if (vlan == 1); }
123 sample mac_check { state fifo_data_mac_check(0:1)
124 if (mac_check == 1); }
125 sample sop { state fifo_data_sop(0:1)
126 if (sop == 1); }
127 sample eop { state fifo_data_eop(0:1) // eop is asserted only
128 if (eop == 1); } // in the second cycle
129 }
130
131#ifdef DISABLE_FOR_NOW
132 coverage_group niu_rx_control_fifo_group_2nd_cycle_port0
133 {
134 sample_event = wait_var(control_fifo_data_port0_2nd_cycle_cov);
135
136 }
137#endif
138
139#ifdef DISABLE_FOR_NOW
140 coverage_group niu_rx_control_fifo_group_1st_cycle_port1
141 {
142 sample_event = wait_var(control_fifo_data_port1_1st_cycle_cov);
143
144 sample drop_pkt { state fifo_data_drop_pkt(0:1)
145 if (drop_pkt == 1); }
146 sample fflp_hw_err { state fifo_data_fflp_hw_err(0:1)
147 if (fflp_hw_err == 1); }
148 sample mac_promiscuous { state fifo_data_mac_promiscuous(0:1)
149 if (mac_promiscuous == 1); }
150 sample tcam_hit { state fifo_data_tcam_hit(0:1)
151 if (tcam_hit == 1); }
152 sample bad_ip { state fifo_data_bad_ip(0:1)
153 if (bad_ip == 1); }
154 sample no_port { state fifo_data_no_port(0:1)
155 if (no_port == 1); }
156 sample llc_snap { state fifo_data_llc_snap(0:1)
157 if (llc_snap == 1); }
158 sample vlan { state fifo_data_vlan(0:1)
159 if (vlan == 1); }
160 sample mac_check { state fifo_data_mac_check(0:1)
161 if (mac_check == 1); }
162 sample sop { state fifo_data_sop(0:1)
163 if (sop == 1); }
164 sample eop { state fifo_data_eop(0:1)
165 if (eop == 1); }
166 }
167
168 coverage_group niu_rx_control_fifo_group_2nd_cycle_port1
169 {
170 sample_event = wait_var(control_fifo_data_port1_2nd_cycle_cov);
171
172 }
173#endif
174
175 coverage_group niu_coverage_mac_xpcs_state_group
176 {
177 const_sample_reference = 1;
178 sample_event = @(posedge niu_coverage_mac_xpcs_state_machine.clk);
179 #include "niu_mac_xpcs_sm.vri"
180 }
181
182 coverage_group niu_coverage_err_group
183 {
184 const_sample_reference = 1;
185 cross_auto_bin_max = 0;
186
187 sample_event = sync (ANY, niu_coverage_err_trig);
188
189 sample niu_coverage_err_det.control_fifo_err0;
190 sample niu_coverage_err_det.control_fifo_err1;
191
192 cross niu_coverage_err_cross_cov(niu_coverage_err_det.control_fifo_err1,
193 niu_coverage_err_det.control_fifo_err0)
194 {
195 state err_0_1(niu_coverage_err_det.control_fifo_err1==0 &&
196 niu_coverage_err_det.control_fifo_err0==1);
197 state err_1_0(niu_coverage_err_det.control_fifo_err1==1 &&
198 niu_coverage_err_det.control_fifo_err0==0);
199 // Currently not checking for both errors happening simultaneously.
200 }
201 }
202
203 coverage_group niu_tx_coverage_txc_fifo_rd_group
204 {
205 //sample_event = wait_var(txc_p0_ro_ram_rd_addr);
206 //sample_event = @(posedge niu_coverage_txc_1024_port0_RO_RAM.clk);
207 sample_event = wait_var(txc_p0_ro_ram_trig);
208
209 sample niu_coverage_txc_1024_port0_RO_RAM.read_ptr
210 {
211 state s_TXC_P0_RO_RAM_EMPTY(0:63)
212 if (txc_p0_ro_ram_size == 0);
213
214 state s_TXC_P0_RO_RAM_RD(0:63)
215 if (niu_coverage_txc_1024_port0_RO_RAM.read_sig === 1'b1);
216
217 state s_TXC_P0_RO_RAM_BACK_TO_BACK_RD(0:63)
218 if (txc_p0_ro_ram_rd_b2b == 1);
219
220 state s_TXC_P0_RAM_RD_AND_WR(0:1023)
221 if (niu_coverage_txc_1024_port0_RO_RAM.write_sig);
222
223 bad_state s_TXC_P0_RAM_RD_AND_WR_SAME_ADDR(0:1023)
224 if (niu_coverage_txc_1024_port0_RO_RAM.write_sig
225 && niu_coverage_txc_1024_port0_RO_RAM.read_sig
226 && niu_coverage_txc_1024_port0_RO_RAM.read_ptr==niu_coverage_txc_1024_port0_RO_RAM.write_ptr);
227
228 state s_TXC_P0_RAM_RD_AND_WR_NOT_SAME_ADDR(0:1023)
229 if (niu_coverage_txc_1024_port0_RO_RAM.write_sig
230 && niu_coverage_txc_1024_port0_RO_RAM.read_sig
231 && niu_coverage_txc_1024_port0_RO_RAM.read_ptr != niu_coverage_txc_1024_port0_RO_RAM.write_ptr);
232
233 trans t_TXC_P0_RO_RAM_RPTR_00 ( 0 -> 1);
234 trans t_TXC_P0_RO_RAM_RPTR_01 ( 1 -> 2);
235 trans t_TXC_P0_RO_RAM_RPTR_02 ( 2 -> 3);
236 trans t_TXC_P0_RO_RAM_RPTR_03 ( 3 -> 4);
237 trans t_TXC_P0_RO_RAM_RPTR_04 ( 4 -> 5);
238 trans t_TXC_P0_RO_RAM_RPTR_05 ( 5 -> 6);
239 trans t_TXC_P0_RO_RAM_RPTR_06 ( 6 -> 7);
240 trans t_TXC_P0_RO_RAM_RPTR_07 ( 7 -> 8);
241 trans t_TXC_P0_RO_RAM_RPTR_08 ( 8 -> 9);
242 trans t_TXC_P0_RO_RAM_RPTR_09 ( 9 -> 10);
243 trans t_TXC_P0_RO_RAM_RPTR_10 (10 -> 11);
244 trans t_TXC_P0_RO_RAM_RPTR_11 (11 -> 12);
245 trans t_TXC_P0_RO_RAM_RPTR_12 (12 -> 13);
246 trans t_TXC_P0_RO_RAM_RPTR_13 (13 -> 14);
247 trans t_TXC_P0_RO_RAM_RPTR_14 (14 -> 15);
248 trans t_TXC_P0_RO_RAM_RPTR_15 (15 -> 16);
249 trans t_TXC_P0_RO_RAM_RPTR_16 (16 -> 17);
250 trans t_TXC_P0_RO_RAM_RPTR_17 (17 -> 18);
251 trans t_TXC_P0_RO_RAM_RPTR_18 (18 -> 19);
252 trans t_TXC_P0_RO_RAM_RPTR_19 (19 -> 20);
253 trans t_TXC_P0_RO_RAM_RPTR_20 (20 -> 21);
254 trans t_TXC_P0_RO_RAM_RPTR_21 (21 -> 22);
255 trans t_TXC_P0_RO_RAM_RPTR_22 (22 -> 23);
256 trans t_TXC_P0_RO_RAM_RPTR_23 (23 -> 24);
257 trans t_TXC_P0_RO_RAM_RPTR_24 (24 -> 25);
258 trans t_TXC_P0_RO_RAM_RPTR_25 (25 -> 26);
259 trans t_TXC_P0_RO_RAM_RPTR_26 (26 -> 27);
260 trans t_TXC_P0_RO_RAM_RPTR_27 (27 -> 28);
261 trans t_TXC_P0_RO_RAM_RPTR_28 (28 -> 29);
262 trans t_TXC_P0_RO_RAM_RPTR_29 (29 -> 30);
263 trans t_TXC_P0_RO_RAM_RPTR_30 (30 -> 31);
264 trans t_TXC_P0_RO_RAM_RPTR_31 (31 -> 32);
265 trans t_TXC_P0_RO_RAM_RPTR_32 (32 -> 33);
266 trans t_TXC_P0_RO_RAM_RPTR_33 (33 -> 34);
267 trans t_TXC_P0_RO_RAM_RPTR_34 (34 -> 35);
268 trans t_TXC_P0_RO_RAM_RPTR_35 (35 -> 36);
269 trans t_TXC_P0_RO_RAM_RPTR_36 (36 -> 37);
270 trans t_TXC_P0_RO_RAM_RPTR_37 (37 -> 38);
271 trans t_TXC_P0_RO_RAM_RPTR_38 (38 -> 39);
272 trans t_TXC_P0_RO_RAM_RPTR_39 (39 -> 40);
273 trans t_TXC_P0_RO_RAM_RPTR_40 (40 -> 41);
274 trans t_TXC_P0_RO_RAM_RPTR_41 (41 -> 42);
275 trans t_TXC_P0_RO_RAM_RPTR_42 (42 -> 43);
276 trans t_TXC_P0_RO_RAM_RPTR_43 (43 -> 44);
277 trans t_TXC_P0_RO_RAM_RPTR_44 (44 -> 45);
278 trans t_TXC_P0_RO_RAM_RPTR_45 (45 -> 46);
279 trans t_TXC_P0_RO_RAM_RPTR_46 (46 -> 47);
280 trans t_TXC_P0_RO_RAM_RPTR_47 (47 -> 48);
281 trans t_TXC_P0_RO_RAM_RPTR_48 (48 -> 49);
282 trans t_TXC_P0_RO_RAM_RPTR_49 (49 -> 50);
283 trans t_TXC_P0_RO_RAM_RPTR_50 (50 -> 51);
284 trans t_TXC_P0_RO_RAM_RPTR_51 (51 -> 52);
285 trans t_TXC_P0_RO_RAM_RPTR_52 (52 -> 53);
286 trans t_TXC_P0_RO_RAM_RPTR_53 (53 -> 54);
287 trans t_TXC_P0_RO_RAM_RPTR_54 (54 -> 55);
288 trans t_TXC_P0_RO_RAM_RPTR_55 (55 -> 56);
289 trans t_TXC_P0_RO_RAM_RPTR_56 (56 -> 57);
290 trans t_TXC_P0_RO_RAM_RPTR_57 (57 -> 58);
291 trans t_TXC_P0_RO_RAM_RPTR_58 (58 -> 59);
292 trans t_TXC_P0_RO_RAM_RPTR_59 (59 -> 60);
293 trans t_TXC_P0_RO_RAM_RPTR_60 (60 -> 61);
294 trans t_TXC_P0_RO_RAM_RPTR_61 (61 -> 62);
295 trans t_TXC_P0_RO_RAM_RPTR_62 (62 -> 63);
296 trans t_TXC_P0_RO_RAM_RPTR_63 (63 -> 0);
297 }
298 }
299
300 coverage_group niu_tx_coverage_txc_fifo_wr_group
301 {
302 sample_event = @(posedge niu_coverage_txc_1024_port0_RO_RAM.clk);
303 //sample_event = wait_var(txc_p0_ro_ram_wr_addr);
304
305 sample niu_coverage_txc_1024_port0_RO_RAM.write_ptr
306 {
307 state s_TXC_P0_RO_RAM_FULL(0:63)
308 if (txc_p0_ro_ram_size == 64);
309
310 state s_TXC_P0_RO_RAM_WR(0:63)
311 if (niu_coverage_txc_1024_port0_RO_RAM.write_sig === 1'b1);
312
313 state s_TXC_P0_RO_RAM_BACK_TO_BACK_WR(0:63)
314 if (txc_p0_ro_ram_wr_b2b == 1);
315
316 trans t_TXC_P0_RO_RAM_WPTR_00 ( 0 -> 1);
317 trans t_TXC_P0_RO_RAM_WPTR_01 ( 1 -> 2);
318 trans t_TXC_P0_RO_RAM_WPTR_02 ( 2 -> 3);
319 trans t_TXC_P0_RO_RAM_WPTR_03 ( 3 -> 4);
320 trans t_TXC_P0_RO_RAM_WPTR_04 ( 4 -> 5);
321 trans t_TXC_P0_RO_RAM_WPTR_05 ( 5 -> 6);
322 trans t_TXC_P0_RO_RAM_WPTR_06 ( 6 -> 7);
323 trans t_TXC_P0_RO_RAM_WPTR_07 ( 7 -> 8);
324 trans t_TXC_P0_RO_RAM_WPTR_08 ( 8 -> 9);
325 trans t_TXC_P0_RO_RAM_WPTR_09 ( 9 -> 10);
326 trans t_TXC_P0_RO_RAM_WPTR_10 (10 -> 11);
327 trans t_TXC_P0_RO_RAM_WPTR_11 (11 -> 12);
328 trans t_TXC_P0_RO_RAM_WPTR_12 (12 -> 13);
329 trans t_TXC_P0_RO_RAM_WPTR_13 (13 -> 14);
330 trans t_TXC_P0_RO_RAM_WPTR_14 (14 -> 15);
331 trans t_TXC_P0_RO_RAM_WPTR_15 (15 -> 16);
332 trans t_TXC_P0_RO_RAM_WPTR_16 (16 -> 17);
333 trans t_TXC_P0_RO_RAM_WPTR_17 (17 -> 18);
334 trans t_TXC_P0_RO_RAM_WPTR_18 (18 -> 19);
335 trans t_TXC_P0_RO_RAM_WPTR_19 (19 -> 20);
336 trans t_TXC_P0_RO_RAM_WPTR_20 (20 -> 21);
337 trans t_TXC_P0_RO_RAM_WPTR_21 (21 -> 22);
338 trans t_TXC_P0_RO_RAM_WPTR_22 (22 -> 23);
339 trans t_TXC_P0_RO_RAM_WPTR_23 (23 -> 24);
340 trans t_TXC_P0_RO_RAM_WPTR_24 (24 -> 25);
341 trans t_TXC_P0_RO_RAM_WPTR_25 (25 -> 26);
342 trans t_TXC_P0_RO_RAM_WPTR_26 (26 -> 27);
343 trans t_TXC_P0_RO_RAM_WPTR_27 (27 -> 28);
344 trans t_TXC_P0_RO_RAM_WPTR_28 (28 -> 29);
345 trans t_TXC_P0_RO_RAM_WPTR_29 (29 -> 30);
346 trans t_TXC_P0_RO_RAM_WPTR_30 (30 -> 31);
347 trans t_TXC_P0_RO_RAM_WPTR_31 (31 -> 32);
348 trans t_TXC_P0_RO_RAM_WPTR_32 (32 -> 33);
349 trans t_TXC_P0_RO_RAM_WPTR_33 (33 -> 34);
350 trans t_TXC_P0_RO_RAM_WPTR_34 (34 -> 35);
351 trans t_TXC_P0_RO_RAM_WPTR_35 (35 -> 36);
352 trans t_TXC_P0_RO_RAM_WPTR_36 (36 -> 37);
353 trans t_TXC_P0_RO_RAM_WPTR_37 (37 -> 38);
354 trans t_TXC_P0_RO_RAM_WPTR_38 (38 -> 39);
355 trans t_TXC_P0_RO_RAM_WPTR_39 (39 -> 40);
356 trans t_TXC_P0_RO_RAM_WPTR_40 (40 -> 41);
357 trans t_TXC_P0_RO_RAM_WPTR_41 (41 -> 42);
358 trans t_TXC_P0_RO_RAM_WPTR_42 (42 -> 43);
359 trans t_TXC_P0_RO_RAM_WPTR_43 (43 -> 44);
360 trans t_TXC_P0_RO_RAM_WPTR_44 (44 -> 45);
361 trans t_TXC_P0_RO_RAM_WPTR_45 (45 -> 46);
362 trans t_TXC_P0_RO_RAM_WPTR_46 (46 -> 47);
363 trans t_TXC_P0_RO_RAM_WPTR_47 (47 -> 48);
364 trans t_TXC_P0_RO_RAM_WPTR_48 (48 -> 49);
365 trans t_TXC_P0_RO_RAM_WPTR_49 (49 -> 50);
366 trans t_TXC_P0_RO_RAM_WPTR_50 (50 -> 51);
367 trans t_TXC_P0_RO_RAM_WPTR_51 (51 -> 52);
368 trans t_TXC_P0_RO_RAM_WPTR_52 (52 -> 53);
369 trans t_TXC_P0_RO_RAM_WPTR_53 (53 -> 54);
370 trans t_TXC_P0_RO_RAM_WPTR_54 (54 -> 55);
371 trans t_TXC_P0_RO_RAM_WPTR_55 (55 -> 56);
372 trans t_TXC_P0_RO_RAM_WPTR_56 (56 -> 57);
373 trans t_TXC_P0_RO_RAM_WPTR_57 (57 -> 58);
374 trans t_TXC_P0_RO_RAM_WPTR_58 (58 -> 59);
375 trans t_TXC_P0_RO_RAM_WPTR_59 (59 -> 60);
376 trans t_TXC_P0_RO_RAM_WPTR_60 (60 -> 61);
377 trans t_TXC_P0_RO_RAM_WPTR_61 (61 -> 62);
378 trans t_TXC_P0_RO_RAM_WPTR_62 (62 -> 63);
379 trans t_TXC_P0_RO_RAM_WPTR_63 (63 -> 0);
380 }
381 }
382
383 task new();
384 task niu_rx_control_fifo_cond(control_fifo_cov_port port_bind, integer port_num);
385 task niu_txc_p0_ro_ram_cond();
386 task niu_rx_err_cond();
387} //class niu_intf_coverage
388
389task niu_intf_coverage::new()
390{
391 printf("COVERAGE OBJECT in NEW\n");
392 niu_rx_control_fifo_group_1st_cycle_port0 = new();
393#ifdef DISABLE_FOR_NOW
394 niu_rx_control_fifo_group_2nd_cycle_port0 = new();
395 niu_rx_control_fifo_group_1st_cycle_port1 = new();
396 niu_rx_control_fifo_group_2nd_cycle_port1 = new();
397#endif
398
399 niu_coverage_err_group = new();
400 niu_tx_coverage_txc_fifo_rd_group = new();
401 niu_tx_coverage_txc_fifo_wr_group = new();
402 niu_coverage_mac_xpcs_state_group = new();
403
404 fork
405 niu_rx_err_cond();
406 niu_rx_control_fifo_cond(control_fifo_p0, Port0);
407 niu_rx_control_fifo_cond(control_fifo_p1, Port1);
408 niu_txc_p0_ro_ram_cond();
409 join none
410}
411
412task niu_intf_coverage::niu_rx_control_fifo_cond(control_fifo_cov_port port_bind, integer port_num)
413{
414 integer num_of_cycle = 0;
415
416 while (1)
417 {
418 @ (posedge port_bind.$clk);
419
420 if (port_bind.$control_fifo_ack==1'b1 && num_of_cycle==0)
421 {
422 printf("%0d: Coverage : 1st Cycle Control fifo = %h\n",
423 {get_time(HI), get_time(LO)}, port_bind.$control_fifo_data[129:0]);
424
425 control_fifo_data = port_bind.$control_fifo_data[129:0];
426
427 se_bit = control_fifo_data[76];
428 drop_pkt = control_fifo_data[77];
429 fflp_hw_err = control_fifo_data[78];
430 mac_promiscuous = control_fifo_data[79];
431 tt_err = control_fifo_data[86];
432 tt_succeed = control_fifo_data[87];
433 hash_sub_index = control_fifo_data[90:88];
434 hzfvld = control_fifo_data[91];
435 exact = control_fifo_data[92];
436 hash_hit = control_fifo_data[93];
437 table_rdc[1:0] = control_fifo_data[95:94];
438 tcam_m_index = control_fifo_data[103:96];
439 table_rdc[4:2] = control_fifo_data[106:104];
440 default_rdc = control_fifo_data[111:107];
441 tzfvld = control_fifo_data[112];
442 tres = control_fifo_data[114:113];
443 tcam_hit = control_fifo_data[115];
444 bad_ip = control_fifo_data[116];
445 no_port = control_fifo_data[117];
446 llc_snap = control_fifo_data[118];
447 vlan = control_fifo_data[119];
448 classs = control_fifo_data[124:120];
449 mac_check = control_fifo_data[125];
450 sop = control_fifo_data[128];
451 mac_port = control_fifo_data[127:126];
452 eop = control_fifo_data[129];
453
454 //if (port_num == Port0)
455 // control_fifo_data_port0_1st_cycle_cov = !control_fifo_data_port0_1st_cycle_cov;
456 //if (port_num == Port1)
457 // control_fifo_data_port1_1st_cycle_cov = !control_fifo_data_port1_1st_cycle_cov;
458 //if (port_num == Port2)
459 // control_fifo_data_port2_1st_cycle_cov = !control_fifo_data_port2_1st_cycle_cov;
460 //if (port_num == Port3)
461 // control_fifo_data_port3_1st_cycle_cov = !control_fifo_data_port3_1st_cycle_cov;
462
463 num_of_cycle = num_of_cycle + 1;
464 }
465 else
466 {
467 if (port_bind.$control_fifo_ack == 1'b1)
468 {
469 printf("%0d: Coverage : 2nd Cycle Control fifo = %h\n",
470 {get_time(HI), get_time(LO)}, port_bind.$control_fifo_data[129:0]);
471
472 control_fifo_data = port_bind.$control_fifo_data[129:0];
473
474 tcp_seq = control_fifo_data[71:40];
475 tcp_hdr_len = control_fifo_data[75:72];
476 ipv4_hdr_len = control_fifo_data[79:76];
477 l3_pkt_len = control_fifo_data[95:80];
478 zc_rdc = control_fifo_data[100:96];
479 dmaw_type = control_fifo_data[102:101];
480 ulp_type = control_fifo_data[105:104];
481 pkt_id = control_fifo_data[109:106];
482 ip_ver = control_fifo_data[110];
483 usr_data = control_fifo_data[127:112];
484 sop_2 = control_fifo_data[128];
485 eop_2 = control_fifo_data[129];
486 eop = control_fifo_data[129];
487
488 num_of_cycle = 0; // reset
489
490 if (port_num == Port0)
491 control_fifo_data_port0_2nd_cycle_cov = !control_fifo_data_port0_2nd_cycle_cov;
492 if (port_num == Port1)
493 control_fifo_data_port1_2nd_cycle_cov = !control_fifo_data_port1_2nd_cycle_cov;
494 if (port_num == Port2)
495 control_fifo_data_port2_2nd_cycle_cov = !control_fifo_data_port2_2nd_cycle_cov;
496 if (port_num == Port3)
497 control_fifo_data_port3_2nd_cycle_cov = !control_fifo_data_port3_2nd_cycle_cov;
498 }
499 }
500 } // end of while
501}
502
503task niu_intf_coverage::niu_txc_p0_ro_ram_cond()
504{
505 while(1) {
506 @ (posedge niu_coverage_txc_1024_port0_RO_RAM.clk);
507 if (niu_coverage_txc_1024_port0_RO_RAM.write_sig == 1'b1)
508 {
509 txc_p0_ro_ram_size++;
510 }
511 if (niu_coverage_txc_1024_port0_RO_RAM.read_sig == 1'b1)
512 {
513 txc_p0_ro_ram_size--;
514 }
515
516 if (niu_coverage_txc_1024_port0_RO_RAM.write_sig
517 && niu_coverage_txc_1024_port0_RO_RAM.read_sig
518 && niu_coverage_txc_1024_port0_RO_RAM.read_ptr==niu_coverage_txc_1024_port0_RO_RAM.write_ptr)
519 {
520 printf("ROB: (%x)read_ptr==write_ptr(%x) at %d\n",
521 niu_coverage_txc_1024_port0_RO_RAM.read_ptr,
522 niu_coverage_txc_1024_port0_RO_RAM.write_ptr,
523 {get_time(HI), get_time(LO)});
524 }
525
526 txc_p0_ro_ram_trig = !txc_p0_ro_ram_trig;
527 }
528}
529
530task niu_intf_coverage::niu_rx_err_cond()
531{
532 @ (posedge niu_coverage_err_det.clk);
533
534 while(1) {
535 @ (posedge niu_coverage_err_det.clk);
536
537 if (niu_coverage_err_det.control_fifo_err0 == 1'b1
538 || niu_coverage_err_det.control_fifo_err1 == 1'b1)
539 {
540 if (niu_coverage_err_det.control_fifo_err0) printf("ROB: Triggering fifo_err0\n");
541 if (niu_coverage_err_det.control_fifo_err1) printf("ROB: Triggering fifo_err1\n");
542
543 trigger(niu_coverage_err_trig);
544 }
545 }
546}
Full OpenSPARC design & verification tarball including full HDL.