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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / niu_intr / niu_intr_mon.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_intr_mon.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "neptune_defines.vri"
37#include "cMesg.vrh"
38
39// If NIU_GATE consider this a blank file
40#ifdef NIU_GATE
41 // Do nothing
42#else
43#include "niu_intr_mon.if.vri"
44
45
46#define TIME {get_time(HI), get_time(LO)}
47#define TRUE 1
48#define FALSE 0
49
50#define ASSERTED 1
51#define ASSERTED_LOW 0
52#define DEASSERTED 0
53#define DEASSERTED_LOW 1
54
55
56extern Mesg be_msg;
57
58
59
60
61class CNiuIntMonitor
62{
63 string name = "Intr_Mon";
64
65 int_mon_port int_monitor;
66 integer INT_MON_ON=0;
67
68 integer int_active_rel_ovrlap = 0;
69 integer int_active_rel_ibusy_ovrlap = 0;
70
71 integer activate_ig_sm_after_ibusy = 0;
72 integer activate_ig_sm_during_ibusy = 0;
73
74 integer ibusy_after_activate_ig_sm = 0;
75 integer ibusy_during_activate_ig_sm = 0;
76
77 integer ibusy_hi_within_actv = 0;
78 integer actv_asserts_during_ibusy = 0;
79 integer intr_rel_group0 = 0;
80 integer intr_rel_group16 = 0;
81 integer intr_rel_group32 = 0;
82 integer intr_rel_group48 = 0;
83 integer intr_rel_othergrp = 0;
84
85 integer group0_intr_rel_after_ibusy = 0;
86 integer group16_intr_rel_after_ibusy = 0;
87 integer group32_intr_rel_after_ibusy = 0;
88 integer group48_intr_rel_after_ibusy = 0;
89
90 integer activate_ig_sm_trigger = 0;
91
92 integer ibusy_trigger = 0;
93 integer latch_rel_info = 0;
94
95
96
97 coverage_group req_rel_hit_skew0_noibusy_cov {
98 sample_event = @(int_monitor.$req_rel_hit_skew0_noibusy);
99
100 sample int_monitor.$req_rel_hit_skew0_noibusy { state req_rel_hit_skew0_noibusy(0:1)
101 if (int_monitor.$req_rel_hit_skew0_noibusy == 1); }
102 }
103
104 coverage_group req_rel_hit_skew1_noibusy_cov {
105 sample_event = @(int_monitor.$req_rel_hit_skew1_noibusy);
106
107 sample int_monitor.$req_rel_hit_skew1_noibusy { state req_rel_hit_skew1_noibusy(0:1)
108 if (int_monitor.$req_rel_hit_skew1_noibusy == 1); }
109 }
110
111 coverage_group req_rel_hit_skew2_noibusy_cov {
112 sample_event = @(int_monitor.$req_rel_hit_skew2_noibusy);
113
114 sample int_monitor.$req_rel_hit_skew2_noibusy { state req_rel_hit_skew2_noibusy(0:1)
115 if (int_monitor.$req_rel_hit_skew2_noibusy == 1); }
116 }
117
118 coverage_group req_rel_hit_skew3_noibusy_cov {
119 sample_event = @(int_monitor.$req_rel_hit_skew3_noibusy);
120
121 sample int_monitor.$req_rel_hit_skew3_noibusy { state req_rel_hit_skew3_noibusy(0:1)
122 if (int_monitor.$req_rel_hit_skew3_noibusy == 1); }
123 }
124
125 coverage_group req_rel_hit_skew4_noibusy_cov {
126 sample_event = @(int_monitor.$req_rel_hit_skew4_noibusy);
127
128 sample int_monitor.$req_rel_hit_skew4_noibusy { state req_rel_hit_skew4_noibusy(0:1)
129 if (int_monitor.$req_rel_hit_skew4_noibusy == 1); }
130 }
131
132 coverage_group req_rel_hit_skew5_noibusy_cov {
133 sample_event = @(int_monitor.$req_rel_hit_skew5_noibusy);
134
135 sample int_monitor.$req_rel_hit_skew5_noibusy { state req_rel_hit_skew5_noibusy(0:1)
136 if (int_monitor.$req_rel_hit_skew5_noibusy == 1); }
137 }
138
139 coverage_group req_rel_hit_skew0_ibusy_cov {
140 sample_event = @(int_monitor.$req_rel_hit_skew0_ibusy);
141
142 sample int_monitor.$req_rel_hit_skew0_ibusy { state req_rel_hit_skew0_ibusy(0:1)
143 if (int_monitor.$req_rel_hit_skew0_ibusy == 1); }
144 }
145
146 coverage_group req_rel_hit_skew1_ibusy_cov {
147 sample_event = @(int_monitor.$req_rel_hit_skew1_ibusy);
148
149 sample int_monitor.$req_rel_hit_skew1_ibusy { state req_rel_hit_skew1_ibusy(0:1)
150 if (int_monitor.$req_rel_hit_skew1_ibusy == 1); }
151
152 }
153 coverage_group req_rel_hit_skew2_ibusy_cov {
154 sample_event = @(int_monitor.$req_rel_hit_skew2_ibusy);
155
156 sample int_monitor.$req_rel_hit_skew2_ibusy { state req_rel_hit_skew2_ibusy(0:1)
157 if (int_monitor.$req_rel_hit_skew2_ibusy == 1); }
158
159 }
160 coverage_group req_rel_hit_skew3_ibusy_cov {
161 sample_event = @(int_monitor.$req_rel_hit_skew3_ibusy);
162
163 sample int_monitor.$req_rel_hit_skew3_ibusy { state req_rel_hit_skew3_ibusy(0:1)
164 if (int_monitor.$req_rel_hit_skew3_ibusy == 1); }
165 }
166
167 coverage_group req_rel_hit_skew4_ibusy_cov {
168 sample_event = @(int_monitor.$req_rel_hit_skew4_ibusy);
169
170 sample int_monitor.$req_rel_hit_skew4_ibusy { state req_rel_hit_skew4_ibusy(0:1)
171 if (int_monitor.$req_rel_hit_skew4_ibusy == 1); }
172
173 }
174 coverage_group req_rel_hit_skew5_ibusy_cov {
175 sample_event = @(int_monitor.$req_rel_hit_skew5_ibusy);
176
177 sample int_monitor.$req_rel_hit_skew5_ibusy { state req_rel_hit_skew5_ibusy(0:1)
178 if (int_monitor.$req_rel_hit_skew5_ibusy == 1); }
179 }
180
181
182
183
184
185 coverage_group rel_req_hit_skew1_noibusy_cov {
186 sample_event = @(int_monitor.$rel_req_hit_skew1_noibusy );
187
188 sample int_monitor.$rel_req_hit_skew1_noibusy { state rel_req_hit_skew1_noibusy(0:1)
189 if (int_monitor.$rel_req_hit_skew1_noibusy == 1); }
190
191 }
192 coverage_group rel_req_hit_skew2_noibusy_cov {
193 sample_event = @(int_monitor.$rel_req_hit_skew2_noibusy );
194
195 sample int_monitor.$rel_req_hit_skew2_noibusy { state rel_req_hit_skew2_noibusy(0:1)
196 if (int_monitor.$rel_req_hit_skew2_noibusy == 1); }
197 }
198
199 coverage_group rel_req_hit_skew3_noibusy_cov {
200 sample_event = @(int_monitor.$rel_req_hit_skew3_noibusy );
201
202 sample int_monitor.$rel_req_hit_skew3_noibusy { state rel_req_hit_skew3_noibusy(0:1)
203 if (int_monitor.$rel_req_hit_skew3_noibusy == 1); }
204 }
205
206 coverage_group rel_req_hit_skew4_noibusy_cov {
207 sample_event = @(int_monitor.$rel_req_hit_skew4_noibusy );
208
209 sample int_monitor.$rel_req_hit_skew4_noibusy { state rel_req_hit_skew4_noibusy(0:1)
210 if (int_monitor.$rel_req_hit_skew4_noibusy == 1); }
211 }
212
213 coverage_group rel_req_hit_skew5_noibusy_cov {
214 sample_event = @(int_monitor.$rel_req_hit_skew5_noibusy );
215
216 sample int_monitor.$rel_req_hit_skew5_noibusy { state rel_req_hit_skew5_noibusy(0:1)
217 if (int_monitor.$rel_req_hit_skew5_noibusy == 1); }
218 }
219
220 coverage_group rel_req_hit_skew1_ibusy_cov {
221 sample_event = @(int_monitor.$rel_req_hit_skew1_ibusy );
222
223 sample int_monitor.$rel_req_hit_skew1_ibusy { state rel_req_hit_skew1_ibusy(0:1)
224 if (int_monitor.$rel_req_hit_skew1_ibusy == 1); }
225 }
226
227 coverage_group rel_req_hit_skew2_ibusy_cov {
228 sample_event = @(int_monitor.$rel_req_hit_skew2_ibusy );
229
230 sample int_monitor.$rel_req_hit_skew2_ibusy { state rel_req_hit_skew2_ibusy(0:1)
231 if (int_monitor.$rel_req_hit_skew2_ibusy == 1); }
232 }
233
234 coverage_group rel_req_hit_skew3_ibusy_cov {
235 sample_event = @(int_monitor.$rel_req_hit_skew3_ibusy );
236
237 sample int_monitor.$rel_req_hit_skew3_ibusy { state rel_req_hit_skew3_ibusy(0:1)
238 if (int_monitor.$rel_req_hit_skew3_ibusy == 1); }
239 }
240
241 coverage_group rel_req_hit_skew4_ibusy_cov {
242 sample_event = @(int_monitor.$rel_req_hit_skew4_ibusy );
243
244 sample int_monitor.$rel_req_hit_skew4_ibusy { state rel_req_hit_skew4_ibusy(0:1)
245 if (int_monitor.$rel_req_hit_skew4_ibusy == 1); }
246 }
247
248 coverage_group rel_req_hit_skew5_ibusy_cov {
249 sample_event = @(int_monitor.$rel_req_hit_skew5_ibusy );
250
251 sample int_monitor.$rel_req_hit_skew5_ibusy { state rel_req_hit_skew5_ibusy(0:1)
252 if (int_monitor.$rel_req_hit_skew5_ibusy == 1); }
253
254 }
255
256
257
258
259 coverage_group int_mon_actv_asserts_during_ibusy_cov {
260 sample_event = @(int_monitor.$ibusy);
261
262 sample actv_asserts_during_ibusy
263 {
264 state actv_asserts_during_ibusy(0:1)
265 if (actv_asserts_during_ibusy == 1);
266 }
267 }
268
269 coverage_group int_mon_ibusy_hi_within_actv_cov {
270 sample_event = @(int_monitor.$activate_ig_sm);
271
272 sample ibusy_hi_within_actv
273 {
274 state ibusy_hi_within_actv(0:1)
275 if (ibusy_hi_within_actv == 1);
276 }
277 }
278
279 coverage_group group0_intr_rel_after_ibusy_cov {
280 sample_event = wait_var(group0_intr_rel_after_ibusy);
281
282 sample group0_intr_rel_after_ibusy
283 {
284 state group0_intr_rel_after_ibusy(0:1)
285 if (group0_intr_rel_after_ibusy == 1);
286 }
287 }
288
289 coverage_group group16_intr_rel_after_ibusy_cov {
290 sample_event = wait_var(group16_intr_rel_after_ibusy);
291
292 sample group16_intr_rel_after_ibusy
293 {
294 state group16_intr_rel_after_ibusy(0:1)
295 if (group16_intr_rel_after_ibusy == 1);
296 }
297
298 }
299
300 coverage_group group32_intr_rel_after_ibusy_cov {
301 sample_event = wait_var(group32_intr_rel_after_ibusy);
302
303 sample group32_intr_rel_after_ibusy
304 {
305 state group32_intr_rel_after_ibusy(0:1)
306 if (group32_intr_rel_after_ibusy == 1);
307 }
308
309 }
310
311 coverage_group group48_intr_rel_after_ibusy_cov {
312 sample_event = wait_var(group48_intr_rel_after_ibusy);
313
314 sample group48_intr_rel_after_ibusy
315 {
316 state group48_intr_rel_after_ibusy(0:1)
317 if (group48_intr_rel_after_ibusy == 1);
318 }
319
320 }
321
322
323
324
325
326 task new();
327 task monitor_sm_active_rel_overlap();
328 task monitor_sm_active_rel_overlap_during_ibusy();
329 task monitor_int_sm_active_during_ibusy();
330 task monitor_ibusy_during_int_sm_active();
331 task monitor_smrel_4grp_after_ibusy();
332}
333
334
335 task CNiuIntMonitor::new()
336 {
337 int_monitor = int_mon_port_bind;
338
339 if(get_plus_arg(CHECK,"INT_MON_ON")) {
340 INT_MON_ON = 1;
341
342 req_rel_hit_skew0_noibusy_cov = new();
343 req_rel_hit_skew1_noibusy_cov = new();
344 req_rel_hit_skew2_noibusy_cov = new();
345 req_rel_hit_skew3_noibusy_cov = new();
346 req_rel_hit_skew4_noibusy_cov = new();
347 req_rel_hit_skew5_noibusy_cov = new();
348 req_rel_hit_skew0_ibusy_cov = new();
349 req_rel_hit_skew1_ibusy_cov = new();
350 req_rel_hit_skew2_ibusy_cov = new();
351 req_rel_hit_skew3_ibusy_cov = new();
352 req_rel_hit_skew4_ibusy_cov = new();
353 req_rel_hit_skew5_ibusy_cov = new();
354
355 rel_req_hit_skew1_noibusy_cov = new();
356 rel_req_hit_skew2_noibusy_cov = new();
357 rel_req_hit_skew3_noibusy_cov = new();
358 rel_req_hit_skew4_noibusy_cov = new();
359 rel_req_hit_skew5_noibusy_cov = new();
360 rel_req_hit_skew1_ibusy_cov = new();
361 rel_req_hit_skew2_ibusy_cov = new();
362 rel_req_hit_skew3_ibusy_cov = new();
363 rel_req_hit_skew4_ibusy_cov = new();
364 rel_req_hit_skew5_ibusy_cov = new();
365
366 int_mon_actv_asserts_during_ibusy_cov = new();
367 int_mon_ibusy_hi_within_actv_cov = new();
368
369 group0_intr_rel_after_ibusy_cov = new();
370 group16_intr_rel_after_ibusy_cov = new();
371 group32_intr_rel_after_ibusy_cov = new();
372 group48_intr_rel_after_ibusy_cov = new();
373
374
375 printf(" Intr_mon: INT Monitor coverage objects enabled... \n");
376
377
378 }
379
380 fork
381 monitor_sm_active_rel_overlap();
382 monitor_sm_active_rel_overlap_during_ibusy();
383 monitor_int_sm_active_during_ibusy();
384 monitor_ibusy_during_int_sm_active();
385 monitor_smrel_4grp_after_ibusy();
386 join none
387
388 }
389
390
391
392 /* Monitor if activate_ig_sm signal overlap with release signal */
393 task CNiuIntMonitor::monitor_sm_active_rel_overlap()
394 {
395
396 /* monitor state machine activate */
397 if(INT_MON_ON){
398 printf (" Monitoring activate_ig_sm...\n");
399
400 while(TRUE)
401 {
402 @ (int_monitor.$activate_ig_sm);
403 if(int_monitor.$activate_ig_sm_rel)
404 {
405 int_active_rel_ovrlap = 1;
406 printf (" Intr_mon: activate_ig_sm and activate_ig_sm_rel overlap occured...\n");
407 }
408 else
409 {
410 int_active_rel_ovrlap = 0;
411 }
412 }
413 }
414 }
415
416
417 /* Monitor if the overlap occurs when ibusy signal is high */
418 task CNiuIntMonitor::monitor_sm_active_rel_overlap_during_ibusy()
419 {
420
421 if(INT_MON_ON){
422 printf (" Monitoring if activate_ig_sm and rel occur during ibusy...\n");
423
424 while(TRUE)
425 {
426 @ (int_monitor.$ibusy);
427 if(int_monitor.$activate_ig_sm && int_monitor.$activate_ig_sm_rel)
428 {
429 int_active_rel_ibusy_ovrlap = 1;
430 printf (" Intr_mon: activate_ig_sm and activate_ig_sm_rel overlap with ibusy occured...\n");
431 }
432 else
433 {
434 int_active_rel_ibusy_ovrlap = 0;
435 }
436 }
437 }
438 }
439
440
441 /* Monitor if activate_ig_sm asserts while ibusy and deasserts after ibusy */
442 /* Test Case 13 */
443 task CNiuIntMonitor::monitor_int_sm_active_during_ibusy()
444 {
445
446 if(INT_MON_ON){
447 printf (" Monitoring activate_ig_sm during ibusy...\n");
448
449 while(TRUE)
450 {
451 @ (posedge int_monitor.$activate_ig_sm);
452 if(int_monitor.$ibusy)
453 {
454 activate_ig_sm_during_ibusy = 1;
455 }
456
457 @ (negedge int_monitor.$ibusy);
458 if(int_monitor.$activate_ig_sm && activate_ig_sm_during_ibusy )
459 {
460 actv_asserts_during_ibusy = 1;
461 printf (" Intr_mon: activate_ig_sm assert after ibusy, deasserts after ibusy...\n");
462 activate_ig_sm_during_ibusy = 0;
463 }
464
465 @ (negedge int_monitor.$activate_ig_sm);
466 if (actv_asserts_during_ibusy)
467 {
468 actv_asserts_during_ibusy = 0;
469 }
470
471 }
472 }
473 }
474
475 /* Monitor if ibusy gets asserted, then deasserted while activate_ig_sm is high */
476 /* Test Case 12 */
477 task CNiuIntMonitor::monitor_ibusy_during_int_sm_active()
478 {
479 /* monitor ibusy when state machine activate_ig is asserted */
480 if(INT_MON_ON){
481 printf (" Monitoring ibusy during activate_ig_sm...\n");
482
483 while(TRUE)
484 {
485 @ (posedge int_monitor.$ibusy);
486 if(int_monitor.$activate_ig_sm)
487 {
488 ibusy_during_activate_ig_sm = 1;
489 }
490
491 @ (negedge int_monitor.$ibusy);
492 if(int_monitor.$activate_ig_sm && ibusy_during_activate_ig_sm )
493 {
494 ibusy_hi_within_actv = 1;
495 printf (" Intr_mon: ibusy asserts and deasserts during activate_ig_sm...\n");
496 ibusy_during_activate_ig_sm = 0;
497 }
498 @ (negedge int_monitor.$activate_ig_sm);
499 if(ibusy_hi_within_actv)
500 {
501 ibusy_hi_within_actv = 0;
502 }
503
504 }
505 }
506 }
507
508
509
510 /* Monitor that sm_rel for groups 0, 16, 32, 48 is released when */
511 /* ibusy goes low... */
512 task CNiuIntMonitor::monitor_smrel_4grp_after_ibusy()
513 {
514 #define GROUP0 64'h0000000000000001
515 #define GROUP16 64'h0000000000010000
516 #define GROUP32 64'h0000000100000000
517 #define GROUP48 64'h0001000000000000
518
519 if(INT_MON_ON){
520 printf (" Monitoring sm_rel for int groups 0, 16, 32, 48...\n");
521
522 while(TRUE)
523 {
524 @ (posedge int_monitor.$activate_ig_sm_rel); /* intr_rel_group changes with activate_ig_sm_rel */
525 if(int_monitor.$ibusy) {
526 ibusy_trigger = 1;
527 }
528
529 @ (negedge CLOCK);
530 if(ibusy_trigger && ~latch_rel_info){
531 latch_rel_info = 1;
532 case( int_monitor.$intr_rel_group ) {
533 GROUP0: {
534 intr_rel_group0 = 1;
535
536 }
537 GROUP16: {
538 intr_rel_group16 = 1;
539
540 }
541 GROUP32: {
542 intr_rel_group32 = 1;
543
544 }
545 GROUP48: {
546 intr_rel_group48 = 1;
547
548 }
549 default: intr_rel_othergrp = 1;
550
551
552 }
553 }
554
555 @ (negedge int_monitor.$ibusy);
556 {
557 ibusy_trigger = 0;
558 latch_rel_info = 0;
559 if(int_monitor.$activate_ig_sm_rel){
560
561
562 if(intr_rel_group0) {
563 printf (" Intr_mon: group 0 intr_rel after ibusy\n"); /* this is where we count events... */
564 /* intr_rel_group0_count++; */
565 group0_intr_rel_after_ibusy = 1;
566
567 }
568 if(intr_rel_group16) {
569 printf (" Intr_mon: group 16 intr_rel after ibusy\n");
570 /* intr_rel_group16_count++; */
571 group16_intr_rel_after_ibusy = 1;
572
573 }
574 if(intr_rel_group32) {
575 printf (" Intr_mon: group 32 intr_rel after ibusy\n");
576 /* intr_rel_group32_count++; */
577 group32_intr_rel_after_ibusy = 1;
578 }
579 if(intr_rel_group48) {
580 printf (" Intr_mon: group 48 intr_rel after ibusy\n");
581 /* intr_rel_group48_count++; */
582 group48_intr_rel_after_ibusy = 1;
583 }
584
585 }
586
587 }
588
589
590 @ (negedge int_monitor.$activate_ig_sm_rel);
591 if(int_monitor.$ibusy && ibusy_trigger){
592 if(intr_rel_group0 || intr_rel_group16 || intr_rel_group32 || intr_rel_group48) {
593 be_msg.print(e_mesg_error, "Intr_mon", "", "intr_rel deasserted during ibusy for groups 0, 16, 32, 48 at time %0d. Exiting the simulation \n", get_time(LO));
594
595 }else{
596
597 if(intr_rel_group0) {
598 intr_rel_group0 = 0;
599 group0_intr_rel_after_ibusy = 0;
600
601 }
602 if(intr_rel_group16) {
603 intr_rel_group16 = 0;
604 group16_intr_rel_after_ibusy = 0;
605
606 }
607 if(intr_rel_group32) {
608 intr_rel_group32 = 0;
609 group32_intr_rel_after_ibusy = 0;
610
611 }
612 if(intr_rel_group48) {
613 intr_rel_group48 = 0;
614 group48_intr_rel_after_ibusy = 0;
615
616 }
617 if(intr_rel_othergrp) {
618 printf (" Intr_mon: intr_rel during ibusy for other groups\n");
619 intr_rel_othergrp = 0;
620 /* intr_rel_othergrp_count++; */
621 }
622 }
623
624
625 }
626 } // while
627 } // if(INT_MON_ON)
628 } // task
629
630
631
632#endif // if NIU_GATE... else...endif
633
634
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