projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: fflp_db.vr | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #define FFLP_DB | |
| 36 | ||
| 37 | extern class fflp_fwd_dec_cl; | |
| 38 | ||
| 39 | class fflp_fwd_dec_cl | |
| 40 | { | |
| 41 | bit multicast = 1'b0; | |
| 42 | bit [2:0] l2_option = 3'b0; | |
| 43 | bit [1:0] l3_version = 2'b00; | |
| 44 | bit [1:0] l4_protocol = 2'b00; | |
| 45 | bit [3:0] tcp_hdr_len = 4'b0000; | |
| 46 | bit push_bit = 1'b0; | |
| 47 | ||
| 48 | bit [31:0] seq_num = 32'h0000_0000; | |
| 49 | bit [15:0] translation_table_index = 16'b0000; // = translation_table_index for protocol = TCP | |
| 50 | // = SEC_index for protocol = IP_SEC | |
| 51 | bit drop_pkt = 1'b0; | |
| 52 | bit [1:0] pkt_dest = 2'b00; | |
| 53 | bit [1:0] pkt_mode = 2'b00; | |
| 54 | bit def_vlan_en = 1'b0; | |
| 55 | bit vlan_table_match = 1'b0; | |
| 56 | bit [2:0] priority = 3'b000; | |
| 57 | bit [7:0] qp_num = 8'h00; | |
| 58 | bit cam_match = 1'b0; | |
| 59 | } | |
| 60 | ||
| 61 | ||
| 62 | class fflp_db { | |
| 63 | // The following are passed by the fake ipp to the fflp | |
| 64 | ||
| 65 | bit null_packet = 1'b0; | |
| 66 | ||
| 67 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 68 | //@ FFLP Header related parameters @ | |
| 69 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 70 | bit raw_cam_key_mode = 1'b0; | |
| 71 | bit req_fifo_full = 1'b0; | |
| 72 | bit token_active = 1'b0; | |
| 73 | bit chksum_error = 1'b0; | |
| 74 | bit ad_drop_pkt = 1'b0; | |
| 75 | bit fflp_bypass = 1'b0; | |
| 76 | integer class_value = 0; | |
| 77 | integer token_box_index = 0; | |
| 78 | integer token_array_ptr = 0; | |
| 79 | bit [15:0] type = 16'h0; | |
| 80 | bit cfi = 1'b0; | |
| 81 | bit tagged = 1'b0; | |
| 82 | bit llc_snap = 1'b0; | |
| 83 | bit [15:0] tpid = 12'hxxx; | |
| 84 | bit [11:0] vlan = 12'hxxx; | |
| 85 | bit [2:0] priority = 3'hx; | |
| 86 | bit [12:0] frag = 13'hx; | |
| 87 | bit [3:0] hdr_len = 4'hx; | |
| 88 | bit [15:0] total_len = 16'hxxxx; | |
| 89 | bit [3:0] tcp_hdr_len = 4'hx; | |
| 90 | bit [2:0] ip_flags = 3'hx; | |
| 91 | bit [4:0] header_type = 5'hx; | |
| 92 | bit [4:0] hdr_type = 5'hx; | |
| 93 | bit [7:0] tcp_flags = 8'hxx; | |
| 94 | bit [7:0] protocol = 8'hxx; | |
| 95 | bit pkt_tcp = 1'b0; | |
| 96 | bit [7:0] next_hdr = 8'hxx; | |
| 97 | bit [4:0] region_key_class_match = 5'bxxxxx; | |
| 98 | bit [5:0] prefix_index = 6'h0; | |
| 99 | bit ipv6_prefix_addr_matched = 1'bx; | |
| 100 | bit [5:0] exp_class_value = 6'hx; | |
| 101 | bit [111:0] gen_expect_class = 112'hx; | |
| 102 | bit perfect_match = 0; | |
| 103 | integer ipp_ffl_hdr_cycles = 0; | |
| 104 | bit [2:0] ipp_ffl_mac_port = 3'h0; | |
| 105 | bit [127:0] ipp_ffl_data_wrd1 = 128'hx; | |
| 106 | bit [127:0] ipp_ffl_data_wrd2 = 128'hx; | |
| 107 | bit [127:0] ipp_ffl_data_wrd3 = 128'hx; | |
| 108 | bit [127:0] ipp_ffl_data_wrd4 = 128'hx; | |
| 109 | bit [127:0] ipp_ffl_data_wrd5 = 128'hx; | |
| 110 | bit [127:0] ipp_ffl_data_wrd6 = 128'hx; | |
| 111 | bit [7:0] ipp_ffl_mac_index = 8'h0; | |
| 112 | bit [11:0] ipp_ffl_mac_default = 12'h0; | |
| 113 | bit fwd_dec_collected = 0; | |
| 114 | bit collected_mac_ctrl_wrd = 0; | |
| 115 | bit [7:0] mac_addr_index = 0; | |
| 116 | bit [2:0] mac_port = 0; | |
| 117 | bit [3:0] version = 4'hx; | |
| 118 | bit no_port = 1'bx; | |
| 119 | bit [31:0] ipv4_dst_addr = 32'hx; | |
| 120 | bit [31:0] ipv4_src_addr = 32'hx; | |
| 121 | bit [15:0] dst_port_num = 16'hx; | |
| 122 | bit [15:0] src_port_num = 16'hx; | |
| 123 | bit [127:0] ipv6_dst_addr = 128'hx; | |
| 124 | bit [127:0] ipv6_src_addr = 128'hx; | |
| 125 | bit [31:0] seq_num = 32'hx; | |
| 126 | bit [31:0] sec_param_index = 32'h0; | |
| 127 | ||
| 128 | bit [287:0] cam_raw_key = 288'h0; | |
| 129 | ||
| 130 | bit [7:0] user_class_b0 = 8'hx; | |
| 131 | bit [7:0] user_class_b1 = 8'hx; | |
| 132 | bit [7:0] user_class_b2 = 8'hx; | |
| 133 | bit [7:0] user_class_b3 = 8'hx; | |
| 134 | bit [7:0] user_class_b4 = 8'hx; | |
| 135 | bit [7:0] user_class_b5 = 8'hx; | |
| 136 | bit [7:0] user_class_b6 = 8'hx; | |
| 137 | bit [7:0] user_class_b7 = 8'hx; | |
| 138 | bit [7:0] user_class_b8 = 8'hx; | |
| 139 | bit [7:0] user_class_b9 = 8'hx; | |
| 140 | bit [7:0] user_class_b10 = 8'hx; | |
| 141 | bit [7:0] user_class_b11 = 8'hx; | |
| 142 | bit [7:0] user_class_b12 = 8'hx; | |
| 143 | bit [7:0] user_class_b13 = 8'hx; | |
| 144 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 145 | //@ FFLP_CAM related parameters @ | |
| 146 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 147 | bit do_raw_cam_key = 1'b0; | |
| 148 | bit cur_lb_cycles_collected = 1'b0; | |
| 149 | bit [287:0] obs_cam_key = 288'h0; | |
| 150 | bit [287:0] exp_cam_key = 288'h0; | |
| 151 | bit [287:0] lb_obs_cam_key = 288'h0; | |
| 152 | bit [287:0] lb_exp_cam_key = 288'h0; | |
| 153 | bit expected_cam_key_type = 1'bx; | |
| 154 | bit [3:0] cam_inst = 4'hx; | |
| 155 | bit [2:0] cam_ltin = 3'hx; | |
| 156 | bit [2:0] lb_cam_ltin = 3'hx; | |
| 157 | bit [3:0] cam_segsel = 3'hx; | |
| 158 | bit [5:0] cam_gmask = 3'hx; | |
| 159 | bit cam_crb_cmp = 1'bx; | |
| 160 | bit cam_crb_rslt = 1'bx; | |
| 161 | bit cam_matchout = 1'bx; | |
| 162 | bit [23:0] cam_index = 24'hxx_xxxx; | |
| 163 | bit cam_match = 1'bx; | |
| 164 | bit cam_burst_ = 1'bx; | |
| 165 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 166 | //@ FFLP_ZBT SRAM related parameters @ | |
| 167 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 168 | bit vcam_parity = 1'b0; | |
| 169 | bit vram_parity = 1'b0; | |
| 170 | bit vlan_mmatch = 1'b0; | |
| 171 | bit ad_skip_bmc_transaction = 1'b0; | |
| 172 | bit expect_fflp_bmc_trans = 1'b0; | |
| 173 | bit [14:0] ad_backlog = 15'hx; | |
| 174 | bit [6:0] ad_cur_wght0 = 7'hx; | |
| 175 | bit [6:0] ad_cur_wght1 = 7'hx; | |
| 176 | bit ad_backlog_val = 1'bx; | |
| 177 | bit ad_cur_wght0_val = 1'bx; | |
| 178 | bit ad_cur_wght1_val = 1'bx; | |
| 179 | bit pkt_fin = 1'bx; | |
| 180 | bit pkt_sync = 1'bx; | |
| 181 | bit pkt_rst = 1'bx; | |
| 182 | bit pkt_psh = 1'bx; | |
| 183 | bit pkt_ack = 1'bx; | |
| 184 | bit pkt_urg = 1'bx; | |
| 185 | bit ad_sync = 1'bx; | |
| 186 | bit ad_map = 1'bx; | |
| 187 | bit ad_mode = 1'bx; | |
| 188 | bit ad_spawn = 1'bx; | |
| 189 | bit ad_cur_wght_used = 1'bx; | |
| 190 | bit [1:0] ad_lmask_sel = 2'hx; | |
| 191 | bit [15:0] ad_cam_index = 16'hxxxx; | |
| 192 | bit [16:0] no_spawn_cam_index = 17'hx_xxxx; | |
| 193 | bit [16:0] nfa_144_index = 17'hx_xxxx; | |
| 194 | bit [16:0] nfa_288_index = 17'hx_xxxx; | |
| 195 | ||
| 196 | fflp_fwd_dec_cl expected_fwd_dec; | |
| 197 | fflp_fwd_dec_cl collected_fwd_dec; | |
| 198 | ||
| 199 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 200 | //@ Default Entry Associative Data @ | |
| 201 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 202 | bit [35:0] zbtsram_rd_asdata_region1_c1 = 36'hx_xxxx_xxxx; | |
| 203 | bit [35:0] zbtsram_rd_asdata_region1_c2 = 36'hx_xxxx_xxxx; | |
| 204 | bit [35:0] zbtsram_rd_asdata_region1_c3 = 36'hx_xxxx_xxxx; | |
| 205 | bit [35:0] zbtsram_wr_asdata_region1_c4 = 36'hx_xxxx_xxxx; | |
| 206 | bit [35:0] asdata_with_chksum_region1_c1 = 36'hx_xxxx_xxxx; | |
| 207 | bit [35:0] asdata_with_chksum_region1_c2 = 36'hx_xxxx_xxxx; | |
| 208 | bit [35:0] asdata_with_chksum_region1_c3 = 36'hx_xxxx_xxxx; | |
| 209 | ||
| 210 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 211 | //@ Default Entry Associative Data @ | |
| 212 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 213 | bit [35:0] zbtsram_rd_asdata_region2_c1 = 36'hx_xxxx_xxxx; | |
| 214 | bit [35:0] zbtsram_rd_asdata_region2_c2 = 36'hx_xxxx_xxxx; | |
| 215 | bit [35:0] zbtsram_rd_asdata_region2_c3 = 36'hx_xxxx_xxxx; | |
| 216 | bit [35:0] zbtsram_wr_asdata_region2_c4 = 36'hx_xxxx_xxxx; | |
| 217 | bit [35:0] asdata_with_chksum_region2_c1 = 36'hx_xxxx_xxxx; | |
| 218 | bit [35:0] asdata_with_chksum_region2_c2 = 36'hx_xxxx_xxxx; | |
| 219 | bit [35:0] asdata_with_chksum_region2_c3 = 36'hx_xxxx_xxxx; | |
| 220 | ||
| 221 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 222 | //@ Default Entry Associative Data(load balancing) @ | |
| 223 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 224 | bit [35:0] lb_zbtsram_wr_asdata_region1_c1 = 36'hx_xxxx_xxxx; | |
| 225 | bit [35:0] lb_zbtsram_wr_asdata_region1_c2 = 36'hx_xxxx_xxxx; | |
| 226 | bit [35:0] lb_zbtsram_wr_asdata_region1_c3 = 36'hx_xxxx_xxxx; | |
| 227 | bit [35:0] lb_asdata_with_chksum_region1_c1 = 36'hx_xxxx_xxxx; | |
| 228 | bit [35:0] lb_asdata_with_chksum_region1_c2 = 36'hx_xxxx_xxxx; | |
| 229 | bit [35:0] lb_asdata_with_chksum_region1_c3 = 36'hx_xxxx_xxxx; | |
| 230 | ||
| 231 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 232 | //@ Default Entry Associative Data(load balancing) @ | |
| 233 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 234 | bit [35:0] lb_zbtsram_wr_asdata_region2_c1 = 36'hx_xxxx_xxxx; | |
| 235 | bit [35:0] lb_zbtsram_wr_asdata_region2_c2 = 36'hx_xxxx_xxxx; | |
| 236 | bit [35:0] lb_zbtsram_wr_asdata_region2_c3 = 36'hx_xxxx_xxxx; | |
| 237 | bit [35:0] lb_asdata_with_chksum_region2_c1 = 36'hx_xxxx_xxxx; | |
| 238 | bit [35:0] lb_asdata_with_chksum_region2_c2 = 36'hx_xxxx_xxxx; | |
| 239 | bit [35:0] lb_asdata_with_chksum_region2_c3 = 36'hx_xxxx_xxxx; | |
| 240 | ||
| 241 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 242 | //@ FFLP_BMC related parameters @ | |
| 243 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 244 | bit ecc_reported_rd2 = 1'b0; | |
| 245 | bit read2 = 1'b0; | |
| 246 | bit fflp_bmc_busy = 1'b1; | |
| 247 | bit fflp_lb_cam_busy = 1'b1; | |
| 248 | bit fflp_lb_cam_update_busy = 1'b1; | |
| 249 | bit double_fflp_bmc_rd = 1'b0; | |
| 250 | bit [15:0] lb_grp_ptr = 16'h0; | |
| 251 | ||
| 252 | bit [16:0] cam_index_wildcard_update = 17'h0; | |
| 253 | bit [1:0] cam_access_type_wildcard_update = 2'h0; | |
| 254 | bit [3:0] cam_inst_update = 4'h0; | |
| 255 | bit [2:0] cam_ltin_update = 3'h0; | |
| 256 | bit [3:0] cam_segsel_update = 4'h0; | |
| 257 | bit [5:0] cam_gmask_update = 6'h0; | |
| 258 | ||
| 259 | bit [20:0] exp_fflp_bmc_rd1_addr1; | |
| 260 | bit [20:0] exp_fflp_bmc_rd1_addr2; | |
| 261 | bit [20:0] exp_fflp_bmc_rd2_addr1; | |
| 262 | bit [20:0] exp_fflp_bmc_rd2_addr2; | |
| 263 | ||
| 264 | bit [20:0] obs_fflp_bmc_rd1_addr1; | |
| 265 | bit [20:0] obs_fflp_bmc_rd1_addr2; | |
| 266 | bit [20:0] obs_fflp_bmc_rd2_addr1; | |
| 267 | bit [20:0] obs_fflp_bmc_rd2_addr2; | |
| 268 | ||
| 269 | bit [127:0] obs_fflp_bmc_rd1_data0; | |
| 270 | bit [127:0] obs_fflp_bmc_rd1_data1; | |
| 271 | bit [127:0] obs_fflp_bmc_rd1_data2; | |
| 272 | bit [127:0] obs_fflp_bmc_rd1_data3; | |
| 273 | ||
| 274 | bit [127:0] obs_fflp_bmc_rd2_data0; | |
| 275 | bit [127:0] obs_fflp_bmc_rd2_data1; | |
| 276 | bit [127:0] obs_fflp_bmc_rd2_data2; | |
| 277 | bit [127:0] obs_fflp_bmc_rd2_data3; | |
| 278 | ||
| 279 | bit [127:0] obs_fflp_bmc_wr1_data; | |
| 280 | bit [127:0] obs_fflp_bmc_wr2_data; | |
| 281 | ||
| 282 | bit valid_qp_num; | |
| 283 | bit [7:0] lb_tbl_qp_num; | |
| 284 | bit [6:0] lb_tbl_init_weight; | |
| 285 | bit [3:0] next_lb_tbl_qp_ptr; | |
| 286 | bit [11:0] next_lb_tbl_bank_ptr; | |
| 287 | ||
| 288 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 289 | //@ FFLP_RTL related parameters @ | |
| 290 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ | |
| 291 | bit lb_fifo_full_pulse = 1'b0; | |
| 292 | // | |
| 293 | // Initialize all variables to zero | |
| 294 | task new() { | |
| 295 | integer n; | |
| 296 | ||
| 297 | expected_fwd_dec = new; | |
| 298 | collected_fwd_dec = new; | |
| 299 | /* | |
| 300 | pkt_hdrs = new; | |
| 301 | fflp_fwd_dec = new; | |
| 302 | usr_def_results = new; | |
| 303 | // | |
| 304 | // The folowiing intailizes the expected results to be X's | |
| 305 | // forwarding decision cycle 1 | |
| 306 | usr_def_results.sa_replace = 1'bx; | |
| 307 | usr_def_results.new_da = 1'bx; | |
| 308 | usr_def_results.header_only = 1'bx; | |
| 309 | usr_def_results.dist_flow = 1'bx; | |
| 310 | usr_def_results.output_ports_mask = 20'hx_xxxx; | |
| 311 | ||
| 312 | // | |
| 313 | // forwarding decision cycle 2 | |
| 314 | usr_def_results.tagged = 1'bx; | |
| 315 | usr_def_results.use_new_vid = 1'bx; | |
| 316 | usr_def_results.ttl_offset = 1'bx; | |
| 317 | usr_def_results.priority = 2'bxx; | |
| 318 | usr_def_results.force_beq = 19'hx_xxxx; | |
| 319 | ||
| 320 | // | |
| 321 | // forwarding decision cycle 3 | |
| 322 | usr_def_results.new_priority = 3'bxxx; | |
| 323 | usr_def_results.cfi = 1'bx; | |
| 324 | usr_def_results.new_vid = 12'hxxx; | |
| 325 | usr_def_results.mirror = 1'bx; | |
| 326 | usr_def_results.dont_lb = 1'bx; | |
| 327 | usr_def_results.nat_addr = 1'bx; | |
| 328 | usr_def_results.nat_port = 1'bx; | |
| 329 | usr_def_results.prot_eq_tcp = 1'bx; | |
| 330 | usr_def_results.prot_eq_udp = 1'bx; | |
| 331 | usr_def_results.not_used = 1'bx; | |
| 332 | usr_def_results.flow_matched = 1'bx; | |
| 333 | ||
| 334 | ||
| 335 | // | |
| 336 | // forwarding decision cycle 4 | |
| 337 | usr_def_results.not_used_4 = 8'hxx; | |
| 338 | usr_def_results.tcp_udp_port_num = 16'hxx_xxxx; | |
| 339 | */ | |
| 340 | // | |
| 341 | // The folowiing intailizes the expected results to be X's | |
| 342 | expected_fwd_dec.multicast = 1'b0; // fwd_dec_c1[0] | |
| 343 | expected_fwd_dec.l2_option = 3'b000; // fwd_dec_c1[3:1] | |
| 344 | expected_fwd_dec.l3_version = 2'b00; // fwd_dec_c1[5:4] | |
| 345 | expected_fwd_dec.l4_protocol = 2'b00; // fwd_dec_c1[7:6] | |
| 346 | expected_fwd_dec.tcp_hdr_len = 4'b0000; // fwd_dec_c1[11:8] | |
| 347 | expected_fwd_dec.push_bit = 1'b0; // fwd_dec_c1[12] | |
| 348 | expected_fwd_dec.seq_num = 32'h0000_0000; // {fwd_dec_c2[18:0],fwd_dec_c1[25:13]} | |
| 349 | expected_fwd_dec.translation_table_index = 16'h0000; // {fwd_dec_c2[25:19],fwd_dec_c3[25:17]} | |
| 350 | expected_fwd_dec.drop_pkt = 1'b0; // fwd_dec_c3[0] | |
| 351 | expected_fwd_dec.pkt_dest = 2'b00; // fwd_dec_c3[2:1] | |
| 352 | expected_fwd_dec.pkt_mode = 2'b00; // fwd_dec_c3[4:3] | |
| 353 | expected_fwd_dec.def_vlan_en = 1'b0; // fwd_dec_c3[6] | |
| 354 | expected_fwd_dec.vlan_table_match = 1'b0; // fwd_dec_c3[5] | |
| 355 | expected_fwd_dec.qp_num = 8'h00; // fwd_dec_c3[15:8] | |
| 356 | expected_fwd_dec.cam_match = 1'b0; // fwd_dec_c3[16] | |
| 357 | // | |
| 358 | // The folowiing intailizes the collected results to be X's | |
| 359 | collected_fwd_dec.multicast = 1'b0; // fwd_dec_c1[0] | |
| 360 | collected_fwd_dec.l2_option = 3'b000; // fwd_dec_c1[3:1] | |
| 361 | collected_fwd_dec.l3_version = 2'b00; // fwd_dec_c1[5:4] | |
| 362 | collected_fwd_dec.l4_protocol = 2'b00; // fwd_dec_c1[7:6] | |
| 363 | collected_fwd_dec.tcp_hdr_len = 4'b0000; // fwd_dec_c1[11:8] | |
| 364 | collected_fwd_dec.push_bit = 1'b0; // fwd_dec_c1[12] | |
| 365 | collected_fwd_dec.seq_num = 32'h0000_0000; // {fwd_dec_c2[18:0],fwd_dec_c1[25:13]} | |
| 366 | collected_fwd_dec.translation_table_index = 16'h0000; // {fwd_dec_c2[25:19],fwd_dec_c3[25:17]} | |
| 367 | collected_fwd_dec.drop_pkt = 1'b0; // fwd_dec_c3[0] | |
| 368 | collected_fwd_dec.pkt_dest = 2'b00; // fwd_dec_c3[2:1] | |
| 369 | collected_fwd_dec.pkt_mode = 2'b00; // fwd_dec_c3[4:3] | |
| 370 | collected_fwd_dec.def_vlan_en = 1'b0; // fwd_dec_c3[6] | |
| 371 | collected_fwd_dec.vlan_table_match = 1'b0; // fwd_dec_c3[5] | |
| 372 | collected_fwd_dec.qp_num = 8'h00; // fwd_dec_c3[15:8] | |
| 373 | collected_fwd_dec.cam_match = 1'b0; // fwd_dec_c3[16] | |
| 374 | ||
| 375 | } // end of task new | |
| 376 | ||
| 377 | } // end of class fflp_db |