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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / vera / niu_randoms / rand_packet.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: rand_packet.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "pcg_defines.vri"
37#include "rand_defines.vri"
38
39class rx_rand_dma_parameters {
40 integer blk_size_max = 4;
41 rand integer blk_size = 4;
42 rand integer buf_siz0 = 256;
43 rand integer buf_siz1 = 1024;
44 rand integer buf_siz2 = 2048;
45 rand bit[15:0] desc_ring_length = 16'hfff;
46 rand bit[15:0] comp_ring_length = 16'hfff;
47 rand bit[15:0] initial_kick;
48 bit[15:0] cring_min, cring_max;
49 bit[15:0] dring_min, dring_max;
50 integer initial_kick_min, initial_kick_max;
51
52 default constraint DEF {
53 blk_size == 4;
54 buf_siz0 == 256;
55 buf_siz1 == 1024;
56 buf_siz2 == 2048;
57 }
58 constraint comp_ring_length_limit {
59 comp_ring_length <= cring_max;
60 comp_ring_length >= cring_min;
61 comp_ring_length == (comp_ring_length/64)*64; //multiple of 64 for now - cache line length
62 }
63 constraint desc_ring_length_limit {
64 desc_ring_length <= dring_max;
65 desc_ring_length >= dring_min;
66 desc_ring_length == (desc_ring_length/64)*64; //multiple of 64 for now - cache line length
67 }
68 constraint initial_kick_limit {
69 initial_kick >= initial_kick_min;
70 initial_kick < initial_kick_max;
71 initial_kick < desc_ring_length;
72 initial_kick == (initial_kick/16)*16;
73 //initial_kick == (initial_kick/64)*64; //multiple of 64 for now - cache line length
74 }
75//valid block sizes: 4, 8, 16, 32
76//valid size0: 256, 512, 1024, 2048
77//valid size1: 1024, 2048, 4096, 8192
78//valis size2: 2048, 4096, 8192, 16384
79
80 constraint con{
81 buf_siz0 dist {
82 256 :/40,
83 512 :/30,
84 1024 :/20,
85 2048 :/10
86 };
87 buf_siz1 dist {
88 1024 :/25,
89 2048 :/25,
90 4096 :/25,
91 8192 :/25
92 };
93 buf_siz2 dist {
94 2048 :/25,
95 4096 :/25,
96 8192 :/25,
97 16384 :/25
98 };
99 blk_size dist {
100 4 :/25,
101 8 :/25,
102 16 :/25,
103 32 :/25
104 };
105 blk_size <= blk_size_max;
106 buf_siz1 > buf_siz0;
107 buf_siz2 > buf_siz1;
108 blk_size >= buf_siz2/1024;
109 }
110
111 task new() {
112 if(get_plus_arg (CHECK, "CRING_MAX")) {
113 cring_max=get_plus_arg (NUM, "CRING_MAX");
114 if(cring_max>12'hfff) cring_max='hfff;
115 }
116 else cring_max=16'hfff;
117 if(get_plus_arg (CHECK, "CRING_MIN")) cring_min=get_plus_arg (NUM, "CRING_MIN");
118 else cring_min=16'h300;
119 printf("TEST Cring_min=0x%0h Cring_max=0x%0h\n", cring_min, cring_max);
120
121 if(get_plus_arg (CHECK, "DRING_MAX")) dring_max=get_plus_arg (NUM, "DRING_MAX");
122 else dring_max=16'h1fff;
123 if(get_plus_arg (CHECK, "DRING_MIN")) dring_min=get_plus_arg (NUM, "DRING_MIN");
124 else dring_min=16'h200;
125 printf("TEST Dring_min=0x%0h Dring_max=0x%0h\n", dring_min, dring_max);
126
127 if(get_plus_arg (CHECK, "INITIAL_KICK_MAX")) initial_kick_max=get_plus_arg (NUM, "INITIAL_KICK_MAX");
128 else initial_kick_max='h100;
129 if(get_plus_arg (CHECK, "INITIAL_KICK_MIN")) initial_kick_min=get_plus_arg (NUM, "INITIAL_KICK_MIN");
130 else initial_kick_min='hc0;
131 printf("TEST initial_kick_min=0x%0h initial_kick_max=0x%0h\n", initial_kick_min, initial_kick_max);
132
133 if(get_plus_arg (CHECK, "BLK_SIZE_MAX")) blk_size_max=get_plus_arg (NUM, "BLK_SIZE_MAX");
134 else blk_size_max=4;
135 printf("TEST blk_size_max=%0d\n", blk_size_max);
136 }
137}
138/////////////////////////////////////////
139class rand_packet {
140 rand bit[47:0] xmac_l2_dest_addr;
141 rand bit[47:0] bmac_l2_dest_addr;
142 rand bit[47:0] l2_src_addr = 48'hdef0_7294_3815;
143 rand bit[19:0] node_src_port = 20'h00001;
144 rand integer rx_frame_class_funct = CLF_SRC;
145 rand integer rx_frame_data_type = DAT_SEQ;
146 rand bit[31:0] rx_param_rcv_isn = 32'hA5A5_F5F5;
147 rand bit[5:0] rx_tcp_flags = 6'b00_0010;
148 integer send_pause=0;
149 integer xmac_addr_weight=6;
150 integer bmac_addr_weight=12;
151
152 constraint xmac_l2_dest_addr_dist {
153 xmac_l2_dest_addr dist {
154 xmac_l2_dest_addr0 :/6,
155 xmac_l2_dest_addr1 :/6,
156 xmac_l2_dest_addr2 :/6,
157 xmac_l2_dest_addr3 :/6,
158 xmac_l2_dest_addr4 :/6,
159 xmac_l2_dest_addr5 :/6,
160 xmac_l2_dest_addr6 :/6,
161 xmac_l2_dest_addr7 :/6,
162 xmac_l2_dest_addr8 :/6,
163 xmac_l2_dest_addr9 :/6,
164 xmac_l2_dest_addr10 :/6,
165 xmac_l2_dest_addr11 :/6,
166 xmac_l2_dest_addr12 :/6,
167 xmac_l2_dest_addr13 :/6,
168 xmac_l2_dest_addr14 :/6,
169 xmac_l2_dest_addr15 :/xmac_addr_weight
170 };
171 }
172 constraint bmac_l2_dest_addr_dist {
173 bmac_l2_dest_addr dist {
174 bmac_l2_dest_addr0 :/12,
175 bmac_l2_dest_addr1 :/12,
176 bmac_l2_dest_addr2 :/12,
177 bmac_l2_dest_addr3 :/12,
178 bmac_l2_dest_addr4 :/12,
179 bmac_l2_dest_addr5 :/12,
180 bmac_l2_dest_addr6 :/12,
181 bmac_l2_dest_addr7 :/bmac_addr_weight
182 };
183 }
184 constraint l2_src_addr_dist {
185 l2_src_addr dist {
186 l2_src_addr0 :/12,
187 l2_src_addr1 :/12,
188 l2_src_addr2 :/12,
189 l2_src_addr3 :/12,
190 l2_src_addr4 :/12,
191 l2_src_addr5 :/12,
192 l2_src_addr6 :/12,
193 l2_src_addr7 :/12
194 };
195 }
196 constraint rx_frame_class_funct_dist {
197 rx_frame_class_funct dist {
198 rx_frame_class_funct_0 :/25,
199 rx_frame_class_funct_1 :/25,
200 rx_frame_class_funct_2 :/25,
201 rx_frame_class_funct_3 :/25
202 };
203 }
204 constraint rx_frame_data_type_dist {
205 rx_frame_data_type dist {
206 DAT_SEQ :/20,
207 DAT_RAND :/20,
208 DAT_W1 :/20,
209 DAT_W0 :/20,
210 //DAT_ALL1 :/20,
211 DAT_ALL0 :/20
212 };
213 }
214 constraint rx_tcp_flags_dist {
215 rx_tcp_flags dist {
216 rx_tcp_flags_0 :/50,
217 rx_tcp_flags_1 :/10,
218 rx_tcp_flags_2 :/10,
219 rx_tcp_flags_3 :/10,
220 rx_tcp_flags_4 :/10,
221 rx_tcp_flags_5 :/10
222 };
223 }
224
225////////////////////
226 task new() {
227 if(get_plus_arg(CHECK, "SEND_PAUSE")) send_pause=get_plus_arg (NUM, "SEND_PAUSE");
228 else send_pause=0;
229 printf("TEST send_pause=%0d\n", send_pause);
230
231 if(send_pause!==0) {
232 xmac_addr_weight=0;
233 bmac_addr_weight=0;
234 }
235 printf("TEST xmac_addr_weight=%0d bmac_addr_weight=%0d\n", xmac_addr_weight, bmac_addr_weight);
236 }
237}
Full OpenSPARC design & verification tarball including full HDL.