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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: axis_trap_core.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef CORE_0 | |
36 | ||
37 | module axis_trap_core0 ( | |
38 | cid, | |
39 | pc_dmp_sz, | |
40 | ); | |
41 | ||
42 | input [2:0] cid; | |
43 | input [21:0] pc_dmp_sz; | |
44 | ||
45 | `ifdef AXIS_TL | |
46 | `ifndef GATESIM | |
47 | reg [47:0] pc_0_e; | |
48 | reg [47:0] pc_1_e; | |
49 | reg [47:0] pc_0_m; | |
50 | reg [47:0] pc_1_m; | |
51 | reg [47:0] pc_0_b; | |
52 | reg [47:0] pc_1_b; | |
53 | reg [47:0] pc_0_w; | |
54 | reg [47:0] pc_1_w; | |
55 | reg [47:0] pc_2_w; | |
56 | reg [47:0] pc_3_w; | |
57 | reg [47:0] pc_4_w; | |
58 | reg [47:0] pc_5_w; | |
59 | reg [47:0] pc_6_w; | |
60 | reg [47:0] pc_7_w; | |
61 | `endif | |
62 | ||
63 | //---------------------------------------------------------- | |
64 | reg [63:0] cycle; | |
65 | initial cycle = 64'b0; | |
66 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
67 | if (`CPU.tcu_aclk) cycle = 0; | |
68 | else cycle = cycle + 64'b1; | |
69 | end | |
70 | ||
71 | //*******************************************************************************************************/ | |
72 | reg [76:0] sig_reg_0; | |
73 | reg [76:0] sig_reg_1; | |
74 | reg [76:0] sig_reg_2; | |
75 | reg [76:0] sig_reg_3; | |
76 | reg [63:0] kern_cnt; | |
77 | reg [47:0] pc_0_saved; | |
78 | ||
79 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
80 | always @(negedge `CPU.tcu_aclk) begin | |
81 | begin // axis tbcall_region | |
82 | $display("%t: dbg rst detected by repeatability_check", $time); | |
83 | end | |
84 | end | |
85 | ||
86 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
87 | pc_0_saved <= pc_0_w; | |
88 | if (`CPU.tcu_aclk) begin | |
89 | sig_reg_1 <= 0; | |
90 | sig_reg_2 <= 0; | |
91 | sig_reg_3 <= 0; | |
92 | sig_reg_0 <= 0; | |
93 | kern_cnt <= 0; | |
94 | end | |
95 | else if (!`CPU.tcu_aclk) begin | |
96 | if (tb_top.cpu.spc0.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc0.exu0.irf.wr_addr_p0,tb_top.cpu.spc0.exu0.irf.wr_data_p0}; | |
97 | if (tb_top.cpu.spc0.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc0.exu0.irf.wr_addr_p1,tb_top.cpu.spc0.exu0.irf.wr_data_p1}; | |
98 | if (tb_top.cpu.spc0.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc0.exu1.irf.wr_addr_p0,tb_top.cpu.spc0.exu1.irf.wr_data_p0}; | |
99 | if (tb_top.cpu.spc0.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc0.exu1.irf.wr_addr_p1,tb_top.cpu.spc0.exu1.irf.wr_data_p1}; | |
100 | kern_cnt <= kern_cnt + 1; | |
101 | end | |
102 | ||
103 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
104 | $display("%t: repeatability_check: core 0, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
105 | end | |
106 | ||
107 | end | |
108 | ||
109 | //************************************************************************************************** | |
110 | //---------------------------------------------------------- | |
111 | ||
112 | //---------------------------------------------------------- | |
113 | // | |
114 | // THREAD 0 | |
115 | // | |
116 | ||
117 | ||
118 | axis_trap_pipe0 t0 ( | |
119 | .mycid (cid), | |
120 | .mytid (3'h0), | |
121 | .PC_reg (pc_0_w) | |
122 | ); | |
123 | ||
124 | wire [2:0] thread0_id=3'h0; | |
125 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c0.t0.pc_fw2},`CPU.l2clk,3'h0,0); | |
126 | dbuff_pc dbuff_pc_t0 ( | |
127 | .cycle (cycle[63:0]), | |
128 | .pc (`TOP.axis_trap_top.c0.t0.pc_fw2), | |
129 | .clk (`CPU.l2clk), | |
130 | .core (cid), | |
131 | .thread (thread0_id) | |
132 | ); | |
133 | ||
134 | always @(posedge axis_top.start_dumps) | |
135 | begin // axis tbcall_region | |
136 | $display("DMP0_0: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t0.addr,tb_top.axis_trap_top.c0.dbuff_pc_t0.ptr_0_cycle); | |
137 | $axis_dumpmemh("c0_t0_pctrc.dat", | |
138 | tb_top.axis_trap_top.c0.dbuff_pc_t0.DBUFF); | |
139 | end | |
140 | ||
141 | ||
142 | //---------------------------------------------------------- | |
143 | // | |
144 | // THREAD 1 | |
145 | // | |
146 | ||
147 | ||
148 | axis_trap_pipe0 t1 ( | |
149 | .mycid (cid), | |
150 | .mytid (3'h1), | |
151 | .PC_reg (pc_1_w) | |
152 | ); | |
153 | ||
154 | wire [2:0] thread1_id=3'h1; | |
155 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c0.t1.pc_fw2},`CPU.l2clk,3'h1,0); | |
156 | dbuff_pc dbuff_pc_t1 ( | |
157 | .cycle (cycle[63:0]), | |
158 | .pc (`TOP.axis_trap_top.c0.t1.pc_fw2), | |
159 | .clk (`CPU.l2clk), | |
160 | .core (cid), | |
161 | .thread (thread1_id) | |
162 | ); | |
163 | ||
164 | always @(posedge axis_top.start_dumps) | |
165 | begin // axis tbcall_region | |
166 | $display("DMP0_1: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t1.addr,tb_top.axis_trap_top.c0.dbuff_pc_t1.ptr_0_cycle); | |
167 | $axis_dumpmemh("c0_t1_pctrc.dat", | |
168 | tb_top.axis_trap_top.c0.dbuff_pc_t1.DBUFF); | |
169 | end | |
170 | ||
171 | ||
172 | //---------------------------------------------------------- | |
173 | // | |
174 | // THREAD 2 | |
175 | // | |
176 | ||
177 | ||
178 | axis_trap_pipe0 t2 ( | |
179 | .mycid (cid), | |
180 | .mytid (3'h2), | |
181 | .PC_reg (pc_2_w) | |
182 | ); | |
183 | ||
184 | wire [2:0] thread2_id=3'h2; | |
185 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c0.t2.pc_fw2},`CPU.l2clk,3'h2,0); | |
186 | dbuff_pc dbuff_pc_t2 ( | |
187 | .cycle (cycle[63:0]), | |
188 | .pc (`TOP.axis_trap_top.c0.t2.pc_fw2), | |
189 | .clk (`CPU.l2clk), | |
190 | .core (cid), | |
191 | .thread (thread2_id) | |
192 | ); | |
193 | ||
194 | always @(posedge axis_top.start_dumps) | |
195 | begin // axis tbcall_region | |
196 | $display("DMP0_2: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t2.addr,tb_top.axis_trap_top.c0.dbuff_pc_t2.ptr_0_cycle); | |
197 | $axis_dumpmemh("c0_t2_pctrc.dat", | |
198 | tb_top.axis_trap_top.c0.dbuff_pc_t2.DBUFF); | |
199 | end | |
200 | ||
201 | ||
202 | //---------------------------------------------------------- | |
203 | // | |
204 | // THREAD 3 | |
205 | // | |
206 | ||
207 | ||
208 | axis_trap_pipe0 t3 ( | |
209 | .mycid (cid), | |
210 | .mytid (3'h3), | |
211 | .PC_reg (pc_3_w) | |
212 | ); | |
213 | ||
214 | wire [2:0] thread3_id=3'h3; | |
215 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c0.t3.pc_fw2},`CPU.l2clk,3'h3,0); | |
216 | dbuff_pc dbuff_pc_t3 ( | |
217 | .cycle (cycle[63:0]), | |
218 | .pc (`TOP.axis_trap_top.c0.t3.pc_fw2), | |
219 | .clk (`CPU.l2clk), | |
220 | .core (cid), | |
221 | .thread (thread3_id) | |
222 | ); | |
223 | ||
224 | always @(posedge axis_top.start_dumps) | |
225 | begin // axis tbcall_region | |
226 | $display("DMP0_3: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t3.addr,tb_top.axis_trap_top.c0.dbuff_pc_t3.ptr_0_cycle); | |
227 | $axis_dumpmemh("c0_t3_pctrc.dat", | |
228 | tb_top.axis_trap_top.c0.dbuff_pc_t3.DBUFF); | |
229 | end | |
230 | ||
231 | ||
232 | reg [5:0] trl0_tsa_wr_addr_r; | |
233 | reg [1:0] tsd0_wr_gl_r; | |
234 | reg [8:0] tsd0_wr_trap_type_r; | |
235 | reg [47:2] tsd0_wr_tpc_r; | |
236 | reg trl0_tsa_wr_en_r; | |
237 | always @(posedge `CPU.l2clk) begin | |
238 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc0.tlu.trl0_tsa_wr_addr; | |
239 | tsd0_wr_gl_r <= tb_top.cpu.spc0.tlu.tsd0_wr_gl; | |
240 | tsd0_wr_trap_type_r <= tb_top.cpu.spc0.tlu.tsd0_wr_trap_type[8:0]; | |
241 | tsd0_wr_tpc_r <= tb_top.cpu.spc0.tlu.tsd0_wr_tpc; | |
242 | trl0_tsa_wr_en_r <= tb_top.cpu.spc0.tlu.trl_tsa_wr_en[0]; | |
243 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
244 | begin // axis tbcall_region | |
245 | $display("%t: TRAP WRITE: CORE 0: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
246 | end | |
247 | end | |
248 | end | |
249 | ||
250 | //---------------------------------------------------------- | |
251 | // | |
252 | // THREAD 4 | |
253 | // | |
254 | ||
255 | ||
256 | axis_trap_pipe0 t4 ( | |
257 | .mycid (cid), | |
258 | .mytid (3'h4), | |
259 | .PC_reg (pc_4_w) | |
260 | ); | |
261 | ||
262 | wire [2:0] thread4_id=3'h4; | |
263 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c0.t4.pc_fw2},`CPU.l2clk,3'h4,0); | |
264 | dbuff_pc dbuff_pc_t4 ( | |
265 | .cycle (cycle[63:0]), | |
266 | .pc (`TOP.axis_trap_top.c0.t4.pc_fw2), | |
267 | .clk (`CPU.l2clk), | |
268 | .core (cid), | |
269 | .thread (thread4_id) | |
270 | ); | |
271 | ||
272 | always @(posedge axis_top.start_dumps) | |
273 | begin // axis tbcall_region | |
274 | $display("DMP0_4: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t4.addr,tb_top.axis_trap_top.c0.dbuff_pc_t4.ptr_0_cycle); | |
275 | $axis_dumpmemh("c0_t4_pctrc.dat", | |
276 | tb_top.axis_trap_top.c0.dbuff_pc_t4.DBUFF); | |
277 | end | |
278 | ||
279 | ||
280 | //---------------------------------------------------------- | |
281 | // | |
282 | // THREAD 5 | |
283 | // | |
284 | ||
285 | ||
286 | axis_trap_pipe0 t5 ( | |
287 | .mycid (cid), | |
288 | .mytid (3'h5), | |
289 | .PC_reg (pc_5_w) | |
290 | ); | |
291 | ||
292 | wire [2:0] thread5_id=3'h5; | |
293 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c0.t5.pc_fw2},`CPU.l2clk,3'h5,0); | |
294 | dbuff_pc dbuff_pc_t5 ( | |
295 | .cycle (cycle[63:0]), | |
296 | .pc (`TOP.axis_trap_top.c0.t5.pc_fw2), | |
297 | .clk (`CPU.l2clk), | |
298 | .core (cid), | |
299 | .thread (thread5_id) | |
300 | ); | |
301 | ||
302 | always @(posedge axis_top.start_dumps) | |
303 | begin // axis tbcall_region | |
304 | $display("DMP0_5: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t5.addr,tb_top.axis_trap_top.c0.dbuff_pc_t5.ptr_0_cycle); | |
305 | $axis_dumpmemh("c0_t5_pctrc.dat", | |
306 | tb_top.axis_trap_top.c0.dbuff_pc_t5.DBUFF); | |
307 | end | |
308 | ||
309 | ||
310 | //---------------------------------------------------------- | |
311 | // | |
312 | // THREAD 6 | |
313 | // | |
314 | ||
315 | ||
316 | axis_trap_pipe0 t6 ( | |
317 | .mycid (cid), | |
318 | .mytid (3'h6), | |
319 | .PC_reg (pc_6_w) | |
320 | ); | |
321 | ||
322 | wire [2:0] thread6_id=3'h6; | |
323 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c0.t6.pc_fw2},`CPU.l2clk,3'h6,0); | |
324 | dbuff_pc dbuff_pc_t6 ( | |
325 | .cycle (cycle[63:0]), | |
326 | .pc (`TOP.axis_trap_top.c0.t6.pc_fw2), | |
327 | .clk (`CPU.l2clk), | |
328 | .core (cid), | |
329 | .thread (thread6_id) | |
330 | ); | |
331 | ||
332 | always @(posedge axis_top.start_dumps) | |
333 | begin // axis tbcall_region | |
334 | $display("DMP0_6: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t6.addr,tb_top.axis_trap_top.c0.dbuff_pc_t6.ptr_0_cycle); | |
335 | $axis_dumpmemh("c0_t6_pctrc.dat", | |
336 | tb_top.axis_trap_top.c0.dbuff_pc_t6.DBUFF); | |
337 | end | |
338 | ||
339 | ||
340 | //---------------------------------------------------------- | |
341 | // | |
342 | // THREAD 7 | |
343 | // | |
344 | ||
345 | ||
346 | axis_trap_pipe0 t7 ( | |
347 | .mycid (cid), | |
348 | .mytid (3'h7), | |
349 | .PC_reg (pc_7_w) | |
350 | ); | |
351 | ||
352 | wire [2:0] thread7_id=3'h7; | |
353 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c0.t7.pc_fw2},`CPU.l2clk,3'h7,0); | |
354 | dbuff_pc dbuff_pc_t7 ( | |
355 | .cycle (cycle[63:0]), | |
356 | .pc (`TOP.axis_trap_top.c0.t7.pc_fw2), | |
357 | .clk (`CPU.l2clk), | |
358 | .core (cid), | |
359 | .thread (thread7_id) | |
360 | ); | |
361 | ||
362 | always @(posedge axis_top.start_dumps) | |
363 | begin // axis tbcall_region | |
364 | $display("DMP0_7: %h %h \n",tb_top.axis_trap_top.c0.dbuff_pc_t7.addr,tb_top.axis_trap_top.c0.dbuff_pc_t7.ptr_0_cycle); | |
365 | $axis_dumpmemh("c0_t7_pctrc.dat", | |
366 | tb_top.axis_trap_top.c0.dbuff_pc_t7.DBUFF); | |
367 | end | |
368 | ||
369 | ||
370 | reg [5:0] trl1_tsa_wr_addr_r; | |
371 | reg [1:0] tsd1_wr_gl_r; | |
372 | reg [8:0] tsd1_wr_trap_type_r; | |
373 | reg [47:2] tsd1_wr_tpc_r; | |
374 | reg trl1_tsa_wr_en_r; | |
375 | always @(posedge `CPU.l2clk) begin | |
376 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc0.tlu.trl1_tsa_wr_addr; | |
377 | tsd1_wr_gl_r <= tb_top.cpu.spc0.tlu.tsd1_wr_gl; | |
378 | tsd1_wr_trap_type_r <= tb_top.cpu.spc0.tlu.tsd1_wr_trap_type[8:0]; | |
379 | tsd1_wr_tpc_r <= tb_top.cpu.spc0.tlu.tsd1_wr_tpc; | |
380 | trl1_tsa_wr_en_r <= tb_top.cpu.spc0.tlu.trl_tsa_wr_en[1]; | |
381 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
382 | begin // axis tbcall_region | |
383 | $display("%t: TRAP WRITE: CORE 0: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
384 | end | |
385 | end | |
386 | end | |
387 | ||
388 | //---------------------------------------------------------- | |
389 | ||
390 | `ifndef GATESIM | |
391 | ||
392 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
393 | // But some of the error checkers need this signal without the qualification | |
394 | // of icache errors | |
395 | wire [7:0] select_pc_b_with_errors; | |
396 | ||
397 | assign select_pc_b_with_errors = | |
398 | {{4 {~`SPC0.dec_flush_b[1]}}, {4 {~`SPC0.dec_flush_b[0]}}} & | |
399 | ||
400 | {~(`SPC0.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
401 | {4 {`SPC0.tlu.fls1.idl_req_in}}), | |
402 | ~(`SPC0.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
403 | {4 {`SPC0.tlu.fls0.idl_req_in}})} & | |
404 | {`SPC0.tlu.fls1.tid_dec_valid_b[3:0], | |
405 | `SPC0.tlu.fls0.tid_dec_valid_b[3:0]}; | |
406 | ||
407 | //------------------------------------ | |
408 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
409 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
410 | wire [7:0] select_pc_b; | |
411 | ||
412 | assign select_pc_b = | |
413 | select_pc_b_with_errors[7:0] & | |
414 | {{4 {~`SPC0.tlu.fls1.ic_err_w_in}}, {4 {~`SPC0.tlu.fls0.ic_err_w_in}}}; | |
415 | ||
416 | //------------------------------------ | |
417 | // ASI & Trap State machines | |
418 | always @(posedge `SPC0.gclk) begin // { | |
419 | ||
420 | // pc_0_e[47:0] <= `SPC0.ifu_pc_d0[47:0]; | |
421 | // pc_1_e[47:0] <= `SPC0.ifu_pc_d1[47:0]; | |
422 | pc_0_e[47:0] <= {`SPC0.tlu_pc_0_d[47:2], 2'b00}; | |
423 | pc_1_e[47:0] <= {`SPC0.tlu_pc_1_d[47:2], 2'b00}; | |
424 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
425 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
426 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
427 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
428 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
429 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
430 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
431 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
432 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
433 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
434 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
435 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
436 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
437 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
438 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
439 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
440 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
441 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
442 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
443 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
444 | end | |
445 | ||
446 | `endif | |
447 | `endif //AXIS_TL | |
448 | ||
449 | //---------------------------------------------------------- | |
450 | endmodule | |
451 | ||
452 | `endif | |
453 | ||
454 | `ifdef CORE_1 | |
455 | ||
456 | module axis_trap_core1 ( | |
457 | cid, | |
458 | pc_dmp_sz, | |
459 | ); | |
460 | ||
461 | input [2:0] cid; | |
462 | input [21:0] pc_dmp_sz; | |
463 | ||
464 | `ifdef AXIS_TL | |
465 | `ifndef GATESIM | |
466 | reg [47:0] pc_0_e; | |
467 | reg [47:0] pc_1_e; | |
468 | reg [47:0] pc_0_m; | |
469 | reg [47:0] pc_1_m; | |
470 | reg [47:0] pc_0_b; | |
471 | reg [47:0] pc_1_b; | |
472 | reg [47:0] pc_0_w; | |
473 | reg [47:0] pc_1_w; | |
474 | reg [47:0] pc_2_w; | |
475 | reg [47:0] pc_3_w; | |
476 | reg [47:0] pc_4_w; | |
477 | reg [47:0] pc_5_w; | |
478 | reg [47:0] pc_6_w; | |
479 | reg [47:0] pc_7_w; | |
480 | `endif | |
481 | ||
482 | //---------------------------------------------------------- | |
483 | reg [63:0] cycle; | |
484 | initial cycle = 64'b0; | |
485 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
486 | if (`CPU.tcu_aclk) cycle = 0; | |
487 | else cycle = cycle + 64'b1; | |
488 | end | |
489 | ||
490 | //*******************************************************************************************************/ | |
491 | reg [76:0] sig_reg_0; | |
492 | reg [76:0] sig_reg_1; | |
493 | reg [76:0] sig_reg_2; | |
494 | reg [76:0] sig_reg_3; | |
495 | reg [63:0] kern_cnt; | |
496 | reg [47:0] pc_0_saved; | |
497 | ||
498 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
499 | always @(negedge `CPU.tcu_aclk) begin | |
500 | begin // axis tbcall_region | |
501 | $display("%t: dbg rst detected by repeatability_check", $time); | |
502 | end | |
503 | end | |
504 | ||
505 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
506 | pc_0_saved <= pc_0_w; | |
507 | if (`CPU.tcu_aclk) begin | |
508 | sig_reg_1 <= 0; | |
509 | sig_reg_2 <= 0; | |
510 | sig_reg_3 <= 0; | |
511 | sig_reg_0 <= 0; | |
512 | kern_cnt <= 0; | |
513 | end | |
514 | else if (!`CPU.tcu_aclk) begin | |
515 | if (tb_top.cpu.spc1.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc1.exu0.irf.wr_addr_p0,tb_top.cpu.spc1.exu0.irf.wr_data_p0}; | |
516 | if (tb_top.cpu.spc1.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc1.exu0.irf.wr_addr_p1,tb_top.cpu.spc1.exu0.irf.wr_data_p1}; | |
517 | if (tb_top.cpu.spc1.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc1.exu1.irf.wr_addr_p0,tb_top.cpu.spc1.exu1.irf.wr_data_p0}; | |
518 | if (tb_top.cpu.spc1.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc1.exu1.irf.wr_addr_p1,tb_top.cpu.spc1.exu1.irf.wr_data_p1}; | |
519 | kern_cnt <= kern_cnt + 1; | |
520 | end | |
521 | ||
522 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
523 | $display("%t: repeatability_check: core 1, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
524 | end | |
525 | ||
526 | end | |
527 | ||
528 | //************************************************************************************************** | |
529 | //---------------------------------------------------------- | |
530 | ||
531 | //---------------------------------------------------------- | |
532 | // | |
533 | // THREAD 0 | |
534 | // | |
535 | ||
536 | ||
537 | axis_trap_pipe1 t0 ( | |
538 | .mycid (cid), | |
539 | .mytid (3'h0), | |
540 | .PC_reg (pc_0_w) | |
541 | ); | |
542 | ||
543 | wire [2:0] thread0_id=3'h0; | |
544 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c1.t0.pc_fw2},`CPU.l2clk,3'h0,1); | |
545 | dbuff_pc dbuff_pc_t0 ( | |
546 | .cycle (cycle[63:0]), | |
547 | .pc (`TOP.axis_trap_top.c1.t0.pc_fw2), | |
548 | .clk (`CPU.l2clk), | |
549 | .core (cid), | |
550 | .thread (thread0_id) | |
551 | ); | |
552 | ||
553 | always @(posedge axis_top.start_dumps) | |
554 | begin // axis tbcall_region | |
555 | $display("DMP1_0: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t0.addr,tb_top.axis_trap_top.c1.dbuff_pc_t0.ptr_0_cycle); | |
556 | $axis_dumpmemh("c1_t0_pctrc.dat", | |
557 | tb_top.axis_trap_top.c1.dbuff_pc_t0.DBUFF); | |
558 | end | |
559 | ||
560 | ||
561 | //---------------------------------------------------------- | |
562 | // | |
563 | // THREAD 1 | |
564 | // | |
565 | ||
566 | ||
567 | axis_trap_pipe1 t1 ( | |
568 | .mycid (cid), | |
569 | .mytid (3'h1), | |
570 | .PC_reg (pc_1_w) | |
571 | ); | |
572 | ||
573 | wire [2:0] thread1_id=3'h1; | |
574 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c1.t1.pc_fw2},`CPU.l2clk,3'h1,1); | |
575 | dbuff_pc dbuff_pc_t1 ( | |
576 | .cycle (cycle[63:0]), | |
577 | .pc (`TOP.axis_trap_top.c1.t1.pc_fw2), | |
578 | .clk (`CPU.l2clk), | |
579 | .core (cid), | |
580 | .thread (thread1_id) | |
581 | ); | |
582 | ||
583 | always @(posedge axis_top.start_dumps) | |
584 | begin // axis tbcall_region | |
585 | $display("DMP1_1: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t1.addr,tb_top.axis_trap_top.c1.dbuff_pc_t1.ptr_0_cycle); | |
586 | $axis_dumpmemh("c1_t1_pctrc.dat", | |
587 | tb_top.axis_trap_top.c1.dbuff_pc_t1.DBUFF); | |
588 | end | |
589 | ||
590 | ||
591 | //---------------------------------------------------------- | |
592 | // | |
593 | // THREAD 2 | |
594 | // | |
595 | ||
596 | ||
597 | axis_trap_pipe1 t2 ( | |
598 | .mycid (cid), | |
599 | .mytid (3'h2), | |
600 | .PC_reg (pc_2_w) | |
601 | ); | |
602 | ||
603 | wire [2:0] thread2_id=3'h2; | |
604 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c1.t2.pc_fw2},`CPU.l2clk,3'h2,1); | |
605 | dbuff_pc dbuff_pc_t2 ( | |
606 | .cycle (cycle[63:0]), | |
607 | .pc (`TOP.axis_trap_top.c1.t2.pc_fw2), | |
608 | .clk (`CPU.l2clk), | |
609 | .core (cid), | |
610 | .thread (thread2_id) | |
611 | ); | |
612 | ||
613 | always @(posedge axis_top.start_dumps) | |
614 | begin // axis tbcall_region | |
615 | $display("DMP1_2: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t2.addr,tb_top.axis_trap_top.c1.dbuff_pc_t2.ptr_0_cycle); | |
616 | $axis_dumpmemh("c1_t2_pctrc.dat", | |
617 | tb_top.axis_trap_top.c1.dbuff_pc_t2.DBUFF); | |
618 | end | |
619 | ||
620 | ||
621 | //---------------------------------------------------------- | |
622 | // | |
623 | // THREAD 3 | |
624 | // | |
625 | ||
626 | ||
627 | axis_trap_pipe1 t3 ( | |
628 | .mycid (cid), | |
629 | .mytid (3'h3), | |
630 | .PC_reg (pc_3_w) | |
631 | ); | |
632 | ||
633 | wire [2:0] thread3_id=3'h3; | |
634 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c1.t3.pc_fw2},`CPU.l2clk,3'h3,1); | |
635 | dbuff_pc dbuff_pc_t3 ( | |
636 | .cycle (cycle[63:0]), | |
637 | .pc (`TOP.axis_trap_top.c1.t3.pc_fw2), | |
638 | .clk (`CPU.l2clk), | |
639 | .core (cid), | |
640 | .thread (thread3_id) | |
641 | ); | |
642 | ||
643 | always @(posedge axis_top.start_dumps) | |
644 | begin // axis tbcall_region | |
645 | $display("DMP1_3: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t3.addr,tb_top.axis_trap_top.c1.dbuff_pc_t3.ptr_0_cycle); | |
646 | $axis_dumpmemh("c1_t3_pctrc.dat", | |
647 | tb_top.axis_trap_top.c1.dbuff_pc_t3.DBUFF); | |
648 | end | |
649 | ||
650 | ||
651 | reg [5:0] trl0_tsa_wr_addr_r; | |
652 | reg [1:0] tsd0_wr_gl_r; | |
653 | reg [8:0] tsd0_wr_trap_type_r; | |
654 | reg [47:2] tsd0_wr_tpc_r; | |
655 | reg trl0_tsa_wr_en_r; | |
656 | always @(posedge `CPU.l2clk) begin | |
657 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc1.tlu.trl0_tsa_wr_addr; | |
658 | tsd0_wr_gl_r <= tb_top.cpu.spc1.tlu.tsd0_wr_gl; | |
659 | tsd0_wr_trap_type_r <= tb_top.cpu.spc1.tlu.tsd0_wr_trap_type[8:0]; | |
660 | tsd0_wr_tpc_r <= tb_top.cpu.spc1.tlu.tsd0_wr_tpc; | |
661 | trl0_tsa_wr_en_r <= tb_top.cpu.spc1.tlu.trl_tsa_wr_en[0]; | |
662 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
663 | begin // axis tbcall_region | |
664 | $display("%t: TRAP WRITE: CORE 1: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
665 | end | |
666 | end | |
667 | end | |
668 | ||
669 | //---------------------------------------------------------- | |
670 | // | |
671 | // THREAD 4 | |
672 | // | |
673 | ||
674 | ||
675 | axis_trap_pipe1 t4 ( | |
676 | .mycid (cid), | |
677 | .mytid (3'h4), | |
678 | .PC_reg (pc_4_w) | |
679 | ); | |
680 | ||
681 | wire [2:0] thread4_id=3'h4; | |
682 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c1.t4.pc_fw2},`CPU.l2clk,3'h4,1); | |
683 | dbuff_pc dbuff_pc_t4 ( | |
684 | .cycle (cycle[63:0]), | |
685 | .pc (`TOP.axis_trap_top.c1.t4.pc_fw2), | |
686 | .clk (`CPU.l2clk), | |
687 | .core (cid), | |
688 | .thread (thread4_id) | |
689 | ); | |
690 | ||
691 | always @(posedge axis_top.start_dumps) | |
692 | begin // axis tbcall_region | |
693 | $display("DMP1_4: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t4.addr,tb_top.axis_trap_top.c1.dbuff_pc_t4.ptr_0_cycle); | |
694 | $axis_dumpmemh("c1_t4_pctrc.dat", | |
695 | tb_top.axis_trap_top.c1.dbuff_pc_t4.DBUFF); | |
696 | end | |
697 | ||
698 | ||
699 | //---------------------------------------------------------- | |
700 | // | |
701 | // THREAD 5 | |
702 | // | |
703 | ||
704 | ||
705 | axis_trap_pipe1 t5 ( | |
706 | .mycid (cid), | |
707 | .mytid (3'h5), | |
708 | .PC_reg (pc_5_w) | |
709 | ); | |
710 | ||
711 | wire [2:0] thread5_id=3'h5; | |
712 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c1.t5.pc_fw2},`CPU.l2clk,3'h5,1); | |
713 | dbuff_pc dbuff_pc_t5 ( | |
714 | .cycle (cycle[63:0]), | |
715 | .pc (`TOP.axis_trap_top.c1.t5.pc_fw2), | |
716 | .clk (`CPU.l2clk), | |
717 | .core (cid), | |
718 | .thread (thread5_id) | |
719 | ); | |
720 | ||
721 | always @(posedge axis_top.start_dumps) | |
722 | begin // axis tbcall_region | |
723 | $display("DMP1_5: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t5.addr,tb_top.axis_trap_top.c1.dbuff_pc_t5.ptr_0_cycle); | |
724 | $axis_dumpmemh("c1_t5_pctrc.dat", | |
725 | tb_top.axis_trap_top.c1.dbuff_pc_t5.DBUFF); | |
726 | end | |
727 | ||
728 | ||
729 | //---------------------------------------------------------- | |
730 | // | |
731 | // THREAD 6 | |
732 | // | |
733 | ||
734 | ||
735 | axis_trap_pipe1 t6 ( | |
736 | .mycid (cid), | |
737 | .mytid (3'h6), | |
738 | .PC_reg (pc_6_w) | |
739 | ); | |
740 | ||
741 | wire [2:0] thread6_id=3'h6; | |
742 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c1.t6.pc_fw2},`CPU.l2clk,3'h6,1); | |
743 | dbuff_pc dbuff_pc_t6 ( | |
744 | .cycle (cycle[63:0]), | |
745 | .pc (`TOP.axis_trap_top.c1.t6.pc_fw2), | |
746 | .clk (`CPU.l2clk), | |
747 | .core (cid), | |
748 | .thread (thread6_id) | |
749 | ); | |
750 | ||
751 | always @(posedge axis_top.start_dumps) | |
752 | begin // axis tbcall_region | |
753 | $display("DMP1_6: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t6.addr,tb_top.axis_trap_top.c1.dbuff_pc_t6.ptr_0_cycle); | |
754 | $axis_dumpmemh("c1_t6_pctrc.dat", | |
755 | tb_top.axis_trap_top.c1.dbuff_pc_t6.DBUFF); | |
756 | end | |
757 | ||
758 | ||
759 | //---------------------------------------------------------- | |
760 | // | |
761 | // THREAD 7 | |
762 | // | |
763 | ||
764 | ||
765 | axis_trap_pipe1 t7 ( | |
766 | .mycid (cid), | |
767 | .mytid (3'h7), | |
768 | .PC_reg (pc_7_w) | |
769 | ); | |
770 | ||
771 | wire [2:0] thread7_id=3'h7; | |
772 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c1.t7.pc_fw2},`CPU.l2clk,3'h7,1); | |
773 | dbuff_pc dbuff_pc_t7 ( | |
774 | .cycle (cycle[63:0]), | |
775 | .pc (`TOP.axis_trap_top.c1.t7.pc_fw2), | |
776 | .clk (`CPU.l2clk), | |
777 | .core (cid), | |
778 | .thread (thread7_id) | |
779 | ); | |
780 | ||
781 | always @(posedge axis_top.start_dumps) | |
782 | begin // axis tbcall_region | |
783 | $display("DMP1_7: %h %h \n",tb_top.axis_trap_top.c1.dbuff_pc_t7.addr,tb_top.axis_trap_top.c1.dbuff_pc_t7.ptr_0_cycle); | |
784 | $axis_dumpmemh("c1_t7_pctrc.dat", | |
785 | tb_top.axis_trap_top.c1.dbuff_pc_t7.DBUFF); | |
786 | end | |
787 | ||
788 | ||
789 | reg [5:0] trl1_tsa_wr_addr_r; | |
790 | reg [1:0] tsd1_wr_gl_r; | |
791 | reg [8:0] tsd1_wr_trap_type_r; | |
792 | reg [47:2] tsd1_wr_tpc_r; | |
793 | reg trl1_tsa_wr_en_r; | |
794 | always @(posedge `CPU.l2clk) begin | |
795 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc1.tlu.trl1_tsa_wr_addr; | |
796 | tsd1_wr_gl_r <= tb_top.cpu.spc1.tlu.tsd1_wr_gl; | |
797 | tsd1_wr_trap_type_r <= tb_top.cpu.spc1.tlu.tsd1_wr_trap_type[8:0]; | |
798 | tsd1_wr_tpc_r <= tb_top.cpu.spc1.tlu.tsd1_wr_tpc; | |
799 | trl1_tsa_wr_en_r <= tb_top.cpu.spc1.tlu.trl_tsa_wr_en[1]; | |
800 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
801 | begin // axis tbcall_region | |
802 | $display("%t: TRAP WRITE: CORE 1: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
803 | end | |
804 | end | |
805 | end | |
806 | ||
807 | //---------------------------------------------------------- | |
808 | ||
809 | `ifndef GATESIM | |
810 | ||
811 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
812 | // But some of the error checkers need this signal without the qualification | |
813 | // of icache errors | |
814 | wire [7:0] select_pc_b_with_errors; | |
815 | ||
816 | assign select_pc_b_with_errors = | |
817 | {{4 {~`SPC1.dec_flush_b[1]}}, {4 {~`SPC1.dec_flush_b[0]}}} & | |
818 | ||
819 | {~(`SPC1.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
820 | {4 {`SPC1.tlu.fls1.idl_req_in}}), | |
821 | ~(`SPC1.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
822 | {4 {`SPC1.tlu.fls0.idl_req_in}})} & | |
823 | {`SPC1.tlu.fls1.tid_dec_valid_b[3:0], | |
824 | `SPC1.tlu.fls0.tid_dec_valid_b[3:0]}; | |
825 | ||
826 | //------------------------------------ | |
827 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
828 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
829 | wire [7:0] select_pc_b; | |
830 | ||
831 | assign select_pc_b = | |
832 | select_pc_b_with_errors[7:0] & | |
833 | {{4 {~`SPC1.tlu.fls1.ic_err_w_in}}, {4 {~`SPC1.tlu.fls0.ic_err_w_in}}}; | |
834 | ||
835 | //------------------------------------ | |
836 | // ASI & Trap State machines | |
837 | always @(posedge `SPC1.gclk) begin // { | |
838 | ||
839 | // pc_0_e[47:0] <= `SPC1.ifu_pc_d0[47:0]; | |
840 | // pc_1_e[47:0] <= `SPC1.ifu_pc_d1[47:0]; | |
841 | pc_0_e[47:0] <= {`SPC1.tlu_pc_0_d[47:2], 2'b00}; | |
842 | pc_1_e[47:0] <= {`SPC1.tlu_pc_1_d[47:2], 2'b00}; | |
843 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
844 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
845 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
846 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
847 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
848 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
849 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
850 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
851 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
852 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
853 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
854 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
855 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
856 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
857 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
858 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
859 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
860 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
861 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
862 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
863 | end | |
864 | ||
865 | `endif | |
866 | `endif //AXIS_TL | |
867 | ||
868 | //---------------------------------------------------------- | |
869 | endmodule | |
870 | ||
871 | `endif | |
872 | ||
873 | `ifdef CORE_2 | |
874 | ||
875 | module axis_trap_core2 ( | |
876 | cid, | |
877 | pc_dmp_sz, | |
878 | ); | |
879 | ||
880 | input [2:0] cid; | |
881 | input [21:0] pc_dmp_sz; | |
882 | ||
883 | `ifdef AXIS_TL | |
884 | `ifndef GATESIM | |
885 | reg [47:0] pc_0_e; | |
886 | reg [47:0] pc_1_e; | |
887 | reg [47:0] pc_0_m; | |
888 | reg [47:0] pc_1_m; | |
889 | reg [47:0] pc_0_b; | |
890 | reg [47:0] pc_1_b; | |
891 | reg [47:0] pc_0_w; | |
892 | reg [47:0] pc_1_w; | |
893 | reg [47:0] pc_2_w; | |
894 | reg [47:0] pc_3_w; | |
895 | reg [47:0] pc_4_w; | |
896 | reg [47:0] pc_5_w; | |
897 | reg [47:0] pc_6_w; | |
898 | reg [47:0] pc_7_w; | |
899 | `endif | |
900 | ||
901 | //---------------------------------------------------------- | |
902 | reg [63:0] cycle; | |
903 | initial cycle = 64'b0; | |
904 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
905 | if (`CPU.tcu_aclk) cycle = 0; | |
906 | else cycle = cycle + 64'b1; | |
907 | end | |
908 | ||
909 | //*******************************************************************************************************/ | |
910 | reg [76:0] sig_reg_0; | |
911 | reg [76:0] sig_reg_1; | |
912 | reg [76:0] sig_reg_2; | |
913 | reg [76:0] sig_reg_3; | |
914 | reg [63:0] kern_cnt; | |
915 | reg [47:0] pc_0_saved; | |
916 | ||
917 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
918 | always @(negedge `CPU.tcu_aclk) begin | |
919 | begin // axis tbcall_region | |
920 | $display("%t: dbg rst detected by repeatability_check", $time); | |
921 | end | |
922 | end | |
923 | ||
924 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
925 | pc_0_saved <= pc_0_w; | |
926 | if (`CPU.tcu_aclk) begin | |
927 | sig_reg_1 <= 0; | |
928 | sig_reg_2 <= 0; | |
929 | sig_reg_3 <= 0; | |
930 | sig_reg_0 <= 0; | |
931 | kern_cnt <= 0; | |
932 | end | |
933 | else if (!`CPU.tcu_aclk) begin | |
934 | if (tb_top.cpu.spc2.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc2.exu0.irf.wr_addr_p0,tb_top.cpu.spc2.exu0.irf.wr_data_p0}; | |
935 | if (tb_top.cpu.spc2.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc2.exu0.irf.wr_addr_p1,tb_top.cpu.spc2.exu0.irf.wr_data_p1}; | |
936 | if (tb_top.cpu.spc2.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc2.exu1.irf.wr_addr_p0,tb_top.cpu.spc2.exu1.irf.wr_data_p0}; | |
937 | if (tb_top.cpu.spc2.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc2.exu1.irf.wr_addr_p1,tb_top.cpu.spc2.exu1.irf.wr_data_p1}; | |
938 | kern_cnt <= kern_cnt + 1; | |
939 | end | |
940 | ||
941 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
942 | $display("%t: repeatability_check: core 2, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
943 | end | |
944 | ||
945 | end | |
946 | ||
947 | //************************************************************************************************** | |
948 | //---------------------------------------------------------- | |
949 | ||
950 | //---------------------------------------------------------- | |
951 | // | |
952 | // THREAD 0 | |
953 | // | |
954 | ||
955 | ||
956 | axis_trap_pipe2 t0 ( | |
957 | .mycid (cid), | |
958 | .mytid (3'h0), | |
959 | .PC_reg (pc_0_w) | |
960 | ); | |
961 | ||
962 | wire [2:0] thread0_id=3'h0; | |
963 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c2.t0.pc_fw2},`CPU.l2clk,3'h0,2); | |
964 | dbuff_pc dbuff_pc_t0 ( | |
965 | .cycle (cycle[63:0]), | |
966 | .pc (`TOP.axis_trap_top.c2.t0.pc_fw2), | |
967 | .clk (`CPU.l2clk), | |
968 | .core (cid), | |
969 | .thread (thread0_id) | |
970 | ); | |
971 | ||
972 | always @(posedge axis_top.start_dumps) | |
973 | begin // axis tbcall_region | |
974 | $display("DMP2_0: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t0.addr,tb_top.axis_trap_top.c2.dbuff_pc_t0.ptr_0_cycle); | |
975 | $axis_dumpmemh("c2_t0_pctrc.dat", | |
976 | tb_top.axis_trap_top.c2.dbuff_pc_t0.DBUFF); | |
977 | end | |
978 | ||
979 | ||
980 | //---------------------------------------------------------- | |
981 | // | |
982 | // THREAD 1 | |
983 | // | |
984 | ||
985 | ||
986 | axis_trap_pipe2 t1 ( | |
987 | .mycid (cid), | |
988 | .mytid (3'h1), | |
989 | .PC_reg (pc_1_w) | |
990 | ); | |
991 | ||
992 | wire [2:0] thread1_id=3'h1; | |
993 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c2.t1.pc_fw2},`CPU.l2clk,3'h1,2); | |
994 | dbuff_pc dbuff_pc_t1 ( | |
995 | .cycle (cycle[63:0]), | |
996 | .pc (`TOP.axis_trap_top.c2.t1.pc_fw2), | |
997 | .clk (`CPU.l2clk), | |
998 | .core (cid), | |
999 | .thread (thread1_id) | |
1000 | ); | |
1001 | ||
1002 | always @(posedge axis_top.start_dumps) | |
1003 | begin // axis tbcall_region | |
1004 | $display("DMP2_1: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t1.addr,tb_top.axis_trap_top.c2.dbuff_pc_t1.ptr_0_cycle); | |
1005 | $axis_dumpmemh("c2_t1_pctrc.dat", | |
1006 | tb_top.axis_trap_top.c2.dbuff_pc_t1.DBUFF); | |
1007 | end | |
1008 | ||
1009 | ||
1010 | //---------------------------------------------------------- | |
1011 | // | |
1012 | // THREAD 2 | |
1013 | // | |
1014 | ||
1015 | ||
1016 | axis_trap_pipe2 t2 ( | |
1017 | .mycid (cid), | |
1018 | .mytid (3'h2), | |
1019 | .PC_reg (pc_2_w) | |
1020 | ); | |
1021 | ||
1022 | wire [2:0] thread2_id=3'h2; | |
1023 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c2.t2.pc_fw2},`CPU.l2clk,3'h2,2); | |
1024 | dbuff_pc dbuff_pc_t2 ( | |
1025 | .cycle (cycle[63:0]), | |
1026 | .pc (`TOP.axis_trap_top.c2.t2.pc_fw2), | |
1027 | .clk (`CPU.l2clk), | |
1028 | .core (cid), | |
1029 | .thread (thread2_id) | |
1030 | ); | |
1031 | ||
1032 | always @(posedge axis_top.start_dumps) | |
1033 | begin // axis tbcall_region | |
1034 | $display("DMP2_2: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t2.addr,tb_top.axis_trap_top.c2.dbuff_pc_t2.ptr_0_cycle); | |
1035 | $axis_dumpmemh("c2_t2_pctrc.dat", | |
1036 | tb_top.axis_trap_top.c2.dbuff_pc_t2.DBUFF); | |
1037 | end | |
1038 | ||
1039 | ||
1040 | //---------------------------------------------------------- | |
1041 | // | |
1042 | // THREAD 3 | |
1043 | // | |
1044 | ||
1045 | ||
1046 | axis_trap_pipe2 t3 ( | |
1047 | .mycid (cid), | |
1048 | .mytid (3'h3), | |
1049 | .PC_reg (pc_3_w) | |
1050 | ); | |
1051 | ||
1052 | wire [2:0] thread3_id=3'h3; | |
1053 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c2.t3.pc_fw2},`CPU.l2clk,3'h3,2); | |
1054 | dbuff_pc dbuff_pc_t3 ( | |
1055 | .cycle (cycle[63:0]), | |
1056 | .pc (`TOP.axis_trap_top.c2.t3.pc_fw2), | |
1057 | .clk (`CPU.l2clk), | |
1058 | .core (cid), | |
1059 | .thread (thread3_id) | |
1060 | ); | |
1061 | ||
1062 | always @(posedge axis_top.start_dumps) | |
1063 | begin // axis tbcall_region | |
1064 | $display("DMP2_3: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t3.addr,tb_top.axis_trap_top.c2.dbuff_pc_t3.ptr_0_cycle); | |
1065 | $axis_dumpmemh("c2_t3_pctrc.dat", | |
1066 | tb_top.axis_trap_top.c2.dbuff_pc_t3.DBUFF); | |
1067 | end | |
1068 | ||
1069 | ||
1070 | reg [5:0] trl0_tsa_wr_addr_r; | |
1071 | reg [1:0] tsd0_wr_gl_r; | |
1072 | reg [8:0] tsd0_wr_trap_type_r; | |
1073 | reg [47:2] tsd0_wr_tpc_r; | |
1074 | reg trl0_tsa_wr_en_r; | |
1075 | always @(posedge `CPU.l2clk) begin | |
1076 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc2.tlu.trl0_tsa_wr_addr; | |
1077 | tsd0_wr_gl_r <= tb_top.cpu.spc2.tlu.tsd0_wr_gl; | |
1078 | tsd0_wr_trap_type_r <= tb_top.cpu.spc2.tlu.tsd0_wr_trap_type[8:0]; | |
1079 | tsd0_wr_tpc_r <= tb_top.cpu.spc2.tlu.tsd0_wr_tpc; | |
1080 | trl0_tsa_wr_en_r <= tb_top.cpu.spc2.tlu.trl_tsa_wr_en[0]; | |
1081 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
1082 | begin // axis tbcall_region | |
1083 | $display("%t: TRAP WRITE: CORE 2: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
1084 | end | |
1085 | end | |
1086 | end | |
1087 | ||
1088 | //---------------------------------------------------------- | |
1089 | // | |
1090 | // THREAD 4 | |
1091 | // | |
1092 | ||
1093 | ||
1094 | axis_trap_pipe2 t4 ( | |
1095 | .mycid (cid), | |
1096 | .mytid (3'h4), | |
1097 | .PC_reg (pc_4_w) | |
1098 | ); | |
1099 | ||
1100 | wire [2:0] thread4_id=3'h4; | |
1101 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c2.t4.pc_fw2},`CPU.l2clk,3'h4,2); | |
1102 | dbuff_pc dbuff_pc_t4 ( | |
1103 | .cycle (cycle[63:0]), | |
1104 | .pc (`TOP.axis_trap_top.c2.t4.pc_fw2), | |
1105 | .clk (`CPU.l2clk), | |
1106 | .core (cid), | |
1107 | .thread (thread4_id) | |
1108 | ); | |
1109 | ||
1110 | always @(posedge axis_top.start_dumps) | |
1111 | begin // axis tbcall_region | |
1112 | $display("DMP2_4: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t4.addr,tb_top.axis_trap_top.c2.dbuff_pc_t4.ptr_0_cycle); | |
1113 | $axis_dumpmemh("c2_t4_pctrc.dat", | |
1114 | tb_top.axis_trap_top.c2.dbuff_pc_t4.DBUFF); | |
1115 | end | |
1116 | ||
1117 | ||
1118 | //---------------------------------------------------------- | |
1119 | // | |
1120 | // THREAD 5 | |
1121 | // | |
1122 | ||
1123 | ||
1124 | axis_trap_pipe2 t5 ( | |
1125 | .mycid (cid), | |
1126 | .mytid (3'h5), | |
1127 | .PC_reg (pc_5_w) | |
1128 | ); | |
1129 | ||
1130 | wire [2:0] thread5_id=3'h5; | |
1131 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c2.t5.pc_fw2},`CPU.l2clk,3'h5,2); | |
1132 | dbuff_pc dbuff_pc_t5 ( | |
1133 | .cycle (cycle[63:0]), | |
1134 | .pc (`TOP.axis_trap_top.c2.t5.pc_fw2), | |
1135 | .clk (`CPU.l2clk), | |
1136 | .core (cid), | |
1137 | .thread (thread5_id) | |
1138 | ); | |
1139 | ||
1140 | always @(posedge axis_top.start_dumps) | |
1141 | begin // axis tbcall_region | |
1142 | $display("DMP2_5: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t5.addr,tb_top.axis_trap_top.c2.dbuff_pc_t5.ptr_0_cycle); | |
1143 | $axis_dumpmemh("c2_t5_pctrc.dat", | |
1144 | tb_top.axis_trap_top.c2.dbuff_pc_t5.DBUFF); | |
1145 | end | |
1146 | ||
1147 | ||
1148 | //---------------------------------------------------------- | |
1149 | // | |
1150 | // THREAD 6 | |
1151 | // | |
1152 | ||
1153 | ||
1154 | axis_trap_pipe2 t6 ( | |
1155 | .mycid (cid), | |
1156 | .mytid (3'h6), | |
1157 | .PC_reg (pc_6_w) | |
1158 | ); | |
1159 | ||
1160 | wire [2:0] thread6_id=3'h6; | |
1161 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c2.t6.pc_fw2},`CPU.l2clk,3'h6,2); | |
1162 | dbuff_pc dbuff_pc_t6 ( | |
1163 | .cycle (cycle[63:0]), | |
1164 | .pc (`TOP.axis_trap_top.c2.t6.pc_fw2), | |
1165 | .clk (`CPU.l2clk), | |
1166 | .core (cid), | |
1167 | .thread (thread6_id) | |
1168 | ); | |
1169 | ||
1170 | always @(posedge axis_top.start_dumps) | |
1171 | begin // axis tbcall_region | |
1172 | $display("DMP2_6: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t6.addr,tb_top.axis_trap_top.c2.dbuff_pc_t6.ptr_0_cycle); | |
1173 | $axis_dumpmemh("c2_t6_pctrc.dat", | |
1174 | tb_top.axis_trap_top.c2.dbuff_pc_t6.DBUFF); | |
1175 | end | |
1176 | ||
1177 | ||
1178 | //---------------------------------------------------------- | |
1179 | // | |
1180 | // THREAD 7 | |
1181 | // | |
1182 | ||
1183 | ||
1184 | axis_trap_pipe2 t7 ( | |
1185 | .mycid (cid), | |
1186 | .mytid (3'h7), | |
1187 | .PC_reg (pc_7_w) | |
1188 | ); | |
1189 | ||
1190 | wire [2:0] thread7_id=3'h7; | |
1191 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c2.t7.pc_fw2},`CPU.l2clk,3'h7,2); | |
1192 | dbuff_pc dbuff_pc_t7 ( | |
1193 | .cycle (cycle[63:0]), | |
1194 | .pc (`TOP.axis_trap_top.c2.t7.pc_fw2), | |
1195 | .clk (`CPU.l2clk), | |
1196 | .core (cid), | |
1197 | .thread (thread7_id) | |
1198 | ); | |
1199 | ||
1200 | always @(posedge axis_top.start_dumps) | |
1201 | begin // axis tbcall_region | |
1202 | $display("DMP2_7: %h %h \n",tb_top.axis_trap_top.c2.dbuff_pc_t7.addr,tb_top.axis_trap_top.c2.dbuff_pc_t7.ptr_0_cycle); | |
1203 | $axis_dumpmemh("c2_t7_pctrc.dat", | |
1204 | tb_top.axis_trap_top.c2.dbuff_pc_t7.DBUFF); | |
1205 | end | |
1206 | ||
1207 | ||
1208 | reg [5:0] trl1_tsa_wr_addr_r; | |
1209 | reg [1:0] tsd1_wr_gl_r; | |
1210 | reg [8:0] tsd1_wr_trap_type_r; | |
1211 | reg [47:2] tsd1_wr_tpc_r; | |
1212 | reg trl1_tsa_wr_en_r; | |
1213 | always @(posedge `CPU.l2clk) begin | |
1214 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc2.tlu.trl1_tsa_wr_addr; | |
1215 | tsd1_wr_gl_r <= tb_top.cpu.spc2.tlu.tsd1_wr_gl; | |
1216 | tsd1_wr_trap_type_r <= tb_top.cpu.spc2.tlu.tsd1_wr_trap_type[8:0]; | |
1217 | tsd1_wr_tpc_r <= tb_top.cpu.spc2.tlu.tsd1_wr_tpc; | |
1218 | trl1_tsa_wr_en_r <= tb_top.cpu.spc2.tlu.trl_tsa_wr_en[1]; | |
1219 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
1220 | begin // axis tbcall_region | |
1221 | $display("%t: TRAP WRITE: CORE 2: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
1222 | end | |
1223 | end | |
1224 | end | |
1225 | ||
1226 | //---------------------------------------------------------- | |
1227 | ||
1228 | `ifndef GATESIM | |
1229 | ||
1230 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
1231 | // But some of the error checkers need this signal without the qualification | |
1232 | // of icache errors | |
1233 | wire [7:0] select_pc_b_with_errors; | |
1234 | ||
1235 | assign select_pc_b_with_errors = | |
1236 | {{4 {~`SPC2.dec_flush_b[1]}}, {4 {~`SPC2.dec_flush_b[0]}}} & | |
1237 | ||
1238 | {~(`SPC2.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
1239 | {4 {`SPC2.tlu.fls1.idl_req_in}}), | |
1240 | ~(`SPC2.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
1241 | {4 {`SPC2.tlu.fls0.idl_req_in}})} & | |
1242 | {`SPC2.tlu.fls1.tid_dec_valid_b[3:0], | |
1243 | `SPC2.tlu.fls0.tid_dec_valid_b[3:0]}; | |
1244 | ||
1245 | //------------------------------------ | |
1246 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
1247 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
1248 | wire [7:0] select_pc_b; | |
1249 | ||
1250 | assign select_pc_b = | |
1251 | select_pc_b_with_errors[7:0] & | |
1252 | {{4 {~`SPC2.tlu.fls1.ic_err_w_in}}, {4 {~`SPC2.tlu.fls0.ic_err_w_in}}}; | |
1253 | ||
1254 | //------------------------------------ | |
1255 | // ASI & Trap State machines | |
1256 | always @(posedge `SPC2.gclk) begin // { | |
1257 | ||
1258 | // pc_0_e[47:0] <= `SPC2.ifu_pc_d0[47:0]; | |
1259 | // pc_1_e[47:0] <= `SPC2.ifu_pc_d1[47:0]; | |
1260 | pc_0_e[47:0] <= {`SPC2.tlu_pc_0_d[47:2], 2'b00}; | |
1261 | pc_1_e[47:0] <= {`SPC2.tlu_pc_1_d[47:2], 2'b00}; | |
1262 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
1263 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
1264 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
1265 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
1266 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
1267 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
1268 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
1269 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
1270 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
1271 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
1272 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
1273 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
1274 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
1275 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
1276 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
1277 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
1278 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
1279 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
1280 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
1281 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
1282 | end | |
1283 | ||
1284 | `endif | |
1285 | `endif //AXIS_TL | |
1286 | ||
1287 | //---------------------------------------------------------- | |
1288 | endmodule | |
1289 | ||
1290 | `endif | |
1291 | ||
1292 | `ifdef CORE_3 | |
1293 | ||
1294 | module axis_trap_core3 ( | |
1295 | cid, | |
1296 | pc_dmp_sz, | |
1297 | ); | |
1298 | ||
1299 | input [2:0] cid; | |
1300 | input [21:0] pc_dmp_sz; | |
1301 | ||
1302 | `ifdef AXIS_TL | |
1303 | `ifndef GATESIM | |
1304 | reg [47:0] pc_0_e; | |
1305 | reg [47:0] pc_1_e; | |
1306 | reg [47:0] pc_0_m; | |
1307 | reg [47:0] pc_1_m; | |
1308 | reg [47:0] pc_0_b; | |
1309 | reg [47:0] pc_1_b; | |
1310 | reg [47:0] pc_0_w; | |
1311 | reg [47:0] pc_1_w; | |
1312 | reg [47:0] pc_2_w; | |
1313 | reg [47:0] pc_3_w; | |
1314 | reg [47:0] pc_4_w; | |
1315 | reg [47:0] pc_5_w; | |
1316 | reg [47:0] pc_6_w; | |
1317 | reg [47:0] pc_7_w; | |
1318 | `endif | |
1319 | ||
1320 | //---------------------------------------------------------- | |
1321 | reg [63:0] cycle; | |
1322 | initial cycle = 64'b0; | |
1323 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
1324 | if (`CPU.tcu_aclk) cycle = 0; | |
1325 | else cycle = cycle + 64'b1; | |
1326 | end | |
1327 | ||
1328 | //*******************************************************************************************************/ | |
1329 | reg [76:0] sig_reg_0; | |
1330 | reg [76:0] sig_reg_1; | |
1331 | reg [76:0] sig_reg_2; | |
1332 | reg [76:0] sig_reg_3; | |
1333 | reg [63:0] kern_cnt; | |
1334 | reg [47:0] pc_0_saved; | |
1335 | ||
1336 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
1337 | always @(negedge `CPU.tcu_aclk) begin | |
1338 | begin // axis tbcall_region | |
1339 | $display("%t: dbg rst detected by repeatability_check", $time); | |
1340 | end | |
1341 | end | |
1342 | ||
1343 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
1344 | pc_0_saved <= pc_0_w; | |
1345 | if (`CPU.tcu_aclk) begin | |
1346 | sig_reg_1 <= 0; | |
1347 | sig_reg_2 <= 0; | |
1348 | sig_reg_3 <= 0; | |
1349 | sig_reg_0 <= 0; | |
1350 | kern_cnt <= 0; | |
1351 | end | |
1352 | else if (!`CPU.tcu_aclk) begin | |
1353 | if (tb_top.cpu.spc3.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc3.exu0.irf.wr_addr_p0,tb_top.cpu.spc3.exu0.irf.wr_data_p0}; | |
1354 | if (tb_top.cpu.spc3.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc3.exu0.irf.wr_addr_p1,tb_top.cpu.spc3.exu0.irf.wr_data_p1}; | |
1355 | if (tb_top.cpu.spc3.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc3.exu1.irf.wr_addr_p0,tb_top.cpu.spc3.exu1.irf.wr_data_p0}; | |
1356 | if (tb_top.cpu.spc3.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc3.exu1.irf.wr_addr_p1,tb_top.cpu.spc3.exu1.irf.wr_data_p1}; | |
1357 | kern_cnt <= kern_cnt + 1; | |
1358 | end | |
1359 | ||
1360 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
1361 | $display("%t: repeatability_check: core 3, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
1362 | end | |
1363 | ||
1364 | end | |
1365 | ||
1366 | //************************************************************************************************** | |
1367 | //---------------------------------------------------------- | |
1368 | ||
1369 | //---------------------------------------------------------- | |
1370 | // | |
1371 | // THREAD 0 | |
1372 | // | |
1373 | ||
1374 | ||
1375 | axis_trap_pipe3 t0 ( | |
1376 | .mycid (cid), | |
1377 | .mytid (3'h0), | |
1378 | .PC_reg (pc_0_w) | |
1379 | ); | |
1380 | ||
1381 | wire [2:0] thread0_id=3'h0; | |
1382 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c3.t0.pc_fw2},`CPU.l2clk,3'h0,3); | |
1383 | dbuff_pc dbuff_pc_t0 ( | |
1384 | .cycle (cycle[63:0]), | |
1385 | .pc (`TOP.axis_trap_top.c3.t0.pc_fw2), | |
1386 | .clk (`CPU.l2clk), | |
1387 | .core (cid), | |
1388 | .thread (thread0_id) | |
1389 | ); | |
1390 | ||
1391 | always @(posedge axis_top.start_dumps) | |
1392 | begin // axis tbcall_region | |
1393 | $display("DMP3_0: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t0.addr,tb_top.axis_trap_top.c3.dbuff_pc_t0.ptr_0_cycle); | |
1394 | $axis_dumpmemh("c3_t0_pctrc.dat", | |
1395 | tb_top.axis_trap_top.c3.dbuff_pc_t0.DBUFF); | |
1396 | end | |
1397 | ||
1398 | ||
1399 | //---------------------------------------------------------- | |
1400 | // | |
1401 | // THREAD 1 | |
1402 | // | |
1403 | ||
1404 | ||
1405 | axis_trap_pipe3 t1 ( | |
1406 | .mycid (cid), | |
1407 | .mytid (3'h1), | |
1408 | .PC_reg (pc_1_w) | |
1409 | ); | |
1410 | ||
1411 | wire [2:0] thread1_id=3'h1; | |
1412 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c3.t1.pc_fw2},`CPU.l2clk,3'h1,3); | |
1413 | dbuff_pc dbuff_pc_t1 ( | |
1414 | .cycle (cycle[63:0]), | |
1415 | .pc (`TOP.axis_trap_top.c3.t1.pc_fw2), | |
1416 | .clk (`CPU.l2clk), | |
1417 | .core (cid), | |
1418 | .thread (thread1_id) | |
1419 | ); | |
1420 | ||
1421 | always @(posedge axis_top.start_dumps) | |
1422 | begin // axis tbcall_region | |
1423 | $display("DMP3_1: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t1.addr,tb_top.axis_trap_top.c3.dbuff_pc_t1.ptr_0_cycle); | |
1424 | $axis_dumpmemh("c3_t1_pctrc.dat", | |
1425 | tb_top.axis_trap_top.c3.dbuff_pc_t1.DBUFF); | |
1426 | end | |
1427 | ||
1428 | ||
1429 | //---------------------------------------------------------- | |
1430 | // | |
1431 | // THREAD 2 | |
1432 | // | |
1433 | ||
1434 | ||
1435 | axis_trap_pipe3 t2 ( | |
1436 | .mycid (cid), | |
1437 | .mytid (3'h2), | |
1438 | .PC_reg (pc_2_w) | |
1439 | ); | |
1440 | ||
1441 | wire [2:0] thread2_id=3'h2; | |
1442 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c3.t2.pc_fw2},`CPU.l2clk,3'h2,3); | |
1443 | dbuff_pc dbuff_pc_t2 ( | |
1444 | .cycle (cycle[63:0]), | |
1445 | .pc (`TOP.axis_trap_top.c3.t2.pc_fw2), | |
1446 | .clk (`CPU.l2clk), | |
1447 | .core (cid), | |
1448 | .thread (thread2_id) | |
1449 | ); | |
1450 | ||
1451 | always @(posedge axis_top.start_dumps) | |
1452 | begin // axis tbcall_region | |
1453 | $display("DMP3_2: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t2.addr,tb_top.axis_trap_top.c3.dbuff_pc_t2.ptr_0_cycle); | |
1454 | $axis_dumpmemh("c3_t2_pctrc.dat", | |
1455 | tb_top.axis_trap_top.c3.dbuff_pc_t2.DBUFF); | |
1456 | end | |
1457 | ||
1458 | ||
1459 | //---------------------------------------------------------- | |
1460 | // | |
1461 | // THREAD 3 | |
1462 | // | |
1463 | ||
1464 | ||
1465 | axis_trap_pipe3 t3 ( | |
1466 | .mycid (cid), | |
1467 | .mytid (3'h3), | |
1468 | .PC_reg (pc_3_w) | |
1469 | ); | |
1470 | ||
1471 | wire [2:0] thread3_id=3'h3; | |
1472 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c3.t3.pc_fw2},`CPU.l2clk,3'h3,3); | |
1473 | dbuff_pc dbuff_pc_t3 ( | |
1474 | .cycle (cycle[63:0]), | |
1475 | .pc (`TOP.axis_trap_top.c3.t3.pc_fw2), | |
1476 | .clk (`CPU.l2clk), | |
1477 | .core (cid), | |
1478 | .thread (thread3_id) | |
1479 | ); | |
1480 | ||
1481 | always @(posedge axis_top.start_dumps) | |
1482 | begin // axis tbcall_region | |
1483 | $display("DMP3_3: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t3.addr,tb_top.axis_trap_top.c3.dbuff_pc_t3.ptr_0_cycle); | |
1484 | $axis_dumpmemh("c3_t3_pctrc.dat", | |
1485 | tb_top.axis_trap_top.c3.dbuff_pc_t3.DBUFF); | |
1486 | end | |
1487 | ||
1488 | ||
1489 | reg [5:0] trl0_tsa_wr_addr_r; | |
1490 | reg [1:0] tsd0_wr_gl_r; | |
1491 | reg [8:0] tsd0_wr_trap_type_r; | |
1492 | reg [47:2] tsd0_wr_tpc_r; | |
1493 | reg trl0_tsa_wr_en_r; | |
1494 | always @(posedge `CPU.l2clk) begin | |
1495 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc3.tlu.trl0_tsa_wr_addr; | |
1496 | tsd0_wr_gl_r <= tb_top.cpu.spc3.tlu.tsd0_wr_gl; | |
1497 | tsd0_wr_trap_type_r <= tb_top.cpu.spc3.tlu.tsd0_wr_trap_type[8:0]; | |
1498 | tsd0_wr_tpc_r <= tb_top.cpu.spc3.tlu.tsd0_wr_tpc; | |
1499 | trl0_tsa_wr_en_r <= tb_top.cpu.spc3.tlu.trl_tsa_wr_en[0]; | |
1500 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
1501 | begin // axis tbcall_region | |
1502 | $display("%t: TRAP WRITE: CORE 3: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
1503 | end | |
1504 | end | |
1505 | end | |
1506 | ||
1507 | //---------------------------------------------------------- | |
1508 | // | |
1509 | // THREAD 4 | |
1510 | // | |
1511 | ||
1512 | ||
1513 | axis_trap_pipe3 t4 ( | |
1514 | .mycid (cid), | |
1515 | .mytid (3'h4), | |
1516 | .PC_reg (pc_4_w) | |
1517 | ); | |
1518 | ||
1519 | wire [2:0] thread4_id=3'h4; | |
1520 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c3.t4.pc_fw2},`CPU.l2clk,3'h4,3); | |
1521 | dbuff_pc dbuff_pc_t4 ( | |
1522 | .cycle (cycle[63:0]), | |
1523 | .pc (`TOP.axis_trap_top.c3.t4.pc_fw2), | |
1524 | .clk (`CPU.l2clk), | |
1525 | .core (cid), | |
1526 | .thread (thread4_id) | |
1527 | ); | |
1528 | ||
1529 | always @(posedge axis_top.start_dumps) | |
1530 | begin // axis tbcall_region | |
1531 | $display("DMP3_4: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t4.addr,tb_top.axis_trap_top.c3.dbuff_pc_t4.ptr_0_cycle); | |
1532 | $axis_dumpmemh("c3_t4_pctrc.dat", | |
1533 | tb_top.axis_trap_top.c3.dbuff_pc_t4.DBUFF); | |
1534 | end | |
1535 | ||
1536 | ||
1537 | //---------------------------------------------------------- | |
1538 | // | |
1539 | // THREAD 5 | |
1540 | // | |
1541 | ||
1542 | ||
1543 | axis_trap_pipe3 t5 ( | |
1544 | .mycid (cid), | |
1545 | .mytid (3'h5), | |
1546 | .PC_reg (pc_5_w) | |
1547 | ); | |
1548 | ||
1549 | wire [2:0] thread5_id=3'h5; | |
1550 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c3.t5.pc_fw2},`CPU.l2clk,3'h5,3); | |
1551 | dbuff_pc dbuff_pc_t5 ( | |
1552 | .cycle (cycle[63:0]), | |
1553 | .pc (`TOP.axis_trap_top.c3.t5.pc_fw2), | |
1554 | .clk (`CPU.l2clk), | |
1555 | .core (cid), | |
1556 | .thread (thread5_id) | |
1557 | ); | |
1558 | ||
1559 | always @(posedge axis_top.start_dumps) | |
1560 | begin // axis tbcall_region | |
1561 | $display("DMP3_5: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t5.addr,tb_top.axis_trap_top.c3.dbuff_pc_t5.ptr_0_cycle); | |
1562 | $axis_dumpmemh("c3_t5_pctrc.dat", | |
1563 | tb_top.axis_trap_top.c3.dbuff_pc_t5.DBUFF); | |
1564 | end | |
1565 | ||
1566 | ||
1567 | //---------------------------------------------------------- | |
1568 | // | |
1569 | // THREAD 6 | |
1570 | // | |
1571 | ||
1572 | ||
1573 | axis_trap_pipe3 t6 ( | |
1574 | .mycid (cid), | |
1575 | .mytid (3'h6), | |
1576 | .PC_reg (pc_6_w) | |
1577 | ); | |
1578 | ||
1579 | wire [2:0] thread6_id=3'h6; | |
1580 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c3.t6.pc_fw2},`CPU.l2clk,3'h6,3); | |
1581 | dbuff_pc dbuff_pc_t6 ( | |
1582 | .cycle (cycle[63:0]), | |
1583 | .pc (`TOP.axis_trap_top.c3.t6.pc_fw2), | |
1584 | .clk (`CPU.l2clk), | |
1585 | .core (cid), | |
1586 | .thread (thread6_id) | |
1587 | ); | |
1588 | ||
1589 | always @(posedge axis_top.start_dumps) | |
1590 | begin // axis tbcall_region | |
1591 | $display("DMP3_6: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t6.addr,tb_top.axis_trap_top.c3.dbuff_pc_t6.ptr_0_cycle); | |
1592 | $axis_dumpmemh("c3_t6_pctrc.dat", | |
1593 | tb_top.axis_trap_top.c3.dbuff_pc_t6.DBUFF); | |
1594 | end | |
1595 | ||
1596 | ||
1597 | //---------------------------------------------------------- | |
1598 | // | |
1599 | // THREAD 7 | |
1600 | // | |
1601 | ||
1602 | ||
1603 | axis_trap_pipe3 t7 ( | |
1604 | .mycid (cid), | |
1605 | .mytid (3'h7), | |
1606 | .PC_reg (pc_7_w) | |
1607 | ); | |
1608 | ||
1609 | wire [2:0] thread7_id=3'h7; | |
1610 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c3.t7.pc_fw2},`CPU.l2clk,3'h7,3); | |
1611 | dbuff_pc dbuff_pc_t7 ( | |
1612 | .cycle (cycle[63:0]), | |
1613 | .pc (`TOP.axis_trap_top.c3.t7.pc_fw2), | |
1614 | .clk (`CPU.l2clk), | |
1615 | .core (cid), | |
1616 | .thread (thread7_id) | |
1617 | ); | |
1618 | ||
1619 | always @(posedge axis_top.start_dumps) | |
1620 | begin // axis tbcall_region | |
1621 | $display("DMP3_7: %h %h \n",tb_top.axis_trap_top.c3.dbuff_pc_t7.addr,tb_top.axis_trap_top.c3.dbuff_pc_t7.ptr_0_cycle); | |
1622 | $axis_dumpmemh("c3_t7_pctrc.dat", | |
1623 | tb_top.axis_trap_top.c3.dbuff_pc_t7.DBUFF); | |
1624 | end | |
1625 | ||
1626 | ||
1627 | reg [5:0] trl1_tsa_wr_addr_r; | |
1628 | reg [1:0] tsd1_wr_gl_r; | |
1629 | reg [8:0] tsd1_wr_trap_type_r; | |
1630 | reg [47:2] tsd1_wr_tpc_r; | |
1631 | reg trl1_tsa_wr_en_r; | |
1632 | always @(posedge `CPU.l2clk) begin | |
1633 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc3.tlu.trl1_tsa_wr_addr; | |
1634 | tsd1_wr_gl_r <= tb_top.cpu.spc3.tlu.tsd1_wr_gl; | |
1635 | tsd1_wr_trap_type_r <= tb_top.cpu.spc3.tlu.tsd1_wr_trap_type[8:0]; | |
1636 | tsd1_wr_tpc_r <= tb_top.cpu.spc3.tlu.tsd1_wr_tpc; | |
1637 | trl1_tsa_wr_en_r <= tb_top.cpu.spc3.tlu.trl_tsa_wr_en[1]; | |
1638 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
1639 | begin // axis tbcall_region | |
1640 | $display("%t: TRAP WRITE: CORE 3: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
1641 | end | |
1642 | end | |
1643 | end | |
1644 | ||
1645 | //---------------------------------------------------------- | |
1646 | ||
1647 | `ifndef GATESIM | |
1648 | ||
1649 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
1650 | // But some of the error checkers need this signal without the qualification | |
1651 | // of icache errors | |
1652 | wire [7:0] select_pc_b_with_errors; | |
1653 | ||
1654 | assign select_pc_b_with_errors = | |
1655 | {{4 {~`SPC3.dec_flush_b[1]}}, {4 {~`SPC3.dec_flush_b[0]}}} & | |
1656 | ||
1657 | {~(`SPC3.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
1658 | {4 {`SPC3.tlu.fls1.idl_req_in}}), | |
1659 | ~(`SPC3.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
1660 | {4 {`SPC3.tlu.fls0.idl_req_in}})} & | |
1661 | {`SPC3.tlu.fls1.tid_dec_valid_b[3:0], | |
1662 | `SPC3.tlu.fls0.tid_dec_valid_b[3:0]}; | |
1663 | ||
1664 | //------------------------------------ | |
1665 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
1666 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
1667 | wire [7:0] select_pc_b; | |
1668 | ||
1669 | assign select_pc_b = | |
1670 | select_pc_b_with_errors[7:0] & | |
1671 | {{4 {~`SPC3.tlu.fls1.ic_err_w_in}}, {4 {~`SPC3.tlu.fls0.ic_err_w_in}}}; | |
1672 | ||
1673 | //------------------------------------ | |
1674 | // ASI & Trap State machines | |
1675 | always @(posedge `SPC3.gclk) begin // { | |
1676 | ||
1677 | // pc_0_e[47:0] <= `SPC3.ifu_pc_d0[47:0]; | |
1678 | // pc_1_e[47:0] <= `SPC3.ifu_pc_d1[47:0]; | |
1679 | pc_0_e[47:0] <= {`SPC3.tlu_pc_0_d[47:2], 2'b00}; | |
1680 | pc_1_e[47:0] <= {`SPC3.tlu_pc_1_d[47:2], 2'b00}; | |
1681 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
1682 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
1683 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
1684 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
1685 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
1686 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
1687 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
1688 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
1689 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
1690 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
1691 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
1692 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
1693 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
1694 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
1695 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
1696 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
1697 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
1698 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
1699 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
1700 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
1701 | end | |
1702 | ||
1703 | `endif | |
1704 | `endif //AXIS_TL | |
1705 | ||
1706 | //---------------------------------------------------------- | |
1707 | endmodule | |
1708 | ||
1709 | `endif | |
1710 | ||
1711 | `ifdef CORE_4 | |
1712 | ||
1713 | module axis_trap_core4 ( | |
1714 | cid, | |
1715 | pc_dmp_sz, | |
1716 | ); | |
1717 | ||
1718 | input [2:0] cid; | |
1719 | input [21:0] pc_dmp_sz; | |
1720 | ||
1721 | `ifdef AXIS_TL | |
1722 | `ifndef GATESIM | |
1723 | reg [47:0] pc_0_e; | |
1724 | reg [47:0] pc_1_e; | |
1725 | reg [47:0] pc_0_m; | |
1726 | reg [47:0] pc_1_m; | |
1727 | reg [47:0] pc_0_b; | |
1728 | reg [47:0] pc_1_b; | |
1729 | reg [47:0] pc_0_w; | |
1730 | reg [47:0] pc_1_w; | |
1731 | reg [47:0] pc_2_w; | |
1732 | reg [47:0] pc_3_w; | |
1733 | reg [47:0] pc_4_w; | |
1734 | reg [47:0] pc_5_w; | |
1735 | reg [47:0] pc_6_w; | |
1736 | reg [47:0] pc_7_w; | |
1737 | `endif | |
1738 | ||
1739 | //---------------------------------------------------------- | |
1740 | reg [63:0] cycle; | |
1741 | initial cycle = 64'b0; | |
1742 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
1743 | if (`CPU.tcu_aclk) cycle = 0; | |
1744 | else cycle = cycle + 64'b1; | |
1745 | end | |
1746 | ||
1747 | //*******************************************************************************************************/ | |
1748 | reg [76:0] sig_reg_0; | |
1749 | reg [76:0] sig_reg_1; | |
1750 | reg [76:0] sig_reg_2; | |
1751 | reg [76:0] sig_reg_3; | |
1752 | reg [63:0] kern_cnt; | |
1753 | reg [47:0] pc_0_saved; | |
1754 | ||
1755 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
1756 | always @(negedge `CPU.tcu_aclk) begin | |
1757 | begin // axis tbcall_region | |
1758 | $display("%t: dbg rst detected by repeatability_check", $time); | |
1759 | end | |
1760 | end | |
1761 | ||
1762 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
1763 | pc_0_saved <= pc_0_w; | |
1764 | if (`CPU.tcu_aclk) begin | |
1765 | sig_reg_1 <= 0; | |
1766 | sig_reg_2 <= 0; | |
1767 | sig_reg_3 <= 0; | |
1768 | sig_reg_0 <= 0; | |
1769 | kern_cnt <= 0; | |
1770 | end | |
1771 | else if (!`CPU.tcu_aclk) begin | |
1772 | if (tb_top.cpu.spc4.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc4.exu0.irf.wr_addr_p0,tb_top.cpu.spc4.exu0.irf.wr_data_p0}; | |
1773 | if (tb_top.cpu.spc4.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc4.exu0.irf.wr_addr_p1,tb_top.cpu.spc4.exu0.irf.wr_data_p1}; | |
1774 | if (tb_top.cpu.spc4.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc4.exu1.irf.wr_addr_p0,tb_top.cpu.spc4.exu1.irf.wr_data_p0}; | |
1775 | if (tb_top.cpu.spc4.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc4.exu1.irf.wr_addr_p1,tb_top.cpu.spc4.exu1.irf.wr_data_p1}; | |
1776 | kern_cnt <= kern_cnt + 1; | |
1777 | end | |
1778 | ||
1779 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
1780 | $display("%t: repeatability_check: core 4, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
1781 | end | |
1782 | ||
1783 | end | |
1784 | ||
1785 | //************************************************************************************************** | |
1786 | //---------------------------------------------------------- | |
1787 | ||
1788 | //---------------------------------------------------------- | |
1789 | // | |
1790 | // THREAD 0 | |
1791 | // | |
1792 | ||
1793 | ||
1794 | axis_trap_pipe4 t0 ( | |
1795 | .mycid (cid), | |
1796 | .mytid (3'h0), | |
1797 | .PC_reg (pc_0_w) | |
1798 | ); | |
1799 | ||
1800 | wire [2:0] thread0_id=3'h0; | |
1801 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c4.t0.pc_fw2},`CPU.l2clk,3'h0,4); | |
1802 | dbuff_pc dbuff_pc_t0 ( | |
1803 | .cycle (cycle[63:0]), | |
1804 | .pc (`TOP.axis_trap_top.c4.t0.pc_fw2), | |
1805 | .clk (`CPU.l2clk), | |
1806 | .core (cid), | |
1807 | .thread (thread0_id) | |
1808 | ); | |
1809 | ||
1810 | always @(posedge axis_top.start_dumps) | |
1811 | begin // axis tbcall_region | |
1812 | $display("DMP4_0: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t0.addr,tb_top.axis_trap_top.c4.dbuff_pc_t0.ptr_0_cycle); | |
1813 | $axis_dumpmemh("c4_t0_pctrc.dat", | |
1814 | tb_top.axis_trap_top.c4.dbuff_pc_t0.DBUFF); | |
1815 | end | |
1816 | ||
1817 | ||
1818 | //---------------------------------------------------------- | |
1819 | // | |
1820 | // THREAD 1 | |
1821 | // | |
1822 | ||
1823 | ||
1824 | axis_trap_pipe4 t1 ( | |
1825 | .mycid (cid), | |
1826 | .mytid (3'h1), | |
1827 | .PC_reg (pc_1_w) | |
1828 | ); | |
1829 | ||
1830 | wire [2:0] thread1_id=3'h1; | |
1831 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c4.t1.pc_fw2},`CPU.l2clk,3'h1,4); | |
1832 | dbuff_pc dbuff_pc_t1 ( | |
1833 | .cycle (cycle[63:0]), | |
1834 | .pc (`TOP.axis_trap_top.c4.t1.pc_fw2), | |
1835 | .clk (`CPU.l2clk), | |
1836 | .core (cid), | |
1837 | .thread (thread1_id) | |
1838 | ); | |
1839 | ||
1840 | always @(posedge axis_top.start_dumps) | |
1841 | begin // axis tbcall_region | |
1842 | $display("DMP4_1: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t1.addr,tb_top.axis_trap_top.c4.dbuff_pc_t1.ptr_0_cycle); | |
1843 | $axis_dumpmemh("c4_t1_pctrc.dat", | |
1844 | tb_top.axis_trap_top.c4.dbuff_pc_t1.DBUFF); | |
1845 | end | |
1846 | ||
1847 | ||
1848 | //---------------------------------------------------------- | |
1849 | // | |
1850 | // THREAD 2 | |
1851 | // | |
1852 | ||
1853 | ||
1854 | axis_trap_pipe4 t2 ( | |
1855 | .mycid (cid), | |
1856 | .mytid (3'h2), | |
1857 | .PC_reg (pc_2_w) | |
1858 | ); | |
1859 | ||
1860 | wire [2:0] thread2_id=3'h2; | |
1861 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c4.t2.pc_fw2},`CPU.l2clk,3'h2,4); | |
1862 | dbuff_pc dbuff_pc_t2 ( | |
1863 | .cycle (cycle[63:0]), | |
1864 | .pc (`TOP.axis_trap_top.c4.t2.pc_fw2), | |
1865 | .clk (`CPU.l2clk), | |
1866 | .core (cid), | |
1867 | .thread (thread2_id) | |
1868 | ); | |
1869 | ||
1870 | always @(posedge axis_top.start_dumps) | |
1871 | begin // axis tbcall_region | |
1872 | $display("DMP4_2: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t2.addr,tb_top.axis_trap_top.c4.dbuff_pc_t2.ptr_0_cycle); | |
1873 | $axis_dumpmemh("c4_t2_pctrc.dat", | |
1874 | tb_top.axis_trap_top.c4.dbuff_pc_t2.DBUFF); | |
1875 | end | |
1876 | ||
1877 | ||
1878 | //---------------------------------------------------------- | |
1879 | // | |
1880 | // THREAD 3 | |
1881 | // | |
1882 | ||
1883 | ||
1884 | axis_trap_pipe4 t3 ( | |
1885 | .mycid (cid), | |
1886 | .mytid (3'h3), | |
1887 | .PC_reg (pc_3_w) | |
1888 | ); | |
1889 | ||
1890 | wire [2:0] thread3_id=3'h3; | |
1891 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c4.t3.pc_fw2},`CPU.l2clk,3'h3,4); | |
1892 | dbuff_pc dbuff_pc_t3 ( | |
1893 | .cycle (cycle[63:0]), | |
1894 | .pc (`TOP.axis_trap_top.c4.t3.pc_fw2), | |
1895 | .clk (`CPU.l2clk), | |
1896 | .core (cid), | |
1897 | .thread (thread3_id) | |
1898 | ); | |
1899 | ||
1900 | always @(posedge axis_top.start_dumps) | |
1901 | begin // axis tbcall_region | |
1902 | $display("DMP4_3: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t3.addr,tb_top.axis_trap_top.c4.dbuff_pc_t3.ptr_0_cycle); | |
1903 | $axis_dumpmemh("c4_t3_pctrc.dat", | |
1904 | tb_top.axis_trap_top.c4.dbuff_pc_t3.DBUFF); | |
1905 | end | |
1906 | ||
1907 | ||
1908 | reg [5:0] trl0_tsa_wr_addr_r; | |
1909 | reg [1:0] tsd0_wr_gl_r; | |
1910 | reg [8:0] tsd0_wr_trap_type_r; | |
1911 | reg [47:2] tsd0_wr_tpc_r; | |
1912 | reg trl0_tsa_wr_en_r; | |
1913 | always @(posedge `CPU.l2clk) begin | |
1914 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc4.tlu.trl0_tsa_wr_addr; | |
1915 | tsd0_wr_gl_r <= tb_top.cpu.spc4.tlu.tsd0_wr_gl; | |
1916 | tsd0_wr_trap_type_r <= tb_top.cpu.spc4.tlu.tsd0_wr_trap_type[8:0]; | |
1917 | tsd0_wr_tpc_r <= tb_top.cpu.spc4.tlu.tsd0_wr_tpc; | |
1918 | trl0_tsa_wr_en_r <= tb_top.cpu.spc4.tlu.trl_tsa_wr_en[0]; | |
1919 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
1920 | begin // axis tbcall_region | |
1921 | $display("%t: TRAP WRITE: CORE 4: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
1922 | end | |
1923 | end | |
1924 | end | |
1925 | ||
1926 | //---------------------------------------------------------- | |
1927 | // | |
1928 | // THREAD 4 | |
1929 | // | |
1930 | ||
1931 | ||
1932 | axis_trap_pipe4 t4 ( | |
1933 | .mycid (cid), | |
1934 | .mytid (3'h4), | |
1935 | .PC_reg (pc_4_w) | |
1936 | ); | |
1937 | ||
1938 | wire [2:0] thread4_id=3'h4; | |
1939 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c4.t4.pc_fw2},`CPU.l2clk,3'h4,4); | |
1940 | dbuff_pc dbuff_pc_t4 ( | |
1941 | .cycle (cycle[63:0]), | |
1942 | .pc (`TOP.axis_trap_top.c4.t4.pc_fw2), | |
1943 | .clk (`CPU.l2clk), | |
1944 | .core (cid), | |
1945 | .thread (thread4_id) | |
1946 | ); | |
1947 | ||
1948 | always @(posedge axis_top.start_dumps) | |
1949 | begin // axis tbcall_region | |
1950 | $display("DMP4_4: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t4.addr,tb_top.axis_trap_top.c4.dbuff_pc_t4.ptr_0_cycle); | |
1951 | $axis_dumpmemh("c4_t4_pctrc.dat", | |
1952 | tb_top.axis_trap_top.c4.dbuff_pc_t4.DBUFF); | |
1953 | end | |
1954 | ||
1955 | ||
1956 | //---------------------------------------------------------- | |
1957 | // | |
1958 | // THREAD 5 | |
1959 | // | |
1960 | ||
1961 | ||
1962 | axis_trap_pipe4 t5 ( | |
1963 | .mycid (cid), | |
1964 | .mytid (3'h5), | |
1965 | .PC_reg (pc_5_w) | |
1966 | ); | |
1967 | ||
1968 | wire [2:0] thread5_id=3'h5; | |
1969 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c4.t5.pc_fw2},`CPU.l2clk,3'h5,4); | |
1970 | dbuff_pc dbuff_pc_t5 ( | |
1971 | .cycle (cycle[63:0]), | |
1972 | .pc (`TOP.axis_trap_top.c4.t5.pc_fw2), | |
1973 | .clk (`CPU.l2clk), | |
1974 | .core (cid), | |
1975 | .thread (thread5_id) | |
1976 | ); | |
1977 | ||
1978 | always @(posedge axis_top.start_dumps) | |
1979 | begin // axis tbcall_region | |
1980 | $display("DMP4_5: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t5.addr,tb_top.axis_trap_top.c4.dbuff_pc_t5.ptr_0_cycle); | |
1981 | $axis_dumpmemh("c4_t5_pctrc.dat", | |
1982 | tb_top.axis_trap_top.c4.dbuff_pc_t5.DBUFF); | |
1983 | end | |
1984 | ||
1985 | ||
1986 | //---------------------------------------------------------- | |
1987 | // | |
1988 | // THREAD 6 | |
1989 | // | |
1990 | ||
1991 | ||
1992 | axis_trap_pipe4 t6 ( | |
1993 | .mycid (cid), | |
1994 | .mytid (3'h6), | |
1995 | .PC_reg (pc_6_w) | |
1996 | ); | |
1997 | ||
1998 | wire [2:0] thread6_id=3'h6; | |
1999 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c4.t6.pc_fw2},`CPU.l2clk,3'h6,4); | |
2000 | dbuff_pc dbuff_pc_t6 ( | |
2001 | .cycle (cycle[63:0]), | |
2002 | .pc (`TOP.axis_trap_top.c4.t6.pc_fw2), | |
2003 | .clk (`CPU.l2clk), | |
2004 | .core (cid), | |
2005 | .thread (thread6_id) | |
2006 | ); | |
2007 | ||
2008 | always @(posedge axis_top.start_dumps) | |
2009 | begin // axis tbcall_region | |
2010 | $display("DMP4_6: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t6.addr,tb_top.axis_trap_top.c4.dbuff_pc_t6.ptr_0_cycle); | |
2011 | $axis_dumpmemh("c4_t6_pctrc.dat", | |
2012 | tb_top.axis_trap_top.c4.dbuff_pc_t6.DBUFF); | |
2013 | end | |
2014 | ||
2015 | ||
2016 | //---------------------------------------------------------- | |
2017 | // | |
2018 | // THREAD 7 | |
2019 | // | |
2020 | ||
2021 | ||
2022 | axis_trap_pipe4 t7 ( | |
2023 | .mycid (cid), | |
2024 | .mytid (3'h7), | |
2025 | .PC_reg (pc_7_w) | |
2026 | ); | |
2027 | ||
2028 | wire [2:0] thread7_id=3'h7; | |
2029 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c4.t7.pc_fw2},`CPU.l2clk,3'h7,4); | |
2030 | dbuff_pc dbuff_pc_t7 ( | |
2031 | .cycle (cycle[63:0]), | |
2032 | .pc (`TOP.axis_trap_top.c4.t7.pc_fw2), | |
2033 | .clk (`CPU.l2clk), | |
2034 | .core (cid), | |
2035 | .thread (thread7_id) | |
2036 | ); | |
2037 | ||
2038 | always @(posedge axis_top.start_dumps) | |
2039 | begin // axis tbcall_region | |
2040 | $display("DMP4_7: %h %h \n",tb_top.axis_trap_top.c4.dbuff_pc_t7.addr,tb_top.axis_trap_top.c4.dbuff_pc_t7.ptr_0_cycle); | |
2041 | $axis_dumpmemh("c4_t7_pctrc.dat", | |
2042 | tb_top.axis_trap_top.c4.dbuff_pc_t7.DBUFF); | |
2043 | end | |
2044 | ||
2045 | ||
2046 | reg [5:0] trl1_tsa_wr_addr_r; | |
2047 | reg [1:0] tsd1_wr_gl_r; | |
2048 | reg [8:0] tsd1_wr_trap_type_r; | |
2049 | reg [47:2] tsd1_wr_tpc_r; | |
2050 | reg trl1_tsa_wr_en_r; | |
2051 | always @(posedge `CPU.l2clk) begin | |
2052 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc4.tlu.trl1_tsa_wr_addr; | |
2053 | tsd1_wr_gl_r <= tb_top.cpu.spc4.tlu.tsd1_wr_gl; | |
2054 | tsd1_wr_trap_type_r <= tb_top.cpu.spc4.tlu.tsd1_wr_trap_type[8:0]; | |
2055 | tsd1_wr_tpc_r <= tb_top.cpu.spc4.tlu.tsd1_wr_tpc; | |
2056 | trl1_tsa_wr_en_r <= tb_top.cpu.spc4.tlu.trl_tsa_wr_en[1]; | |
2057 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
2058 | begin // axis tbcall_region | |
2059 | $display("%t: TRAP WRITE: CORE 4: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
2060 | end | |
2061 | end | |
2062 | end | |
2063 | ||
2064 | //---------------------------------------------------------- | |
2065 | ||
2066 | `ifndef GATESIM | |
2067 | ||
2068 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
2069 | // But some of the error checkers need this signal without the qualification | |
2070 | // of icache errors | |
2071 | wire [7:0] select_pc_b_with_errors; | |
2072 | ||
2073 | assign select_pc_b_with_errors = | |
2074 | {{4 {~`SPC4.dec_flush_b[1]}}, {4 {~`SPC4.dec_flush_b[0]}}} & | |
2075 | ||
2076 | {~(`SPC4.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
2077 | {4 {`SPC4.tlu.fls1.idl_req_in}}), | |
2078 | ~(`SPC4.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
2079 | {4 {`SPC4.tlu.fls0.idl_req_in}})} & | |
2080 | {`SPC4.tlu.fls1.tid_dec_valid_b[3:0], | |
2081 | `SPC4.tlu.fls0.tid_dec_valid_b[3:0]}; | |
2082 | ||
2083 | //------------------------------------ | |
2084 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
2085 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
2086 | wire [7:0] select_pc_b; | |
2087 | ||
2088 | assign select_pc_b = | |
2089 | select_pc_b_with_errors[7:0] & | |
2090 | {{4 {~`SPC4.tlu.fls1.ic_err_w_in}}, {4 {~`SPC4.tlu.fls0.ic_err_w_in}}}; | |
2091 | ||
2092 | //------------------------------------ | |
2093 | // ASI & Trap State machines | |
2094 | always @(posedge `SPC4.gclk) begin // { | |
2095 | ||
2096 | // pc_0_e[47:0] <= `SPC4.ifu_pc_d0[47:0]; | |
2097 | // pc_1_e[47:0] <= `SPC4.ifu_pc_d1[47:0]; | |
2098 | pc_0_e[47:0] <= {`SPC4.tlu_pc_0_d[47:2], 2'b00}; | |
2099 | pc_1_e[47:0] <= {`SPC4.tlu_pc_1_d[47:2], 2'b00}; | |
2100 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
2101 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
2102 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
2103 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
2104 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
2105 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
2106 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
2107 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
2108 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
2109 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
2110 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
2111 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
2112 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
2113 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
2114 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
2115 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
2116 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
2117 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
2118 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
2119 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
2120 | end | |
2121 | ||
2122 | `endif | |
2123 | `endif //AXIS_TL | |
2124 | ||
2125 | //---------------------------------------------------------- | |
2126 | endmodule | |
2127 | ||
2128 | `endif | |
2129 | ||
2130 | `ifdef CORE_5 | |
2131 | ||
2132 | module axis_trap_core5 ( | |
2133 | cid, | |
2134 | pc_dmp_sz, | |
2135 | ); | |
2136 | ||
2137 | input [2:0] cid; | |
2138 | input [21:0] pc_dmp_sz; | |
2139 | ||
2140 | `ifdef AXIS_TL | |
2141 | `ifndef GATESIM | |
2142 | reg [47:0] pc_0_e; | |
2143 | reg [47:0] pc_1_e; | |
2144 | reg [47:0] pc_0_m; | |
2145 | reg [47:0] pc_1_m; | |
2146 | reg [47:0] pc_0_b; | |
2147 | reg [47:0] pc_1_b; | |
2148 | reg [47:0] pc_0_w; | |
2149 | reg [47:0] pc_1_w; | |
2150 | reg [47:0] pc_2_w; | |
2151 | reg [47:0] pc_3_w; | |
2152 | reg [47:0] pc_4_w; | |
2153 | reg [47:0] pc_5_w; | |
2154 | reg [47:0] pc_6_w; | |
2155 | reg [47:0] pc_7_w; | |
2156 | `endif | |
2157 | ||
2158 | //---------------------------------------------------------- | |
2159 | reg [63:0] cycle; | |
2160 | initial cycle = 64'b0; | |
2161 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
2162 | if (`CPU.tcu_aclk) cycle = 0; | |
2163 | else cycle = cycle + 64'b1; | |
2164 | end | |
2165 | ||
2166 | //*******************************************************************************************************/ | |
2167 | reg [76:0] sig_reg_0; | |
2168 | reg [76:0] sig_reg_1; | |
2169 | reg [76:0] sig_reg_2; | |
2170 | reg [76:0] sig_reg_3; | |
2171 | reg [63:0] kern_cnt; | |
2172 | reg [47:0] pc_0_saved; | |
2173 | ||
2174 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
2175 | always @(negedge `CPU.tcu_aclk) begin | |
2176 | begin // axis tbcall_region | |
2177 | $display("%t: dbg rst detected by repeatability_check", $time); | |
2178 | end | |
2179 | end | |
2180 | ||
2181 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
2182 | pc_0_saved <= pc_0_w; | |
2183 | if (`CPU.tcu_aclk) begin | |
2184 | sig_reg_1 <= 0; | |
2185 | sig_reg_2 <= 0; | |
2186 | sig_reg_3 <= 0; | |
2187 | sig_reg_0 <= 0; | |
2188 | kern_cnt <= 0; | |
2189 | end | |
2190 | else if (!`CPU.tcu_aclk) begin | |
2191 | if (tb_top.cpu.spc5.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc5.exu0.irf.wr_addr_p0,tb_top.cpu.spc5.exu0.irf.wr_data_p0}; | |
2192 | if (tb_top.cpu.spc5.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc5.exu0.irf.wr_addr_p1,tb_top.cpu.spc5.exu0.irf.wr_data_p1}; | |
2193 | if (tb_top.cpu.spc5.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc5.exu1.irf.wr_addr_p0,tb_top.cpu.spc5.exu1.irf.wr_data_p0}; | |
2194 | if (tb_top.cpu.spc5.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc5.exu1.irf.wr_addr_p1,tb_top.cpu.spc5.exu1.irf.wr_data_p1}; | |
2195 | kern_cnt <= kern_cnt + 1; | |
2196 | end | |
2197 | ||
2198 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
2199 | $display("%t: repeatability_check: core 5, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
2200 | end | |
2201 | ||
2202 | end | |
2203 | ||
2204 | //************************************************************************************************** | |
2205 | //---------------------------------------------------------- | |
2206 | ||
2207 | //---------------------------------------------------------- | |
2208 | // | |
2209 | // THREAD 0 | |
2210 | // | |
2211 | ||
2212 | ||
2213 | axis_trap_pipe5 t0 ( | |
2214 | .mycid (cid), | |
2215 | .mytid (3'h0), | |
2216 | .PC_reg (pc_0_w) | |
2217 | ); | |
2218 | ||
2219 | wire [2:0] thread0_id=3'h0; | |
2220 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c5.t0.pc_fw2},`CPU.l2clk,3'h0,5); | |
2221 | dbuff_pc dbuff_pc_t0 ( | |
2222 | .cycle (cycle[63:0]), | |
2223 | .pc (`TOP.axis_trap_top.c5.t0.pc_fw2), | |
2224 | .clk (`CPU.l2clk), | |
2225 | .core (cid), | |
2226 | .thread (thread0_id) | |
2227 | ); | |
2228 | ||
2229 | always @(posedge axis_top.start_dumps) | |
2230 | begin // axis tbcall_region | |
2231 | $display("DMP5_0: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t0.addr,tb_top.axis_trap_top.c5.dbuff_pc_t0.ptr_0_cycle); | |
2232 | $axis_dumpmemh("c5_t0_pctrc.dat", | |
2233 | tb_top.axis_trap_top.c5.dbuff_pc_t0.DBUFF); | |
2234 | end | |
2235 | ||
2236 | ||
2237 | //---------------------------------------------------------- | |
2238 | // | |
2239 | // THREAD 1 | |
2240 | // | |
2241 | ||
2242 | ||
2243 | axis_trap_pipe5 t1 ( | |
2244 | .mycid (cid), | |
2245 | .mytid (3'h1), | |
2246 | .PC_reg (pc_1_w) | |
2247 | ); | |
2248 | ||
2249 | wire [2:0] thread1_id=3'h1; | |
2250 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c5.t1.pc_fw2},`CPU.l2clk,3'h1,5); | |
2251 | dbuff_pc dbuff_pc_t1 ( | |
2252 | .cycle (cycle[63:0]), | |
2253 | .pc (`TOP.axis_trap_top.c5.t1.pc_fw2), | |
2254 | .clk (`CPU.l2clk), | |
2255 | .core (cid), | |
2256 | .thread (thread1_id) | |
2257 | ); | |
2258 | ||
2259 | always @(posedge axis_top.start_dumps) | |
2260 | begin // axis tbcall_region | |
2261 | $display("DMP5_1: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t1.addr,tb_top.axis_trap_top.c5.dbuff_pc_t1.ptr_0_cycle); | |
2262 | $axis_dumpmemh("c5_t1_pctrc.dat", | |
2263 | tb_top.axis_trap_top.c5.dbuff_pc_t1.DBUFF); | |
2264 | end | |
2265 | ||
2266 | ||
2267 | //---------------------------------------------------------- | |
2268 | // | |
2269 | // THREAD 2 | |
2270 | // | |
2271 | ||
2272 | ||
2273 | axis_trap_pipe5 t2 ( | |
2274 | .mycid (cid), | |
2275 | .mytid (3'h2), | |
2276 | .PC_reg (pc_2_w) | |
2277 | ); | |
2278 | ||
2279 | wire [2:0] thread2_id=3'h2; | |
2280 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c5.t2.pc_fw2},`CPU.l2clk,3'h2,5); | |
2281 | dbuff_pc dbuff_pc_t2 ( | |
2282 | .cycle (cycle[63:0]), | |
2283 | .pc (`TOP.axis_trap_top.c5.t2.pc_fw2), | |
2284 | .clk (`CPU.l2clk), | |
2285 | .core (cid), | |
2286 | .thread (thread2_id) | |
2287 | ); | |
2288 | ||
2289 | always @(posedge axis_top.start_dumps) | |
2290 | begin // axis tbcall_region | |
2291 | $display("DMP5_2: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t2.addr,tb_top.axis_trap_top.c5.dbuff_pc_t2.ptr_0_cycle); | |
2292 | $axis_dumpmemh("c5_t2_pctrc.dat", | |
2293 | tb_top.axis_trap_top.c5.dbuff_pc_t2.DBUFF); | |
2294 | end | |
2295 | ||
2296 | ||
2297 | //---------------------------------------------------------- | |
2298 | // | |
2299 | // THREAD 3 | |
2300 | // | |
2301 | ||
2302 | ||
2303 | axis_trap_pipe5 t3 ( | |
2304 | .mycid (cid), | |
2305 | .mytid (3'h3), | |
2306 | .PC_reg (pc_3_w) | |
2307 | ); | |
2308 | ||
2309 | wire [2:0] thread3_id=3'h3; | |
2310 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c5.t3.pc_fw2},`CPU.l2clk,3'h3,5); | |
2311 | dbuff_pc dbuff_pc_t3 ( | |
2312 | .cycle (cycle[63:0]), | |
2313 | .pc (`TOP.axis_trap_top.c5.t3.pc_fw2), | |
2314 | .clk (`CPU.l2clk), | |
2315 | .core (cid), | |
2316 | .thread (thread3_id) | |
2317 | ); | |
2318 | ||
2319 | always @(posedge axis_top.start_dumps) | |
2320 | begin // axis tbcall_region | |
2321 | $display("DMP5_3: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t3.addr,tb_top.axis_trap_top.c5.dbuff_pc_t3.ptr_0_cycle); | |
2322 | $axis_dumpmemh("c5_t3_pctrc.dat", | |
2323 | tb_top.axis_trap_top.c5.dbuff_pc_t3.DBUFF); | |
2324 | end | |
2325 | ||
2326 | ||
2327 | reg [5:0] trl0_tsa_wr_addr_r; | |
2328 | reg [1:0] tsd0_wr_gl_r; | |
2329 | reg [8:0] tsd0_wr_trap_type_r; | |
2330 | reg [47:2] tsd0_wr_tpc_r; | |
2331 | reg trl0_tsa_wr_en_r; | |
2332 | always @(posedge `CPU.l2clk) begin | |
2333 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc5.tlu.trl0_tsa_wr_addr; | |
2334 | tsd0_wr_gl_r <= tb_top.cpu.spc5.tlu.tsd0_wr_gl; | |
2335 | tsd0_wr_trap_type_r <= tb_top.cpu.spc5.tlu.tsd0_wr_trap_type[8:0]; | |
2336 | tsd0_wr_tpc_r <= tb_top.cpu.spc5.tlu.tsd0_wr_tpc; | |
2337 | trl0_tsa_wr_en_r <= tb_top.cpu.spc5.tlu.trl_tsa_wr_en[0]; | |
2338 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
2339 | begin // axis tbcall_region | |
2340 | $display("%t: TRAP WRITE: CORE 5: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
2341 | end | |
2342 | end | |
2343 | end | |
2344 | ||
2345 | //---------------------------------------------------------- | |
2346 | // | |
2347 | // THREAD 4 | |
2348 | // | |
2349 | ||
2350 | ||
2351 | axis_trap_pipe5 t4 ( | |
2352 | .mycid (cid), | |
2353 | .mytid (3'h4), | |
2354 | .PC_reg (pc_4_w) | |
2355 | ); | |
2356 | ||
2357 | wire [2:0] thread4_id=3'h4; | |
2358 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c5.t4.pc_fw2},`CPU.l2clk,3'h4,5); | |
2359 | dbuff_pc dbuff_pc_t4 ( | |
2360 | .cycle (cycle[63:0]), | |
2361 | .pc (`TOP.axis_trap_top.c5.t4.pc_fw2), | |
2362 | .clk (`CPU.l2clk), | |
2363 | .core (cid), | |
2364 | .thread (thread4_id) | |
2365 | ); | |
2366 | ||
2367 | always @(posedge axis_top.start_dumps) | |
2368 | begin // axis tbcall_region | |
2369 | $display("DMP5_4: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t4.addr,tb_top.axis_trap_top.c5.dbuff_pc_t4.ptr_0_cycle); | |
2370 | $axis_dumpmemh("c5_t4_pctrc.dat", | |
2371 | tb_top.axis_trap_top.c5.dbuff_pc_t4.DBUFF); | |
2372 | end | |
2373 | ||
2374 | ||
2375 | //---------------------------------------------------------- | |
2376 | // | |
2377 | // THREAD 5 | |
2378 | // | |
2379 | ||
2380 | ||
2381 | axis_trap_pipe5 t5 ( | |
2382 | .mycid (cid), | |
2383 | .mytid (3'h5), | |
2384 | .PC_reg (pc_5_w) | |
2385 | ); | |
2386 | ||
2387 | wire [2:0] thread5_id=3'h5; | |
2388 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c5.t5.pc_fw2},`CPU.l2clk,3'h5,5); | |
2389 | dbuff_pc dbuff_pc_t5 ( | |
2390 | .cycle (cycle[63:0]), | |
2391 | .pc (`TOP.axis_trap_top.c5.t5.pc_fw2), | |
2392 | .clk (`CPU.l2clk), | |
2393 | .core (cid), | |
2394 | .thread (thread5_id) | |
2395 | ); | |
2396 | ||
2397 | always @(posedge axis_top.start_dumps) | |
2398 | begin // axis tbcall_region | |
2399 | $display("DMP5_5: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t5.addr,tb_top.axis_trap_top.c5.dbuff_pc_t5.ptr_0_cycle); | |
2400 | $axis_dumpmemh("c5_t5_pctrc.dat", | |
2401 | tb_top.axis_trap_top.c5.dbuff_pc_t5.DBUFF); | |
2402 | end | |
2403 | ||
2404 | ||
2405 | //---------------------------------------------------------- | |
2406 | // | |
2407 | // THREAD 6 | |
2408 | // | |
2409 | ||
2410 | ||
2411 | axis_trap_pipe5 t6 ( | |
2412 | .mycid (cid), | |
2413 | .mytid (3'h6), | |
2414 | .PC_reg (pc_6_w) | |
2415 | ); | |
2416 | ||
2417 | wire [2:0] thread6_id=3'h6; | |
2418 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c5.t6.pc_fw2},`CPU.l2clk,3'h6,5); | |
2419 | dbuff_pc dbuff_pc_t6 ( | |
2420 | .cycle (cycle[63:0]), | |
2421 | .pc (`TOP.axis_trap_top.c5.t6.pc_fw2), | |
2422 | .clk (`CPU.l2clk), | |
2423 | .core (cid), | |
2424 | .thread (thread6_id) | |
2425 | ); | |
2426 | ||
2427 | always @(posedge axis_top.start_dumps) | |
2428 | begin // axis tbcall_region | |
2429 | $display("DMP5_6: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t6.addr,tb_top.axis_trap_top.c5.dbuff_pc_t6.ptr_0_cycle); | |
2430 | $axis_dumpmemh("c5_t6_pctrc.dat", | |
2431 | tb_top.axis_trap_top.c5.dbuff_pc_t6.DBUFF); | |
2432 | end | |
2433 | ||
2434 | ||
2435 | //---------------------------------------------------------- | |
2436 | // | |
2437 | // THREAD 7 | |
2438 | // | |
2439 | ||
2440 | ||
2441 | axis_trap_pipe5 t7 ( | |
2442 | .mycid (cid), | |
2443 | .mytid (3'h7), | |
2444 | .PC_reg (pc_7_w) | |
2445 | ); | |
2446 | ||
2447 | wire [2:0] thread7_id=3'h7; | |
2448 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c5.t7.pc_fw2},`CPU.l2clk,3'h7,5); | |
2449 | dbuff_pc dbuff_pc_t7 ( | |
2450 | .cycle (cycle[63:0]), | |
2451 | .pc (`TOP.axis_trap_top.c5.t7.pc_fw2), | |
2452 | .clk (`CPU.l2clk), | |
2453 | .core (cid), | |
2454 | .thread (thread7_id) | |
2455 | ); | |
2456 | ||
2457 | always @(posedge axis_top.start_dumps) | |
2458 | begin // axis tbcall_region | |
2459 | $display("DMP5_7: %h %h \n",tb_top.axis_trap_top.c5.dbuff_pc_t7.addr,tb_top.axis_trap_top.c5.dbuff_pc_t7.ptr_0_cycle); | |
2460 | $axis_dumpmemh("c5_t7_pctrc.dat", | |
2461 | tb_top.axis_trap_top.c5.dbuff_pc_t7.DBUFF); | |
2462 | end | |
2463 | ||
2464 | ||
2465 | reg [5:0] trl1_tsa_wr_addr_r; | |
2466 | reg [1:0] tsd1_wr_gl_r; | |
2467 | reg [8:0] tsd1_wr_trap_type_r; | |
2468 | reg [47:2] tsd1_wr_tpc_r; | |
2469 | reg trl1_tsa_wr_en_r; | |
2470 | always @(posedge `CPU.l2clk) begin | |
2471 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc5.tlu.trl1_tsa_wr_addr; | |
2472 | tsd1_wr_gl_r <= tb_top.cpu.spc5.tlu.tsd1_wr_gl; | |
2473 | tsd1_wr_trap_type_r <= tb_top.cpu.spc5.tlu.tsd1_wr_trap_type[8:0]; | |
2474 | tsd1_wr_tpc_r <= tb_top.cpu.spc5.tlu.tsd1_wr_tpc; | |
2475 | trl1_tsa_wr_en_r <= tb_top.cpu.spc5.tlu.trl_tsa_wr_en[1]; | |
2476 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
2477 | begin // axis tbcall_region | |
2478 | $display("%t: TRAP WRITE: CORE 5: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
2479 | end | |
2480 | end | |
2481 | end | |
2482 | ||
2483 | //---------------------------------------------------------- | |
2484 | ||
2485 | `ifndef GATESIM | |
2486 | ||
2487 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
2488 | // But some of the error checkers need this signal without the qualification | |
2489 | // of icache errors | |
2490 | wire [7:0] select_pc_b_with_errors; | |
2491 | ||
2492 | assign select_pc_b_with_errors = | |
2493 | {{4 {~`SPC5.dec_flush_b[1]}}, {4 {~`SPC5.dec_flush_b[0]}}} & | |
2494 | ||
2495 | {~(`SPC5.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
2496 | {4 {`SPC5.tlu.fls1.idl_req_in}}), | |
2497 | ~(`SPC5.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
2498 | {4 {`SPC5.tlu.fls0.idl_req_in}})} & | |
2499 | {`SPC5.tlu.fls1.tid_dec_valid_b[3:0], | |
2500 | `SPC5.tlu.fls0.tid_dec_valid_b[3:0]}; | |
2501 | ||
2502 | //------------------------------------ | |
2503 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
2504 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
2505 | wire [7:0] select_pc_b; | |
2506 | ||
2507 | assign select_pc_b = | |
2508 | select_pc_b_with_errors[7:0] & | |
2509 | {{4 {~`SPC5.tlu.fls1.ic_err_w_in}}, {4 {~`SPC5.tlu.fls0.ic_err_w_in}}}; | |
2510 | ||
2511 | //------------------------------------ | |
2512 | // ASI & Trap State machines | |
2513 | always @(posedge `SPC5.gclk) begin // { | |
2514 | ||
2515 | // pc_0_e[47:0] <= `SPC5.ifu_pc_d0[47:0]; | |
2516 | // pc_1_e[47:0] <= `SPC5.ifu_pc_d1[47:0]; | |
2517 | pc_0_e[47:0] <= {`SPC5.tlu_pc_0_d[47:2], 2'b00}; | |
2518 | pc_1_e[47:0] <= {`SPC5.tlu_pc_1_d[47:2], 2'b00}; | |
2519 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
2520 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
2521 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
2522 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
2523 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
2524 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
2525 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
2526 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
2527 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
2528 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
2529 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
2530 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
2531 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
2532 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
2533 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
2534 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
2535 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
2536 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
2537 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
2538 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
2539 | end | |
2540 | ||
2541 | `endif | |
2542 | `endif //AXIS_TL | |
2543 | ||
2544 | //---------------------------------------------------------- | |
2545 | endmodule | |
2546 | ||
2547 | `endif | |
2548 | ||
2549 | `ifdef CORE_6 | |
2550 | ||
2551 | module axis_trap_core6 ( | |
2552 | cid, | |
2553 | pc_dmp_sz, | |
2554 | ); | |
2555 | ||
2556 | input [2:0] cid; | |
2557 | input [21:0] pc_dmp_sz; | |
2558 | ||
2559 | `ifdef AXIS_TL | |
2560 | `ifndef GATESIM | |
2561 | reg [47:0] pc_0_e; | |
2562 | reg [47:0] pc_1_e; | |
2563 | reg [47:0] pc_0_m; | |
2564 | reg [47:0] pc_1_m; | |
2565 | reg [47:0] pc_0_b; | |
2566 | reg [47:0] pc_1_b; | |
2567 | reg [47:0] pc_0_w; | |
2568 | reg [47:0] pc_1_w; | |
2569 | reg [47:0] pc_2_w; | |
2570 | reg [47:0] pc_3_w; | |
2571 | reg [47:0] pc_4_w; | |
2572 | reg [47:0] pc_5_w; | |
2573 | reg [47:0] pc_6_w; | |
2574 | reg [47:0] pc_7_w; | |
2575 | `endif | |
2576 | ||
2577 | //---------------------------------------------------------- | |
2578 | reg [63:0] cycle; | |
2579 | initial cycle = 64'b0; | |
2580 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
2581 | if (`CPU.tcu_aclk) cycle = 0; | |
2582 | else cycle = cycle + 64'b1; | |
2583 | end | |
2584 | ||
2585 | //*******************************************************************************************************/ | |
2586 | reg [76:0] sig_reg_0; | |
2587 | reg [76:0] sig_reg_1; | |
2588 | reg [76:0] sig_reg_2; | |
2589 | reg [76:0] sig_reg_3; | |
2590 | reg [63:0] kern_cnt; | |
2591 | reg [47:0] pc_0_saved; | |
2592 | ||
2593 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
2594 | always @(negedge `CPU.tcu_aclk) begin | |
2595 | begin // axis tbcall_region | |
2596 | $display("%t: dbg rst detected by repeatability_check", $time); | |
2597 | end | |
2598 | end | |
2599 | ||
2600 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
2601 | pc_0_saved <= pc_0_w; | |
2602 | if (`CPU.tcu_aclk) begin | |
2603 | sig_reg_1 <= 0; | |
2604 | sig_reg_2 <= 0; | |
2605 | sig_reg_3 <= 0; | |
2606 | sig_reg_0 <= 0; | |
2607 | kern_cnt <= 0; | |
2608 | end | |
2609 | else if (!`CPU.tcu_aclk) begin | |
2610 | if (tb_top.cpu.spc6.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc6.exu0.irf.wr_addr_p0,tb_top.cpu.spc6.exu0.irf.wr_data_p0}; | |
2611 | if (tb_top.cpu.spc6.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc6.exu0.irf.wr_addr_p1,tb_top.cpu.spc6.exu0.irf.wr_data_p1}; | |
2612 | if (tb_top.cpu.spc6.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc6.exu1.irf.wr_addr_p0,tb_top.cpu.spc6.exu1.irf.wr_data_p0}; | |
2613 | if (tb_top.cpu.spc6.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc6.exu1.irf.wr_addr_p1,tb_top.cpu.spc6.exu1.irf.wr_data_p1}; | |
2614 | kern_cnt <= kern_cnt + 1; | |
2615 | end | |
2616 | ||
2617 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
2618 | $display("%t: repeatability_check: core 6, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
2619 | end | |
2620 | ||
2621 | end | |
2622 | ||
2623 | //************************************************************************************************** | |
2624 | //---------------------------------------------------------- | |
2625 | ||
2626 | //---------------------------------------------------------- | |
2627 | // | |
2628 | // THREAD 0 | |
2629 | // | |
2630 | ||
2631 | ||
2632 | axis_trap_pipe6 t0 ( | |
2633 | .mycid (cid), | |
2634 | .mytid (3'h0), | |
2635 | .PC_reg (pc_0_w) | |
2636 | ); | |
2637 | ||
2638 | wire [2:0] thread0_id=3'h0; | |
2639 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c6.t0.pc_fw2},`CPU.l2clk,3'h0,6); | |
2640 | dbuff_pc dbuff_pc_t0 ( | |
2641 | .cycle (cycle[63:0]), | |
2642 | .pc (`TOP.axis_trap_top.c6.t0.pc_fw2), | |
2643 | .clk (`CPU.l2clk), | |
2644 | .core (cid), | |
2645 | .thread (thread0_id) | |
2646 | ); | |
2647 | ||
2648 | always @(posedge axis_top.start_dumps) | |
2649 | begin // axis tbcall_region | |
2650 | $display("DMP6_0: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t0.addr,tb_top.axis_trap_top.c6.dbuff_pc_t0.ptr_0_cycle); | |
2651 | $axis_dumpmemh("c6_t0_pctrc.dat", | |
2652 | tb_top.axis_trap_top.c6.dbuff_pc_t0.DBUFF); | |
2653 | end | |
2654 | ||
2655 | ||
2656 | //---------------------------------------------------------- | |
2657 | // | |
2658 | // THREAD 1 | |
2659 | // | |
2660 | ||
2661 | ||
2662 | axis_trap_pipe6 t1 ( | |
2663 | .mycid (cid), | |
2664 | .mytid (3'h1), | |
2665 | .PC_reg (pc_1_w) | |
2666 | ); | |
2667 | ||
2668 | wire [2:0] thread1_id=3'h1; | |
2669 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c6.t1.pc_fw2},`CPU.l2clk,3'h1,6); | |
2670 | dbuff_pc dbuff_pc_t1 ( | |
2671 | .cycle (cycle[63:0]), | |
2672 | .pc (`TOP.axis_trap_top.c6.t1.pc_fw2), | |
2673 | .clk (`CPU.l2clk), | |
2674 | .core (cid), | |
2675 | .thread (thread1_id) | |
2676 | ); | |
2677 | ||
2678 | always @(posedge axis_top.start_dumps) | |
2679 | begin // axis tbcall_region | |
2680 | $display("DMP6_1: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t1.addr,tb_top.axis_trap_top.c6.dbuff_pc_t1.ptr_0_cycle); | |
2681 | $axis_dumpmemh("c6_t1_pctrc.dat", | |
2682 | tb_top.axis_trap_top.c6.dbuff_pc_t1.DBUFF); | |
2683 | end | |
2684 | ||
2685 | ||
2686 | //---------------------------------------------------------- | |
2687 | // | |
2688 | // THREAD 2 | |
2689 | // | |
2690 | ||
2691 | ||
2692 | axis_trap_pipe6 t2 ( | |
2693 | .mycid (cid), | |
2694 | .mytid (3'h2), | |
2695 | .PC_reg (pc_2_w) | |
2696 | ); | |
2697 | ||
2698 | wire [2:0] thread2_id=3'h2; | |
2699 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c6.t2.pc_fw2},`CPU.l2clk,3'h2,6); | |
2700 | dbuff_pc dbuff_pc_t2 ( | |
2701 | .cycle (cycle[63:0]), | |
2702 | .pc (`TOP.axis_trap_top.c6.t2.pc_fw2), | |
2703 | .clk (`CPU.l2clk), | |
2704 | .core (cid), | |
2705 | .thread (thread2_id) | |
2706 | ); | |
2707 | ||
2708 | always @(posedge axis_top.start_dumps) | |
2709 | begin // axis tbcall_region | |
2710 | $display("DMP6_2: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t2.addr,tb_top.axis_trap_top.c6.dbuff_pc_t2.ptr_0_cycle); | |
2711 | $axis_dumpmemh("c6_t2_pctrc.dat", | |
2712 | tb_top.axis_trap_top.c6.dbuff_pc_t2.DBUFF); | |
2713 | end | |
2714 | ||
2715 | ||
2716 | //---------------------------------------------------------- | |
2717 | // | |
2718 | // THREAD 3 | |
2719 | // | |
2720 | ||
2721 | ||
2722 | axis_trap_pipe6 t3 ( | |
2723 | .mycid (cid), | |
2724 | .mytid (3'h3), | |
2725 | .PC_reg (pc_3_w) | |
2726 | ); | |
2727 | ||
2728 | wire [2:0] thread3_id=3'h3; | |
2729 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c6.t3.pc_fw2},`CPU.l2clk,3'h3,6); | |
2730 | dbuff_pc dbuff_pc_t3 ( | |
2731 | .cycle (cycle[63:0]), | |
2732 | .pc (`TOP.axis_trap_top.c6.t3.pc_fw2), | |
2733 | .clk (`CPU.l2clk), | |
2734 | .core (cid), | |
2735 | .thread (thread3_id) | |
2736 | ); | |
2737 | ||
2738 | always @(posedge axis_top.start_dumps) | |
2739 | begin // axis tbcall_region | |
2740 | $display("DMP6_3: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t3.addr,tb_top.axis_trap_top.c6.dbuff_pc_t3.ptr_0_cycle); | |
2741 | $axis_dumpmemh("c6_t3_pctrc.dat", | |
2742 | tb_top.axis_trap_top.c6.dbuff_pc_t3.DBUFF); | |
2743 | end | |
2744 | ||
2745 | ||
2746 | reg [5:0] trl0_tsa_wr_addr_r; | |
2747 | reg [1:0] tsd0_wr_gl_r; | |
2748 | reg [8:0] tsd0_wr_trap_type_r; | |
2749 | reg [47:2] tsd0_wr_tpc_r; | |
2750 | reg trl0_tsa_wr_en_r; | |
2751 | always @(posedge `CPU.l2clk) begin | |
2752 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc6.tlu.trl0_tsa_wr_addr; | |
2753 | tsd0_wr_gl_r <= tb_top.cpu.spc6.tlu.tsd0_wr_gl; | |
2754 | tsd0_wr_trap_type_r <= tb_top.cpu.spc6.tlu.tsd0_wr_trap_type[8:0]; | |
2755 | tsd0_wr_tpc_r <= tb_top.cpu.spc6.tlu.tsd0_wr_tpc; | |
2756 | trl0_tsa_wr_en_r <= tb_top.cpu.spc6.tlu.trl_tsa_wr_en[0]; | |
2757 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
2758 | begin // axis tbcall_region | |
2759 | $display("%t: TRAP WRITE: CORE 6: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
2760 | end | |
2761 | end | |
2762 | end | |
2763 | ||
2764 | //---------------------------------------------------------- | |
2765 | // | |
2766 | // THREAD 4 | |
2767 | // | |
2768 | ||
2769 | ||
2770 | axis_trap_pipe6 t4 ( | |
2771 | .mycid (cid), | |
2772 | .mytid (3'h4), | |
2773 | .PC_reg (pc_4_w) | |
2774 | ); | |
2775 | ||
2776 | wire [2:0] thread4_id=3'h4; | |
2777 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c6.t4.pc_fw2},`CPU.l2clk,3'h4,6); | |
2778 | dbuff_pc dbuff_pc_t4 ( | |
2779 | .cycle (cycle[63:0]), | |
2780 | .pc (`TOP.axis_trap_top.c6.t4.pc_fw2), | |
2781 | .clk (`CPU.l2clk), | |
2782 | .core (cid), | |
2783 | .thread (thread4_id) | |
2784 | ); | |
2785 | ||
2786 | always @(posedge axis_top.start_dumps) | |
2787 | begin // axis tbcall_region | |
2788 | $display("DMP6_4: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t4.addr,tb_top.axis_trap_top.c6.dbuff_pc_t4.ptr_0_cycle); | |
2789 | $axis_dumpmemh("c6_t4_pctrc.dat", | |
2790 | tb_top.axis_trap_top.c6.dbuff_pc_t4.DBUFF); | |
2791 | end | |
2792 | ||
2793 | ||
2794 | //---------------------------------------------------------- | |
2795 | // | |
2796 | // THREAD 5 | |
2797 | // | |
2798 | ||
2799 | ||
2800 | axis_trap_pipe6 t5 ( | |
2801 | .mycid (cid), | |
2802 | .mytid (3'h5), | |
2803 | .PC_reg (pc_5_w) | |
2804 | ); | |
2805 | ||
2806 | wire [2:0] thread5_id=3'h5; | |
2807 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c6.t5.pc_fw2},`CPU.l2clk,3'h5,6); | |
2808 | dbuff_pc dbuff_pc_t5 ( | |
2809 | .cycle (cycle[63:0]), | |
2810 | .pc (`TOP.axis_trap_top.c6.t5.pc_fw2), | |
2811 | .clk (`CPU.l2clk), | |
2812 | .core (cid), | |
2813 | .thread (thread5_id) | |
2814 | ); | |
2815 | ||
2816 | always @(posedge axis_top.start_dumps) | |
2817 | begin // axis tbcall_region | |
2818 | $display("DMP6_5: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t5.addr,tb_top.axis_trap_top.c6.dbuff_pc_t5.ptr_0_cycle); | |
2819 | $axis_dumpmemh("c6_t5_pctrc.dat", | |
2820 | tb_top.axis_trap_top.c6.dbuff_pc_t5.DBUFF); | |
2821 | end | |
2822 | ||
2823 | ||
2824 | //---------------------------------------------------------- | |
2825 | // | |
2826 | // THREAD 6 | |
2827 | // | |
2828 | ||
2829 | ||
2830 | axis_trap_pipe6 t6 ( | |
2831 | .mycid (cid), | |
2832 | .mytid (3'h6), | |
2833 | .PC_reg (pc_6_w) | |
2834 | ); | |
2835 | ||
2836 | wire [2:0] thread6_id=3'h6; | |
2837 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c6.t6.pc_fw2},`CPU.l2clk,3'h6,6); | |
2838 | dbuff_pc dbuff_pc_t6 ( | |
2839 | .cycle (cycle[63:0]), | |
2840 | .pc (`TOP.axis_trap_top.c6.t6.pc_fw2), | |
2841 | .clk (`CPU.l2clk), | |
2842 | .core (cid), | |
2843 | .thread (thread6_id) | |
2844 | ); | |
2845 | ||
2846 | always @(posedge axis_top.start_dumps) | |
2847 | begin // axis tbcall_region | |
2848 | $display("DMP6_6: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t6.addr,tb_top.axis_trap_top.c6.dbuff_pc_t6.ptr_0_cycle); | |
2849 | $axis_dumpmemh("c6_t6_pctrc.dat", | |
2850 | tb_top.axis_trap_top.c6.dbuff_pc_t6.DBUFF); | |
2851 | end | |
2852 | ||
2853 | ||
2854 | //---------------------------------------------------------- | |
2855 | // | |
2856 | // THREAD 7 | |
2857 | // | |
2858 | ||
2859 | ||
2860 | axis_trap_pipe6 t7 ( | |
2861 | .mycid (cid), | |
2862 | .mytid (3'h7), | |
2863 | .PC_reg (pc_7_w) | |
2864 | ); | |
2865 | ||
2866 | wire [2:0] thread7_id=3'h7; | |
2867 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c6.t7.pc_fw2},`CPU.l2clk,3'h7,6); | |
2868 | dbuff_pc dbuff_pc_t7 ( | |
2869 | .cycle (cycle[63:0]), | |
2870 | .pc (`TOP.axis_trap_top.c6.t7.pc_fw2), | |
2871 | .clk (`CPU.l2clk), | |
2872 | .core (cid), | |
2873 | .thread (thread7_id) | |
2874 | ); | |
2875 | ||
2876 | always @(posedge axis_top.start_dumps) | |
2877 | begin // axis tbcall_region | |
2878 | $display("DMP6_7: %h %h \n",tb_top.axis_trap_top.c6.dbuff_pc_t7.addr,tb_top.axis_trap_top.c6.dbuff_pc_t7.ptr_0_cycle); | |
2879 | $axis_dumpmemh("c6_t7_pctrc.dat", | |
2880 | tb_top.axis_trap_top.c6.dbuff_pc_t7.DBUFF); | |
2881 | end | |
2882 | ||
2883 | ||
2884 | reg [5:0] trl1_tsa_wr_addr_r; | |
2885 | reg [1:0] tsd1_wr_gl_r; | |
2886 | reg [8:0] tsd1_wr_trap_type_r; | |
2887 | reg [47:2] tsd1_wr_tpc_r; | |
2888 | reg trl1_tsa_wr_en_r; | |
2889 | always @(posedge `CPU.l2clk) begin | |
2890 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc6.tlu.trl1_tsa_wr_addr; | |
2891 | tsd1_wr_gl_r <= tb_top.cpu.spc6.tlu.tsd1_wr_gl; | |
2892 | tsd1_wr_trap_type_r <= tb_top.cpu.spc6.tlu.tsd1_wr_trap_type[8:0]; | |
2893 | tsd1_wr_tpc_r <= tb_top.cpu.spc6.tlu.tsd1_wr_tpc; | |
2894 | trl1_tsa_wr_en_r <= tb_top.cpu.spc6.tlu.trl_tsa_wr_en[1]; | |
2895 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
2896 | begin // axis tbcall_region | |
2897 | $display("%t: TRAP WRITE: CORE 6: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
2898 | end | |
2899 | end | |
2900 | end | |
2901 | ||
2902 | //---------------------------------------------------------- | |
2903 | ||
2904 | `ifndef GATESIM | |
2905 | ||
2906 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
2907 | // But some of the error checkers need this signal without the qualification | |
2908 | // of icache errors | |
2909 | wire [7:0] select_pc_b_with_errors; | |
2910 | ||
2911 | assign select_pc_b_with_errors = | |
2912 | {{4 {~`SPC6.dec_flush_b[1]}}, {4 {~`SPC6.dec_flush_b[0]}}} & | |
2913 | ||
2914 | {~(`SPC6.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
2915 | {4 {`SPC6.tlu.fls1.idl_req_in}}), | |
2916 | ~(`SPC6.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
2917 | {4 {`SPC6.tlu.fls0.idl_req_in}})} & | |
2918 | {`SPC6.tlu.fls1.tid_dec_valid_b[3:0], | |
2919 | `SPC6.tlu.fls0.tid_dec_valid_b[3:0]}; | |
2920 | ||
2921 | //------------------------------------ | |
2922 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
2923 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
2924 | wire [7:0] select_pc_b; | |
2925 | ||
2926 | assign select_pc_b = | |
2927 | select_pc_b_with_errors[7:0] & | |
2928 | {{4 {~`SPC6.tlu.fls1.ic_err_w_in}}, {4 {~`SPC6.tlu.fls0.ic_err_w_in}}}; | |
2929 | ||
2930 | //------------------------------------ | |
2931 | // ASI & Trap State machines | |
2932 | always @(posedge `SPC6.gclk) begin // { | |
2933 | ||
2934 | // pc_0_e[47:0] <= `SPC6.ifu_pc_d0[47:0]; | |
2935 | // pc_1_e[47:0] <= `SPC6.ifu_pc_d1[47:0]; | |
2936 | pc_0_e[47:0] <= {`SPC6.tlu_pc_0_d[47:2], 2'b00}; | |
2937 | pc_1_e[47:0] <= {`SPC6.tlu_pc_1_d[47:2], 2'b00}; | |
2938 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
2939 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
2940 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
2941 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
2942 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
2943 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
2944 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
2945 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
2946 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
2947 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
2948 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
2949 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
2950 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
2951 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
2952 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
2953 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
2954 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
2955 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
2956 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
2957 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
2958 | end | |
2959 | ||
2960 | `endif | |
2961 | `endif //AXIS_TL | |
2962 | ||
2963 | //---------------------------------------------------------- | |
2964 | endmodule | |
2965 | ||
2966 | `endif | |
2967 | ||
2968 | `ifdef CORE_7 | |
2969 | ||
2970 | module axis_trap_core7 ( | |
2971 | cid, | |
2972 | pc_dmp_sz, | |
2973 | ); | |
2974 | ||
2975 | input [2:0] cid; | |
2976 | input [21:0] pc_dmp_sz; | |
2977 | ||
2978 | `ifdef AXIS_TL | |
2979 | `ifndef GATESIM | |
2980 | reg [47:0] pc_0_e; | |
2981 | reg [47:0] pc_1_e; | |
2982 | reg [47:0] pc_0_m; | |
2983 | reg [47:0] pc_1_m; | |
2984 | reg [47:0] pc_0_b; | |
2985 | reg [47:0] pc_1_b; | |
2986 | reg [47:0] pc_0_w; | |
2987 | reg [47:0] pc_1_w; | |
2988 | reg [47:0] pc_2_w; | |
2989 | reg [47:0] pc_3_w; | |
2990 | reg [47:0] pc_4_w; | |
2991 | reg [47:0] pc_5_w; | |
2992 | reg [47:0] pc_6_w; | |
2993 | reg [47:0] pc_7_w; | |
2994 | `endif | |
2995 | ||
2996 | //---------------------------------------------------------- | |
2997 | reg [63:0] cycle; | |
2998 | initial cycle = 64'b0; | |
2999 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
3000 | if (`CPU.tcu_aclk) cycle = 0; | |
3001 | else cycle = cycle + 64'b1; | |
3002 | end | |
3003 | ||
3004 | //*******************************************************************************************************/ | |
3005 | reg [76:0] sig_reg_0; | |
3006 | reg [76:0] sig_reg_1; | |
3007 | reg [76:0] sig_reg_2; | |
3008 | reg [76:0] sig_reg_3; | |
3009 | reg [63:0] kern_cnt; | |
3010 | reg [47:0] pc_0_saved; | |
3011 | ||
3012 | //wire kern_start = (pc_0_saved != 48'h20) && (pc_0_w == 48'h20); | |
3013 | always @(negedge `CPU.tcu_aclk) begin | |
3014 | begin // axis tbcall_region | |
3015 | $display("%t: dbg rst detected by repeatability_check", $time); | |
3016 | end | |
3017 | end | |
3018 | ||
3019 | always @(posedge `CPU.l2clk , posedge `CPU.tcu_aclk) begin | |
3020 | pc_0_saved <= pc_0_w; | |
3021 | if (`CPU.tcu_aclk) begin | |
3022 | sig_reg_1 <= 0; | |
3023 | sig_reg_2 <= 0; | |
3024 | sig_reg_3 <= 0; | |
3025 | sig_reg_0 <= 0; | |
3026 | kern_cnt <= 0; | |
3027 | end | |
3028 | else if (!`CPU.tcu_aclk) begin | |
3029 | if (tb_top.cpu.spc7.exu0.irf.wr_en_p0) sig_reg_0 <= sig_reg_0 ^ {tb_top.cpu.spc7.exu0.irf.wr_addr_p0,tb_top.cpu.spc7.exu0.irf.wr_data_p0}; | |
3030 | if (tb_top.cpu.spc7.exu0.irf.wr_en_p1) sig_reg_1 <= sig_reg_1 ^ {tb_top.cpu.spc7.exu0.irf.wr_addr_p1,tb_top.cpu.spc7.exu0.irf.wr_data_p1}; | |
3031 | if (tb_top.cpu.spc7.exu1.irf.wr_en_p0) sig_reg_2 <= sig_reg_2 ^ {tb_top.cpu.spc7.exu1.irf.wr_addr_p0,tb_top.cpu.spc7.exu1.irf.wr_data_p0}; | |
3032 | if (tb_top.cpu.spc7.exu1.irf.wr_en_p1) sig_reg_3 <= sig_reg_3 ^ {tb_top.cpu.spc7.exu1.irf.wr_addr_p1,tb_top.cpu.spc7.exu1.irf.wr_data_p1}; | |
3033 | kern_cnt <= kern_cnt + 1; | |
3034 | end | |
3035 | ||
3036 | if ((kern_cnt[19:0] == 20'hfffff) && tb_top.repeatablility_check) begin // axis tbcall_region | |
3037 | $display("%t: repeatability_check: core 7, sig_reg_0 = %0h, sig_reg_1 = %0h, sig_reg_2 = %0h, sig_reg_3 = %0h kern_cnt = %0h, cycle = %0h",$time,sig_reg_0,sig_reg_1,sig_reg_2,sig_reg_3,kern_cnt,cycle); | |
3038 | end | |
3039 | ||
3040 | end | |
3041 | ||
3042 | //************************************************************************************************** | |
3043 | //---------------------------------------------------------- | |
3044 | ||
3045 | //---------------------------------------------------------- | |
3046 | // | |
3047 | // THREAD 0 | |
3048 | // | |
3049 | ||
3050 | ||
3051 | axis_trap_pipe7 t0 ( | |
3052 | .mycid (cid), | |
3053 | .mytid (3'h0), | |
3054 | .PC_reg (pc_0_w) | |
3055 | ); | |
3056 | ||
3057 | wire [2:0] thread0_id=3'h0; | |
3058 | //dbuff_pc dbuff_pc_t0 ({cycle[19:4],`TOP.axis_trap_top.c7.t0.pc_fw2},`CPU.l2clk,3'h0,7); | |
3059 | dbuff_pc dbuff_pc_t0 ( | |
3060 | .cycle (cycle[63:0]), | |
3061 | .pc (`TOP.axis_trap_top.c7.t0.pc_fw2), | |
3062 | .clk (`CPU.l2clk), | |
3063 | .core (cid), | |
3064 | .thread (thread0_id) | |
3065 | ); | |
3066 | ||
3067 | always @(posedge axis_top.start_dumps) | |
3068 | begin // axis tbcall_region | |
3069 | $display("DMP7_0: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t0.addr,tb_top.axis_trap_top.c7.dbuff_pc_t0.ptr_0_cycle); | |
3070 | $axis_dumpmemh("c7_t0_pctrc.dat", | |
3071 | tb_top.axis_trap_top.c7.dbuff_pc_t0.DBUFF); | |
3072 | end | |
3073 | ||
3074 | ||
3075 | //---------------------------------------------------------- | |
3076 | // | |
3077 | // THREAD 1 | |
3078 | // | |
3079 | ||
3080 | ||
3081 | axis_trap_pipe7 t1 ( | |
3082 | .mycid (cid), | |
3083 | .mytid (3'h1), | |
3084 | .PC_reg (pc_1_w) | |
3085 | ); | |
3086 | ||
3087 | wire [2:0] thread1_id=3'h1; | |
3088 | //dbuff_pc dbuff_pc_t1 ({cycle[19:4],`TOP.axis_trap_top.c7.t1.pc_fw2},`CPU.l2clk,3'h1,7); | |
3089 | dbuff_pc dbuff_pc_t1 ( | |
3090 | .cycle (cycle[63:0]), | |
3091 | .pc (`TOP.axis_trap_top.c7.t1.pc_fw2), | |
3092 | .clk (`CPU.l2clk), | |
3093 | .core (cid), | |
3094 | .thread (thread1_id) | |
3095 | ); | |
3096 | ||
3097 | always @(posedge axis_top.start_dumps) | |
3098 | begin // axis tbcall_region | |
3099 | $display("DMP7_1: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t1.addr,tb_top.axis_trap_top.c7.dbuff_pc_t1.ptr_0_cycle); | |
3100 | $axis_dumpmemh("c7_t1_pctrc.dat", | |
3101 | tb_top.axis_trap_top.c7.dbuff_pc_t1.DBUFF); | |
3102 | end | |
3103 | ||
3104 | ||
3105 | //---------------------------------------------------------- | |
3106 | // | |
3107 | // THREAD 2 | |
3108 | // | |
3109 | ||
3110 | ||
3111 | axis_trap_pipe7 t2 ( | |
3112 | .mycid (cid), | |
3113 | .mytid (3'h2), | |
3114 | .PC_reg (pc_2_w) | |
3115 | ); | |
3116 | ||
3117 | wire [2:0] thread2_id=3'h2; | |
3118 | //dbuff_pc dbuff_pc_t2 ({cycle[19:4],`TOP.axis_trap_top.c7.t2.pc_fw2},`CPU.l2clk,3'h2,7); | |
3119 | dbuff_pc dbuff_pc_t2 ( | |
3120 | .cycle (cycle[63:0]), | |
3121 | .pc (`TOP.axis_trap_top.c7.t2.pc_fw2), | |
3122 | .clk (`CPU.l2clk), | |
3123 | .core (cid), | |
3124 | .thread (thread2_id) | |
3125 | ); | |
3126 | ||
3127 | always @(posedge axis_top.start_dumps) | |
3128 | begin // axis tbcall_region | |
3129 | $display("DMP7_2: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t2.addr,tb_top.axis_trap_top.c7.dbuff_pc_t2.ptr_0_cycle); | |
3130 | $axis_dumpmemh("c7_t2_pctrc.dat", | |
3131 | tb_top.axis_trap_top.c7.dbuff_pc_t2.DBUFF); | |
3132 | end | |
3133 | ||
3134 | ||
3135 | //---------------------------------------------------------- | |
3136 | // | |
3137 | // THREAD 3 | |
3138 | // | |
3139 | ||
3140 | ||
3141 | axis_trap_pipe7 t3 ( | |
3142 | .mycid (cid), | |
3143 | .mytid (3'h3), | |
3144 | .PC_reg (pc_3_w) | |
3145 | ); | |
3146 | ||
3147 | wire [2:0] thread3_id=3'h3; | |
3148 | //dbuff_pc dbuff_pc_t3 ({cycle[19:4],`TOP.axis_trap_top.c7.t3.pc_fw2},`CPU.l2clk,3'h3,7); | |
3149 | dbuff_pc dbuff_pc_t3 ( | |
3150 | .cycle (cycle[63:0]), | |
3151 | .pc (`TOP.axis_trap_top.c7.t3.pc_fw2), | |
3152 | .clk (`CPU.l2clk), | |
3153 | .core (cid), | |
3154 | .thread (thread3_id) | |
3155 | ); | |
3156 | ||
3157 | always @(posedge axis_top.start_dumps) | |
3158 | begin // axis tbcall_region | |
3159 | $display("DMP7_3: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t3.addr,tb_top.axis_trap_top.c7.dbuff_pc_t3.ptr_0_cycle); | |
3160 | $axis_dumpmemh("c7_t3_pctrc.dat", | |
3161 | tb_top.axis_trap_top.c7.dbuff_pc_t3.DBUFF); | |
3162 | end | |
3163 | ||
3164 | ||
3165 | reg [5:0] trl0_tsa_wr_addr_r; | |
3166 | reg [1:0] tsd0_wr_gl_r; | |
3167 | reg [8:0] tsd0_wr_trap_type_r; | |
3168 | reg [47:2] tsd0_wr_tpc_r; | |
3169 | reg trl0_tsa_wr_en_r; | |
3170 | always @(posedge `CPU.l2clk) begin | |
3171 | trl0_tsa_wr_addr_r <= tb_top.cpu.spc7.tlu.trl0_tsa_wr_addr; | |
3172 | tsd0_wr_gl_r <= tb_top.cpu.spc7.tlu.tsd0_wr_gl; | |
3173 | tsd0_wr_trap_type_r <= tb_top.cpu.spc7.tlu.tsd0_wr_trap_type[8:0]; | |
3174 | tsd0_wr_tpc_r <= tb_top.cpu.spc7.tlu.tsd0_wr_tpc; | |
3175 | trl0_tsa_wr_en_r <= tb_top.cpu.spc7.tlu.trl_tsa_wr_en[0]; | |
3176 | if ( trl0_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
3177 | begin // axis tbcall_region | |
3178 | $display("%t: TRAP WRITE: CORE 7: PIPE 0: %x %3x %12x %2x", $time, tsd0_wr_gl_r, tsd0_wr_trap_type_r, {tsd0_wr_tpc_r, 2'b00}, trl0_tsa_wr_addr_r); | |
3179 | end | |
3180 | end | |
3181 | end | |
3182 | ||
3183 | //---------------------------------------------------------- | |
3184 | // | |
3185 | // THREAD 4 | |
3186 | // | |
3187 | ||
3188 | ||
3189 | axis_trap_pipe7 t4 ( | |
3190 | .mycid (cid), | |
3191 | .mytid (3'h4), | |
3192 | .PC_reg (pc_4_w) | |
3193 | ); | |
3194 | ||
3195 | wire [2:0] thread4_id=3'h4; | |
3196 | //dbuff_pc dbuff_pc_t4 ({cycle[19:4],`TOP.axis_trap_top.c7.t4.pc_fw2},`CPU.l2clk,3'h4,7); | |
3197 | dbuff_pc dbuff_pc_t4 ( | |
3198 | .cycle (cycle[63:0]), | |
3199 | .pc (`TOP.axis_trap_top.c7.t4.pc_fw2), | |
3200 | .clk (`CPU.l2clk), | |
3201 | .core (cid), | |
3202 | .thread (thread4_id) | |
3203 | ); | |
3204 | ||
3205 | always @(posedge axis_top.start_dumps) | |
3206 | begin // axis tbcall_region | |
3207 | $display("DMP7_4: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t4.addr,tb_top.axis_trap_top.c7.dbuff_pc_t4.ptr_0_cycle); | |
3208 | $axis_dumpmemh("c7_t4_pctrc.dat", | |
3209 | tb_top.axis_trap_top.c7.dbuff_pc_t4.DBUFF); | |
3210 | end | |
3211 | ||
3212 | ||
3213 | //---------------------------------------------------------- | |
3214 | // | |
3215 | // THREAD 5 | |
3216 | // | |
3217 | ||
3218 | ||
3219 | axis_trap_pipe7 t5 ( | |
3220 | .mycid (cid), | |
3221 | .mytid (3'h5), | |
3222 | .PC_reg (pc_5_w) | |
3223 | ); | |
3224 | ||
3225 | wire [2:0] thread5_id=3'h5; | |
3226 | //dbuff_pc dbuff_pc_t5 ({cycle[19:4],`TOP.axis_trap_top.c7.t5.pc_fw2},`CPU.l2clk,3'h5,7); | |
3227 | dbuff_pc dbuff_pc_t5 ( | |
3228 | .cycle (cycle[63:0]), | |
3229 | .pc (`TOP.axis_trap_top.c7.t5.pc_fw2), | |
3230 | .clk (`CPU.l2clk), | |
3231 | .core (cid), | |
3232 | .thread (thread5_id) | |
3233 | ); | |
3234 | ||
3235 | always @(posedge axis_top.start_dumps) | |
3236 | begin // axis tbcall_region | |
3237 | $display("DMP7_5: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t5.addr,tb_top.axis_trap_top.c7.dbuff_pc_t5.ptr_0_cycle); | |
3238 | $axis_dumpmemh("c7_t5_pctrc.dat", | |
3239 | tb_top.axis_trap_top.c7.dbuff_pc_t5.DBUFF); | |
3240 | end | |
3241 | ||
3242 | ||
3243 | //---------------------------------------------------------- | |
3244 | // | |
3245 | // THREAD 6 | |
3246 | // | |
3247 | ||
3248 | ||
3249 | axis_trap_pipe7 t6 ( | |
3250 | .mycid (cid), | |
3251 | .mytid (3'h6), | |
3252 | .PC_reg (pc_6_w) | |
3253 | ); | |
3254 | ||
3255 | wire [2:0] thread6_id=3'h6; | |
3256 | //dbuff_pc dbuff_pc_t6 ({cycle[19:4],`TOP.axis_trap_top.c7.t6.pc_fw2},`CPU.l2clk,3'h6,7); | |
3257 | dbuff_pc dbuff_pc_t6 ( | |
3258 | .cycle (cycle[63:0]), | |
3259 | .pc (`TOP.axis_trap_top.c7.t6.pc_fw2), | |
3260 | .clk (`CPU.l2clk), | |
3261 | .core (cid), | |
3262 | .thread (thread6_id) | |
3263 | ); | |
3264 | ||
3265 | always @(posedge axis_top.start_dumps) | |
3266 | begin // axis tbcall_region | |
3267 | $display("DMP7_6: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t6.addr,tb_top.axis_trap_top.c7.dbuff_pc_t6.ptr_0_cycle); | |
3268 | $axis_dumpmemh("c7_t6_pctrc.dat", | |
3269 | tb_top.axis_trap_top.c7.dbuff_pc_t6.DBUFF); | |
3270 | end | |
3271 | ||
3272 | ||
3273 | //---------------------------------------------------------- | |
3274 | // | |
3275 | // THREAD 7 | |
3276 | // | |
3277 | ||
3278 | ||
3279 | axis_trap_pipe7 t7 ( | |
3280 | .mycid (cid), | |
3281 | .mytid (3'h7), | |
3282 | .PC_reg (pc_7_w) | |
3283 | ); | |
3284 | ||
3285 | wire [2:0] thread7_id=3'h7; | |
3286 | //dbuff_pc dbuff_pc_t7 ({cycle[19:4],`TOP.axis_trap_top.c7.t7.pc_fw2},`CPU.l2clk,3'h7,7); | |
3287 | dbuff_pc dbuff_pc_t7 ( | |
3288 | .cycle (cycle[63:0]), | |
3289 | .pc (`TOP.axis_trap_top.c7.t7.pc_fw2), | |
3290 | .clk (`CPU.l2clk), | |
3291 | .core (cid), | |
3292 | .thread (thread7_id) | |
3293 | ); | |
3294 | ||
3295 | always @(posedge axis_top.start_dumps) | |
3296 | begin // axis tbcall_region | |
3297 | $display("DMP7_7: %h %h \n",tb_top.axis_trap_top.c7.dbuff_pc_t7.addr,tb_top.axis_trap_top.c7.dbuff_pc_t7.ptr_0_cycle); | |
3298 | $axis_dumpmemh("c7_t7_pctrc.dat", | |
3299 | tb_top.axis_trap_top.c7.dbuff_pc_t7.DBUFF); | |
3300 | end | |
3301 | ||
3302 | ||
3303 | reg [5:0] trl1_tsa_wr_addr_r; | |
3304 | reg [1:0] tsd1_wr_gl_r; | |
3305 | reg [8:0] tsd1_wr_trap_type_r; | |
3306 | reg [47:2] tsd1_wr_tpc_r; | |
3307 | reg trl1_tsa_wr_en_r; | |
3308 | always @(posedge `CPU.l2clk) begin | |
3309 | trl1_tsa_wr_addr_r <= tb_top.cpu.spc7.tlu.trl1_tsa_wr_addr; | |
3310 | tsd1_wr_gl_r <= tb_top.cpu.spc7.tlu.tsd1_wr_gl; | |
3311 | tsd1_wr_trap_type_r <= tb_top.cpu.spc7.tlu.tsd1_wr_trap_type[8:0]; | |
3312 | tsd1_wr_tpc_r <= tb_top.cpu.spc7.tlu.tsd1_wr_tpc; | |
3313 | trl1_tsa_wr_en_r <= tb_top.cpu.spc7.tlu.trl_tsa_wr_en[1]; | |
3314 | if ( trl1_tsa_wr_en_r & tb_top.tlu_dbg_en) begin | |
3315 | begin // axis tbcall_region | |
3316 | $display("%t: TRAP WRITE: CORE 7: PIPE 1: %x %3x %12x %2x", $time, tsd1_wr_gl_r, tsd1_wr_trap_type_r, {tsd1_wr_tpc_r, 2'b00}, trl1_tsa_wr_addr_r); | |
3317 | end | |
3318 | end | |
3319 | end | |
3320 | ||
3321 | //---------------------------------------------------------- | |
3322 | ||
3323 | `ifndef GATESIM | |
3324 | ||
3325 | // This was the original select_pc_b, the latest select_pc_b qualifies with errors | |
3326 | // But some of the error checkers need this signal without the qualification | |
3327 | // of icache errors | |
3328 | wire [7:0] select_pc_b_with_errors; | |
3329 | ||
3330 | assign select_pc_b_with_errors = | |
3331 | {{4 {~`SPC7.dec_flush_b[1]}}, {4 {~`SPC7.dec_flush_b[0]}}} & | |
3332 | ||
3333 | {~(`SPC7.tlu.fls1.clear_disrupting_flush_pending_w_in[3:0] & | |
3334 | {4 {`SPC7.tlu.fls1.idl_req_in}}), | |
3335 | ~(`SPC7.tlu.fls0.clear_disrupting_flush_pending_w_in[3:0] & | |
3336 | {4 {`SPC7.tlu.fls0.idl_req_in}})} & | |
3337 | {`SPC7.tlu.fls1.tid_dec_valid_b[3:0], | |
3338 | `SPC7.tlu.fls0.tid_dec_valid_b[3:0]}; | |
3339 | ||
3340 | //------------------------------------ | |
3341 | // Suppress instruction on flush or park request (clear_disrupting_flush_pending) | |
3342 | // Qualify select_pc_b_with_errors, with no errors to get final select_pc_b signal | |
3343 | wire [7:0] select_pc_b; | |
3344 | ||
3345 | assign select_pc_b = | |
3346 | select_pc_b_with_errors[7:0] & | |
3347 | {{4 {~`SPC7.tlu.fls1.ic_err_w_in}}, {4 {~`SPC7.tlu.fls0.ic_err_w_in}}}; | |
3348 | ||
3349 | //------------------------------------ | |
3350 | // ASI & Trap State machines | |
3351 | always @(posedge `SPC7.gclk) begin // { | |
3352 | ||
3353 | // pc_0_e[47:0] <= `SPC7.ifu_pc_d0[47:0]; | |
3354 | // pc_1_e[47:0] <= `SPC7.ifu_pc_d1[47:0]; | |
3355 | pc_0_e[47:0] <= {`SPC7.tlu_pc_0_d[47:2], 2'b00}; | |
3356 | pc_1_e[47:0] <= {`SPC7.tlu_pc_1_d[47:2], 2'b00}; | |
3357 | pc_0_m[47:0] <= pc_0_e[47:0]; | |
3358 | pc_1_m[47:0] <= pc_1_e[47:0]; | |
3359 | pc_0_b[47:0] <= pc_0_m[47:0]; | |
3360 | pc_1_b[47:0] <= pc_1_m[47:0]; | |
3361 | pc_0_w[47:0] <= ({48 { select_pc_b[0]}} & pc_0_b[47:0]) | | |
3362 | ({48 {~select_pc_b[0]}} & pc_0_w[47:0]) ; | |
3363 | pc_1_w[47:0] <= ({48 { select_pc_b[1]}} & pc_0_b[47:0]) | | |
3364 | ({48 {~select_pc_b[1]}} & pc_1_w[47:0]) ; | |
3365 | pc_2_w[47:0] <= ({48 { select_pc_b[2]}} & pc_0_b[47:0]) | | |
3366 | ({48 {~select_pc_b[2]}} & pc_2_w[47:0]) ; | |
3367 | pc_3_w[47:0] <= ({48 { select_pc_b[3]}} & pc_0_b[47:0]) | | |
3368 | ({48 {~select_pc_b[3]}} & pc_3_w[47:0]) ; | |
3369 | pc_4_w[47:0] <= ({48 { select_pc_b[4]}} & pc_1_b[47:0]) | | |
3370 | ({48 {~select_pc_b[4]}} & pc_4_w[47:0]) ; | |
3371 | pc_5_w[47:0] <= ({48 { select_pc_b[5]}} & pc_1_b[47:0]) | | |
3372 | ({48 {~select_pc_b[5]}} & pc_5_w[47:0]) ; | |
3373 | pc_6_w[47:0] <= ({48 { select_pc_b[6]}} & pc_1_b[47:0]) | | |
3374 | ({48 {~select_pc_b[6]}} & pc_6_w[47:0]) ; | |
3375 | pc_7_w[47:0] <= ({48 { select_pc_b[7]}} & pc_1_b[47:0]) | | |
3376 | ({48 {~select_pc_b[7]}} & pc_7_w[47:0]) ; | |
3377 | end | |
3378 | ||
3379 | `endif | |
3380 | `endif //AXIS_TL | |
3381 | ||
3382 | //---------------------------------------------------------- | |
3383 | endmodule | |
3384 | ||
3385 | `endif | |
3386 |