Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / verilog / axis_traps / axis_trap_top.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: axis_trap_top.v
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// ========== Copyright Header End ============================================
module axis_trap_top(pc_dmp_sz);
input [21:0] pc_dmp_sz;

//`include "defines.vh"
//`include "nas.vh"

// wires for asm user events
//`include "asmEventsProbes.vh"

//----------------------------------------------------------
// Instantiate 1-8 cores
`ifdef CORE_0
  axis_trap_core0 c0 (3'h0,pc_dmp_sz);
`endif
`ifdef CORE_1
  axis_trap_core1 c1 (3'h1,pc_dmp_sz);
`endif
`ifdef CORE_2
  axis_trap_core2 c2 (3'h2,pc_dmp_sz);
`endif
`ifdef CORE_3
  axis_trap_core3 c3 (3'h3,pc_dmp_sz);
`endif
`ifdef CORE_4
  axis_trap_core4 c4 (3'h4,pc_dmp_sz);
`endif
`ifdef CORE_5
  axis_trap_core5 c5 (3'h5,pc_dmp_sz);
`endif
`ifdef CORE_6
  axis_trap_core6 c6 (3'h6,pc_dmp_sz);
`endif
`ifdef CORE_7
  axis_trap_core7 c7 (3'h7,pc_dmp_sz);
`endif

//----------------------------------------------------------
endmodule
//----------------------------------------------------------
//----------------------------------------------------------