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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ncu_chkr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ncu_chkr ; | |
36 | ||
37 | `ifdef X_GUARD | |
38 | // 0in known_driven -var `CPU.ncu_dmu_stall -name ncu_dmu_stall_x_guard -clock `CPU.dmu.iol2clk | |
39 | // 0in known_driven -var `CPU.dmu_ncu_vld -name dmu_ncu_vld_x_guard -clock `CPU.dmu.iol2clk | |
40 | // 0in known_driven -var `CPU.dmu_ncu_stall -name dmu_ncu_stall_x_guard -clock `CPU.dmu.iol2clk | |
41 | // 0in known_driven -var `CPU.ncu_dmu_vld -name ncu_dmu_vld_x_guard -clock `CPU.dmu.iol2clk | |
42 | ||
43 | // The dmu_ncu_data and ncu_dmu_data buses should be known_driven when | |
44 | // the cooresponding valid signal is active and the stall signal was | |
45 | // inactive in the previous cycle. | |
46 | ||
47 | /* 0in known_driven -var `CPU.dmu_ncu_data -name dmu_ncu_data_x_guard -clock `CPU.dmu.iol2clk | |
48 | -active (`CPU.dmu_ncu_vld & ($0in_delay(`CPU.ncu_dmu_stall,1) == 1'b0) ) */ | |
49 | /* 0in known_driven -var `CPU.ncu_dmu_data -name ncu_dmu_data_x_guard -clock `CPU.dmu.iol2clk | |
50 | -active (`CPU.ncu_dmu_vld & ($0in_delay(`CPU.dmu_ncu_stall,1) == 1'b0) ) */ | |
51 | ||
52 | // 0in known_driven -var `CPU.ncu_dmu_pio_hdr_vld -name ncu_dmu_pio_hdr_vld_x_guard -clock `CPU.dmu.iol2clk | |
53 | // 0in known_driven -var `CPU.ncu_dmu_mmu_addr_vld -name ncu_dmu_mmu_addr_vld_x_guard -clock `CPU.dmu.iol2clk | |
54 | // 0in known_driven -var `CPU.dmu_ncu_wrack_vld -name dmu_ncu_wrack_vld_x_guard -clock `CPU.dmu.iol2clk | |
55 | // 0in known_driven -var `CPU.ncu_dmu_mondo_ack -name ncu_dmu_mondo_ack_x_guard -clock `CPU.dmu.iol2clk | |
56 | // 0in known_driven -var `CPU.ncu_dmu_mondo_nack -name ncu_dmu_mondo_nack_x_guard -clock `CPU.dmu.iol2clk | |
57 | /* 0in known_driven -var `CPU.ncu_dmu_pio_data -name ncu_dmu_pio_data_x_guard -clock `CPU.dmu.iol2clk | |
58 | -active (`CPU.ncu_dmu_pio_hdr_vld | `CPU.ncu_dmu_mmu_addr_vld) */ | |
59 | /* 0in known_driven -var `CPU.dmu_ncu_wrack_tag -name dmu_ncu_wrack_tag_x_guard -clock `CPU.dmu.iol2clk | |
60 | -active `CPU.dmu_ncu_wrack_vld */ | |
61 | /* 0in known_driven -var `CPU.ncu_dmu_mondo_id -name ncu_dmu_mondo_id_x_guard -clock `CPU.dmu.iol2clk | |
62 | -active (`CPU.ncu_dmu_mondo_ack | `CPU.ncu_dmu_mondo_nack) */ | |
63 | ||
64 | `endif | |
65 | ||
66 | ||
67 | //****************************************************************** | |
68 | // *_vld can't active over 32 cycle without *_stall in active | |
69 | //****************************************************************** | |
70 | ||
71 | /* 0in assert_window | |
72 | -start `CPU.dmu_ncu_vld | |
73 | -stop_count 32 | |
74 | -in (!`CPU.dmu_ncu_vld || `CPU.ncu_dmu_stall) | |
75 | -min 1 | |
76 | -clock `CPU.dmu.iol2clk | |
77 | */ | |
78 | /* 0in assert_window | |
79 | -start `CPU.ncu_dmu_vld | |
80 | -stop_count 32 | |
81 | -in (!`CPU.ncu_dmu_vld || `CPU.dmu_ncu_stall) | |
82 | -min 1 | |
83 | -clock `CPU.dmu.iol2clk | |
84 | */ | |
85 | ||
86 | ||
87 | //****************************************************************** | |
88 | // *_stall can't active too long, for dmu_ncu_stall this is | |
89 | // determined in dmu_dsn_ccc_fsm.v | |
90 | //****************************************************************** | |
91 | /* 0in assert_window | |
92 | -start `CPU.dmu_ncu_stall | |
93 | -stop_count 265 | |
94 | -in !`CPU.dmu_ncu_stall | |
95 | -min 1 | |
96 | -name dmu_stall_too_long | |
97 | -clock `CPU.dmu.iol2clk | |
98 | */ | |
99 | ||
100 | ||
101 | /* 0in assert_window | |
102 | -start `CPU.ncu_dmu_stall | |
103 | -stop_count 100 | |
104 | -in !`CPU.ncu_dmu_stall | |
105 | -min 1 | |
106 | -name ncu_stall_too_long | |
107 | -clock `CPU.dmu.iol2clk | |
108 | */ | |
109 | ||
110 | ||
111 | //****************************************************************** | |
112 | // ncu_dmu_mondo_nack and ncu_dmu_mondo_ack never active same time | |
113 | //****************************************************************** | |
114 | /* 0in mutex | |
115 | -var {`CPU.ncu_dmu_mondo_ack, `CPU.ncu_dmu_mondo_nack} | |
116 | -clock `CPU.dmu.iol2clk | |
117 | */ | |
118 | ||
119 | //****************************************************************** | |
120 | // ncu_dmu_pio_hdr_vld and ncu_dmu_mmu_addr_vld never active same time | |
121 | //****************************************************************** | |
122 | /* 0in mutex | |
123 | -var {`CPU.ncu_dmu_mmu_addr_vld, `CPU.ncu_dmu_pio_hdr_vld} | |
124 | -clock `CPU.dmu.iol2clk | |
125 | */ | |
126 | ||
127 | endmodule // dmu_ncu_chkr |