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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / checkers / ilupeu / ilu_peu_checkers.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilu_peu_checkers.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module ilu_peu_checkers;
36
37
38
39 //-----------------------------------------------------------------------
40 // Disabling the Checkers for a certain time at the beginning of the sim
41 //
42 // The before_rst signal is used to disable all checkers for a specific
43 // delay at the start of simulation. The '#120' delay should be modified
44 // as necessary. Alternatively, the disable_checker directive can be
45 // altered to use a signal in the design (other than the before_rst
46 // signal) that informs 0-In when the design has been reset and the
47 // inputs are stable.
48 //-----------------------------------------------------------------------
49
50 //----------------------------------------------------------------------
51 // Disable case checkers in IHP for a cycle after reset
52 //----------------------------------------------------------------------
53
54
55// ****************************************************************************
56// This is the N2 peu portion
57// ****************************************************************************
58`define ilu_top `CPU.dmu.ilu
59`define ilu_clock `CPU.dmu.ilu.l1clk
60// `define ilu_warmreset `CPU.dmu.ilu.isb.rst_cct.rst_l_out
61`define ilu_warmreset `CPU.dmu.ilu.j2d_rst_l
62
63`define peu_clock `PEU.pc_clk
64`define peu_warmreset `PEU.peu_ptl.j2p_rst_l
65`define peu_debug_a_reg `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_dbg_sel_a
66`define peu_ptl_etl_hcs `PEU.peu_ptl.etl.hcs
67
68
69reg no_edb_par ;
70reg no_ibc_req_ack ;
71reg no_mps_val_chk ;
72initial begin // {
73 @(posedge tb_top.cpu.peu.iol2clk) ;
74 if ($test$plusargs("no_dmu2peu_edb_parity"))
75 no_edb_par <= 1;
76 else
77 no_edb_par <= 0;
78
79 if ($test$plusargs("no_dmu2peu_ibc_req_ack"))
80 no_ibc_req_ack <= 1;
81 else
82 no_ibc_req_ack <= 0;
83
84 if ($test$plusargs("no_dmu2peu_mps_val_chk"))
85 no_mps_val_chk <= 1;
86 else
87 no_mps_val_chk <= 0;
88
89end //}
90
91// 0in disable_checker -name *d2p_edb_odd_parity* no_edb_par
92
93// 0in disable_checker -name *d2p_ibc_req_ack* no_ibc_req_ack
94
95// 0in disable_checker -name *p2d_mps_value* no_mps_val_chk
96// 0in disable_checker -name *p2d_mps_less_than* no_mps_val_chk
97
98
99 // p2d_ihb_data is matched by y2k_rcd when y2k_rcd_enq is active
100 // p2d_ihb_data is qualified by ihb_rptr_inc
101
102 // use the internal is_ihb_rcd signal to check the ihb data on y2k_rcd only, no
103 // completion or drain cases
104// AT: -ret $0in_delay(`CPU.dmu.ilu.iil.rcdbldr.is_ihb_rcd)
105// y2k_rcd[115:109] also does NOT follow p2d_ihb_data[126:120] when the ingress TLP is not
106// a supported req. (See line 233-234 :/design/dmu/dmu_ilu_l/dmu_ilu/rtl/dmu_ilu_iil_rcdbldr.v.)
107
108 /* 0in oid
109 -req $0in_delay(`CPU.dmu.ilu.iil.xfrfsm.ihb_rptr_inc)
110 -req_id `CPU.dmu.ilu.p2d_ihb_data[126:120]
111 -ret $0in_delay(!`CPU.dmu.ilu.iil.rcdbldr.is_unsupported_req &
112 `CPU.dmu.ilu.iil.rcdbldr.is_ihb_rcd )
113 -ret_id `CPU.dmu.ilu.y2k_rcd[115:109]
114 -clock `ilu_clock
115 -reset ~`ilu_warmreset
116 -max_ids_check off
117 -max_count_per_id_check off
118 -name AC_y2k_rcd_follows_p2d_ihb_data
119
120 */
121
122 // k2y_rcd when k2y_rcd_enq active is matched by d2p_ehb_data when d2p_ehb_we is active
123 /* 0in oid
124 -req `CPU.dmu.ilu.k2y_rcd_enq
125 -req_id `CPU.dmu.ilu.k2y_rcd[123:117]
126 -ret `PEU.d2p_ehb_we
127 -ret_id `PEU.d2p_ehb_data[126:120]
128 -clock `ilu_clock
129 -reset ~`ilu_warmreset
130 -max_ids_check off
131 -max_count_per_id_check off
132 -name AC_d2p_ehb_data_follows_k2y_rcd
133
134
135 */
136
137
138
139
140 // Parity check on d2p_edb_data
141 // parity bit 0
142 /* 0in odd_parity -var ({`PEU.d2p_edb_data[31:0], `PEU.d2p_edb_dpar[0]})
143 -active `PEU.d2p_edb_we
144 -clock `ilu_clock
145 -reset ~`ilu_warmreset
146 -module peu
147 -name AC_d2p_edb_odd_parity_bit_0
148 */
149
150 // parity bit 1
151 /* 0in odd_parity -var {`PEU.d2p_edb_data[63:32], `PEU.d2p_edb_dpar[1]}
152 -active `PEU.d2p_edb_we
153 -clock `ilu_clock
154 -reset ~`ilu_warmreset
155 -module peu
156 -name AC_d2p_edb_odd_parity_bit_1
157 */
158
159 // parity bit 2
160 /* 0in odd_parity -var {`PEU.d2p_edb_data[95:64], `PEU.d2p_edb_dpar[2]}
161 -active `PEU.d2p_edb_we
162 -clock `ilu_clock
163 -reset ~`ilu_warmreset
164 -module peu
165 -name AC_d2p_edb_odd_parity_bit_2
166 */
167
168
169 // parity bit 3
170 /* 0in odd_parity -var {`PEU.d2p_edb_data[127:96], `PEU.d2p_edb_dpar[3]}
171 -active `PEU.d2p_edb_we
172 -clock `ilu_clock
173 -reset ~`ilu_warmreset
174 -module peu
175 -name AC_d2p_edb_odd_parity_bit_3
176 */
177
178 // === p2d_mps
179
180 // == value check 0,1,2
181 /* 0in value -var `PEU.p2d_mps
182 -val 0 1 2
183 -clock `peu_clock
184 -reset ~`peu_warmreset
185 -module peu
186 -name AC_p2d_mps_value_check
187 */
188
189 // == check against dev_ctl_reg[7:0]
190 /* 0in assert_follower
191 -leader `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.dev_ctl.dev_ctl_0.dev_ctl_csrbus_read_data[7:5]
192 -follower `PEU.p2d_mps
193 -max 3
194 -clock `peu_clock
195 -reset ~`peu_warmreset
196 -module peu
197 -name AC_p2d_mps_against_dev_ctl_reg
198 */
199
200 // == check p2d_mps < peu device capability register mps field
201 wire [2:0] peu_dev_cap_reg_mps = `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.dev_cap.dev_cap_csrbus_read_data[2:0] ;
202 /* 0in max
203 -var `PEU.p2d_mps
204 -val peu_dev_cap_reg_mps
205 -clock `peu_clock
206 -reset ~`peu_warmreset
207 -module peu
208 -name AC_p2d_mps_less_than_dev_cap_mps
209
210 */
211
212
213 // === p2d_drain active when ehb or edb has parity error or when link is down
214 // === et2ct_header_parity_err = ehb and edb parity
215 // -leader (`PEU.peu_ptl.etl.hcs.et2ct_header_parity_err | `PEU.peu_ptl.etl.lcs.et2ct_data_parity_err | `PEU.peu_ptl.ctb.tlr.csr.rio.lpu_ldn )
216 /*
217 0in assert_follower
218 -leader ($0in_rising_edge(`PEU.peu_ptl.etl.hcs.et2ct_header_parity_err | `PEU.peu_ptl.etl.lcs.et2ct_data_parity_err))
219 -follower ($0in_rising_edge(`PEU.p2d_drain))
220 -max 4
221 -clock `peu_clock
222 -reset ~`peu_warmreset
223 -name AC_p2d_drain_active
224 */
225
226// AT-: All the signals are in peu_clock domain: -clock `ilu_clock
227// AT-: -reset ~`ilu_warmreset
228
229
230
231
232
233 //-----------------------------------------------------------------------
234 // Checkers for the gray code pointers
235 //
236 // There is a checker for each side of the clock domain boundary.
237 //
238 //-----------------------------------------------------------------------
239
240 //== d2p
241 /* 0in gray_code -clock `ilu_clock
242 -reset (~`ilu_warmreset | `PEU.p2d_drain)
243 -var `PEU.d2p_ech_wptr
244 -name AC_d2p_ech_wptr_gray_code */
245 /* 0in gray_code -clock `ilu_clock
246 -reset (~`ilu_warmreset | `PEU.p2d_drain)
247 -var `PEU.d2p_erh_wptr
248 -name AC_d2p_erh_wptr_gray_code */
249
250 //== p2d
251 /* 0in gray_code -clock `peu_clock
252 -reset (~`peu_warmreset | `PEU.p2d_drain)
253 -var `PEU.p2d_ihb_wptr
254 -name AC_p2d_ihb_wptr_gray_code */
255 /* 0in gray_code -clock `peu_clock
256 -reset (~`peu_warmreset | `PEU.p2d_drain)
257 -var `PEU.p2d_ech_rptr
258 -name AC_p2d_ech_rptr_gray_code */
259 /* 0in gray_code -clock `peu_clock
260 -reset (~`peu_warmreset | `PEU.p2d_drain)
261 -var `PEU.p2d_erh_rptr
262 -name AC_p2d_erh_rptr_gray_code */
263 /* 0in gray_code -clock `peu_clock
264 -reset (~`peu_warmreset | `PEU.p2d_drain)
265 -var `PEU.p2d_ecd_rptr
266 -name AC_p2d_ecd_rptr_gray_code */
267 /* 0in gray_code -clock `peu_clock
268 -reset (~`peu_warmreset | `PEU.p2d_drain)
269 -var `PEU.p2d_erd_rptr
270 -name AC_p2d_erd_rptr_gray_code */
271
272
273
274 //=== p2d, d2p request follows acknowlege
275 // Let 0in infer the transmit and receive clocks
276 // /* 0in req_ack `PEU.p2d_cto_req `PEU.d2p_cto_ack
277 // peu.d2p_cto_ack = peu.peu_ptl.rsb.rsb_ctrl.n_cto_ack_reg
278 /* 0in req_ack -req `PEU.p2d_cto_req
279 -ack `PEU.peu_ptl.rsb.rsb_ctrl.n_cto_ack_reg
280 -req_until_ack
281 -ack_until_req_deassert
282 -min 2 -max 10
283 -clock `peu_clock
284 -reset ~`peu_warmreset
285 -name AC_p2d_cto_req_ack
286 */
287
288 // /* 0in req_ack `PEU.d2p_csr_req `PEU.p2d_csr_ack
289 // peu.d2p_csr_req = peu.peu_ptl.ctb.dcd.req
290 /* 0in req_ack -req `PEU.peu_ptl.ctb.dcd.req
291 -ack `PEU.p2d_csr_ack
292 -req_until_ack
293 -ack_until_req_deassert
294 -clock `peu_clock
295 -reset ~`peu_warmreset
296 -name AC_d2p_csr_req_ack -max 100 */
297
298 // /* 0in req_ack `PEU.p2d_csr_req `PEU.d2p_csr_ack
299 // peu.d2p_csr_ack = peu.peu_ptl.ctb.dcs.osm.ack
300 /* 0in req_ack -req `PEU.p2d_csr_req
301 -ack `PEU.peu_ptl.ctb.dcs.osm.ack
302 -req_until_ack
303 -ack_until_req_deassert
304 -clock `peu_clock
305 -reset ~`peu_warmreset
306 -max 100
307 -name AC_p2d_csr_req_ack */
308
309 // peu.peu_ptl.itl.ifc.req = sync'd version of peu.d2p_ibc_req
310
311 // 07/21/05: Add back the -active option, since the ifc won't ack
312 // ingress buffer credit req during link training.
313 // For x1,x2,x4 tests, link training takes >10K cycles,
314 // which would have caused the checker to misfire.
315
316 // 09/16/06: suggested changing:
317 // -reset ~`PEU.peu_ptl.etl.ct2et_rst_l to
318 // -reset (tb_top.cpu.peu.peu_ptl.ctb.tlr.rio.ct2et_lnk_dwn |
319 // ~tb_top.cpu.peu.peu_ptl.ctb.tlr.rio.rst_l)
320
321 /* 0in req_ack -req `PEU.peu_ptl.itl.ifc.req
322 -ack `PEU.p2d_ibc_ack
323 -req_until_ack
324 -ack_assert_to_req_deassert_min 1
325 -ack_until_req_deassert
326 -clock `peu_clock
327 -reset (`PEU.peu_ptl.ctb.tlr.rio.ct2et_lnk_dwn |
328 ~`PEU.peu_ptl.ctb.tlr.rio.rst_l)
329 -active `PEU.peu_ptl.itl.ifc.ct2it_link
330 -max 10000
331 -name AC_d2p_ibc_req_ack
332 */
333
334
335 //=== p2d_ce_int active when ce-status_reg <> 0 and ce-interrupt_enable active
336// /* 0in assert_window
337// -start (|(`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_csrbus_read_data[63:0] & `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_csrbus_read_data[63:0]))
338// -stop_count 2
339// -in `PEU.p2d_ce_int
340// -max 1
341// -clock `peu_clock
342// -reset ~`peu_warmreset
343// -name AC_p2d_ce_int
344//
345// */
346wire [63:0] p2d_ce_int_transition_count;
347 /* 0in assert_together
348 -leader $0in_delay(|(`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_int_en.ce_int_en_csrbus_read_data[63:0] & `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_csrbus_read_data[63:0]))
349 -follower (`PEU.p2d_ce_int)
350 -transitions_checked p2d_ce_int_transition_count
351 -clock `peu_clock
352 -reset ~`peu_warmreset
353 -name AC_p2d_ce_int
354 */
355
356
357
358
359
360 //=== p2d_oe_int active when oe-status_reg <> 0 and oe-interrupt_enable active
361
362// reg [63:0] p2d_oe_int_transition_count;
363// -transitions_checked p2d_oe_int_transition_count
364wire [63:0] p2d_oe_int_transition_count;
365 /* 0in assert_together
366 -leader $0in_delay(|(`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_int_en.oe_int_en_csrbus_read_data[63:0] & `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_csrbus_read_data[63:0]))
367 -follower (`PEU.p2d_oe_int)
368 -transitions_checked p2d_oe_int_transition_count
369 -clock `peu_clock
370 -reset ~`peu_warmreset
371 -name AC_p2d_oe_int
372 */
373
374
375
376
377 //=== p2d_ue_int active when ue-status_reg <> 0 and ue-interrupt_enable active
378 wire ue_int_on = (|(`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_csrbus_read_data[63:0] & `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_csrbus_read_data[63:0]));
379
380
381
382
383wire [63:0] p2d_ue_int_transition_count;
384 /* 0in assert_together
385 -leader $0in_delay(|(`PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_int_en.ue_int_en_csrbus_read_data[63:0] & `PEU.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_csrbus_read_data[63:0]))
386 -follower (`PEU.p2d_ue_int)
387 -transitions_checked p2d_ue_int_transition_count
388 -clock `peu_clock
389 -reset ~`peu_warmreset
390 -name AC_p2d_ue_int
391 */
392
393
394
395
396
397
398
399 //==== p2d_cto_tag is valid and constant during p2d_cto_req
400 /* 0in constant -var `PEU.p2d_cto_tag -active `PEU.p2d_cto_req
401 -clock `peu_clock
402 -reset ~`peu_warmreset
403 -name AC_p2d_cto_tag_constant
404 */
405
406
407 //===== peu_psr_pll_mpy should only change value 1 cycle after falling edge
408 // of warm reset. Otherwise, its value is constant until next warmreset
409 /* 0in change_window
410 -start $0in_delay(($0in_falling_edge(`PEU.rst_wmr_)),3)
411 -stop $0in_falling_edge(`PEU.rst_wmr_)
412 -not_in $0in_delay(peu_psr_pll_mpy)
413 -module peu
414 -clock `peu_clock
415 -reset 1'b0
416 -name AC_peu_mpy_update_after_wrm
417 */
418
419
420
421 //-----------------------------------------------------------------------
422 // known-driven checkers for signals between ILU and PEU
423 //
424 // There is a checker for each side of the clock domain boundary.
425 //
426 // NOTE: resets are active low!
427 //-----------------------------------------------------------------------
428
429
430 //---------------------------------------------------------------------
431 // 350 MHz domain
432 //---------------------------------------------------------------------
433 /* 0in known_driven -clock `ilu_clock
434 -reset !`ilu_warmreset
435 -var `CPU.dmu.ilu.d2p_ihb_addr */
436 /* 0in known_driven -clock `ilu_clock
437 -reset !`ilu_warmreset
438 -var `CPU.dmu.ilu.p2d_ihb_wptr */
439
440
441 /* 0in known_driven -clock `ilu_clock
442 -reset !`ilu_warmreset
443 -var `CPU.dmu.ilu.d2p_idb_addr */
444
445 /* 0in known_driven -clock `ilu_clock
446 -reset !`ilu_warmreset
447 -active `CPU.dmu.ilu.d2p_ibc_req
448 -var `CPU.dmu.ilu.d2p_ibc_nhc */
449 /* 0in known_driven -clock `ilu_clock
450 -reset !`ilu_warmreset
451 -active `CPU.dmu.ilu.d2p_ibc_req
452 -var `CPU.dmu.ilu.d2p_ibc_phc */
453 /* 0in known_driven -clock `ilu_clock
454 -reset !`ilu_warmreset
455 -active `CPU.dmu.ilu.d2p_ibc_req
456 -var `CPU.dmu.ilu.d2p_ibc_pdc */
457 /* 0in known_driven -clock `ilu_clock
458 -reset !`ilu_warmreset
459 -var `CPU.dmu.ilu.d2p_ibc_req */
460 /* 0in known_driven -clock `ilu_clock
461 -reset !`ilu_warmreset
462 -var `CPU.dmu.ilu.p2d_ibc_ack */
463
464 /* 0in known_driven -clock `ilu_clock
465 -reset !`ilu_warmreset
466 -active `CPU.dmu.ilu.p2d_cto_req
467 -var `CPU.dmu.ilu.p2d_cto_tag */
468 /* 0in known_driven -clock `ilu_clock
469 -reset !`ilu_warmreset
470 -var `CPU.dmu.ilu.p2d_cto_req */
471 /* 0in known_driven -clock `ilu_clock
472 -reset !`ilu_warmreset
473 -var `CPU.dmu.ilu.d2p_cto_ack */
474
475 /* 0in known_driven -clock `ilu_clock
476 -reset !`ilu_warmreset
477 -var `CPU.dmu.ilu.p2d_ue_int */
478 /* 0in known_driven -clock `ilu_clock
479 -reset !`ilu_warmreset
480 -var `CPU.dmu.ilu.p2d_ce_int */
481 /* 0in known_driven -clock `ilu_clock
482 -reset !`ilu_warmreset
483 -var `CPU.dmu.ilu.p2d_oe_int */
484
485 /* 0in known_driven -clock `ilu_clock
486 -reset !`ilu_warmreset
487 -var `CPU.dmu.ilu.d2p_ech_wptr */
488 /* 0in known_driven -clock `ilu_clock
489 -reset !`ilu_warmreset
490 -var `CPU.dmu.ilu.p2d_ech_rptr */
491 /* 0in known_driven -clock `ilu_clock
492 -reset !`ilu_warmreset
493 -var `CPU.dmu.ilu.d2p_erh_wptr */
494 /* 0in known_driven -clock `ilu_clock
495 -reset !`ilu_warmreset
496 -var `CPU.dmu.ilu.p2d_erh_rptr */
497
498 /* 0in known_driven -clock `ilu_clock
499 -reset !`ilu_warmreset
500 -var `CPU.dmu.ilu.p2d_ecd_rptr */
501 /* 0in known_driven -clock `ilu_clock
502 -reset !`ilu_warmreset
503 -var `CPU.dmu.ilu.p2d_erd_rptr */
504 /* 0in known_driven -clock `ilu_clock
505 -reset !`ilu_warmreset
506 -var `CPU.dmu.ilu.d2p_edb_addr
507 -active `CPU.dmu.ilu.d2p_edb_we */
508 //---------------------------------------------------------------------
509 // 250 MHz domain
510 //---------------------------------------------------------------------
511 /* 0in known_driven -clock `peu_clock
512 -reset !`peu_warmreset
513 -var `PEU.d2p_ihb_addr */
514 /* 0in known_driven -clock `peu_clock
515 -reset !`peu_warmreset
516 -var `PEU.p2d_ihb_wptr */
517
518 /* 0in known_driven -clock `peu_clock
519 -reset !`peu_warmreset
520 -var `PEU.d2p_idb_addr */
521
522 /* 0in known_driven -clock `peu_clock
523 -reset !`peu_warmreset
524 -active `PEU.d2p_ibc_req
525 -var `PEU.d2p_ibc_nhc */
526 /* 0in known_driven -clock `peu_clock
527 -reset !`peu_warmreset
528 -active `PEU.d2p_ibc_req
529 -var `PEU.d2p_ibc_phc */
530 /* 0in known_driven -clock `peu_clock
531 -reset !`peu_warmreset
532 -active `PEU.d2p_ibc_req
533 -var `PEU.d2p_ibc_pdc */
534 /* 0in known_driven -clock `peu_clock
535 -reset !`peu_warmreset
536 -var `PEU.d2p_ibc_req */
537 /* 0in known_driven -clock `peu_clock
538 -reset !`peu_warmreset
539 -var `PEU.p2d_ibc_ack */
540
541 /* 0in known_driven -clock `peu_clock
542 -reset !`peu_warmreset
543 -active `PEU.p2d_cto_req
544 -var `PEU.p2d_cto_tag */
545 /* 0in known_driven -clock `peu_clock
546 -reset !`peu_warmreset
547 -var `PEU.p2d_cto_req */
548 /* 0in known_driven -clock `peu_clock
549 -reset !`peu_warmreset
550 -var `PEU.d2p_cto_ack */
551
552 /* 0in known_driven -clock `peu_clock
553 -reset !`peu_warmreset
554 -var `PEU.p2d_ue_int */
555 /* 0in known_driven -clock `peu_clock
556 -reset !`peu_warmreset
557 -var `PEU.p2d_ce_int */
558 /* 0in known_driven -clock `peu_clock
559 -reset !`peu_warmreset
560 -var `PEU.p2d_oe_int */
561
562 /* 0in known_driven -clock `peu_clock
563 -reset !`peu_warmreset
564 -var `PEU.d2p_ech_wptr */
565 /* 0in known_driven -clock `peu_clock
566 -reset !`peu_warmreset
567 -var `PEU.p2d_ech_rptr */
568 /* 0in known_driven -clock `peu_clock
569 -reset !`peu_warmreset
570 -var `PEU.d2p_erh_wptr */
571 /* 0in known_driven -clock `peu_clock
572 -reset !`peu_warmreset
573 -var `PEU.p2d_erh_rptr */
574
575 /* 0in known_driven -clock `peu_clock
576 -reset !`peu_warmreset
577 -var `PEU.p2d_ecd_rptr */
578 /* 0in known_driven -clock `peu_clock
579 -reset !`peu_warmreset
580 -var `PEU.p2d_erd_rptr */
581 /* 0in known_driven -clock `peu_clock
582 -reset !`peu_warmreset
583 -var `PEU.d2p_edb_addr
584 -active `PEU.d2p_edb_we */
585
586 // 0in disable_checker -name cpu.peu.peu_ptl.etl.hcs.fifo_request.enq_deq 1
587 /* 0in fifo
588 -name etl_hcs_fifo_request_enq_deq1
589 -enq `PEU.peu_ptl.etl.hcs.fifo_request.enq
590 -deq `PEU.peu_ptl.etl.hcs.fifo_request.deq
591 -enq_data `PEU.peu_ptl.etl.hcs.fifo_request.di
592 -deq_data `PEU.peu_ptl.etl.hcs.fifo_request.do
593 -depth 2
594 -clock `PEU.peu_ptl.etl.hcs.fifo_request.clk
595 -reset ~`PEU.peu_ptl.etl.hcs.fifo_request.rst_l
596 -module peu
597 */
598
599 // 0in disable_checker -name cpu.peu.peu_ptl.etl.hcs.fifo_completion.enq_deq 1
600 /* 0in fifo
601 -name etl_hcs_fifo_completion_enq_deq1
602 -enq `PEU.peu_ptl.etl.hcs.fifo_completion.enq
603 -deq `PEU.peu_ptl.etl.hcs.fifo_completion.deq
604 -enq_data `PEU.peu_ptl.etl.hcs.fifo_completion.di
605 -deq_data `PEU.peu_ptl.etl.hcs.fifo_completion.do
606 -depth 2
607 -clock `PEU.peu_ptl.etl.hcs.fifo_completion.clk
608 -reset ~`PEU.peu_ptl.etl.hcs.fifo_completion.rst_l
609 -module peu
610 */
611
612 // 0in disable_checker -name cpu.peu.peu_ptl.rsb.rsb_rar.et2rs_ld_tx 1
613 /* 0in scoreboard
614 -name et2rs_ld_tx1
615 -rx_id etl_ld_tag
616 -rx et2rs_ld
617 -tx_id itl_chk_tag
618 -tx (it2rs_vld & ~n_rs2it_err)
619 -flush_id work_tag
620 -flush vld_clr
621 -max_ids 16
622 -known_flush on
623 -max_count_per_id 1
624 -reset ~`PEU.peu_ptl.etl.ct2et_rst_l
625 -module ptl_rsb_rar
626 */
627
628 // 0in disable_checker -name cpu.peu.peu_ptl.edb.ptl_edb_async_ram_chk 1
629 /* 0in multi_clock_fifo
630 -name ptl_edb_async_ram_chk1
631 -depth 256
632 -enq edb_ram_wr_en
633 -enq_clock d2p_edb_clk
634 -deq edb_ram_rd_en
635 -deq_clock clk
636 -enq_reset ~`PEU.peu_ptl.etl.ct2et_rst_l
637 -deq_reset ~`PEU.peu_ptl.etl.ct2et_rst_l
638 -module ptl_edb
639 */
640
641 // 0in disable_checker -name cpu.dmu.ilu.iil.xfrfsm.zivar 1
642 /* 0in assert -var `CPU.dmu.ilu.iil.xfrfsm.isb2iil_vld
643 -active (((`CPU.dmu.ilu.iil.xfrfsm.is_ihb_rcd &
644 `CPU.dmu.ilu.iil.xfrfsm.ihb_rcd_is_cpl) |
645 `CPU.dmu.ilu.iil.xfrfsm.is_cto_rcd_ps2 ) &
646 ~`CPU.dmu.ilu.iil.cib2iil_pec_drain &
647 ~`CPU.dmu.ilu.iil.cib2iil_ihb_pe_drain)
648 -clock `ilu_clock
649
650 */
651
652
653endmodule
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