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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / checkers / l2 / l2_mh_chkr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2_mh_chkr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module l2_mh_chkr();
36
37///////////////////////////////////////////////////////////////////////////////
38// These signals can be used to disable certain 0-In checkers at runtime,
39// so that testcases forcing interface errors don't die with checker firings.
40///////////////////////////////////////////////////////////////////////////////
41
42// 0in set_clock -default l2clk -module cpu
43
44
45/* 0in
46 mutex -var {dirvec.dc_cam_hit_c6[35:32], dirvec.ic_cam_hit_c6[7:0]}
47 -name multi_hit_chkr_2
48 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
49 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
50 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
51 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
52 -module l2t
53*/
54/* 0in
55 mutex -var {dirvec.dc_cam_hit_c6[3:0], dirvec.ic_cam_hit_c6[7:0]}
56 -name multi_hit_chkr_1
57 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
58 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
59 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
60 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
61 -module l2t
62*/
63/* 0in
64 mutex -var {dirvec.dc_cam_hit_c6[7:4], dirvec.ic_cam_hit_c6[15:8]}
65 -name multi_hit_chkr_3
66 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
67 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
68 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
69 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
70 -module l2t
71*/
72/* 0in
73 mutex -var {dirvec.dc_cam_hit_c6[39:36], dirvec.ic_cam_hit_c6[15:8]}
74 -name multi_hit_chkr_4
75 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
76 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
77 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
78 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
79 -module l2t
80*/
81/* 0in
82 mutex -var {dirvec.dc_cam_hit_c6[11:8], dirvec.ic_cam_hit_c6[23:16]}
83 -name multi_hit_chkr_5
84 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
85 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
86 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
87 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
88 -module l2t
89*/
90
91/* 0in
92 mutex -var {dirvec.dc_cam_hit_c6[43:40], dirvec.ic_cam_hit_c6[23:16]}
93 -name multi_hit_chkr_6
94 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
95 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
96 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
97 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
98 -module l2t
99*/
100/* 0in
101 mutex -var {dirvec.dc_cam_hit_c6[15:12], dirvec.ic_cam_hit_c6[31:24]}
102 -name multi_hit_chkr_7
103 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
104 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
105 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
106 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
107 -module l2t
108*/
109/* 0in
110 mutex -var {dirvec.dc_cam_hit_c6[47:44], dirvec.ic_cam_hit_c6[31:24]}
111 -name multi_hit_chkr_8
112 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
113 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
114 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
115 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
116 -module l2t
117*/
118/* 0in
119 mutex -var {dirvec.dc_cam_hit_c6[19:16], dirvec.ic_cam_hit_c6[39:32]}
120 -name multi_hit_chkr_9
121 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
122 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
123 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
124 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
125 -module l2t
126*/
127/* 0in
128 mutex -var {dirvec.dc_cam_hit_c6[51:48], dirvec.ic_cam_hit_c6[39:32]}
129 -name multi_hit_chkr_10
130 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
131 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
132 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
133 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
134 -module l2t
135*/
136/* 0in
137 mutex -var {dirvec.dc_cam_hit_c6[23:20], dirvec.ic_cam_hit_c6[47:40]}
138 -name multi_hit_chkr_11
139 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
140 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
141 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
142 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
143 -module l2t
144*/
145/* 0in
146 mutex -var {dirvec.dc_cam_hit_c6[55:52], dirvec.ic_cam_hit_c6[47:40]}
147 -name multi_hit_chkr_12
148 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
149 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
150 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
151 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
152 -module l2t
153*/
154
155/* 0in
156 mutex -var {dirvec.dc_cam_hit_c6[27:24], dirvec.ic_cam_hit_c6[55:48]}
157 -name multi_hit_chkr_13
158 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
159 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
160 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
161 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
162 -module l2t
163*/
164/* 0in
165 mutex -var {dirvec.dc_cam_hit_c6[59:56], dirvec.ic_cam_hit_c6[55:48]}
166 -name multi_hit_chkr_14
167 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
168 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
169 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
170 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
171 -module l2t
172*/
173/* 0in
174 mutex -var {dirvec.dc_cam_hit_c6[31:28], dirvec.ic_cam_hit_c6[63:56]}
175 -name multi_hit_chkr_15
176 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
177 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
178 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
179 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
180 -module l2t
181*/
182/* 0in
183 mutex -var {dirvec.dc_cam_hit_c6[63:60], dirvec.ic_cam_hit_c6[63:56]}
184 -name multi_hit_chkr_16
185 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
186 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
187 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
188 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
189 -module l2t
190*/
191/* 0in
192 mutex -var {dirvec.dc_cam_hit_c6[67:64], dirvec.ic_cam_hit_c6[71:64]}
193 -name multi_hit_chkr_17
194 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
195 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
196 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
197 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
198 -module l2t
199*/
200/* 0in
201 mutex -var {dirvec.dc_cam_hit_c6[99:96], dirvec.ic_cam_hit_c6[71:64]}
202 -name multi_hit_chkr_18
203 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
204 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
205 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
206 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
207 -module l2t
208*/
209/* 0in
210 mutex -var {dirvec.dc_cam_hit_c6[71:68], dirvec.ic_cam_hit_c6[79:72]}
211 -name multi_hit_chkr_19
212 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
213 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
214 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
215 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
216 -module l2t
217*/
218/* 0in
219 mutex -var {dirvec.dc_cam_hit_c6[103:100], dirvec.ic_cam_hit_c6[79:72]}
220 -name multi_hit_chkr_20
221 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
222 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
223 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
224 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
225 -module l2t
226*/
227/* 0in
228 mutex -var {dirvec.dc_cam_hit_c6[75:72], dirvec.ic_cam_hit_c6[87:80]}
229 -name multi_hit_chkr_21
230 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
231 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
232 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
233 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
234 -module l2t
235*/
236/* 0in
237 mutex -var {dirvec.dc_cam_hit_c6[107:104], dirvec.ic_cam_hit_c6[87:80]}
238 -name multi_hit_chkr_22
239 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
240 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
241 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
242 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
243 -module l2t
244*/
245/* 0in
246 mutex -var {dirvec.dc_cam_hit_c6[79:76], dirvec.ic_cam_hit_c6[95:88]}
247 -name multi_hit_chkr_23
248 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
249 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
250 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
251 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
252 -module l2t
253*/
254/* 0in
255 mutex -var {dirvec.dc_cam_hit_c6[111:108], dirvec.ic_cam_hit_c6[95:88]}
256 -name multi_hit_chkr_24
257 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
258 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
259 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
260 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
261 -module l2t
262*/
263/* 0in
264 mutex -var {dirvec.dc_cam_hit_c6[83:80], dirvec.ic_cam_hit_c6[103:96]}
265 -name multi_hit_chkr_25
266 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
267 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
268 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
269 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
270 -module l2t
271*/
272
273/* 0in
274 mutex -var {dirvec.dc_cam_hit_c6[115:112], dirvec.ic_cam_hit_c6[103:96]}
275 -name multi_hit_chkr_26
276 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
277 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
278 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
279 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
280 -module l2t
281*/
282
283/* 0in
284 mutex -var {dirvec.dc_cam_hit_c6[87:84], dirvec.ic_cam_hit_c6[111:104]}
285 -name multi_hit_chkr_27
286 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
287 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
288 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
289 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
290 -module l2t
291*/
292/* 0in
293 mutex -var {dirvec.dc_cam_hit_c6[119:116], dirvec.ic_cam_hit_c6[111:104]}
294 -name multi_hit_chkr_28
295 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
296 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
297 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
298 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
299 -module l2t
300*/
301/* 0in
302 mutex -var {dirvec.dc_cam_hit_c6[91:88], dirvec.ic_cam_hit_c6[119:112]}
303 -name multi_hit_chkr_29
304 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
305 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
306 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
307 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
308 -module l2t
309*/
310/* 0in
311 mutex -var {dirvec.dc_cam_hit_c6[123:120], dirvec.ic_cam_hit_c6[119:112]}
312 -name multi_hit_chkr_30
313 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
314 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
315 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
316 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
317 -module l2t
318*/
319/* 0in
320 mutex -var {dirvec.dc_cam_hit_c6[95:92], dirvec.ic_cam_hit_c6[127:120]}
321 -name multi_hit_chkr_31
322 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
323 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
324 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
325 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
326 -module l2t
327*/
328/* 0in
329 mutex -var {dirvec.dc_cam_hit_c6[127:124], dirvec.ic_cam_hit_c6[127:120]}
330 -name multi_hit_chkr_32
331 -active $0in_delay((dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
332 dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
333 dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
334 dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
335 -module l2t
336*/
337
338
339
340
341/* x0in
342 mutex -var {l2sat_top.cpu.l2t0.dirvec.dc_cam_hit_c6[3:0], l2sat_top.cpu.l2t0.dirvec.ic_cam_hit_c6[35:32], l2sat_top.cpu.l2t0.dirvec.ic_cam_hit[3:0]}
343 -name multi_hit_chkr_1
344 -active $0in_delay((l2sat_top.cpu.l2t0.dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
345 l2sat_top.cpu.l2t0.dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
346 l2sat_top.cpu.l2t0.dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
347 l2sat_top.cpu.l2t0.dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
348 -clock l2sat_top.cpu.l2clk
349*/
350/* x0in
351 mutex -var {l2sat_top.cpu.l2t0.dirvec.dc_cam_hit_c6[7:4], l2sat_top.cpu.l2t0.dirvec.ic_cam_hit_c6[39:36], l2sat_top.cpu.l2t0.dirvec.ic_cam_hit_c6[7:4]}
352 -name multi_hit_chkr_2
353 -active $0in_delay((l2sat_top.cpu.l2t0.dirrep.dirrep_dc_lkup_panel_dec_c4 != 0 &&
354 l2sat_top.cpu.l2t0.dirrep.dirrep_dc_lkup_row_dec_c4 != 0 ||
355 l2sat_top.cpu.l2t0.dirrep.dirrep_ic_lkup_panel_dec_c4 != 0 &&
356 l2sat_top.cpu.l2t0.dirrep.dirrep_ic_lkup_row_dec_c4 != 0), 3)
357 -clock l2sat_top.cpu.l2clk
358*/
359
360endmodule //l2_mh_chkr
Full OpenSPARC design & verification tarball including full HDL.