projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ncu_rtl_chkr.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module ncu_rtl_chkr(); | |
| 36 | ||
| 37 | // 0in default_reset `NCU.tcu_aclk -module ncu_rtl_chkr | |
| 38 | ||
| 39 | /* 0in bits_on | |
| 40 | -var {ncu_man_acc,ncu_asi_a_acc,ncu_asi_b_acc} | |
| 41 | -max 1 | |
| 42 | -message "first register decoder is not one hot" | |
| 43 | -clock iol2clk | |
| 44 | -module ncu_ctrl_ctl | |
| 45 | -name cov_reg_first_decod | |
| 46 | */ | |
| 47 | ||
| 48 | /* 0in bits_on | |
| 49 | -var { asi_coreavail_dec,asi_core_enable_status_dec,asi_core_enable_dec, | |
| 50 | asi_xir_steering_dec, asi_core_running_dec, asi_core_running_status_dec, | |
| 51 | asi_core_runningw1s_dec, asi_core_runningw1c_dec, asi_intvecdisp_dec} | |
| 52 | -max 1 | |
| 53 | -message "first register decoder is not one hot" | |
| 54 | -clock iol2clk | |
| 55 | -module ncu_ctrl_ctl | |
| 56 | -name cov_reg_asi_decod | |
| 57 | */ | |
| 58 | /* 0in bits_on | |
| 59 | -var { creg_esr_dec, creg_ele_dec, creg_eie_dec, | |
| 60 | creg_ejr_dec, creg_fee_dec, creg_per_dec, creg_siisyn_dec, | |
| 61 | creg_ncusyn_dec} | |
| 62 | -max 1 | |
| 63 | -message "first register decoder is not one hot" | |
| 64 | -clock iol2clk | |
| 65 | -module ncu_ctrl_ctl | |
| 66 | -name cov_reg_ras_decod | |
| 67 | */ | |
| 68 | /* 0in bits_on | |
| 69 | -var {creg_intman_dec, creg_sernum_dec, creg_coreavail_dec, creg_fusestat_dec, | |
| 70 | creg_bankavail_dec, creg_bank_en_dec,creg_bank_en_status_dec,creg_l2idxhs_en_dec, | |
| 71 | creg_l2idxhs_en_status_dec,creg_mondoinvec_dec,creg_mem32_base_dec,creg_mem32_mask_dec, | |
| 72 | creg_mem64_base_dec,creg_mem64_mask_dec,creg_iocon_base_dec,creg_iocon_mask_dec, | |
| 73 | creg_mmufsh_dec} | |
| 74 | -max 1 | |
| 75 | -message "first register decoder is not one hot" | |
| 76 | -clock iol2clk | |
| 77 | -module ncu_ctrl_ctl | |
| 78 | -name cov_reg_second_decod | |
| 79 | */ | |
| 80 | ||
| 81 | /* 0in bits_on | |
| 82 | -var {wake_thread,asi_core_runningw1s_wr, asi_core_running_wr,asi_core_runningw1c_wr} | |
| 83 | -max 1 | |
| 84 | -message "first register decoder is not one hot" | |
| 85 | -clock iol2clk | |
| 86 | -module ncu_ctrl_ctl | |
| 87 | -name cov_reg_run | |
| 88 | */ | |
| 89 | ||
| 90 | /* 0in value | |
| 91 | -var xir_mini_vec | |
| 92 | -val 8'bxxxx_xxx1 8'bxxxx_xx10 8'bxxxx_x100 8'bxxxx_1000 8'bxxx1_0000 8'bxx10_0000 8'bx100_0000 8'b1000_0000 8'b0000_0000 | |
| 93 | -casex | |
| 94 | -clock iol2clk | |
| 95 | -module ncu_ctrl_ctl | |
| 96 | -name cov_xir_mini_vec | |
| 97 | */ | |
| 98 | ||
| 99 | /* 0in value | |
| 100 | -var {coreavail_done,~asi_core_en_wr,c2i_core_en_a0} | |
| 101 | -val 3'b1xx 3'b000 3'b01x 3'b001 | |
| 102 | -casex | |
| 103 | -clock iol2clk | |
| 104 | -module ncu_ctrl_ctl | |
| 105 | -name cov_ncu_core_avail_enable_dec_chk | |
| 106 | ||
| 107 | */ | |
| 108 | ||
| 109 | /* 0in value | |
| 110 | -var {coreavail_done,wmr_upd_en} | |
| 111 | -val 2'b1x 2'b01 2'b00 | |
| 112 | -casex | |
| 113 | -clock iol2clk | |
| 114 | -module ncu_ctrl_ctl | |
| 115 | -name cov_ncu_en_enstatus_dec_chk | |
| 116 | */ | |
| 117 | ||
| 118 | /* 0in value | |
| 119 | -var {coreavail_done_d1,asi_xir_steering_wr} | |
| 120 | -val 2'b1x 2'b01 2'b00 | |
| 121 | -casex | |
| 122 | -clock iol2clk | |
| 123 | -module ncu_ctrl_ctl | |
| 124 | -name cov_ncu_xir_reg_dec_chk | |
| 125 | */ | |
| 126 | ||
| 127 | /* 0in value | |
| 128 | -var {wake_thread,asi_core_runningw1s_wr, asi_core_running_wr,asi_core_runningw1c_wr} | |
| 129 | -val 4'b1xxx 4'b01xx 4'b001x 4'b0001 4'b0000 | |
| 130 | -casex | |
| 131 | -clock iol2clk | |
| 132 | -module ncu_ctrl_ctl | |
| 133 | -name cov_ncu_run_reg_dec_chk | |
| 134 | */ | |
| 135 | /* 0in value | |
| 136 | -var {bankavail_done,~bank_en_wr,c2i_bank_en_a0} | |
| 137 | -val 3'b1xx 3'b000 3'b01x 3'b001 | |
| 138 | -casex | |
| 139 | -clock iol2clk | |
| 140 | -module ncu_ctrl_ctl | |
| 141 | -name cov_ncu_bank_reg_dec_chk | |
| 142 | */ | |
| 143 | ||
| 144 | ||
| 145 | /* 0in range | |
| 146 | -var sii_rcv_cntr | |
| 147 | -min 0 | |
| 148 | -max 5 | |
| 149 | -clock iol2clk | |
| 150 | -module ncu_i2cbufsii_ctl | |
| 151 | -name cov_ncu_sii_rcv_cntr_chk | |
| 152 | */ | |
| 153 | ||
| 154 | ||
| 155 | /* 0in range | |
| 156 | -var cpx_cnt0 | |
| 157 | -min 0 | |
| 158 | -max 2 | |
| 159 | -clock l2clk | |
| 160 | -module ncu_i2cfc_ctl | |
| 161 | -name cov_cpx_cnt0_chk | |
| 162 | */ | |
| 163 | /* 0in value | |
| 164 | -var {cpx_cnt0_minus1_sel,cpx_cnt0_plus1_sel} | |
| 165 | -val 2'b10 2'b01 2'b00 | |
| 166 | -casex | |
| 167 | -clock l2clk | |
| 168 | -module ncu_i2cfc_ctl | |
| 169 | -name cov_ncu_cnt0_ctrl_chk | |
| 170 | */ | |
| 171 | /* 0in range | |
| 172 | -var cpx_cnt1 | |
| 173 | -min 0 | |
| 174 | -max 2 | |
| 175 | -clock l2clk | |
| 176 | -module ncu_i2cfc_ctl | |
| 177 | -name cov_cpx_cnt1_chk | |
| 178 | */ | |
| 179 | /* 0in value | |
| 180 | -var {cpx_cnt1_minus1_sel,cpx_cnt1_plus1_sel} | |
| 181 | -val 2'b10 2'b01 2'b00 | |
| 182 | -casex | |
| 183 | -clock l2clk | |
| 184 | -module ncu_i2cfc_ctl | |
| 185 | -name cov_ncu_cnt1_ctrl_chk | |
| 186 | */ | |
| 187 | /* 0in range | |
| 188 | -var cpx_cnt2 | |
| 189 | -min 0 | |
| 190 | -max 2 | |
| 191 | -clock l2clk | |
| 192 | -module ncu_i2cfc_ctl | |
| 193 | -name cov_cpx_cnt2_chk | |
| 194 | */ | |
| 195 | /* 0in value | |
| 196 | -var {cpx_cnt2_minus1_sel,cpx_cnt2_plus1_sel} | |
| 197 | -val 2'b10 2'b01 2'b00 | |
| 198 | -casex | |
| 199 | -clock l2clk | |
| 200 | -module ncu_i2cfc_ctl | |
| 201 | -name cov_ncu_cnt2_ctrl_chk | |
| 202 | */ | |
| 203 | /* 0in range | |
| 204 | -var cpx_cnt3 | |
| 205 | -min 0 | |
| 206 | -max 2 | |
| 207 | -clock l2clk | |
| 208 | -module ncu_i2cfc_ctl | |
| 209 | -name cov_cpx_cnt3_chk | |
| 210 | */ | |
| 211 | /* 0in value | |
| 212 | -var {cpx_cnt3_minus1_sel,cpx_cnt3_plus1_sel} | |
| 213 | -val 2'b10 2'b01 2'b00 | |
| 214 | -casex | |
| 215 | -clock l2clk | |
| 216 | -module ncu_i2cfc_ctl | |
| 217 | -name cov_ncu_cnt3_ctrl_chk | |
| 218 | */ | |
| 219 | /* 0in range | |
| 220 | -var cpx_cnt4 | |
| 221 | -min 0 | |
| 222 | -max 2 | |
| 223 | -clock l2clk | |
| 224 | -module ncu_i2cfc_ctl | |
| 225 | -name cov_cpx_cnt4_chk | |
| 226 | */ | |
| 227 | /* 0in value | |
| 228 | -var {cpx_cnt4_minus1_sel,cpx_cnt4_plus1_sel} | |
| 229 | -val 2'b10 2'b01 2'b00 | |
| 230 | -casex | |
| 231 | -clock l2clk | |
| 232 | -module ncu_i2cfc_ctl | |
| 233 | -name cov_ncu_cnt4_ctrl_chk | |
| 234 | */ | |
| 235 | /* 0in range | |
| 236 | -var cpx_cnt5 | |
| 237 | -min 0 | |
| 238 | -max 2 | |
| 239 | -clock l2clk | |
| 240 | -module ncu_i2cfc_ctl | |
| 241 | -name cov_cpx_cnt5_chk | |
| 242 | */ | |
| 243 | /* 0in value | |
| 244 | -var {cpx_cnt5_minus1_sel,cpx_cnt5_plus1_sel} | |
| 245 | -val 2'b10 2'b01 2'b00 | |
| 246 | -casex | |
| 247 | -clock l2clk | |
| 248 | -module ncu_i2cfc_ctl | |
| 249 | -name cov_ncu_cnt5_ctrl_chk | |
| 250 | */ | |
| 251 | /* 0in range | |
| 252 | -var cpx_cnt6 | |
| 253 | -min 0 | |
| 254 | -max 2 | |
| 255 | -clock l2clk | |
| 256 | -module ncu_i2cfc_ctl | |
| 257 | -name cov_cpx_cnt6_chk | |
| 258 | */ | |
| 259 | /* 0in value | |
| 260 | -var {cpx_cnt6_minus1_sel,cpx_cnt6_plus1_sel} | |
| 261 | -val 2'b10 2'b01 2'b00 | |
| 262 | -casex | |
| 263 | -clock l2clk | |
| 264 | -module ncu_i2cfc_ctl | |
| 265 | -name cov_ncu_cnt6_ctrl_chk | |
| 266 | */ | |
| 267 | /* 0in range | |
| 268 | -var cpx_cnt7 | |
| 269 | -min 0 | |
| 270 | -max 2 | |
| 271 | -clock l2clk | |
| 272 | -module ncu_i2cfc_ctl | |
| 273 | -name cov_cpx_cnt7_chk | |
| 274 | */ | |
| 275 | /* 0in value | |
| 276 | -var {cpx_cnt7_minus1_sel,cpx_cnt7_plus1_sel} | |
| 277 | -val 2'b10 2'b01 2'b00 | |
| 278 | -casex | |
| 279 | -clock l2clk | |
| 280 | -module ncu_i2cfc_ctl | |
| 281 | -name cov_ncu_cnt7_ctrl_chk | |
| 282 | */ | |
| 283 | ||
| 284 | ||
| 285 | /* 0in bits_on | |
| 286 | -var int_sel | |
| 287 | -max 1 | |
| 288 | -clock iol2clk | |
| 289 | -module ncu_i2csd_ctl | |
| 290 | -name cov_ncu_int_sel_chk | |
| 291 | */ | |
| 292 | /* 0in bits_on | |
| 293 | -var ack_sel | |
| 294 | -max 1 | |
| 295 | -clock iol2clk | |
| 296 | -module ncu_i2csd_ctl | |
| 297 | -name cov_ncu_ack_sel_chk | |
| 298 | */ | |
| 299 | ||
| 300 | /* 0in value | |
| 301 | -var snapd_int_vec | |
| 302 | -val 7'b1xx_xxxx 7'b01x_xxxx 7'b001_xxxx 7'b000_1xxx | |
| 303 | 7'b000_01xx 7'b000_001x 7'b000_0001 7'h000_0000 | |
| 304 | -casex | |
| 305 | -clock iol2clk | |
| 306 | -module ncu_i2csc_ctl | |
| 307 | -name cov_ncu_snapd_int_vec | |
| 308 | */ | |
| 309 | /* 0in value | |
| 310 | -var snapd_ack_vec | |
| 311 | -val 15'b1xx_xxxx_xxxx_xxxx 15'b01x_xxxx_xxxx_xxxx 15'b001_xxxx_xxxx_xxxx | |
| 312 | 15'b000_1xxx_xxxx_xxxx 15'b000_01xx_xxxx_xxxx 15'b000_001x_xxxx_xxxx | |
| 313 | 15'b000_0001_xxxx_xxxx 15'b000_0000_1xxx_xxxx 15'b000_0000_01xx_xxxx | |
| 314 | 15'b000_0000_001x_xxxx 15'b000_0000_0001_xxxx 15'b000_0000_0000_1xxx | |
| 315 | 15'b000_0000_0000_01xx 15'b000_0000_0000_001x 15'b000_0000_0000_0001 | |
| 316 | 15'b000_0000_0000_0000 | |
| 317 | -casex | |
| 318 | -clock iol2clk | |
| 319 | -module ncu_i2csc_ctl | |
| 320 | -name cov_ncu_snapd_ack_vec | |
| 321 | */ | |
| 322 | ||
| 323 | /* 0in bits_on | |
| 324 | -var {ssi_int_rd, mcu0_int_rd,mcu1_int_rd,mcu2_int_rd,mcu3_int_rd,niu_int_rd,ncu_man_int_rd} | |
| 325 | -max 1 | |
| 326 | -clock iol2clk | |
| 327 | -module ncu_i2csc_ctl | |
| 328 | -name cov_ncu_io_int_dec_chk | |
| 329 | */ | |
| 330 | /* 0in bits_on | |
| 331 | -var {siipio_ack_rd, dmucsr_ack_rd,ccu_ack_rd,mcu0_ack_rd,mcu1_ack_rd,mcu2_ack_rd,mcu3_ack_rd, | |
| 332 | ssi_ack_rd, rcu_ack_rd, niu_ack_rd, ncu_man_ack_rd, ncu_int_ack_rd, | |
| 333 | bounce_ack_rd, rd_nack_rd} | |
| 334 | -max 1 | |
| 335 | -clock iol2clk | |
| 336 | -module ncu_i2csc_ctl | |
| 337 | -name cov_io_ack_dec_chk | |
| 338 | */ | |
| 339 | /* 0in range | |
| 340 | -var cr_id[3:0] | |
| 341 | -min 0 | |
| 342 | -max 15 | |
| 343 | -clock iol2clk | |
| 344 | -module ncu_c2ibufpio_ctl | |
| 345 | -name cov_ncu_cr_id_chk | |
| 346 | */ | |
| 347 | ||
| 348 | /* 0in bits_on | |
| 349 | -var {mmu_ld, pio_ld} | |
| 350 | -max 1 | |
| 351 | -clock iol2clk | |
| 352 | -module ncu_c2ibufpio_ctl | |
| 353 | -name cov_mmu_pio_arb_chk | |
| 354 | */ | |
| 355 | ||
| 356 | ||
| 357 | /* 0in range | |
| 358 | -var dmu_cr_id_rtn | |
| 359 | -min 0 | |
| 360 | -max 15 | |
| 361 | -clock iol2clk | |
| 362 | -module ncu_c2ibufpio_ctl | |
| 363 | -name cov_dmu_cr_id_rtn_chk | |
| 364 | */ | |
| 365 | /* 0in range | |
| 366 | -var sii_cr_id_rtn | |
| 367 | -min 0 | |
| 368 | -max 15 | |
| 369 | -clock iol2clk | |
| 370 | -module ncu_c2ibufpio_ctl | |
| 371 | -name cov_sii_cr_id_rtn_chk | |
| 372 | */ | |
| 373 | /* 0in bits_on | |
| 374 | -var {mcu0_ucb_sel,mcu1_ucb_sel,mcu2_ucb_sel,mcu3_ucb_sel,dmucsr_ucb_sel,dmupio_ucb_sel,ssi_ucb_sel,ccu_ucb_sel,rcu_ucb_sel,niu_ucb_sel, ncu_man_ucb_sel,ncu_int_ucb_sel, rd_nack_ucb_sel} | |
| 375 | -max 1 | |
| 376 | -clock iol2clk | |
| 377 | -module ncu_c2isc_ctl | |
| 378 | -name cov_ncu_io_sel_dec_chk | |
| 379 | */ | |
| 380 | /* 0in bits_on | |
| 381 | -var {c_creg_mdata0_alias_dec, c_creg_mdata1_alias_dec, c_creg_mbusy_alias_dec,c_creg_mdata0_proper_dec, c_creg_mdata1_proper_dec, c_creg_mbusy_proper_dec} | |
| 382 | -max 1 | |
| 383 | -clock l2clk | |
| 384 | -module ncu_c2ifc_ctl | |
| 385 | -name cov_ncu_cpu_mondo_dec | |
| 386 | */ | |
| 387 | /* 0in bits_on | |
| 388 | -var {t_creg_mdata0_alias_dec, t_creg_mdata1_alias_dec, t_creg_mbusy_alias_dec,t_creg_mdata0_proper_dec, t_creg_mdata1_proper_dec, t_creg_mbusy_proper_dec} | |
| 389 | -max 1 | |
| 390 | -clock l2clk | |
| 391 | -module ncu_c2ifc_ctl | |
| 392 | -name cov_ncu_tcu_mondo_dec | |
| 393 | */ | |
| 394 | endmodule |