Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / checkers / ncu / niu_ncu_intr_chkr.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_ncu_intr_chkr.v
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35module niu_ncu_intr_chkr ();
36
37// assemble interrupt back to CPU
38//assign int_iopkt[152:0] =
39// {// 1'b1, //valid [145]
40// int_iopkt_rt[3:0], //return type [144:141]
41// 1'b0, //un-used [140]
42// err_type[1:0], //err field [139:138], ue=10, ce=01
43// 1'b0, //un-used [137]
44// int_packet_cputhr_d2[2:0], //thr_id [136:134]
45// 6'b0, //un-used [133:128]
46// 64'b0, //un-used [127:64]
47// 48'b0, //un-used [63:16]
48// tt_d2[1:0], //tt [15:14]
49// int_iopkt_bit_13_8[5:0], //cputhr ID [13:8]
50// 2'b0, //un-used [7:6]
51// int_packet_vec_d2[5:0] }; //int vector [5:0]
52//n2_com_dp_128x16s_cust ncu_intman_rf_cust ( /*autoinst*/
53// // Outputs
54// .dout(intman_tbl_dout[15:0]), // Templated
55// // Inputs
56// .scan_in(ncu_intman_rf_cust_scanin),
57// .scan_out(ncu_intman_rf_cust_scanout),
58// .wrclk(iol2clk), // Templated
59// .rdclk(iol2clk), // Templated
60// .wr_en(intman_tbl_wr), // Templated
61// .rd_en(intman_tbl_rden), // Templated
62// .wr_adr(intman_tbl_waddr[6:0]), // Templated
63// .rd_adr(intman_tbl_raddr[6:0]), // Templated
64// .din(intman_tbl_din[15:0]), // Templated
65// .tcu_se_scancollar_in(tcu_se_scancollar_in),
66// .tcu_se_scancollar_out(tcu_se_scancollar_out),
67// .tcu_array_wr_inhibit(array_wr_inhibit_io),
68// .tcu_aclk(aclk_io),
69// .tcu_bclk(bclk_io),
70// .tcu_pce_ov(pce_ov),
71// .bist_clk_mux_sel(1'b0),
72// .rd_pce(1'b1),
73// .wr_pce(1'b1));
74
75reg niu_ncu_vld_d;
76reg niu_ncu_int_vld_d1;
77reg niu_ncu_int_vld_d2;
78reg [6:0] device_id_q;
79reg [15:0] intmem_tbl [127:0];
80reg [15:0] tbl_dout;
81reg [5:0] expected_intr_vec;
82reg [5:0] expected_cputhread;
83reg [7:0] c;
84
85wire niu_ncu_vld_pulse = `NCU.niu_ncu_vld & ~niu_ncu_vld_d;
86
87wire niu_ncu_int_vld = (niu_ncu_vld_pulse & (`NCU.niu_ncu_data[3:0] == 4'h8));
88
89wire ncu_cpx_vld = `CPU.ncu_cpx_data_ca[145] & (`CPU.ncu_cpx_data_ca[144:141] == 4'b0111) & (`CPU.ncu_cpx_data_ca[15:14] == 2'b00);
90
91wire [6:0] device_id_din = niu_ncu_vld_pulse ? `NCU.niu_ncu_data[16:10] : device_id_q;
92
93wire equal_compare = (`CPU.ncu_cpx_data_ca[136:134] == expected_cputhread[2:0]) & (`CPU.ncu_cpx_data_ca[13:8] == expected_cputhread[5:0]) & (`CPU.ncu_cpx_data_ca[7:6] == 2'b00) & (`CPU.ncu_cpx_data_ca[5:0] == expected_intr_vec[5:0]) & ncu_cpx_vld;
94
95/* 0in assert_follower
96 -leader ( $0in_rising_edge (niu_ncu_int_vld) )
97 -follower ( $0in_rising_edge (equal_compare) )
98 -max 1024
99 -clock `NCU.l2clk
100 -message "ERROR: mismatch cpu and thread id after niu_intr_vld packet"
101*/
102
103
104initial begin
105 niu_ncu_vld_d = 1'b0;
106 niu_ncu_int_vld_d1 = 1'b0;
107 niu_ncu_int_vld_d2 = 1'b0;
108 device_id_q = 7'b0;
109 for ( c=0; c<128; c=c+1)
110 intmem_tbl[c] = 16'b0;
111 tbl_dout[15:0] = 16'b0;
112 expected_intr_vec[5:0] = 6'b0;
113 expected_cputhread[5:0] = 6'b0;
114end
115
116always @ (posedge `NCU.iol2clk)
117 begin
118 niu_ncu_vld_d <= `NCU.niu_ncu_vld;
119
120 niu_ncu_int_vld_d1 <= niu_ncu_int_vld;
121
122 niu_ncu_int_vld_d2 <= niu_ncu_int_vld_d1;
123
124 device_id_q <= device_id_din[6:0];
125
126 if ( `NCU.intman_tbl_wr )
127 intmem_tbl[`NCU.intman_tbl_waddr[6:0]] <= `NCU.intman_tbl_din[15:0];
128
129 tbl_dout[15:0] <= intmem_tbl[device_id_q[6:0]];
130
131 expected_cputhread[5:0] <= niu_ncu_int_vld_d2 ? tbl_dout[11:6] : expected_cputhread[5:0];
132
133 expected_intr_vec[5:0] <= niu_ncu_int_vld_d2 ? tbl_dout[5:0] : expected_intr_vec[5:0];
134 end
135endmodule