projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / checkers / siudmu / dmu_siu_chkr.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_siu_chkr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef SIU
36`define TOP siu_top
37`else
38`define TOP tb_top
39`endif
40module dmu_siu_chkr();
41
42// set this to -constraint to constrain input signals to SIU
43`define SIU_CONSTRAINT
44// set this to -constraint to constrain input signals to DMU
45`define DMU_CONSTRAINT
46
47`define WRI_ORD_PST 7'b0100100
48`define WRM_ORD_PST 7'b0101100
49`define RDD_ORD_NPT 7'b0010100
50`define INT_ORD_NPT 7'b0000010
51`define PIO_BYP_NPT 7'b1x1x011
52
53`ifdef FC_BENCH
54`else
55`ifdef IOS
56// 0in set_clock iol2clk -default -module dmu
57`else
58// 0in set_clock ccu_io_out -default -module cpu
59`endif
60`endif
61
62`ifdef FC_BENCH
63`define TOP_DESIGN_DMU_INTF dmu
64`else
65`define TOP_DESIGN_DMU_INTF cpu
66`endif
67
68
69`ifdef FC_BENCH
70reg bid_chk_off;
71initial begin // {
72 @(posedge tb_top.cpu.ncu.iol2clk) ;
73 if ($test$plusargs("dmusiu_bid_chk_off"))
74 bid_chk_off <= 1;
75 else
76 bid_chk_off <= 0;
77end //}
78
79// 0in disable_checker bid_chk_off -name *dmu_bus_id*
80`endif
81
82///////////////////////////////////////////////////////////////////////////////
83// Check that all interface signals are not X or Z. This check can be disabled
84// by not including the +define+X_GUARD arg on the command line.
85///////////////////////////////////////////////////////////////////////////////
86`ifdef X_GUARD
87 // 0in known_driven -var dmu_sii_hdr_vld -name dmu_sii_hdr_vld_x_guard -module `TOP_DESIGN_DMU_INTF
88 // 0in known_driven -var dmu_sii_reqbypass -name dmu_sii_reqbypass_x_guard -module `TOP_DESIGN_DMU_INTF
89 // 0in known_driven -var dmu_sii_datareq -name dmu_sii_datareq_x_guard -module `TOP_DESIGN_DMU_INTF
90 // 0in known_driven -var dmu_sii_datareq16 -name dmu_sii_datareq16_x_guard -module `TOP_DESIGN_DMU_INTF
91 // 0in known_driven -var dmu_sii_data -name dmu_sii_data_x_guard -module `TOP_DESIGN_DMU_INTF
92 // 0in known_driven -var dmu_sii_parity -name dmu_sii_parity_x_guard -module `TOP_DESIGN_DMU_INTF
93 // 0in known_driven -var dmu_sii_be -name dmu_sii_be_x_guard -module `TOP_DESIGN_DMU_INTF
94 // 0in known_driven -var sii_dmu_wrack_vld -name sii_dmu_wrack_vld_x_guard -module `TOP_DESIGN_DMU_INTF
95 // 0in known_driven -var sii_dmu_wrack_tag -name sii_dmu_wrack_tag_x_guard -module `TOP_DESIGN_DMU_INTF
96
97 // 0in known_driven -var sio_dmu_hdr_vld -name sio_dmu_hdr_vld_x_guard -module `TOP_DESIGN_DMU_INTF
98 // 0in known_driven -var sio_dmu_data -name sio_dmu_data_x_guard -module `TOP_DESIGN_DMU_INTF
99 // 0in known_driven -var sio_dmu_parity -name sio_dmu_parity_x_guard -module `TOP_DESIGN_DMU_INTF
100`endif
101
102`define DMU_SII_COMMAND {dmu_sii_data[127:122], dmu_sii_reqbypass}
103`define DMC_TAG dmu_sii_data[79:64]
104
105///////////////////////////////////////////////////////////////////////////////
106// Check for valid commands from DMU to SIU
107///////////////////////////////////////////////////////////////////////////////
108
109 /* 0in value -var `DMU_SII_COMMAND -casex
110 -val `WRI_ORD_PST `WRM_ORD_PST `RDD_ORD_NPT `INT_ORD_NPT `PIO_BYP_NPT
111 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF -name dmu_sii_hdr_cmd_vld
112 -message "Bad value for dmu_siu header"
113 `SIU_CONSTRAINT
114 */
115
116
117 // check for reserved bits of header
118 /* 0in value
119 -var {dmu_sii_data[121:85],dmu_sii_data[63], dmu_sii_data[55:40], dmu_sii_data[5:0]}
120 -val 0
121 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF -name dmu_sii_hdr_rsrvd_bits
122 -message "reserved bits in header are not all zero"
123 `SIU_CONSTRAINT
124 */
125
126
127///////////////////////////////////////////////////////////////////////////////
128// Check for no overlap of transactions:
129// 1. After dmu_sii_hdr_vld & dmu_sii_datareq16,
130// dmu_sii_hdr_vld and datareq signals are 0 for 1 cycle.
131// 2. After dmu_sii_datareq and not dmu_sii_datareq16,
132// dmu_sii_hdr_vld and datareq signals are 0 for 4 cycles.
133///////////////////////////////////////////////////////////////////////////////
134
135 /* 0in assert_window
136 -start (dmu_sii_hdr_vld & dmu_sii_datareq16)
137 -start_count 0
138 -stop_count 1
139 -not_in dmu_sii_hdr_vld dmu_sii_datareq16 dmu_sii_datareq
140 -module `TOP_DESIGN_DMU_INTF -name dmu_siu_no_overlap_chk1 `SIU_CONSTRAINT
141 */
142
143 /* 0in assert_window
144 -start (dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16)
145 -start_count 0
146 -stop_count 4
147 -not_in dmu_sii_hdr_vld dmu_sii_datareq16 dmu_sii_datareq
148 -module `TOP_DESIGN_DMU_INTF -name dmu_siu_no_overlap_chk2 `SIU_CONSTRAINT
149 */
150
151
152///////////////////////////////////////////////////////////////////////////////
153// Check for good parity on header
154///////////////////////////////////////////////////////////////////////////////
155
156 /* x0in
157 even_parity -var {dmu_sii_data[127:64], dmu_sii_parity[1]}
158 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF `SIU_CONSTRAINT
159 -name dmu_sii_hdr_parity1 ;
160 even_parity -var {dmu_sii_data[ 63: 0], dmu_sii_parity[0]}
161 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF `SIU_CONSTRAINT
162 -name dmu_sii_hdr_parity0
163 */
164
165 /* x0in
166 even_parity -var {dmu_sii_data[127:96], dmu_sii_parity[3]}
167 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF `SIU_CONSTRAINT
168 -name dmu_sii_hdr_parity3 ;
169 even_parity -var {dmu_sii_data[ 95:64], dmu_sii_parity[2]}
170 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF `SIU_CONSTRAINT
171 -name dmu_sii_hdr_parity2 ;
172 even_parity -var {dmu_sii_data[ 63:32], dmu_sii_parity[1]}
173 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF `SIU_CONSTRAINT
174 -name dmu_sii_hdr_parity1 ;
175 even_parity -var {dmu_sii_data[ 31: 0], dmu_sii_parity[0]}
176 -active dmu_sii_hdr_vld -module `TOP_DESIGN_DMU_INTF `SIU_CONSTRAINT
177 -name dmu_sii_hdr_parity0
178 */
179
180
181///////////////////////////////////////////////////////////////////////////////
182// Check for good parity on data0, data1, data2, and data3
183// - DSN spec says that there are 4 parity bits, but sii rtl only has 2.
184///////////////////////////////////////////////////////////////////////////////
185
186 /* x0in
187 even_parity -var {dmu_sii_data[127:64], dmu_sii_parity[1]} `SIU_CONSTRAINT
188 -active $0in_delay((dmu_sii_hdr_vld & (dmu_sii_datareq16|dmu_sii_datareq)), 1 )
189 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data0_parity1 ;
190 even_parity -var {dmu_sii_data[ 63: 0], dmu_sii_parity[0]} `SIU_CONSTRAINT
191 -active $0in_delay((dmu_sii_hdr_vld & (dmu_sii_datareq16|dmu_sii_datareq)), 1 )
192 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data0_parity0
193 */
194
195 /* x0in
196 even_parity -var {dmu_sii_data[127:64], dmu_sii_parity[1]} `SIU_CONSTRAINT
197 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16), 2 )
198 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data1_parity1 ;
199 even_parity -var {dmu_sii_data[ 63: 0], dmu_sii_parity[0]} `SIU_CONSTRAINT
200 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16), 2 )
201 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data1_parity0
202 */
203
204 /* x0in
205 even_parity -var {dmu_sii_data[127:64], dmu_sii_parity[1]} `SIU_CONSTRAINT
206 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16), 3 )
207 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data2_parity1 ;
208 even_parity -var {dmu_sii_data[ 63: 0], dmu_sii_parity[0]} `SIU_CONSTRAINT
209 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16), 3 )
210 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data2_parity0
211 */
212
213 /* x0in
214 even_parity -var {dmu_sii_data[127:64], dmu_sii_parity[1]} `SIU_CONSTRAINT
215 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16), 4 )
216 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data3_parity1 ;
217 even_parity -var {dmu_sii_data[ 63: 0], dmu_sii_parity[0]} `SIU_CONSTRAINT
218 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq & !dmu_sii_datareq16), 4 )
219 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data3_parity0
220 */
221
222
223 /* x0in
224 even_parity -var {dmu_sii_data[127:96], dmu_sii_parity[3]} `SIU_CONSTRAINT
225 -active $0in_delay((dmu_sii_hdr_vld & (dmu_sii_datareq16|dmu_sii_datareq)), 1 )
226 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data0_parity3 ;
227 even_parity -var {dmu_sii_data[ 95:64], dmu_sii_parity[2]} `SIU_CONSTRAINT
228 -active $0in_delay((dmu_sii_hdr_vld & (dmu_sii_datareq16|dmu_sii_datareq)), 1 )
229 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data0_parity2 ;
230 even_parity -var {dmu_sii_data[ 63:32], dmu_sii_parity[1]} `SIU_CONSTRAINT
231 -active $0in_delay((dmu_sii_hdr_vld & (dmu_sii_datareq16|dmu_sii_datareq)), 1 )
232 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data0_parity1 ;
233 even_parity -var {dmu_sii_data[ 31: 0], dmu_sii_parity[0]} `SIU_CONSTRAINT
234 -active $0in_delay((dmu_sii_hdr_vld & (dmu_sii_datareq16|dmu_sii_datareq)), 1 )
235 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data0_parity0
236 */
237
238 /* x0in
239 even_parity -var {dmu_sii_data[127:96], dmu_sii_parity[3]}
240 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 2 ) `SIU_CONSTRAINT
241 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data1_parity3 ;
242 even_parity -var {dmu_sii_data[ 95:64], dmu_sii_parity[2]}
243 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 2 ) `SIU_CONSTRAINT
244 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data1_parity2 ;
245 even_parity -var {dmu_sii_data[ 63:32], dmu_sii_parity[1]}
246 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 2 ) `SIU_CONSTRAINT
247 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data1_parity1 ;
248 even_parity -var {dmu_sii_data[ 31: 0], dmu_sii_parity[0]}
249 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 2 ) `SIU_CONSTRAINT
250 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data1_parity0
251 */
252
253 /* x0in
254 even_parity -var {dmu_sii_data[127:96], dmu_sii_parity[3]}
255 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 3 ) `SIU_CONSTRAINT
256 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data2_parity3 ;
257 even_parity -var {dmu_sii_data[ 95:64], dmu_sii_parity[2]}
258 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 3 ) `SIU_CONSTRAINT
259 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data2_parity2 ;
260 even_parity -var {dmu_sii_data[ 63:32], dmu_sii_parity[1]}
261 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 3 ) `SIU_CONSTRAINT
262 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data2_parity1 ;
263 even_parity -var {dmu_sii_data[ 31: 0], dmu_sii_parity[0]}
264 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 3 ) `SIU_CONSTRAINT
265 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data2_parity0
266 */
267
268 /* x0in
269 even_parity -var {dmu_sii_data[127:96], dmu_sii_parity[3]}
270 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 4 ) `SIU_CONSTRAINT
271 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data3_parity3 ;
272 even_parity -var {dmu_sii_data[ 95:64], dmu_sii_parity[2]}
273 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 4 ) `SIU_CONSTRAINT
274 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data3_parity2 ;
275 even_parity -var {dmu_sii_data[ 63:32], dmu_sii_parity[1]}
276 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 4 ) `SIU_CONSTRAINT
277 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data3_parity1 ;
278 even_parity -var {dmu_sii_data[ 31: 0], dmu_sii_parity[0]}
279 -active $0in_delay((dmu_sii_hdr_vld & dmu_sii_datareq), 4 ) `SIU_CONSTRAINT
280 -module `TOP_DESIGN_DMU_INTF -name dmu_sii_data3_parity0
281 */
282
283
284
285
286///////////////////////////////////////////////////////////////////////////////
287// Check for no overlap of transactions from sio to dmu:
288// After dmu_sii_datareq and not dmu_sii_datareq16,
289// dmu_sii_hdr_vld and datareq signals are 0 for 4 cycles.
290///////////////////////////////////////////////////////////////////////////////
291
292`define SIO_DMU_COMMAND sio_dmu_data[127:122]
293`define SIO_DMC_TAG sio_dmu_data[79:64]
294
295`ifdef FC_BENCH
296 /* 0in
297 assert_window
298 -start (sio_dmu_hdr_vld)
299 -start_count 0
300 -stop_count 4
301 -not_in sio_dmu_hdr_vld
302 -module cpu
303 -clock tb_top.cpu.dmu.iol2clk
304 -name sio_dmu_pkt_no_overlap `DMU_CONSTRAINT
305 */
306`else
307 /* 0in
308 assert_window
309 -start (sio_dmu_hdr_vld)
310 -start_count 0
311 -stop_count 4
312 -not_in sio_dmu_hdr_vld
313 -module `TOP_DESIGN_DMU_INTF
314 -name sio_dmu_pkt_no_overlap `DMU_CONSTRAINT
315 */
316`endif
317
318 /* x0in value
319 -var `SIO_DMU_COMMAND
320 -casex
321 -val 6'b101010
322 -active sio_dmu_hdr_vld
323 -module `TOP_DESIGN_DMU_INTF
324 -name sio_dmu_cmd_chk
325 -message "Bad value for sio_dmu header"
326 */
327
328
329 // check for reserved bits of header
330 // UPDATE/check for the differences with RAS changes for RSVD bits
331 /* 0in assert
332 -var ( |{sio_dmu_data[121:82],sio_dmu_data[63:62], sio_dmu_data[55:40]} == 1'b0)
333 -active sio_dmu_hdr_vld
334 -module `TOP_DESIGN_DMU_INTF
335 -name sio_dmu_hdr_rsrvd_bits
336 -message "reserved bits in header are not all zero"
337 */
338
339`ifdef FC_BENCH
340 // RDD
341 /* 0in assert_together
342 -leader ((`SIO_DMU_COMMAND==6'b101010) & sio_dmu_hdr_vld)
343 -follower (sio_dmu_hdr_vld)
344 -module cpu
345 -clock tb_top.cpu.dmu.iol2clk
346 -name sio_dmu_cmd_rdd
347 */
348`else
349 /* 0in assert_together
350 -leader ((sio_dmu_data[127]==1'b1) & sio_dmu_hdr_vld)
351 -follower (sio_dmu_hdr_vld)
352 -module `TOP_DESIGN_DMU_INTF
353 -name sio_dmu_cmd_rdd
354 */
355`endif
356
357///////////////////////////////////////////////////////////////////////////////
358// NO check for good parity on header in sio_dmu_data, since SIU does not
359// generate parity during the header cycle.
360///////////////////////////////////////////////////////////////////////////////
361
362 /* x0inx
363 even_parity -var {sio_dmu_data[127:96], sio_dmu_parity[3]}
364 -active sio_dmu_hdr_vld -module `TOP_DESIGN_DMU_INTF `DMU_CONSTRAINT
365 -name sio_dmu_hdr_parity3 ;
366 even_parity -var {sio_dmu_data[ 95:64], sio_dmu_parity[2]}
367 -active sio_dmu_hdr_vld -module `TOP_DESIGN_DMU_INTF `DMU_CONSTRAINT
368 -name sio_dmu_hdr_parity2 ;
369 even_parity -var {sio_dmu_data[ 63:32], sio_dmu_parity[1]}
370 -active sio_dmu_hdr_vld -module `TOP_DESIGN_DMU_INTF `DMU_CONSTRAINT
371 -name sio_dmu_hdr_parity1 ;
372 even_parity -var {sio_dmu_data[ 31: 0], sio_dmu_parity[0]}
373 -active sio_dmu_hdr_vld -module `TOP_DESIGN_DMU_INTF `DMU_CONSTRAINT
374 -name sio_dmu_hdr_parity0
375 */
376
377///////////////////////////////////////////////////////////////////////////////
378// Check for good parity in sio_dmu_data during data xfer cycles
379///////////////////////////////////////////////////////////////////////////////
380
381 /* x0in
382 even_parity -var {sio_dmu_data[127:96], sio_dmu_parity[3]} `DMU_CONSTRAINT
383 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 1 ) -module `TOP_DESIGN_DMU_INTF
384 -name sio_dmu_data0_parity3 ;
385 even_parity -var {sio_dmu_data[ 95:64], sio_dmu_parity[2]} `DMU_CONSTRAINT
386 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 1 ) -module `TOP_DESIGN_DMU_INTF
387 -name sio_dmu_data0_parity2 ;
388 even_parity -var {sio_dmu_data[ 63:32], sio_dmu_parity[1]} `DMU_CONSTRAINT
389 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 1 ) -module `TOP_DESIGN_DMU_INTF
390 -name sio_dmu_data0_parity1 ;
391 even_parity -var {sio_dmu_data[ 31: 0], sio_dmu_parity[0]} `DMU_CONSTRAINT
392 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 1 ) -module `TOP_DESIGN_DMU_INTF
393 -name sio_dmu_data0_parity0
394 */
395
396 /* x0in
397 even_parity -var {sio_dmu_data[127:96], sio_dmu_parity[3]} `DMU_CONSTRAINT
398 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 2 ) -module `TOP_DESIGN_DMU_INTF
399 -name sio_dmu_data1_parity3 ;
400 even_parity -var {sio_dmu_data[ 95:64], sio_dmu_parity[2]} `DMU_CONSTRAINT
401 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 2 ) -module `TOP_DESIGN_DMU_INTF
402 -name sio_dmu_data1_parity2 ;
403 even_parity -var {sio_dmu_data[ 63:32], sio_dmu_parity[1]} `DMU_CONSTRAINT
404 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 2 ) -module `TOP_DESIGN_DMU_INTF
405 -name sio_dmu_data1_parity1 ;
406 even_parity -var {sio_dmu_data[ 31: 0], sio_dmu_parity[0]} `DMU_CONSTRAINT
407 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 2 ) -module `TOP_DESIGN_DMU_INTF
408 -name sio_dmu_data1_parity0
409 */
410
411 /* x0in
412 even_parity -var {sio_dmu_data[127:96], sio_dmu_parity[3]} `DMU_CONSTRAINT
413 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 3 ) -module `TOP_DESIGN_DMU_INTF
414 -name sio_dmu_data2_parity3 ;
415 even_parity -var {sio_dmu_data[ 95:64], sio_dmu_parity[2]} `DMU_CONSTRAINT
416 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 3 ) -module `TOP_DESIGN_DMU_INTF
417 -name sio_dmu_data2_parity2 ;
418 even_parity -var {sio_dmu_data[ 63:32], sio_dmu_parity[1]} `DMU_CONSTRAINT
419 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 3 ) -module `TOP_DESIGN_DMU_INTF
420 -name sio_dmu_data2_parity1 ;
421 even_parity -var {sio_dmu_data[ 31: 0], sio_dmu_parity[0]} `DMU_CONSTRAINT
422 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 3 ) -module `TOP_DESIGN_DMU_INTF
423 -name sio_dmu_data2_parity0
424 */
425
426 /* x0in
427 even_parity -var {sio_dmu_data[127:96], sio_dmu_parity[3]} `DMU_CONSTRAINT
428 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 4 ) -module `TOP_DESIGN_DMU_INTF
429 -name sio_dmu_data3_parity3 ;
430 even_parity -var {sio_dmu_data[ 95:64], sio_dmu_parity[2]} `DMU_CONSTRAINT
431 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 4 ) -module `TOP_DESIGN_DMU_INTF
432 -name sio_dmu_data3_parity2 ;
433 even_parity -var {sio_dmu_data[ 63:32], sio_dmu_parity[1]} `DMU_CONSTRAINT
434 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 4 ) -module `TOP_DESIGN_DMU_INTF
435 -name sio_dmu_data3_parity1 ;
436 even_parity -var {sio_dmu_data[ 31: 0], sio_dmu_parity[0]} `DMU_CONSTRAINT
437 -active $0in_delay((sio_dmu_hdr_vld & sio_dmu_datareq), 4 ) -module `TOP_DESIGN_DMU_INTF
438 -name sio_dmu_data3_parity0
439 */
440
441 /* 0in bus_id
442 -req (dmu_sii_hdr_vld & ~dmu_sii_data[126] & dmu_sii_data[123])
443 -ret sio_dmu_hdr_vld
444 -req_id dmu_sii_data[79:64]
445 -ret_id sio_dmu_data[79:64]
446 -max_ids 65536
447 -max_ids_check off
448 -module `TOP_DESIGN_DMU_INTF
449 -name dmu_bus_id
450 */
451
452
453////////////////////////////////////////////////////////////////////////////////
454// Each WRI and WRM Transaction to sii has to be followed by a sii_dmu_wrack_vld
455// and the other way also
456
457////////////////////////////////////////////////////////////////////////////////
458 /* 0in assert_follower
459 -leader (dmu_sii_hdr_vld & ((`DMU_SII_COMMAND==`WRI_ORD_PST) || (`DMU_SII_COMMAND==`WRM_ORD_PST)))
460 -follower sii_dmu_wrack_vld
461 -min 2
462 -max 48000
463 -max_leader 16
464 -clock ccu_io_out
465 -module `TOP_DESIGN_DMU_INTF
466 -name dmu_sii_wriack_assert_follower
467 */
468
469
470 /* 0in assert_leader
471 -leader (dmu_sii_hdr_vld & ((`DMU_SII_COMMAND==`WRI_ORD_PST) || (`DMU_SII_COMMAND==`WRM_ORD_PST)))
472 -follower sii_dmu_wrack_vld
473 -min 2
474 -max 48000
475 -max_leader 16
476 -clock ccu_io_out
477 -module `TOP_DESIGN_DMU_INTF
478 -name dmu_sii_wriack_assert_leader
479 */
480
481/////////////////////////////////////////////////////////
482// Header and signals with Transactions from DMU to SII:
483// RDD, WRI, INT, PIO
484//////////////////////////////////////////////////////////
485 // RDD
486 /* 0in assert_together
487 -leader ((dmu_sii_data[127:122]==6'b001010) & dmu_sii_hdr_vld)
488 -follower (dmu_sii_hdr_vld & ~dmu_sii_datareq & ~dmu_sii_datareq16 & ~dmu_sii_reqbypass)
489 -module `TOP_DESIGN_DMU_INTF
490 -name dmu_sii_cmd_rdd
491 */
492
493 // WRI or WRM
494 /* 0in assert_together
495 -leader ((dmu_sii_data[127:122]==6'b010x10) & dmu_sii_hdr_vld)
496 -follower (dmu_sii_hdr_vld & dmu_sii_datareq & ~dmu_sii_datareq16 & ~dmu_sii_reqbypass)
497 -module `TOP_DESIGN_DMU_INTF
498 -name dmu_sii_cmd_wri_wrm
499 */
500
501 // INT
502 /* 0in assert_together
503 -leader ((dmu_sii_data[127:122]==6'b000001) & dmu_sii_hdr_vld)
504 -follower (dmu_sii_hdr_vld & dmu_sii_datareq & dmu_sii_datareq16 & ~dmu_sii_reqbypass)
505 -module `TOP_DESIGN_DMU_INTF
506 -name dmu_sii_cmd_int
507 */
508
509 // PIO
510 /* 0in assert_together
511 -leader ((dmu_sii_data[127:122]==6'b1x1001) & dmu_sii_hdr_vld)
512 -follower (dmu_sii_hdr_vld & dmu_sii_datareq & dmu_sii_datareq16 & dmu_sii_reqbypass)
513 -module `TOP_DESIGN_DMU_INTF
514 -name dmu_sii_cmd_pio
515 */
516
517
518
519endmodule // dmu_siu_chkr
Full OpenSPARC design & verification tarball including full HDL.