projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: rst_chkr.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module rst_chkr(); | |
| 36 | ||
| 37 | // 0in set_clock `CPU.rst.ccu_rst_sys_clk -default -module rst_chkr | |
| 38 | ||
| 39 | //--------- RST interface assertions -------------- | |
| 40 | `ifdef X_GUARD | |
| 41 | /* 0in- known_driven | |
| 42 | -name x_guard_rst_dmu_peu_wmr_ | |
| 43 | -var rst_dmu_peu_wmr_ | |
| 44 | -active rst_dmu_async_por_ | |
| 45 | -module rst | |
| 46 | -group rst_chkr | |
| 47 | */ | |
| 48 | /* 0in- known_driven | |
| 49 | -name x_guard_rst_dmu_peu_por_ | |
| 50 | -var rst_dmu_peu_por_ | |
| 51 | -active rst_dmu_async_por_ | |
| 52 | -module rst | |
| 53 | -group rst_chkr | |
| 54 | */ | |
| 55 | ||
| 56 | // changed the following 3 assertions from: | |
| 57 | //-active mio_rst_pwron_rst_l | |
| 58 | // because, with addition of sync_en flop, this signal | |
| 59 | // will stay X until cmp clock starts. | |
| 60 | // This assertion needs to be tightened. Oct 6 '05. | |
| 61 | ||
| 62 | /* 0in known_driven | |
| 63 | -name x_guard_rst_niu_mac_ | |
| 64 | -var rst_niu_mac_ | |
| 65 | -active (!init_state && !por1_state) | |
| 66 | -module rst | |
| 67 | -group rst_chkr | |
| 68 | */ | |
| 69 | /* 0in known_driven | |
| 70 | -name x_guard_rst_niu_wmr_ | |
| 71 | -var rst_niu_wmr_ | |
| 72 | -active (!init_state && !por1_state) | |
| 73 | -module rst | |
| 74 | -group rst_chkr | |
| 75 | */ | |
| 76 | /* 0in known_driven | |
| 77 | -name x_guard_rst_mcu_selfrsh | |
| 78 | -var rst_mcu_selfrsh | |
| 79 | -active (!init_state && !por1_state) | |
| 80 | -module rst | |
| 81 | -group rst_chkr | |
| 82 | */ | |
| 83 | /* 0in known_driven | |
| 84 | -name x_guard_rst_ncu_unpark_thread | |
| 85 | -var rst_ncu_unpark_thread | |
| 86 | -active ccu_rst_sync_stable | |
| 87 | -module rst | |
| 88 | -group rst_chkr | |
| 89 | */ | |
| 90 | // was: -active mio_rst_pwron_rst_l | |
| 91 | ||
| 92 | /* 0in known_driven | |
| 93 | -name x_guard_rst_ncu_xir | |
| 94 | -var rst_ncu_xir_ | |
| 95 | -active ccu_rst_sync_stable | |
| 96 | -module rst | |
| 97 | -group rst_chkr | |
| 98 | */ | |
| 99 | // was: -active mio_rst_pwron_rst_l | |
| 100 | ||
| 101 | /* 0in- known_driven | |
| 102 | -name x_guard_rst_por | |
| 103 | -var rst_l2_por_ | |
| 104 | -active rst_dmu_async_por_ | |
| 105 | -module rst | |
| 106 | -group rst_chkr | |
| 107 | */ | |
| 108 | /* 0in- known_driven | |
| 109 | -name x_guard_rst_wmr | |
| 110 | -var rst_l2_wmr_ | |
| 111 | -active rst_dmu_async_por_ | |
| 112 | -module rst | |
| 113 | -group rst_chkr | |
| 114 | */ | |
| 115 | /* 0in- known_driven | |
| 116 | -name x_guard_rst_wmr_protect | |
| 117 | -var rst_wmr_protect | |
| 118 | -active rst_dmu_async_por_ | |
| 119 | -module rst | |
| 120 | -group rst_chkr | |
| 121 | */ | |
| 122 | /* 0in known_driven | |
| 123 | -name x_guard_rst_state | |
| 124 | -var state_q | |
| 125 | -active mio_rst_pwron_rst_l | |
| 126 | -module rst_fsm_ctl | |
| 127 | -group rst_chkr | |
| 128 | */ | |
| 129 | /* 0in known_driven | |
| 130 | -name x_guard_lock_count | |
| 131 | -var lock_count_q | |
| 132 | -active mio_rst_pwron_rst_l | |
| 133 | -module rst_fsm_ctl | |
| 134 | -group rst_chkr | |
| 135 | */ | |
| 136 | /* 0in known_driven | |
| 137 | -name x_guard_prop_count | |
| 138 | -var prop_count_q | |
| 139 | -active mio_rst_pwron_rst_l | |
| 140 | -module rst_fsm_ctl | |
| 141 | -group rst_chkr | |
| 142 | * | |
| 143 | ||
| 144 | /* 0in known_driven | |
| 145 | -name x_guard_ncu_rst_data | |
| 146 | -var ncu_rst_data | |
| 147 | -active ncu_rst_vld | |
| 148 | -reset tb_top.default_reset_0in | |
| 149 | -module rst | |
| 150 | -group rst_chkr | |
| 151 | */ | |
| 152 | /* 0in known_driven | |
| 153 | -name x_guard_rst_ncu_data | |
| 154 | -var rst_ncu_data | |
| 155 | -active rst_ncu_vld | |
| 156 | -reset tb_top.default_reset_0in | |
| 157 | -module rst | |
| 158 | -group rst_chkr | |
| 159 | */ | |
| 160 | /* 0in- known_driven | |
| 161 | -name x_guard_rst_tcu_flush_init_req | |
| 162 | -var rst_tcu_flush_init_req | |
| 163 | -active rst_dmu_async_por_ | |
| 164 | -module rst | |
| 165 | -group rst_chkr | |
| 166 | */ | |
| 167 | /* 0in- known_driven | |
| 168 | -name x_guard_rst_tcu_flush_stop_req | |
| 169 | -var rst_tcu_flush_stop_req | |
| 170 | -active rst_dmu_async_por_ | |
| 171 | -module rst | |
| 172 | -group rst_chkr | |
| 173 | */ | |
| 174 | /* 0in known_driven | |
| 175 | -name x_guard_tcu_rst_flush_init_ack | |
| 176 | -var tcu_rst_flush_init_ack | |
| 177 | -active (mio_rst_pwron_rst_l & `RST.ccu_rst_sync_stable) | |
| 178 | -module rst | |
| 179 | -group rst_chkr | |
| 180 | */ | |
| 181 | /* 0in known_driven | |
| 182 | -name x_guard_tcu_rst_flush_stop_ack | |
| 183 | -var tcu_rst_flush_stop_ack | |
| 184 | -active mio_rst_pwron_rst_l | |
| 185 | -module rst | |
| 186 | -group rst_chkr | |
| 187 | */ | |
| 188 | ||
| 189 | /* 0in known_driven | |
| 190 | -name x_guard_tcu_sck_bypass | |
| 191 | -var `TCU.tcu_sck_bypass | |
| 192 | -active (`CPU.PWRON_RST_L & `CPU.TRST_L) | |
| 193 | -module rst | |
| 194 | -group rst_chkr | |
| 195 | */ | |
| 196 | `endif | |
| 197 | ||
| 198 | //--------- RST inline assertions (to be moved) -------------- | |
| 199 | // 0in use_synthesis_case_directives -module rst_fsm_ctl | |
| 200 | ||
| 201 | //--------- Scan flush or simulation scan enable undefined -------------- | |
| 202 | // 0000in disable_checker 1'b1 -type fire -name tb_top.cpu.rst.rst_fsm_ctl.rst_state_invalid | |
| 203 | // For some reason, we cannot disable checkers via -name unless we pass "-d tb_top" flag | |
| 204 | // commented 02/10/05 0in disable_checker 1'b1 -module rst_fsm_ctl | |
| 205 | ||
| 206 | // ----Verilog Checker Code --------------------------- | |
| 207 | ||
| 208 | // ===== Define Declarations ================================ | |
| 209 | ||
| 210 | parameter RST_SIM_FSM_WIDTH = 4, | |
| 211 | INIT_ST = 4'd0, | |
| 212 | POR1_ST = 4'd1, | |
| 213 | POR2_ST = 4'd2, | |
| 214 | WMR1_ST = 4'd3, | |
| 215 | WMR2_ST = 4'd4, | |
| 216 | WMR1GEN_ST = 4'd5, | |
| 217 | WMR2GEN_ST = 4'd6, | |
| 218 | UNPARK_ST = 4'd7, | |
| 219 | POR_UNPARK_ST = 4'd8, | |
| 220 | FSM_TIMEOUT_CYC = 6000; | |
| 221 | parameter [15:0] PROP_TIME = 16'd16, | |
| 222 | LOCK_TIME = 16'd16, | |
| 223 | NIU_TIME = 16'd16; | |
| 224 | // ========== RTL Model ===============================/ | |
| 225 | ||
| 226 | // ------------------------------------------------------ | |
| 227 | // Variable Declarations: Used by Verilog 0-in Checker Code | |
| 228 | // ------------------------------------------------------- | |
| 229 | ||
| 230 | wire clk; | |
| 231 | wire PWR_ON; | |
| 232 | wire PB_RST; | |
| 233 | wire [8:0] L2t_err; | |
| 234 | wire ras_err; | |
| 235 | wire rst_tcu_flush_init_req; | |
| 236 | wire rst_wmr_protect; | |
| 237 | wire unpark_thread; | |
| 238 | wire [3:0] reset_gen_q; | |
| 239 | wire xir_rst_active; | |
| 240 | wire [15:0] prop_time; | |
| 241 | wire [15:0] lock_time; | |
| 242 | wire [15:0] niu_time; | |
| 243 | wire [15:0] ccu_time; | |
| 244 | wire [15:0] sync_stable_time; | |
| 245 | wire [15:0] dmu_time; | |
| 246 | ||
| 247 | reg [RST_SIM_FSM_WIDTH - 1 : 0] curr_st, next_st; | |
| 248 | reg DEBUG_RST ; | |
| 249 | wire init_state; | |
| 250 | wire por1_state; | |
| 251 | wire por2_state ; | |
| 252 | wire por_unpark_state ; | |
| 253 | wire wmr1_state ; | |
| 254 | wire wmr2_state; | |
| 255 | wire unpark_state ; | |
| 256 | wire wmr2gen_state; | |
| 257 | ||
| 258 | assign prop_time = `RST.rst_fsm_ctl.prop_time_q; | |
| 259 | assign lock_time = `RST.rst_fsm_ctl.lock_time_q; | |
| 260 | assign niu_time = `RST.rst_fsm_ctl.niu_time_q; | |
| 261 | assign ccu_time = `RST.rst_fsm_ctl.ccu_time_q ; | |
| 262 | assign sync_stable_time = `RST.rst_fsm_ctl.ccu_time_q + 16'h3; | |
| 263 | assign dmu_time = niu_time * 2; | |
| 264 | ||
| 265 | assign init_state = (curr_st == INIT_ST) ? 1'b1: 1'b0; | |
| 266 | assign por1_state = (curr_st == POR1_ST) ? 1'b1: 1'b0; | |
| 267 | assign por2_state = (curr_st == POR2_ST) ? 1'b1: 1'b0; | |
| 268 | assign por_unpark_state = (curr_st == POR_UNPARK_ST ) ? 1'b1: 1'b0; | |
| 269 | assign wmr1_state = (curr_st == WMR1_ST) ? 1'b1: 1'b0; | |
| 270 | assign wmr2gen_state = (curr_st == WMR2GEN_ST) ? 1'b1: 1'b0; | |
| 271 | assign wmr2_state = (curr_st == WMR2_ST) ? 1'b1: 1'b0; | |
| 272 | assign unpark_state = (curr_st == UNPARK_ST ) ? 1'b1: 1'b0; | |
| 273 | ||
| 274 | //assign clk = `RST.ccu_rst_sys_clk; | |
| 275 | assign clk = `RST.rst_fsm_ctl.ref_clk; | |
| 276 | assign PWR_ON = `RST.mio_rst_pwron_rst_l; | |
| 277 | assign PB_RST = `RST.mio_rst_pb_rst_l; | |
| 278 | assign L2t_err = {`RST.l2t7_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[7], | |
| 279 | `RST.l2t6_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[6], | |
| 280 | `RST.l2t5_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[5], | |
| 281 | `RST.l2t4_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[4], | |
| 282 | `RST.l2t3_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[3], | |
| 283 | `RST.l2t2_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[2], | |
| 284 | `RST.l2t1_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[1], | |
| 285 | `RST.l2t0_rst_fatal_error & `RST.rst_fsm_ctl.reset_fee_q[0] }; | |
| 286 | ||
| 287 | assign ras_err = `RST.ncu_rst_fatal_error; | |
| 288 | assign rst_tcu_flush_init_req = `RST.rst_tcu_flush_init_req; | |
| 289 | assign rst_wmr_protect = `RST.rst_wmr_protect; | |
| 290 | assign unpark_thread = `RST.rst_ncu_unpark_thread; | |
| 291 | assign reset_gen_q = `RST.rst_fsm_ctl.reset_gen_q; | |
| 292 | assign xir_rst_active = ((reset_gen_q[1] == 1'b1) || (`RST.mio_rst_button_xir_l == 1'b0)) ? 1'b1 : 1'b0; | |
| 293 | ||
| 294 | ||
| 295 | initial | |
| 296 | begin | |
| 297 | curr_st = INIT_ST; | |
| 298 | next_st = INIT_ST; | |
| 299 | end | |
| 300 | ||
| 301 | always @(posedge clk or negedge PWR_ON) | |
| 302 | begin | |
| 303 | if(!PWR_ON) | |
| 304 | curr_st = POR1_ST; | |
| 305 | else | |
| 306 | curr_st = next_st; | |
| 307 | end | |
| 308 | ||
| 309 | ||
| 310 | always @(PWR_ON or | |
| 311 | PB_RST or | |
| 312 | L2t_err or | |
| 313 | ras_err or | |
| 314 | rst_tcu_flush_init_req or | |
| 315 | rst_wmr_protect or | |
| 316 | unpark_thread or | |
| 317 | `RST.tcu_rst_flush_stop_ack or | |
| 318 | curr_st ) | |
| 319 | begin | |
| 320 | case (curr_st) | |
| 321 | INIT_ST: begin | |
| 322 | DEBUG_RST <= 1'b0; | |
| 323 | if(PWR_ON == 1'b0 ) begin | |
| 324 | next_st <= POR1_ST; | |
| 325 | $dispmon("rst_chkr.v", `INFO, "PWRON_RST is %b", PWR_ON); | |
| 326 | end | |
| 327 | else if((PB_RST == 1'b0) || (|L2t_err) || ras_err || (reset_gen_q[0] == 1'b1)) | |
| 328 | next_st <= WMR1GEN_ST; | |
| 329 | else if(reset_gen_q[3] == 1'b1) begin | |
| 330 | next_st <= WMR1GEN_ST; | |
| 331 | DEBUG_RST <= 1'b1; | |
| 332 | end | |
| 333 | //else | |
| 334 | // next_st <= INIT_ST; | |
| 335 | end | |
| 336 | POR1_ST: begin | |
| 337 | // Control o/ps from RST will be X until clocks stable | |
| 338 | // Email dated sept 29 '05 | |
| 339 | if((`RST.ccu_rst_sync_stable == 1'b1) && | |
| 340 | (rst_tcu_flush_init_req == 1'b1)) | |
| 341 | next_st <= POR2_ST; | |
| 342 | else | |
| 343 | next_st <= POR1_ST; | |
| 344 | end | |
| 345 | POR2_ST: begin | |
| 346 | if(`RST.tcu_rst_flush_stop_ack == 1'b1) | |
| 347 | begin | |
| 348 | next_st <= POR_UNPARK_ST; | |
| 349 | end | |
| 350 | else | |
| 351 | next_st <= POR2_ST; | |
| 352 | ||
| 353 | if (`RST.rst_fsm_ctl.prop_time_q != prop_time) | |
| 354 | $dispmon("rst_chkr.v", `ALWAYS, "PROP time delay setting in test differs from the setting in RTL"); | |
| 355 | end | |
| 356 | POR_UNPARK_ST: begin | |
| 357 | if(unpark_thread == 1'b1) | |
| 358 | begin | |
| 359 | next_st <= INIT_ST; | |
| 360 | end | |
| 361 | if (`RST.rst_fsm_ctl.prop_time_q != prop_time) | |
| 362 | $dispmon("rst_chkr.v", `ALWAYS, "PROP time delay setting in test differs from the setting in RTL"); | |
| 363 | end | |
| 364 | ||
| 365 | WMR1GEN_ST: begin | |
| 366 | if(rst_tcu_flush_init_req == 1'b1) | |
| 367 | next_st <= WMR1_ST; | |
| 368 | else | |
| 369 | next_st <= WMR1GEN_ST; | |
| 370 | ||
| 371 | end | |
| 372 | WMR1_ST: begin | |
| 373 | if(`RST.tcu_rst_flush_stop_ack == 1'b1) | |
| 374 | next_st <= WMR2GEN_ST; | |
| 375 | else | |
| 376 | next_st <= WMR1_ST; | |
| 377 | end | |
| 378 | ||
| 379 | WMR2GEN_ST: begin | |
| 380 | if(rst_tcu_flush_init_req == 1'b1) | |
| 381 | next_st <= WMR2_ST; | |
| 382 | else | |
| 383 | next_st <= WMR2GEN_ST; | |
| 384 | ||
| 385 | end | |
| 386 | ||
| 387 | WMR2_ST: begin | |
| 388 | if(`RST.tcu_rst_flush_stop_ack == 1'b1) | |
| 389 | next_st <= UNPARK_ST; | |
| 390 | else | |
| 391 | next_st <= WMR2_ST; | |
| 392 | end | |
| 393 | ||
| 394 | UNPARK_ST: begin | |
| 395 | if(unpark_thread == 1'b1) begin | |
| 396 | next_st <= INIT_ST; | |
| 397 | end | |
| 398 | end | |
| 399 | default: begin | |
| 400 | next_st <= INIT_ST; | |
| 401 | end | |
| 402 | endcase | |
| 403 | /* 0in state_transition | |
| 404 | -var curr_st | |
| 405 | -val INIT_ST | |
| 406 | -next POR1_ST WMR1GEN_ST INIT_ST | |
| 407 | -clock clk | |
| 408 | -group rst_chkr | |
| 409 | */ | |
| 410 | /* 0in state_transition | |
| 411 | -var curr_st | |
| 412 | -val POR1_ST | |
| 413 | -next POR1_ST POR2_ST | |
| 414 | -clock clk | |
| 415 | -group rst_chkr | |
| 416 | */ | |
| 417 | /* 0in state_transition | |
| 418 | -var curr_st | |
| 419 | -val POR2_ST | |
| 420 | -next POR2_ST POR_UNPARK_ST | |
| 421 | -clock clk | |
| 422 | -group rst_chkr | |
| 423 | */ | |
| 424 | /* 0in state_transition | |
| 425 | -var curr_st | |
| 426 | -val POR_UNPARK_ST | |
| 427 | -next POR_UNPARK_ST INIT_ST POR1_ST | |
| 428 | -clock clk | |
| 429 | -group rst_chkr | |
| 430 | */ | |
| 431 | /* 0in state_transition | |
| 432 | -var curr_st | |
| 433 | -val WMR1GEN_ST | |
| 434 | -next WMR1GEN_ST WMR1_ST POR1_ST | |
| 435 | -clock clk | |
| 436 | -group rst_chkr | |
| 437 | */ | |
| 438 | /* 0in state_transition | |
| 439 | -var curr_st | |
| 440 | -val WMR1_ST | |
| 441 | -next WMR1_ST WMR2GEN_ST POR1_ST | |
| 442 | -clock clk | |
| 443 | -group rst_chkr | |
| 444 | */ | |
| 445 | /* 0in state_transition | |
| 446 | -var curr_st | |
| 447 | -val WMR2GEN_ST | |
| 448 | -next WMR2GEN_ST WMR2_ST POR1_ST | |
| 449 | -clock clk | |
| 450 | -group rst_chkr | |
| 451 | */ | |
| 452 | /* 0in state_transition | |
| 453 | -var curr_st | |
| 454 | -val WMR2_ST | |
| 455 | -next WMR2_ST UNPARK_ST POR1_ST | |
| 456 | -clock clk | |
| 457 | -group rst_chkr | |
| 458 | */ | |
| 459 | /* 0in state_transition | |
| 460 | -var curr_st -val UNPARK_ST | |
| 461 | -next UNPARK_ST INIT_ST POR1_ST | |
| 462 | -clock clk | |
| 463 | -group rst_chkr | |
| 464 | */ | |
| 465 | ||
| 466 | // Temporary commented till we know the exact value for timeout 0in timeout -var curr_st -val FSM_TIMEOUT_CYC -name checker_code_deadlock -active (curr_st != INIT_ST) -clock `RST.ccu_rst_sys_clk | |
| 467 | end | |
| 468 | ||
| 469 | ||
| 470 | //<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Section A : Assertions for clk_stop and scan_enable for flush >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>// | |
| 471 | ||
| 472 | // Following assertions for clock stop and scan enable signal check. | |
| 473 | ||
| 474 | /* 0in assert_window | |
| 475 | -start $0in_rising_edge(`TCU.rst_tcu_flush_init_req) | |
| 476 | -stop $0in_rising_edge(`TCU.tcu_rst_flush_init_ack) | |
| 477 | -in `TCU.tcu_scan_en `TCU.tcu_array_wr_inhibit | |
| 478 | `TCU.tcu_se_scancollar_in `TCU.tcu_se_scancollar_out | |
| 479 | `TCU.tcu_spc0_clk_stop `TCU.tcu_spc1_clk_stop | |
| 480 | `TCU.tcu_spc2_clk_stop `TCU.tcu_spc3_clk_stop | |
| 481 | `TCU.tcu_spc4_clk_stop `TCU.tcu_spc5_clk_stop | |
| 482 | `TCU.tcu_spc6_clk_stop `TCU.tcu_spc7_clk_stop | |
| 483 | `TCU.tcu_l2d0_clk_stop `TCU.tcu_l2d1_clk_stop | |
| 484 | `TCU.tcu_l2d2_clk_stop `TCU.tcu_l2d3_clk_stop | |
| 485 | `TCU.tcu_l2d4_clk_stop `TCU.tcu_l2d5_clk_stop | |
| 486 | `TCU.tcu_l2d6_clk_stop `TCU.tcu_l2d7_clk_stop | |
| 487 | `TCU.tcu_l2t0_clk_stop `TCU.tcu_l2t1_clk_stop | |
| 488 | `TCU.tcu_l2t2_clk_stop `TCU.tcu_l2t3_clk_stop | |
| 489 | `TCU.tcu_l2t4_clk_stop `TCU.tcu_l2t5_clk_stop | |
| 490 | `TCU.tcu_l2t6_clk_stop `TCU.tcu_l2t7_clk_stop | |
| 491 | `TCU.tcu_l2b0_clk_stop `TCU.tcu_l2b1_clk_stop | |
| 492 | `TCU.tcu_l2b2_clk_stop `TCU.tcu_l2b3_clk_stop | |
| 493 | `TCU.tcu_l2b4_clk_stop `TCU.tcu_l2b5_clk_stop | |
| 494 | `TCU.tcu_l2b6_clk_stop `TCU.tcu_l2b7_clk_stop | |
| 495 | `TCU.tcu_mcu0_clk_stop `TCU.tcu_mcu0_dr_clk_stop | |
| 496 | `TCU.tcu_mcu0_io_clk_stop `TCU.tcu_mcu1_clk_stop | |
| 497 | `TCU.tcu_mcu1_dr_clk_stop `TCU.tcu_mcu1_io_clk_stop | |
| 498 | `TCU.tcu_mcu2_clk_stop `TCU.tcu_mcu2_dr_clk_stop | |
| 499 | `TCU.tcu_mcu2_io_clk_stop `TCU.tcu_mcu3_clk_stop | |
| 500 | `TCU.tcu_mcu3_dr_clk_stop `TCU.tcu_mcu3_io_clk_stop | |
| 501 | `TCU.tcu_ccx_clk_stop `TCU.tcu_sii_clk_stop | |
| 502 | `TCU.tcu_sii_io_clk_stop `TCU.tcu_sio_clk_stop | |
| 503 | `TCU.tcu_sio_io_clk_stop `TCU.tcu_ncu_clk_stop | |
| 504 | `TCU.tcu_ncu_io_clk_stop `TCU.tcu_efu_clk_stop | |
| 505 | `TCU.tcu_efu_io_clk_stop `TCU.tcu_mio_clk_stop | |
| 506 | `TCU.tcu_db0_clk_stop `TCU.tcu_db1_clk_stop | |
| 507 | -module tcu | |
| 508 | -clock l2clk | |
| 509 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 510 | -name aw_clk_stop_scan_assrt | |
| 511 | -group rst_chkr | |
| 512 | */ | |
| 513 | ||
| 514 | /* 0in assert_sequence | |
| 515 | -var $0in_rising_edge(`TCU.tcu_bclk) $0in_rising_edge(`TCU.tcu_scan_en) $0in_rising_edge(`TCU.tcu_aclk) | |
| 516 | -min 12 | |
| 517 | -module tcu | |
| 518 | -clock l2clk | |
| 519 | -active `TCU.rst_tcu_flush_init_req | |
| 520 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 521 | -name aw_clk_stop_scan_assrt | |
| 522 | -group rst_chkr | |
| 523 | */// Minimum 12 cycle delay: refer Tom email Date 10/18 | |
| 524 | ||
| 525 | //ASIC clk stops | |
| 526 | /* 0in assert_window | |
| 527 | -start `TCU.rst_tcu_flush_init_req | |
| 528 | -stop $0in_rising_edge(`TCU.tcu_rst_flush_init_ack) | |
| 529 | -in `TCU.tcu_dmu_io_clk_stop `TCU.tcu_rdp_io_clk_stop | |
| 530 | `TCU.tcu_mac_io_clk_stop `TCU.tcu_rtx_io_clk_stop | |
| 531 | `TCU.tcu_tds_io_clk_stop `TCU.tcu_peu_pc_clk_stop | |
| 532 | `TCU.tcu_peu_io_clk_stop | |
| 533 | -module tcu | |
| 534 | -clock l2clk | |
| 535 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 536 | -active ((wmr1_state | wmr2_state) & !DEBUG_RST) | |
| 537 | -name aw_clk_stop_asic_assrt | |
| 538 | -group rst_chkr | |
| 539 | */ | |
| 540 | ||
| 541 | // Core , l2 and MCU not included becaoz those depend upon core available and bank available regs in NCU | |
| 542 | ||
| 543 | /* 0in assert_window | |
| 544 | -start `TCU.rst_tcu_flush_stop_req | |
| 545 | -stop `TCU.tcu_rst_flush_stop_ack | |
| 546 | -in !`TCU.tcu_scan_en !`TCU.tcu_array_wr_inhibit | |
| 547 | !`TCU.tcu_se_scancollar_in !`TCU.tcu_se_scancollar_out | |
| 548 | !`TCU.tcu_ccx_clk_stop !`TCU.tcu_sii_clk_stop | |
| 549 | !`TCU.tcu_sii_io_clk_stop !`TCU.tcu_sio_clk_stop !`TCU.tcu_sio_io_clk_stop | |
| 550 | !`TCU.tcu_ncu_clk_stop !`TCU.tcu_ncu_io_clk_stop !`TCU.tcu_efu_clk_stop | |
| 551 | !`TCU.tcu_efu_io_clk_stop !`TCU.tcu_mio_clk_stop | |
| 552 | !`TCU.tcu_db0_clk_stop !`TCU.tcu_db1_clk_stop | |
| 553 | -module tcu | |
| 554 | -clock l2clk | |
| 555 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 556 | -name aw_clk_stop_scan_deassrt | |
| 557 | -group rst_chkr | |
| 558 | */ | |
| 559 | ||
| 560 | //<<<<< Section B : TCU-RST handshake signals >>>>>>>>>>>>>>>>>>>>>>// | |
| 561 | ||
| 562 | /* 0in req_ack | |
| 563 | -req `RST.rst_tcu_flush_stop_req | |
| 564 | -ack `RST.tcu_rst_flush_stop_ack | |
| 565 | -req_until_ack on | |
| 566 | -module rst | |
| 567 | -clock l2clk | |
| 568 | -name rq_ack_flush_stop | |
| 569 | -areset (!`RST.mio_rst_pwron_rst_l || !`RST.rst_tcu_pwron_rst_l) | |
| 570 | -group rst_chkr | |
| 571 | */ | |
| 572 | ||
| 573 | /* 0in req_ack | |
| 574 | -req `RST.rst_tcu_flush_init_req | |
| 575 | -ack `RST.tcu_rst_flush_init_ack | |
| 576 | -req_until_ack on | |
| 577 | -module rst | |
| 578 | -clock l2clk | |
| 579 | -name rq_ack_flush_init | |
| 580 | -active (!init_state & !por1_state ) | |
| 581 | -areset (!`RST.mio_rst_pwron_rst_l || !`RST.rst_tcu_pwron_rst_l ) | |
| 582 | -group rst_chkr | |
| 583 | */ | |
| 584 | // -reset $0in_falling_edge(`RST.mio_rst_pwron_rst_l) | |
| 585 | ||
| 586 | /* 0in req_ack | |
| 587 | -req `RST.rst_tcu_asicflush_stop_req | |
| 588 | -ack `RST.tcu_rst_asicflush_stop_ack | |
| 589 | -req_until_ack on | |
| 590 | -module rst | |
| 591 | -clock l2clk | |
| 592 | -name rq_ack_asicflush_stop | |
| 593 | -areset (!`RST.mio_rst_pwron_rst_l || !`RST.rst_tcu_pwron_rst_l ) | |
| 594 | -group rst_chkr | |
| 595 | */ | |
| 596 | // -reset $0in_falling_edge(`RST.mio_rst_pwron_rst_l) | |
| 597 | ||
| 598 | // PROP_TIME delay for POR1, POR2 and WMR1 | |
| 599 | /* 0in assert_follower | |
| 600 | -leader $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 601 | -follower $0in_rising_edge(`RST.rst_tcu_flush_stop_req) | |
| 602 | -min prop_time | |
| 603 | -active (por2_state | wmr1_state | wmr2_state ) | |
| 604 | -module rst | |
| 605 | -clock `RST.ccu_rst_sys_clk | |
| 606 | -name af_prop_time_delay_flush | |
| 607 | -group rst_chkr | |
| 608 | */ | |
| 609 | ||
| 610 | //<<<<<<<Section C : ASIC block NIU reset & PEU_DMU reset >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>// | |
| 611 | // Check the assertion of asic warm reset | |
| 612 | /* 0in assert_window | |
| 613 | -start $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 614 | -stop $0in_rising_edge(`RST.rst_tcu_flush_stop_req) | |
| 615 | -in !`RST.rst_niu_wmr_ !`RST.rst_dmu_peu_wmr_ !`RST.rst_mio_pex_reset_l !`RST.rst_l2_wmr_ | |
| 616 | -module rst | |
| 617 | -clock l2clk | |
| 618 | -name aw_niu_peu_dmu_wmr_assrt1 | |
| 619 | -active (!init_state && !DEBUG_RST) | |
| 620 | -group rst_chkr | |
| 621 | */ | |
| 622 | ||
| 623 | // Check the deassertion of asic warm reset | |
| 624 | // restored this assertion Sep 16 '05. | |
| 625 | /* 0in assert_window | |
| 626 | -start $0in_rising_edge(`RST.tcu_rst_flush_stop_ack ) | |
| 627 | -stop $0in_rising_edge(`RST.rst_tcu_flush_init_req ) | |
| 628 | -in $0in_rising_edge(`RST.rst_niu_wmr_) | |
| 629 | $0in_rising_edge(`RST.rst_dmu_peu_wmr_) | |
| 630 | `RST.rst_mio_pex_reset_l | |
| 631 | $0in_rising_edge(`RST.rst_l2_wmr_ ) | |
| 632 | -module rst | |
| 633 | -clock l2clk | |
| 634 | -name aw_niu_peu_dmu_wmr_deassrt | |
| 635 | -active (!init_state && !DEBUG_RST) | |
| 636 | -group rst_chkr | |
| 637 | */ | |
| 638 | ||
| 639 | // Check the assertion of asic por reset | |
| 640 | ||
| 641 | // rst_niu_wmr_ assertion when MAC_PROTECT bit not set. Sep 19 '05. | |
| 642 | /* 0in assert_window | |
| 643 | -start $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 644 | -stop $0in_rising_edge(`RST.rst_tcu_flush_stop_req) | |
| 645 | -in !`RST.rst_niu_mac_ | |
| 646 | -module rst | |
| 647 | -clock l2clk | |
| 648 | -name aw_niu_mac_assrt | |
| 649 | -active (!init_state && !DEBUG_RST && !`RST.rst_fsm_ctl.ssys_reset_q[6] && `RST.ccu_rst_change) | |
| 650 | -group rst_chkr | |
| 651 | */ | |
| 652 | ||
| 653 | /* 0in assert_timer | |
| 654 | -var !`RST.rst_niu_mac_ | |
| 655 | -min niu_time | |
| 656 | -name at_mac_pll_lock_delay | |
| 657 | -module rst | |
| 658 | -clock `RST.ccu_rst_sys_clk | |
| 659 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 660 | -group rst_chkr | |
| 661 | */ | |
| 662 | ||
| 663 | // DH: 09/19/06 This checker is failing during FC full reset simulation | |
| 664 | ||
| 665 | /* -0in- assert_timer | |
| 666 | -var !`RST.rst_dmu_peu_wmr_ | |
| 667 | -min dmu_time | |
| 668 | -name at_dmu_peu_wmr_delay | |
| 669 | -module rst | |
| 670 | -clock `RST.ccu_rst_sys_clk | |
| 671 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 672 | -group rst_chkr | |
| 673 | */ | |
| 674 | ||
| 675 | //<<<<<<<< EFUSE related tcu-efu interface signals >>>>>>>>>>>>>>>>>>>>>>// | |
| 676 | ||
| 677 | /* 0in assert_window | |
| 678 | -start `TCU.tcu_rst_flush_stop_ack | |
| 679 | -stop `TCU.tcu_efu_read_start | |
| 680 | -in (&`TCU.tcu_efu_rvclr) | |
| 681 | -module tcu | |
| 682 | -clock l2clk | |
| 683 | -active ((por1_state | por_unpark_state) & (~`CPU.TESTMODE)) | |
| 684 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 685 | -name aw_efu_rvclr | |
| 686 | -group rst_chkr | |
| 687 | */ | |
| 688 | ||
| 689 | /* 0in assert_follower | |
| 690 | -leader $0in_rising_edge((&`TCU.tcu_efu_rvclr)) | |
| 691 | -follower $0in_rising_edge(`TCU.tcu_efu_read_start ) | |
| 692 | -min 8 | |
| 693 | -module tcu | |
| 694 | -clock l2clk | |
| 695 | -name af_efu_rvclr_efu_read_start | |
| 696 | -active (por1_state | por_unpark_state) | |
| 697 | -group rst_chkr | |
| 698 | */ | |
| 699 | ||
| 700 | //<<<<<<<Section D : POR1 specific assertions >>>>>>>>>>>>>>>>>>>>>// | |
| 701 | /* 0in assert_follower | |
| 702 | -leader $0in_rising_edge(`RST.ccu_rst_sync_stable) | |
| 703 | -follower $0in_rising_edge(`RST.rst_tcu_asicflush_stop_req ) | |
| 704 | -max 64 | |
| 705 | -module rst | |
| 706 | -clock ccu_rst_sys_clk | |
| 707 | -name af_asicstop_req_assrt_por1 | |
| 708 | -active (por1_state) | |
| 709 | -group rst_chkr | |
| 710 | */ | |
| 711 | ||
| 712 | /* 0in assert_follower | |
| 713 | -leader $0in_rising_edge(`RST.mio_rst_pwron_rst_l) | |
| 714 | -follower $0in_rising_edge(`RST.rst_ccu_pll_ ) | |
| 715 | -max 5 | |
| 716 | -module rst | |
| 717 | -clock ccu_rst_sys_clk | |
| 718 | -name at_rst_ccu_pll -active (por1_state) | |
| 719 | -group rst_chkr | |
| 720 | */ //RST_CCU interface assertion | |
| 721 | ||
| 722 | /* 0in assert_follower | |
| 723 | -leader $0in_rising_edge(`RST.rst_ccu_pll_) | |
| 724 | -follower $0in_rising_edge(`RST.rst_ccu_) | |
| 725 | -min lock_time | |
| 726 | -active ( por1_state || (wmr1_state && `RST.ccu_rst_change)) | |
| 727 | -module rst | |
| 728 | -clock ccu_rst_sys_clk | |
| 729 | -name af_ccu_pll_rst_ccu | |
| 730 | -group rst_chkr | |
| 731 | */ //RST_CCU interface assertion | |
| 732 | ||
| 733 | /* 0in assert_window | |
| 734 | -start `RST.rst_ccu_ | |
| 735 | -stop `RST.rst_tcu_asicflush_stop_req | |
| 736 | -in `RST.ccu_rst_sync_stable | |
| 737 | -module rst | |
| 738 | -clock l2clk | |
| 739 | -name aw_ccu_rst_sync_stable_por1 | |
| 740 | -group rst_chkr | |
| 741 | -active (por1_state) | |
| 742 | */ | |
| 743 | ||
| 744 | wire asic_clk_stop , asic_clk_start; | |
| 745 | assign asic_clk_stop = `TCU.tcu_dmu_io_clk_stop & `TCU.tcu_rdp_io_clk_stop & | |
| 746 | `TCU.tcu_rtx_io_clk_stop & `TCU.tcu_tds_io_clk_stop & | |
| 747 | `TCU.tcu_peu_pc_clk_stop & `TCU.tcu_peu_io_clk_stop; | |
| 748 | assign asic_clk_start = !`TCU.tcu_dmu_io_clk_stop & !`TCU.tcu_rdp_io_clk_stop & | |
| 749 | !`TCU.tcu_rtx_io_clk_stop & !`TCU.tcu_tds_io_clk_stop & | |
| 750 | !`TCU.tcu_peu_pc_clk_stop & !`TCU.tcu_peu_io_clk_stop; | |
| 751 | ||
| 752 | /* 0in assert_window | |
| 753 | -start `TCU.rst_tcu_asicflush_stop_req | |
| 754 | -stop `TCU.tcu_rst_asicflush_stop_ack | |
| 755 | -in asic_clk_start !`TCU.tcu_asic_scan_en | |
| 756 | -module tcu | |
| 757 | -clock l2clk | |
| 758 | -name aw_asic_flushstop_req | |
| 759 | -active (por1_state) | |
| 760 | -group rst_chkr | |
| 761 | */ | |
| 762 | ||
| 763 | // Clock contention prevention signals | |
| 764 | /* 0in assert -and | |
| 765 | -var !`RST.cluster_arst_l `TCU.tcu_asic_scan_en asic_clk_stop | |
| 766 | -module rst | |
| 767 | -clock ccu_rst_sys_clk | |
| 768 | -name a_clk_contention_sigs | |
| 769 | -active !`RST.mio_rst_pwron_rst_l | |
| 770 | -group rst_chkr | |
| 771 | */ | |
| 772 | ||
| 773 | /* 0in assert_follower | |
| 774 | -leader $0in_rising_edge(`RST.rst_ccu_) | |
| 775 | -follower $0in_rising_edge(`RST.cluster_arst_l) | |
| 776 | -min ccu_time | |
| 777 | -active por1_state | |
| 778 | -module rst | |
| 779 | -clock ccu_rst_sys_clk | |
| 780 | -name af_rst_ccu_cluster_arst_l | |
| 781 | -group rst_chkr | |
| 782 | */ | |
| 783 | ||
| 784 | /* 0in assert_follower | |
| 785 | -leader $0in_falling_edge(`TCU.tcu_asic_scan_en) | |
| 786 | -follower $0in_falling_edge(asic_clk_stop) | |
| 787 | -max 8 | |
| 788 | -active por1_state | |
| 789 | -module tcu | |
| 790 | -clock l2clk | |
| 791 | -name af_tcu_asic_scan_en_asic_clk_stop | |
| 792 | -group rst_chkr | |
| 793 | */ | |
| 794 | // END Clock contention prevention signals | |
| 795 | ||
| 796 | /* 0in assert_follower | |
| 797 | -leader $0in_rising_edge(`RST.rst_tcu_pwron_rst_l) | |
| 798 | -follower $0in_rising_edge(`TCU.rst_tcu_asicflush_stop_req ) | |
| 799 | -min 8 | |
| 800 | -active por1_state | |
| 801 | -module tcu | |
| 802 | -clock l2clk | |
| 803 | -name af_tcu_pwron_asicflush_stop_req | |
| 804 | -group rst_chkr | |
| 805 | *///Circuit delay requirement : Tom email date 10/13/05 | |
| 806 | ||
| 807 | /* 0in assert_follower | |
| 808 | -leader $0in_rising_edge(`RST.tcu_rst_asicflush_stop_ack) | |
| 809 | -follower (`RST.rst_niu_mac_ & `RST.rst_niu_wmr_) | |
| 810 | -min niu_time | |
| 811 | -active por1_state | |
| 812 | -module rst | |
| 813 | -clock ccu_rst_sys_clk | |
| 814 | -name af_rst_niu_mac_por | |
| 815 | -group rst_chkr | |
| 816 | */ | |
| 817 | ||
| 818 | /* 0in assert_follower | |
| 819 | -leader $0in_rising_edge(`RST.tcu_rst_asicflush_stop_ack) | |
| 820 | -follower $0in_rising_edge(`RST.rst_dmu_peu_por_ ) | |
| 821 | -min niu_time | |
| 822 | -active por1_state | |
| 823 | -module rst | |
| 824 | -clock ccu_rst_sys_clk | |
| 825 | -name af_rst_dmu_peu_por | |
| 826 | -group rst_chkr | |
| 827 | */ | |
| 828 | ||
| 829 | /* 0in assert_follower | |
| 830 | -leader $0in_rising_edge(`RST.tcu_rst_asicflush_stop_ack) | |
| 831 | -follower $0in_rising_edge(`RST.rst_dmu_async_por_ ) | |
| 832 | -min niu_time | |
| 833 | -active por1_state | |
| 834 | -module rst | |
| 835 | -clock ccu_rst_sys_clk | |
| 836 | -name af_rst_dmu_async_por | |
| 837 | -group rst_chkr | |
| 838 | */ | |
| 839 | ||
| 840 | /* 0in assert_follower | |
| 841 | -leader $0in_rising_edge(`RST.tcu_rst_asicflush_stop_ack) | |
| 842 | -follower (`RST.rst_tcu_flush_stop_req ) | |
| 843 | -min niu_time | |
| 844 | -active por1_state | |
| 845 | -module rst | |
| 846 | -clock ccu_rst_sys_clk | |
| 847 | -name af_rst_tcu_flush_stop_req_por1 | |
| 848 | -group rst_chkr | |
| 849 | */ | |
| 850 | ||
| 851 | /* 0in assert_follower | |
| 852 | -leader $0in_rising_edge(`RST.tcu_rst_flush_stop_ack) | |
| 853 | -follower $0in_rising_edge(`RST.rst_l2_por_) | |
| 854 | -min 1 | |
| 855 | -module rst | |
| 856 | -clock ccu_rst_sys_clk | |
| 857 | -name af_rst_l2_por | |
| 858 | -active (por1_state) | |
| 859 | -group rst_chkr | |
| 860 | */ // Should be also specified for other phases. 03/17 This signal shd go away, when dont know | |
| 861 | // Aug 26 - I guess will not go away | |
| 862 | ||
| 863 | /* 0in assert_window | |
| 864 | -start `RST.tcu_rst_flush_stop_ack | |
| 865 | -stop `RST.rst_tcu_flush_init_req | |
| 866 | -in `RST.rst_l2_por_ | |
| 867 | -module rst -name aw_rst_l2_por | |
| 868 | -clock l2clk | |
| 869 | -active (por1_state ) | |
| 870 | -group rst_chkr | |
| 871 | */ // Solved 03/17 This signal shd go away, when dont know | |
| 872 | // Aug 26 - I guess will not go away | |
| 873 | ||
| 874 | /* 0in assert_window | |
| 875 | -start `RST.tcu_rst_flush_stop_ack | |
| 876 | -stop `RST.tcu_bisx_done | |
| 877 | -in `RST.tcu_rst_efu_done | |
| 878 | -module rst | |
| 879 | -clock ccu_rst_sys_clk | |
| 880 | -name aw_efu_done_assrt | |
| 881 | -active (por1_state) | |
| 882 | -group rst_chkr | |
| 883 | */ | |
| 884 | ||
| 885 | /* 0in assert_window | |
| 886 | -start `RST.tcu_rst_flush_stop_ack | |
| 887 | -stop `RST.rst_tcu_flush_init_req | |
| 888 | -in `RST.tcu_bisx_done | |
| 889 | -module rst | |
| 890 | -clock ccu_rst_sys_clk | |
| 891 | -name aw_bisx_done_assrt | |
| 892 | -active ($0in_delay(por1_state,3)) | |
| 893 | -group rst_chkr | |
| 894 | */ | |
| 895 | ||
| 896 | /* 0in assert_window | |
| 897 | -start `TCU.tcu_rst_flush_stop_ack | |
| 898 | -stop `TCU.tcu_bisx_done | |
| 899 | -in `TCU.tcu_mbist_bisi_en | |
| 900 | -module tcu | |
| 901 | -clock l2clk | |
| 902 | -name aw_tcu_mbist_bisi_en | |
| 903 | -active ($0in_delay(por1_state,3)) | |
| 904 | -group rst_chkr | |
| 905 | */ | |
| 906 | ||
| 907 | //<<<<<< Section E : POR2 specific assertions >>>>>>>>>>>>>>>>>>>>>>>>>// | |
| 908 | ||
| 909 | /* 0in assert_follower | |
| 910 | -leader $0in_rising_edge(`TCU.tcu_rst_flush_stop_ack) | |
| 911 | -follower $0in_rising_edge(`TCU.tcu_efu_read_start) | |
| 912 | -min 8 | |
| 913 | -module tcu | |
| 914 | -clock l2clk | |
| 915 | -name af_tcu_efu_read_start_delay | |
| 916 | -group rst_chkr | |
| 917 | -active (por1_state | por2_state | por_unpark_state) | |
| 918 | */ // Valid for por1 and por2 -- minimum 8 cycle delay after clock starting | |
| 919 | ||
| 920 | /* 0in assert_window | |
| 921 | -start `RST.tcu_rst_efu_done | |
| 922 | -stop_count 50 | |
| 923 | -in `RST.rst_ncu_unpark_thread | |
| 924 | -module rst | |
| 925 | -name aw_unpark_thread_assrt_por2_2 | |
| 926 | -clock iol2clk | |
| 927 | -active (por_unpark_state) | |
| 928 | -reset $0in_falling_edge(`RST.rst_tcu_pwron_rst_l) | |
| 929 | -group rst_chkr | |
| 930 | */ | |
| 931 | ||
| 932 | //<<<<<<< Section F : WMR1 specifics assertions>>>>>>>>>>>>>>>>>>>>>>>>>>>// | |
| 933 | // ASIC should not be flushed during warm reset | |
| 934 | /*0in assert | |
| 935 | -var !`TCU.tcu_asic_scan_en | |
| 936 | -module tcu | |
| 937 | -clock l2clk | |
| 938 | -name a_asic_scan_en | |
| 939 | -active (wmr1_state | wmr2_state) | |
| 940 | -group rst_chkr | |
| 941 | */ | |
| 942 | ||
| 943 | /*0in assert | |
| 944 | -var `RST.rst_wmr_protect | |
| 945 | -module rst | |
| 946 | -clock ccu_rst_sys_clk | |
| 947 | -name a_rst_wmr_protect_assrt | |
| 948 | -active (wmr1_state || wmr2_state) | |
| 949 | -group rst_chkr | |
| 950 | */ | |
| 951 | ||
| 952 | /* 0in assert_follower | |
| 953 | -leader `RST.rst_fsm_ctl.ssys_reset_q[5] | |
| 954 | -follower `RST.rst_mcu_selfrsh | |
| 955 | -max 4 | |
| 956 | -module rst | |
| 957 | -max_leader_check off | |
| 958 | -name a_rst_mcu_selfrsh | |
| 959 | -clock iol2clk | |
| 960 | -group rst_chkr | |
| 961 | */ | |
| 962 | ||
| 963 | /* 0in assert_follower | |
| 964 | -leader $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 965 | -follower $0in_falling_edge(`RST.rst_ccu_pll_) | |
| 966 | -max 14 | |
| 967 | -known_follower | |
| 968 | -max_leader_check off | |
| 969 | -module rst | |
| 970 | -clock ccu_rst_sys_clk | |
| 971 | -name af_init_ack_rst_ccu_pll_wmr1 | |
| 972 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 973 | -group rst_chkr | |
| 974 | */ //RST_CCU interface assertion | |
| 975 | ||
| 976 | /* 0in assert_follower | |
| 977 | -leader $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 978 | -follower $0in_falling_edge(`RST.rst_ccu_) | |
| 979 | -max 14 | |
| 980 | -known_follower | |
| 981 | -max_leader_check off | |
| 982 | -module rst | |
| 983 | -clock ccu_rst_sys_clk | |
| 984 | -name af_init_ack_rst_ccu_wmr1 | |
| 985 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 986 | -group rst_chkr | |
| 987 | */ //RST_CCU interface assertion | |
| 988 | ||
| 989 | // Stop TCU clock before reset pll | |
| 990 | /* 0in assert_window | |
| 991 | -start $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 992 | -stop $0in_rising_edge(`RST.rst_ccu_pll_) | |
| 993 | -in $0in_rising_edge(`RST.rst_tcu_clk_stop) | |
| 994 | -module rst | |
| 995 | -clock ccu_rst_sys_clk | |
| 996 | -name aw_rst_tcu_clk_stop_wmr1 | |
| 997 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 998 | -group rst_chkr | |
| 999 | */ | |
| 1000 | ||
| 1001 | /* 0in assert_window | |
| 1002 | -start $0in_rising_edge(`RST.tcu_rst_flush_init_ack) | |
| 1003 | -stop $0in_rising_edge(`RST.rst_tcu_flush_stop_req) | |
| 1004 | -in $0in_falling_edge(`RST.rst_tcu_clk_stop) | |
| 1005 | -module rst | |
| 1006 | -clock ccu_rst_sys_clk | |
| 1007 | -name aw_rst_tcu_clk_stop_wmr1_deassert | |
| 1008 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 1009 | -group rst_chkr | |
| 1010 | */ | |
| 1011 | ||
| 1012 | /* 0in assert_follower | |
| 1013 | -leader $0in_rising_edge(`RST.rst_ccu_pll_) | |
| 1014 | -follower $0in_rising_edge(rst_ccu_) | |
| 1015 | -min lock_time | |
| 1016 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 1017 | -module rst | |
| 1018 | -clock ccu_rst_sys_clk | |
| 1019 | -name af_rst_ccu_pll_rst_ccu_wmr1 | |
| 1020 | -group rst_chkr | |
| 1021 | */ //RST_CCU interface assertion | |
| 1022 | ||
| 1023 | /* 0in assert_follower | |
| 1024 | -leader $0in_rising_edge(`RST.rst_ccu_) | |
| 1025 | -follower $0in_rising_edge(`RST.ccu_rst_sync_stable) | |
| 1026 | -max sync_stable_time | |
| 1027 | -module rst | |
| 1028 | -clock ccu_rst_sys_clk | |
| 1029 | -name af_ccu_rst_sync_stable_wmr1 | |
| 1030 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 1031 | -group rst_chkr | |
| 1032 | */ //RST_CCU interface assertion | |
| 1033 | ||
| 1034 | /* Comment for BUGID 119939 0in assert_follower | |
| 1035 | -leader $0in_rising_edge(`RST.ccu_rst_sync_stable) | |
| 1036 | -follower $0in_falling_edge(`RST.rst_tcu_clk_stop) | |
| 1037 | -max 64 | |
| 1038 | -known_follower | |
| 1039 | -max_leader_check off | |
| 1040 | -module rst | |
| 1041 | -clock ccu_rst_sys_clk | |
| 1042 | -name af_deassert_tcu_clk_stop_wmr1 | |
| 1043 | -active (wmr1_state && `RST.ccu_rst_change) | |
| 1044 | -group rst_chkr | |
| 1045 | */ | |
| 1046 | ||
| 1047 | // No rst signals to CCU when chng=0 or wmr2 | |
| 1048 | /* 0in assert | |
| 1049 | -and -var `RST.rst_ccu_pll_ `RST.rst_ccu_ | |
| 1050 | -module rst | |
| 1051 | -name a_rst_ccu_pll_wmr | |
| 1052 | -clock ccu_rst_sys_clk | |
| 1053 | -active (wmr2_state || (wmr1_state && !`RST.ccu_rst_change) ) | |
| 1054 | -message "Reset signal to ccu should NOT be asserted during this warm reset" | |
| 1055 | -group rst_chkr | |
| 1056 | */ //RST_CCU interface assertion | |
| 1057 | ||
| 1058 | //Transition from WMR1 to WMR2 check | |
| 1059 | /* 0in assert_window | |
| 1060 | -start `RST.tcu_rst_flush_stop_ack | |
| 1061 | -stop `RST.rst_tcu_flush_init_req | |
| 1062 | -in `RST.tcu_bisx_done | |
| 1063 | -module rst | |
| 1064 | -clock ccu_rst_sys_clk | |
| 1065 | -name aw_bisx_done_assrt_wmr1 | |
| 1066 | -active (wmr1_state | wmr2gen_state) | |
| 1067 | -group rst_chkr | |
| 1068 | */ | |
| 1069 | //<<<<<<< Section G : WMR2 specific assertions>>>>>>>>>>>>>>>>>>>>>>// | |
| 1070 | ||
| 1071 | /* 0in assert_follower | |
| 1072 | -leader $0in_rising_edge(`RST.tcu_rst_flush_stop_ack) | |
| 1073 | -follower $0in_rising_edge(`RST.rst_ncu_unpark_thread) | |
| 1074 | -known_follower | |
| 1075 | -assert_follower off | |
| 1076 | -max_leader_check off | |
| 1077 | -module rst | |
| 1078 | -clock l2clk | |
| 1079 | -name af_unpark_thread_assrt_wmr2 | |
| 1080 | -active (wmr2_state || unpark_state) | |
| 1081 | -group rst_chkr | |
| 1082 | */ | |
| 1083 | ||
| 1084 | /* 0in assert_follower | |
| 1085 | -leader $0in_rising_edge(`RST.tcu_rst_flush_stop_ack) | |
| 1086 | -follower $0in_rising_edge(`RST.rst_niu_wmr_) | |
| 1087 | -min niu_time | |
| 1088 | -name af_wmr2_niu_time_wait | |
| 1089 | -module rst | |
| 1090 | -clock ccu_rst_sys_clk | |
| 1091 | -active ((wmr2_state | unpark_state) & !DEBUG_RST) | |
| 1092 | -group rst_chkr | |
| 1093 | */ | |
| 1094 | ||
| 1095 | ||
| 1096 | //<<<<<< Section H: XIR sequence check assertions >>>>>>>>>>>>>>>>>>>// | |
| 1097 | /* 0in assert_follower | |
| 1098 | -leader $0in_rising_edge(xir_rst_active) | |
| 1099 | -follower $0in_falling_edge(`RST.rst_ncu_xir_) | |
| 1100 | -known_follower | |
| 1101 | -assert_follower off | |
| 1102 | -max_leader_check off | |
| 1103 | -module rst | |
| 1104 | -clock iol2clk | |
| 1105 | -name af_rst_ncu_xir_done | |
| 1106 | -active `RST.rst_ncu_xir_ | |
| 1107 | -group rst_chkr | |
| 1108 | */ | |
| 1109 | ||
| 1110 | /* 0in req_ack | |
| 1111 | -req !`RST.rst_ncu_xir_ | |
| 1112 | -ack `RST.ncu_rst_xir_done | |
| 1113 | -req_until_ack on | |
| 1114 | -module rst | |
| 1115 | -clock iol2clk | |
| 1116 | -name rq_ack_ncu_xir_done | |
| 1117 | -reset ($0in_falling_edge(`RST.mio_rst_pwron_rst_l) || !init_state ) | |
| 1118 | -group rst_chkr | |
| 1119 | */ | |
| 1120 | ||
| 1121 | //<<<<<<<<< Section I: Miscellaneous >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>// | |
| 1122 | ||
| 1123 | //Ensure unpark_thread is not asserted during any phase other than por2 and wmr2 | |
| 1124 | ||
| 1125 | // commented out the following Nov 2 '05. | |
| 1126 | // It was firing at the end of WMR2 that was initiated by: | |
| 1127 | // l2t1_fatal_error | |
| 1128 | // l2t3_fatal_error | |
| 1129 | // l2t4_fatal_error and | |
| 1130 | // l2t6_fatal_error in tcu_rst_wmr_L2T_error.vr at 84702500ps. | |
| 1131 | ||
| 1132 | /* 0in assert | |
| 1133 | -var !`RST.rst_ncu_unpark_thread | |
| 1134 | -module rst -name a_rst_ncu_unpark_thread | |
| 1135 | -active (por1_state || por2_state || wmr1_state || wmr2_state) | |
| 1136 | -clock clk | |
| 1137 | -message "Signal should not have been asserted : unpark_thread" | |
| 1138 | -group rst_chkr | |
| 1139 | */ | |
| 1140 | ||
| 1141 | ||
| 1142 | /* 0in assert | |
| 1143 | -var `RST.rst_dmu_peu_por_ | |
| 1144 | -module rst | |
| 1145 | -clock ccu_rst_sys_clk | |
| 1146 | -name a_rst_dmu_peu_por_ | |
| 1147 | -active ((init_state | wmr1_state | wmr2_state) & PWR_ON ) | |
| 1148 | -message "Signal should not have been asserted : rst_dmu_peu_por_" | |
| 1149 | -group rst_chkr | |
| 1150 | */ | |
| 1151 | ||
| 1152 | // Removed the following 2 assertions because they are no longer valid for | |
| 1153 | // the new timing requirements on these asic block reset signal | |
| 1154 | /* Remove0in assert | |
| 1155 | -var `RST.rst_niu_wmr_ | |
| 1156 | -module rst | |
| 1157 | -clock ccu_rst_sys_clk | |
| 1158 | -name a_rst_niu_wmr_ | |
| 1159 | -active ((init_state & PWR_ON & !`RST.rst_fsm_ctl.data_in_sys[0] & !`RST.rst_fsm_ctl.ssys_reset_addr) | | |
| 1160 | ((wmr1_state | wmr2_state) & DEBUG_RST) ) | |
| 1161 | -message "Signal should not have been asserted : rst_niu_wmr_" | |
| 1162 | -group rst_chkr | |
| 1163 | */ | |
| 1164 | /* Remove0in assert | |
| 1165 | -var `RST.rst_dmu_peu_wmr_ | |
| 1166 | -module rst | |
| 1167 | -clock ccu_rst_sys_clk | |
| 1168 | -name a_rst_dmu_peu_wmr | |
| 1169 | -active ((init_state & PWR_ON & !`RST.rst_fsm_ctl.data_in_sys[1] & !`RST.rst_fsm_ctl.ssys_reset_addr) | | |
| 1170 | ((wmr1_state | wmr2_state) & DEBUG_RST) ) | |
| 1171 | -message "Signal should not have been asserted : rst_dmu_peu_wmr_" | |
| 1172 | -group rst_chkr | |
| 1173 | */ | |
| 1174 | ||
| 1175 | // MAC_PROTECT bit to disable reset signal to niu mac | |
| 1176 | /* 0in assert | |
| 1177 | -var `RST.rst_niu_mac_ | |
| 1178 | -name assert_niu_mac_ | |
| 1179 | -module rst | |
| 1180 | -clock ccu_rst_sys_clk | |
| 1181 | -active `RST.rst_fsm_ctl.ssys_reset_q[6] | |
| 1182 | -message "Signal should not have been asserted : rst_niu_mac_" | |
| 1183 | -group rst_chkr | |
| 1184 | */ | |
| 1185 | ||
| 1186 | //<<<<<<<< Section J: MIO interface assertion >>>>>>>>>>>>>>>>>>>>>>// | |
| 1187 | ||
| 1188 | /* 0in assert | |
| 1189 | -var `RST.rst_mio_ssi_sync_l | |
| 1190 | -module rst | |
| 1191 | -clock ccu_rst_sys_clk | |
| 1192 | -name a_rst_mio_ssi_sync_l | |
| 1193 | -active ($0in_delay(por1_state,5) | por2_state | wmr1_state | wmr2_state ) | |
| 1194 | -message "Signal should not have been asserted : rst_mio_ssi_sync_l" | |
| 1195 | -group rst_chkr | |
| 1196 | */ | |
| 1197 | ||
| 1198 | ||
| 1199 | /* 0in assert_follower | |
| 1200 | -leader $0in_falling_edge(tcu_scan_en) | |
| 1201 | -follower $0in_rising_edge(tcu_rst_flush_stop_ack) | |
| 1202 | -min 4 | |
| 1203 | -module rst | |
| 1204 | -active (!init_state) | |
| 1205 | -clock l2clk | |
| 1206 | -name scan_en_time_delay_flush | |
| 1207 | -group rst_chkr | |
| 1208 | */ | |
| 1209 | ||
| 1210 | ||
| 1211 | //<<<<<<<< Section K: Scan_mode assertion >>>>>>>>>>>>>>>>>>>>>>// | |
| 1212 | ||
| 1213 | /* 0in assert | |
| 1214 | -var !`RST.tcu_rst_scan_mode | |
| 1215 | -module rst | |
| 1216 | -clock ccu_rst_sys_clk | |
| 1217 | -name a_tcu_rst_scan_mode | |
| 1218 | -active ((!`CPU.TESTMODE) & (!init_state)) | |
| 1219 | -message "Signal should not have been asserted : tcu_rst_scan_mode" | |
| 1220 | -group rst_chkr | |
| 1221 | */ | |
| 1222 | endmodule // rst_chkr | |
| 1223 | ||
| 1224 |