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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2err_ccm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2err_ccm ( L2_INT_RST,err_cntr); | |
36 | ||
37 | parameter SAMPLE = 3; | |
38 | parameter s0=0,s1=1,S0=0,S1=1; | |
39 | ||
40 | ||
41 | //tb_top tb_top(); | |
42 | ||
43 | //input declarations | |
44 | input L2_INT_RST; | |
45 | ||
46 | //output declarations | |
47 | output [23:0] err_cntr; | |
48 | ||
49 | ||
50 | ||
51 | //reg declarations | |
52 | reg stuck_to0, stuck_to1, rand_bit_flip,err_enable, err_enable_fwd,bit_err_enable,bit_err_enable_c5b; | |
53 | wire take_ade,take_eer,take_retry; | |
54 | reg trph,trpH; | |
55 | reg [3:0] bit_pos; | |
56 | reg [3:0] i; | |
57 | reg [154:0] k; | |
58 | reg [63:0] j; | |
59 | reg [23:0] err_cntr; | |
60 | ||
61 | reg [127:0] way,way_int; | |
62 | reg [23:0] cache_col_offset,cache_col_offset_int; | |
63 | reg [623:0] dataecc,int; | |
64 | reg [23:0] inject_limit; | |
65 | reg [39:0] err_addr; | |
66 | reg injectErr,start_injection; | |
67 | reg Tevent; | |
68 | reg [1:0] cs,ns,cs1,ns1; | |
69 | ||
70 | integer r,m,rand_limit_hi,rand,rand1,rand2; | |
71 | ||
72 | ||
73 | //wire declarations | |
74 | wire [8:0] TRAP_EVENT; | |
75 | wire [39:0] err_addr_0,err_addr_1,err_addr_2,err_addr_3,err_addr_4,err_addr_5; | |
76 | wire [39:0] err_addr_6,err_addr_7; | |
77 | ||
78 | ||
79 | wire [15:0] cache_way_sel_c3_0,cache_way_sel_c3_1,cache_way_sel_c3_2; | |
80 | wire [15:0] cache_way_sel_c3_3,cache_way_sel_c3_4,cache_way_sel_c3_5; | |
81 | wire [15:0] cache_way_sel_c3_6,cache_way_sel_c3_7; | |
82 | wire [15:0] cache_way_sel_c3; | |
83 | ||
84 | wire cache_rd_wr_c3_0,cache_rd_wr_c3_1,cache_rd_wr_c3_2; | |
85 | wire cache_rd_wr_c3_3,cache_rd_wr_c3_4,cache_rd_wr_c3_5; | |
86 | wire cache_rd_wr_c3_6,cache_rd_wr_c3_7; | |
87 | wire [7:0] cache_rd_wr_c3; | |
88 | ||
89 | wire inst_l2data_vld_c4_0,inst_l2data_vld_c4_1; | |
90 | wire inst_l2data_vld_c4_2,inst_l2data_vld_c4_3,inst_l2data_vld_c4_4; | |
91 | wire inst_l2data_vld_c4_5,inst_l2data_vld_c4_6,inst_l2data_vld_c4_7; | |
92 | wire [7:0] inst_l2data_vld_c4; | |
93 | ||
94 | wire [8:0] cache_set_c3_0,cache_set_c3_1,cache_set_c3_2,cache_set_c3_3; | |
95 | wire [8:0] cache_set_c3_4,cache_set_c3_5,cache_set_c3_6,cache_set_c3_7; | |
96 | wire [71:0] cache_set_c3; | |
97 | ||
98 | wire [3:0]cache_col_offset_c3_0,cache_col_offset_c3_1; | |
99 | wire [3:0]cache_col_offset_c3_2,cache_col_offset_c3_3; | |
100 | wire [3:0] cache_col_offset_c3_4,cache_col_offset_c3_5; | |
101 | wire [3:0] cache_col_offset_c3_6,cache_col_offset_c3_7; | |
102 | wire [31:0] cache_col_offset_c3; | |
103 | ||
104 | wire [623:0] cache_decc_out_c52_0,cache_decc_out_c52_1; | |
105 | wire [623:0] cache_decc_out_c52_2,cache_decc_out_c52_3; | |
106 | wire [623:0] cache_decc_out_c52_4,cache_decc_out_c52_5; | |
107 | wire [623:0] cache_decc_out_c52_6,cache_decc_out_c52_7; | |
108 | wire [4991:0] cache_decc_out_c52; | |
109 | ||
110 | /**** | |
111 | wire [623:0] l2d_l2t_decc_c6_0, l2d_l2t_decc_c6_1, l2d_l2t_decc_c6_2; | |
112 | wire [623:0] l2d_l2t_decc_c6_3, l2d_l2t_decc_c6_4, l2d_l2t_decc_c6_5; | |
113 | wire [623:0] l2d_l2t_decc_c6_6, l2d_l2t_decc_c6_7; | |
114 | ***/ | |
115 | ||
116 | wire [155:0] l2d_l2t_decc_c6_0, l2d_l2t_decc_c6_1, l2d_l2t_decc_c6_2; | |
117 | wire [155:0] l2d_l2t_decc_c6_3, l2d_l2t_decc_c6_4, l2d_l2t_decc_c6_5; | |
118 | wire [155:0] l2d_l2t_decc_c6_6, l2d_l2t_decc_c6_7; | |
119 | ||
120 | assign take_retry = tb_top.cpu.spc0.tlu.trl0.take_ret; | |
121 | assign take_eer = tb_top.cpu.spc0.tlu.trl0.take_eer; // For Hw Corr | |
122 | assign take_ade = tb_top.cpu.spc0.tlu.trl0.take_ade; // For Sw Recov | |
123 | ||
124 | assign l2d_l2t_decc_c6_0 = tb_top.cpu.l2d0.l2d_l2t_decc_c6; | |
125 | assign l2d_l2t_decc_c6_1 = tb_top.cpu.l2d1.l2d_l2t_decc_c6; | |
126 | assign l2d_l2t_decc_c6_2 = tb_top.cpu.l2d2.l2d_l2t_decc_c6; | |
127 | assign l2d_l2t_decc_c6_3 = tb_top.cpu.l2d3.l2d_l2t_decc_c6; | |
128 | assign l2d_l2t_decc_c6_4 = tb_top.cpu.l2d4.l2d_l2t_decc_c6; | |
129 | assign l2d_l2t_decc_c6_5 = tb_top.cpu.l2d5.l2d_l2t_decc_c6; | |
130 | assign l2d_l2t_decc_c6_6 = tb_top.cpu.l2d6.l2d_l2t_decc_c6; | |
131 | assign l2d_l2t_decc_c6_7 = tb_top.cpu.l2d7.l2d_l2t_decc_c6; | |
132 | ||
133 | /**** | |
134 | assign l2d_l2t_decc_c6_0 = tb_top.cpu.l2d0.ctr.l2d_l2t_decc_c6; | |
135 | assign l2d_l2t_decc_c6_1 = tb_top.cpu.l2d1.ctr.l2d_l2t_decc_c6; | |
136 | assign l2d_l2t_decc_c6_2 = tb_top.cpu.l2d2.ctr.l2d_l2t_decc_c6; | |
137 | assign l2d_l2t_decc_c6_3 = tb_top.cpu.l2d3.ctr.l2d_l2t_decc_c6; | |
138 | assign l2d_l2t_decc_c6_4 = tb_top.cpu.l2d4.ctr.l2d_l2t_decc_c6; | |
139 | assign l2d_l2t_decc_c6_5 = tb_top.cpu.l2d5.ctr.l2d_l2t_decc_c6; | |
140 | assign l2d_l2t_decc_c6_6 = tb_top.cpu.l2d6.ctr.l2d_l2t_decc_c6; | |
141 | assign l2d_l2t_decc_c6_7 = tb_top.cpu.l2d7.ctr.l2d_l2t_decc_c6; | |
142 | ||
143 | assign l2d_l2t_decc_c6_0 = tb_top.cpu.l2d0.ctr.l2d_decc_out_c6; | |
144 | assign l2d_l2t_decc_c6_1 = tb_top.cpu.l2d1.ctr.l2d_decc_out_c6; | |
145 | assign l2d_l2t_decc_c6_2 = tb_top.cpu.l2d2.ctr.l2d_decc_out_c6; | |
146 | assign l2d_l2t_decc_c6_3 = tb_top.cpu.l2d3.ctr.l2d_decc_out_c6; | |
147 | assign l2d_l2t_decc_c6_4 = tb_top.cpu.l2d4.ctr.l2d_decc_out_c6; | |
148 | assign l2d_l2t_decc_c6_5 = tb_top.cpu.l2d5.ctr.l2d_decc_out_c6; | |
149 | assign l2d_l2t_decc_c6_6 = tb_top.cpu.l2d6.ctr.l2d_decc_out_c6; | |
150 | assign l2d_l2t_decc_c6_7 = tb_top.cpu.l2d7.ctr.l2d_decc_out_c6; | |
151 | *****/ | |
152 | ||
153 | ||
154 | ||
155 | assign err_addr_0 = tb_top.cpu.l2t0.arbadr.arbdp_addr_c2; | |
156 | assign err_addr_1 = tb_top.cpu.l2t1.arbadr.arbdp_addr_c2; | |
157 | assign err_addr_2 = tb_top.cpu.l2t2.arbadr.arbdp_addr_c2; | |
158 | assign err_addr_3 = tb_top.cpu.l2t3.arbadr.arbdp_addr_c2; | |
159 | assign err_addr_4 = tb_top.cpu.l2t4.arbadr.arbdp_addr_c2; | |
160 | assign err_addr_5 = tb_top.cpu.l2t5.arbadr.arbdp_addr_c2; | |
161 | assign err_addr_6 = tb_top.cpu.l2t6.arbadr.arbdp_addr_c2; | |
162 | assign err_addr_7 = tb_top.cpu.l2t7.arbadr.arbdp_addr_c2; | |
163 | ||
164 | //assign TRAP_EVENT = tb_top.cpu.spc0.tlu.trl0_trap_type; | |
165 | assign TRAP_EVENT = tb_top.cpu.spc0.tlu.tsd0_wr_trap_type; | |
166 | ||
167 | assign cache_way_sel_c3_0 = tb_top.cpu.l2d0.ctr.l2t_l2d_way_sel_c3; | |
168 | assign cache_way_sel_c3_1 = tb_top.cpu.l2d1.ctr.l2t_l2d_way_sel_c3; | |
169 | assign cache_way_sel_c3_2 = tb_top.cpu.l2d2.ctr.l2t_l2d_way_sel_c3; | |
170 | assign cache_way_sel_c3_3 = tb_top.cpu.l2d3.ctr.l2t_l2d_way_sel_c3; | |
171 | assign cache_way_sel_c3_4 = tb_top.cpu.l2d4.ctr.l2t_l2d_way_sel_c3; | |
172 | assign cache_way_sel_c3_5 = tb_top.cpu.l2d5.ctr.l2t_l2d_way_sel_c3; | |
173 | assign cache_way_sel_c3_6 = tb_top.cpu.l2d6.ctr.l2t_l2d_way_sel_c3; | |
174 | assign cache_way_sel_c3_7 = tb_top.cpu.l2d7.ctr.l2t_l2d_way_sel_c3; | |
175 | ||
176 | //assign cache_way_sel_c3 = {cache_way_sel_c3_7,cache_way_sel_c3_6,cache_way_sel_c3_5,cache_way_sel_c3_4,cache_way_sel_c3_3,cache_way_sel_c3_2,cache_way_sel_c3_1,cache_way_sel_c3_0}; | |
177 | ||
178 | ||
179 | assign cache_way_sel_c3[0] = (cache_way_sel_c3_7[0] || cache_way_sel_c3_6[0] || cache_way_sel_c3_5[0] || cache_way_sel_c3_4[0] || cache_way_sel_c3_3[0] || cache_way_sel_c3_2[0] || cache_way_sel_c3_1[0] || cache_way_sel_c3_0[0]); | |
180 | ||
181 | assign cache_way_sel_c3[1] = (cache_way_sel_c3_7[1] || cache_way_sel_c3_6[1] || cache_way_sel_c3_5[1] || cache_way_sel_c3_4[1] || cache_way_sel_c3_3[1] || cache_way_sel_c3_2[1] || cache_way_sel_c3_1[1] || cache_way_sel_c3_0[1]); | |
182 | ||
183 | assign cache_way_sel_c3[2] = (cache_way_sel_c3_7[2] || cache_way_sel_c3_6[2] || cache_way_sel_c3_5[2] || cache_way_sel_c3_4[2] || cache_way_sel_c3_3[2] || cache_way_sel_c3_2[2] || cache_way_sel_c3_1[2] || cache_way_sel_c3_0[2]); | |
184 | ||
185 | assign cache_way_sel_c3[3] = (cache_way_sel_c3_7[3] || cache_way_sel_c3_6[3] || cache_way_sel_c3_5[3] || cache_way_sel_c3_4[3] || cache_way_sel_c3_3[3] || cache_way_sel_c3_2[3] || cache_way_sel_c3_1[3] || cache_way_sel_c3_0[3]); | |
186 | ||
187 | assign cache_way_sel_c3[4] = (cache_way_sel_c3_7[4] || cache_way_sel_c3_6[4] || cache_way_sel_c3_5[4] || cache_way_sel_c3_4[4] || cache_way_sel_c3_3[4] || cache_way_sel_c3_2[4] || cache_way_sel_c3_1[4] || cache_way_sel_c3_0[4]); | |
188 | ||
189 | assign cache_way_sel_c3[5] = (cache_way_sel_c3_7[5] || cache_way_sel_c3_6[5] || cache_way_sel_c3_5[5] || cache_way_sel_c3_4[5] || cache_way_sel_c3_3[5] || cache_way_sel_c3_2[5] || cache_way_sel_c3_1[5] || cache_way_sel_c3_0[5]); | |
190 | ||
191 | assign cache_way_sel_c3[6] = (cache_way_sel_c3_7[6] || cache_way_sel_c3_6[6] || cache_way_sel_c3_5[6] || cache_way_sel_c3_4[6] || cache_way_sel_c3_3[6] || cache_way_sel_c3_2[6] || cache_way_sel_c3_1[6] || cache_way_sel_c3_0[6]); | |
192 | ||
193 | assign cache_way_sel_c3[7] = (cache_way_sel_c3_7[7] || cache_way_sel_c3_6[7] || cache_way_sel_c3_5[7] || cache_way_sel_c3_4[7] || cache_way_sel_c3_3[7] || cache_way_sel_c3_2[7] || cache_way_sel_c3_1[7] || cache_way_sel_c3_0[7]); | |
194 | ||
195 | assign cache_way_sel_c3[8] = (cache_way_sel_c3_7[8] || cache_way_sel_c3_6[8] || cache_way_sel_c3_5[8] || cache_way_sel_c3_4[8] || cache_way_sel_c3_3[8] || cache_way_sel_c3_2[8] || cache_way_sel_c3_1[8] || cache_way_sel_c3_0[8]); | |
196 | ||
197 | assign cache_way_sel_c3[9] = (cache_way_sel_c3_7[9] || cache_way_sel_c3_6[9] || cache_way_sel_c3_5[9] || cache_way_sel_c3_4[9] || cache_way_sel_c3_3[9] || cache_way_sel_c3_2[9] || cache_way_sel_c3_1[9] || cache_way_sel_c3_0[9]); | |
198 | ||
199 | assign cache_way_sel_c3[10] = (cache_way_sel_c3_7[10] || cache_way_sel_c3_6[10] || cache_way_sel_c3_5[10] || cache_way_sel_c3_4[10] || cache_way_sel_c3_3[10] || cache_way_sel_c3_2[10] || cache_way_sel_c3_1[10] || cache_way_sel_c3_0[10]); | |
200 | ||
201 | assign cache_way_sel_c3[11] = (cache_way_sel_c3_7[11] || cache_way_sel_c3_6[11] || cache_way_sel_c3_5[11] || cache_way_sel_c3_4[11] || cache_way_sel_c3_3[11] || cache_way_sel_c3_2[11] || cache_way_sel_c3_1[11] || cache_way_sel_c3_0[11]); | |
202 | ||
203 | assign cache_way_sel_c3[12] = (cache_way_sel_c3_7[12] || cache_way_sel_c3_6[12] || cache_way_sel_c3_5[12] || cache_way_sel_c3_4[12] || cache_way_sel_c3_3[12] || cache_way_sel_c3_2[12] || cache_way_sel_c3_1[12] || cache_way_sel_c3_0[12]); | |
204 | ||
205 | assign cache_way_sel_c3[13] = (cache_way_sel_c3_7[13] || cache_way_sel_c3_6[13] || cache_way_sel_c3_5[13] || cache_way_sel_c3_4[13] || cache_way_sel_c3_3[13] || cache_way_sel_c3_2[13] || cache_way_sel_c3_1[13] || cache_way_sel_c3_0[13]); | |
206 | ||
207 | assign cache_way_sel_c3[14] = (cache_way_sel_c3_7[14] || cache_way_sel_c3_6[14] || cache_way_sel_c3_5[14] || cache_way_sel_c3_4[14] || cache_way_sel_c3_3[14] || cache_way_sel_c3_2[14] || cache_way_sel_c3_1[14] || cache_way_sel_c3_0[14]); | |
208 | ||
209 | assign cache_way_sel_c3[15] = (cache_way_sel_c3_7[15] || cache_way_sel_c3_6[15] || cache_way_sel_c3_5[15] || cache_way_sel_c3_4[15] || cache_way_sel_c3_3[15] || cache_way_sel_c3_2[15] || cache_way_sel_c3_1[15] || cache_way_sel_c3_0[15]); | |
210 | ||
211 | ||
212 | //assign cache_rd_wr_c3 | |
213 | assign cache_rd_wr_c3_0 = tb_top.cpu.l2d0.ctr.cache_rd_wr_c3; | |
214 | assign cache_rd_wr_c3_1 = tb_top.cpu.l2d1.ctr.cache_rd_wr_c3; | |
215 | assign cache_rd_wr_c3_2 = tb_top.cpu.l2d2.ctr.cache_rd_wr_c3; | |
216 | assign cache_rd_wr_c3_3 = tb_top.cpu.l2d3.ctr.cache_rd_wr_c3; | |
217 | assign cache_rd_wr_c3_4 = tb_top.cpu.l2d4.ctr.cache_rd_wr_c3; | |
218 | assign cache_rd_wr_c3_5 = tb_top.cpu.l2d5.ctr.cache_rd_wr_c3; | |
219 | assign cache_rd_wr_c3_6 = tb_top.cpu.l2d6.ctr.cache_rd_wr_c3; | |
220 | assign cache_rd_wr_c3_7 = tb_top.cpu.l2d7.ctr.cache_rd_wr_c3; | |
221 | ||
222 | assign cache_rd_wr_c3 = {cache_rd_wr_c3_7,cache_rd_wr_c3_6,cache_rd_wr_c3_5,cache_rd_wr_c3_4,cache_rd_wr_c3_3,cache_rd_wr_c3_2,cache_rd_wr_c3_1,cache_rd_wr_c3_0}; | |
223 | ||
224 | //inst_l2data_vld_c4 | |
225 | assign inst_l2data_vld_c4_0 = tb_top.cpu.l2t0.arb.inst_l2data_vld_c4; | |
226 | assign inst_l2data_vld_c4_1 = tb_top.cpu.l2t1.arb.inst_l2data_vld_c4; | |
227 | assign inst_l2data_vld_c4_2 = tb_top.cpu.l2t2.arb.inst_l2data_vld_c4; | |
228 | assign inst_l2data_vld_c4_3 = tb_top.cpu.l2t3.arb.inst_l2data_vld_c4; | |
229 | assign inst_l2data_vld_c4_4 = tb_top.cpu.l2t4.arb.inst_l2data_vld_c4; | |
230 | assign inst_l2data_vld_c4_5 = tb_top.cpu.l2t5.arb.inst_l2data_vld_c4; | |
231 | assign inst_l2data_vld_c4_6 = tb_top.cpu.l2t6.arb.inst_l2data_vld_c4; | |
232 | assign inst_l2data_vld_c4_7 = tb_top.cpu.l2t7.arb.inst_l2data_vld_c4; | |
233 | ||
234 | assign inst_l2data_vld_c4 = {inst_l2data_vld_c4_7,inst_l2data_vld_c4_6,inst_l2data_vld_c4_5,inst_l2data_vld_c4_4,inst_l2data_vld_c4_3,inst_l2data_vld_c4_2,inst_l2data_vld_c4_1,inst_l2data_vld_c4_0}; | |
235 | ||
236 | ||
237 | // cache_set_c3 | |
238 | assign cache_set_c3_0 = tb_top.cpu.l2d0.ctr.cache_set_c3; | |
239 | assign cache_set_c3_1 = tb_top.cpu.l2d1.ctr.cache_set_c3; | |
240 | assign cache_set_c3_2 = tb_top.cpu.l2d2.ctr.cache_set_c3; | |
241 | assign cache_set_c3_3 = tb_top.cpu.l2d3.ctr.cache_set_c3; | |
242 | assign cache_set_c3_4 = tb_top.cpu.l2d4.ctr.cache_set_c3; | |
243 | assign cache_set_c3_5 = tb_top.cpu.l2d5.ctr.cache_set_c3; | |
244 | assign cache_set_c3_6 = tb_top.cpu.l2d6.ctr.cache_set_c3; | |
245 | assign cache_set_c3_7 = tb_top.cpu.l2d7.ctr.cache_set_c3; | |
246 | ||
247 | ||
248 | assign cache_set_c3 = {cache_set_c3_7,cache_set_c3_6,cache_set_c3_5,cache_set_c3_4,cache_set_c3_3,cache_set_c3_2,cache_set_c3_1,cache_set_c3_0}; | |
249 | ||
250 | //cache_col_offset_c3 | |
251 | assign cache_col_offset_c3_0 = tb_top.cpu.l2d0.ctr.cache_col_offset_c3; | |
252 | assign cache_col_offset_c3_1 = tb_top.cpu.l2d1.ctr.cache_col_offset_c3; | |
253 | assign cache_col_offset_c3_2 = tb_top.cpu.l2d2.ctr.cache_col_offset_c3; | |
254 | assign cache_col_offset_c3_3 = tb_top.cpu.l2d3.ctr.cache_col_offset_c3; | |
255 | assign cache_col_offset_c3_4 = tb_top.cpu.l2d4.ctr.cache_col_offset_c3; | |
256 | assign cache_col_offset_c3_5 = tb_top.cpu.l2d5.ctr.cache_col_offset_c3; | |
257 | assign cache_col_offset_c3_6 = tb_top.cpu.l2d6.ctr.cache_col_offset_c3; | |
258 | assign cache_col_offset_c3_7 = tb_top.cpu.l2d7.ctr.cache_col_offset_c3; | |
259 | ||
260 | assign cache_col_offset_c3 = {cache_col_offset_c3_7,cache_col_offset_c3_6,cache_col_offset_c3_5,cache_col_offset_c3_4,cache_col_offset_c3_3,cache_col_offset_c3_2,cache_col_offset_c3_1,cache_col_offset_c3_0}; | |
261 | ||
262 | //cache_decc_out_c52 | |
263 | // changed from c5b to c52 AK 09/20 | |
264 | assign cache_decc_out_c52_0 = tb_top.cpu.l2d0.ctr.cache_decc_out_c52; | |
265 | assign cache_decc_out_c52_1 = tb_top.cpu.l2d1.ctr.cache_decc_out_c52; | |
266 | assign cache_decc_out_c52_2 = tb_top.cpu.l2d2.ctr.cache_decc_out_c52; | |
267 | assign cache_decc_out_c52_3 = tb_top.cpu.l2d3.ctr.cache_decc_out_c52; | |
268 | assign cache_decc_out_c52_4 = tb_top.cpu.l2d4.ctr.cache_decc_out_c52; | |
269 | assign cache_decc_out_c52_5 = tb_top.cpu.l2d5.ctr.cache_decc_out_c52; | |
270 | assign cache_decc_out_c52_6 = tb_top.cpu.l2d6.ctr.cache_decc_out_c52; | |
271 | assign cache_decc_out_c52_7 = tb_top.cpu.l2d7.ctr.cache_decc_out_c52; | |
272 | ||
273 | assign cache_decc_out_c52 = {cache_decc_out_c52_7,cache_decc_out_c52_6,cache_decc_out_c52_5,cache_decc_out_c52_4,cache_decc_out_c52_3,cache_decc_out_c52_2,cache_decc_out_c52_1,cache_decc_out_c52_0}; | |
274 | ||
275 | ||
276 | initial | |
277 | begin | |
278 | ||
279 | ||
280 | //================================= | |
281 | // Initialize the forcing variables | |
282 | //================================= | |
283 | ||
284 | stuck_to0 = 1'b0; | |
285 | stuck_to1 = 1'b0; | |
286 | rand_bit_flip = 1'b0; | |
287 | err_enable = 1'b0; | |
288 | inject_limit = 0; | |
289 | rand_limit_hi = 150; | |
290 | err_addr <= 0; | |
291 | ||
292 | ||
293 | Tevent = 1'b0; | |
294 | trph = 1'b0; | |
295 | trpH = 1'b0; | |
296 | ns=0; | |
297 | ns1=0; | |
298 | ||
299 | //================================= | |
300 | // Initialize the variables used in here | |
301 | //================================= | |
302 | rand1 = 0; | |
303 | rand2 = 0; | |
304 | injectErr = 0; | |
305 | start_injection = 0; | |
306 | stuck_to1= 0; | |
307 | rand_bit_flip = 0; | |
308 | err_enable = 0; | |
309 | err_enable_fwd = 0; | |
310 | bit_err_enable = 0; | |
311 | bit_err_enable_c5b = 0; | |
312 | bit_pos = 0; | |
313 | ||
314 | ||
315 | //========================================= | |
316 | // Check if forcing variables are changed by verargs | |
317 | //========================================= | |
318 | ||
319 | if($test$plusargs("L2DA_BIT_STUCK_TO0")) | |
320 | begin | |
321 | stuck_to0= 1; | |
322 | `PR_ALWAYS("l2err_injector", `ALWAYS, "L2 bit stuck to 0"); | |
323 | end | |
324 | else if ($test$plusargs("L2DA_BIT_STUCK_TO1")) | |
325 | begin | |
326 | stuck_to1= 1; | |
327 | `PR_ALWAYS("l2err_injector", `ALWAYS, "L2 bit stuck to 1"); | |
328 | end | |
329 | if ($test$plusargs("L2DA_ERR_ENABLE_FWD")) | |
330 | begin | |
331 | // err_enable_fwd = 1; | |
332 | bit_err_enable = 1; | |
333 | `PR_ALWAYS("l2err_injector", `ALWAYS, "L2 DATA ARRAY Err INJECTION ENABLED"); | |
334 | end | |
335 | if ($test$plusargs("L2DA_INT_ERR_ENABLE")) | |
336 | begin | |
337 | bit_err_enable_c5b = 1; | |
338 | `PR_ALWAYS("l2err_injector", `ALWAYS, "L2 DATA ARRAY Err INJECTION ENABLED"); | |
339 | end | |
340 | if ($test$plusargs("L2DA_ERR_ENABLE")) | |
341 | begin | |
342 | // err_enable_fwd = 1; | |
343 | `PR_ALWAYS("l2err_injector", `ALWAYS, "L2 DATA ARRAY Err INJECTION ENABLED"); | |
344 | bit_err_enable = 1; | |
345 | err_enable = 1; | |
346 | end | |
347 | if ($test$plusargs("L2DA_RAND_ERR_ENABLE")) | |
348 | begin | |
349 | rand_bit_flip = 1; | |
350 | bit_err_enable = 1; | |
351 | ||
352 | `PR_ALWAYS("l2err_injector", `ALWAYS, "L2 DATA ARRAY RANDOM Err INJECTION ENABLED"); | |
353 | end | |
354 | ||
355 | end | |
356 | ||
357 | ||
358 | ||
359 | always @(TRAP_EVENT) | |
360 | begin | |
361 | if( TRAP_EVENT == 9'h1a0 || TRAP_EVENT == 9'h100 || TRAP_EVENT == 9'h101 || TRAP_EVENT == 9'h1a1 || TRAP_EVENT == 8'h09 || TRAP_EVENT == 8'h31 || TRAP_EVENT == 9'h18a || TRAP_EVENT == 9'h12a) | |
362 | Tevent = 1'b1; | |
363 | else Tevent = 1'b0; | |
364 | //$display("TRAP_EVENT=%x,Tevent= %x",TRAP_EVENT,Tevent); | |
365 | end | |
366 | ||
367 | /*** | |
368 | // review LATER --> while(errorInject && !checkNotData) | |
369 | ||
370 | ||
371 | always @(posedge tb_top.cpu.l2clk) | |
372 | begin | |
373 | ||
374 | if(!L2_INT_RST) | |
375 | begin | |
376 | ||
377 | j <= 0; | |
378 | way <= 0; | |
379 | way_int <= 0; | |
380 | cache_col_offset <= 0; | |
381 | cache_col_offset_int <= 0; | |
382 | k <= 0; | |
383 | dataecc <= 0; | |
384 | int <= 0; | |
385 | i <= 0; | |
386 | bit_pos <= 0; | |
387 | err_addr <= 0; | |
388 | err_cntr <= 0; | |
389 | ||
390 | end | |
391 | else | |
392 | begin | |
393 | if (( `TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0] ) && bit_err_enable_c5b) | |
394 | begin | |
395 | //$display("In INT Logic"); | |
396 | err_addr <= err_addr_0; | |
397 | @(posedge tb_top.cpu.l2clk); | |
398 | ||
399 | j <= cache_set_c3; | |
400 | way <= Decode(cache_way_sel_c3); | |
401 | cache_col_offset <= Decode1(cache_col_offset_c3); | |
402 | ||
403 | //$display("cache_way_sel_c3_0 = %x,cache_rd_wr_c3 = %x,inst_l2data_vld_c4 = %x,Tevent = %x,trph = %x,trpH = %x",cache_way_sel_c3_0,cache_rd_wr_c3,inst_l2data_vld_c4,Tevent,trph,trpH); | |
404 | ||
405 | #(SAMPLE) if(cache_way_sel_c3_0 != 0 && cache_rd_wr_c3 == 255 && !inst_l2data_vld_c4 && Tevent == 0 && !trph && !trpH && bit_pos[3] != 1) | |
406 | begin | |
407 | //$display("In cache_sel_c3"); | |
408 | //C3 | |
409 | @(posedge tb_top.cpu.l2clk);//C4 | |
410 | @(posedge tb_top.cpu.l2clk);//C5 | |
411 | ||
412 | #(SAMPLE) k <= cache_col_offset; | |
413 | // initially was not injecting on negedge but pos edge..simukate and check this. | |
414 | @(negedge tb_top.cpu.l2clk); //Workaround as c5b is valid only for half clk cycle | |
415 | #(SAMPLE) i=0; | |
416 | ||
417 | if (bit_err_enable_c5b) | |
418 | begin | |
419 | SetCacheDeccOutC52(i, ( cache_decc_out_c52_0 ^ (624'b1 << k))); | |
420 | `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected into bank%0d, index%0d, way%0d, bit%0d",i, j, way, k); | |
421 | `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected at PA: %0h",err_addr); | |
422 | err_cntr <= err_cntr + 1; | |
423 | end | |
424 | ||
425 | @(negedge tb_top.cpu.l2clk); | |
426 | #(SAMPLE) ReleaseCacheDeccOutC52(i); | |
427 | end //if(cache_way_sel_c3_0 != 0 .... | |
428 | bit_pos = bit_pos +1; | |
429 | end //if of OutOfBootCode | |
430 | end // else of If(!Rst) | |
431 | ||
432 | end //always | |
433 | ||
434 | **/ | |
435 | //Sequential part of stmc... | |
436 | //To not inject in traphandler | |
437 | always @(posedge tb_top.cpu.l2clk) | |
438 | begin | |
439 | if(bit_err_enable || bit_err_enable_c5b) | |
440 | begin | |
441 | if(!L2_INT_RST) cs <= s0; | |
442 | else cs <= ns; | |
443 | end | |
444 | end | |
445 | //combo logic | |
446 | always @(s0 or s1 or take_ade or take_retry or cs or bit_err_enable or bit_err_enable_c5b) | |
447 | begin | |
448 | if(bit_err_enable || bit_err_enable_c5b) | |
449 | begin | |
450 | ||
451 | trph <= 0; | |
452 | case(cs) | |
453 | s0: | |
454 | begin | |
455 | if ( take_ade == 0) ns <= s0; | |
456 | else if (take_ade == 1) begin ns <= s1; trph<= 1;end | |
457 | end | |
458 | s1: | |
459 | begin | |
460 | if (take_retry == 0)begin ns <= s1; trph <= 1; end | |
461 | else if (take_retry == 1) begin ns <= s0;trph<=0;end | |
462 | end | |
463 | endcase | |
464 | //$display("In Combo Logic take_retry=%d,take_ade=%d,trph=%d,ns=%d",take_retry,take_ade,trph,ns); | |
465 | end | |
466 | end //end combo logic | |
467 | ||
468 | always @(posedge tb_top.cpu.l2clk) | |
469 | begin | |
470 | if(bit_err_enable || bit_err_enable_c5b) | |
471 | begin | |
472 | if(!L2_INT_RST) cs1 <= S0; | |
473 | else cs1 <= ns1; | |
474 | end | |
475 | end | |
476 | //combo logic | |
477 | always @(S0 or S1 or take_eer or take_retry or cs1) | |
478 | begin | |
479 | trpH <= 0; | |
480 | case(cs1) | |
481 | S0: | |
482 | begin | |
483 | if ( take_eer == 0) ns1 <= S0; | |
484 | else if (take_eer == 1) begin ns1 <= S1; trpH<= 1;end | |
485 | end | |
486 | S1: | |
487 | begin | |
488 | if (take_retry == 0)begin ns1 <= S1; trpH <= 1; end | |
489 | else if (take_retry == 1) begin ns1 <= S0;trpH<=0;end | |
490 | end | |
491 | endcase | |
492 | //$display("In Combo Logic take_retry=%d,take_ade=%d,trph=%d,ns=%d",take_retry,take_ade,trph,ns); | |
493 | end //end combo logic | |
494 | ||
495 | always @(posedge tb_top.cpu.l2clk) | |
496 | begin | |
497 | ||
498 | if(!L2_INT_RST) | |
499 | begin | |
500 | err_cntr <= 0; | |
501 | end | |
502 | else | |
503 | begin | |
504 | if (( `TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0] ) && (stuck_to0 || stuck_to1 || bit_err_enable || bit_err_enable_c5b)) | |
505 | begin | |
506 | //$display("In FWD Logic"); | |
507 | //$display("Out Of Boot TOP.gOutOfBoot = %d",`TOP.gOutOfBoot[63:0]); | |
508 | err_addr <= err_addr_0; | |
509 | j <= cache_set_c3; | |
510 | way <= Decode(cache_way_sel_c3); | |
511 | cache_col_offset <= Decode1(cache_col_offset_c3); | |
512 | //$display("cache_way_sel_c3_0 = %x,cache_rd_wr_c3=%x,inst_l2data_vld_c4=%d,Tevent=%x,trph=%d",cache_way_sel_c3_0,cache_rd_wr_c3,inst_l2data_vld_c4,Tevent,trph); | |
513 | #(SAMPLE) if(cache_way_sel_c3_0 != 0 && cache_rd_wr_c3 == 255 && !inst_l2data_vld_c4 && Tevent == 0 && !trph && !trpH) //C3 | |
514 | begin | |
515 | @(posedge tb_top.cpu.l2clk); // C4 | |
516 | @(posedge tb_top.cpu.l2clk); //C5 | |
517 | // @(negedge tb_top.cpu.l2clk); | |
518 | #(SAMPLE) i=0; | |
519 | // if(stuck_to0 == 0 && stuck_to1 == 0 && rand_bit_flip ==0 && err_enable ==0 && err_enable_fwd ==0 && bit_err_enable ==1) | |
520 | // begin | |
521 | #(SAMPLE) | |
522 | // k <= 298; | |
523 | // SetCacheDeccOutC52(i, ( cache_decc_out_c52_0 ^ (300'b1 << k))); | |
524 | // `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected into bank%0d, index%0d, way%0d, bit%0d",i, j, way, k); | |
525 | // @(negedge tb_top.cpu.l2clk);//negedge of C5 | |
526 | // #(SAMPLE) ReleaseCacheDeccOutC52(i); | |
527 | // end | |
528 | ||
529 | @(posedge tb_top.cpu.l2clk);// C52 //Inject in the data array itself | |
530 | if(stuck_to0 == 0 && stuck_to1 == 0 && bit_err_enable == 0 && bit_pos[3] != 1 && bit_err_enable_c5b == 1) | |
531 | begin | |
532 | k = cache_col_offset; | |
533 | @(negedge tb_top.cpu.l2clk); | |
534 | SetCacheDeccOutC52(i, ( cache_decc_out_c52_0 ^ (624'b1 << k))); | |
535 | `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected in bank%0d, index%0d, way%0d, bit%0d",i, j, way, k); | |
536 | `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected at PA: %0h",err_addr); | |
537 | err_cntr <= err_cntr + 1; | |
538 | @(negedge tb_top.cpu.l2clk); | |
539 | #(SAMPLE) ReleaseCacheDeccOutC52(i); | |
540 | ||
541 | ||
542 | end | |
543 | @(posedge tb_top.cpu.l2clk); //C6 One clk cycle reduced 10/13/2005 | |
544 | //Inject in C6 stage of Pipeline and not in data array | |
545 | ||
546 | @(negedge tb_top.cpu.l2clk);// negedge of C6 | |
547 | #(SAMPLE) i=0; | |
548 | //$display("In bit_pos=%d",bit_pos); | |
549 | ||
550 | if(stuck_to0 == 0 && stuck_to1 == 0 && bit_err_enable ==1 && bit_pos[3] != 1 && bit_err_enable_c5b == 0) | |
551 | // if(stuck_to0 == 0 && stuck_to1 == 0 && bit_err_enable ==1 && bit_err_enable_c5b == 0) | |
552 | begin | |
553 | // if(({$random(`PARGS.seed)} % 16) == 0) | |
554 | // begin | |
555 | /** | |
556 | if (rand_bit_flip == 1) k <= ({$random(`PARGS.seed)} % 154); | |
557 | else k<= 144; **/ | |
558 | k <= ({$random(`PARGS.seed)} % 154); | |
559 | #(SAMPLE) | |
560 | Setl2d_l2t_decc_c6(i, ( l2d_l2t_decc_c6_0 ^ (156'b1 << k))); | |
561 | `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected in pipeline in bank%0d, index%0d, way%0d, bit%0d",i, j, way, k); | |
562 | `PR_ALWAYS("l2err_injector", `ALWAYS,"Data array error injected at PA %0h",err_addr); | |
563 | ||
564 | err_cntr <= err_cntr + 1; | |
565 | // end // end of if({$random(`PARGS.seed)} % 16) | |
566 | end // end of if (stuck_to0..... | |
567 | else err_cntr <= err_cntr; | |
568 | //$display("err_cntr=%d",err_cntr); | |
569 | ||
570 | ||
571 | @(negedge tb_top.cpu.l2clk); | |
572 | #(SAMPLE) Releasel2d_l2t_decc_c6(i); | |
573 | end //if(cache_way_sel_c3_0 != 0 .... | |
574 | bit_pos <= bit_pos + 1; | |
575 | ||
576 | end // if od OutOfBootCode | |
577 | end // else of If(!Rst) | |
578 | ||
579 | end //always | |
580 | ||
581 | ||
582 | ||
583 | ||
584 | /////////////////////////////////////////////////////////////////////// | |
585 | //This function returns the bit position of the least significant high bit in the bit vector. | |
586 | /////////////////////////////////////////////////////////////////////// | |
587 | ||
588 | //*function bit [3:0] Decode(bit [15:0] cache_way_sel_c3) */ | |
589 | ||
590 | function Decode; | |
591 | input [15:0] cache_way_sel_c3; | |
592 | begin | |
593 | if(cache_way_sel_c3[15] == 1) | |
594 | Decode = 15; | |
595 | else if(cache_way_sel_c3[14] == 1) | |
596 | Decode = 14; | |
597 | else if(cache_way_sel_c3[13] == 1) | |
598 | Decode = 13; | |
599 | else if(cache_way_sel_c3[12] == 1) | |
600 | Decode = 12; | |
601 | else if(cache_way_sel_c3[11] == 1) | |
602 | Decode = 11; | |
603 | else if(cache_way_sel_c3[10] == 1) | |
604 | Decode = 10; | |
605 | else if(cache_way_sel_c3[9] == 1) | |
606 | Decode = 9; | |
607 | else if(cache_way_sel_c3[8] == 1) | |
608 | Decode = 8; | |
609 | else if(cache_way_sel_c3[7] == 1) | |
610 | Decode = 7; | |
611 | else if(cache_way_sel_c3[6] == 1) | |
612 | Decode = 6; | |
613 | else if(cache_way_sel_c3[5] == 1) | |
614 | Decode = 5; | |
615 | else if(cache_way_sel_c3[4] == 1) | |
616 | Decode = 4; | |
617 | else if(cache_way_sel_c3[3] == 1) | |
618 | Decode = 3; | |
619 | else if(cache_way_sel_c3[2] == 1) | |
620 | Decode = 2; | |
621 | else if(cache_way_sel_c3[1] == 1) | |
622 | Decode = 1; | |
623 | else | |
624 | Decode = 0; | |
625 | ||
626 | ||
627 | ||
628 | end | |
629 | endfunction | |
630 | ||
631 | function Decode1; | |
632 | input [3:0] cache_col_offset_c3; | |
633 | begin | |
634 | ||
635 | if(cache_col_offset_c3[3]) | |
636 | Decode1 = 3; | |
637 | else if(cache_col_offset_c3[2]) | |
638 | Decode1 = 2; | |
639 | else if(cache_col_offset_c3[1]) | |
640 | Decode1 = 1; | |
641 | else | |
642 | Decode1 = 0; | |
643 | ||
644 | end | |
645 | endfunction | |
646 | ||
647 | ||
648 | // Task for error forward | |
649 | // Removed ctr on 10/13/2005 0: force tb_top.cpu.l2d0.ctr.l2d_l2t_decc_c6 = value; | |
650 | task Setl2d_l2t_decc_c6; | |
651 | input bank; | |
652 | input [155:0] value; | |
653 | integer bank; | |
654 | reg [155:0] value; | |
655 | begin | |
656 | case (bank) | |
657 | 0: force tb_top.cpu.l2d0.l2d_l2t_decc_c6 = value; | |
658 | 1: force tb_top.cpu.l2d1.l2d_l2t_decc_c6 = value; | |
659 | 2: force tb_top.cpu.l2d2.l2d_l2t_decc_c6 = value; | |
660 | 3: force tb_top.cpu.l2d3.l2d_l2t_decc_c6 = value; | |
661 | 4: force tb_top.cpu.l2d4.l2d_l2t_decc_c6 = value; | |
662 | 5: force tb_top.cpu.l2d5.l2d_l2t_decc_c6 = value; | |
663 | 6: force tb_top.cpu.l2d6.l2d_l2t_decc_c6 = value; | |
664 | 7: force tb_top.cpu.l2d7.l2d_l2t_decc_c6 = value; | |
665 | endcase | |
666 | end | |
667 | endtask | |
668 | ||
669 | task Releasel2d_l2t_decc_c6; | |
670 | input bank; | |
671 | integer bank; | |
672 | begin | |
673 | case (bank) | |
674 | 0: release tb_top.cpu.l2d0.l2d_l2t_decc_c6; | |
675 | 1: release tb_top.cpu.l2d1.l2d_l2t_decc_c6; | |
676 | 2: release tb_top.cpu.l2d2.l2d_l2t_decc_c6; | |
677 | 3: release tb_top.cpu.l2d3.l2d_l2t_decc_c6; | |
678 | 4: release tb_top.cpu.l2d4.l2d_l2t_decc_c6; | |
679 | 5: release tb_top.cpu.l2d5.l2d_l2t_decc_c6; | |
680 | 6: release tb_top.cpu.l2d6.l2d_l2t_decc_c6; | |
681 | 7: release tb_top.cpu.l2d7.l2d_l2t_decc_c6; | |
682 | endcase | |
683 | end | |
684 | endtask | |
685 | ||
686 | ||
687 | ||
688 | ||
689 | /**** | |
690 | Task for error forward | |
691 | task Setl2d_l2t_decc_c6; | |
692 | input bank; | |
693 | input [623:0] value; | |
694 | integer bank; | |
695 | reg [623:0] value; | |
696 | begin | |
697 | case (bank) | |
698 | 0: force tb_top.cpu.l2d0.ctr.l2d_decc_out_c6 = value; | |
699 | 1: force tb_top.cpu.l2d1.ctr.l2d_decc_out_c6 = value; | |
700 | 2: force tb_top.cpu.l2d2.ctr.l2d_decc_out_c6 = value; | |
701 | 3: force tb_top.cpu.l2d3.ctr.l2d_decc_out_c6 = value; | |
702 | 4: force tb_top.cpu.l2d4.ctr.l2d_decc_out_c6 = value; | |
703 | 5: force tb_top.cpu.l2d5.ctr.l2d_decc_out_c6 = value; | |
704 | 6: force tb_top.cpu.l2d6.ctr.l2d_decc_out_c6 = value; | |
705 | 7: force tb_top.cpu.l2d7.ctr.l2d_decc_out_c6 = value; | |
706 | endcase | |
707 | end | |
708 | endtask | |
709 | ||
710 | task Releasel2d_l2t_decc_c6; | |
711 | input bank; | |
712 | integer bank; | |
713 | begin | |
714 | case (bank) | |
715 | 0: release tb_top.cpu.l2d0.ctr.l2d_decc_out_c6; | |
716 | 1: release tb_top.cpu.l2d1.ctr.l2d_decc_out_c6; | |
717 | 2: release tb_top.cpu.l2d2.ctr.l2d_decc_out_c6; | |
718 | 3: release tb_top.cpu.l2d3.ctr.l2d_decc_out_c6; | |
719 | 4: release tb_top.cpu.l2d4.ctr.l2d_decc_out_c6; | |
720 | 5: release tb_top.cpu.l2d5.ctr.l2d_decc_out_c6; | |
721 | 6: release tb_top.cpu.l2d6.ctr.l2d_decc_out_c6; | |
722 | 7: release tb_top.cpu.l2d7.ctr.l2d_decc_out_c6; | |
723 | endcase | |
724 | end | |
725 | endtask | |
726 | ***/ | |
727 | ||
728 | ||
729 | /*** Old task | |
730 | task SetCacheDeccOutC52; | |
731 | input bank; | |
732 | input [623:0] value; | |
733 | integer bank; | |
734 | reg [623:0] value; | |
735 | begin | |
736 | case (bank) | |
737 | 0: force tb_top.cpu.l2d0.ctr.cache_decc_out_c5b = value; | |
738 | 1: force tb_top.cpu.l2d1.ctr.cache_decc_out_c5b = value; | |
739 | 2: force tb_top.cpu.l2d2.ctr.cache_decc_out_c5b = value; | |
740 | 3: force tb_top.cpu.l2d3.ctr.cache_decc_out_c5b = value; | |
741 | 4: force tb_top.cpu.l2d4.ctr.cache_decc_out_c5b = value; | |
742 | 5: force tb_top.cpu.l2d5.ctr.cache_decc_out_c5b = value; | |
743 | 6: force tb_top.cpu.l2d6.ctr.cache_decc_out_c5b = value; | |
744 | 7: force tb_top.cpu.l2d7.ctr.cache_decc_out_c5b = value; | |
745 | endcase | |
746 | end | |
747 | endtask | |
748 | ||
749 | task ReleaseCacheDeccOutC52; | |
750 | input bank; | |
751 | integer bank; | |
752 | begin | |
753 | case (bank) | |
754 | 0: release tb_top.cpu.l2d0.ctr.cache_decc_out_c5b; | |
755 | 1: release tb_top.cpu.l2d1.ctr.cache_decc_out_c5b; | |
756 | 2: release tb_top.cpu.l2d2.ctr.cache_decc_out_c5b; | |
757 | 3: release tb_top.cpu.l2d3.ctr.cache_decc_out_c5b; | |
758 | 4: release tb_top.cpu.l2d4.ctr.cache_decc_out_c5b; | |
759 | 5: release tb_top.cpu.l2d5.ctr.cache_decc_out_c5b; | |
760 | 6: release tb_top.cpu.l2d6.ctr.cache_decc_out_c5b; | |
761 | 7: release tb_top.cpu.l2d7.ctr.cache_decc_out_c5b; | |
762 | endcase | |
763 | end | |
764 | endtask ****/ | |
765 | ||
766 | ||
767 | // New Task | |
768 | ||
769 | task SetCacheDeccOutC52; | |
770 | input bank; | |
771 | input [623:0] value; | |
772 | integer bank; | |
773 | reg [623:0] value; | |
774 | begin | |
775 | //$display("In Task SetCacheDeccOutC52"); | |
776 | case (bank) | |
777 | 0:begin | |
778 | force tb_top.cpu.l2d0.ctr.cache_decc_out_0_c52 = value[155:0]; | |
779 | force tb_top.cpu.l2d0.ctr.cache_decc_out_1_c52 = value[311:156]; | |
780 | force tb_top.cpu.l2d0.ctr.cache_decc_out_2_c52 = value[467:312]; | |
781 | force tb_top.cpu.l2d0.ctr.cache_decc_out_3_c52 = value[623:468]; | |
782 | end | |
783 | 1:begin | |
784 | force tb_top.cpu.l2d1.ctr.cache_decc_out_0_c52 = value[155:0]; | |
785 | force tb_top.cpu.l2d1.ctr.cache_decc_out_1_c52 = value[311:156]; | |
786 | force tb_top.cpu.l2d1.ctr.cache_decc_out_2_c52 = value[467:312]; | |
787 | force tb_top.cpu.l2d1.ctr.cache_decc_out_3_c52 = value[623:468]; | |
788 | end | |
789 | 2:begin | |
790 | force tb_top.cpu.l2d2.ctr.cache_decc_out_0_c52 = value[155:0]; | |
791 | force tb_top.cpu.l2d2.ctr.cache_decc_out_1_c52 = value[311:156]; | |
792 | force tb_top.cpu.l2d2.ctr.cache_decc_out_2_c52 = value[467:312]; | |
793 | force tb_top.cpu.l2d2.ctr.cache_decc_out_3_c52 = value[623:468]; | |
794 | end | |
795 | 3:begin | |
796 | force tb_top.cpu.l2d3.ctr.cache_decc_out_0_c52 = value[155:0]; | |
797 | force tb_top.cpu.l2d3.ctr.cache_decc_out_1_c52 = value[311:156]; | |
798 | force tb_top.cpu.l2d3.ctr.cache_decc_out_2_c52 = value[467:312]; | |
799 | force tb_top.cpu.l2d3.ctr.cache_decc_out_3_c52 = value[623:468]; | |
800 | end | |
801 | 4:begin | |
802 | force tb_top.cpu.l2d4.ctr.cache_decc_out_0_c52 = value[155:0]; | |
803 | force tb_top.cpu.l2d4.ctr.cache_decc_out_1_c52 = value[311:156]; | |
804 | force tb_top.cpu.l2d4.ctr.cache_decc_out_2_c52 = value[467:312]; | |
805 | force tb_top.cpu.l2d4.ctr.cache_decc_out_3_c52 = value[623:468]; | |
806 | end | |
807 | 5:begin | |
808 | force tb_top.cpu.l2d5.ctr.cache_decc_out_0_c52 = value[155:0]; | |
809 | force tb_top.cpu.l2d5.ctr.cache_decc_out_1_c52 = value[311:156]; | |
810 | force tb_top.cpu.l2d5.ctr.cache_decc_out_2_c52 = value[467:312]; | |
811 | force tb_top.cpu.l2d5.ctr.cache_decc_out_3_c52 = value[623:468]; | |
812 | end | |
813 | 6:begin | |
814 | force tb_top.cpu.l2d6.ctr.cache_decc_out_0_c52 = value[155:0]; | |
815 | force tb_top.cpu.l2d6.ctr.cache_decc_out_1_c52 = value[311:156]; | |
816 | force tb_top.cpu.l2d6.ctr.cache_decc_out_2_c52 = value[467:312]; | |
817 | force tb_top.cpu.l2d6.ctr.cache_decc_out_3_c52 = value[623:468]; | |
818 | end | |
819 | 7:begin | |
820 | force tb_top.cpu.l2d7.ctr.cache_decc_out_0_c52 = value[155:0]; | |
821 | force tb_top.cpu.l2d7.ctr.cache_decc_out_1_c52 = value[311:156]; | |
822 | force tb_top.cpu.l2d7.ctr.cache_decc_out_2_c52 = value[467:312]; | |
823 | force tb_top.cpu.l2d7.ctr.cache_decc_out_3_c52 = value[623:468]; | |
824 | end | |
825 | endcase | |
826 | end | |
827 | endtask | |
828 | ||
829 | task ReleaseCacheDeccOutC52; | |
830 | input bank; | |
831 | integer bank; | |
832 | begin | |
833 | case (bank) | |
834 | 0:begin | |
835 | release tb_top.cpu.l2d0.ctr.cache_decc_out_0_c52; | |
836 | release tb_top.cpu.l2d0.ctr.cache_decc_out_1_c52; | |
837 | release tb_top.cpu.l2d0.ctr.cache_decc_out_2_c52; | |
838 | release tb_top.cpu.l2d0.ctr.cache_decc_out_3_c52; | |
839 | end | |
840 | 1: begin | |
841 | release tb_top.cpu.l2d1.ctr.cache_decc_out_0_c52; | |
842 | release tb_top.cpu.l2d1.ctr.cache_decc_out_1_c52; | |
843 | release tb_top.cpu.l2d1.ctr.cache_decc_out_2_c52; | |
844 | release tb_top.cpu.l2d1.ctr.cache_decc_out_3_c52; | |
845 | end | |
846 | 2: begin | |
847 | release tb_top.cpu.l2d2.ctr.cache_decc_out_0_c52; | |
848 | release tb_top.cpu.l2d2.ctr.cache_decc_out_1_c52; | |
849 | release tb_top.cpu.l2d2.ctr.cache_decc_out_2_c52; | |
850 | release tb_top.cpu.l2d2.ctr.cache_decc_out_3_c52; | |
851 | end | |
852 | 3:begin | |
853 | release tb_top.cpu.l2d3.ctr.cache_decc_out_0_c52; | |
854 | release tb_top.cpu.l2d3.ctr.cache_decc_out_1_c52; | |
855 | release tb_top.cpu.l2d3.ctr.cache_decc_out_2_c52; | |
856 | release tb_top.cpu.l2d3.ctr.cache_decc_out_3_c52; | |
857 | end | |
858 | 4: begin | |
859 | release tb_top.cpu.l2d4.ctr.cache_decc_out_0_c52; | |
860 | release tb_top.cpu.l2d4.ctr.cache_decc_out_1_c52; | |
861 | release tb_top.cpu.l2d4.ctr.cache_decc_out_2_c52; | |
862 | release tb_top.cpu.l2d4.ctr.cache_decc_out_3_c52; | |
863 | end | |
864 | 5:begin | |
865 | release tb_top.cpu.l2d5.ctr.cache_decc_out_0_c52; | |
866 | release tb_top.cpu.l2d5.ctr.cache_decc_out_1_c52; | |
867 | release tb_top.cpu.l2d5.ctr.cache_decc_out_2_c52; | |
868 | release tb_top.cpu.l2d5.ctr.cache_decc_out_3_c52; | |
869 | end | |
870 | 6:begin | |
871 | release tb_top.cpu.l2d6.ctr.cache_decc_out_0_c52; | |
872 | release tb_top.cpu.l2d6.ctr.cache_decc_out_1_c52; | |
873 | release tb_top.cpu.l2d6.ctr.cache_decc_out_2_c52; | |
874 | release tb_top.cpu.l2d6.ctr.cache_decc_out_3_c52; | |
875 | end | |
876 | 7:begin | |
877 | release tb_top.cpu.l2d7.ctr.cache_decc_out_0_c52; | |
878 | release tb_top.cpu.l2d7.ctr.cache_decc_out_1_c52; | |
879 | release tb_top.cpu.l2d7.ctr.cache_decc_out_2_c52; | |
880 | release tb_top.cpu.l2d7.ctr.cache_decc_out_3_c52; | |
881 | end | |
882 | endcase | |
883 | end | |
884 | endtask | |
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | endmodule | |
891 | ||
892 |