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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2err_checker.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2err_checker(L2_INT_RST,cpx_pkt_cnt,desr_log_cnt); | |
36 | ||
37 | input L2_INT_RST; | |
38 | output [23:0] cpx_pkt_cnt,desr_log_cnt; | |
39 | ||
40 | ||
41 | parameter S0=0,S1=1,S2=2,S3=3,SAMPLE=3; | |
42 | ||
43 | wire [63:0] err_detected; | |
44 | wire cpx_packet_valid,cpx_packet_l2miss; | |
45 | wire [3:0] cpx_packet_rtntyp; | |
46 | wire [1:0] cpx_packet_err; | |
47 | wire [7:0] cpx_grnt; | |
48 | wire [4:0] ras_desr_errtyp; | |
49 | wire ras_desr_S,desr_F,desr_S,desr_ME; | |
50 | ||
51 | reg [1:0] currentstate,currentstate1,currentstate2; | |
52 | reg [1:0] nextstate,nextstate1,nextstate2; | |
53 | reg st_inst,L2_err_flag,ld_pkt,err_pkt,pck_grnt_flag_ld,stmc_busy,pck_grnt_flag_err,desr_correct,errInj_enabled; | |
54 | reg [23:0] cpx_pkt_cnt,desr_log_cnt; | |
55 | ||
56 | ||
57 | assign err_detected = tb_top.cpu.l2t0.csreg.err_state_new_c8; | |
58 | ||
59 | assign cpx_packet_valid = tb_top.cpu.l2t0.l2t_cpx_data_ca[145]; | |
60 | assign cpx_packet_l2miss = tb_top.cpu.l2t0.l2t_cpx_data_ca[140]; | |
61 | assign cpx_packet_rtntyp= tb_top.cpu.l2t0.l2t_cpx_data_ca[144:141]; | |
62 | assign cpx_packet_err= tb_top.cpu.l2t0.l2t_cpx_data_ca[139:138]; | |
63 | assign cpx_grnt = tb_top.cpu.l2t0.cpx_l2t_grant_cx; | |
64 | assign desr_F = tb_top.cpu.spc0.tlu.dfd.desr_0[63]; | |
65 | assign desr_S = tb_top.cpu.spc0.tlu.dfd.desr_0[61]; | |
66 | assign desr_ME = tb_top.cpu.spc0.tlu.dfd.desr_0[62]; | |
67 | assign ras_desr_S = tb_top.cpu.spc0.tlu.dfd.ras_desr_et_0[61]; | |
68 | assign ras_desr_errtyp = tb_top.cpu.spc0.tlu.dfd.ras_desr_et_0[60:56]; | |
69 | ||
70 | ||
71 | //-------------------------------------------------------------------------------------- | |
72 | // Enable/Disable support : MAQ | |
73 | //-------------------------------------------------------------------------------------- | |
74 | ||
75 | wire flush_reset_complete = `TOP.flush_reset_complete; | |
76 | ||
77 | reg enabled; | |
78 | initial | |
79 | begin | |
80 | cpx_pkt_cnt = 0; | |
81 | desr_log_cnt = 0; | |
82 | /** | |
83 | if (!($test$plusargs("l2err_checker_disable")) && (($test$plusargs("L2DA_ERR_ENABLE")) || ($test$plusargs("L2VD_CE_ERR_INJECT")) || ($test$plusargs("L2TA_RAND_ERR_ENABLE")))) | |
84 | enabled = 1'b1; | |
85 | else | |
86 | **/ | |
87 | enabled = 1'b0; | |
88 | end | |
89 | ||
90 | always @ (flush_reset_complete) | |
91 | begin | |
92 | if (flush_reset_complete == 1'b0) | |
93 | enabled = 1'b0; | |
94 | ||
95 | if ((flush_reset_complete == 1'b1) && !($test$plusargs("l2err_checker_disable")) && (($test$plusargs("L2DA_ERR_ENABLE")) || ($test$plusargs("L2VD_CE_ERR_INJECT")) || ($test$plusargs("L2TA_RAND_ERR_ENABLE")) ) ) | |
96 | enabled = 1'b1; | |
97 | end | |
98 | //-------------------------------------------------------------------------------------- | |
99 | ||
100 | ||
101 | //L2_err_flag signal for SCOREBOARD | |
102 | always @(posedge tb_top.cpu.l2clk) | |
103 | begin | |
104 | if(!L2_INT_RST) | |
105 | begin | |
106 | L2_err_flag <= 0; | |
107 | end | |
108 | else | |
109 | begin | |
110 | if(enabled && cpx_packet_valid && cpx_packet_err == 2'b01 && (cpx_packet_rtntyp == 4'b1100 || cpx_packet_rtntyp == 4'b0000)) | |
111 | L2_err_flag <= 1; | |
112 | else L2_err_flag <= 0; | |
113 | ||
114 | end// else of if(RST) | |
115 | end | |
116 | ||
117 | ||
118 | //To detect if the packet was with a load or an error indication packet | |
119 | always @(posedge tb_top.cpu.l2clk) | |
120 | begin | |
121 | if(!L2_INT_RST) | |
122 | begin | |
123 | ld_pkt <= 0; | |
124 | err_pkt <= 0; | |
125 | end | |
126 | else | |
127 | begin | |
128 | ||
129 | if(cpx_packet_l2miss == 1 && cpx_packet_valid == 1 && cpx_packet_err == 2'b01 && cpx_packet_rtntyp == 4'b0000) | |
130 | begin | |
131 | ld_pkt <= 0; | |
132 | err_pkt <= 1; | |
133 | end | |
134 | ||
135 | else if(cpx_packet_l2miss != 1 && cpx_packet_valid == 1 && cpx_packet_err == 2'b01 && cpx_packet_rtntyp == 4'b0000) | |
136 | begin | |
137 | ld_pkt <= 1; | |
138 | err_pkt <= 0; | |
139 | end | |
140 | else if(cpx_packet_l2miss != 1 && cpx_packet_valid == 1 && cpx_packet_err == 2'b01 && cpx_packet_rtntyp == 4'b1100) | |
141 | begin | |
142 | ld_pkt <= 0; | |
143 | err_pkt <= 1; | |
144 | end | |
145 | else if(cpx_packet_valid == 1 && cpx_packet_err == 2'b01 && (cpx_packet_rtntyp == 4'b1100 || cpx_packet_rtntyp == 4'b0001 || cpx_packet_rtntyp == 4'b0010 || cpx_packet_rtntyp == 4'b0100 || cpx_packet_rtntyp == 4'b1101)) | |
146 | begin | |
147 | ld_pkt <= 0; | |
148 | err_pkt <= 1; | |
149 | end | |
150 | else | |
151 | begin | |
152 | ld_pkt <= 0; | |
153 | err_pkt <= 0; | |
154 | end | |
155 | ||
156 | end// else of if(RST) | |
157 | end | |
158 | ||
159 | ||
160 | ||
161 | //StateMachine for detecting the PCX Ack For ld_pkt - Sequential Logic | |
162 | always @(posedge tb_top.cpu.l2clk) | |
163 | begin | |
164 | if(!L2_INT_RST) | |
165 | currentstate <= S0; | |
166 | else | |
167 | currentstate <= nextstate; | |
168 | ||
169 | end | |
170 | ||
171 | ||
172 | ||
173 | //StateMachine for detecting the PCX Ack For ld_pkt - Combo Logic | |
174 | always @(currentstate or nextstate or L2_INT_RST or ld_pkt) | |
175 | begin | |
176 | if(!L2_INT_RST) | |
177 | begin | |
178 | nextstate <= S0; | |
179 | pck_grnt_flag_ld <= 0; | |
180 | end | |
181 | else | |
182 | begin | |
183 | case(currentstate) | |
184 | S0: begin | |
185 | if(ld_pkt == 1 && err_pkt == 0) | |
186 | begin | |
187 | if (cpx_grnt != 0) | |
188 | begin | |
189 | nextstate <= S0; | |
190 | pck_grnt_flag_ld <= 1; | |
191 | stmc_busy <= 0; | |
192 | end //if != 0) | |
193 | else | |
194 | begin | |
195 | nextstate <= S1; | |
196 | pck_grnt_flag_ld <= 0; | |
197 | stmc_busy <= 1; | |
198 | end //else of if != 0) | |
199 | end // if(ld_pkt == 1) | |
200 | else | |
201 | begin | |
202 | nextstate <= S0; | |
203 | pck_grnt_flag_ld <= 0; | |
204 | stmc_busy <= 0; | |
205 | end //else of if(L2_err_flag == 1) | |
206 | end //for case begin | |
207 | S1: begin | |
208 | if(cpx_grnt != 0) | |
209 | begin | |
210 | pck_grnt_flag_ld <= 1; | |
211 | nextstate <= S0; | |
212 | ||
213 | end | |
214 | else | |
215 | begin | |
216 | pck_grnt_flag_ld <= 0; | |
217 | nextstate <= S2; | |
218 | end | |
219 | end | |
220 | S2: begin | |
221 | if(cpx_grnt != 0) | |
222 | begin | |
223 | pck_grnt_flag_ld <= 1; | |
224 | nextstate <= S0; | |
225 | end | |
226 | else | |
227 | begin | |
228 | pck_grnt_flag_ld <= 0; | |
229 | nextstate <= S3; | |
230 | end | |
231 | end | |
232 | S3: begin | |
233 | if(cpx_grnt != 0) | |
234 | begin | |
235 | pck_grnt_flag_ld <= 1; | |
236 | nextstate <= S0; | |
237 | end | |
238 | else | |
239 | begin | |
240 | pck_grnt_flag_ld <= 0; | |
241 | nextstate <= S0; | |
242 | // `PR_ERROR("l2errChecker", `ERROR, "cpx_l2t_grant packet not generated by the CCX"); | |
243 | `PR_ALWAYS("l2errChecker", `ALWAYS, "cpx_l2t_grant packet not generated by the CCX"); | |
244 | ||
245 | ||
246 | end | |
247 | end | |
248 | endcase | |
249 | ||
250 | end //else of if(!ClrN) | |
251 | end//always block | |
252 | ||
253 | //StateMachine for detecting the PCX Ack For err_pkt - Sequential Logic | |
254 | always @(posedge tb_top.cpu.l2clk) | |
255 | begin | |
256 | if(!L2_INT_RST) | |
257 | currentstate1 <= S0; | |
258 | else | |
259 | currentstate1 <= nextstate1; | |
260 | ||
261 | end | |
262 | ||
263 | ||
264 | ||
265 | ||
266 | //StateMachine for detecting the PCX Ack For err_pkt - Combo Logic | |
267 | always @(currentstate1 or nextstate1 or L2_INT_RST or err_pkt) | |
268 | begin | |
269 | if(!L2_INT_RST) | |
270 | begin | |
271 | nextstate1 <= S0; | |
272 | pck_grnt_flag_err <= 0; | |
273 | end | |
274 | else | |
275 | begin | |
276 | case(currentstate1) | |
277 | S0: begin | |
278 | if(err_pkt == 1 && ld_pkt == 0) | |
279 | begin | |
280 | if (cpx_grnt != 0) | |
281 | begin | |
282 | nextstate1 <= S0; | |
283 | pck_grnt_flag_err <= 1; | |
284 | ||
285 | stmc_busy <= 0; | |
286 | end //if != 0) | |
287 | else | |
288 | begin | |
289 | nextstate1 <= S1; | |
290 | pck_grnt_flag_err <= 0; | |
291 | stmc_busy <= 1; | |
292 | end //else of if != 0) | |
293 | end // if(ld_pkt == 1) | |
294 | else | |
295 | begin | |
296 | nextstate1 <= S0; | |
297 | pck_grnt_flag_err <= 0; | |
298 | stmc_busy <= 0; | |
299 | end //else of if(L2_err_flag == 1) | |
300 | end //for case begin | |
301 | S1: begin | |
302 | if(cpx_grnt != 0) | |
303 | begin | |
304 | pck_grnt_flag_err <= 1; | |
305 | nextstate1 <= S0; | |
306 | ||
307 | end | |
308 | else | |
309 | begin | |
310 | pck_grnt_flag_err <= 0; | |
311 | nextstate1 <= S2; | |
312 | ||
313 | ||
314 | end | |
315 | end | |
316 | S2: begin | |
317 | if(cpx_grnt != 0) | |
318 | begin | |
319 | pck_grnt_flag_err <= 1; | |
320 | nextstate1 <= S0; | |
321 | ||
322 | end | |
323 | else | |
324 | begin | |
325 | pck_grnt_flag_err <= 0; | |
326 | nextstate1 <= S3; | |
327 | ||
328 | end | |
329 | end | |
330 | S3: begin | |
331 | if(cpx_grnt != 0) | |
332 | begin | |
333 | pck_grnt_flag_err <= 1; | |
334 | nextstate1 <= S0; | |
335 | end | |
336 | else | |
337 | begin | |
338 | pck_grnt_flag_err <= 0; | |
339 | nextstate1 <= S0; | |
340 | `PR_ALWAYS("l2errChecker", `ALWAYS, "cpx_l2t_grant packet not generated by the CCX"); | |
341 | //`PR_ERROR("l2errChecker", `ERROR, "cpx_l2t_grant packet not generated by the CCX"); | |
342 | ||
343 | end | |
344 | end | |
345 | endcase | |
346 | ||
347 | end //else of if(!ClrN) | |
348 | end//always block | |
349 | ||
350 | ||
351 | ||
352 | //For Checking DESR for error packet | |
353 | always @(pck_grnt_flag_err or desr_F or ras_desr_S or ras_desr_errtyp or enabled) // MAQ : Added Enabled | |
354 | begin | |
355 | if((pck_grnt_flag_err == 1) && (enabled == 1)) // MAQ : Added Enabled | |
356 | begin | |
357 | ||
358 | @(posedge tb_top.cpu.l2clk) | |
359 | @(posedge tb_top.cpu.l2clk) | |
360 | @(posedge tb_top.cpu.l2clk) | |
361 | @(posedge tb_top.cpu.l2clk) | |
362 | #(SAMPLE) | |
363 | if(desr_F == 0 && ras_desr_S ==0 && (ras_desr_errtyp ==1 || ras_desr_errtyp ==2 || ras_desr_errtyp ==3 || ras_desr_errtyp ==8 || ras_desr_errtyp == 9 || ras_desr_errtyp ==11 )) | |
364 | begin | |
365 | desr_correct <= 1; | |
366 | @(posedge tb_top.cpu.l2clk) | |
367 | if(desr_S == 0 && desr_F == 1 ) begin end | |
368 | else | |
369 | begin | |
370 | desr_correct <= 0; | |
371 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
372 | end | |
373 | end | |
374 | else if(desr_F == 0 && ras_desr_S ==1 && ras_desr_errtyp == 20) | |
375 | begin | |
376 | desr_correct <= 1; | |
377 | @(posedge tb_top.cpu.l2clk) | |
378 | if(desr_S == 1 && desr_F == 1 ) begin end | |
379 | else | |
380 | begin | |
381 | desr_correct <= 0; | |
382 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
383 | end | |
384 | end | |
385 | else if(desr_F == 1 && ras_desr_S ==1) | |
386 | begin | |
387 | desr_correct <= 1; | |
388 | @(posedge tb_top.cpu.l2clk) | |
389 | if(desr_S == 1 && desr_ME == 1 ) begin end | |
390 | else | |
391 | begin | |
392 | desr_correct <= 0; | |
393 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
394 | end | |
395 | end | |
396 | else if(desr_F == 1 && ras_desr_S ==0) | |
397 | begin | |
398 | desr_correct <= 1; | |
399 | @(posedge tb_top.cpu.l2clk) | |
400 | if(desr_ME == 1 ) begin end | |
401 | else | |
402 | begin | |
403 | desr_correct <= 0; | |
404 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
405 | end | |
406 | end | |
407 | ||
408 | else | |
409 | begin | |
410 | desr_correct <= 0; | |
411 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
412 | //`PR_ERROR("l2errChecker", `ERROR,"DESR is incorrectly Logged With Error Pcket"); | |
413 | end | |
414 | end | |
415 | else desr_correct <= 0; | |
416 | end | |
417 | ||
418 | ||
419 | //For Checking DESR for load instruction | |
420 | always @(pck_grnt_flag_ld or desr_F or ras_desr_S or ras_desr_errtyp or enabled) // MAQ : Added Enabled | |
421 | begin | |
422 | if((pck_grnt_flag_ld == 1) && (enabled == 1)) // MAQ : Added Enabled | |
423 | begin | |
424 | @(posedge tb_top.cpu.l2clk) | |
425 | @(posedge tb_top.cpu.l2clk) | |
426 | @(posedge tb_top.cpu.l2clk) | |
427 | @(posedge tb_top.cpu.l2clk) | |
428 | #(SAMPLE) | |
429 | if(desr_F == 0 && (ras_desr_S == 1) && (ras_desr_errtyp == 4)) | |
430 | begin | |
431 | desr_correct <= 1; | |
432 | @(posedge tb_top.cpu.l2clk) | |
433 | if(desr_S == 1 && desr_F == 1 ) begin end | |
434 | else | |
435 | begin | |
436 | desr_correct <= 0; | |
437 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
438 | end | |
439 | end | |
440 | else if(desr_F == 0 && (ras_desr_S == 0) && (ras_desr_errtyp == 9)) | |
441 | begin | |
442 | desr_correct <= 1; | |
443 | @(posedge tb_top.cpu.l2clk) | |
444 | if(desr_S == 0 && desr_F == 1 ) begin end | |
445 | else | |
446 | begin | |
447 | desr_correct <= 0; | |
448 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
449 | end | |
450 | end | |
451 | else if(desr_F == 1 && ras_desr_S ==1) | |
452 | begin | |
453 | desr_correct <= 1; | |
454 | @(posedge tb_top.cpu.l2clk) | |
455 | if(desr_S == 1 && desr_ME == 1 ) begin end | |
456 | else | |
457 | begin | |
458 | desr_correct <= 0; | |
459 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
460 | end | |
461 | end | |
462 | else if(desr_F == 1 && ras_desr_S ==0) | |
463 | begin | |
464 | desr_correct <= 1; | |
465 | @(posedge tb_top.cpu.l2clk) | |
466 | if(desr_ME == 1 ) begin end | |
467 | else | |
468 | begin | |
469 | desr_correct <= 0; | |
470 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged With Error Pcket"); | |
471 | end | |
472 | end | |
473 | ||
474 | else | |
475 | begin | |
476 | desr_correct <= 0; | |
477 | `PR_ALWAYS("l2errChecker", `ALWAYS,"DESR is incorrectly Logged, Load Return Packet With Error"); | |
478 | //`PR_ERROR("l2errChecker", `ERROR,"DESR is incorrectly Logged, Load Return Packet With Error"); | |
479 | ||
480 | end | |
481 | end | |
482 | else desr_correct <= 0; | |
483 | end | |
484 | ||
485 | ||
486 | //To count the number of cpx packets sent | |
487 | always @(L2_err_flag) | |
488 | begin | |
489 | if(L2_err_flag == 1) | |
490 | cpx_pkt_cnt <= cpx_pkt_cnt + 1; | |
491 | else cpx_pkt_cnt <= cpx_pkt_cnt; | |
492 | end | |
493 | ||
494 | //To count the number of time DESR was logged | |
495 | always @(desr_correct) | |
496 | begin | |
497 | if(desr_correct == 1) | |
498 | desr_log_cnt <= desr_log_cnt + 1; | |
499 | else desr_log_cnt <= desr_log_cnt; | |
500 | ||
501 | end | |
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | endmodule |