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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / int_sync / int.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: int.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`timescale 1 ps/ 1 ps
36
37`ifdef CORE_0
38
39// }}}
40
41module int_c0t0 ();
42`ifndef GATESIM
43
44// common defines
45`include "defines.vh"
46`include "ccx.vri"
47`include "cmp.vri"
48
49wire [2:0] mycid;
50wire [2:0] mytid;
51wire [5:0] mytnum;
52integer junk;
53
54reg [63:0] int_vec_recv_reg;
55reg int_vec_recv_reg_delta;
56reg int_vec_reg_rdwr;
57reg inc_vec_reg_rd;
58reg int_vec_reg_rdwr_late;
59reg [16:0] softint;
60reg softint_rdwr;
61reg softint_rdwr_late;
62reg softint_delta;
63reg hintp;
64reg hintp_rdwr;
65reg hintp_rdwr_late;
66reg hintp_delta;
67reg hstmatch_late;
68reg ready;
69reg [7:0] int_num_w;
70reg [7:0] int_num_fx4;
71reg [7:0] int_num_fx5;
72reg [7:0] int_num_fb;
73reg [7:0] int_num_fw;
74reg [7:0] int_num_fw1;
75reg [7:0] int_num_fw2;
76reg take_disrupting_w;
77reg take_disrupting_fx4;
78reg take_disrupting_fx5;
79reg take_disrupting_fb;
80reg take_disrupting_fw;
81reg take_disrupting_fw1;
82reg take_disrupting_fw2;
83
84 assign mycid = 0;
85 assign mytid = 0;
86 assign mytnum = 0*8 + 0;
87
88initial begin // {
89 ready = 0; // Wait for socket setup ..
90 inc_vec_reg_rd <= 1'b0;
91 int_vec_recv_reg_delta <= 1'b0;
92 softint_delta <= 1'b0;
93 hintp_delta <= 1'b0;
94 int_vec_recv_reg = 64'b0;
95 @(posedge `BENCH_SPC0_GCLK) ;
96 @(posedge `BENCH_SPC0_GCLK) ;
97 ready = `PARGS.int_sync_on;
98end //}
99
100
101/////////////////////////////// Probes //////////////////////////////////// {{{
102
103`define INT_VEC_RECV_REG_0 `SPC0.tlu.cth.int_rec0
104`define INT_VEC_RECV_ASIWR_0 (`TOP.nas_top.c0.t0.asi_wr_int_rec_delay)
105`define INT_VEC_RDWR_0 (`TOP.nas_top.c0.t0.asi_rdwr_int_rec)
106`define INT_VEC_TAKEN_0 `SPC0.tlu.trl0.take_ivt&`SPC0.tlu.trl0.trap[0]
107
108`define CPU_MONDO_TAKEN_0 `SPC0.tlu.trl0.take_mqr&`SPC0.tlu.trl0.trap[0]
109`define DEV_MONDO_TAKEN_0 `SPC0.tlu.trl0.take_dqr&`SPC0.tlu.trl0.trap[0]
110`define RES_MONDO_TAKEN_0 `SPC0.tlu.trl0.take_rqr&`SPC0.tlu.trl0.trap[0]
111
112`define XIR_TAKEN_0 `SPC0.tlu.trl0.take_xir&`SPC0.tlu.trl0.trap[0]
113
114`define SOFTINT_RDWR_0 (`TOP.nas_top.c0.t0.asi_rdwr_softint|`TOP.nas_top.c0.t0.asi_wr_softint_delay)
115
116`define SOFTINT_REG_0 `SPC0.tlu.trl0.softint0
117`define RD_SOFTINT_REG_0 `SPC0.tlu.trl0.rd_softint0
118`define INT_LEVEL_TAKEN_0 `SPC0.tlu.trl0.take_iln&`SPC0.tlu.trl0.trap[0]
119`define INT_LEVEL_NUM_0 `SPC0.tlu.trl0.int_level_n
120`define PMU_TAKEN_0 `SPC0.tlu.trl0.take_pmu&`SPC0.tlu.trl0.trap[0]
121
122`define HINTP_RDWR_0 (`TOP.nas_top.c0.t0.asi_rdwr_hintp | `TOP.nas_top.c0.t0.asi_wr_hintp_delay)
123`define HINTP_WR_0 (`SPC0.tlu.asi_wr_hintp[0])
124`define HSTMATCH_0 `SPC0.tlu.trl0.hstick0_compare
125
126`define HINTP_REG_0 `SPC0.tlu.trl0.hintp0
127`define HSTM_TAKEN_0 `SPC0.tlu.trl0.take_hst&`SPC0.tlu.trl0.trap[0]
128
129`define NAS_PIPE_FW2_0 |`TOP.nas_top.c0.t0.complete_fw2
130
131`define CWQ_TAKEN_0 `SPC0.tlu.trl0.take_cwq&`SPC0.tlu.trl0.trap[0]
132`define SMA_TAKEN_0 `SPC0.tlu.trl0.take_sma&`SPC0.tlu.trl0.trap[0]
133
134`define POR_TAKEN_0 `SPC0.tlu.trl0.take_por&`SPC0.tlu.trl0.trap[0]
135
136/////////////////////////////// Probes //////////////////////////////////// }}}
137
138always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
139
140 // {{{ DETECT, PIPE & SEND
141 take_disrupting_w <= (`INT_VEC_TAKEN_0 || `CPU_MONDO_TAKEN_0 ||
142 `DEV_MONDO_TAKEN_0 || `RES_MONDO_TAKEN_0 ||
143 `XIR_TAKEN_0 || `INT_LEVEL_TAKEN_0 ||
144 `HSTM_TAKEN_0 || `CWQ_TAKEN_0 ||
145 `SMA_TAKEN_0 || `PMU_TAKEN_0 || `POR_TAKEN_0);
146 take_disrupting_fx4 <= take_disrupting_w;
147 take_disrupting_fx5 <= take_disrupting_fx4;
148 take_disrupting_fb <= take_disrupting_fx5;
149 take_disrupting_fw <= take_disrupting_fb;
150 take_disrupting_fw1 <= take_disrupting_fw;
151 take_disrupting_fw2 <= take_disrupting_fw1;
152
153 case ({`INT_VEC_TAKEN_0, `CPU_MONDO_TAKEN_0,
154 `DEV_MONDO_TAKEN_0, `RES_MONDO_TAKEN_0,
155 `XIR_TAKEN_0, `INT_LEVEL_TAKEN_0,
156 `HSTM_TAKEN_0, `CWQ_TAKEN_0, `SMA_TAKEN_0 ,
157 `PMU_TAKEN_0, `POR_TAKEN_0})
158 11'b10000000000: int_num_w <= 8'h60;
159 11'b01000000000: int_num_w <= 8'h7c;
160 11'b00100000000: int_num_w <= 8'h7d;
161 11'b00010000000: int_num_w <= 8'h7e;
162 11'b00001000000: int_num_w <= 8'h03;
163 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_0;
164 11'b00000010000: int_num_w <= 8'h5e;
165 11'b00000001000: int_num_w <= 8'h3c;
166 11'b00000000100: int_num_w <= 8'h3d;
167 11'b00000000010: int_num_w <= 8'h4f;
168 11'b00000000001: int_num_w <= 8'h01;
169 endcase
170
171 int_num_fx4 <= int_num_w;
172 int_num_fx5 <= int_num_fx4;
173 int_num_fb <= int_num_fx5;
174 int_num_fw <= int_num_fb;
175 int_num_fw1 <= int_num_fw;
176 int_num_fw2 <= int_num_fw1;
177 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
178 begin // {
179 `PR_INFO ("pli_int", `INFO,
180 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
181 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
182 end // }
183
184 // }}}
185
186/////////////////////////// Vectored Interrupt /////////////////////////// {{{
187
188 // Vectored Interrupt Recv Register Detection
189 // Indicate when register changes due to arriving interrupt, and not
190 // due to read of incoming register or ASI write ..
191
192
193 // If any read occurs, send value right away.
194 // While a read/write is pending, do not update delta.
195 // Send non read/wr delta during fw2 ..
196
197
198 if (!(`INT_VEC_RDWR_0 | `INT_VEC_RECV_ASIWR_0)) begin // {
199 if (~`INT_VEC_RECV_ASIWR_0 &
200 (int_vec_recv_reg !== `INT_VEC_RECV_REG_0 ))
201 int_vec_recv_reg_delta <= 1'b1;
202 int_vec_recv_reg <= `INT_VEC_RECV_REG_0;
203 end // }
204 else if (`INT_VEC_RECV_ASIWR_0)
205 int_vec_recv_reg <= `TOP.nas_top.c0.t0.asi_updated_int_rec;
206
207 if ((`NAS_PIPE_FW2_0 & int_vec_recv_reg_delta ) |
208 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
209 `INT_VEC_RECV_ASIWR_0 ) begin // {
210 `PR_INFO ("pli_int", `INFO,
211 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
212 mycid,mytid, int_vec_recv_reg);
213 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
214 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
215 64'h0, int_vec_recv_reg);
216 end // }
217 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_0 &
218 (int_vec_recv_reg !== `INT_VEC_RECV_REG_0 ))))
219 int_vec_recv_reg_delta <= 1'b0;
220 end //}
221
222 int_vec_reg_rdwr <= `INT_VEC_RDWR_0 | `INT_VEC_RECV_ASIWR_0;
223 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_0 & ~ inc_vec_reg_rd;
224
225 if (`INT_VEC_RECV_ASIWR_0)
226 inc_vec_reg_rd <= 1'b1;
227 if (`NAS_PIPE_FW2_0)
228 inc_vec_reg_rd <= 1'b0;
229
230
231/////////////////////////// Vectored Interrupt /////////////////////////// }}}
232
233/////////////////////////// Asynchronous Resets ////////////////////////// {{{
234
235
236/////////////////////////// Asynchronous Resets ////////////////////////// }}}
237
238/////////////////////////// Softint ///////////////////////////////////// {{{
239
240 // Softint Register hardware Update Detection
241
242 // Non software updates (TM/SM)
243
244 // If any read occurs, send value right away.
245 // While a read/write is pending, do not update delta.
246 // Send non read/wr delta during fw2 ..
247
248 // RTL keeps pic_ovf indication in rd_softint and not softint.
249 // So for set/clear writes, we send softint before the write ..,
250 // and for read/asyncs we send rd_softint ..
251
252
253 if (~`SOFTINT_RDWR_0) begin // {
254 if (softint !== `RD_SOFTINT_REG_0 )
255 softint_delta <= 1'b1;
256 softint <= `RD_SOFTINT_REG_0;
257 end // }
258
259 if ((`NAS_PIPE_FW2_0 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
260 ) begin // {
261 `PR_INFO ("pli_int", `INFO,
262 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
263 mycid,mytid, {47'h0, softint});
264 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
265 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
266 {47'h0, softint});
267 end // }
268 if (!(~`SOFTINT_RDWR_0&(softint !== `RD_SOFTINT_REG_0)))
269 softint_delta <= 1'b0;
270 end //}
271 else if (`SPC0.tlu.asi_wr_clear_softint[0] |
272 `SPC0.tlu.asi_wr_set_softint[0] ) begin // {
273 `PR_INFO ("pli_int", `INFO,
274 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
275 mycid,mytid, {47'h0, `RD_SOFTINT_REG_0});
276 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
277 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
278 {47'h0, `RD_SOFTINT_REG_0});
279 end // }
280 end //}
281
282
283 softint_rdwr <= `SOFTINT_RDWR_0 ;
284 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_0;
285
286
287/////////////////////////// Softint ///////////////////////////////////// }}}
288
289/////////////////////////// Hintp ///////////////////////////////////// {{{
290
291 // Hintp Register hardware Update Detection
292
293 // Non software updates (HSP)
294 // If HINTP is already read/written by SW, then don't send
295 // any async updates to Nas. Reads/Writes pending sstep is detected
296 // by snooping nas_pipe ..
297
298 hintp <= `HINTP_REG_0 ;
299 if (hstmatch_late)
300 hintp_delta <= 1'b1;
301
302 if ((~hintp_rdwr & `NAS_PIPE_FW2_0 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
303 (hintp_rdwr_late & hintp_delta) ) begin // {
304 `PR_INFO ("pli_int", `INFO,
305 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
306 mycid,mytid, {63'h0, hintp});
307 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
308 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
309 {63'h0, hintp});
310 end // }
311 if (~(hintp_rdwr_late & hintp_delta))
312 hintp_delta <= 1'b0;
313 end //}
314
315 hintp_rdwr <= `HINTP_RDWR_0;
316 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_0;
317 hstmatch_late <= `HSTMATCH_0;
318
319
320/////////////////////////// Hintp ///////////////////////////////////// }}}
321
322end //}
323`endif
324endmodule
325
326// }}}
327
328module int_c0t1 ();
329`ifndef GATESIM
330
331// common defines
332`include "defines.vh"
333`include "ccx.vri"
334`include "cmp.vri"
335
336wire [2:0] mycid;
337wire [2:0] mytid;
338wire [5:0] mytnum;
339integer junk;
340
341reg [63:0] int_vec_recv_reg;
342reg int_vec_recv_reg_delta;
343reg int_vec_reg_rdwr;
344reg inc_vec_reg_rd;
345reg int_vec_reg_rdwr_late;
346reg [16:0] softint;
347reg softint_rdwr;
348reg softint_rdwr_late;
349reg softint_delta;
350reg hintp;
351reg hintp_rdwr;
352reg hintp_rdwr_late;
353reg hintp_delta;
354reg hstmatch_late;
355reg ready;
356reg [7:0] int_num_w;
357reg [7:0] int_num_fx4;
358reg [7:0] int_num_fx5;
359reg [7:0] int_num_fb;
360reg [7:0] int_num_fw;
361reg [7:0] int_num_fw1;
362reg [7:0] int_num_fw2;
363reg take_disrupting_w;
364reg take_disrupting_fx4;
365reg take_disrupting_fx5;
366reg take_disrupting_fb;
367reg take_disrupting_fw;
368reg take_disrupting_fw1;
369reg take_disrupting_fw2;
370
371 assign mycid = 0;
372 assign mytid = 1;
373 assign mytnum = 0*8 + 1;
374
375initial begin // {
376 ready = 0; // Wait for socket setup ..
377 inc_vec_reg_rd <= 1'b0;
378 int_vec_recv_reg_delta <= 1'b0;
379 softint_delta <= 1'b0;
380 hintp_delta <= 1'b0;
381 int_vec_recv_reg = 64'b0;
382 @(posedge `BENCH_SPC0_GCLK) ;
383 @(posedge `BENCH_SPC0_GCLK) ;
384 ready = `PARGS.int_sync_on;
385end //}
386
387
388/////////////////////////////// Probes //////////////////////////////////// {{{
389
390`define INT_VEC_RECV_REG_1 `SPC0.tlu.cth.int_rec1
391`define INT_VEC_RECV_ASIWR_1 (`TOP.nas_top.c0.t1.asi_wr_int_rec_delay)
392`define INT_VEC_RDWR_1 (`TOP.nas_top.c0.t1.asi_rdwr_int_rec)
393`define INT_VEC_TAKEN_1 `SPC0.tlu.trl0.take_ivt&`SPC0.tlu.trl0.trap[1]
394
395`define CPU_MONDO_TAKEN_1 `SPC0.tlu.trl0.take_mqr&`SPC0.tlu.trl0.trap[1]
396`define DEV_MONDO_TAKEN_1 `SPC0.tlu.trl0.take_dqr&`SPC0.tlu.trl0.trap[1]
397`define RES_MONDO_TAKEN_1 `SPC0.tlu.trl0.take_rqr&`SPC0.tlu.trl0.trap[1]
398
399`define XIR_TAKEN_1 `SPC0.tlu.trl0.take_xir&`SPC0.tlu.trl0.trap[1]
400
401`define SOFTINT_RDWR_1 (`TOP.nas_top.c0.t1.asi_rdwr_softint|`TOP.nas_top.c0.t1.asi_wr_softint_delay)
402
403`define SOFTINT_REG_1 `SPC0.tlu.trl0.softint1
404`define RD_SOFTINT_REG_1 `SPC0.tlu.trl0.rd_softint1
405`define INT_LEVEL_TAKEN_1 `SPC0.tlu.trl0.take_iln&`SPC0.tlu.trl0.trap[1]
406`define INT_LEVEL_NUM_1 `SPC0.tlu.trl0.int_level_n
407`define PMU_TAKEN_1 `SPC0.tlu.trl0.take_pmu&`SPC0.tlu.trl0.trap[1]
408
409`define HINTP_RDWR_1 (`TOP.nas_top.c0.t1.asi_rdwr_hintp | `TOP.nas_top.c0.t1.asi_wr_hintp_delay)
410`define HINTP_WR_1 (`SPC0.tlu.asi_wr_hintp[1])
411`define HSTMATCH_1 `SPC0.tlu.trl0.hstick1_compare
412
413`define HINTP_REG_1 `SPC0.tlu.trl0.hintp1
414`define HSTM_TAKEN_1 `SPC0.tlu.trl0.take_hst&`SPC0.tlu.trl0.trap[1]
415
416`define NAS_PIPE_FW2_1 |`TOP.nas_top.c0.t1.complete_fw2
417
418`define CWQ_TAKEN_1 `SPC0.tlu.trl0.take_cwq&`SPC0.tlu.trl0.trap[1]
419`define SMA_TAKEN_1 `SPC0.tlu.trl0.take_sma&`SPC0.tlu.trl0.trap[1]
420
421`define POR_TAKEN_1 `SPC0.tlu.trl0.take_por&`SPC0.tlu.trl0.trap[1]
422
423/////////////////////////////// Probes //////////////////////////////////// }}}
424
425always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
426
427 // {{{ DETECT, PIPE & SEND
428 take_disrupting_w <= (`INT_VEC_TAKEN_1 || `CPU_MONDO_TAKEN_1 ||
429 `DEV_MONDO_TAKEN_1 || `RES_MONDO_TAKEN_1 ||
430 `XIR_TAKEN_1 || `INT_LEVEL_TAKEN_1 ||
431 `HSTM_TAKEN_1 || `CWQ_TAKEN_1 ||
432 `SMA_TAKEN_1 || `PMU_TAKEN_1 || `POR_TAKEN_1);
433 take_disrupting_fx4 <= take_disrupting_w;
434 take_disrupting_fx5 <= take_disrupting_fx4;
435 take_disrupting_fb <= take_disrupting_fx5;
436 take_disrupting_fw <= take_disrupting_fb;
437 take_disrupting_fw1 <= take_disrupting_fw;
438 take_disrupting_fw2 <= take_disrupting_fw1;
439
440 case ({`INT_VEC_TAKEN_1, `CPU_MONDO_TAKEN_1,
441 `DEV_MONDO_TAKEN_1, `RES_MONDO_TAKEN_1,
442 `XIR_TAKEN_1, `INT_LEVEL_TAKEN_1,
443 `HSTM_TAKEN_1, `CWQ_TAKEN_1, `SMA_TAKEN_1 ,
444 `PMU_TAKEN_1, `POR_TAKEN_1})
445 11'b10000000000: int_num_w <= 8'h60;
446 11'b01000000000: int_num_w <= 8'h7c;
447 11'b00100000000: int_num_w <= 8'h7d;
448 11'b00010000000: int_num_w <= 8'h7e;
449 11'b00001000000: int_num_w <= 8'h03;
450 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_1;
451 11'b00000010000: int_num_w <= 8'h5e;
452 11'b00000001000: int_num_w <= 8'h3c;
453 11'b00000000100: int_num_w <= 8'h3d;
454 11'b00000000010: int_num_w <= 8'h4f;
455 11'b00000000001: int_num_w <= 8'h01;
456 endcase
457
458 int_num_fx4 <= int_num_w;
459 int_num_fx5 <= int_num_fx4;
460 int_num_fb <= int_num_fx5;
461 int_num_fw <= int_num_fb;
462 int_num_fw1 <= int_num_fw;
463 int_num_fw2 <= int_num_fw1;
464 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
465 begin // {
466 `PR_INFO ("pli_int", `INFO,
467 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
468 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
469 end // }
470
471 // }}}
472
473/////////////////////////// Vectored Interrupt /////////////////////////// {{{
474
475 // Vectored Interrupt Recv Register Detection
476 // Indicate when register changes due to arriving interrupt, and not
477 // due to read of incoming register or ASI write ..
478
479
480 // If any read occurs, send value right away.
481 // While a read/write is pending, do not update delta.
482 // Send non read/wr delta during fw2 ..
483
484
485 if (!(`INT_VEC_RDWR_1 | `INT_VEC_RECV_ASIWR_1)) begin // {
486 if (~`INT_VEC_RECV_ASIWR_1 &
487 (int_vec_recv_reg !== `INT_VEC_RECV_REG_1 ))
488 int_vec_recv_reg_delta <= 1'b1;
489 int_vec_recv_reg <= `INT_VEC_RECV_REG_1;
490 end // }
491 else if (`INT_VEC_RECV_ASIWR_1)
492 int_vec_recv_reg <= `TOP.nas_top.c0.t1.asi_updated_int_rec;
493
494 if ((`NAS_PIPE_FW2_1 & int_vec_recv_reg_delta ) |
495 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
496 `INT_VEC_RECV_ASIWR_1 ) begin // {
497 `PR_INFO ("pli_int", `INFO,
498 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
499 mycid,mytid, int_vec_recv_reg);
500 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
501 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
502 64'h0, int_vec_recv_reg);
503 end // }
504 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_1 &
505 (int_vec_recv_reg !== `INT_VEC_RECV_REG_1 ))))
506 int_vec_recv_reg_delta <= 1'b0;
507 end //}
508
509 int_vec_reg_rdwr <= `INT_VEC_RDWR_1 | `INT_VEC_RECV_ASIWR_1;
510 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_1 & ~ inc_vec_reg_rd;
511
512 if (`INT_VEC_RECV_ASIWR_1)
513 inc_vec_reg_rd <= 1'b1;
514 if (`NAS_PIPE_FW2_1)
515 inc_vec_reg_rd <= 1'b0;
516
517
518/////////////////////////// Vectored Interrupt /////////////////////////// }}}
519
520/////////////////////////// Asynchronous Resets ////////////////////////// {{{
521
522
523/////////////////////////// Asynchronous Resets ////////////////////////// }}}
524
525/////////////////////////// Softint ///////////////////////////////////// {{{
526
527 // Softint Register hardware Update Detection
528
529 // Non software updates (TM/SM)
530
531 // If any read occurs, send value right away.
532 // While a read/write is pending, do not update delta.
533 // Send non read/wr delta during fw2 ..
534
535 // RTL keeps pic_ovf indication in rd_softint and not softint.
536 // So for set/clear writes, we send softint before the write ..,
537 // and for read/asyncs we send rd_softint ..
538
539
540 if (~`SOFTINT_RDWR_1) begin // {
541 if (softint !== `RD_SOFTINT_REG_1 )
542 softint_delta <= 1'b1;
543 softint <= `RD_SOFTINT_REG_1;
544 end // }
545
546 if ((`NAS_PIPE_FW2_1 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
547 ) begin // {
548 `PR_INFO ("pli_int", `INFO,
549 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
550 mycid,mytid, {47'h0, softint});
551 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
552 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
553 {47'h0, softint});
554 end // }
555 if (!(~`SOFTINT_RDWR_1&(softint !== `RD_SOFTINT_REG_1)))
556 softint_delta <= 1'b0;
557 end //}
558 else if (`SPC0.tlu.asi_wr_clear_softint[1] |
559 `SPC0.tlu.asi_wr_set_softint[1] ) begin // {
560 `PR_INFO ("pli_int", `INFO,
561 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
562 mycid,mytid, {47'h0, `RD_SOFTINT_REG_1});
563 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
564 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
565 {47'h0, `RD_SOFTINT_REG_1});
566 end // }
567 end //}
568
569
570 softint_rdwr <= `SOFTINT_RDWR_1 ;
571 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_1;
572
573
574/////////////////////////// Softint ///////////////////////////////////// }}}
575
576/////////////////////////// Hintp ///////////////////////////////////// {{{
577
578 // Hintp Register hardware Update Detection
579
580 // Non software updates (HSP)
581 // If HINTP is already read/written by SW, then don't send
582 // any async updates to Nas. Reads/Writes pending sstep is detected
583 // by snooping nas_pipe ..
584
585 hintp <= `HINTP_REG_1 ;
586 if (hstmatch_late)
587 hintp_delta <= 1'b1;
588
589 if ((~hintp_rdwr & `NAS_PIPE_FW2_1 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
590 (hintp_rdwr_late & hintp_delta) ) begin // {
591 `PR_INFO ("pli_int", `INFO,
592 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
593 mycid,mytid, {63'h0, hintp});
594 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
595 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
596 {63'h0, hintp});
597 end // }
598 if (~(hintp_rdwr_late & hintp_delta))
599 hintp_delta <= 1'b0;
600 end //}
601
602 hintp_rdwr <= `HINTP_RDWR_1;
603 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_1;
604 hstmatch_late <= `HSTMATCH_1;
605
606
607/////////////////////////// Hintp ///////////////////////////////////// }}}
608
609end //}
610`endif
611endmodule
612
613// }}}
614
615module int_c0t2 ();
616`ifndef GATESIM
617
618// common defines
619`include "defines.vh"
620`include "ccx.vri"
621`include "cmp.vri"
622
623wire [2:0] mycid;
624wire [2:0] mytid;
625wire [5:0] mytnum;
626integer junk;
627
628reg [63:0] int_vec_recv_reg;
629reg int_vec_recv_reg_delta;
630reg int_vec_reg_rdwr;
631reg inc_vec_reg_rd;
632reg int_vec_reg_rdwr_late;
633reg [16:0] softint;
634reg softint_rdwr;
635reg softint_rdwr_late;
636reg softint_delta;
637reg hintp;
638reg hintp_rdwr;
639reg hintp_rdwr_late;
640reg hintp_delta;
641reg hstmatch_late;
642reg ready;
643reg [7:0] int_num_w;
644reg [7:0] int_num_fx4;
645reg [7:0] int_num_fx5;
646reg [7:0] int_num_fb;
647reg [7:0] int_num_fw;
648reg [7:0] int_num_fw1;
649reg [7:0] int_num_fw2;
650reg take_disrupting_w;
651reg take_disrupting_fx4;
652reg take_disrupting_fx5;
653reg take_disrupting_fb;
654reg take_disrupting_fw;
655reg take_disrupting_fw1;
656reg take_disrupting_fw2;
657
658 assign mycid = 0;
659 assign mytid = 2;
660 assign mytnum = 0*8 + 2;
661
662initial begin // {
663 ready = 0; // Wait for socket setup ..
664 inc_vec_reg_rd <= 1'b0;
665 int_vec_recv_reg_delta <= 1'b0;
666 softint_delta <= 1'b0;
667 hintp_delta <= 1'b0;
668 int_vec_recv_reg = 64'b0;
669 @(posedge `BENCH_SPC0_GCLK) ;
670 @(posedge `BENCH_SPC0_GCLK) ;
671 ready = `PARGS.int_sync_on;
672end //}
673
674
675/////////////////////////////// Probes //////////////////////////////////// {{{
676
677`define INT_VEC_RECV_REG_2 `SPC0.tlu.cth.int_rec2
678`define INT_VEC_RECV_ASIWR_2 (`TOP.nas_top.c0.t2.asi_wr_int_rec_delay)
679`define INT_VEC_RDWR_2 (`TOP.nas_top.c0.t2.asi_rdwr_int_rec)
680`define INT_VEC_TAKEN_2 `SPC0.tlu.trl0.take_ivt&`SPC0.tlu.trl0.trap[2]
681
682`define CPU_MONDO_TAKEN_2 `SPC0.tlu.trl0.take_mqr&`SPC0.tlu.trl0.trap[2]
683`define DEV_MONDO_TAKEN_2 `SPC0.tlu.trl0.take_dqr&`SPC0.tlu.trl0.trap[2]
684`define RES_MONDO_TAKEN_2 `SPC0.tlu.trl0.take_rqr&`SPC0.tlu.trl0.trap[2]
685
686`define XIR_TAKEN_2 `SPC0.tlu.trl0.take_xir&`SPC0.tlu.trl0.trap[2]
687
688`define SOFTINT_RDWR_2 (`TOP.nas_top.c0.t2.asi_rdwr_softint|`TOP.nas_top.c0.t2.asi_wr_softint_delay)
689
690`define SOFTINT_REG_2 `SPC0.tlu.trl0.softint2
691`define RD_SOFTINT_REG_2 `SPC0.tlu.trl0.rd_softint2
692`define INT_LEVEL_TAKEN_2 `SPC0.tlu.trl0.take_iln&`SPC0.tlu.trl0.trap[2]
693`define INT_LEVEL_NUM_2 `SPC0.tlu.trl0.int_level_n
694`define PMU_TAKEN_2 `SPC0.tlu.trl0.take_pmu&`SPC0.tlu.trl0.trap[2]
695
696`define HINTP_RDWR_2 (`TOP.nas_top.c0.t2.asi_rdwr_hintp | `TOP.nas_top.c0.t2.asi_wr_hintp_delay)
697`define HINTP_WR_2 (`SPC0.tlu.asi_wr_hintp[2])
698`define HSTMATCH_2 `SPC0.tlu.trl0.hstick2_compare
699
700`define HINTP_REG_2 `SPC0.tlu.trl0.hintp2
701`define HSTM_TAKEN_2 `SPC0.tlu.trl0.take_hst&`SPC0.tlu.trl0.trap[2]
702
703`define NAS_PIPE_FW2_2 |`TOP.nas_top.c0.t2.complete_fw2
704
705`define CWQ_TAKEN_2 `SPC0.tlu.trl0.take_cwq&`SPC0.tlu.trl0.trap[2]
706`define SMA_TAKEN_2 `SPC0.tlu.trl0.take_sma&`SPC0.tlu.trl0.trap[2]
707
708`define POR_TAKEN_2 `SPC0.tlu.trl0.take_por&`SPC0.tlu.trl0.trap[2]
709
710/////////////////////////////// Probes //////////////////////////////////// }}}
711
712always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
713
714 // {{{ DETECT, PIPE & SEND
715 take_disrupting_w <= (`INT_VEC_TAKEN_2 || `CPU_MONDO_TAKEN_2 ||
716 `DEV_MONDO_TAKEN_2 || `RES_MONDO_TAKEN_2 ||
717 `XIR_TAKEN_2 || `INT_LEVEL_TAKEN_2 ||
718 `HSTM_TAKEN_2 || `CWQ_TAKEN_2 ||
719 `SMA_TAKEN_2 || `PMU_TAKEN_2 || `POR_TAKEN_2);
720 take_disrupting_fx4 <= take_disrupting_w;
721 take_disrupting_fx5 <= take_disrupting_fx4;
722 take_disrupting_fb <= take_disrupting_fx5;
723 take_disrupting_fw <= take_disrupting_fb;
724 take_disrupting_fw1 <= take_disrupting_fw;
725 take_disrupting_fw2 <= take_disrupting_fw1;
726
727 case ({`INT_VEC_TAKEN_2, `CPU_MONDO_TAKEN_2,
728 `DEV_MONDO_TAKEN_2, `RES_MONDO_TAKEN_2,
729 `XIR_TAKEN_2, `INT_LEVEL_TAKEN_2,
730 `HSTM_TAKEN_2, `CWQ_TAKEN_2, `SMA_TAKEN_2 ,
731 `PMU_TAKEN_2, `POR_TAKEN_2})
732 11'b10000000000: int_num_w <= 8'h60;
733 11'b01000000000: int_num_w <= 8'h7c;
734 11'b00100000000: int_num_w <= 8'h7d;
735 11'b00010000000: int_num_w <= 8'h7e;
736 11'b00001000000: int_num_w <= 8'h03;
737 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_2;
738 11'b00000010000: int_num_w <= 8'h5e;
739 11'b00000001000: int_num_w <= 8'h3c;
740 11'b00000000100: int_num_w <= 8'h3d;
741 11'b00000000010: int_num_w <= 8'h4f;
742 11'b00000000001: int_num_w <= 8'h01;
743 endcase
744
745 int_num_fx4 <= int_num_w;
746 int_num_fx5 <= int_num_fx4;
747 int_num_fb <= int_num_fx5;
748 int_num_fw <= int_num_fb;
749 int_num_fw1 <= int_num_fw;
750 int_num_fw2 <= int_num_fw1;
751 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
752 begin // {
753 `PR_INFO ("pli_int", `INFO,
754 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
755 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
756 end // }
757
758 // }}}
759
760/////////////////////////// Vectored Interrupt /////////////////////////// {{{
761
762 // Vectored Interrupt Recv Register Detection
763 // Indicate when register changes due to arriving interrupt, and not
764 // due to read of incoming register or ASI write ..
765
766
767 // If any read occurs, send value right away.
768 // While a read/write is pending, do not update delta.
769 // Send non read/wr delta during fw2 ..
770
771
772 if (!(`INT_VEC_RDWR_2 | `INT_VEC_RECV_ASIWR_2)) begin // {
773 if (~`INT_VEC_RECV_ASIWR_2 &
774 (int_vec_recv_reg !== `INT_VEC_RECV_REG_2 ))
775 int_vec_recv_reg_delta <= 1'b1;
776 int_vec_recv_reg <= `INT_VEC_RECV_REG_2;
777 end // }
778 else if (`INT_VEC_RECV_ASIWR_2)
779 int_vec_recv_reg <= `TOP.nas_top.c0.t2.asi_updated_int_rec;
780
781 if ((`NAS_PIPE_FW2_2 & int_vec_recv_reg_delta ) |
782 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
783 `INT_VEC_RECV_ASIWR_2 ) begin // {
784 `PR_INFO ("pli_int", `INFO,
785 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
786 mycid,mytid, int_vec_recv_reg);
787 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
788 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
789 64'h0, int_vec_recv_reg);
790 end // }
791 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_2 &
792 (int_vec_recv_reg !== `INT_VEC_RECV_REG_2 ))))
793 int_vec_recv_reg_delta <= 1'b0;
794 end //}
795
796 int_vec_reg_rdwr <= `INT_VEC_RDWR_2 | `INT_VEC_RECV_ASIWR_2;
797 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_2 & ~ inc_vec_reg_rd;
798
799 if (`INT_VEC_RECV_ASIWR_2)
800 inc_vec_reg_rd <= 1'b1;
801 if (`NAS_PIPE_FW2_2)
802 inc_vec_reg_rd <= 1'b0;
803
804
805/////////////////////////// Vectored Interrupt /////////////////////////// }}}
806
807/////////////////////////// Asynchronous Resets ////////////////////////// {{{
808
809
810/////////////////////////// Asynchronous Resets ////////////////////////// }}}
811
812/////////////////////////// Softint ///////////////////////////////////// {{{
813
814 // Softint Register hardware Update Detection
815
816 // Non software updates (TM/SM)
817
818 // If any read occurs, send value right away.
819 // While a read/write is pending, do not update delta.
820 // Send non read/wr delta during fw2 ..
821
822 // RTL keeps pic_ovf indication in rd_softint and not softint.
823 // So for set/clear writes, we send softint before the write ..,
824 // and for read/asyncs we send rd_softint ..
825
826
827 if (~`SOFTINT_RDWR_2) begin // {
828 if (softint !== `RD_SOFTINT_REG_2 )
829 softint_delta <= 1'b1;
830 softint <= `RD_SOFTINT_REG_2;
831 end // }
832
833 if ((`NAS_PIPE_FW2_2 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
834 ) begin // {
835 `PR_INFO ("pli_int", `INFO,
836 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
837 mycid,mytid, {47'h0, softint});
838 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
839 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
840 {47'h0, softint});
841 end // }
842 if (!(~`SOFTINT_RDWR_2&(softint !== `RD_SOFTINT_REG_2)))
843 softint_delta <= 1'b0;
844 end //}
845 else if (`SPC0.tlu.asi_wr_clear_softint[2] |
846 `SPC0.tlu.asi_wr_set_softint[2] ) begin // {
847 `PR_INFO ("pli_int", `INFO,
848 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
849 mycid,mytid, {47'h0, `RD_SOFTINT_REG_2});
850 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
851 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
852 {47'h0, `RD_SOFTINT_REG_2});
853 end // }
854 end //}
855
856
857 softint_rdwr <= `SOFTINT_RDWR_2 ;
858 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_2;
859
860
861/////////////////////////// Softint ///////////////////////////////////// }}}
862
863/////////////////////////// Hintp ///////////////////////////////////// {{{
864
865 // Hintp Register hardware Update Detection
866
867 // Non software updates (HSP)
868 // If HINTP is already read/written by SW, then don't send
869 // any async updates to Nas. Reads/Writes pending sstep is detected
870 // by snooping nas_pipe ..
871
872 hintp <= `HINTP_REG_2 ;
873 if (hstmatch_late)
874 hintp_delta <= 1'b1;
875
876 if ((~hintp_rdwr & `NAS_PIPE_FW2_2 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
877 (hintp_rdwr_late & hintp_delta) ) begin // {
878 `PR_INFO ("pli_int", `INFO,
879 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
880 mycid,mytid, {63'h0, hintp});
881 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
882 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
883 {63'h0, hintp});
884 end // }
885 if (~(hintp_rdwr_late & hintp_delta))
886 hintp_delta <= 1'b0;
887 end //}
888
889 hintp_rdwr <= `HINTP_RDWR_2;
890 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_2;
891 hstmatch_late <= `HSTMATCH_2;
892
893
894/////////////////////////// Hintp ///////////////////////////////////// }}}
895
896end //}
897`endif
898endmodule
899
900// }}}
901
902module int_c0t3 ();
903`ifndef GATESIM
904
905// common defines
906`include "defines.vh"
907`include "ccx.vri"
908`include "cmp.vri"
909
910wire [2:0] mycid;
911wire [2:0] mytid;
912wire [5:0] mytnum;
913integer junk;
914
915reg [63:0] int_vec_recv_reg;
916reg int_vec_recv_reg_delta;
917reg int_vec_reg_rdwr;
918reg inc_vec_reg_rd;
919reg int_vec_reg_rdwr_late;
920reg [16:0] softint;
921reg softint_rdwr;
922reg softint_rdwr_late;
923reg softint_delta;
924reg hintp;
925reg hintp_rdwr;
926reg hintp_rdwr_late;
927reg hintp_delta;
928reg hstmatch_late;
929reg ready;
930reg [7:0] int_num_w;
931reg [7:0] int_num_fx4;
932reg [7:0] int_num_fx5;
933reg [7:0] int_num_fb;
934reg [7:0] int_num_fw;
935reg [7:0] int_num_fw1;
936reg [7:0] int_num_fw2;
937reg take_disrupting_w;
938reg take_disrupting_fx4;
939reg take_disrupting_fx5;
940reg take_disrupting_fb;
941reg take_disrupting_fw;
942reg take_disrupting_fw1;
943reg take_disrupting_fw2;
944
945 assign mycid = 0;
946 assign mytid = 3;
947 assign mytnum = 0*8 + 3;
948
949initial begin // {
950 ready = 0; // Wait for socket setup ..
951 inc_vec_reg_rd <= 1'b0;
952 int_vec_recv_reg_delta <= 1'b0;
953 softint_delta <= 1'b0;
954 hintp_delta <= 1'b0;
955 int_vec_recv_reg = 64'b0;
956 @(posedge `BENCH_SPC0_GCLK) ;
957 @(posedge `BENCH_SPC0_GCLK) ;
958 ready = `PARGS.int_sync_on;
959end //}
960
961
962/////////////////////////////// Probes //////////////////////////////////// {{{
963
964`define INT_VEC_RECV_REG_3 `SPC0.tlu.cth.int_rec3
965`define INT_VEC_RECV_ASIWR_3 (`TOP.nas_top.c0.t3.asi_wr_int_rec_delay)
966`define INT_VEC_RDWR_3 (`TOP.nas_top.c0.t3.asi_rdwr_int_rec)
967`define INT_VEC_TAKEN_3 `SPC0.tlu.trl0.take_ivt&`SPC0.tlu.trl0.trap[3]
968
969`define CPU_MONDO_TAKEN_3 `SPC0.tlu.trl0.take_mqr&`SPC0.tlu.trl0.trap[3]
970`define DEV_MONDO_TAKEN_3 `SPC0.tlu.trl0.take_dqr&`SPC0.tlu.trl0.trap[3]
971`define RES_MONDO_TAKEN_3 `SPC0.tlu.trl0.take_rqr&`SPC0.tlu.trl0.trap[3]
972
973`define XIR_TAKEN_3 `SPC0.tlu.trl0.take_xir&`SPC0.tlu.trl0.trap[3]
974
975`define SOFTINT_RDWR_3 (`TOP.nas_top.c0.t3.asi_rdwr_softint|`TOP.nas_top.c0.t3.asi_wr_softint_delay)
976
977`define SOFTINT_REG_3 `SPC0.tlu.trl0.softint3
978`define RD_SOFTINT_REG_3 `SPC0.tlu.trl0.rd_softint3
979`define INT_LEVEL_TAKEN_3 `SPC0.tlu.trl0.take_iln&`SPC0.tlu.trl0.trap[3]
980`define INT_LEVEL_NUM_3 `SPC0.tlu.trl0.int_level_n
981`define PMU_TAKEN_3 `SPC0.tlu.trl0.take_pmu&`SPC0.tlu.trl0.trap[3]
982
983`define HINTP_RDWR_3 (`TOP.nas_top.c0.t3.asi_rdwr_hintp | `TOP.nas_top.c0.t3.asi_wr_hintp_delay)
984`define HINTP_WR_3 (`SPC0.tlu.asi_wr_hintp[3])
985`define HSTMATCH_3 `SPC0.tlu.trl0.hstick3_compare
986
987`define HINTP_REG_3 `SPC0.tlu.trl0.hintp3
988`define HSTM_TAKEN_3 `SPC0.tlu.trl0.take_hst&`SPC0.tlu.trl0.trap[3]
989
990`define NAS_PIPE_FW2_3 |`TOP.nas_top.c0.t3.complete_fw2
991
992`define CWQ_TAKEN_3 `SPC0.tlu.trl0.take_cwq&`SPC0.tlu.trl0.trap[3]
993`define SMA_TAKEN_3 `SPC0.tlu.trl0.take_sma&`SPC0.tlu.trl0.trap[3]
994
995`define POR_TAKEN_3 `SPC0.tlu.trl0.take_por&`SPC0.tlu.trl0.trap[3]
996
997/////////////////////////////// Probes //////////////////////////////////// }}}
998
999always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
1000
1001 // {{{ DETECT, PIPE & SEND
1002 take_disrupting_w <= (`INT_VEC_TAKEN_3 || `CPU_MONDO_TAKEN_3 ||
1003 `DEV_MONDO_TAKEN_3 || `RES_MONDO_TAKEN_3 ||
1004 `XIR_TAKEN_3 || `INT_LEVEL_TAKEN_3 ||
1005 `HSTM_TAKEN_3 || `CWQ_TAKEN_3 ||
1006 `SMA_TAKEN_3 || `PMU_TAKEN_3 || `POR_TAKEN_3);
1007 take_disrupting_fx4 <= take_disrupting_w;
1008 take_disrupting_fx5 <= take_disrupting_fx4;
1009 take_disrupting_fb <= take_disrupting_fx5;
1010 take_disrupting_fw <= take_disrupting_fb;
1011 take_disrupting_fw1 <= take_disrupting_fw;
1012 take_disrupting_fw2 <= take_disrupting_fw1;
1013
1014 case ({`INT_VEC_TAKEN_3, `CPU_MONDO_TAKEN_3,
1015 `DEV_MONDO_TAKEN_3, `RES_MONDO_TAKEN_3,
1016 `XIR_TAKEN_3, `INT_LEVEL_TAKEN_3,
1017 `HSTM_TAKEN_3, `CWQ_TAKEN_3, `SMA_TAKEN_3 ,
1018 `PMU_TAKEN_3, `POR_TAKEN_3})
1019 11'b10000000000: int_num_w <= 8'h60;
1020 11'b01000000000: int_num_w <= 8'h7c;
1021 11'b00100000000: int_num_w <= 8'h7d;
1022 11'b00010000000: int_num_w <= 8'h7e;
1023 11'b00001000000: int_num_w <= 8'h03;
1024 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_3;
1025 11'b00000010000: int_num_w <= 8'h5e;
1026 11'b00000001000: int_num_w <= 8'h3c;
1027 11'b00000000100: int_num_w <= 8'h3d;
1028 11'b00000000010: int_num_w <= 8'h4f;
1029 11'b00000000001: int_num_w <= 8'h01;
1030 endcase
1031
1032 int_num_fx4 <= int_num_w;
1033 int_num_fx5 <= int_num_fx4;
1034 int_num_fb <= int_num_fx5;
1035 int_num_fw <= int_num_fb;
1036 int_num_fw1 <= int_num_fw;
1037 int_num_fw2 <= int_num_fw1;
1038 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
1039 begin // {
1040 `PR_INFO ("pli_int", `INFO,
1041 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
1042 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1043 end // }
1044
1045 // }}}
1046
1047/////////////////////////// Vectored Interrupt /////////////////////////// {{{
1048
1049 // Vectored Interrupt Recv Register Detection
1050 // Indicate when register changes due to arriving interrupt, and not
1051 // due to read of incoming register or ASI write ..
1052
1053
1054 // If any read occurs, send value right away.
1055 // While a read/write is pending, do not update delta.
1056 // Send non read/wr delta during fw2 ..
1057
1058
1059 if (!(`INT_VEC_RDWR_3 | `INT_VEC_RECV_ASIWR_3)) begin // {
1060 if (~`INT_VEC_RECV_ASIWR_3 &
1061 (int_vec_recv_reg !== `INT_VEC_RECV_REG_3 ))
1062 int_vec_recv_reg_delta <= 1'b1;
1063 int_vec_recv_reg <= `INT_VEC_RECV_REG_3;
1064 end // }
1065 else if (`INT_VEC_RECV_ASIWR_3)
1066 int_vec_recv_reg <= `TOP.nas_top.c0.t3.asi_updated_int_rec;
1067
1068 if ((`NAS_PIPE_FW2_3 & int_vec_recv_reg_delta ) |
1069 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
1070 `INT_VEC_RECV_ASIWR_3 ) begin // {
1071 `PR_INFO ("pli_int", `INFO,
1072 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
1073 mycid,mytid, int_vec_recv_reg);
1074 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1075 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
1076 64'h0, int_vec_recv_reg);
1077 end // }
1078 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_3 &
1079 (int_vec_recv_reg !== `INT_VEC_RECV_REG_3 ))))
1080 int_vec_recv_reg_delta <= 1'b0;
1081 end //}
1082
1083 int_vec_reg_rdwr <= `INT_VEC_RDWR_3 | `INT_VEC_RECV_ASIWR_3;
1084 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_3 & ~ inc_vec_reg_rd;
1085
1086 if (`INT_VEC_RECV_ASIWR_3)
1087 inc_vec_reg_rd <= 1'b1;
1088 if (`NAS_PIPE_FW2_3)
1089 inc_vec_reg_rd <= 1'b0;
1090
1091
1092/////////////////////////// Vectored Interrupt /////////////////////////// }}}
1093
1094/////////////////////////// Asynchronous Resets ////////////////////////// {{{
1095
1096
1097/////////////////////////// Asynchronous Resets ////////////////////////// }}}
1098
1099/////////////////////////// Softint ///////////////////////////////////// {{{
1100
1101 // Softint Register hardware Update Detection
1102
1103 // Non software updates (TM/SM)
1104
1105 // If any read occurs, send value right away.
1106 // While a read/write is pending, do not update delta.
1107 // Send non read/wr delta during fw2 ..
1108
1109 // RTL keeps pic_ovf indication in rd_softint and not softint.
1110 // So for set/clear writes, we send softint before the write ..,
1111 // and for read/asyncs we send rd_softint ..
1112
1113
1114 if (~`SOFTINT_RDWR_3) begin // {
1115 if (softint !== `RD_SOFTINT_REG_3 )
1116 softint_delta <= 1'b1;
1117 softint <= `RD_SOFTINT_REG_3;
1118 end // }
1119
1120 if ((`NAS_PIPE_FW2_3 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
1121 ) begin // {
1122 `PR_INFO ("pli_int", `INFO,
1123 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1124 mycid,mytid, {47'h0, softint});
1125 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1126 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1127 {47'h0, softint});
1128 end // }
1129 if (!(~`SOFTINT_RDWR_3&(softint !== `RD_SOFTINT_REG_3)))
1130 softint_delta <= 1'b0;
1131 end //}
1132 else if (`SPC0.tlu.asi_wr_clear_softint[3] |
1133 `SPC0.tlu.asi_wr_set_softint[3] ) begin // {
1134 `PR_INFO ("pli_int", `INFO,
1135 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1136 mycid,mytid, {47'h0, `RD_SOFTINT_REG_3});
1137 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1138 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1139 {47'h0, `RD_SOFTINT_REG_3});
1140 end // }
1141 end //}
1142
1143
1144 softint_rdwr <= `SOFTINT_RDWR_3 ;
1145 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_3;
1146
1147
1148/////////////////////////// Softint ///////////////////////////////////// }}}
1149
1150/////////////////////////// Hintp ///////////////////////////////////// {{{
1151
1152 // Hintp Register hardware Update Detection
1153
1154 // Non software updates (HSP)
1155 // If HINTP is already read/written by SW, then don't send
1156 // any async updates to Nas. Reads/Writes pending sstep is detected
1157 // by snooping nas_pipe ..
1158
1159 hintp <= `HINTP_REG_3 ;
1160 if (hstmatch_late)
1161 hintp_delta <= 1'b1;
1162
1163 if ((~hintp_rdwr & `NAS_PIPE_FW2_3 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
1164 (hintp_rdwr_late & hintp_delta) ) begin // {
1165 `PR_INFO ("pli_int", `INFO,
1166 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
1167 mycid,mytid, {63'h0, hintp});
1168 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1169 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
1170 {63'h0, hintp});
1171 end // }
1172 if (~(hintp_rdwr_late & hintp_delta))
1173 hintp_delta <= 1'b0;
1174 end //}
1175
1176 hintp_rdwr <= `HINTP_RDWR_3;
1177 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_3;
1178 hstmatch_late <= `HSTMATCH_3;
1179
1180
1181/////////////////////////// Hintp ///////////////////////////////////// }}}
1182
1183end //}
1184`endif
1185endmodule
1186
1187// }}}
1188
1189module int_c0t4 ();
1190`ifndef GATESIM
1191
1192// common defines
1193`include "defines.vh"
1194`include "ccx.vri"
1195`include "cmp.vri"
1196
1197wire [2:0] mycid;
1198wire [2:0] mytid;
1199wire [5:0] mytnum;
1200integer junk;
1201
1202reg [63:0] int_vec_recv_reg;
1203reg int_vec_recv_reg_delta;
1204reg int_vec_reg_rdwr;
1205reg inc_vec_reg_rd;
1206reg int_vec_reg_rdwr_late;
1207reg [16:0] softint;
1208reg softint_rdwr;
1209reg softint_rdwr_late;
1210reg softint_delta;
1211reg hintp;
1212reg hintp_rdwr;
1213reg hintp_rdwr_late;
1214reg hintp_delta;
1215reg hstmatch_late;
1216reg ready;
1217reg [7:0] int_num_w;
1218reg [7:0] int_num_fx4;
1219reg [7:0] int_num_fx5;
1220reg [7:0] int_num_fb;
1221reg [7:0] int_num_fw;
1222reg [7:0] int_num_fw1;
1223reg [7:0] int_num_fw2;
1224reg take_disrupting_w;
1225reg take_disrupting_fx4;
1226reg take_disrupting_fx5;
1227reg take_disrupting_fb;
1228reg take_disrupting_fw;
1229reg take_disrupting_fw1;
1230reg take_disrupting_fw2;
1231
1232 assign mycid = 0;
1233 assign mytid = 4;
1234 assign mytnum = 0*8 + 4;
1235
1236initial begin // {
1237 ready = 0; // Wait for socket setup ..
1238 inc_vec_reg_rd <= 1'b0;
1239 int_vec_recv_reg_delta <= 1'b0;
1240 softint_delta <= 1'b0;
1241 hintp_delta <= 1'b0;
1242 int_vec_recv_reg = 64'b0;
1243 @(posedge `BENCH_SPC0_GCLK) ;
1244 @(posedge `BENCH_SPC0_GCLK) ;
1245 ready = `PARGS.int_sync_on;
1246end //}
1247
1248
1249/////////////////////////////// Probes //////////////////////////////////// {{{
1250
1251`define INT_VEC_RECV_REG_4 `SPC0.tlu.cth.int_rec4
1252`define INT_VEC_RECV_ASIWR_4 (`TOP.nas_top.c0.t4.asi_wr_int_rec_delay)
1253`define INT_VEC_RDWR_4 (`TOP.nas_top.c0.t4.asi_rdwr_int_rec)
1254`define INT_VEC_TAKEN_4 `SPC0.tlu.trl1.take_ivt&`SPC0.tlu.trl1.trap[0]
1255
1256`define CPU_MONDO_TAKEN_4 `SPC0.tlu.trl1.take_mqr&`SPC0.tlu.trl1.trap[0]
1257`define DEV_MONDO_TAKEN_4 `SPC0.tlu.trl1.take_dqr&`SPC0.tlu.trl1.trap[0]
1258`define RES_MONDO_TAKEN_4 `SPC0.tlu.trl1.take_rqr&`SPC0.tlu.trl1.trap[0]
1259
1260`define XIR_TAKEN_4 `SPC0.tlu.trl1.take_xir&`SPC0.tlu.trl1.trap[0]
1261
1262`define SOFTINT_RDWR_4 (`TOP.nas_top.c0.t4.asi_rdwr_softint|`TOP.nas_top.c0.t4.asi_wr_softint_delay)
1263
1264`define SOFTINT_REG_4 `SPC0.tlu.trl1.softint0
1265`define RD_SOFTINT_REG_4 `SPC0.tlu.trl1.rd_softint0
1266`define INT_LEVEL_TAKEN_4 `SPC0.tlu.trl1.take_iln&`SPC0.tlu.trl1.trap[0]
1267`define INT_LEVEL_NUM_4 `SPC0.tlu.trl1.int_level_n
1268`define PMU_TAKEN_4 `SPC0.tlu.trl1.take_pmu&`SPC0.tlu.trl1.trap[0]
1269
1270`define HINTP_RDWR_4 (`TOP.nas_top.c0.t4.asi_rdwr_hintp | `TOP.nas_top.c0.t4.asi_wr_hintp_delay)
1271`define HINTP_WR_4 (`SPC0.tlu.asi_wr_hintp[4])
1272`define HSTMATCH_4 `SPC0.tlu.trl1.hstick0_compare
1273
1274`define HINTP_REG_4 `SPC0.tlu.trl1.hintp0
1275`define HSTM_TAKEN_4 `SPC0.tlu.trl1.take_hst&`SPC0.tlu.trl1.trap[0]
1276
1277`define NAS_PIPE_FW2_4 |`TOP.nas_top.c0.t4.complete_fw2
1278
1279`define CWQ_TAKEN_4 `SPC0.tlu.trl1.take_cwq&`SPC0.tlu.trl1.trap[0]
1280`define SMA_TAKEN_4 `SPC0.tlu.trl1.take_sma&`SPC0.tlu.trl1.trap[0]
1281
1282`define POR_TAKEN_4 `SPC0.tlu.trl1.take_por&`SPC0.tlu.trl1.trap[0]
1283
1284/////////////////////////////// Probes //////////////////////////////////// }}}
1285
1286always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
1287
1288 // {{{ DETECT, PIPE & SEND
1289 take_disrupting_w <= (`INT_VEC_TAKEN_4 || `CPU_MONDO_TAKEN_4 ||
1290 `DEV_MONDO_TAKEN_4 || `RES_MONDO_TAKEN_4 ||
1291 `XIR_TAKEN_4 || `INT_LEVEL_TAKEN_4 ||
1292 `HSTM_TAKEN_4 || `CWQ_TAKEN_4 ||
1293 `SMA_TAKEN_4 || `PMU_TAKEN_4 || `POR_TAKEN_4);
1294 take_disrupting_fx4 <= take_disrupting_w;
1295 take_disrupting_fx5 <= take_disrupting_fx4;
1296 take_disrupting_fb <= take_disrupting_fx5;
1297 take_disrupting_fw <= take_disrupting_fb;
1298 take_disrupting_fw1 <= take_disrupting_fw;
1299 take_disrupting_fw2 <= take_disrupting_fw1;
1300
1301 case ({`INT_VEC_TAKEN_4, `CPU_MONDO_TAKEN_4,
1302 `DEV_MONDO_TAKEN_4, `RES_MONDO_TAKEN_4,
1303 `XIR_TAKEN_4, `INT_LEVEL_TAKEN_4,
1304 `HSTM_TAKEN_4, `CWQ_TAKEN_4, `SMA_TAKEN_4 ,
1305 `PMU_TAKEN_4, `POR_TAKEN_4})
1306 11'b10000000000: int_num_w <= 8'h60;
1307 11'b01000000000: int_num_w <= 8'h7c;
1308 11'b00100000000: int_num_w <= 8'h7d;
1309 11'b00010000000: int_num_w <= 8'h7e;
1310 11'b00001000000: int_num_w <= 8'h03;
1311 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_4;
1312 11'b00000010000: int_num_w <= 8'h5e;
1313 11'b00000001000: int_num_w <= 8'h3c;
1314 11'b00000000100: int_num_w <= 8'h3d;
1315 11'b00000000010: int_num_w <= 8'h4f;
1316 11'b00000000001: int_num_w <= 8'h01;
1317 endcase
1318
1319 int_num_fx4 <= int_num_w;
1320 int_num_fx5 <= int_num_fx4;
1321 int_num_fb <= int_num_fx5;
1322 int_num_fw <= int_num_fb;
1323 int_num_fw1 <= int_num_fw;
1324 int_num_fw2 <= int_num_fw1;
1325 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
1326 begin // {
1327 `PR_INFO ("pli_int", `INFO,
1328 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
1329 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1330 end // }
1331
1332 // }}}
1333
1334/////////////////////////// Vectored Interrupt /////////////////////////// {{{
1335
1336 // Vectored Interrupt Recv Register Detection
1337 // Indicate when register changes due to arriving interrupt, and not
1338 // due to read of incoming register or ASI write ..
1339
1340
1341 // If any read occurs, send value right away.
1342 // While a read/write is pending, do not update delta.
1343 // Send non read/wr delta during fw2 ..
1344
1345
1346 if (!(`INT_VEC_RDWR_4 | `INT_VEC_RECV_ASIWR_4)) begin // {
1347 if (~`INT_VEC_RECV_ASIWR_4 &
1348 (int_vec_recv_reg !== `INT_VEC_RECV_REG_4 ))
1349 int_vec_recv_reg_delta <= 1'b1;
1350 int_vec_recv_reg <= `INT_VEC_RECV_REG_4;
1351 end // }
1352 else if (`INT_VEC_RECV_ASIWR_4)
1353 int_vec_recv_reg <= `TOP.nas_top.c0.t4.asi_updated_int_rec;
1354
1355 if ((`NAS_PIPE_FW2_4 & int_vec_recv_reg_delta ) |
1356 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
1357 `INT_VEC_RECV_ASIWR_4 ) begin // {
1358 `PR_INFO ("pli_int", `INFO,
1359 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
1360 mycid,mytid, int_vec_recv_reg);
1361 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1362 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
1363 64'h0, int_vec_recv_reg);
1364 end // }
1365 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_4 &
1366 (int_vec_recv_reg !== `INT_VEC_RECV_REG_4 ))))
1367 int_vec_recv_reg_delta <= 1'b0;
1368 end //}
1369
1370 int_vec_reg_rdwr <= `INT_VEC_RDWR_4 | `INT_VEC_RECV_ASIWR_4;
1371 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_4 & ~ inc_vec_reg_rd;
1372
1373 if (`INT_VEC_RECV_ASIWR_4)
1374 inc_vec_reg_rd <= 1'b1;
1375 if (`NAS_PIPE_FW2_4)
1376 inc_vec_reg_rd <= 1'b0;
1377
1378
1379/////////////////////////// Vectored Interrupt /////////////////////////// }}}
1380
1381/////////////////////////// Asynchronous Resets ////////////////////////// {{{
1382
1383
1384/////////////////////////// Asynchronous Resets ////////////////////////// }}}
1385
1386/////////////////////////// Softint ///////////////////////////////////// {{{
1387
1388 // Softint Register hardware Update Detection
1389
1390 // Non software updates (TM/SM)
1391
1392 // If any read occurs, send value right away.
1393 // While a read/write is pending, do not update delta.
1394 // Send non read/wr delta during fw2 ..
1395
1396 // RTL keeps pic_ovf indication in rd_softint and not softint.
1397 // So for set/clear writes, we send softint before the write ..,
1398 // and for read/asyncs we send rd_softint ..
1399
1400
1401 if (~`SOFTINT_RDWR_4) begin // {
1402 if (softint !== `RD_SOFTINT_REG_4 )
1403 softint_delta <= 1'b1;
1404 softint <= `RD_SOFTINT_REG_4;
1405 end // }
1406
1407 if ((`NAS_PIPE_FW2_4 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
1408 ) begin // {
1409 `PR_INFO ("pli_int", `INFO,
1410 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1411 mycid,mytid, {47'h0, softint});
1412 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1413 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1414 {47'h0, softint});
1415 end // }
1416 if (!(~`SOFTINT_RDWR_4&(softint !== `RD_SOFTINT_REG_4)))
1417 softint_delta <= 1'b0;
1418 end //}
1419 else if (`SPC0.tlu.asi_wr_clear_softint[4] |
1420 `SPC0.tlu.asi_wr_set_softint[4] ) begin // {
1421 `PR_INFO ("pli_int", `INFO,
1422 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1423 mycid,mytid, {47'h0, `RD_SOFTINT_REG_4});
1424 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1425 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1426 {47'h0, `RD_SOFTINT_REG_4});
1427 end // }
1428 end //}
1429
1430
1431 softint_rdwr <= `SOFTINT_RDWR_4 ;
1432 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_4;
1433
1434
1435/////////////////////////// Softint ///////////////////////////////////// }}}
1436
1437/////////////////////////// Hintp ///////////////////////////////////// {{{
1438
1439 // Hintp Register hardware Update Detection
1440
1441 // Non software updates (HSP)
1442 // If HINTP is already read/written by SW, then don't send
1443 // any async updates to Nas. Reads/Writes pending sstep is detected
1444 // by snooping nas_pipe ..
1445
1446 hintp <= `HINTP_REG_4 ;
1447 if (hstmatch_late)
1448 hintp_delta <= 1'b1;
1449
1450 if ((~hintp_rdwr & `NAS_PIPE_FW2_4 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
1451 (hintp_rdwr_late & hintp_delta) ) begin // {
1452 `PR_INFO ("pli_int", `INFO,
1453 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
1454 mycid,mytid, {63'h0, hintp});
1455 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1456 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
1457 {63'h0, hintp});
1458 end // }
1459 if (~(hintp_rdwr_late & hintp_delta))
1460 hintp_delta <= 1'b0;
1461 end //}
1462
1463 hintp_rdwr <= `HINTP_RDWR_4;
1464 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_4;
1465 hstmatch_late <= `HSTMATCH_4;
1466
1467
1468/////////////////////////// Hintp ///////////////////////////////////// }}}
1469
1470end //}
1471`endif
1472endmodule
1473
1474// }}}
1475
1476module int_c0t5 ();
1477`ifndef GATESIM
1478
1479// common defines
1480`include "defines.vh"
1481`include "ccx.vri"
1482`include "cmp.vri"
1483
1484wire [2:0] mycid;
1485wire [2:0] mytid;
1486wire [5:0] mytnum;
1487integer junk;
1488
1489reg [63:0] int_vec_recv_reg;
1490reg int_vec_recv_reg_delta;
1491reg int_vec_reg_rdwr;
1492reg inc_vec_reg_rd;
1493reg int_vec_reg_rdwr_late;
1494reg [16:0] softint;
1495reg softint_rdwr;
1496reg softint_rdwr_late;
1497reg softint_delta;
1498reg hintp;
1499reg hintp_rdwr;
1500reg hintp_rdwr_late;
1501reg hintp_delta;
1502reg hstmatch_late;
1503reg ready;
1504reg [7:0] int_num_w;
1505reg [7:0] int_num_fx4;
1506reg [7:0] int_num_fx5;
1507reg [7:0] int_num_fb;
1508reg [7:0] int_num_fw;
1509reg [7:0] int_num_fw1;
1510reg [7:0] int_num_fw2;
1511reg take_disrupting_w;
1512reg take_disrupting_fx4;
1513reg take_disrupting_fx5;
1514reg take_disrupting_fb;
1515reg take_disrupting_fw;
1516reg take_disrupting_fw1;
1517reg take_disrupting_fw2;
1518
1519 assign mycid = 0;
1520 assign mytid = 5;
1521 assign mytnum = 0*8 + 5;
1522
1523initial begin // {
1524 ready = 0; // Wait for socket setup ..
1525 inc_vec_reg_rd <= 1'b0;
1526 int_vec_recv_reg_delta <= 1'b0;
1527 softint_delta <= 1'b0;
1528 hintp_delta <= 1'b0;
1529 int_vec_recv_reg = 64'b0;
1530 @(posedge `BENCH_SPC0_GCLK) ;
1531 @(posedge `BENCH_SPC0_GCLK) ;
1532 ready = `PARGS.int_sync_on;
1533end //}
1534
1535
1536/////////////////////////////// Probes //////////////////////////////////// {{{
1537
1538`define INT_VEC_RECV_REG_5 `SPC0.tlu.cth.int_rec5
1539`define INT_VEC_RECV_ASIWR_5 (`TOP.nas_top.c0.t5.asi_wr_int_rec_delay)
1540`define INT_VEC_RDWR_5 (`TOP.nas_top.c0.t5.asi_rdwr_int_rec)
1541`define INT_VEC_TAKEN_5 `SPC0.tlu.trl1.take_ivt&`SPC0.tlu.trl1.trap[1]
1542
1543`define CPU_MONDO_TAKEN_5 `SPC0.tlu.trl1.take_mqr&`SPC0.tlu.trl1.trap[1]
1544`define DEV_MONDO_TAKEN_5 `SPC0.tlu.trl1.take_dqr&`SPC0.tlu.trl1.trap[1]
1545`define RES_MONDO_TAKEN_5 `SPC0.tlu.trl1.take_rqr&`SPC0.tlu.trl1.trap[1]
1546
1547`define XIR_TAKEN_5 `SPC0.tlu.trl1.take_xir&`SPC0.tlu.trl1.trap[1]
1548
1549`define SOFTINT_RDWR_5 (`TOP.nas_top.c0.t5.asi_rdwr_softint|`TOP.nas_top.c0.t5.asi_wr_softint_delay)
1550
1551`define SOFTINT_REG_5 `SPC0.tlu.trl1.softint1
1552`define RD_SOFTINT_REG_5 `SPC0.tlu.trl1.rd_softint1
1553`define INT_LEVEL_TAKEN_5 `SPC0.tlu.trl1.take_iln&`SPC0.tlu.trl1.trap[1]
1554`define INT_LEVEL_NUM_5 `SPC0.tlu.trl1.int_level_n
1555`define PMU_TAKEN_5 `SPC0.tlu.trl1.take_pmu&`SPC0.tlu.trl1.trap[1]
1556
1557`define HINTP_RDWR_5 (`TOP.nas_top.c0.t5.asi_rdwr_hintp | `TOP.nas_top.c0.t5.asi_wr_hintp_delay)
1558`define HINTP_WR_5 (`SPC0.tlu.asi_wr_hintp[5])
1559`define HSTMATCH_5 `SPC0.tlu.trl1.hstick1_compare
1560
1561`define HINTP_REG_5 `SPC0.tlu.trl1.hintp1
1562`define HSTM_TAKEN_5 `SPC0.tlu.trl1.take_hst&`SPC0.tlu.trl1.trap[1]
1563
1564`define NAS_PIPE_FW2_5 |`TOP.nas_top.c0.t5.complete_fw2
1565
1566`define CWQ_TAKEN_5 `SPC0.tlu.trl1.take_cwq&`SPC0.tlu.trl1.trap[1]
1567`define SMA_TAKEN_5 `SPC0.tlu.trl1.take_sma&`SPC0.tlu.trl1.trap[1]
1568
1569`define POR_TAKEN_5 `SPC0.tlu.trl1.take_por&`SPC0.tlu.trl1.trap[1]
1570
1571/////////////////////////////// Probes //////////////////////////////////// }}}
1572
1573always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
1574
1575 // {{{ DETECT, PIPE & SEND
1576 take_disrupting_w <= (`INT_VEC_TAKEN_5 || `CPU_MONDO_TAKEN_5 ||
1577 `DEV_MONDO_TAKEN_5 || `RES_MONDO_TAKEN_5 ||
1578 `XIR_TAKEN_5 || `INT_LEVEL_TAKEN_5 ||
1579 `HSTM_TAKEN_5 || `CWQ_TAKEN_5 ||
1580 `SMA_TAKEN_5 || `PMU_TAKEN_5 || `POR_TAKEN_5);
1581 take_disrupting_fx4 <= take_disrupting_w;
1582 take_disrupting_fx5 <= take_disrupting_fx4;
1583 take_disrupting_fb <= take_disrupting_fx5;
1584 take_disrupting_fw <= take_disrupting_fb;
1585 take_disrupting_fw1 <= take_disrupting_fw;
1586 take_disrupting_fw2 <= take_disrupting_fw1;
1587
1588 case ({`INT_VEC_TAKEN_5, `CPU_MONDO_TAKEN_5,
1589 `DEV_MONDO_TAKEN_5, `RES_MONDO_TAKEN_5,
1590 `XIR_TAKEN_5, `INT_LEVEL_TAKEN_5,
1591 `HSTM_TAKEN_5, `CWQ_TAKEN_5, `SMA_TAKEN_5 ,
1592 `PMU_TAKEN_5, `POR_TAKEN_5})
1593 11'b10000000000: int_num_w <= 8'h60;
1594 11'b01000000000: int_num_w <= 8'h7c;
1595 11'b00100000000: int_num_w <= 8'h7d;
1596 11'b00010000000: int_num_w <= 8'h7e;
1597 11'b00001000000: int_num_w <= 8'h03;
1598 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_5;
1599 11'b00000010000: int_num_w <= 8'h5e;
1600 11'b00000001000: int_num_w <= 8'h3c;
1601 11'b00000000100: int_num_w <= 8'h3d;
1602 11'b00000000010: int_num_w <= 8'h4f;
1603 11'b00000000001: int_num_w <= 8'h01;
1604 endcase
1605
1606 int_num_fx4 <= int_num_w;
1607 int_num_fx5 <= int_num_fx4;
1608 int_num_fb <= int_num_fx5;
1609 int_num_fw <= int_num_fb;
1610 int_num_fw1 <= int_num_fw;
1611 int_num_fw2 <= int_num_fw1;
1612 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
1613 begin // {
1614 `PR_INFO ("pli_int", `INFO,
1615 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
1616 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1617 end // }
1618
1619 // }}}
1620
1621/////////////////////////// Vectored Interrupt /////////////////////////// {{{
1622
1623 // Vectored Interrupt Recv Register Detection
1624 // Indicate when register changes due to arriving interrupt, and not
1625 // due to read of incoming register or ASI write ..
1626
1627
1628 // If any read occurs, send value right away.
1629 // While a read/write is pending, do not update delta.
1630 // Send non read/wr delta during fw2 ..
1631
1632
1633 if (!(`INT_VEC_RDWR_5 | `INT_VEC_RECV_ASIWR_5)) begin // {
1634 if (~`INT_VEC_RECV_ASIWR_5 &
1635 (int_vec_recv_reg !== `INT_VEC_RECV_REG_5 ))
1636 int_vec_recv_reg_delta <= 1'b1;
1637 int_vec_recv_reg <= `INT_VEC_RECV_REG_5;
1638 end // }
1639 else if (`INT_VEC_RECV_ASIWR_5)
1640 int_vec_recv_reg <= `TOP.nas_top.c0.t5.asi_updated_int_rec;
1641
1642 if ((`NAS_PIPE_FW2_5 & int_vec_recv_reg_delta ) |
1643 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
1644 `INT_VEC_RECV_ASIWR_5 ) begin // {
1645 `PR_INFO ("pli_int", `INFO,
1646 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
1647 mycid,mytid, int_vec_recv_reg);
1648 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1649 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
1650 64'h0, int_vec_recv_reg);
1651 end // }
1652 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_5 &
1653 (int_vec_recv_reg !== `INT_VEC_RECV_REG_5 ))))
1654 int_vec_recv_reg_delta <= 1'b0;
1655 end //}
1656
1657 int_vec_reg_rdwr <= `INT_VEC_RDWR_5 | `INT_VEC_RECV_ASIWR_5;
1658 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_5 & ~ inc_vec_reg_rd;
1659
1660 if (`INT_VEC_RECV_ASIWR_5)
1661 inc_vec_reg_rd <= 1'b1;
1662 if (`NAS_PIPE_FW2_5)
1663 inc_vec_reg_rd <= 1'b0;
1664
1665
1666/////////////////////////// Vectored Interrupt /////////////////////////// }}}
1667
1668/////////////////////////// Asynchronous Resets ////////////////////////// {{{
1669
1670
1671/////////////////////////// Asynchronous Resets ////////////////////////// }}}
1672
1673/////////////////////////// Softint ///////////////////////////////////// {{{
1674
1675 // Softint Register hardware Update Detection
1676
1677 // Non software updates (TM/SM)
1678
1679 // If any read occurs, send value right away.
1680 // While a read/write is pending, do not update delta.
1681 // Send non read/wr delta during fw2 ..
1682
1683 // RTL keeps pic_ovf indication in rd_softint and not softint.
1684 // So for set/clear writes, we send softint before the write ..,
1685 // and for read/asyncs we send rd_softint ..
1686
1687
1688 if (~`SOFTINT_RDWR_5) begin // {
1689 if (softint !== `RD_SOFTINT_REG_5 )
1690 softint_delta <= 1'b1;
1691 softint <= `RD_SOFTINT_REG_5;
1692 end // }
1693
1694 if ((`NAS_PIPE_FW2_5 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
1695 ) begin // {
1696 `PR_INFO ("pli_int", `INFO,
1697 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1698 mycid,mytid, {47'h0, softint});
1699 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1700 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1701 {47'h0, softint});
1702 end // }
1703 if (!(~`SOFTINT_RDWR_5&(softint !== `RD_SOFTINT_REG_5)))
1704 softint_delta <= 1'b0;
1705 end //}
1706 else if (`SPC0.tlu.asi_wr_clear_softint[5] |
1707 `SPC0.tlu.asi_wr_set_softint[5] ) begin // {
1708 `PR_INFO ("pli_int", `INFO,
1709 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1710 mycid,mytid, {47'h0, `RD_SOFTINT_REG_5});
1711 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1712 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1713 {47'h0, `RD_SOFTINT_REG_5});
1714 end // }
1715 end //}
1716
1717
1718 softint_rdwr <= `SOFTINT_RDWR_5 ;
1719 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_5;
1720
1721
1722/////////////////////////// Softint ///////////////////////////////////// }}}
1723
1724/////////////////////////// Hintp ///////////////////////////////////// {{{
1725
1726 // Hintp Register hardware Update Detection
1727
1728 // Non software updates (HSP)
1729 // If HINTP is already read/written by SW, then don't send
1730 // any async updates to Nas. Reads/Writes pending sstep is detected
1731 // by snooping nas_pipe ..
1732
1733 hintp <= `HINTP_REG_5 ;
1734 if (hstmatch_late)
1735 hintp_delta <= 1'b1;
1736
1737 if ((~hintp_rdwr & `NAS_PIPE_FW2_5 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
1738 (hintp_rdwr_late & hintp_delta) ) begin // {
1739 `PR_INFO ("pli_int", `INFO,
1740 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
1741 mycid,mytid, {63'h0, hintp});
1742 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1743 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
1744 {63'h0, hintp});
1745 end // }
1746 if (~(hintp_rdwr_late & hintp_delta))
1747 hintp_delta <= 1'b0;
1748 end //}
1749
1750 hintp_rdwr <= `HINTP_RDWR_5;
1751 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_5;
1752 hstmatch_late <= `HSTMATCH_5;
1753
1754
1755/////////////////////////// Hintp ///////////////////////////////////// }}}
1756
1757end //}
1758`endif
1759endmodule
1760
1761// }}}
1762
1763module int_c0t6 ();
1764`ifndef GATESIM
1765
1766// common defines
1767`include "defines.vh"
1768`include "ccx.vri"
1769`include "cmp.vri"
1770
1771wire [2:0] mycid;
1772wire [2:0] mytid;
1773wire [5:0] mytnum;
1774integer junk;
1775
1776reg [63:0] int_vec_recv_reg;
1777reg int_vec_recv_reg_delta;
1778reg int_vec_reg_rdwr;
1779reg inc_vec_reg_rd;
1780reg int_vec_reg_rdwr_late;
1781reg [16:0] softint;
1782reg softint_rdwr;
1783reg softint_rdwr_late;
1784reg softint_delta;
1785reg hintp;
1786reg hintp_rdwr;
1787reg hintp_rdwr_late;
1788reg hintp_delta;
1789reg hstmatch_late;
1790reg ready;
1791reg [7:0] int_num_w;
1792reg [7:0] int_num_fx4;
1793reg [7:0] int_num_fx5;
1794reg [7:0] int_num_fb;
1795reg [7:0] int_num_fw;
1796reg [7:0] int_num_fw1;
1797reg [7:0] int_num_fw2;
1798reg take_disrupting_w;
1799reg take_disrupting_fx4;
1800reg take_disrupting_fx5;
1801reg take_disrupting_fb;
1802reg take_disrupting_fw;
1803reg take_disrupting_fw1;
1804reg take_disrupting_fw2;
1805
1806 assign mycid = 0;
1807 assign mytid = 6;
1808 assign mytnum = 0*8 + 6;
1809
1810initial begin // {
1811 ready = 0; // Wait for socket setup ..
1812 inc_vec_reg_rd <= 1'b0;
1813 int_vec_recv_reg_delta <= 1'b0;
1814 softint_delta <= 1'b0;
1815 hintp_delta <= 1'b0;
1816 int_vec_recv_reg = 64'b0;
1817 @(posedge `BENCH_SPC0_GCLK) ;
1818 @(posedge `BENCH_SPC0_GCLK) ;
1819 ready = `PARGS.int_sync_on;
1820end //}
1821
1822
1823/////////////////////////////// Probes //////////////////////////////////// {{{
1824
1825`define INT_VEC_RECV_REG_6 `SPC0.tlu.cth.int_rec6
1826`define INT_VEC_RECV_ASIWR_6 (`TOP.nas_top.c0.t6.asi_wr_int_rec_delay)
1827`define INT_VEC_RDWR_6 (`TOP.nas_top.c0.t6.asi_rdwr_int_rec)
1828`define INT_VEC_TAKEN_6 `SPC0.tlu.trl1.take_ivt&`SPC0.tlu.trl1.trap[2]
1829
1830`define CPU_MONDO_TAKEN_6 `SPC0.tlu.trl1.take_mqr&`SPC0.tlu.trl1.trap[2]
1831`define DEV_MONDO_TAKEN_6 `SPC0.tlu.trl1.take_dqr&`SPC0.tlu.trl1.trap[2]
1832`define RES_MONDO_TAKEN_6 `SPC0.tlu.trl1.take_rqr&`SPC0.tlu.trl1.trap[2]
1833
1834`define XIR_TAKEN_6 `SPC0.tlu.trl1.take_xir&`SPC0.tlu.trl1.trap[2]
1835
1836`define SOFTINT_RDWR_6 (`TOP.nas_top.c0.t6.asi_rdwr_softint|`TOP.nas_top.c0.t6.asi_wr_softint_delay)
1837
1838`define SOFTINT_REG_6 `SPC0.tlu.trl1.softint2
1839`define RD_SOFTINT_REG_6 `SPC0.tlu.trl1.rd_softint2
1840`define INT_LEVEL_TAKEN_6 `SPC0.tlu.trl1.take_iln&`SPC0.tlu.trl1.trap[2]
1841`define INT_LEVEL_NUM_6 `SPC0.tlu.trl1.int_level_n
1842`define PMU_TAKEN_6 `SPC0.tlu.trl1.take_pmu&`SPC0.tlu.trl1.trap[2]
1843
1844`define HINTP_RDWR_6 (`TOP.nas_top.c0.t6.asi_rdwr_hintp | `TOP.nas_top.c0.t6.asi_wr_hintp_delay)
1845`define HINTP_WR_6 (`SPC0.tlu.asi_wr_hintp[6])
1846`define HSTMATCH_6 `SPC0.tlu.trl1.hstick2_compare
1847
1848`define HINTP_REG_6 `SPC0.tlu.trl1.hintp2
1849`define HSTM_TAKEN_6 `SPC0.tlu.trl1.take_hst&`SPC0.tlu.trl1.trap[2]
1850
1851`define NAS_PIPE_FW2_6 |`TOP.nas_top.c0.t6.complete_fw2
1852
1853`define CWQ_TAKEN_6 `SPC0.tlu.trl1.take_cwq&`SPC0.tlu.trl1.trap[2]
1854`define SMA_TAKEN_6 `SPC0.tlu.trl1.take_sma&`SPC0.tlu.trl1.trap[2]
1855
1856`define POR_TAKEN_6 `SPC0.tlu.trl1.take_por&`SPC0.tlu.trl1.trap[2]
1857
1858/////////////////////////////// Probes //////////////////////////////////// }}}
1859
1860always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
1861
1862 // {{{ DETECT, PIPE & SEND
1863 take_disrupting_w <= (`INT_VEC_TAKEN_6 || `CPU_MONDO_TAKEN_6 ||
1864 `DEV_MONDO_TAKEN_6 || `RES_MONDO_TAKEN_6 ||
1865 `XIR_TAKEN_6 || `INT_LEVEL_TAKEN_6 ||
1866 `HSTM_TAKEN_6 || `CWQ_TAKEN_6 ||
1867 `SMA_TAKEN_6 || `PMU_TAKEN_6 || `POR_TAKEN_6);
1868 take_disrupting_fx4 <= take_disrupting_w;
1869 take_disrupting_fx5 <= take_disrupting_fx4;
1870 take_disrupting_fb <= take_disrupting_fx5;
1871 take_disrupting_fw <= take_disrupting_fb;
1872 take_disrupting_fw1 <= take_disrupting_fw;
1873 take_disrupting_fw2 <= take_disrupting_fw1;
1874
1875 case ({`INT_VEC_TAKEN_6, `CPU_MONDO_TAKEN_6,
1876 `DEV_MONDO_TAKEN_6, `RES_MONDO_TAKEN_6,
1877 `XIR_TAKEN_6, `INT_LEVEL_TAKEN_6,
1878 `HSTM_TAKEN_6, `CWQ_TAKEN_6, `SMA_TAKEN_6 ,
1879 `PMU_TAKEN_6, `POR_TAKEN_6})
1880 11'b10000000000: int_num_w <= 8'h60;
1881 11'b01000000000: int_num_w <= 8'h7c;
1882 11'b00100000000: int_num_w <= 8'h7d;
1883 11'b00010000000: int_num_w <= 8'h7e;
1884 11'b00001000000: int_num_w <= 8'h03;
1885 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_6;
1886 11'b00000010000: int_num_w <= 8'h5e;
1887 11'b00000001000: int_num_w <= 8'h3c;
1888 11'b00000000100: int_num_w <= 8'h3d;
1889 11'b00000000010: int_num_w <= 8'h4f;
1890 11'b00000000001: int_num_w <= 8'h01;
1891 endcase
1892
1893 int_num_fx4 <= int_num_w;
1894 int_num_fx5 <= int_num_fx4;
1895 int_num_fb <= int_num_fx5;
1896 int_num_fw <= int_num_fb;
1897 int_num_fw1 <= int_num_fw;
1898 int_num_fw2 <= int_num_fw1;
1899 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
1900 begin // {
1901 `PR_INFO ("pli_int", `INFO,
1902 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
1903 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
1904 end // }
1905
1906 // }}}
1907
1908/////////////////////////// Vectored Interrupt /////////////////////////// {{{
1909
1910 // Vectored Interrupt Recv Register Detection
1911 // Indicate when register changes due to arriving interrupt, and not
1912 // due to read of incoming register or ASI write ..
1913
1914
1915 // If any read occurs, send value right away.
1916 // While a read/write is pending, do not update delta.
1917 // Send non read/wr delta during fw2 ..
1918
1919
1920 if (!(`INT_VEC_RDWR_6 | `INT_VEC_RECV_ASIWR_6)) begin // {
1921 if (~`INT_VEC_RECV_ASIWR_6 &
1922 (int_vec_recv_reg !== `INT_VEC_RECV_REG_6 ))
1923 int_vec_recv_reg_delta <= 1'b1;
1924 int_vec_recv_reg <= `INT_VEC_RECV_REG_6;
1925 end // }
1926 else if (`INT_VEC_RECV_ASIWR_6)
1927 int_vec_recv_reg <= `TOP.nas_top.c0.t6.asi_updated_int_rec;
1928
1929 if ((`NAS_PIPE_FW2_6 & int_vec_recv_reg_delta ) |
1930 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
1931 `INT_VEC_RECV_ASIWR_6 ) begin // {
1932 `PR_INFO ("pli_int", `INFO,
1933 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
1934 mycid,mytid, int_vec_recv_reg);
1935 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1936 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
1937 64'h0, int_vec_recv_reg);
1938 end // }
1939 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_6 &
1940 (int_vec_recv_reg !== `INT_VEC_RECV_REG_6 ))))
1941 int_vec_recv_reg_delta <= 1'b0;
1942 end //}
1943
1944 int_vec_reg_rdwr <= `INT_VEC_RDWR_6 | `INT_VEC_RECV_ASIWR_6;
1945 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_6 & ~ inc_vec_reg_rd;
1946
1947 if (`INT_VEC_RECV_ASIWR_6)
1948 inc_vec_reg_rd <= 1'b1;
1949 if (`NAS_PIPE_FW2_6)
1950 inc_vec_reg_rd <= 1'b0;
1951
1952
1953/////////////////////////// Vectored Interrupt /////////////////////////// }}}
1954
1955/////////////////////////// Asynchronous Resets ////////////////////////// {{{
1956
1957
1958/////////////////////////// Asynchronous Resets ////////////////////////// }}}
1959
1960/////////////////////////// Softint ///////////////////////////////////// {{{
1961
1962 // Softint Register hardware Update Detection
1963
1964 // Non software updates (TM/SM)
1965
1966 // If any read occurs, send value right away.
1967 // While a read/write is pending, do not update delta.
1968 // Send non read/wr delta during fw2 ..
1969
1970 // RTL keeps pic_ovf indication in rd_softint and not softint.
1971 // So for set/clear writes, we send softint before the write ..,
1972 // and for read/asyncs we send rd_softint ..
1973
1974
1975 if (~`SOFTINT_RDWR_6) begin // {
1976 if (softint !== `RD_SOFTINT_REG_6 )
1977 softint_delta <= 1'b1;
1978 softint <= `RD_SOFTINT_REG_6;
1979 end // }
1980
1981 if ((`NAS_PIPE_FW2_6 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
1982 ) begin // {
1983 `PR_INFO ("pli_int", `INFO,
1984 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1985 mycid,mytid, {47'h0, softint});
1986 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1987 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
1988 {47'h0, softint});
1989 end // }
1990 if (!(~`SOFTINT_RDWR_6&(softint !== `RD_SOFTINT_REG_6)))
1991 softint_delta <= 1'b0;
1992 end //}
1993 else if (`SPC0.tlu.asi_wr_clear_softint[6] |
1994 `SPC0.tlu.asi_wr_set_softint[6] ) begin // {
1995 `PR_INFO ("pli_int", `INFO,
1996 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
1997 mycid,mytid, {47'h0, `RD_SOFTINT_REG_6});
1998 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
1999 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2000 {47'h0, `RD_SOFTINT_REG_6});
2001 end // }
2002 end //}
2003
2004
2005 softint_rdwr <= `SOFTINT_RDWR_6 ;
2006 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_6;
2007
2008
2009/////////////////////////// Softint ///////////////////////////////////// }}}
2010
2011/////////////////////////// Hintp ///////////////////////////////////// {{{
2012
2013 // Hintp Register hardware Update Detection
2014
2015 // Non software updates (HSP)
2016 // If HINTP is already read/written by SW, then don't send
2017 // any async updates to Nas. Reads/Writes pending sstep is detected
2018 // by snooping nas_pipe ..
2019
2020 hintp <= `HINTP_REG_6 ;
2021 if (hstmatch_late)
2022 hintp_delta <= 1'b1;
2023
2024 if ((~hintp_rdwr & `NAS_PIPE_FW2_6 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
2025 (hintp_rdwr_late & hintp_delta) ) begin // {
2026 `PR_INFO ("pli_int", `INFO,
2027 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
2028 mycid,mytid, {63'h0, hintp});
2029 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2030 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
2031 {63'h0, hintp});
2032 end // }
2033 if (~(hintp_rdwr_late & hintp_delta))
2034 hintp_delta <= 1'b0;
2035 end //}
2036
2037 hintp_rdwr <= `HINTP_RDWR_6;
2038 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_6;
2039 hstmatch_late <= `HSTMATCH_6;
2040
2041
2042/////////////////////////// Hintp ///////////////////////////////////// }}}
2043
2044end //}
2045`endif
2046endmodule
2047
2048// }}}
2049
2050module int_c0t7 ();
2051`ifndef GATESIM
2052
2053// common defines
2054`include "defines.vh"
2055`include "ccx.vri"
2056`include "cmp.vri"
2057
2058wire [2:0] mycid;
2059wire [2:0] mytid;
2060wire [5:0] mytnum;
2061integer junk;
2062
2063reg [63:0] int_vec_recv_reg;
2064reg int_vec_recv_reg_delta;
2065reg int_vec_reg_rdwr;
2066reg inc_vec_reg_rd;
2067reg int_vec_reg_rdwr_late;
2068reg [16:0] softint;
2069reg softint_rdwr;
2070reg softint_rdwr_late;
2071reg softint_delta;
2072reg hintp;
2073reg hintp_rdwr;
2074reg hintp_rdwr_late;
2075reg hintp_delta;
2076reg hstmatch_late;
2077reg ready;
2078reg [7:0] int_num_w;
2079reg [7:0] int_num_fx4;
2080reg [7:0] int_num_fx5;
2081reg [7:0] int_num_fb;
2082reg [7:0] int_num_fw;
2083reg [7:0] int_num_fw1;
2084reg [7:0] int_num_fw2;
2085reg take_disrupting_w;
2086reg take_disrupting_fx4;
2087reg take_disrupting_fx5;
2088reg take_disrupting_fb;
2089reg take_disrupting_fw;
2090reg take_disrupting_fw1;
2091reg take_disrupting_fw2;
2092
2093 assign mycid = 0;
2094 assign mytid = 7;
2095 assign mytnum = 0*8 + 7;
2096
2097initial begin // {
2098 ready = 0; // Wait for socket setup ..
2099 inc_vec_reg_rd <= 1'b0;
2100 int_vec_recv_reg_delta <= 1'b0;
2101 softint_delta <= 1'b0;
2102 hintp_delta <= 1'b0;
2103 int_vec_recv_reg = 64'b0;
2104 @(posedge `BENCH_SPC0_GCLK) ;
2105 @(posedge `BENCH_SPC0_GCLK) ;
2106 ready = `PARGS.int_sync_on;
2107end //}
2108
2109
2110/////////////////////////////// Probes //////////////////////////////////// {{{
2111
2112`define INT_VEC_RECV_REG_7 `SPC0.tlu.cth.int_rec7
2113`define INT_VEC_RECV_ASIWR_7 (`TOP.nas_top.c0.t7.asi_wr_int_rec_delay)
2114`define INT_VEC_RDWR_7 (`TOP.nas_top.c0.t7.asi_rdwr_int_rec)
2115`define INT_VEC_TAKEN_7 `SPC0.tlu.trl1.take_ivt&`SPC0.tlu.trl1.trap[3]
2116
2117`define CPU_MONDO_TAKEN_7 `SPC0.tlu.trl1.take_mqr&`SPC0.tlu.trl1.trap[3]
2118`define DEV_MONDO_TAKEN_7 `SPC0.tlu.trl1.take_dqr&`SPC0.tlu.trl1.trap[3]
2119`define RES_MONDO_TAKEN_7 `SPC0.tlu.trl1.take_rqr&`SPC0.tlu.trl1.trap[3]
2120
2121`define XIR_TAKEN_7 `SPC0.tlu.trl1.take_xir&`SPC0.tlu.trl1.trap[3]
2122
2123`define SOFTINT_RDWR_7 (`TOP.nas_top.c0.t7.asi_rdwr_softint|`TOP.nas_top.c0.t7.asi_wr_softint_delay)
2124
2125`define SOFTINT_REG_7 `SPC0.tlu.trl1.softint3
2126`define RD_SOFTINT_REG_7 `SPC0.tlu.trl1.rd_softint3
2127`define INT_LEVEL_TAKEN_7 `SPC0.tlu.trl1.take_iln&`SPC0.tlu.trl1.trap[3]
2128`define INT_LEVEL_NUM_7 `SPC0.tlu.trl1.int_level_n
2129`define PMU_TAKEN_7 `SPC0.tlu.trl1.take_pmu&`SPC0.tlu.trl1.trap[3]
2130
2131`define HINTP_RDWR_7 (`TOP.nas_top.c0.t7.asi_rdwr_hintp | `TOP.nas_top.c0.t7.asi_wr_hintp_delay)
2132`define HINTP_WR_7 (`SPC0.tlu.asi_wr_hintp[7])
2133`define HSTMATCH_7 `SPC0.tlu.trl1.hstick3_compare
2134
2135`define HINTP_REG_7 `SPC0.tlu.trl1.hintp3
2136`define HSTM_TAKEN_7 `SPC0.tlu.trl1.take_hst&`SPC0.tlu.trl1.trap[3]
2137
2138`define NAS_PIPE_FW2_7 |`TOP.nas_top.c0.t7.complete_fw2
2139
2140`define CWQ_TAKEN_7 `SPC0.tlu.trl1.take_cwq&`SPC0.tlu.trl1.trap[3]
2141`define SMA_TAKEN_7 `SPC0.tlu.trl1.take_sma&`SPC0.tlu.trl1.trap[3]
2142
2143`define POR_TAKEN_7 `SPC0.tlu.trl1.take_por&`SPC0.tlu.trl1.trap[3]
2144
2145/////////////////////////////// Probes //////////////////////////////////// }}}
2146
2147always @(negedge (`BENCH_SPC0_GCLK & ready)) begin // {
2148
2149 // {{{ DETECT, PIPE & SEND
2150 take_disrupting_w <= (`INT_VEC_TAKEN_7 || `CPU_MONDO_TAKEN_7 ||
2151 `DEV_MONDO_TAKEN_7 || `RES_MONDO_TAKEN_7 ||
2152 `XIR_TAKEN_7 || `INT_LEVEL_TAKEN_7 ||
2153 `HSTM_TAKEN_7 || `CWQ_TAKEN_7 ||
2154 `SMA_TAKEN_7 || `PMU_TAKEN_7 || `POR_TAKEN_7);
2155 take_disrupting_fx4 <= take_disrupting_w;
2156 take_disrupting_fx5 <= take_disrupting_fx4;
2157 take_disrupting_fb <= take_disrupting_fx5;
2158 take_disrupting_fw <= take_disrupting_fb;
2159 take_disrupting_fw1 <= take_disrupting_fw;
2160 take_disrupting_fw2 <= take_disrupting_fw1;
2161
2162 case ({`INT_VEC_TAKEN_7, `CPU_MONDO_TAKEN_7,
2163 `DEV_MONDO_TAKEN_7, `RES_MONDO_TAKEN_7,
2164 `XIR_TAKEN_7, `INT_LEVEL_TAKEN_7,
2165 `HSTM_TAKEN_7, `CWQ_TAKEN_7, `SMA_TAKEN_7 ,
2166 `PMU_TAKEN_7, `POR_TAKEN_7})
2167 11'b10000000000: int_num_w <= 8'h60;
2168 11'b01000000000: int_num_w <= 8'h7c;
2169 11'b00100000000: int_num_w <= 8'h7d;
2170 11'b00010000000: int_num_w <= 8'h7e;
2171 11'b00001000000: int_num_w <= 8'h03;
2172 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_7;
2173 11'b00000010000: int_num_w <= 8'h5e;
2174 11'b00000001000: int_num_w <= 8'h3c;
2175 11'b00000000100: int_num_w <= 8'h3d;
2176 11'b00000000010: int_num_w <= 8'h4f;
2177 11'b00000000001: int_num_w <= 8'h01;
2178 endcase
2179
2180 int_num_fx4 <= int_num_w;
2181 int_num_fx5 <= int_num_fx4;
2182 int_num_fb <= int_num_fx5;
2183 int_num_fw <= int_num_fb;
2184 int_num_fw1 <= int_num_fw;
2185 int_num_fw2 <= int_num_fw1;
2186 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
2187 begin // {
2188 `PR_INFO ("pli_int", `INFO,
2189 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
2190 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
2191 end // }
2192
2193 // }}}
2194
2195/////////////////////////// Vectored Interrupt /////////////////////////// {{{
2196
2197 // Vectored Interrupt Recv Register Detection
2198 // Indicate when register changes due to arriving interrupt, and not
2199 // due to read of incoming register or ASI write ..
2200
2201
2202 // If any read occurs, send value right away.
2203 // While a read/write is pending, do not update delta.
2204 // Send non read/wr delta during fw2 ..
2205
2206
2207 if (!(`INT_VEC_RDWR_7 | `INT_VEC_RECV_ASIWR_7)) begin // {
2208 if (~`INT_VEC_RECV_ASIWR_7 &
2209 (int_vec_recv_reg !== `INT_VEC_RECV_REG_7 ))
2210 int_vec_recv_reg_delta <= 1'b1;
2211 int_vec_recv_reg <= `INT_VEC_RECV_REG_7;
2212 end // }
2213 else if (`INT_VEC_RECV_ASIWR_7)
2214 int_vec_recv_reg <= `TOP.nas_top.c0.t7.asi_updated_int_rec;
2215
2216 if ((`NAS_PIPE_FW2_7 & int_vec_recv_reg_delta ) |
2217 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
2218 `INT_VEC_RECV_ASIWR_7 ) begin // {
2219 `PR_INFO ("pli_int", `INFO,
2220 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
2221 mycid,mytid, int_vec_recv_reg);
2222 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2223 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
2224 64'h0, int_vec_recv_reg);
2225 end // }
2226 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_7 &
2227 (int_vec_recv_reg !== `INT_VEC_RECV_REG_7 ))))
2228 int_vec_recv_reg_delta <= 1'b0;
2229 end //}
2230
2231 int_vec_reg_rdwr <= `INT_VEC_RDWR_7 | `INT_VEC_RECV_ASIWR_7;
2232 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_7 & ~ inc_vec_reg_rd;
2233
2234 if (`INT_VEC_RECV_ASIWR_7)
2235 inc_vec_reg_rd <= 1'b1;
2236 if (`NAS_PIPE_FW2_7)
2237 inc_vec_reg_rd <= 1'b0;
2238
2239
2240/////////////////////////// Vectored Interrupt /////////////////////////// }}}
2241
2242/////////////////////////// Asynchronous Resets ////////////////////////// {{{
2243
2244
2245/////////////////////////// Asynchronous Resets ////////////////////////// }}}
2246
2247/////////////////////////// Softint ///////////////////////////////////// {{{
2248
2249 // Softint Register hardware Update Detection
2250
2251 // Non software updates (TM/SM)
2252
2253 // If any read occurs, send value right away.
2254 // While a read/write is pending, do not update delta.
2255 // Send non read/wr delta during fw2 ..
2256
2257 // RTL keeps pic_ovf indication in rd_softint and not softint.
2258 // So for set/clear writes, we send softint before the write ..,
2259 // and for read/asyncs we send rd_softint ..
2260
2261
2262 if (~`SOFTINT_RDWR_7) begin // {
2263 if (softint !== `RD_SOFTINT_REG_7 )
2264 softint_delta <= 1'b1;
2265 softint <= `RD_SOFTINT_REG_7;
2266 end // }
2267
2268 if ((`NAS_PIPE_FW2_7 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
2269 ) begin // {
2270 `PR_INFO ("pli_int", `INFO,
2271 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
2272 mycid,mytid, {47'h0, softint});
2273 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2274 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2275 {47'h0, softint});
2276 end // }
2277 if (!(~`SOFTINT_RDWR_7&(softint !== `RD_SOFTINT_REG_7)))
2278 softint_delta <= 1'b0;
2279 end //}
2280 else if (`SPC0.tlu.asi_wr_clear_softint[7] |
2281 `SPC0.tlu.asi_wr_set_softint[7] ) begin // {
2282 `PR_INFO ("pli_int", `INFO,
2283 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
2284 mycid,mytid, {47'h0, `RD_SOFTINT_REG_7});
2285 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2286 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2287 {47'h0, `RD_SOFTINT_REG_7});
2288 end // }
2289 end //}
2290
2291
2292 softint_rdwr <= `SOFTINT_RDWR_7 ;
2293 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_7;
2294
2295
2296/////////////////////////// Softint ///////////////////////////////////// }}}
2297
2298/////////////////////////// Hintp ///////////////////////////////////// {{{
2299
2300 // Hintp Register hardware Update Detection
2301
2302 // Non software updates (HSP)
2303 // If HINTP is already read/written by SW, then don't send
2304 // any async updates to Nas. Reads/Writes pending sstep is detected
2305 // by snooping nas_pipe ..
2306
2307 hintp <= `HINTP_REG_7 ;
2308 if (hstmatch_late)
2309 hintp_delta <= 1'b1;
2310
2311 if ((~hintp_rdwr & `NAS_PIPE_FW2_7 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
2312 (hintp_rdwr_late & hintp_delta) ) begin // {
2313 `PR_INFO ("pli_int", `INFO,
2314 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
2315 mycid,mytid, {63'h0, hintp});
2316 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2317 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
2318 {63'h0, hintp});
2319 end // }
2320 if (~(hintp_rdwr_late & hintp_delta))
2321 hintp_delta <= 1'b0;
2322 end //}
2323
2324 hintp_rdwr <= `HINTP_RDWR_7;
2325 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_7;
2326 hstmatch_late <= `HSTMATCH_7;
2327
2328
2329/////////////////////////// Hintp ///////////////////////////////////// }}}
2330
2331end //}
2332`endif
2333endmodule
2334
2335`endif
2336`ifdef CORE_1
2337
2338// }}}
2339
2340module int_c1t0 ();
2341`ifndef GATESIM
2342
2343// common defines
2344`include "defines.vh"
2345`include "ccx.vri"
2346`include "cmp.vri"
2347
2348wire [2:0] mycid;
2349wire [2:0] mytid;
2350wire [5:0] mytnum;
2351integer junk;
2352
2353reg [63:0] int_vec_recv_reg;
2354reg int_vec_recv_reg_delta;
2355reg int_vec_reg_rdwr;
2356reg inc_vec_reg_rd;
2357reg int_vec_reg_rdwr_late;
2358reg [16:0] softint;
2359reg softint_rdwr;
2360reg softint_rdwr_late;
2361reg softint_delta;
2362reg hintp;
2363reg hintp_rdwr;
2364reg hintp_rdwr_late;
2365reg hintp_delta;
2366reg hstmatch_late;
2367reg ready;
2368reg [7:0] int_num_w;
2369reg [7:0] int_num_fx4;
2370reg [7:0] int_num_fx5;
2371reg [7:0] int_num_fb;
2372reg [7:0] int_num_fw;
2373reg [7:0] int_num_fw1;
2374reg [7:0] int_num_fw2;
2375reg take_disrupting_w;
2376reg take_disrupting_fx4;
2377reg take_disrupting_fx5;
2378reg take_disrupting_fb;
2379reg take_disrupting_fw;
2380reg take_disrupting_fw1;
2381reg take_disrupting_fw2;
2382
2383 assign mycid = 1;
2384 assign mytid = 0;
2385 assign mytnum = 1*8 + 0;
2386
2387initial begin // {
2388 ready = 0; // Wait for socket setup ..
2389 inc_vec_reg_rd <= 1'b0;
2390 int_vec_recv_reg_delta <= 1'b0;
2391 softint_delta <= 1'b0;
2392 hintp_delta <= 1'b0;
2393 int_vec_recv_reg = 64'b0;
2394 @(posedge `BENCH_SPC1_GCLK) ;
2395 @(posedge `BENCH_SPC1_GCLK) ;
2396 ready = `PARGS.int_sync_on;
2397end //}
2398
2399
2400/////////////////////////////// Probes //////////////////////////////////// {{{
2401
2402`define INT_VEC_RECV_REG_8 `SPC1.tlu.cth.int_rec0
2403`define INT_VEC_RECV_ASIWR_8 (`TOP.nas_top.c1.t0.asi_wr_int_rec_delay)
2404`define INT_VEC_RDWR_8 (`TOP.nas_top.c1.t0.asi_rdwr_int_rec)
2405`define INT_VEC_TAKEN_8 `SPC1.tlu.trl0.take_ivt&`SPC1.tlu.trl0.trap[0]
2406
2407`define CPU_MONDO_TAKEN_8 `SPC1.tlu.trl0.take_mqr&`SPC1.tlu.trl0.trap[0]
2408`define DEV_MONDO_TAKEN_8 `SPC1.tlu.trl0.take_dqr&`SPC1.tlu.trl0.trap[0]
2409`define RES_MONDO_TAKEN_8 `SPC1.tlu.trl0.take_rqr&`SPC1.tlu.trl0.trap[0]
2410
2411`define XIR_TAKEN_8 `SPC1.tlu.trl0.take_xir&`SPC1.tlu.trl0.trap[0]
2412
2413`define SOFTINT_RDWR_8 (`TOP.nas_top.c1.t0.asi_rdwr_softint|`TOP.nas_top.c1.t0.asi_wr_softint_delay)
2414
2415`define SOFTINT_REG_8 `SPC1.tlu.trl0.softint0
2416`define RD_SOFTINT_REG_8 `SPC1.tlu.trl0.rd_softint0
2417`define INT_LEVEL_TAKEN_8 `SPC1.tlu.trl0.take_iln&`SPC1.tlu.trl0.trap[0]
2418`define INT_LEVEL_NUM_8 `SPC1.tlu.trl0.int_level_n
2419`define PMU_TAKEN_8 `SPC1.tlu.trl0.take_pmu&`SPC1.tlu.trl0.trap[0]
2420
2421`define HINTP_RDWR_8 (`TOP.nas_top.c1.t0.asi_rdwr_hintp | `TOP.nas_top.c1.t0.asi_wr_hintp_delay)
2422`define HINTP_WR_8 (`SPC1.tlu.asi_wr_hintp[8])
2423`define HSTMATCH_8 `SPC1.tlu.trl0.hstick0_compare
2424
2425`define HINTP_REG_8 `SPC1.tlu.trl0.hintp0
2426`define HSTM_TAKEN_8 `SPC1.tlu.trl0.take_hst&`SPC1.tlu.trl0.trap[0]
2427
2428`define NAS_PIPE_FW2_8 |`TOP.nas_top.c1.t0.complete_fw2
2429
2430`define CWQ_TAKEN_8 `SPC1.tlu.trl0.take_cwq&`SPC1.tlu.trl0.trap[0]
2431`define SMA_TAKEN_8 `SPC1.tlu.trl0.take_sma&`SPC1.tlu.trl0.trap[0]
2432
2433`define POR_TAKEN_8 `SPC1.tlu.trl0.take_por&`SPC1.tlu.trl0.trap[0]
2434
2435/////////////////////////////// Probes //////////////////////////////////// }}}
2436
2437always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
2438
2439 // {{{ DETECT, PIPE & SEND
2440 take_disrupting_w <= (`INT_VEC_TAKEN_8 || `CPU_MONDO_TAKEN_8 ||
2441 `DEV_MONDO_TAKEN_8 || `RES_MONDO_TAKEN_8 ||
2442 `XIR_TAKEN_8 || `INT_LEVEL_TAKEN_8 ||
2443 `HSTM_TAKEN_8 || `CWQ_TAKEN_8 ||
2444 `SMA_TAKEN_8 || `PMU_TAKEN_8 || `POR_TAKEN_8);
2445 take_disrupting_fx4 <= take_disrupting_w;
2446 take_disrupting_fx5 <= take_disrupting_fx4;
2447 take_disrupting_fb <= take_disrupting_fx5;
2448 take_disrupting_fw <= take_disrupting_fb;
2449 take_disrupting_fw1 <= take_disrupting_fw;
2450 take_disrupting_fw2 <= take_disrupting_fw1;
2451
2452 case ({`INT_VEC_TAKEN_8, `CPU_MONDO_TAKEN_8,
2453 `DEV_MONDO_TAKEN_8, `RES_MONDO_TAKEN_8,
2454 `XIR_TAKEN_8, `INT_LEVEL_TAKEN_8,
2455 `HSTM_TAKEN_8, `CWQ_TAKEN_8, `SMA_TAKEN_8 ,
2456 `PMU_TAKEN_8, `POR_TAKEN_8})
2457 11'b10000000000: int_num_w <= 8'h60;
2458 11'b01000000000: int_num_w <= 8'h7c;
2459 11'b00100000000: int_num_w <= 8'h7d;
2460 11'b00010000000: int_num_w <= 8'h7e;
2461 11'b00001000000: int_num_w <= 8'h03;
2462 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_8;
2463 11'b00000010000: int_num_w <= 8'h5e;
2464 11'b00000001000: int_num_w <= 8'h3c;
2465 11'b00000000100: int_num_w <= 8'h3d;
2466 11'b00000000010: int_num_w <= 8'h4f;
2467 11'b00000000001: int_num_w <= 8'h01;
2468 endcase
2469
2470 int_num_fx4 <= int_num_w;
2471 int_num_fx5 <= int_num_fx4;
2472 int_num_fb <= int_num_fx5;
2473 int_num_fw <= int_num_fb;
2474 int_num_fw1 <= int_num_fw;
2475 int_num_fw2 <= int_num_fw1;
2476 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
2477 begin // {
2478 `PR_INFO ("pli_int", `INFO,
2479 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
2480 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
2481 end // }
2482
2483 // }}}
2484
2485/////////////////////////// Vectored Interrupt /////////////////////////// {{{
2486
2487 // Vectored Interrupt Recv Register Detection
2488 // Indicate when register changes due to arriving interrupt, and not
2489 // due to read of incoming register or ASI write ..
2490
2491
2492 // If any read occurs, send value right away.
2493 // While a read/write is pending, do not update delta.
2494 // Send non read/wr delta during fw2 ..
2495
2496
2497 if (!(`INT_VEC_RDWR_8 | `INT_VEC_RECV_ASIWR_8)) begin // {
2498 if (~`INT_VEC_RECV_ASIWR_8 &
2499 (int_vec_recv_reg !== `INT_VEC_RECV_REG_8 ))
2500 int_vec_recv_reg_delta <= 1'b1;
2501 int_vec_recv_reg <= `INT_VEC_RECV_REG_8;
2502 end // }
2503 else if (`INT_VEC_RECV_ASIWR_8)
2504 int_vec_recv_reg <= `TOP.nas_top.c1.t0.asi_updated_int_rec;
2505
2506 if ((`NAS_PIPE_FW2_8 & int_vec_recv_reg_delta ) |
2507 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
2508 `INT_VEC_RECV_ASIWR_8 ) begin // {
2509 `PR_INFO ("pli_int", `INFO,
2510 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
2511 mycid,mytid, int_vec_recv_reg);
2512 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2513 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
2514 64'h0, int_vec_recv_reg);
2515 end // }
2516 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_8 &
2517 (int_vec_recv_reg !== `INT_VEC_RECV_REG_8 ))))
2518 int_vec_recv_reg_delta <= 1'b0;
2519 end //}
2520
2521 int_vec_reg_rdwr <= `INT_VEC_RDWR_8 | `INT_VEC_RECV_ASIWR_8;
2522 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_8 & ~ inc_vec_reg_rd;
2523
2524 if (`INT_VEC_RECV_ASIWR_8)
2525 inc_vec_reg_rd <= 1'b1;
2526 if (`NAS_PIPE_FW2_8)
2527 inc_vec_reg_rd <= 1'b0;
2528
2529
2530/////////////////////////// Vectored Interrupt /////////////////////////// }}}
2531
2532/////////////////////////// Asynchronous Resets ////////////////////////// {{{
2533
2534
2535/////////////////////////// Asynchronous Resets ////////////////////////// }}}
2536
2537/////////////////////////// Softint ///////////////////////////////////// {{{
2538
2539 // Softint Register hardware Update Detection
2540
2541 // Non software updates (TM/SM)
2542
2543 // If any read occurs, send value right away.
2544 // While a read/write is pending, do not update delta.
2545 // Send non read/wr delta during fw2 ..
2546
2547 // RTL keeps pic_ovf indication in rd_softint and not softint.
2548 // So for set/clear writes, we send softint before the write ..,
2549 // and for read/asyncs we send rd_softint ..
2550
2551
2552 if (~`SOFTINT_RDWR_8) begin // {
2553 if (softint !== `RD_SOFTINT_REG_8 )
2554 softint_delta <= 1'b1;
2555 softint <= `RD_SOFTINT_REG_8;
2556 end // }
2557
2558 if ((`NAS_PIPE_FW2_8 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
2559 ) begin // {
2560 `PR_INFO ("pli_int", `INFO,
2561 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
2562 mycid,mytid, {47'h0, softint});
2563 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2564 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2565 {47'h0, softint});
2566 end // }
2567 if (!(~`SOFTINT_RDWR_8&(softint !== `RD_SOFTINT_REG_8)))
2568 softint_delta <= 1'b0;
2569 end //}
2570 else if (`SPC1.tlu.asi_wr_clear_softint[0] |
2571 `SPC1.tlu.asi_wr_set_softint[0] ) begin // {
2572 `PR_INFO ("pli_int", `INFO,
2573 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
2574 mycid,mytid, {47'h0, `RD_SOFTINT_REG_8});
2575 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2576 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2577 {47'h0, `RD_SOFTINT_REG_8});
2578 end // }
2579 end //}
2580
2581
2582 softint_rdwr <= `SOFTINT_RDWR_8 ;
2583 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_8;
2584
2585
2586/////////////////////////// Softint ///////////////////////////////////// }}}
2587
2588/////////////////////////// Hintp ///////////////////////////////////// {{{
2589
2590 // Hintp Register hardware Update Detection
2591
2592 // Non software updates (HSP)
2593 // If HINTP is already read/written by SW, then don't send
2594 // any async updates to Nas. Reads/Writes pending sstep is detected
2595 // by snooping nas_pipe ..
2596
2597 hintp <= `HINTP_REG_8 ;
2598 if (hstmatch_late)
2599 hintp_delta <= 1'b1;
2600
2601 if ((~hintp_rdwr & `NAS_PIPE_FW2_8 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
2602 (hintp_rdwr_late & hintp_delta) ) begin // {
2603 `PR_INFO ("pli_int", `INFO,
2604 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
2605 mycid,mytid, {63'h0, hintp});
2606 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2607 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
2608 {63'h0, hintp});
2609 end // }
2610 if (~(hintp_rdwr_late & hintp_delta))
2611 hintp_delta <= 1'b0;
2612 end //}
2613
2614 hintp_rdwr <= `HINTP_RDWR_8;
2615 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_8;
2616 hstmatch_late <= `HSTMATCH_8;
2617
2618
2619/////////////////////////// Hintp ///////////////////////////////////// }}}
2620
2621end //}
2622`endif
2623endmodule
2624
2625// }}}
2626
2627module int_c1t1 ();
2628`ifndef GATESIM
2629
2630// common defines
2631`include "defines.vh"
2632`include "ccx.vri"
2633`include "cmp.vri"
2634
2635wire [2:0] mycid;
2636wire [2:0] mytid;
2637wire [5:0] mytnum;
2638integer junk;
2639
2640reg [63:0] int_vec_recv_reg;
2641reg int_vec_recv_reg_delta;
2642reg int_vec_reg_rdwr;
2643reg inc_vec_reg_rd;
2644reg int_vec_reg_rdwr_late;
2645reg [16:0] softint;
2646reg softint_rdwr;
2647reg softint_rdwr_late;
2648reg softint_delta;
2649reg hintp;
2650reg hintp_rdwr;
2651reg hintp_rdwr_late;
2652reg hintp_delta;
2653reg hstmatch_late;
2654reg ready;
2655reg [7:0] int_num_w;
2656reg [7:0] int_num_fx4;
2657reg [7:0] int_num_fx5;
2658reg [7:0] int_num_fb;
2659reg [7:0] int_num_fw;
2660reg [7:0] int_num_fw1;
2661reg [7:0] int_num_fw2;
2662reg take_disrupting_w;
2663reg take_disrupting_fx4;
2664reg take_disrupting_fx5;
2665reg take_disrupting_fb;
2666reg take_disrupting_fw;
2667reg take_disrupting_fw1;
2668reg take_disrupting_fw2;
2669
2670 assign mycid = 1;
2671 assign mytid = 1;
2672 assign mytnum = 1*8 + 1;
2673
2674initial begin // {
2675 ready = 0; // Wait for socket setup ..
2676 inc_vec_reg_rd <= 1'b0;
2677 int_vec_recv_reg_delta <= 1'b0;
2678 softint_delta <= 1'b0;
2679 hintp_delta <= 1'b0;
2680 int_vec_recv_reg = 64'b0;
2681 @(posedge `BENCH_SPC1_GCLK) ;
2682 @(posedge `BENCH_SPC1_GCLK) ;
2683 ready = `PARGS.int_sync_on;
2684end //}
2685
2686
2687/////////////////////////////// Probes //////////////////////////////////// {{{
2688
2689`define INT_VEC_RECV_REG_9 `SPC1.tlu.cth.int_rec1
2690`define INT_VEC_RECV_ASIWR_9 (`TOP.nas_top.c1.t1.asi_wr_int_rec_delay)
2691`define INT_VEC_RDWR_9 (`TOP.nas_top.c1.t1.asi_rdwr_int_rec)
2692`define INT_VEC_TAKEN_9 `SPC1.tlu.trl0.take_ivt&`SPC1.tlu.trl0.trap[1]
2693
2694`define CPU_MONDO_TAKEN_9 `SPC1.tlu.trl0.take_mqr&`SPC1.tlu.trl0.trap[1]
2695`define DEV_MONDO_TAKEN_9 `SPC1.tlu.trl0.take_dqr&`SPC1.tlu.trl0.trap[1]
2696`define RES_MONDO_TAKEN_9 `SPC1.tlu.trl0.take_rqr&`SPC1.tlu.trl0.trap[1]
2697
2698`define XIR_TAKEN_9 `SPC1.tlu.trl0.take_xir&`SPC1.tlu.trl0.trap[1]
2699
2700`define SOFTINT_RDWR_9 (`TOP.nas_top.c1.t1.asi_rdwr_softint|`TOP.nas_top.c1.t1.asi_wr_softint_delay)
2701
2702`define SOFTINT_REG_9 `SPC1.tlu.trl0.softint1
2703`define RD_SOFTINT_REG_9 `SPC1.tlu.trl0.rd_softint1
2704`define INT_LEVEL_TAKEN_9 `SPC1.tlu.trl0.take_iln&`SPC1.tlu.trl0.trap[1]
2705`define INT_LEVEL_NUM_9 `SPC1.tlu.trl0.int_level_n
2706`define PMU_TAKEN_9 `SPC1.tlu.trl0.take_pmu&`SPC1.tlu.trl0.trap[1]
2707
2708`define HINTP_RDWR_9 (`TOP.nas_top.c1.t1.asi_rdwr_hintp | `TOP.nas_top.c1.t1.asi_wr_hintp_delay)
2709`define HINTP_WR_9 (`SPC1.tlu.asi_wr_hintp[9])
2710`define HSTMATCH_9 `SPC1.tlu.trl0.hstick1_compare
2711
2712`define HINTP_REG_9 `SPC1.tlu.trl0.hintp1
2713`define HSTM_TAKEN_9 `SPC1.tlu.trl0.take_hst&`SPC1.tlu.trl0.trap[1]
2714
2715`define NAS_PIPE_FW2_9 |`TOP.nas_top.c1.t1.complete_fw2
2716
2717`define CWQ_TAKEN_9 `SPC1.tlu.trl0.take_cwq&`SPC1.tlu.trl0.trap[1]
2718`define SMA_TAKEN_9 `SPC1.tlu.trl0.take_sma&`SPC1.tlu.trl0.trap[1]
2719
2720`define POR_TAKEN_9 `SPC1.tlu.trl0.take_por&`SPC1.tlu.trl0.trap[1]
2721
2722/////////////////////////////// Probes //////////////////////////////////// }}}
2723
2724always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
2725
2726 // {{{ DETECT, PIPE & SEND
2727 take_disrupting_w <= (`INT_VEC_TAKEN_9 || `CPU_MONDO_TAKEN_9 ||
2728 `DEV_MONDO_TAKEN_9 || `RES_MONDO_TAKEN_9 ||
2729 `XIR_TAKEN_9 || `INT_LEVEL_TAKEN_9 ||
2730 `HSTM_TAKEN_9 || `CWQ_TAKEN_9 ||
2731 `SMA_TAKEN_9 || `PMU_TAKEN_9 || `POR_TAKEN_9);
2732 take_disrupting_fx4 <= take_disrupting_w;
2733 take_disrupting_fx5 <= take_disrupting_fx4;
2734 take_disrupting_fb <= take_disrupting_fx5;
2735 take_disrupting_fw <= take_disrupting_fb;
2736 take_disrupting_fw1 <= take_disrupting_fw;
2737 take_disrupting_fw2 <= take_disrupting_fw1;
2738
2739 case ({`INT_VEC_TAKEN_9, `CPU_MONDO_TAKEN_9,
2740 `DEV_MONDO_TAKEN_9, `RES_MONDO_TAKEN_9,
2741 `XIR_TAKEN_9, `INT_LEVEL_TAKEN_9,
2742 `HSTM_TAKEN_9, `CWQ_TAKEN_9, `SMA_TAKEN_9 ,
2743 `PMU_TAKEN_9, `POR_TAKEN_9})
2744 11'b10000000000: int_num_w <= 8'h60;
2745 11'b01000000000: int_num_w <= 8'h7c;
2746 11'b00100000000: int_num_w <= 8'h7d;
2747 11'b00010000000: int_num_w <= 8'h7e;
2748 11'b00001000000: int_num_w <= 8'h03;
2749 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_9;
2750 11'b00000010000: int_num_w <= 8'h5e;
2751 11'b00000001000: int_num_w <= 8'h3c;
2752 11'b00000000100: int_num_w <= 8'h3d;
2753 11'b00000000010: int_num_w <= 8'h4f;
2754 11'b00000000001: int_num_w <= 8'h01;
2755 endcase
2756
2757 int_num_fx4 <= int_num_w;
2758 int_num_fx5 <= int_num_fx4;
2759 int_num_fb <= int_num_fx5;
2760 int_num_fw <= int_num_fb;
2761 int_num_fw1 <= int_num_fw;
2762 int_num_fw2 <= int_num_fw1;
2763 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
2764 begin // {
2765 `PR_INFO ("pli_int", `INFO,
2766 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
2767 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
2768 end // }
2769
2770 // }}}
2771
2772/////////////////////////// Vectored Interrupt /////////////////////////// {{{
2773
2774 // Vectored Interrupt Recv Register Detection
2775 // Indicate when register changes due to arriving interrupt, and not
2776 // due to read of incoming register or ASI write ..
2777
2778
2779 // If any read occurs, send value right away.
2780 // While a read/write is pending, do not update delta.
2781 // Send non read/wr delta during fw2 ..
2782
2783
2784 if (!(`INT_VEC_RDWR_9 | `INT_VEC_RECV_ASIWR_9)) begin // {
2785 if (~`INT_VEC_RECV_ASIWR_9 &
2786 (int_vec_recv_reg !== `INT_VEC_RECV_REG_9 ))
2787 int_vec_recv_reg_delta <= 1'b1;
2788 int_vec_recv_reg <= `INT_VEC_RECV_REG_9;
2789 end // }
2790 else if (`INT_VEC_RECV_ASIWR_9)
2791 int_vec_recv_reg <= `TOP.nas_top.c1.t1.asi_updated_int_rec;
2792
2793 if ((`NAS_PIPE_FW2_9 & int_vec_recv_reg_delta ) |
2794 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
2795 `INT_VEC_RECV_ASIWR_9 ) begin // {
2796 `PR_INFO ("pli_int", `INFO,
2797 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
2798 mycid,mytid, int_vec_recv_reg);
2799 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2800 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
2801 64'h0, int_vec_recv_reg);
2802 end // }
2803 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_9 &
2804 (int_vec_recv_reg !== `INT_VEC_RECV_REG_9 ))))
2805 int_vec_recv_reg_delta <= 1'b0;
2806 end //}
2807
2808 int_vec_reg_rdwr <= `INT_VEC_RDWR_9 | `INT_VEC_RECV_ASIWR_9;
2809 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_9 & ~ inc_vec_reg_rd;
2810
2811 if (`INT_VEC_RECV_ASIWR_9)
2812 inc_vec_reg_rd <= 1'b1;
2813 if (`NAS_PIPE_FW2_9)
2814 inc_vec_reg_rd <= 1'b0;
2815
2816
2817/////////////////////////// Vectored Interrupt /////////////////////////// }}}
2818
2819/////////////////////////// Asynchronous Resets ////////////////////////// {{{
2820
2821
2822/////////////////////////// Asynchronous Resets ////////////////////////// }}}
2823
2824/////////////////////////// Softint ///////////////////////////////////// {{{
2825
2826 // Softint Register hardware Update Detection
2827
2828 // Non software updates (TM/SM)
2829
2830 // If any read occurs, send value right away.
2831 // While a read/write is pending, do not update delta.
2832 // Send non read/wr delta during fw2 ..
2833
2834 // RTL keeps pic_ovf indication in rd_softint and not softint.
2835 // So for set/clear writes, we send softint before the write ..,
2836 // and for read/asyncs we send rd_softint ..
2837
2838
2839 if (~`SOFTINT_RDWR_9) begin // {
2840 if (softint !== `RD_SOFTINT_REG_9 )
2841 softint_delta <= 1'b1;
2842 softint <= `RD_SOFTINT_REG_9;
2843 end // }
2844
2845 if ((`NAS_PIPE_FW2_9 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
2846 ) begin // {
2847 `PR_INFO ("pli_int", `INFO,
2848 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
2849 mycid,mytid, {47'h0, softint});
2850 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2851 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2852 {47'h0, softint});
2853 end // }
2854 if (!(~`SOFTINT_RDWR_9&(softint !== `RD_SOFTINT_REG_9)))
2855 softint_delta <= 1'b0;
2856 end //}
2857 else if (`SPC1.tlu.asi_wr_clear_softint[1] |
2858 `SPC1.tlu.asi_wr_set_softint[1] ) begin // {
2859 `PR_INFO ("pli_int", `INFO,
2860 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
2861 mycid,mytid, {47'h0, `RD_SOFTINT_REG_9});
2862 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2863 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
2864 {47'h0, `RD_SOFTINT_REG_9});
2865 end // }
2866 end //}
2867
2868
2869 softint_rdwr <= `SOFTINT_RDWR_9 ;
2870 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_9;
2871
2872
2873/////////////////////////// Softint ///////////////////////////////////// }}}
2874
2875/////////////////////////// Hintp ///////////////////////////////////// {{{
2876
2877 // Hintp Register hardware Update Detection
2878
2879 // Non software updates (HSP)
2880 // If HINTP is already read/written by SW, then don't send
2881 // any async updates to Nas. Reads/Writes pending sstep is detected
2882 // by snooping nas_pipe ..
2883
2884 hintp <= `HINTP_REG_9 ;
2885 if (hstmatch_late)
2886 hintp_delta <= 1'b1;
2887
2888 if ((~hintp_rdwr & `NAS_PIPE_FW2_9 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
2889 (hintp_rdwr_late & hintp_delta) ) begin // {
2890 `PR_INFO ("pli_int", `INFO,
2891 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
2892 mycid,mytid, {63'h0, hintp});
2893 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
2894 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
2895 {63'h0, hintp});
2896 end // }
2897 if (~(hintp_rdwr_late & hintp_delta))
2898 hintp_delta <= 1'b0;
2899 end //}
2900
2901 hintp_rdwr <= `HINTP_RDWR_9;
2902 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_9;
2903 hstmatch_late <= `HSTMATCH_9;
2904
2905
2906/////////////////////////// Hintp ///////////////////////////////////// }}}
2907
2908end //}
2909`endif
2910endmodule
2911
2912// }}}
2913
2914module int_c1t2 ();
2915`ifndef GATESIM
2916
2917// common defines
2918`include "defines.vh"
2919`include "ccx.vri"
2920`include "cmp.vri"
2921
2922wire [2:0] mycid;
2923wire [2:0] mytid;
2924wire [5:0] mytnum;
2925integer junk;
2926
2927reg [63:0] int_vec_recv_reg;
2928reg int_vec_recv_reg_delta;
2929reg int_vec_reg_rdwr;
2930reg inc_vec_reg_rd;
2931reg int_vec_reg_rdwr_late;
2932reg [16:0] softint;
2933reg softint_rdwr;
2934reg softint_rdwr_late;
2935reg softint_delta;
2936reg hintp;
2937reg hintp_rdwr;
2938reg hintp_rdwr_late;
2939reg hintp_delta;
2940reg hstmatch_late;
2941reg ready;
2942reg [7:0] int_num_w;
2943reg [7:0] int_num_fx4;
2944reg [7:0] int_num_fx5;
2945reg [7:0] int_num_fb;
2946reg [7:0] int_num_fw;
2947reg [7:0] int_num_fw1;
2948reg [7:0] int_num_fw2;
2949reg take_disrupting_w;
2950reg take_disrupting_fx4;
2951reg take_disrupting_fx5;
2952reg take_disrupting_fb;
2953reg take_disrupting_fw;
2954reg take_disrupting_fw1;
2955reg take_disrupting_fw2;
2956
2957 assign mycid = 1;
2958 assign mytid = 2;
2959 assign mytnum = 1*8 + 2;
2960
2961initial begin // {
2962 ready = 0; // Wait for socket setup ..
2963 inc_vec_reg_rd <= 1'b0;
2964 int_vec_recv_reg_delta <= 1'b0;
2965 softint_delta <= 1'b0;
2966 hintp_delta <= 1'b0;
2967 int_vec_recv_reg = 64'b0;
2968 @(posedge `BENCH_SPC1_GCLK) ;
2969 @(posedge `BENCH_SPC1_GCLK) ;
2970 ready = `PARGS.int_sync_on;
2971end //}
2972
2973
2974/////////////////////////////// Probes //////////////////////////////////// {{{
2975
2976`define INT_VEC_RECV_REG_10 `SPC1.tlu.cth.int_rec2
2977`define INT_VEC_RECV_ASIWR_10 (`TOP.nas_top.c1.t2.asi_wr_int_rec_delay)
2978`define INT_VEC_RDWR_10 (`TOP.nas_top.c1.t2.asi_rdwr_int_rec)
2979`define INT_VEC_TAKEN_10 `SPC1.tlu.trl0.take_ivt&`SPC1.tlu.trl0.trap[2]
2980
2981`define CPU_MONDO_TAKEN_10 `SPC1.tlu.trl0.take_mqr&`SPC1.tlu.trl0.trap[2]
2982`define DEV_MONDO_TAKEN_10 `SPC1.tlu.trl0.take_dqr&`SPC1.tlu.trl0.trap[2]
2983`define RES_MONDO_TAKEN_10 `SPC1.tlu.trl0.take_rqr&`SPC1.tlu.trl0.trap[2]
2984
2985`define XIR_TAKEN_10 `SPC1.tlu.trl0.take_xir&`SPC1.tlu.trl0.trap[2]
2986
2987`define SOFTINT_RDWR_10 (`TOP.nas_top.c1.t2.asi_rdwr_softint|`TOP.nas_top.c1.t2.asi_wr_softint_delay)
2988
2989`define SOFTINT_REG_10 `SPC1.tlu.trl0.softint2
2990`define RD_SOFTINT_REG_10 `SPC1.tlu.trl0.rd_softint2
2991`define INT_LEVEL_TAKEN_10 `SPC1.tlu.trl0.take_iln&`SPC1.tlu.trl0.trap[2]
2992`define INT_LEVEL_NUM_10 `SPC1.tlu.trl0.int_level_n
2993`define PMU_TAKEN_10 `SPC1.tlu.trl0.take_pmu&`SPC1.tlu.trl0.trap[2]
2994
2995`define HINTP_RDWR_10 (`TOP.nas_top.c1.t2.asi_rdwr_hintp | `TOP.nas_top.c1.t2.asi_wr_hintp_delay)
2996`define HINTP_WR_10 (`SPC1.tlu.asi_wr_hintp[10])
2997`define HSTMATCH_10 `SPC1.tlu.trl0.hstick2_compare
2998
2999`define HINTP_REG_10 `SPC1.tlu.trl0.hintp2
3000`define HSTM_TAKEN_10 `SPC1.tlu.trl0.take_hst&`SPC1.tlu.trl0.trap[2]
3001
3002`define NAS_PIPE_FW2_10 |`TOP.nas_top.c1.t2.complete_fw2
3003
3004`define CWQ_TAKEN_10 `SPC1.tlu.trl0.take_cwq&`SPC1.tlu.trl0.trap[2]
3005`define SMA_TAKEN_10 `SPC1.tlu.trl0.take_sma&`SPC1.tlu.trl0.trap[2]
3006
3007`define POR_TAKEN_10 `SPC1.tlu.trl0.take_por&`SPC1.tlu.trl0.trap[2]
3008
3009/////////////////////////////// Probes //////////////////////////////////// }}}
3010
3011always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
3012
3013 // {{{ DETECT, PIPE & SEND
3014 take_disrupting_w <= (`INT_VEC_TAKEN_10 || `CPU_MONDO_TAKEN_10 ||
3015 `DEV_MONDO_TAKEN_10 || `RES_MONDO_TAKEN_10 ||
3016 `XIR_TAKEN_10 || `INT_LEVEL_TAKEN_10 ||
3017 `HSTM_TAKEN_10 || `CWQ_TAKEN_10 ||
3018 `SMA_TAKEN_10 || `PMU_TAKEN_10 || `POR_TAKEN_10);
3019 take_disrupting_fx4 <= take_disrupting_w;
3020 take_disrupting_fx5 <= take_disrupting_fx4;
3021 take_disrupting_fb <= take_disrupting_fx5;
3022 take_disrupting_fw <= take_disrupting_fb;
3023 take_disrupting_fw1 <= take_disrupting_fw;
3024 take_disrupting_fw2 <= take_disrupting_fw1;
3025
3026 case ({`INT_VEC_TAKEN_10, `CPU_MONDO_TAKEN_10,
3027 `DEV_MONDO_TAKEN_10, `RES_MONDO_TAKEN_10,
3028 `XIR_TAKEN_10, `INT_LEVEL_TAKEN_10,
3029 `HSTM_TAKEN_10, `CWQ_TAKEN_10, `SMA_TAKEN_10 ,
3030 `PMU_TAKEN_10, `POR_TAKEN_10})
3031 11'b10000000000: int_num_w <= 8'h60;
3032 11'b01000000000: int_num_w <= 8'h7c;
3033 11'b00100000000: int_num_w <= 8'h7d;
3034 11'b00010000000: int_num_w <= 8'h7e;
3035 11'b00001000000: int_num_w <= 8'h03;
3036 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_10;
3037 11'b00000010000: int_num_w <= 8'h5e;
3038 11'b00000001000: int_num_w <= 8'h3c;
3039 11'b00000000100: int_num_w <= 8'h3d;
3040 11'b00000000010: int_num_w <= 8'h4f;
3041 11'b00000000001: int_num_w <= 8'h01;
3042 endcase
3043
3044 int_num_fx4 <= int_num_w;
3045 int_num_fx5 <= int_num_fx4;
3046 int_num_fb <= int_num_fx5;
3047 int_num_fw <= int_num_fb;
3048 int_num_fw1 <= int_num_fw;
3049 int_num_fw2 <= int_num_fw1;
3050 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
3051 begin // {
3052 `PR_INFO ("pli_int", `INFO,
3053 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
3054 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3055 end // }
3056
3057 // }}}
3058
3059/////////////////////////// Vectored Interrupt /////////////////////////// {{{
3060
3061 // Vectored Interrupt Recv Register Detection
3062 // Indicate when register changes due to arriving interrupt, and not
3063 // due to read of incoming register or ASI write ..
3064
3065
3066 // If any read occurs, send value right away.
3067 // While a read/write is pending, do not update delta.
3068 // Send non read/wr delta during fw2 ..
3069
3070
3071 if (!(`INT_VEC_RDWR_10 | `INT_VEC_RECV_ASIWR_10)) begin // {
3072 if (~`INT_VEC_RECV_ASIWR_10 &
3073 (int_vec_recv_reg !== `INT_VEC_RECV_REG_10 ))
3074 int_vec_recv_reg_delta <= 1'b1;
3075 int_vec_recv_reg <= `INT_VEC_RECV_REG_10;
3076 end // }
3077 else if (`INT_VEC_RECV_ASIWR_10)
3078 int_vec_recv_reg <= `TOP.nas_top.c1.t2.asi_updated_int_rec;
3079
3080 if ((`NAS_PIPE_FW2_10 & int_vec_recv_reg_delta ) |
3081 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
3082 `INT_VEC_RECV_ASIWR_10 ) begin // {
3083 `PR_INFO ("pli_int", `INFO,
3084 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
3085 mycid,mytid, int_vec_recv_reg);
3086 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3087 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
3088 64'h0, int_vec_recv_reg);
3089 end // }
3090 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_10 &
3091 (int_vec_recv_reg !== `INT_VEC_RECV_REG_10 ))))
3092 int_vec_recv_reg_delta <= 1'b0;
3093 end //}
3094
3095 int_vec_reg_rdwr <= `INT_VEC_RDWR_10 | `INT_VEC_RECV_ASIWR_10;
3096 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_10 & ~ inc_vec_reg_rd;
3097
3098 if (`INT_VEC_RECV_ASIWR_10)
3099 inc_vec_reg_rd <= 1'b1;
3100 if (`NAS_PIPE_FW2_10)
3101 inc_vec_reg_rd <= 1'b0;
3102
3103
3104/////////////////////////// Vectored Interrupt /////////////////////////// }}}
3105
3106/////////////////////////// Asynchronous Resets ////////////////////////// {{{
3107
3108
3109/////////////////////////// Asynchronous Resets ////////////////////////// }}}
3110
3111/////////////////////////// Softint ///////////////////////////////////// {{{
3112
3113 // Softint Register hardware Update Detection
3114
3115 // Non software updates (TM/SM)
3116
3117 // If any read occurs, send value right away.
3118 // While a read/write is pending, do not update delta.
3119 // Send non read/wr delta during fw2 ..
3120
3121 // RTL keeps pic_ovf indication in rd_softint and not softint.
3122 // So for set/clear writes, we send softint before the write ..,
3123 // and for read/asyncs we send rd_softint ..
3124
3125
3126 if (~`SOFTINT_RDWR_10) begin // {
3127 if (softint !== `RD_SOFTINT_REG_10 )
3128 softint_delta <= 1'b1;
3129 softint <= `RD_SOFTINT_REG_10;
3130 end // }
3131
3132 if ((`NAS_PIPE_FW2_10 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
3133 ) begin // {
3134 `PR_INFO ("pli_int", `INFO,
3135 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3136 mycid,mytid, {47'h0, softint});
3137 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3138 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
3139 {47'h0, softint});
3140 end // }
3141 if (!(~`SOFTINT_RDWR_10&(softint !== `RD_SOFTINT_REG_10)))
3142 softint_delta <= 1'b0;
3143 end //}
3144 else if (`SPC1.tlu.asi_wr_clear_softint[2] |
3145 `SPC1.tlu.asi_wr_set_softint[2] ) begin // {
3146 `PR_INFO ("pli_int", `INFO,
3147 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3148 mycid,mytid, {47'h0, `RD_SOFTINT_REG_10});
3149 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3150 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
3151 {47'h0, `RD_SOFTINT_REG_10});
3152 end // }
3153 end //}
3154
3155
3156 softint_rdwr <= `SOFTINT_RDWR_10 ;
3157 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_10;
3158
3159
3160/////////////////////////// Softint ///////////////////////////////////// }}}
3161
3162/////////////////////////// Hintp ///////////////////////////////////// {{{
3163
3164 // Hintp Register hardware Update Detection
3165
3166 // Non software updates (HSP)
3167 // If HINTP is already read/written by SW, then don't send
3168 // any async updates to Nas. Reads/Writes pending sstep is detected
3169 // by snooping nas_pipe ..
3170
3171 hintp <= `HINTP_REG_10 ;
3172 if (hstmatch_late)
3173 hintp_delta <= 1'b1;
3174
3175 if ((~hintp_rdwr & `NAS_PIPE_FW2_10 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
3176 (hintp_rdwr_late & hintp_delta) ) begin // {
3177 `PR_INFO ("pli_int", `INFO,
3178 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
3179 mycid,mytid, {63'h0, hintp});
3180 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3181 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
3182 {63'h0, hintp});
3183 end // }
3184 if (~(hintp_rdwr_late & hintp_delta))
3185 hintp_delta <= 1'b0;
3186 end //}
3187
3188 hintp_rdwr <= `HINTP_RDWR_10;
3189 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_10;
3190 hstmatch_late <= `HSTMATCH_10;
3191
3192
3193/////////////////////////// Hintp ///////////////////////////////////// }}}
3194
3195end //}
3196`endif
3197endmodule
3198
3199// }}}
3200
3201module int_c1t3 ();
3202`ifndef GATESIM
3203
3204// common defines
3205`include "defines.vh"
3206`include "ccx.vri"
3207`include "cmp.vri"
3208
3209wire [2:0] mycid;
3210wire [2:0] mytid;
3211wire [5:0] mytnum;
3212integer junk;
3213
3214reg [63:0] int_vec_recv_reg;
3215reg int_vec_recv_reg_delta;
3216reg int_vec_reg_rdwr;
3217reg inc_vec_reg_rd;
3218reg int_vec_reg_rdwr_late;
3219reg [16:0] softint;
3220reg softint_rdwr;
3221reg softint_rdwr_late;
3222reg softint_delta;
3223reg hintp;
3224reg hintp_rdwr;
3225reg hintp_rdwr_late;
3226reg hintp_delta;
3227reg hstmatch_late;
3228reg ready;
3229reg [7:0] int_num_w;
3230reg [7:0] int_num_fx4;
3231reg [7:0] int_num_fx5;
3232reg [7:0] int_num_fb;
3233reg [7:0] int_num_fw;
3234reg [7:0] int_num_fw1;
3235reg [7:0] int_num_fw2;
3236reg take_disrupting_w;
3237reg take_disrupting_fx4;
3238reg take_disrupting_fx5;
3239reg take_disrupting_fb;
3240reg take_disrupting_fw;
3241reg take_disrupting_fw1;
3242reg take_disrupting_fw2;
3243
3244 assign mycid = 1;
3245 assign mytid = 3;
3246 assign mytnum = 1*8 + 3;
3247
3248initial begin // {
3249 ready = 0; // Wait for socket setup ..
3250 inc_vec_reg_rd <= 1'b0;
3251 int_vec_recv_reg_delta <= 1'b0;
3252 softint_delta <= 1'b0;
3253 hintp_delta <= 1'b0;
3254 int_vec_recv_reg = 64'b0;
3255 @(posedge `BENCH_SPC1_GCLK) ;
3256 @(posedge `BENCH_SPC1_GCLK) ;
3257 ready = `PARGS.int_sync_on;
3258end //}
3259
3260
3261/////////////////////////////// Probes //////////////////////////////////// {{{
3262
3263`define INT_VEC_RECV_REG_11 `SPC1.tlu.cth.int_rec3
3264`define INT_VEC_RECV_ASIWR_11 (`TOP.nas_top.c1.t3.asi_wr_int_rec_delay)
3265`define INT_VEC_RDWR_11 (`TOP.nas_top.c1.t3.asi_rdwr_int_rec)
3266`define INT_VEC_TAKEN_11 `SPC1.tlu.trl0.take_ivt&`SPC1.tlu.trl0.trap[3]
3267
3268`define CPU_MONDO_TAKEN_11 `SPC1.tlu.trl0.take_mqr&`SPC1.tlu.trl0.trap[3]
3269`define DEV_MONDO_TAKEN_11 `SPC1.tlu.trl0.take_dqr&`SPC1.tlu.trl0.trap[3]
3270`define RES_MONDO_TAKEN_11 `SPC1.tlu.trl0.take_rqr&`SPC1.tlu.trl0.trap[3]
3271
3272`define XIR_TAKEN_11 `SPC1.tlu.trl0.take_xir&`SPC1.tlu.trl0.trap[3]
3273
3274`define SOFTINT_RDWR_11 (`TOP.nas_top.c1.t3.asi_rdwr_softint|`TOP.nas_top.c1.t3.asi_wr_softint_delay)
3275
3276`define SOFTINT_REG_11 `SPC1.tlu.trl0.softint3
3277`define RD_SOFTINT_REG_11 `SPC1.tlu.trl0.rd_softint3
3278`define INT_LEVEL_TAKEN_11 `SPC1.tlu.trl0.take_iln&`SPC1.tlu.trl0.trap[3]
3279`define INT_LEVEL_NUM_11 `SPC1.tlu.trl0.int_level_n
3280`define PMU_TAKEN_11 `SPC1.tlu.trl0.take_pmu&`SPC1.tlu.trl0.trap[3]
3281
3282`define HINTP_RDWR_11 (`TOP.nas_top.c1.t3.asi_rdwr_hintp | `TOP.nas_top.c1.t3.asi_wr_hintp_delay)
3283`define HINTP_WR_11 (`SPC1.tlu.asi_wr_hintp[11])
3284`define HSTMATCH_11 `SPC1.tlu.trl0.hstick3_compare
3285
3286`define HINTP_REG_11 `SPC1.tlu.trl0.hintp3
3287`define HSTM_TAKEN_11 `SPC1.tlu.trl0.take_hst&`SPC1.tlu.trl0.trap[3]
3288
3289`define NAS_PIPE_FW2_11 |`TOP.nas_top.c1.t3.complete_fw2
3290
3291`define CWQ_TAKEN_11 `SPC1.tlu.trl0.take_cwq&`SPC1.tlu.trl0.trap[3]
3292`define SMA_TAKEN_11 `SPC1.tlu.trl0.take_sma&`SPC1.tlu.trl0.trap[3]
3293
3294`define POR_TAKEN_11 `SPC1.tlu.trl0.take_por&`SPC1.tlu.trl0.trap[3]
3295
3296/////////////////////////////// Probes //////////////////////////////////// }}}
3297
3298always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
3299
3300 // {{{ DETECT, PIPE & SEND
3301 take_disrupting_w <= (`INT_VEC_TAKEN_11 || `CPU_MONDO_TAKEN_11 ||
3302 `DEV_MONDO_TAKEN_11 || `RES_MONDO_TAKEN_11 ||
3303 `XIR_TAKEN_11 || `INT_LEVEL_TAKEN_11 ||
3304 `HSTM_TAKEN_11 || `CWQ_TAKEN_11 ||
3305 `SMA_TAKEN_11 || `PMU_TAKEN_11 || `POR_TAKEN_11);
3306 take_disrupting_fx4 <= take_disrupting_w;
3307 take_disrupting_fx5 <= take_disrupting_fx4;
3308 take_disrupting_fb <= take_disrupting_fx5;
3309 take_disrupting_fw <= take_disrupting_fb;
3310 take_disrupting_fw1 <= take_disrupting_fw;
3311 take_disrupting_fw2 <= take_disrupting_fw1;
3312
3313 case ({`INT_VEC_TAKEN_11, `CPU_MONDO_TAKEN_11,
3314 `DEV_MONDO_TAKEN_11, `RES_MONDO_TAKEN_11,
3315 `XIR_TAKEN_11, `INT_LEVEL_TAKEN_11,
3316 `HSTM_TAKEN_11, `CWQ_TAKEN_11, `SMA_TAKEN_11 ,
3317 `PMU_TAKEN_11, `POR_TAKEN_11})
3318 11'b10000000000: int_num_w <= 8'h60;
3319 11'b01000000000: int_num_w <= 8'h7c;
3320 11'b00100000000: int_num_w <= 8'h7d;
3321 11'b00010000000: int_num_w <= 8'h7e;
3322 11'b00001000000: int_num_w <= 8'h03;
3323 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_11;
3324 11'b00000010000: int_num_w <= 8'h5e;
3325 11'b00000001000: int_num_w <= 8'h3c;
3326 11'b00000000100: int_num_w <= 8'h3d;
3327 11'b00000000010: int_num_w <= 8'h4f;
3328 11'b00000000001: int_num_w <= 8'h01;
3329 endcase
3330
3331 int_num_fx4 <= int_num_w;
3332 int_num_fx5 <= int_num_fx4;
3333 int_num_fb <= int_num_fx5;
3334 int_num_fw <= int_num_fb;
3335 int_num_fw1 <= int_num_fw;
3336 int_num_fw2 <= int_num_fw1;
3337 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
3338 begin // {
3339 `PR_INFO ("pli_int", `INFO,
3340 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
3341 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3342 end // }
3343
3344 // }}}
3345
3346/////////////////////////// Vectored Interrupt /////////////////////////// {{{
3347
3348 // Vectored Interrupt Recv Register Detection
3349 // Indicate when register changes due to arriving interrupt, and not
3350 // due to read of incoming register or ASI write ..
3351
3352
3353 // If any read occurs, send value right away.
3354 // While a read/write is pending, do not update delta.
3355 // Send non read/wr delta during fw2 ..
3356
3357
3358 if (!(`INT_VEC_RDWR_11 | `INT_VEC_RECV_ASIWR_11)) begin // {
3359 if (~`INT_VEC_RECV_ASIWR_11 &
3360 (int_vec_recv_reg !== `INT_VEC_RECV_REG_11 ))
3361 int_vec_recv_reg_delta <= 1'b1;
3362 int_vec_recv_reg <= `INT_VEC_RECV_REG_11;
3363 end // }
3364 else if (`INT_VEC_RECV_ASIWR_11)
3365 int_vec_recv_reg <= `TOP.nas_top.c1.t3.asi_updated_int_rec;
3366
3367 if ((`NAS_PIPE_FW2_11 & int_vec_recv_reg_delta ) |
3368 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
3369 `INT_VEC_RECV_ASIWR_11 ) begin // {
3370 `PR_INFO ("pli_int", `INFO,
3371 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
3372 mycid,mytid, int_vec_recv_reg);
3373 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3374 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
3375 64'h0, int_vec_recv_reg);
3376 end // }
3377 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_11 &
3378 (int_vec_recv_reg !== `INT_VEC_RECV_REG_11 ))))
3379 int_vec_recv_reg_delta <= 1'b0;
3380 end //}
3381
3382 int_vec_reg_rdwr <= `INT_VEC_RDWR_11 | `INT_VEC_RECV_ASIWR_11;
3383 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_11 & ~ inc_vec_reg_rd;
3384
3385 if (`INT_VEC_RECV_ASIWR_11)
3386 inc_vec_reg_rd <= 1'b1;
3387 if (`NAS_PIPE_FW2_11)
3388 inc_vec_reg_rd <= 1'b0;
3389
3390
3391/////////////////////////// Vectored Interrupt /////////////////////////// }}}
3392
3393/////////////////////////// Asynchronous Resets ////////////////////////// {{{
3394
3395
3396/////////////////////////// Asynchronous Resets ////////////////////////// }}}
3397
3398/////////////////////////// Softint ///////////////////////////////////// {{{
3399
3400 // Softint Register hardware Update Detection
3401
3402 // Non software updates (TM/SM)
3403
3404 // If any read occurs, send value right away.
3405 // While a read/write is pending, do not update delta.
3406 // Send non read/wr delta during fw2 ..
3407
3408 // RTL keeps pic_ovf indication in rd_softint and not softint.
3409 // So for set/clear writes, we send softint before the write ..,
3410 // and for read/asyncs we send rd_softint ..
3411
3412
3413 if (~`SOFTINT_RDWR_11) begin // {
3414 if (softint !== `RD_SOFTINT_REG_11 )
3415 softint_delta <= 1'b1;
3416 softint <= `RD_SOFTINT_REG_11;
3417 end // }
3418
3419 if ((`NAS_PIPE_FW2_11 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
3420 ) begin // {
3421 `PR_INFO ("pli_int", `INFO,
3422 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3423 mycid,mytid, {47'h0, softint});
3424 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3425 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
3426 {47'h0, softint});
3427 end // }
3428 if (!(~`SOFTINT_RDWR_11&(softint !== `RD_SOFTINT_REG_11)))
3429 softint_delta <= 1'b0;
3430 end //}
3431 else if (`SPC1.tlu.asi_wr_clear_softint[3] |
3432 `SPC1.tlu.asi_wr_set_softint[3] ) begin // {
3433 `PR_INFO ("pli_int", `INFO,
3434 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3435 mycid,mytid, {47'h0, `RD_SOFTINT_REG_11});
3436 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3437 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
3438 {47'h0, `RD_SOFTINT_REG_11});
3439 end // }
3440 end //}
3441
3442
3443 softint_rdwr <= `SOFTINT_RDWR_11 ;
3444 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_11;
3445
3446
3447/////////////////////////// Softint ///////////////////////////////////// }}}
3448
3449/////////////////////////// Hintp ///////////////////////////////////// {{{
3450
3451 // Hintp Register hardware Update Detection
3452
3453 // Non software updates (HSP)
3454 // If HINTP is already read/written by SW, then don't send
3455 // any async updates to Nas. Reads/Writes pending sstep is detected
3456 // by snooping nas_pipe ..
3457
3458 hintp <= `HINTP_REG_11 ;
3459 if (hstmatch_late)
3460 hintp_delta <= 1'b1;
3461
3462 if ((~hintp_rdwr & `NAS_PIPE_FW2_11 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
3463 (hintp_rdwr_late & hintp_delta) ) begin // {
3464 `PR_INFO ("pli_int", `INFO,
3465 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
3466 mycid,mytid, {63'h0, hintp});
3467 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3468 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
3469 {63'h0, hintp});
3470 end // }
3471 if (~(hintp_rdwr_late & hintp_delta))
3472 hintp_delta <= 1'b0;
3473 end //}
3474
3475 hintp_rdwr <= `HINTP_RDWR_11;
3476 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_11;
3477 hstmatch_late <= `HSTMATCH_11;
3478
3479
3480/////////////////////////// Hintp ///////////////////////////////////// }}}
3481
3482end //}
3483`endif
3484endmodule
3485
3486// }}}
3487
3488module int_c1t4 ();
3489`ifndef GATESIM
3490
3491// common defines
3492`include "defines.vh"
3493`include "ccx.vri"
3494`include "cmp.vri"
3495
3496wire [2:0] mycid;
3497wire [2:0] mytid;
3498wire [5:0] mytnum;
3499integer junk;
3500
3501reg [63:0] int_vec_recv_reg;
3502reg int_vec_recv_reg_delta;
3503reg int_vec_reg_rdwr;
3504reg inc_vec_reg_rd;
3505reg int_vec_reg_rdwr_late;
3506reg [16:0] softint;
3507reg softint_rdwr;
3508reg softint_rdwr_late;
3509reg softint_delta;
3510reg hintp;
3511reg hintp_rdwr;
3512reg hintp_rdwr_late;
3513reg hintp_delta;
3514reg hstmatch_late;
3515reg ready;
3516reg [7:0] int_num_w;
3517reg [7:0] int_num_fx4;
3518reg [7:0] int_num_fx5;
3519reg [7:0] int_num_fb;
3520reg [7:0] int_num_fw;
3521reg [7:0] int_num_fw1;
3522reg [7:0] int_num_fw2;
3523reg take_disrupting_w;
3524reg take_disrupting_fx4;
3525reg take_disrupting_fx5;
3526reg take_disrupting_fb;
3527reg take_disrupting_fw;
3528reg take_disrupting_fw1;
3529reg take_disrupting_fw2;
3530
3531 assign mycid = 1;
3532 assign mytid = 4;
3533 assign mytnum = 1*8 + 4;
3534
3535initial begin // {
3536 ready = 0; // Wait for socket setup ..
3537 inc_vec_reg_rd <= 1'b0;
3538 int_vec_recv_reg_delta <= 1'b0;
3539 softint_delta <= 1'b0;
3540 hintp_delta <= 1'b0;
3541 int_vec_recv_reg = 64'b0;
3542 @(posedge `BENCH_SPC1_GCLK) ;
3543 @(posedge `BENCH_SPC1_GCLK) ;
3544 ready = `PARGS.int_sync_on;
3545end //}
3546
3547
3548/////////////////////////////// Probes //////////////////////////////////// {{{
3549
3550`define INT_VEC_RECV_REG_12 `SPC1.tlu.cth.int_rec4
3551`define INT_VEC_RECV_ASIWR_12 (`TOP.nas_top.c1.t4.asi_wr_int_rec_delay)
3552`define INT_VEC_RDWR_12 (`TOP.nas_top.c1.t4.asi_rdwr_int_rec)
3553`define INT_VEC_TAKEN_12 `SPC1.tlu.trl1.take_ivt&`SPC1.tlu.trl1.trap[0]
3554
3555`define CPU_MONDO_TAKEN_12 `SPC1.tlu.trl1.take_mqr&`SPC1.tlu.trl1.trap[0]
3556`define DEV_MONDO_TAKEN_12 `SPC1.tlu.trl1.take_dqr&`SPC1.tlu.trl1.trap[0]
3557`define RES_MONDO_TAKEN_12 `SPC1.tlu.trl1.take_rqr&`SPC1.tlu.trl1.trap[0]
3558
3559`define XIR_TAKEN_12 `SPC1.tlu.trl1.take_xir&`SPC1.tlu.trl1.trap[0]
3560
3561`define SOFTINT_RDWR_12 (`TOP.nas_top.c1.t4.asi_rdwr_softint|`TOP.nas_top.c1.t4.asi_wr_softint_delay)
3562
3563`define SOFTINT_REG_12 `SPC1.tlu.trl1.softint0
3564`define RD_SOFTINT_REG_12 `SPC1.tlu.trl1.rd_softint0
3565`define INT_LEVEL_TAKEN_12 `SPC1.tlu.trl1.take_iln&`SPC1.tlu.trl1.trap[0]
3566`define INT_LEVEL_NUM_12 `SPC1.tlu.trl1.int_level_n
3567`define PMU_TAKEN_12 `SPC1.tlu.trl1.take_pmu&`SPC1.tlu.trl1.trap[0]
3568
3569`define HINTP_RDWR_12 (`TOP.nas_top.c1.t4.asi_rdwr_hintp | `TOP.nas_top.c1.t4.asi_wr_hintp_delay)
3570`define HINTP_WR_12 (`SPC1.tlu.asi_wr_hintp[12])
3571`define HSTMATCH_12 `SPC1.tlu.trl1.hstick0_compare
3572
3573`define HINTP_REG_12 `SPC1.tlu.trl1.hintp0
3574`define HSTM_TAKEN_12 `SPC1.tlu.trl1.take_hst&`SPC1.tlu.trl1.trap[0]
3575
3576`define NAS_PIPE_FW2_12 |`TOP.nas_top.c1.t4.complete_fw2
3577
3578`define CWQ_TAKEN_12 `SPC1.tlu.trl1.take_cwq&`SPC1.tlu.trl1.trap[0]
3579`define SMA_TAKEN_12 `SPC1.tlu.trl1.take_sma&`SPC1.tlu.trl1.trap[0]
3580
3581`define POR_TAKEN_12 `SPC1.tlu.trl1.take_por&`SPC1.tlu.trl1.trap[0]
3582
3583/////////////////////////////// Probes //////////////////////////////////// }}}
3584
3585always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
3586
3587 // {{{ DETECT, PIPE & SEND
3588 take_disrupting_w <= (`INT_VEC_TAKEN_12 || `CPU_MONDO_TAKEN_12 ||
3589 `DEV_MONDO_TAKEN_12 || `RES_MONDO_TAKEN_12 ||
3590 `XIR_TAKEN_12 || `INT_LEVEL_TAKEN_12 ||
3591 `HSTM_TAKEN_12 || `CWQ_TAKEN_12 ||
3592 `SMA_TAKEN_12 || `PMU_TAKEN_12 || `POR_TAKEN_12);
3593 take_disrupting_fx4 <= take_disrupting_w;
3594 take_disrupting_fx5 <= take_disrupting_fx4;
3595 take_disrupting_fb <= take_disrupting_fx5;
3596 take_disrupting_fw <= take_disrupting_fb;
3597 take_disrupting_fw1 <= take_disrupting_fw;
3598 take_disrupting_fw2 <= take_disrupting_fw1;
3599
3600 case ({`INT_VEC_TAKEN_12, `CPU_MONDO_TAKEN_12,
3601 `DEV_MONDO_TAKEN_12, `RES_MONDO_TAKEN_12,
3602 `XIR_TAKEN_12, `INT_LEVEL_TAKEN_12,
3603 `HSTM_TAKEN_12, `CWQ_TAKEN_12, `SMA_TAKEN_12 ,
3604 `PMU_TAKEN_12, `POR_TAKEN_12})
3605 11'b10000000000: int_num_w <= 8'h60;
3606 11'b01000000000: int_num_w <= 8'h7c;
3607 11'b00100000000: int_num_w <= 8'h7d;
3608 11'b00010000000: int_num_w <= 8'h7e;
3609 11'b00001000000: int_num_w <= 8'h03;
3610 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_12;
3611 11'b00000010000: int_num_w <= 8'h5e;
3612 11'b00000001000: int_num_w <= 8'h3c;
3613 11'b00000000100: int_num_w <= 8'h3d;
3614 11'b00000000010: int_num_w <= 8'h4f;
3615 11'b00000000001: int_num_w <= 8'h01;
3616 endcase
3617
3618 int_num_fx4 <= int_num_w;
3619 int_num_fx5 <= int_num_fx4;
3620 int_num_fb <= int_num_fx5;
3621 int_num_fw <= int_num_fb;
3622 int_num_fw1 <= int_num_fw;
3623 int_num_fw2 <= int_num_fw1;
3624 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
3625 begin // {
3626 `PR_INFO ("pli_int", `INFO,
3627 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
3628 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3629 end // }
3630
3631 // }}}
3632
3633/////////////////////////// Vectored Interrupt /////////////////////////// {{{
3634
3635 // Vectored Interrupt Recv Register Detection
3636 // Indicate when register changes due to arriving interrupt, and not
3637 // due to read of incoming register or ASI write ..
3638
3639
3640 // If any read occurs, send value right away.
3641 // While a read/write is pending, do not update delta.
3642 // Send non read/wr delta during fw2 ..
3643
3644
3645 if (!(`INT_VEC_RDWR_12 | `INT_VEC_RECV_ASIWR_12)) begin // {
3646 if (~`INT_VEC_RECV_ASIWR_12 &
3647 (int_vec_recv_reg !== `INT_VEC_RECV_REG_12 ))
3648 int_vec_recv_reg_delta <= 1'b1;
3649 int_vec_recv_reg <= `INT_VEC_RECV_REG_12;
3650 end // }
3651 else if (`INT_VEC_RECV_ASIWR_12)
3652 int_vec_recv_reg <= `TOP.nas_top.c1.t4.asi_updated_int_rec;
3653
3654 if ((`NAS_PIPE_FW2_12 & int_vec_recv_reg_delta ) |
3655 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
3656 `INT_VEC_RECV_ASIWR_12 ) begin // {
3657 `PR_INFO ("pli_int", `INFO,
3658 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
3659 mycid,mytid, int_vec_recv_reg);
3660 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3661 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
3662 64'h0, int_vec_recv_reg);
3663 end // }
3664 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_12 &
3665 (int_vec_recv_reg !== `INT_VEC_RECV_REG_12 ))))
3666 int_vec_recv_reg_delta <= 1'b0;
3667 end //}
3668
3669 int_vec_reg_rdwr <= `INT_VEC_RDWR_12 | `INT_VEC_RECV_ASIWR_12;
3670 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_12 & ~ inc_vec_reg_rd;
3671
3672 if (`INT_VEC_RECV_ASIWR_12)
3673 inc_vec_reg_rd <= 1'b1;
3674 if (`NAS_PIPE_FW2_12)
3675 inc_vec_reg_rd <= 1'b0;
3676
3677
3678/////////////////////////// Vectored Interrupt /////////////////////////// }}}
3679
3680/////////////////////////// Asynchronous Resets ////////////////////////// {{{
3681
3682
3683/////////////////////////// Asynchronous Resets ////////////////////////// }}}
3684
3685/////////////////////////// Softint ///////////////////////////////////// {{{
3686
3687 // Softint Register hardware Update Detection
3688
3689 // Non software updates (TM/SM)
3690
3691 // If any read occurs, send value right away.
3692 // While a read/write is pending, do not update delta.
3693 // Send non read/wr delta during fw2 ..
3694
3695 // RTL keeps pic_ovf indication in rd_softint and not softint.
3696 // So for set/clear writes, we send softint before the write ..,
3697 // and for read/asyncs we send rd_softint ..
3698
3699
3700 if (~`SOFTINT_RDWR_12) begin // {
3701 if (softint !== `RD_SOFTINT_REG_12 )
3702 softint_delta <= 1'b1;
3703 softint <= `RD_SOFTINT_REG_12;
3704 end // }
3705
3706 if ((`NAS_PIPE_FW2_12 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
3707 ) begin // {
3708 `PR_INFO ("pli_int", `INFO,
3709 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3710 mycid,mytid, {47'h0, softint});
3711 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3712 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
3713 {47'h0, softint});
3714 end // }
3715 if (!(~`SOFTINT_RDWR_12&(softint !== `RD_SOFTINT_REG_12)))
3716 softint_delta <= 1'b0;
3717 end //}
3718 else if (`SPC1.tlu.asi_wr_clear_softint[4] |
3719 `SPC1.tlu.asi_wr_set_softint[4] ) begin // {
3720 `PR_INFO ("pli_int", `INFO,
3721 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3722 mycid,mytid, {47'h0, `RD_SOFTINT_REG_12});
3723 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3724 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
3725 {47'h0, `RD_SOFTINT_REG_12});
3726 end // }
3727 end //}
3728
3729
3730 softint_rdwr <= `SOFTINT_RDWR_12 ;
3731 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_12;
3732
3733
3734/////////////////////////// Softint ///////////////////////////////////// }}}
3735
3736/////////////////////////// Hintp ///////////////////////////////////// {{{
3737
3738 // Hintp Register hardware Update Detection
3739
3740 // Non software updates (HSP)
3741 // If HINTP is already read/written by SW, then don't send
3742 // any async updates to Nas. Reads/Writes pending sstep is detected
3743 // by snooping nas_pipe ..
3744
3745 hintp <= `HINTP_REG_12 ;
3746 if (hstmatch_late)
3747 hintp_delta <= 1'b1;
3748
3749 if ((~hintp_rdwr & `NAS_PIPE_FW2_12 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
3750 (hintp_rdwr_late & hintp_delta) ) begin // {
3751 `PR_INFO ("pli_int", `INFO,
3752 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
3753 mycid,mytid, {63'h0, hintp});
3754 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3755 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
3756 {63'h0, hintp});
3757 end // }
3758 if (~(hintp_rdwr_late & hintp_delta))
3759 hintp_delta <= 1'b0;
3760 end //}
3761
3762 hintp_rdwr <= `HINTP_RDWR_12;
3763 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_12;
3764 hstmatch_late <= `HSTMATCH_12;
3765
3766
3767/////////////////////////// Hintp ///////////////////////////////////// }}}
3768
3769end //}
3770`endif
3771endmodule
3772
3773// }}}
3774
3775module int_c1t5 ();
3776`ifndef GATESIM
3777
3778// common defines
3779`include "defines.vh"
3780`include "ccx.vri"
3781`include "cmp.vri"
3782
3783wire [2:0] mycid;
3784wire [2:0] mytid;
3785wire [5:0] mytnum;
3786integer junk;
3787
3788reg [63:0] int_vec_recv_reg;
3789reg int_vec_recv_reg_delta;
3790reg int_vec_reg_rdwr;
3791reg inc_vec_reg_rd;
3792reg int_vec_reg_rdwr_late;
3793reg [16:0] softint;
3794reg softint_rdwr;
3795reg softint_rdwr_late;
3796reg softint_delta;
3797reg hintp;
3798reg hintp_rdwr;
3799reg hintp_rdwr_late;
3800reg hintp_delta;
3801reg hstmatch_late;
3802reg ready;
3803reg [7:0] int_num_w;
3804reg [7:0] int_num_fx4;
3805reg [7:0] int_num_fx5;
3806reg [7:0] int_num_fb;
3807reg [7:0] int_num_fw;
3808reg [7:0] int_num_fw1;
3809reg [7:0] int_num_fw2;
3810reg take_disrupting_w;
3811reg take_disrupting_fx4;
3812reg take_disrupting_fx5;
3813reg take_disrupting_fb;
3814reg take_disrupting_fw;
3815reg take_disrupting_fw1;
3816reg take_disrupting_fw2;
3817
3818 assign mycid = 1;
3819 assign mytid = 5;
3820 assign mytnum = 1*8 + 5;
3821
3822initial begin // {
3823 ready = 0; // Wait for socket setup ..
3824 inc_vec_reg_rd <= 1'b0;
3825 int_vec_recv_reg_delta <= 1'b0;
3826 softint_delta <= 1'b0;
3827 hintp_delta <= 1'b0;
3828 int_vec_recv_reg = 64'b0;
3829 @(posedge `BENCH_SPC1_GCLK) ;
3830 @(posedge `BENCH_SPC1_GCLK) ;
3831 ready = `PARGS.int_sync_on;
3832end //}
3833
3834
3835/////////////////////////////// Probes //////////////////////////////////// {{{
3836
3837`define INT_VEC_RECV_REG_13 `SPC1.tlu.cth.int_rec5
3838`define INT_VEC_RECV_ASIWR_13 (`TOP.nas_top.c1.t5.asi_wr_int_rec_delay)
3839`define INT_VEC_RDWR_13 (`TOP.nas_top.c1.t5.asi_rdwr_int_rec)
3840`define INT_VEC_TAKEN_13 `SPC1.tlu.trl1.take_ivt&`SPC1.tlu.trl1.trap[1]
3841
3842`define CPU_MONDO_TAKEN_13 `SPC1.tlu.trl1.take_mqr&`SPC1.tlu.trl1.trap[1]
3843`define DEV_MONDO_TAKEN_13 `SPC1.tlu.trl1.take_dqr&`SPC1.tlu.trl1.trap[1]
3844`define RES_MONDO_TAKEN_13 `SPC1.tlu.trl1.take_rqr&`SPC1.tlu.trl1.trap[1]
3845
3846`define XIR_TAKEN_13 `SPC1.tlu.trl1.take_xir&`SPC1.tlu.trl1.trap[1]
3847
3848`define SOFTINT_RDWR_13 (`TOP.nas_top.c1.t5.asi_rdwr_softint|`TOP.nas_top.c1.t5.asi_wr_softint_delay)
3849
3850`define SOFTINT_REG_13 `SPC1.tlu.trl1.softint1
3851`define RD_SOFTINT_REG_13 `SPC1.tlu.trl1.rd_softint1
3852`define INT_LEVEL_TAKEN_13 `SPC1.tlu.trl1.take_iln&`SPC1.tlu.trl1.trap[1]
3853`define INT_LEVEL_NUM_13 `SPC1.tlu.trl1.int_level_n
3854`define PMU_TAKEN_13 `SPC1.tlu.trl1.take_pmu&`SPC1.tlu.trl1.trap[1]
3855
3856`define HINTP_RDWR_13 (`TOP.nas_top.c1.t5.asi_rdwr_hintp | `TOP.nas_top.c1.t5.asi_wr_hintp_delay)
3857`define HINTP_WR_13 (`SPC1.tlu.asi_wr_hintp[13])
3858`define HSTMATCH_13 `SPC1.tlu.trl1.hstick1_compare
3859
3860`define HINTP_REG_13 `SPC1.tlu.trl1.hintp1
3861`define HSTM_TAKEN_13 `SPC1.tlu.trl1.take_hst&`SPC1.tlu.trl1.trap[1]
3862
3863`define NAS_PIPE_FW2_13 |`TOP.nas_top.c1.t5.complete_fw2
3864
3865`define CWQ_TAKEN_13 `SPC1.tlu.trl1.take_cwq&`SPC1.tlu.trl1.trap[1]
3866`define SMA_TAKEN_13 `SPC1.tlu.trl1.take_sma&`SPC1.tlu.trl1.trap[1]
3867
3868`define POR_TAKEN_13 `SPC1.tlu.trl1.take_por&`SPC1.tlu.trl1.trap[1]
3869
3870/////////////////////////////// Probes //////////////////////////////////// }}}
3871
3872always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
3873
3874 // {{{ DETECT, PIPE & SEND
3875 take_disrupting_w <= (`INT_VEC_TAKEN_13 || `CPU_MONDO_TAKEN_13 ||
3876 `DEV_MONDO_TAKEN_13 || `RES_MONDO_TAKEN_13 ||
3877 `XIR_TAKEN_13 || `INT_LEVEL_TAKEN_13 ||
3878 `HSTM_TAKEN_13 || `CWQ_TAKEN_13 ||
3879 `SMA_TAKEN_13 || `PMU_TAKEN_13 || `POR_TAKEN_13);
3880 take_disrupting_fx4 <= take_disrupting_w;
3881 take_disrupting_fx5 <= take_disrupting_fx4;
3882 take_disrupting_fb <= take_disrupting_fx5;
3883 take_disrupting_fw <= take_disrupting_fb;
3884 take_disrupting_fw1 <= take_disrupting_fw;
3885 take_disrupting_fw2 <= take_disrupting_fw1;
3886
3887 case ({`INT_VEC_TAKEN_13, `CPU_MONDO_TAKEN_13,
3888 `DEV_MONDO_TAKEN_13, `RES_MONDO_TAKEN_13,
3889 `XIR_TAKEN_13, `INT_LEVEL_TAKEN_13,
3890 `HSTM_TAKEN_13, `CWQ_TAKEN_13, `SMA_TAKEN_13 ,
3891 `PMU_TAKEN_13, `POR_TAKEN_13})
3892 11'b10000000000: int_num_w <= 8'h60;
3893 11'b01000000000: int_num_w <= 8'h7c;
3894 11'b00100000000: int_num_w <= 8'h7d;
3895 11'b00010000000: int_num_w <= 8'h7e;
3896 11'b00001000000: int_num_w <= 8'h03;
3897 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_13;
3898 11'b00000010000: int_num_w <= 8'h5e;
3899 11'b00000001000: int_num_w <= 8'h3c;
3900 11'b00000000100: int_num_w <= 8'h3d;
3901 11'b00000000010: int_num_w <= 8'h4f;
3902 11'b00000000001: int_num_w <= 8'h01;
3903 endcase
3904
3905 int_num_fx4 <= int_num_w;
3906 int_num_fx5 <= int_num_fx4;
3907 int_num_fb <= int_num_fx5;
3908 int_num_fw <= int_num_fb;
3909 int_num_fw1 <= int_num_fw;
3910 int_num_fw2 <= int_num_fw1;
3911 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
3912 begin // {
3913 `PR_INFO ("pli_int", `INFO,
3914 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
3915 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
3916 end // }
3917
3918 // }}}
3919
3920/////////////////////////// Vectored Interrupt /////////////////////////// {{{
3921
3922 // Vectored Interrupt Recv Register Detection
3923 // Indicate when register changes due to arriving interrupt, and not
3924 // due to read of incoming register or ASI write ..
3925
3926
3927 // If any read occurs, send value right away.
3928 // While a read/write is pending, do not update delta.
3929 // Send non read/wr delta during fw2 ..
3930
3931
3932 if (!(`INT_VEC_RDWR_13 | `INT_VEC_RECV_ASIWR_13)) begin // {
3933 if (~`INT_VEC_RECV_ASIWR_13 &
3934 (int_vec_recv_reg !== `INT_VEC_RECV_REG_13 ))
3935 int_vec_recv_reg_delta <= 1'b1;
3936 int_vec_recv_reg <= `INT_VEC_RECV_REG_13;
3937 end // }
3938 else if (`INT_VEC_RECV_ASIWR_13)
3939 int_vec_recv_reg <= `TOP.nas_top.c1.t5.asi_updated_int_rec;
3940
3941 if ((`NAS_PIPE_FW2_13 & int_vec_recv_reg_delta ) |
3942 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
3943 `INT_VEC_RECV_ASIWR_13 ) begin // {
3944 `PR_INFO ("pli_int", `INFO,
3945 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
3946 mycid,mytid, int_vec_recv_reg);
3947 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3948 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
3949 64'h0, int_vec_recv_reg);
3950 end // }
3951 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_13 &
3952 (int_vec_recv_reg !== `INT_VEC_RECV_REG_13 ))))
3953 int_vec_recv_reg_delta <= 1'b0;
3954 end //}
3955
3956 int_vec_reg_rdwr <= `INT_VEC_RDWR_13 | `INT_VEC_RECV_ASIWR_13;
3957 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_13 & ~ inc_vec_reg_rd;
3958
3959 if (`INT_VEC_RECV_ASIWR_13)
3960 inc_vec_reg_rd <= 1'b1;
3961 if (`NAS_PIPE_FW2_13)
3962 inc_vec_reg_rd <= 1'b0;
3963
3964
3965/////////////////////////// Vectored Interrupt /////////////////////////// }}}
3966
3967/////////////////////////// Asynchronous Resets ////////////////////////// {{{
3968
3969
3970/////////////////////////// Asynchronous Resets ////////////////////////// }}}
3971
3972/////////////////////////// Softint ///////////////////////////////////// {{{
3973
3974 // Softint Register hardware Update Detection
3975
3976 // Non software updates (TM/SM)
3977
3978 // If any read occurs, send value right away.
3979 // While a read/write is pending, do not update delta.
3980 // Send non read/wr delta during fw2 ..
3981
3982 // RTL keeps pic_ovf indication in rd_softint and not softint.
3983 // So for set/clear writes, we send softint before the write ..,
3984 // and for read/asyncs we send rd_softint ..
3985
3986
3987 if (~`SOFTINT_RDWR_13) begin // {
3988 if (softint !== `RD_SOFTINT_REG_13 )
3989 softint_delta <= 1'b1;
3990 softint <= `RD_SOFTINT_REG_13;
3991 end // }
3992
3993 if ((`NAS_PIPE_FW2_13 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
3994 ) begin // {
3995 `PR_INFO ("pli_int", `INFO,
3996 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
3997 mycid,mytid, {47'h0, softint});
3998 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
3999 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4000 {47'h0, softint});
4001 end // }
4002 if (!(~`SOFTINT_RDWR_13&(softint !== `RD_SOFTINT_REG_13)))
4003 softint_delta <= 1'b0;
4004 end //}
4005 else if (`SPC1.tlu.asi_wr_clear_softint[5] |
4006 `SPC1.tlu.asi_wr_set_softint[5] ) begin // {
4007 `PR_INFO ("pli_int", `INFO,
4008 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4009 mycid,mytid, {47'h0, `RD_SOFTINT_REG_13});
4010 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4011 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4012 {47'h0, `RD_SOFTINT_REG_13});
4013 end // }
4014 end //}
4015
4016
4017 softint_rdwr <= `SOFTINT_RDWR_13 ;
4018 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_13;
4019
4020
4021/////////////////////////// Softint ///////////////////////////////////// }}}
4022
4023/////////////////////////// Hintp ///////////////////////////////////// {{{
4024
4025 // Hintp Register hardware Update Detection
4026
4027 // Non software updates (HSP)
4028 // If HINTP is already read/written by SW, then don't send
4029 // any async updates to Nas. Reads/Writes pending sstep is detected
4030 // by snooping nas_pipe ..
4031
4032 hintp <= `HINTP_REG_13 ;
4033 if (hstmatch_late)
4034 hintp_delta <= 1'b1;
4035
4036 if ((~hintp_rdwr & `NAS_PIPE_FW2_13 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
4037 (hintp_rdwr_late & hintp_delta) ) begin // {
4038 `PR_INFO ("pli_int", `INFO,
4039 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
4040 mycid,mytid, {63'h0, hintp});
4041 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4042 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
4043 {63'h0, hintp});
4044 end // }
4045 if (~(hintp_rdwr_late & hintp_delta))
4046 hintp_delta <= 1'b0;
4047 end //}
4048
4049 hintp_rdwr <= `HINTP_RDWR_13;
4050 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_13;
4051 hstmatch_late <= `HSTMATCH_13;
4052
4053
4054/////////////////////////// Hintp ///////////////////////////////////// }}}
4055
4056end //}
4057`endif
4058endmodule
4059
4060// }}}
4061
4062module int_c1t6 ();
4063`ifndef GATESIM
4064
4065// common defines
4066`include "defines.vh"
4067`include "ccx.vri"
4068`include "cmp.vri"
4069
4070wire [2:0] mycid;
4071wire [2:0] mytid;
4072wire [5:0] mytnum;
4073integer junk;
4074
4075reg [63:0] int_vec_recv_reg;
4076reg int_vec_recv_reg_delta;
4077reg int_vec_reg_rdwr;
4078reg inc_vec_reg_rd;
4079reg int_vec_reg_rdwr_late;
4080reg [16:0] softint;
4081reg softint_rdwr;
4082reg softint_rdwr_late;
4083reg softint_delta;
4084reg hintp;
4085reg hintp_rdwr;
4086reg hintp_rdwr_late;
4087reg hintp_delta;
4088reg hstmatch_late;
4089reg ready;
4090reg [7:0] int_num_w;
4091reg [7:0] int_num_fx4;
4092reg [7:0] int_num_fx5;
4093reg [7:0] int_num_fb;
4094reg [7:0] int_num_fw;
4095reg [7:0] int_num_fw1;
4096reg [7:0] int_num_fw2;
4097reg take_disrupting_w;
4098reg take_disrupting_fx4;
4099reg take_disrupting_fx5;
4100reg take_disrupting_fb;
4101reg take_disrupting_fw;
4102reg take_disrupting_fw1;
4103reg take_disrupting_fw2;
4104
4105 assign mycid = 1;
4106 assign mytid = 6;
4107 assign mytnum = 1*8 + 6;
4108
4109initial begin // {
4110 ready = 0; // Wait for socket setup ..
4111 inc_vec_reg_rd <= 1'b0;
4112 int_vec_recv_reg_delta <= 1'b0;
4113 softint_delta <= 1'b0;
4114 hintp_delta <= 1'b0;
4115 int_vec_recv_reg = 64'b0;
4116 @(posedge `BENCH_SPC1_GCLK) ;
4117 @(posedge `BENCH_SPC1_GCLK) ;
4118 ready = `PARGS.int_sync_on;
4119end //}
4120
4121
4122/////////////////////////////// Probes //////////////////////////////////// {{{
4123
4124`define INT_VEC_RECV_REG_14 `SPC1.tlu.cth.int_rec6
4125`define INT_VEC_RECV_ASIWR_14 (`TOP.nas_top.c1.t6.asi_wr_int_rec_delay)
4126`define INT_VEC_RDWR_14 (`TOP.nas_top.c1.t6.asi_rdwr_int_rec)
4127`define INT_VEC_TAKEN_14 `SPC1.tlu.trl1.take_ivt&`SPC1.tlu.trl1.trap[2]
4128
4129`define CPU_MONDO_TAKEN_14 `SPC1.tlu.trl1.take_mqr&`SPC1.tlu.trl1.trap[2]
4130`define DEV_MONDO_TAKEN_14 `SPC1.tlu.trl1.take_dqr&`SPC1.tlu.trl1.trap[2]
4131`define RES_MONDO_TAKEN_14 `SPC1.tlu.trl1.take_rqr&`SPC1.tlu.trl1.trap[2]
4132
4133`define XIR_TAKEN_14 `SPC1.tlu.trl1.take_xir&`SPC1.tlu.trl1.trap[2]
4134
4135`define SOFTINT_RDWR_14 (`TOP.nas_top.c1.t6.asi_rdwr_softint|`TOP.nas_top.c1.t6.asi_wr_softint_delay)
4136
4137`define SOFTINT_REG_14 `SPC1.tlu.trl1.softint2
4138`define RD_SOFTINT_REG_14 `SPC1.tlu.trl1.rd_softint2
4139`define INT_LEVEL_TAKEN_14 `SPC1.tlu.trl1.take_iln&`SPC1.tlu.trl1.trap[2]
4140`define INT_LEVEL_NUM_14 `SPC1.tlu.trl1.int_level_n
4141`define PMU_TAKEN_14 `SPC1.tlu.trl1.take_pmu&`SPC1.tlu.trl1.trap[2]
4142
4143`define HINTP_RDWR_14 (`TOP.nas_top.c1.t6.asi_rdwr_hintp | `TOP.nas_top.c1.t6.asi_wr_hintp_delay)
4144`define HINTP_WR_14 (`SPC1.tlu.asi_wr_hintp[14])
4145`define HSTMATCH_14 `SPC1.tlu.trl1.hstick2_compare
4146
4147`define HINTP_REG_14 `SPC1.tlu.trl1.hintp2
4148`define HSTM_TAKEN_14 `SPC1.tlu.trl1.take_hst&`SPC1.tlu.trl1.trap[2]
4149
4150`define NAS_PIPE_FW2_14 |`TOP.nas_top.c1.t6.complete_fw2
4151
4152`define CWQ_TAKEN_14 `SPC1.tlu.trl1.take_cwq&`SPC1.tlu.trl1.trap[2]
4153`define SMA_TAKEN_14 `SPC1.tlu.trl1.take_sma&`SPC1.tlu.trl1.trap[2]
4154
4155`define POR_TAKEN_14 `SPC1.tlu.trl1.take_por&`SPC1.tlu.trl1.trap[2]
4156
4157/////////////////////////////// Probes //////////////////////////////////// }}}
4158
4159always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
4160
4161 // {{{ DETECT, PIPE & SEND
4162 take_disrupting_w <= (`INT_VEC_TAKEN_14 || `CPU_MONDO_TAKEN_14 ||
4163 `DEV_MONDO_TAKEN_14 || `RES_MONDO_TAKEN_14 ||
4164 `XIR_TAKEN_14 || `INT_LEVEL_TAKEN_14 ||
4165 `HSTM_TAKEN_14 || `CWQ_TAKEN_14 ||
4166 `SMA_TAKEN_14 || `PMU_TAKEN_14 || `POR_TAKEN_14);
4167 take_disrupting_fx4 <= take_disrupting_w;
4168 take_disrupting_fx5 <= take_disrupting_fx4;
4169 take_disrupting_fb <= take_disrupting_fx5;
4170 take_disrupting_fw <= take_disrupting_fb;
4171 take_disrupting_fw1 <= take_disrupting_fw;
4172 take_disrupting_fw2 <= take_disrupting_fw1;
4173
4174 case ({`INT_VEC_TAKEN_14, `CPU_MONDO_TAKEN_14,
4175 `DEV_MONDO_TAKEN_14, `RES_MONDO_TAKEN_14,
4176 `XIR_TAKEN_14, `INT_LEVEL_TAKEN_14,
4177 `HSTM_TAKEN_14, `CWQ_TAKEN_14, `SMA_TAKEN_14 ,
4178 `PMU_TAKEN_14, `POR_TAKEN_14})
4179 11'b10000000000: int_num_w <= 8'h60;
4180 11'b01000000000: int_num_w <= 8'h7c;
4181 11'b00100000000: int_num_w <= 8'h7d;
4182 11'b00010000000: int_num_w <= 8'h7e;
4183 11'b00001000000: int_num_w <= 8'h03;
4184 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_14;
4185 11'b00000010000: int_num_w <= 8'h5e;
4186 11'b00000001000: int_num_w <= 8'h3c;
4187 11'b00000000100: int_num_w <= 8'h3d;
4188 11'b00000000010: int_num_w <= 8'h4f;
4189 11'b00000000001: int_num_w <= 8'h01;
4190 endcase
4191
4192 int_num_fx4 <= int_num_w;
4193 int_num_fx5 <= int_num_fx4;
4194 int_num_fb <= int_num_fx5;
4195 int_num_fw <= int_num_fb;
4196 int_num_fw1 <= int_num_fw;
4197 int_num_fw2 <= int_num_fw1;
4198 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
4199 begin // {
4200 `PR_INFO ("pli_int", `INFO,
4201 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
4202 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
4203 end // }
4204
4205 // }}}
4206
4207/////////////////////////// Vectored Interrupt /////////////////////////// {{{
4208
4209 // Vectored Interrupt Recv Register Detection
4210 // Indicate when register changes due to arriving interrupt, and not
4211 // due to read of incoming register or ASI write ..
4212
4213
4214 // If any read occurs, send value right away.
4215 // While a read/write is pending, do not update delta.
4216 // Send non read/wr delta during fw2 ..
4217
4218
4219 if (!(`INT_VEC_RDWR_14 | `INT_VEC_RECV_ASIWR_14)) begin // {
4220 if (~`INT_VEC_RECV_ASIWR_14 &
4221 (int_vec_recv_reg !== `INT_VEC_RECV_REG_14 ))
4222 int_vec_recv_reg_delta <= 1'b1;
4223 int_vec_recv_reg <= `INT_VEC_RECV_REG_14;
4224 end // }
4225 else if (`INT_VEC_RECV_ASIWR_14)
4226 int_vec_recv_reg <= `TOP.nas_top.c1.t6.asi_updated_int_rec;
4227
4228 if ((`NAS_PIPE_FW2_14 & int_vec_recv_reg_delta ) |
4229 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
4230 `INT_VEC_RECV_ASIWR_14 ) begin // {
4231 `PR_INFO ("pli_int", `INFO,
4232 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
4233 mycid,mytid, int_vec_recv_reg);
4234 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4235 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
4236 64'h0, int_vec_recv_reg);
4237 end // }
4238 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_14 &
4239 (int_vec_recv_reg !== `INT_VEC_RECV_REG_14 ))))
4240 int_vec_recv_reg_delta <= 1'b0;
4241 end //}
4242
4243 int_vec_reg_rdwr <= `INT_VEC_RDWR_14 | `INT_VEC_RECV_ASIWR_14;
4244 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_14 & ~ inc_vec_reg_rd;
4245
4246 if (`INT_VEC_RECV_ASIWR_14)
4247 inc_vec_reg_rd <= 1'b1;
4248 if (`NAS_PIPE_FW2_14)
4249 inc_vec_reg_rd <= 1'b0;
4250
4251
4252/////////////////////////// Vectored Interrupt /////////////////////////// }}}
4253
4254/////////////////////////// Asynchronous Resets ////////////////////////// {{{
4255
4256
4257/////////////////////////// Asynchronous Resets ////////////////////////// }}}
4258
4259/////////////////////////// Softint ///////////////////////////////////// {{{
4260
4261 // Softint Register hardware Update Detection
4262
4263 // Non software updates (TM/SM)
4264
4265 // If any read occurs, send value right away.
4266 // While a read/write is pending, do not update delta.
4267 // Send non read/wr delta during fw2 ..
4268
4269 // RTL keeps pic_ovf indication in rd_softint and not softint.
4270 // So for set/clear writes, we send softint before the write ..,
4271 // and for read/asyncs we send rd_softint ..
4272
4273
4274 if (~`SOFTINT_RDWR_14) begin // {
4275 if (softint !== `RD_SOFTINT_REG_14 )
4276 softint_delta <= 1'b1;
4277 softint <= `RD_SOFTINT_REG_14;
4278 end // }
4279
4280 if ((`NAS_PIPE_FW2_14 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
4281 ) begin // {
4282 `PR_INFO ("pli_int", `INFO,
4283 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4284 mycid,mytid, {47'h0, softint});
4285 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4286 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4287 {47'h0, softint});
4288 end // }
4289 if (!(~`SOFTINT_RDWR_14&(softint !== `RD_SOFTINT_REG_14)))
4290 softint_delta <= 1'b0;
4291 end //}
4292 else if (`SPC1.tlu.asi_wr_clear_softint[6] |
4293 `SPC1.tlu.asi_wr_set_softint[6] ) begin // {
4294 `PR_INFO ("pli_int", `INFO,
4295 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4296 mycid,mytid, {47'h0, `RD_SOFTINT_REG_14});
4297 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4298 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4299 {47'h0, `RD_SOFTINT_REG_14});
4300 end // }
4301 end //}
4302
4303
4304 softint_rdwr <= `SOFTINT_RDWR_14 ;
4305 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_14;
4306
4307
4308/////////////////////////// Softint ///////////////////////////////////// }}}
4309
4310/////////////////////////// Hintp ///////////////////////////////////// {{{
4311
4312 // Hintp Register hardware Update Detection
4313
4314 // Non software updates (HSP)
4315 // If HINTP is already read/written by SW, then don't send
4316 // any async updates to Nas. Reads/Writes pending sstep is detected
4317 // by snooping nas_pipe ..
4318
4319 hintp <= `HINTP_REG_14 ;
4320 if (hstmatch_late)
4321 hintp_delta <= 1'b1;
4322
4323 if ((~hintp_rdwr & `NAS_PIPE_FW2_14 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
4324 (hintp_rdwr_late & hintp_delta) ) begin // {
4325 `PR_INFO ("pli_int", `INFO,
4326 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
4327 mycid,mytid, {63'h0, hintp});
4328 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4329 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
4330 {63'h0, hintp});
4331 end // }
4332 if (~(hintp_rdwr_late & hintp_delta))
4333 hintp_delta <= 1'b0;
4334 end //}
4335
4336 hintp_rdwr <= `HINTP_RDWR_14;
4337 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_14;
4338 hstmatch_late <= `HSTMATCH_14;
4339
4340
4341/////////////////////////// Hintp ///////////////////////////////////// }}}
4342
4343end //}
4344`endif
4345endmodule
4346
4347// }}}
4348
4349module int_c1t7 ();
4350`ifndef GATESIM
4351
4352// common defines
4353`include "defines.vh"
4354`include "ccx.vri"
4355`include "cmp.vri"
4356
4357wire [2:0] mycid;
4358wire [2:0] mytid;
4359wire [5:0] mytnum;
4360integer junk;
4361
4362reg [63:0] int_vec_recv_reg;
4363reg int_vec_recv_reg_delta;
4364reg int_vec_reg_rdwr;
4365reg inc_vec_reg_rd;
4366reg int_vec_reg_rdwr_late;
4367reg [16:0] softint;
4368reg softint_rdwr;
4369reg softint_rdwr_late;
4370reg softint_delta;
4371reg hintp;
4372reg hintp_rdwr;
4373reg hintp_rdwr_late;
4374reg hintp_delta;
4375reg hstmatch_late;
4376reg ready;
4377reg [7:0] int_num_w;
4378reg [7:0] int_num_fx4;
4379reg [7:0] int_num_fx5;
4380reg [7:0] int_num_fb;
4381reg [7:0] int_num_fw;
4382reg [7:0] int_num_fw1;
4383reg [7:0] int_num_fw2;
4384reg take_disrupting_w;
4385reg take_disrupting_fx4;
4386reg take_disrupting_fx5;
4387reg take_disrupting_fb;
4388reg take_disrupting_fw;
4389reg take_disrupting_fw1;
4390reg take_disrupting_fw2;
4391
4392 assign mycid = 1;
4393 assign mytid = 7;
4394 assign mytnum = 1*8 + 7;
4395
4396initial begin // {
4397 ready = 0; // Wait for socket setup ..
4398 inc_vec_reg_rd <= 1'b0;
4399 int_vec_recv_reg_delta <= 1'b0;
4400 softint_delta <= 1'b0;
4401 hintp_delta <= 1'b0;
4402 int_vec_recv_reg = 64'b0;
4403 @(posedge `BENCH_SPC1_GCLK) ;
4404 @(posedge `BENCH_SPC1_GCLK) ;
4405 ready = `PARGS.int_sync_on;
4406end //}
4407
4408
4409/////////////////////////////// Probes //////////////////////////////////// {{{
4410
4411`define INT_VEC_RECV_REG_15 `SPC1.tlu.cth.int_rec7
4412`define INT_VEC_RECV_ASIWR_15 (`TOP.nas_top.c1.t7.asi_wr_int_rec_delay)
4413`define INT_VEC_RDWR_15 (`TOP.nas_top.c1.t7.asi_rdwr_int_rec)
4414`define INT_VEC_TAKEN_15 `SPC1.tlu.trl1.take_ivt&`SPC1.tlu.trl1.trap[3]
4415
4416`define CPU_MONDO_TAKEN_15 `SPC1.tlu.trl1.take_mqr&`SPC1.tlu.trl1.trap[3]
4417`define DEV_MONDO_TAKEN_15 `SPC1.tlu.trl1.take_dqr&`SPC1.tlu.trl1.trap[3]
4418`define RES_MONDO_TAKEN_15 `SPC1.tlu.trl1.take_rqr&`SPC1.tlu.trl1.trap[3]
4419
4420`define XIR_TAKEN_15 `SPC1.tlu.trl1.take_xir&`SPC1.tlu.trl1.trap[3]
4421
4422`define SOFTINT_RDWR_15 (`TOP.nas_top.c1.t7.asi_rdwr_softint|`TOP.nas_top.c1.t7.asi_wr_softint_delay)
4423
4424`define SOFTINT_REG_15 `SPC1.tlu.trl1.softint3
4425`define RD_SOFTINT_REG_15 `SPC1.tlu.trl1.rd_softint3
4426`define INT_LEVEL_TAKEN_15 `SPC1.tlu.trl1.take_iln&`SPC1.tlu.trl1.trap[3]
4427`define INT_LEVEL_NUM_15 `SPC1.tlu.trl1.int_level_n
4428`define PMU_TAKEN_15 `SPC1.tlu.trl1.take_pmu&`SPC1.tlu.trl1.trap[3]
4429
4430`define HINTP_RDWR_15 (`TOP.nas_top.c1.t7.asi_rdwr_hintp | `TOP.nas_top.c1.t7.asi_wr_hintp_delay)
4431`define HINTP_WR_15 (`SPC1.tlu.asi_wr_hintp[15])
4432`define HSTMATCH_15 `SPC1.tlu.trl1.hstick3_compare
4433
4434`define HINTP_REG_15 `SPC1.tlu.trl1.hintp3
4435`define HSTM_TAKEN_15 `SPC1.tlu.trl1.take_hst&`SPC1.tlu.trl1.trap[3]
4436
4437`define NAS_PIPE_FW2_15 |`TOP.nas_top.c1.t7.complete_fw2
4438
4439`define CWQ_TAKEN_15 `SPC1.tlu.trl1.take_cwq&`SPC1.tlu.trl1.trap[3]
4440`define SMA_TAKEN_15 `SPC1.tlu.trl1.take_sma&`SPC1.tlu.trl1.trap[3]
4441
4442`define POR_TAKEN_15 `SPC1.tlu.trl1.take_por&`SPC1.tlu.trl1.trap[3]
4443
4444/////////////////////////////// Probes //////////////////////////////////// }}}
4445
4446always @(negedge (`BENCH_SPC1_GCLK & ready)) begin // {
4447
4448 // {{{ DETECT, PIPE & SEND
4449 take_disrupting_w <= (`INT_VEC_TAKEN_15 || `CPU_MONDO_TAKEN_15 ||
4450 `DEV_MONDO_TAKEN_15 || `RES_MONDO_TAKEN_15 ||
4451 `XIR_TAKEN_15 || `INT_LEVEL_TAKEN_15 ||
4452 `HSTM_TAKEN_15 || `CWQ_TAKEN_15 ||
4453 `SMA_TAKEN_15 || `PMU_TAKEN_15 || `POR_TAKEN_15);
4454 take_disrupting_fx4 <= take_disrupting_w;
4455 take_disrupting_fx5 <= take_disrupting_fx4;
4456 take_disrupting_fb <= take_disrupting_fx5;
4457 take_disrupting_fw <= take_disrupting_fb;
4458 take_disrupting_fw1 <= take_disrupting_fw;
4459 take_disrupting_fw2 <= take_disrupting_fw1;
4460
4461 case ({`INT_VEC_TAKEN_15, `CPU_MONDO_TAKEN_15,
4462 `DEV_MONDO_TAKEN_15, `RES_MONDO_TAKEN_15,
4463 `XIR_TAKEN_15, `INT_LEVEL_TAKEN_15,
4464 `HSTM_TAKEN_15, `CWQ_TAKEN_15, `SMA_TAKEN_15 ,
4465 `PMU_TAKEN_15, `POR_TAKEN_15})
4466 11'b10000000000: int_num_w <= 8'h60;
4467 11'b01000000000: int_num_w <= 8'h7c;
4468 11'b00100000000: int_num_w <= 8'h7d;
4469 11'b00010000000: int_num_w <= 8'h7e;
4470 11'b00001000000: int_num_w <= 8'h03;
4471 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_15;
4472 11'b00000010000: int_num_w <= 8'h5e;
4473 11'b00000001000: int_num_w <= 8'h3c;
4474 11'b00000000100: int_num_w <= 8'h3d;
4475 11'b00000000010: int_num_w <= 8'h4f;
4476 11'b00000000001: int_num_w <= 8'h01;
4477 endcase
4478
4479 int_num_fx4 <= int_num_w;
4480 int_num_fx5 <= int_num_fx4;
4481 int_num_fb <= int_num_fx5;
4482 int_num_fw <= int_num_fb;
4483 int_num_fw1 <= int_num_fw;
4484 int_num_fw2 <= int_num_fw1;
4485 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
4486 begin // {
4487 `PR_INFO ("pli_int", `INFO,
4488 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
4489 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
4490 end // }
4491
4492 // }}}
4493
4494/////////////////////////// Vectored Interrupt /////////////////////////// {{{
4495
4496 // Vectored Interrupt Recv Register Detection
4497 // Indicate when register changes due to arriving interrupt, and not
4498 // due to read of incoming register or ASI write ..
4499
4500
4501 // If any read occurs, send value right away.
4502 // While a read/write is pending, do not update delta.
4503 // Send non read/wr delta during fw2 ..
4504
4505
4506 if (!(`INT_VEC_RDWR_15 | `INT_VEC_RECV_ASIWR_15)) begin // {
4507 if (~`INT_VEC_RECV_ASIWR_15 &
4508 (int_vec_recv_reg !== `INT_VEC_RECV_REG_15 ))
4509 int_vec_recv_reg_delta <= 1'b1;
4510 int_vec_recv_reg <= `INT_VEC_RECV_REG_15;
4511 end // }
4512 else if (`INT_VEC_RECV_ASIWR_15)
4513 int_vec_recv_reg <= `TOP.nas_top.c1.t7.asi_updated_int_rec;
4514
4515 if ((`NAS_PIPE_FW2_15 & int_vec_recv_reg_delta ) |
4516 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
4517 `INT_VEC_RECV_ASIWR_15 ) begin // {
4518 `PR_INFO ("pli_int", `INFO,
4519 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
4520 mycid,mytid, int_vec_recv_reg);
4521 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4522 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
4523 64'h0, int_vec_recv_reg);
4524 end // }
4525 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_15 &
4526 (int_vec_recv_reg !== `INT_VEC_RECV_REG_15 ))))
4527 int_vec_recv_reg_delta <= 1'b0;
4528 end //}
4529
4530 int_vec_reg_rdwr <= `INT_VEC_RDWR_15 | `INT_VEC_RECV_ASIWR_15;
4531 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_15 & ~ inc_vec_reg_rd;
4532
4533 if (`INT_VEC_RECV_ASIWR_15)
4534 inc_vec_reg_rd <= 1'b1;
4535 if (`NAS_PIPE_FW2_15)
4536 inc_vec_reg_rd <= 1'b0;
4537
4538
4539/////////////////////////// Vectored Interrupt /////////////////////////// }}}
4540
4541/////////////////////////// Asynchronous Resets ////////////////////////// {{{
4542
4543
4544/////////////////////////// Asynchronous Resets ////////////////////////// }}}
4545
4546/////////////////////////// Softint ///////////////////////////////////// {{{
4547
4548 // Softint Register hardware Update Detection
4549
4550 // Non software updates (TM/SM)
4551
4552 // If any read occurs, send value right away.
4553 // While a read/write is pending, do not update delta.
4554 // Send non read/wr delta during fw2 ..
4555
4556 // RTL keeps pic_ovf indication in rd_softint and not softint.
4557 // So for set/clear writes, we send softint before the write ..,
4558 // and for read/asyncs we send rd_softint ..
4559
4560
4561 if (~`SOFTINT_RDWR_15) begin // {
4562 if (softint !== `RD_SOFTINT_REG_15 )
4563 softint_delta <= 1'b1;
4564 softint <= `RD_SOFTINT_REG_15;
4565 end // }
4566
4567 if ((`NAS_PIPE_FW2_15 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
4568 ) begin // {
4569 `PR_INFO ("pli_int", `INFO,
4570 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4571 mycid,mytid, {47'h0, softint});
4572 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4573 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4574 {47'h0, softint});
4575 end // }
4576 if (!(~`SOFTINT_RDWR_15&(softint !== `RD_SOFTINT_REG_15)))
4577 softint_delta <= 1'b0;
4578 end //}
4579 else if (`SPC1.tlu.asi_wr_clear_softint[7] |
4580 `SPC1.tlu.asi_wr_set_softint[7] ) begin // {
4581 `PR_INFO ("pli_int", `INFO,
4582 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4583 mycid,mytid, {47'h0, `RD_SOFTINT_REG_15});
4584 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4585 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4586 {47'h0, `RD_SOFTINT_REG_15});
4587 end // }
4588 end //}
4589
4590
4591 softint_rdwr <= `SOFTINT_RDWR_15 ;
4592 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_15;
4593
4594
4595/////////////////////////// Softint ///////////////////////////////////// }}}
4596
4597/////////////////////////// Hintp ///////////////////////////////////// {{{
4598
4599 // Hintp Register hardware Update Detection
4600
4601 // Non software updates (HSP)
4602 // If HINTP is already read/written by SW, then don't send
4603 // any async updates to Nas. Reads/Writes pending sstep is detected
4604 // by snooping nas_pipe ..
4605
4606 hintp <= `HINTP_REG_15 ;
4607 if (hstmatch_late)
4608 hintp_delta <= 1'b1;
4609
4610 if ((~hintp_rdwr & `NAS_PIPE_FW2_15 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
4611 (hintp_rdwr_late & hintp_delta) ) begin // {
4612 `PR_INFO ("pli_int", `INFO,
4613 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
4614 mycid,mytid, {63'h0, hintp});
4615 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4616 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
4617 {63'h0, hintp});
4618 end // }
4619 if (~(hintp_rdwr_late & hintp_delta))
4620 hintp_delta <= 1'b0;
4621 end //}
4622
4623 hintp_rdwr <= `HINTP_RDWR_15;
4624 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_15;
4625 hstmatch_late <= `HSTMATCH_15;
4626
4627
4628/////////////////////////// Hintp ///////////////////////////////////// }}}
4629
4630end //}
4631`endif
4632endmodule
4633
4634`endif
4635`ifdef CORE_2
4636
4637// }}}
4638
4639module int_c2t0 ();
4640`ifndef GATESIM
4641
4642// common defines
4643`include "defines.vh"
4644`include "ccx.vri"
4645`include "cmp.vri"
4646
4647wire [2:0] mycid;
4648wire [2:0] mytid;
4649wire [5:0] mytnum;
4650integer junk;
4651
4652reg [63:0] int_vec_recv_reg;
4653reg int_vec_recv_reg_delta;
4654reg int_vec_reg_rdwr;
4655reg inc_vec_reg_rd;
4656reg int_vec_reg_rdwr_late;
4657reg [16:0] softint;
4658reg softint_rdwr;
4659reg softint_rdwr_late;
4660reg softint_delta;
4661reg hintp;
4662reg hintp_rdwr;
4663reg hintp_rdwr_late;
4664reg hintp_delta;
4665reg hstmatch_late;
4666reg ready;
4667reg [7:0] int_num_w;
4668reg [7:0] int_num_fx4;
4669reg [7:0] int_num_fx5;
4670reg [7:0] int_num_fb;
4671reg [7:0] int_num_fw;
4672reg [7:0] int_num_fw1;
4673reg [7:0] int_num_fw2;
4674reg take_disrupting_w;
4675reg take_disrupting_fx4;
4676reg take_disrupting_fx5;
4677reg take_disrupting_fb;
4678reg take_disrupting_fw;
4679reg take_disrupting_fw1;
4680reg take_disrupting_fw2;
4681
4682 assign mycid = 2;
4683 assign mytid = 0;
4684 assign mytnum = 2*8 + 0;
4685
4686initial begin // {
4687 ready = 0; // Wait for socket setup ..
4688 inc_vec_reg_rd <= 1'b0;
4689 int_vec_recv_reg_delta <= 1'b0;
4690 softint_delta <= 1'b0;
4691 hintp_delta <= 1'b0;
4692 int_vec_recv_reg = 64'b0;
4693 @(posedge `BENCH_SPC2_GCLK) ;
4694 @(posedge `BENCH_SPC2_GCLK) ;
4695 ready = `PARGS.int_sync_on;
4696end //}
4697
4698
4699/////////////////////////////// Probes //////////////////////////////////// {{{
4700
4701`define INT_VEC_RECV_REG_16 `SPC2.tlu.cth.int_rec0
4702`define INT_VEC_RECV_ASIWR_16 (`TOP.nas_top.c2.t0.asi_wr_int_rec_delay)
4703`define INT_VEC_RDWR_16 (`TOP.nas_top.c2.t0.asi_rdwr_int_rec)
4704`define INT_VEC_TAKEN_16 `SPC2.tlu.trl0.take_ivt&`SPC2.tlu.trl0.trap[0]
4705
4706`define CPU_MONDO_TAKEN_16 `SPC2.tlu.trl0.take_mqr&`SPC2.tlu.trl0.trap[0]
4707`define DEV_MONDO_TAKEN_16 `SPC2.tlu.trl0.take_dqr&`SPC2.tlu.trl0.trap[0]
4708`define RES_MONDO_TAKEN_16 `SPC2.tlu.trl0.take_rqr&`SPC2.tlu.trl0.trap[0]
4709
4710`define XIR_TAKEN_16 `SPC2.tlu.trl0.take_xir&`SPC2.tlu.trl0.trap[0]
4711
4712`define SOFTINT_RDWR_16 (`TOP.nas_top.c2.t0.asi_rdwr_softint|`TOP.nas_top.c2.t0.asi_wr_softint_delay)
4713
4714`define SOFTINT_REG_16 `SPC2.tlu.trl0.softint0
4715`define RD_SOFTINT_REG_16 `SPC2.tlu.trl0.rd_softint0
4716`define INT_LEVEL_TAKEN_16 `SPC2.tlu.trl0.take_iln&`SPC2.tlu.trl0.trap[0]
4717`define INT_LEVEL_NUM_16 `SPC2.tlu.trl0.int_level_n
4718`define PMU_TAKEN_16 `SPC2.tlu.trl0.take_pmu&`SPC2.tlu.trl0.trap[0]
4719
4720`define HINTP_RDWR_16 (`TOP.nas_top.c2.t0.asi_rdwr_hintp | `TOP.nas_top.c2.t0.asi_wr_hintp_delay)
4721`define HINTP_WR_16 (`SPC2.tlu.asi_wr_hintp[16])
4722`define HSTMATCH_16 `SPC2.tlu.trl0.hstick0_compare
4723
4724`define HINTP_REG_16 `SPC2.tlu.trl0.hintp0
4725`define HSTM_TAKEN_16 `SPC2.tlu.trl0.take_hst&`SPC2.tlu.trl0.trap[0]
4726
4727`define NAS_PIPE_FW2_16 |`TOP.nas_top.c2.t0.complete_fw2
4728
4729`define CWQ_TAKEN_16 `SPC2.tlu.trl0.take_cwq&`SPC2.tlu.trl0.trap[0]
4730`define SMA_TAKEN_16 `SPC2.tlu.trl0.take_sma&`SPC2.tlu.trl0.trap[0]
4731
4732`define POR_TAKEN_16 `SPC2.tlu.trl0.take_por&`SPC2.tlu.trl0.trap[0]
4733
4734/////////////////////////////// Probes //////////////////////////////////// }}}
4735
4736always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
4737
4738 // {{{ DETECT, PIPE & SEND
4739 take_disrupting_w <= (`INT_VEC_TAKEN_16 || `CPU_MONDO_TAKEN_16 ||
4740 `DEV_MONDO_TAKEN_16 || `RES_MONDO_TAKEN_16 ||
4741 `XIR_TAKEN_16 || `INT_LEVEL_TAKEN_16 ||
4742 `HSTM_TAKEN_16 || `CWQ_TAKEN_16 ||
4743 `SMA_TAKEN_16 || `PMU_TAKEN_16 || `POR_TAKEN_16);
4744 take_disrupting_fx4 <= take_disrupting_w;
4745 take_disrupting_fx5 <= take_disrupting_fx4;
4746 take_disrupting_fb <= take_disrupting_fx5;
4747 take_disrupting_fw <= take_disrupting_fb;
4748 take_disrupting_fw1 <= take_disrupting_fw;
4749 take_disrupting_fw2 <= take_disrupting_fw1;
4750
4751 case ({`INT_VEC_TAKEN_16, `CPU_MONDO_TAKEN_16,
4752 `DEV_MONDO_TAKEN_16, `RES_MONDO_TAKEN_16,
4753 `XIR_TAKEN_16, `INT_LEVEL_TAKEN_16,
4754 `HSTM_TAKEN_16, `CWQ_TAKEN_16, `SMA_TAKEN_16 ,
4755 `PMU_TAKEN_16, `POR_TAKEN_16})
4756 11'b10000000000: int_num_w <= 8'h60;
4757 11'b01000000000: int_num_w <= 8'h7c;
4758 11'b00100000000: int_num_w <= 8'h7d;
4759 11'b00010000000: int_num_w <= 8'h7e;
4760 11'b00001000000: int_num_w <= 8'h03;
4761 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_16;
4762 11'b00000010000: int_num_w <= 8'h5e;
4763 11'b00000001000: int_num_w <= 8'h3c;
4764 11'b00000000100: int_num_w <= 8'h3d;
4765 11'b00000000010: int_num_w <= 8'h4f;
4766 11'b00000000001: int_num_w <= 8'h01;
4767 endcase
4768
4769 int_num_fx4 <= int_num_w;
4770 int_num_fx5 <= int_num_fx4;
4771 int_num_fb <= int_num_fx5;
4772 int_num_fw <= int_num_fb;
4773 int_num_fw1 <= int_num_fw;
4774 int_num_fw2 <= int_num_fw1;
4775 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
4776 begin // {
4777 `PR_INFO ("pli_int", `INFO,
4778 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
4779 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
4780 end // }
4781
4782 // }}}
4783
4784/////////////////////////// Vectored Interrupt /////////////////////////// {{{
4785
4786 // Vectored Interrupt Recv Register Detection
4787 // Indicate when register changes due to arriving interrupt, and not
4788 // due to read of incoming register or ASI write ..
4789
4790
4791 // If any read occurs, send value right away.
4792 // While a read/write is pending, do not update delta.
4793 // Send non read/wr delta during fw2 ..
4794
4795
4796 if (!(`INT_VEC_RDWR_16 | `INT_VEC_RECV_ASIWR_16)) begin // {
4797 if (~`INT_VEC_RECV_ASIWR_16 &
4798 (int_vec_recv_reg !== `INT_VEC_RECV_REG_16 ))
4799 int_vec_recv_reg_delta <= 1'b1;
4800 int_vec_recv_reg <= `INT_VEC_RECV_REG_16;
4801 end // }
4802 else if (`INT_VEC_RECV_ASIWR_16)
4803 int_vec_recv_reg <= `TOP.nas_top.c2.t0.asi_updated_int_rec;
4804
4805 if ((`NAS_PIPE_FW2_16 & int_vec_recv_reg_delta ) |
4806 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
4807 `INT_VEC_RECV_ASIWR_16 ) begin // {
4808 `PR_INFO ("pli_int", `INFO,
4809 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
4810 mycid,mytid, int_vec_recv_reg);
4811 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4812 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
4813 64'h0, int_vec_recv_reg);
4814 end // }
4815 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_16 &
4816 (int_vec_recv_reg !== `INT_VEC_RECV_REG_16 ))))
4817 int_vec_recv_reg_delta <= 1'b0;
4818 end //}
4819
4820 int_vec_reg_rdwr <= `INT_VEC_RDWR_16 | `INT_VEC_RECV_ASIWR_16;
4821 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_16 & ~ inc_vec_reg_rd;
4822
4823 if (`INT_VEC_RECV_ASIWR_16)
4824 inc_vec_reg_rd <= 1'b1;
4825 if (`NAS_PIPE_FW2_16)
4826 inc_vec_reg_rd <= 1'b0;
4827
4828
4829/////////////////////////// Vectored Interrupt /////////////////////////// }}}
4830
4831/////////////////////////// Asynchronous Resets ////////////////////////// {{{
4832
4833
4834/////////////////////////// Asynchronous Resets ////////////////////////// }}}
4835
4836/////////////////////////// Softint ///////////////////////////////////// {{{
4837
4838 // Softint Register hardware Update Detection
4839
4840 // Non software updates (TM/SM)
4841
4842 // If any read occurs, send value right away.
4843 // While a read/write is pending, do not update delta.
4844 // Send non read/wr delta during fw2 ..
4845
4846 // RTL keeps pic_ovf indication in rd_softint and not softint.
4847 // So for set/clear writes, we send softint before the write ..,
4848 // and for read/asyncs we send rd_softint ..
4849
4850
4851 if (~`SOFTINT_RDWR_16) begin // {
4852 if (softint !== `RD_SOFTINT_REG_16 )
4853 softint_delta <= 1'b1;
4854 softint <= `RD_SOFTINT_REG_16;
4855 end // }
4856
4857 if ((`NAS_PIPE_FW2_16 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
4858 ) begin // {
4859 `PR_INFO ("pli_int", `INFO,
4860 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4861 mycid,mytid, {47'h0, softint});
4862 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4863 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4864 {47'h0, softint});
4865 end // }
4866 if (!(~`SOFTINT_RDWR_16&(softint !== `RD_SOFTINT_REG_16)))
4867 softint_delta <= 1'b0;
4868 end //}
4869 else if (`SPC2.tlu.asi_wr_clear_softint[0] |
4870 `SPC2.tlu.asi_wr_set_softint[0] ) begin // {
4871 `PR_INFO ("pli_int", `INFO,
4872 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
4873 mycid,mytid, {47'h0, `RD_SOFTINT_REG_16});
4874 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4875 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
4876 {47'h0, `RD_SOFTINT_REG_16});
4877 end // }
4878 end //}
4879
4880
4881 softint_rdwr <= `SOFTINT_RDWR_16 ;
4882 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_16;
4883
4884
4885/////////////////////////// Softint ///////////////////////////////////// }}}
4886
4887/////////////////////////// Hintp ///////////////////////////////////// {{{
4888
4889 // Hintp Register hardware Update Detection
4890
4891 // Non software updates (HSP)
4892 // If HINTP is already read/written by SW, then don't send
4893 // any async updates to Nas. Reads/Writes pending sstep is detected
4894 // by snooping nas_pipe ..
4895
4896 hintp <= `HINTP_REG_16 ;
4897 if (hstmatch_late)
4898 hintp_delta <= 1'b1;
4899
4900 if ((~hintp_rdwr & `NAS_PIPE_FW2_16 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
4901 (hintp_rdwr_late & hintp_delta) ) begin // {
4902 `PR_INFO ("pli_int", `INFO,
4903 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
4904 mycid,mytid, {63'h0, hintp});
4905 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
4906 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
4907 {63'h0, hintp});
4908 end // }
4909 if (~(hintp_rdwr_late & hintp_delta))
4910 hintp_delta <= 1'b0;
4911 end //}
4912
4913 hintp_rdwr <= `HINTP_RDWR_16;
4914 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_16;
4915 hstmatch_late <= `HSTMATCH_16;
4916
4917
4918/////////////////////////// Hintp ///////////////////////////////////// }}}
4919
4920end //}
4921`endif
4922endmodule
4923
4924// }}}
4925
4926module int_c2t1 ();
4927`ifndef GATESIM
4928
4929// common defines
4930`include "defines.vh"
4931`include "ccx.vri"
4932`include "cmp.vri"
4933
4934wire [2:0] mycid;
4935wire [2:0] mytid;
4936wire [5:0] mytnum;
4937integer junk;
4938
4939reg [63:0] int_vec_recv_reg;
4940reg int_vec_recv_reg_delta;
4941reg int_vec_reg_rdwr;
4942reg inc_vec_reg_rd;
4943reg int_vec_reg_rdwr_late;
4944reg [16:0] softint;
4945reg softint_rdwr;
4946reg softint_rdwr_late;
4947reg softint_delta;
4948reg hintp;
4949reg hintp_rdwr;
4950reg hintp_rdwr_late;
4951reg hintp_delta;
4952reg hstmatch_late;
4953reg ready;
4954reg [7:0] int_num_w;
4955reg [7:0] int_num_fx4;
4956reg [7:0] int_num_fx5;
4957reg [7:0] int_num_fb;
4958reg [7:0] int_num_fw;
4959reg [7:0] int_num_fw1;
4960reg [7:0] int_num_fw2;
4961reg take_disrupting_w;
4962reg take_disrupting_fx4;
4963reg take_disrupting_fx5;
4964reg take_disrupting_fb;
4965reg take_disrupting_fw;
4966reg take_disrupting_fw1;
4967reg take_disrupting_fw2;
4968
4969 assign mycid = 2;
4970 assign mytid = 1;
4971 assign mytnum = 2*8 + 1;
4972
4973initial begin // {
4974 ready = 0; // Wait for socket setup ..
4975 inc_vec_reg_rd <= 1'b0;
4976 int_vec_recv_reg_delta <= 1'b0;
4977 softint_delta <= 1'b0;
4978 hintp_delta <= 1'b0;
4979 int_vec_recv_reg = 64'b0;
4980 @(posedge `BENCH_SPC2_GCLK) ;
4981 @(posedge `BENCH_SPC2_GCLK) ;
4982 ready = `PARGS.int_sync_on;
4983end //}
4984
4985
4986/////////////////////////////// Probes //////////////////////////////////// {{{
4987
4988`define INT_VEC_RECV_REG_17 `SPC2.tlu.cth.int_rec1
4989`define INT_VEC_RECV_ASIWR_17 (`TOP.nas_top.c2.t1.asi_wr_int_rec_delay)
4990`define INT_VEC_RDWR_17 (`TOP.nas_top.c2.t1.asi_rdwr_int_rec)
4991`define INT_VEC_TAKEN_17 `SPC2.tlu.trl0.take_ivt&`SPC2.tlu.trl0.trap[1]
4992
4993`define CPU_MONDO_TAKEN_17 `SPC2.tlu.trl0.take_mqr&`SPC2.tlu.trl0.trap[1]
4994`define DEV_MONDO_TAKEN_17 `SPC2.tlu.trl0.take_dqr&`SPC2.tlu.trl0.trap[1]
4995`define RES_MONDO_TAKEN_17 `SPC2.tlu.trl0.take_rqr&`SPC2.tlu.trl0.trap[1]
4996
4997`define XIR_TAKEN_17 `SPC2.tlu.trl0.take_xir&`SPC2.tlu.trl0.trap[1]
4998
4999`define SOFTINT_RDWR_17 (`TOP.nas_top.c2.t1.asi_rdwr_softint|`TOP.nas_top.c2.t1.asi_wr_softint_delay)
5000
5001`define SOFTINT_REG_17 `SPC2.tlu.trl0.softint1
5002`define RD_SOFTINT_REG_17 `SPC2.tlu.trl0.rd_softint1
5003`define INT_LEVEL_TAKEN_17 `SPC2.tlu.trl0.take_iln&`SPC2.tlu.trl0.trap[1]
5004`define INT_LEVEL_NUM_17 `SPC2.tlu.trl0.int_level_n
5005`define PMU_TAKEN_17 `SPC2.tlu.trl0.take_pmu&`SPC2.tlu.trl0.trap[1]
5006
5007`define HINTP_RDWR_17 (`TOP.nas_top.c2.t1.asi_rdwr_hintp | `TOP.nas_top.c2.t1.asi_wr_hintp_delay)
5008`define HINTP_WR_17 (`SPC2.tlu.asi_wr_hintp[17])
5009`define HSTMATCH_17 `SPC2.tlu.trl0.hstick1_compare
5010
5011`define HINTP_REG_17 `SPC2.tlu.trl0.hintp1
5012`define HSTM_TAKEN_17 `SPC2.tlu.trl0.take_hst&`SPC2.tlu.trl0.trap[1]
5013
5014`define NAS_PIPE_FW2_17 |`TOP.nas_top.c2.t1.complete_fw2
5015
5016`define CWQ_TAKEN_17 `SPC2.tlu.trl0.take_cwq&`SPC2.tlu.trl0.trap[1]
5017`define SMA_TAKEN_17 `SPC2.tlu.trl0.take_sma&`SPC2.tlu.trl0.trap[1]
5018
5019`define POR_TAKEN_17 `SPC2.tlu.trl0.take_por&`SPC2.tlu.trl0.trap[1]
5020
5021/////////////////////////////// Probes //////////////////////////////////// }}}
5022
5023always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
5024
5025 // {{{ DETECT, PIPE & SEND
5026 take_disrupting_w <= (`INT_VEC_TAKEN_17 || `CPU_MONDO_TAKEN_17 ||
5027 `DEV_MONDO_TAKEN_17 || `RES_MONDO_TAKEN_17 ||
5028 `XIR_TAKEN_17 || `INT_LEVEL_TAKEN_17 ||
5029 `HSTM_TAKEN_17 || `CWQ_TAKEN_17 ||
5030 `SMA_TAKEN_17 || `PMU_TAKEN_17 || `POR_TAKEN_17);
5031 take_disrupting_fx4 <= take_disrupting_w;
5032 take_disrupting_fx5 <= take_disrupting_fx4;
5033 take_disrupting_fb <= take_disrupting_fx5;
5034 take_disrupting_fw <= take_disrupting_fb;
5035 take_disrupting_fw1 <= take_disrupting_fw;
5036 take_disrupting_fw2 <= take_disrupting_fw1;
5037
5038 case ({`INT_VEC_TAKEN_17, `CPU_MONDO_TAKEN_17,
5039 `DEV_MONDO_TAKEN_17, `RES_MONDO_TAKEN_17,
5040 `XIR_TAKEN_17, `INT_LEVEL_TAKEN_17,
5041 `HSTM_TAKEN_17, `CWQ_TAKEN_17, `SMA_TAKEN_17 ,
5042 `PMU_TAKEN_17, `POR_TAKEN_17})
5043 11'b10000000000: int_num_w <= 8'h60;
5044 11'b01000000000: int_num_w <= 8'h7c;
5045 11'b00100000000: int_num_w <= 8'h7d;
5046 11'b00010000000: int_num_w <= 8'h7e;
5047 11'b00001000000: int_num_w <= 8'h03;
5048 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_17;
5049 11'b00000010000: int_num_w <= 8'h5e;
5050 11'b00000001000: int_num_w <= 8'h3c;
5051 11'b00000000100: int_num_w <= 8'h3d;
5052 11'b00000000010: int_num_w <= 8'h4f;
5053 11'b00000000001: int_num_w <= 8'h01;
5054 endcase
5055
5056 int_num_fx4 <= int_num_w;
5057 int_num_fx5 <= int_num_fx4;
5058 int_num_fb <= int_num_fx5;
5059 int_num_fw <= int_num_fb;
5060 int_num_fw1 <= int_num_fw;
5061 int_num_fw2 <= int_num_fw1;
5062 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
5063 begin // {
5064 `PR_INFO ("pli_int", `INFO,
5065 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
5066 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5067 end // }
5068
5069 // }}}
5070
5071/////////////////////////// Vectored Interrupt /////////////////////////// {{{
5072
5073 // Vectored Interrupt Recv Register Detection
5074 // Indicate when register changes due to arriving interrupt, and not
5075 // due to read of incoming register or ASI write ..
5076
5077
5078 // If any read occurs, send value right away.
5079 // While a read/write is pending, do not update delta.
5080 // Send non read/wr delta during fw2 ..
5081
5082
5083 if (!(`INT_VEC_RDWR_17 | `INT_VEC_RECV_ASIWR_17)) begin // {
5084 if (~`INT_VEC_RECV_ASIWR_17 &
5085 (int_vec_recv_reg !== `INT_VEC_RECV_REG_17 ))
5086 int_vec_recv_reg_delta <= 1'b1;
5087 int_vec_recv_reg <= `INT_VEC_RECV_REG_17;
5088 end // }
5089 else if (`INT_VEC_RECV_ASIWR_17)
5090 int_vec_recv_reg <= `TOP.nas_top.c2.t1.asi_updated_int_rec;
5091
5092 if ((`NAS_PIPE_FW2_17 & int_vec_recv_reg_delta ) |
5093 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
5094 `INT_VEC_RECV_ASIWR_17 ) begin // {
5095 `PR_INFO ("pli_int", `INFO,
5096 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
5097 mycid,mytid, int_vec_recv_reg);
5098 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5099 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
5100 64'h0, int_vec_recv_reg);
5101 end // }
5102 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_17 &
5103 (int_vec_recv_reg !== `INT_VEC_RECV_REG_17 ))))
5104 int_vec_recv_reg_delta <= 1'b0;
5105 end //}
5106
5107 int_vec_reg_rdwr <= `INT_VEC_RDWR_17 | `INT_VEC_RECV_ASIWR_17;
5108 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_17 & ~ inc_vec_reg_rd;
5109
5110 if (`INT_VEC_RECV_ASIWR_17)
5111 inc_vec_reg_rd <= 1'b1;
5112 if (`NAS_PIPE_FW2_17)
5113 inc_vec_reg_rd <= 1'b0;
5114
5115
5116/////////////////////////// Vectored Interrupt /////////////////////////// }}}
5117
5118/////////////////////////// Asynchronous Resets ////////////////////////// {{{
5119
5120
5121/////////////////////////// Asynchronous Resets ////////////////////////// }}}
5122
5123/////////////////////////// Softint ///////////////////////////////////// {{{
5124
5125 // Softint Register hardware Update Detection
5126
5127 // Non software updates (TM/SM)
5128
5129 // If any read occurs, send value right away.
5130 // While a read/write is pending, do not update delta.
5131 // Send non read/wr delta during fw2 ..
5132
5133 // RTL keeps pic_ovf indication in rd_softint and not softint.
5134 // So for set/clear writes, we send softint before the write ..,
5135 // and for read/asyncs we send rd_softint ..
5136
5137
5138 if (~`SOFTINT_RDWR_17) begin // {
5139 if (softint !== `RD_SOFTINT_REG_17 )
5140 softint_delta <= 1'b1;
5141 softint <= `RD_SOFTINT_REG_17;
5142 end // }
5143
5144 if ((`NAS_PIPE_FW2_17 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
5145 ) begin // {
5146 `PR_INFO ("pli_int", `INFO,
5147 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
5148 mycid,mytid, {47'h0, softint});
5149 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5150 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
5151 {47'h0, softint});
5152 end // }
5153 if (!(~`SOFTINT_RDWR_17&(softint !== `RD_SOFTINT_REG_17)))
5154 softint_delta <= 1'b0;
5155 end //}
5156 else if (`SPC2.tlu.asi_wr_clear_softint[1] |
5157 `SPC2.tlu.asi_wr_set_softint[1] ) begin // {
5158 `PR_INFO ("pli_int", `INFO,
5159 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
5160 mycid,mytid, {47'h0, `RD_SOFTINT_REG_17});
5161 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5162 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
5163 {47'h0, `RD_SOFTINT_REG_17});
5164 end // }
5165 end //}
5166
5167
5168 softint_rdwr <= `SOFTINT_RDWR_17 ;
5169 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_17;
5170
5171
5172/////////////////////////// Softint ///////////////////////////////////// }}}
5173
5174/////////////////////////// Hintp ///////////////////////////////////// {{{
5175
5176 // Hintp Register hardware Update Detection
5177
5178 // Non software updates (HSP)
5179 // If HINTP is already read/written by SW, then don't send
5180 // any async updates to Nas. Reads/Writes pending sstep is detected
5181 // by snooping nas_pipe ..
5182
5183 hintp <= `HINTP_REG_17 ;
5184 if (hstmatch_late)
5185 hintp_delta <= 1'b1;
5186
5187 if ((~hintp_rdwr & `NAS_PIPE_FW2_17 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
5188 (hintp_rdwr_late & hintp_delta) ) begin // {
5189 `PR_INFO ("pli_int", `INFO,
5190 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
5191 mycid,mytid, {63'h0, hintp});
5192 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5193 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
5194 {63'h0, hintp});
5195 end // }
5196 if (~(hintp_rdwr_late & hintp_delta))
5197 hintp_delta <= 1'b0;
5198 end //}
5199
5200 hintp_rdwr <= `HINTP_RDWR_17;
5201 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_17;
5202 hstmatch_late <= `HSTMATCH_17;
5203
5204
5205/////////////////////////// Hintp ///////////////////////////////////// }}}
5206
5207end //}
5208`endif
5209endmodule
5210
5211// }}}
5212
5213module int_c2t2 ();
5214`ifndef GATESIM
5215
5216// common defines
5217`include "defines.vh"
5218`include "ccx.vri"
5219`include "cmp.vri"
5220
5221wire [2:0] mycid;
5222wire [2:0] mytid;
5223wire [5:0] mytnum;
5224integer junk;
5225
5226reg [63:0] int_vec_recv_reg;
5227reg int_vec_recv_reg_delta;
5228reg int_vec_reg_rdwr;
5229reg inc_vec_reg_rd;
5230reg int_vec_reg_rdwr_late;
5231reg [16:0] softint;
5232reg softint_rdwr;
5233reg softint_rdwr_late;
5234reg softint_delta;
5235reg hintp;
5236reg hintp_rdwr;
5237reg hintp_rdwr_late;
5238reg hintp_delta;
5239reg hstmatch_late;
5240reg ready;
5241reg [7:0] int_num_w;
5242reg [7:0] int_num_fx4;
5243reg [7:0] int_num_fx5;
5244reg [7:0] int_num_fb;
5245reg [7:0] int_num_fw;
5246reg [7:0] int_num_fw1;
5247reg [7:0] int_num_fw2;
5248reg take_disrupting_w;
5249reg take_disrupting_fx4;
5250reg take_disrupting_fx5;
5251reg take_disrupting_fb;
5252reg take_disrupting_fw;
5253reg take_disrupting_fw1;
5254reg take_disrupting_fw2;
5255
5256 assign mycid = 2;
5257 assign mytid = 2;
5258 assign mytnum = 2*8 + 2;
5259
5260initial begin // {
5261 ready = 0; // Wait for socket setup ..
5262 inc_vec_reg_rd <= 1'b0;
5263 int_vec_recv_reg_delta <= 1'b0;
5264 softint_delta <= 1'b0;
5265 hintp_delta <= 1'b0;
5266 int_vec_recv_reg = 64'b0;
5267 @(posedge `BENCH_SPC2_GCLK) ;
5268 @(posedge `BENCH_SPC2_GCLK) ;
5269 ready = `PARGS.int_sync_on;
5270end //}
5271
5272
5273/////////////////////////////// Probes //////////////////////////////////// {{{
5274
5275`define INT_VEC_RECV_REG_18 `SPC2.tlu.cth.int_rec2
5276`define INT_VEC_RECV_ASIWR_18 (`TOP.nas_top.c2.t2.asi_wr_int_rec_delay)
5277`define INT_VEC_RDWR_18 (`TOP.nas_top.c2.t2.asi_rdwr_int_rec)
5278`define INT_VEC_TAKEN_18 `SPC2.tlu.trl0.take_ivt&`SPC2.tlu.trl0.trap[2]
5279
5280`define CPU_MONDO_TAKEN_18 `SPC2.tlu.trl0.take_mqr&`SPC2.tlu.trl0.trap[2]
5281`define DEV_MONDO_TAKEN_18 `SPC2.tlu.trl0.take_dqr&`SPC2.tlu.trl0.trap[2]
5282`define RES_MONDO_TAKEN_18 `SPC2.tlu.trl0.take_rqr&`SPC2.tlu.trl0.trap[2]
5283
5284`define XIR_TAKEN_18 `SPC2.tlu.trl0.take_xir&`SPC2.tlu.trl0.trap[2]
5285
5286`define SOFTINT_RDWR_18 (`TOP.nas_top.c2.t2.asi_rdwr_softint|`TOP.nas_top.c2.t2.asi_wr_softint_delay)
5287
5288`define SOFTINT_REG_18 `SPC2.tlu.trl0.softint2
5289`define RD_SOFTINT_REG_18 `SPC2.tlu.trl0.rd_softint2
5290`define INT_LEVEL_TAKEN_18 `SPC2.tlu.trl0.take_iln&`SPC2.tlu.trl0.trap[2]
5291`define INT_LEVEL_NUM_18 `SPC2.tlu.trl0.int_level_n
5292`define PMU_TAKEN_18 `SPC2.tlu.trl0.take_pmu&`SPC2.tlu.trl0.trap[2]
5293
5294`define HINTP_RDWR_18 (`TOP.nas_top.c2.t2.asi_rdwr_hintp | `TOP.nas_top.c2.t2.asi_wr_hintp_delay)
5295`define HINTP_WR_18 (`SPC2.tlu.asi_wr_hintp[18])
5296`define HSTMATCH_18 `SPC2.tlu.trl0.hstick2_compare
5297
5298`define HINTP_REG_18 `SPC2.tlu.trl0.hintp2
5299`define HSTM_TAKEN_18 `SPC2.tlu.trl0.take_hst&`SPC2.tlu.trl0.trap[2]
5300
5301`define NAS_PIPE_FW2_18 |`TOP.nas_top.c2.t2.complete_fw2
5302
5303`define CWQ_TAKEN_18 `SPC2.tlu.trl0.take_cwq&`SPC2.tlu.trl0.trap[2]
5304`define SMA_TAKEN_18 `SPC2.tlu.trl0.take_sma&`SPC2.tlu.trl0.trap[2]
5305
5306`define POR_TAKEN_18 `SPC2.tlu.trl0.take_por&`SPC2.tlu.trl0.trap[2]
5307
5308/////////////////////////////// Probes //////////////////////////////////// }}}
5309
5310always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
5311
5312 // {{{ DETECT, PIPE & SEND
5313 take_disrupting_w <= (`INT_VEC_TAKEN_18 || `CPU_MONDO_TAKEN_18 ||
5314 `DEV_MONDO_TAKEN_18 || `RES_MONDO_TAKEN_18 ||
5315 `XIR_TAKEN_18 || `INT_LEVEL_TAKEN_18 ||
5316 `HSTM_TAKEN_18 || `CWQ_TAKEN_18 ||
5317 `SMA_TAKEN_18 || `PMU_TAKEN_18 || `POR_TAKEN_18);
5318 take_disrupting_fx4 <= take_disrupting_w;
5319 take_disrupting_fx5 <= take_disrupting_fx4;
5320 take_disrupting_fb <= take_disrupting_fx5;
5321 take_disrupting_fw <= take_disrupting_fb;
5322 take_disrupting_fw1 <= take_disrupting_fw;
5323 take_disrupting_fw2 <= take_disrupting_fw1;
5324
5325 case ({`INT_VEC_TAKEN_18, `CPU_MONDO_TAKEN_18,
5326 `DEV_MONDO_TAKEN_18, `RES_MONDO_TAKEN_18,
5327 `XIR_TAKEN_18, `INT_LEVEL_TAKEN_18,
5328 `HSTM_TAKEN_18, `CWQ_TAKEN_18, `SMA_TAKEN_18 ,
5329 `PMU_TAKEN_18, `POR_TAKEN_18})
5330 11'b10000000000: int_num_w <= 8'h60;
5331 11'b01000000000: int_num_w <= 8'h7c;
5332 11'b00100000000: int_num_w <= 8'h7d;
5333 11'b00010000000: int_num_w <= 8'h7e;
5334 11'b00001000000: int_num_w <= 8'h03;
5335 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_18;
5336 11'b00000010000: int_num_w <= 8'h5e;
5337 11'b00000001000: int_num_w <= 8'h3c;
5338 11'b00000000100: int_num_w <= 8'h3d;
5339 11'b00000000010: int_num_w <= 8'h4f;
5340 11'b00000000001: int_num_w <= 8'h01;
5341 endcase
5342
5343 int_num_fx4 <= int_num_w;
5344 int_num_fx5 <= int_num_fx4;
5345 int_num_fb <= int_num_fx5;
5346 int_num_fw <= int_num_fb;
5347 int_num_fw1 <= int_num_fw;
5348 int_num_fw2 <= int_num_fw1;
5349 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
5350 begin // {
5351 `PR_INFO ("pli_int", `INFO,
5352 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
5353 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5354 end // }
5355
5356 // }}}
5357
5358/////////////////////////// Vectored Interrupt /////////////////////////// {{{
5359
5360 // Vectored Interrupt Recv Register Detection
5361 // Indicate when register changes due to arriving interrupt, and not
5362 // due to read of incoming register or ASI write ..
5363
5364
5365 // If any read occurs, send value right away.
5366 // While a read/write is pending, do not update delta.
5367 // Send non read/wr delta during fw2 ..
5368
5369
5370 if (!(`INT_VEC_RDWR_18 | `INT_VEC_RECV_ASIWR_18)) begin // {
5371 if (~`INT_VEC_RECV_ASIWR_18 &
5372 (int_vec_recv_reg !== `INT_VEC_RECV_REG_18 ))
5373 int_vec_recv_reg_delta <= 1'b1;
5374 int_vec_recv_reg <= `INT_VEC_RECV_REG_18;
5375 end // }
5376 else if (`INT_VEC_RECV_ASIWR_18)
5377 int_vec_recv_reg <= `TOP.nas_top.c2.t2.asi_updated_int_rec;
5378
5379 if ((`NAS_PIPE_FW2_18 & int_vec_recv_reg_delta ) |
5380 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
5381 `INT_VEC_RECV_ASIWR_18 ) begin // {
5382 `PR_INFO ("pli_int", `INFO,
5383 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
5384 mycid,mytid, int_vec_recv_reg);
5385 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5386 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
5387 64'h0, int_vec_recv_reg);
5388 end // }
5389 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_18 &
5390 (int_vec_recv_reg !== `INT_VEC_RECV_REG_18 ))))
5391 int_vec_recv_reg_delta <= 1'b0;
5392 end //}
5393
5394 int_vec_reg_rdwr <= `INT_VEC_RDWR_18 | `INT_VEC_RECV_ASIWR_18;
5395 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_18 & ~ inc_vec_reg_rd;
5396
5397 if (`INT_VEC_RECV_ASIWR_18)
5398 inc_vec_reg_rd <= 1'b1;
5399 if (`NAS_PIPE_FW2_18)
5400 inc_vec_reg_rd <= 1'b0;
5401
5402
5403/////////////////////////// Vectored Interrupt /////////////////////////// }}}
5404
5405/////////////////////////// Asynchronous Resets ////////////////////////// {{{
5406
5407
5408/////////////////////////// Asynchronous Resets ////////////////////////// }}}
5409
5410/////////////////////////// Softint ///////////////////////////////////// {{{
5411
5412 // Softint Register hardware Update Detection
5413
5414 // Non software updates (TM/SM)
5415
5416 // If any read occurs, send value right away.
5417 // While a read/write is pending, do not update delta.
5418 // Send non read/wr delta during fw2 ..
5419
5420 // RTL keeps pic_ovf indication in rd_softint and not softint.
5421 // So for set/clear writes, we send softint before the write ..,
5422 // and for read/asyncs we send rd_softint ..
5423
5424
5425 if (~`SOFTINT_RDWR_18) begin // {
5426 if (softint !== `RD_SOFTINT_REG_18 )
5427 softint_delta <= 1'b1;
5428 softint <= `RD_SOFTINT_REG_18;
5429 end // }
5430
5431 if ((`NAS_PIPE_FW2_18 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
5432 ) begin // {
5433 `PR_INFO ("pli_int", `INFO,
5434 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
5435 mycid,mytid, {47'h0, softint});
5436 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5437 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
5438 {47'h0, softint});
5439 end // }
5440 if (!(~`SOFTINT_RDWR_18&(softint !== `RD_SOFTINT_REG_18)))
5441 softint_delta <= 1'b0;
5442 end //}
5443 else if (`SPC2.tlu.asi_wr_clear_softint[2] |
5444 `SPC2.tlu.asi_wr_set_softint[2] ) begin // {
5445 `PR_INFO ("pli_int", `INFO,
5446 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
5447 mycid,mytid, {47'h0, `RD_SOFTINT_REG_18});
5448 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5449 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
5450 {47'h0, `RD_SOFTINT_REG_18});
5451 end // }
5452 end //}
5453
5454
5455 softint_rdwr <= `SOFTINT_RDWR_18 ;
5456 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_18;
5457
5458
5459/////////////////////////// Softint ///////////////////////////////////// }}}
5460
5461/////////////////////////// Hintp ///////////////////////////////////// {{{
5462
5463 // Hintp Register hardware Update Detection
5464
5465 // Non software updates (HSP)
5466 // If HINTP is already read/written by SW, then don't send
5467 // any async updates to Nas. Reads/Writes pending sstep is detected
5468 // by snooping nas_pipe ..
5469
5470 hintp <= `HINTP_REG_18 ;
5471 if (hstmatch_late)
5472 hintp_delta <= 1'b1;
5473
5474 if ((~hintp_rdwr & `NAS_PIPE_FW2_18 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
5475 (hintp_rdwr_late & hintp_delta) ) begin // {
5476 `PR_INFO ("pli_int", `INFO,
5477 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
5478 mycid,mytid, {63'h0, hintp});
5479 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5480 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
5481 {63'h0, hintp});
5482 end // }
5483 if (~(hintp_rdwr_late & hintp_delta))
5484 hintp_delta <= 1'b0;
5485 end //}
5486
5487 hintp_rdwr <= `HINTP_RDWR_18;
5488 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_18;
5489 hstmatch_late <= `HSTMATCH_18;
5490
5491
5492/////////////////////////// Hintp ///////////////////////////////////// }}}
5493
5494end //}
5495`endif
5496endmodule
5497
5498// }}}
5499
5500module int_c2t3 ();
5501`ifndef GATESIM
5502
5503// common defines
5504`include "defines.vh"
5505`include "ccx.vri"
5506`include "cmp.vri"
5507
5508wire [2:0] mycid;
5509wire [2:0] mytid;
5510wire [5:0] mytnum;
5511integer junk;
5512
5513reg [63:0] int_vec_recv_reg;
5514reg int_vec_recv_reg_delta;
5515reg int_vec_reg_rdwr;
5516reg inc_vec_reg_rd;
5517reg int_vec_reg_rdwr_late;
5518reg [16:0] softint;
5519reg softint_rdwr;
5520reg softint_rdwr_late;
5521reg softint_delta;
5522reg hintp;
5523reg hintp_rdwr;
5524reg hintp_rdwr_late;
5525reg hintp_delta;
5526reg hstmatch_late;
5527reg ready;
5528reg [7:0] int_num_w;
5529reg [7:0] int_num_fx4;
5530reg [7:0] int_num_fx5;
5531reg [7:0] int_num_fb;
5532reg [7:0] int_num_fw;
5533reg [7:0] int_num_fw1;
5534reg [7:0] int_num_fw2;
5535reg take_disrupting_w;
5536reg take_disrupting_fx4;
5537reg take_disrupting_fx5;
5538reg take_disrupting_fb;
5539reg take_disrupting_fw;
5540reg take_disrupting_fw1;
5541reg take_disrupting_fw2;
5542
5543 assign mycid = 2;
5544 assign mytid = 3;
5545 assign mytnum = 2*8 + 3;
5546
5547initial begin // {
5548 ready = 0; // Wait for socket setup ..
5549 inc_vec_reg_rd <= 1'b0;
5550 int_vec_recv_reg_delta <= 1'b0;
5551 softint_delta <= 1'b0;
5552 hintp_delta <= 1'b0;
5553 int_vec_recv_reg = 64'b0;
5554 @(posedge `BENCH_SPC2_GCLK) ;
5555 @(posedge `BENCH_SPC2_GCLK) ;
5556 ready = `PARGS.int_sync_on;
5557end //}
5558
5559
5560/////////////////////////////// Probes //////////////////////////////////// {{{
5561
5562`define INT_VEC_RECV_REG_19 `SPC2.tlu.cth.int_rec3
5563`define INT_VEC_RECV_ASIWR_19 (`TOP.nas_top.c2.t3.asi_wr_int_rec_delay)
5564`define INT_VEC_RDWR_19 (`TOP.nas_top.c2.t3.asi_rdwr_int_rec)
5565`define INT_VEC_TAKEN_19 `SPC2.tlu.trl0.take_ivt&`SPC2.tlu.trl0.trap[3]
5566
5567`define CPU_MONDO_TAKEN_19 `SPC2.tlu.trl0.take_mqr&`SPC2.tlu.trl0.trap[3]
5568`define DEV_MONDO_TAKEN_19 `SPC2.tlu.trl0.take_dqr&`SPC2.tlu.trl0.trap[3]
5569`define RES_MONDO_TAKEN_19 `SPC2.tlu.trl0.take_rqr&`SPC2.tlu.trl0.trap[3]
5570
5571`define XIR_TAKEN_19 `SPC2.tlu.trl0.take_xir&`SPC2.tlu.trl0.trap[3]
5572
5573`define SOFTINT_RDWR_19 (`TOP.nas_top.c2.t3.asi_rdwr_softint|`TOP.nas_top.c2.t3.asi_wr_softint_delay)
5574
5575`define SOFTINT_REG_19 `SPC2.tlu.trl0.softint3
5576`define RD_SOFTINT_REG_19 `SPC2.tlu.trl0.rd_softint3
5577`define INT_LEVEL_TAKEN_19 `SPC2.tlu.trl0.take_iln&`SPC2.tlu.trl0.trap[3]
5578`define INT_LEVEL_NUM_19 `SPC2.tlu.trl0.int_level_n
5579`define PMU_TAKEN_19 `SPC2.tlu.trl0.take_pmu&`SPC2.tlu.trl0.trap[3]
5580
5581`define HINTP_RDWR_19 (`TOP.nas_top.c2.t3.asi_rdwr_hintp | `TOP.nas_top.c2.t3.asi_wr_hintp_delay)
5582`define HINTP_WR_19 (`SPC2.tlu.asi_wr_hintp[19])
5583`define HSTMATCH_19 `SPC2.tlu.trl0.hstick3_compare
5584
5585`define HINTP_REG_19 `SPC2.tlu.trl0.hintp3
5586`define HSTM_TAKEN_19 `SPC2.tlu.trl0.take_hst&`SPC2.tlu.trl0.trap[3]
5587
5588`define NAS_PIPE_FW2_19 |`TOP.nas_top.c2.t3.complete_fw2
5589
5590`define CWQ_TAKEN_19 `SPC2.tlu.trl0.take_cwq&`SPC2.tlu.trl0.trap[3]
5591`define SMA_TAKEN_19 `SPC2.tlu.trl0.take_sma&`SPC2.tlu.trl0.trap[3]
5592
5593`define POR_TAKEN_19 `SPC2.tlu.trl0.take_por&`SPC2.tlu.trl0.trap[3]
5594
5595/////////////////////////////// Probes //////////////////////////////////// }}}
5596
5597always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
5598
5599 // {{{ DETECT, PIPE & SEND
5600 take_disrupting_w <= (`INT_VEC_TAKEN_19 || `CPU_MONDO_TAKEN_19 ||
5601 `DEV_MONDO_TAKEN_19 || `RES_MONDO_TAKEN_19 ||
5602 `XIR_TAKEN_19 || `INT_LEVEL_TAKEN_19 ||
5603 `HSTM_TAKEN_19 || `CWQ_TAKEN_19 ||
5604 `SMA_TAKEN_19 || `PMU_TAKEN_19 || `POR_TAKEN_19);
5605 take_disrupting_fx4 <= take_disrupting_w;
5606 take_disrupting_fx5 <= take_disrupting_fx4;
5607 take_disrupting_fb <= take_disrupting_fx5;
5608 take_disrupting_fw <= take_disrupting_fb;
5609 take_disrupting_fw1 <= take_disrupting_fw;
5610 take_disrupting_fw2 <= take_disrupting_fw1;
5611
5612 case ({`INT_VEC_TAKEN_19, `CPU_MONDO_TAKEN_19,
5613 `DEV_MONDO_TAKEN_19, `RES_MONDO_TAKEN_19,
5614 `XIR_TAKEN_19, `INT_LEVEL_TAKEN_19,
5615 `HSTM_TAKEN_19, `CWQ_TAKEN_19, `SMA_TAKEN_19 ,
5616 `PMU_TAKEN_19, `POR_TAKEN_19})
5617 11'b10000000000: int_num_w <= 8'h60;
5618 11'b01000000000: int_num_w <= 8'h7c;
5619 11'b00100000000: int_num_w <= 8'h7d;
5620 11'b00010000000: int_num_w <= 8'h7e;
5621 11'b00001000000: int_num_w <= 8'h03;
5622 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_19;
5623 11'b00000010000: int_num_w <= 8'h5e;
5624 11'b00000001000: int_num_w <= 8'h3c;
5625 11'b00000000100: int_num_w <= 8'h3d;
5626 11'b00000000010: int_num_w <= 8'h4f;
5627 11'b00000000001: int_num_w <= 8'h01;
5628 endcase
5629
5630 int_num_fx4 <= int_num_w;
5631 int_num_fx5 <= int_num_fx4;
5632 int_num_fb <= int_num_fx5;
5633 int_num_fw <= int_num_fb;
5634 int_num_fw1 <= int_num_fw;
5635 int_num_fw2 <= int_num_fw1;
5636 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
5637 begin // {
5638 `PR_INFO ("pli_int", `INFO,
5639 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
5640 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5641 end // }
5642
5643 // }}}
5644
5645/////////////////////////// Vectored Interrupt /////////////////////////// {{{
5646
5647 // Vectored Interrupt Recv Register Detection
5648 // Indicate when register changes due to arriving interrupt, and not
5649 // due to read of incoming register or ASI write ..
5650
5651
5652 // If any read occurs, send value right away.
5653 // While a read/write is pending, do not update delta.
5654 // Send non read/wr delta during fw2 ..
5655
5656
5657 if (!(`INT_VEC_RDWR_19 | `INT_VEC_RECV_ASIWR_19)) begin // {
5658 if (~`INT_VEC_RECV_ASIWR_19 &
5659 (int_vec_recv_reg !== `INT_VEC_RECV_REG_19 ))
5660 int_vec_recv_reg_delta <= 1'b1;
5661 int_vec_recv_reg <= `INT_VEC_RECV_REG_19;
5662 end // }
5663 else if (`INT_VEC_RECV_ASIWR_19)
5664 int_vec_recv_reg <= `TOP.nas_top.c2.t3.asi_updated_int_rec;
5665
5666 if ((`NAS_PIPE_FW2_19 & int_vec_recv_reg_delta ) |
5667 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
5668 `INT_VEC_RECV_ASIWR_19 ) begin // {
5669 `PR_INFO ("pli_int", `INFO,
5670 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
5671 mycid,mytid, int_vec_recv_reg);
5672 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5673 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
5674 64'h0, int_vec_recv_reg);
5675 end // }
5676 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_19 &
5677 (int_vec_recv_reg !== `INT_VEC_RECV_REG_19 ))))
5678 int_vec_recv_reg_delta <= 1'b0;
5679 end //}
5680
5681 int_vec_reg_rdwr <= `INT_VEC_RDWR_19 | `INT_VEC_RECV_ASIWR_19;
5682 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_19 & ~ inc_vec_reg_rd;
5683
5684 if (`INT_VEC_RECV_ASIWR_19)
5685 inc_vec_reg_rd <= 1'b1;
5686 if (`NAS_PIPE_FW2_19)
5687 inc_vec_reg_rd <= 1'b0;
5688
5689
5690/////////////////////////// Vectored Interrupt /////////////////////////// }}}
5691
5692/////////////////////////// Asynchronous Resets ////////////////////////// {{{
5693
5694
5695/////////////////////////// Asynchronous Resets ////////////////////////// }}}
5696
5697/////////////////////////// Softint ///////////////////////////////////// {{{
5698
5699 // Softint Register hardware Update Detection
5700
5701 // Non software updates (TM/SM)
5702
5703 // If any read occurs, send value right away.
5704 // While a read/write is pending, do not update delta.
5705 // Send non read/wr delta during fw2 ..
5706
5707 // RTL keeps pic_ovf indication in rd_softint and not softint.
5708 // So for set/clear writes, we send softint before the write ..,
5709 // and for read/asyncs we send rd_softint ..
5710
5711
5712 if (~`SOFTINT_RDWR_19) begin // {
5713 if (softint !== `RD_SOFTINT_REG_19 )
5714 softint_delta <= 1'b1;
5715 softint <= `RD_SOFTINT_REG_19;
5716 end // }
5717
5718 if ((`NAS_PIPE_FW2_19 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
5719 ) begin // {
5720 `PR_INFO ("pli_int", `INFO,
5721 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
5722 mycid,mytid, {47'h0, softint});
5723 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5724 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
5725 {47'h0, softint});
5726 end // }
5727 if (!(~`SOFTINT_RDWR_19&(softint !== `RD_SOFTINT_REG_19)))
5728 softint_delta <= 1'b0;
5729 end //}
5730 else if (`SPC2.tlu.asi_wr_clear_softint[3] |
5731 `SPC2.tlu.asi_wr_set_softint[3] ) begin // {
5732 `PR_INFO ("pli_int", `INFO,
5733 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
5734 mycid,mytid, {47'h0, `RD_SOFTINT_REG_19});
5735 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5736 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
5737 {47'h0, `RD_SOFTINT_REG_19});
5738 end // }
5739 end //}
5740
5741
5742 softint_rdwr <= `SOFTINT_RDWR_19 ;
5743 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_19;
5744
5745
5746/////////////////////////// Softint ///////////////////////////////////// }}}
5747
5748/////////////////////////// Hintp ///////////////////////////////////// {{{
5749
5750 // Hintp Register hardware Update Detection
5751
5752 // Non software updates (HSP)
5753 // If HINTP is already read/written by SW, then don't send
5754 // any async updates to Nas. Reads/Writes pending sstep is detected
5755 // by snooping nas_pipe ..
5756
5757 hintp <= `HINTP_REG_19 ;
5758 if (hstmatch_late)
5759 hintp_delta <= 1'b1;
5760
5761 if ((~hintp_rdwr & `NAS_PIPE_FW2_19 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
5762 (hintp_rdwr_late & hintp_delta) ) begin // {
5763 `PR_INFO ("pli_int", `INFO,
5764 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
5765 mycid,mytid, {63'h0, hintp});
5766 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5767 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
5768 {63'h0, hintp});
5769 end // }
5770 if (~(hintp_rdwr_late & hintp_delta))
5771 hintp_delta <= 1'b0;
5772 end //}
5773
5774 hintp_rdwr <= `HINTP_RDWR_19;
5775 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_19;
5776 hstmatch_late <= `HSTMATCH_19;
5777
5778
5779/////////////////////////// Hintp ///////////////////////////////////// }}}
5780
5781end //}
5782`endif
5783endmodule
5784
5785// }}}
5786
5787module int_c2t4 ();
5788`ifndef GATESIM
5789
5790// common defines
5791`include "defines.vh"
5792`include "ccx.vri"
5793`include "cmp.vri"
5794
5795wire [2:0] mycid;
5796wire [2:0] mytid;
5797wire [5:0] mytnum;
5798integer junk;
5799
5800reg [63:0] int_vec_recv_reg;
5801reg int_vec_recv_reg_delta;
5802reg int_vec_reg_rdwr;
5803reg inc_vec_reg_rd;
5804reg int_vec_reg_rdwr_late;
5805reg [16:0] softint;
5806reg softint_rdwr;
5807reg softint_rdwr_late;
5808reg softint_delta;
5809reg hintp;
5810reg hintp_rdwr;
5811reg hintp_rdwr_late;
5812reg hintp_delta;
5813reg hstmatch_late;
5814reg ready;
5815reg [7:0] int_num_w;
5816reg [7:0] int_num_fx4;
5817reg [7:0] int_num_fx5;
5818reg [7:0] int_num_fb;
5819reg [7:0] int_num_fw;
5820reg [7:0] int_num_fw1;
5821reg [7:0] int_num_fw2;
5822reg take_disrupting_w;
5823reg take_disrupting_fx4;
5824reg take_disrupting_fx5;
5825reg take_disrupting_fb;
5826reg take_disrupting_fw;
5827reg take_disrupting_fw1;
5828reg take_disrupting_fw2;
5829
5830 assign mycid = 2;
5831 assign mytid = 4;
5832 assign mytnum = 2*8 + 4;
5833
5834initial begin // {
5835 ready = 0; // Wait for socket setup ..
5836 inc_vec_reg_rd <= 1'b0;
5837 int_vec_recv_reg_delta <= 1'b0;
5838 softint_delta <= 1'b0;
5839 hintp_delta <= 1'b0;
5840 int_vec_recv_reg = 64'b0;
5841 @(posedge `BENCH_SPC2_GCLK) ;
5842 @(posedge `BENCH_SPC2_GCLK) ;
5843 ready = `PARGS.int_sync_on;
5844end //}
5845
5846
5847/////////////////////////////// Probes //////////////////////////////////// {{{
5848
5849`define INT_VEC_RECV_REG_20 `SPC2.tlu.cth.int_rec4
5850`define INT_VEC_RECV_ASIWR_20 (`TOP.nas_top.c2.t4.asi_wr_int_rec_delay)
5851`define INT_VEC_RDWR_20 (`TOP.nas_top.c2.t4.asi_rdwr_int_rec)
5852`define INT_VEC_TAKEN_20 `SPC2.tlu.trl1.take_ivt&`SPC2.tlu.trl1.trap[0]
5853
5854`define CPU_MONDO_TAKEN_20 `SPC2.tlu.trl1.take_mqr&`SPC2.tlu.trl1.trap[0]
5855`define DEV_MONDO_TAKEN_20 `SPC2.tlu.trl1.take_dqr&`SPC2.tlu.trl1.trap[0]
5856`define RES_MONDO_TAKEN_20 `SPC2.tlu.trl1.take_rqr&`SPC2.tlu.trl1.trap[0]
5857
5858`define XIR_TAKEN_20 `SPC2.tlu.trl1.take_xir&`SPC2.tlu.trl1.trap[0]
5859
5860`define SOFTINT_RDWR_20 (`TOP.nas_top.c2.t4.asi_rdwr_softint|`TOP.nas_top.c2.t4.asi_wr_softint_delay)
5861
5862`define SOFTINT_REG_20 `SPC2.tlu.trl1.softint0
5863`define RD_SOFTINT_REG_20 `SPC2.tlu.trl1.rd_softint0
5864`define INT_LEVEL_TAKEN_20 `SPC2.tlu.trl1.take_iln&`SPC2.tlu.trl1.trap[0]
5865`define INT_LEVEL_NUM_20 `SPC2.tlu.trl1.int_level_n
5866`define PMU_TAKEN_20 `SPC2.tlu.trl1.take_pmu&`SPC2.tlu.trl1.trap[0]
5867
5868`define HINTP_RDWR_20 (`TOP.nas_top.c2.t4.asi_rdwr_hintp | `TOP.nas_top.c2.t4.asi_wr_hintp_delay)
5869`define HINTP_WR_20 (`SPC2.tlu.asi_wr_hintp[20])
5870`define HSTMATCH_20 `SPC2.tlu.trl1.hstick0_compare
5871
5872`define HINTP_REG_20 `SPC2.tlu.trl1.hintp0
5873`define HSTM_TAKEN_20 `SPC2.tlu.trl1.take_hst&`SPC2.tlu.trl1.trap[0]
5874
5875`define NAS_PIPE_FW2_20 |`TOP.nas_top.c2.t4.complete_fw2
5876
5877`define CWQ_TAKEN_20 `SPC2.tlu.trl1.take_cwq&`SPC2.tlu.trl1.trap[0]
5878`define SMA_TAKEN_20 `SPC2.tlu.trl1.take_sma&`SPC2.tlu.trl1.trap[0]
5879
5880`define POR_TAKEN_20 `SPC2.tlu.trl1.take_por&`SPC2.tlu.trl1.trap[0]
5881
5882/////////////////////////////// Probes //////////////////////////////////// }}}
5883
5884always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
5885
5886 // {{{ DETECT, PIPE & SEND
5887 take_disrupting_w <= (`INT_VEC_TAKEN_20 || `CPU_MONDO_TAKEN_20 ||
5888 `DEV_MONDO_TAKEN_20 || `RES_MONDO_TAKEN_20 ||
5889 `XIR_TAKEN_20 || `INT_LEVEL_TAKEN_20 ||
5890 `HSTM_TAKEN_20 || `CWQ_TAKEN_20 ||
5891 `SMA_TAKEN_20 || `PMU_TAKEN_20 || `POR_TAKEN_20);
5892 take_disrupting_fx4 <= take_disrupting_w;
5893 take_disrupting_fx5 <= take_disrupting_fx4;
5894 take_disrupting_fb <= take_disrupting_fx5;
5895 take_disrupting_fw <= take_disrupting_fb;
5896 take_disrupting_fw1 <= take_disrupting_fw;
5897 take_disrupting_fw2 <= take_disrupting_fw1;
5898
5899 case ({`INT_VEC_TAKEN_20, `CPU_MONDO_TAKEN_20,
5900 `DEV_MONDO_TAKEN_20, `RES_MONDO_TAKEN_20,
5901 `XIR_TAKEN_20, `INT_LEVEL_TAKEN_20,
5902 `HSTM_TAKEN_20, `CWQ_TAKEN_20, `SMA_TAKEN_20 ,
5903 `PMU_TAKEN_20, `POR_TAKEN_20})
5904 11'b10000000000: int_num_w <= 8'h60;
5905 11'b01000000000: int_num_w <= 8'h7c;
5906 11'b00100000000: int_num_w <= 8'h7d;
5907 11'b00010000000: int_num_w <= 8'h7e;
5908 11'b00001000000: int_num_w <= 8'h03;
5909 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_20;
5910 11'b00000010000: int_num_w <= 8'h5e;
5911 11'b00000001000: int_num_w <= 8'h3c;
5912 11'b00000000100: int_num_w <= 8'h3d;
5913 11'b00000000010: int_num_w <= 8'h4f;
5914 11'b00000000001: int_num_w <= 8'h01;
5915 endcase
5916
5917 int_num_fx4 <= int_num_w;
5918 int_num_fx5 <= int_num_fx4;
5919 int_num_fb <= int_num_fx5;
5920 int_num_fw <= int_num_fb;
5921 int_num_fw1 <= int_num_fw;
5922 int_num_fw2 <= int_num_fw1;
5923 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
5924 begin // {
5925 `PR_INFO ("pli_int", `INFO,
5926 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
5927 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
5928 end // }
5929
5930 // }}}
5931
5932/////////////////////////// Vectored Interrupt /////////////////////////// {{{
5933
5934 // Vectored Interrupt Recv Register Detection
5935 // Indicate when register changes due to arriving interrupt, and not
5936 // due to read of incoming register or ASI write ..
5937
5938
5939 // If any read occurs, send value right away.
5940 // While a read/write is pending, do not update delta.
5941 // Send non read/wr delta during fw2 ..
5942
5943
5944 if (!(`INT_VEC_RDWR_20 | `INT_VEC_RECV_ASIWR_20)) begin // {
5945 if (~`INT_VEC_RECV_ASIWR_20 &
5946 (int_vec_recv_reg !== `INT_VEC_RECV_REG_20 ))
5947 int_vec_recv_reg_delta <= 1'b1;
5948 int_vec_recv_reg <= `INT_VEC_RECV_REG_20;
5949 end // }
5950 else if (`INT_VEC_RECV_ASIWR_20)
5951 int_vec_recv_reg <= `TOP.nas_top.c2.t4.asi_updated_int_rec;
5952
5953 if ((`NAS_PIPE_FW2_20 & int_vec_recv_reg_delta ) |
5954 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
5955 `INT_VEC_RECV_ASIWR_20 ) begin // {
5956 `PR_INFO ("pli_int", `INFO,
5957 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
5958 mycid,mytid, int_vec_recv_reg);
5959 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
5960 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
5961 64'h0, int_vec_recv_reg);
5962 end // }
5963 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_20 &
5964 (int_vec_recv_reg !== `INT_VEC_RECV_REG_20 ))))
5965 int_vec_recv_reg_delta <= 1'b0;
5966 end //}
5967
5968 int_vec_reg_rdwr <= `INT_VEC_RDWR_20 | `INT_VEC_RECV_ASIWR_20;
5969 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_20 & ~ inc_vec_reg_rd;
5970
5971 if (`INT_VEC_RECV_ASIWR_20)
5972 inc_vec_reg_rd <= 1'b1;
5973 if (`NAS_PIPE_FW2_20)
5974 inc_vec_reg_rd <= 1'b0;
5975
5976
5977/////////////////////////// Vectored Interrupt /////////////////////////// }}}
5978
5979/////////////////////////// Asynchronous Resets ////////////////////////// {{{
5980
5981
5982/////////////////////////// Asynchronous Resets ////////////////////////// }}}
5983
5984/////////////////////////// Softint ///////////////////////////////////// {{{
5985
5986 // Softint Register hardware Update Detection
5987
5988 // Non software updates (TM/SM)
5989
5990 // If any read occurs, send value right away.
5991 // While a read/write is pending, do not update delta.
5992 // Send non read/wr delta during fw2 ..
5993
5994 // RTL keeps pic_ovf indication in rd_softint and not softint.
5995 // So for set/clear writes, we send softint before the write ..,
5996 // and for read/asyncs we send rd_softint ..
5997
5998
5999 if (~`SOFTINT_RDWR_20) begin // {
6000 if (softint !== `RD_SOFTINT_REG_20 )
6001 softint_delta <= 1'b1;
6002 softint <= `RD_SOFTINT_REG_20;
6003 end // }
6004
6005 if ((`NAS_PIPE_FW2_20 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
6006 ) begin // {
6007 `PR_INFO ("pli_int", `INFO,
6008 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6009 mycid,mytid, {47'h0, softint});
6010 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6011 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6012 {47'h0, softint});
6013 end // }
6014 if (!(~`SOFTINT_RDWR_20&(softint !== `RD_SOFTINT_REG_20)))
6015 softint_delta <= 1'b0;
6016 end //}
6017 else if (`SPC2.tlu.asi_wr_clear_softint[4] |
6018 `SPC2.tlu.asi_wr_set_softint[4] ) begin // {
6019 `PR_INFO ("pli_int", `INFO,
6020 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6021 mycid,mytid, {47'h0, `RD_SOFTINT_REG_20});
6022 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6023 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6024 {47'h0, `RD_SOFTINT_REG_20});
6025 end // }
6026 end //}
6027
6028
6029 softint_rdwr <= `SOFTINT_RDWR_20 ;
6030 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_20;
6031
6032
6033/////////////////////////// Softint ///////////////////////////////////// }}}
6034
6035/////////////////////////// Hintp ///////////////////////////////////// {{{
6036
6037 // Hintp Register hardware Update Detection
6038
6039 // Non software updates (HSP)
6040 // If HINTP is already read/written by SW, then don't send
6041 // any async updates to Nas. Reads/Writes pending sstep is detected
6042 // by snooping nas_pipe ..
6043
6044 hintp <= `HINTP_REG_20 ;
6045 if (hstmatch_late)
6046 hintp_delta <= 1'b1;
6047
6048 if ((~hintp_rdwr & `NAS_PIPE_FW2_20 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
6049 (hintp_rdwr_late & hintp_delta) ) begin // {
6050 `PR_INFO ("pli_int", `INFO,
6051 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
6052 mycid,mytid, {63'h0, hintp});
6053 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6054 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
6055 {63'h0, hintp});
6056 end // }
6057 if (~(hintp_rdwr_late & hintp_delta))
6058 hintp_delta <= 1'b0;
6059 end //}
6060
6061 hintp_rdwr <= `HINTP_RDWR_20;
6062 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_20;
6063 hstmatch_late <= `HSTMATCH_20;
6064
6065
6066/////////////////////////// Hintp ///////////////////////////////////// }}}
6067
6068end //}
6069`endif
6070endmodule
6071
6072// }}}
6073
6074module int_c2t5 ();
6075`ifndef GATESIM
6076
6077// common defines
6078`include "defines.vh"
6079`include "ccx.vri"
6080`include "cmp.vri"
6081
6082wire [2:0] mycid;
6083wire [2:0] mytid;
6084wire [5:0] mytnum;
6085integer junk;
6086
6087reg [63:0] int_vec_recv_reg;
6088reg int_vec_recv_reg_delta;
6089reg int_vec_reg_rdwr;
6090reg inc_vec_reg_rd;
6091reg int_vec_reg_rdwr_late;
6092reg [16:0] softint;
6093reg softint_rdwr;
6094reg softint_rdwr_late;
6095reg softint_delta;
6096reg hintp;
6097reg hintp_rdwr;
6098reg hintp_rdwr_late;
6099reg hintp_delta;
6100reg hstmatch_late;
6101reg ready;
6102reg [7:0] int_num_w;
6103reg [7:0] int_num_fx4;
6104reg [7:0] int_num_fx5;
6105reg [7:0] int_num_fb;
6106reg [7:0] int_num_fw;
6107reg [7:0] int_num_fw1;
6108reg [7:0] int_num_fw2;
6109reg take_disrupting_w;
6110reg take_disrupting_fx4;
6111reg take_disrupting_fx5;
6112reg take_disrupting_fb;
6113reg take_disrupting_fw;
6114reg take_disrupting_fw1;
6115reg take_disrupting_fw2;
6116
6117 assign mycid = 2;
6118 assign mytid = 5;
6119 assign mytnum = 2*8 + 5;
6120
6121initial begin // {
6122 ready = 0; // Wait for socket setup ..
6123 inc_vec_reg_rd <= 1'b0;
6124 int_vec_recv_reg_delta <= 1'b0;
6125 softint_delta <= 1'b0;
6126 hintp_delta <= 1'b0;
6127 int_vec_recv_reg = 64'b0;
6128 @(posedge `BENCH_SPC2_GCLK) ;
6129 @(posedge `BENCH_SPC2_GCLK) ;
6130 ready = `PARGS.int_sync_on;
6131end //}
6132
6133
6134/////////////////////////////// Probes //////////////////////////////////// {{{
6135
6136`define INT_VEC_RECV_REG_21 `SPC2.tlu.cth.int_rec5
6137`define INT_VEC_RECV_ASIWR_21 (`TOP.nas_top.c2.t5.asi_wr_int_rec_delay)
6138`define INT_VEC_RDWR_21 (`TOP.nas_top.c2.t5.asi_rdwr_int_rec)
6139`define INT_VEC_TAKEN_21 `SPC2.tlu.trl1.take_ivt&`SPC2.tlu.trl1.trap[1]
6140
6141`define CPU_MONDO_TAKEN_21 `SPC2.tlu.trl1.take_mqr&`SPC2.tlu.trl1.trap[1]
6142`define DEV_MONDO_TAKEN_21 `SPC2.tlu.trl1.take_dqr&`SPC2.tlu.trl1.trap[1]
6143`define RES_MONDO_TAKEN_21 `SPC2.tlu.trl1.take_rqr&`SPC2.tlu.trl1.trap[1]
6144
6145`define XIR_TAKEN_21 `SPC2.tlu.trl1.take_xir&`SPC2.tlu.trl1.trap[1]
6146
6147`define SOFTINT_RDWR_21 (`TOP.nas_top.c2.t5.asi_rdwr_softint|`TOP.nas_top.c2.t5.asi_wr_softint_delay)
6148
6149`define SOFTINT_REG_21 `SPC2.tlu.trl1.softint1
6150`define RD_SOFTINT_REG_21 `SPC2.tlu.trl1.rd_softint1
6151`define INT_LEVEL_TAKEN_21 `SPC2.tlu.trl1.take_iln&`SPC2.tlu.trl1.trap[1]
6152`define INT_LEVEL_NUM_21 `SPC2.tlu.trl1.int_level_n
6153`define PMU_TAKEN_21 `SPC2.tlu.trl1.take_pmu&`SPC2.tlu.trl1.trap[1]
6154
6155`define HINTP_RDWR_21 (`TOP.nas_top.c2.t5.asi_rdwr_hintp | `TOP.nas_top.c2.t5.asi_wr_hintp_delay)
6156`define HINTP_WR_21 (`SPC2.tlu.asi_wr_hintp[21])
6157`define HSTMATCH_21 `SPC2.tlu.trl1.hstick1_compare
6158
6159`define HINTP_REG_21 `SPC2.tlu.trl1.hintp1
6160`define HSTM_TAKEN_21 `SPC2.tlu.trl1.take_hst&`SPC2.tlu.trl1.trap[1]
6161
6162`define NAS_PIPE_FW2_21 |`TOP.nas_top.c2.t5.complete_fw2
6163
6164`define CWQ_TAKEN_21 `SPC2.tlu.trl1.take_cwq&`SPC2.tlu.trl1.trap[1]
6165`define SMA_TAKEN_21 `SPC2.tlu.trl1.take_sma&`SPC2.tlu.trl1.trap[1]
6166
6167`define POR_TAKEN_21 `SPC2.tlu.trl1.take_por&`SPC2.tlu.trl1.trap[1]
6168
6169/////////////////////////////// Probes //////////////////////////////////// }}}
6170
6171always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
6172
6173 // {{{ DETECT, PIPE & SEND
6174 take_disrupting_w <= (`INT_VEC_TAKEN_21 || `CPU_MONDO_TAKEN_21 ||
6175 `DEV_MONDO_TAKEN_21 || `RES_MONDO_TAKEN_21 ||
6176 `XIR_TAKEN_21 || `INT_LEVEL_TAKEN_21 ||
6177 `HSTM_TAKEN_21 || `CWQ_TAKEN_21 ||
6178 `SMA_TAKEN_21 || `PMU_TAKEN_21 || `POR_TAKEN_21);
6179 take_disrupting_fx4 <= take_disrupting_w;
6180 take_disrupting_fx5 <= take_disrupting_fx4;
6181 take_disrupting_fb <= take_disrupting_fx5;
6182 take_disrupting_fw <= take_disrupting_fb;
6183 take_disrupting_fw1 <= take_disrupting_fw;
6184 take_disrupting_fw2 <= take_disrupting_fw1;
6185
6186 case ({`INT_VEC_TAKEN_21, `CPU_MONDO_TAKEN_21,
6187 `DEV_MONDO_TAKEN_21, `RES_MONDO_TAKEN_21,
6188 `XIR_TAKEN_21, `INT_LEVEL_TAKEN_21,
6189 `HSTM_TAKEN_21, `CWQ_TAKEN_21, `SMA_TAKEN_21 ,
6190 `PMU_TAKEN_21, `POR_TAKEN_21})
6191 11'b10000000000: int_num_w <= 8'h60;
6192 11'b01000000000: int_num_w <= 8'h7c;
6193 11'b00100000000: int_num_w <= 8'h7d;
6194 11'b00010000000: int_num_w <= 8'h7e;
6195 11'b00001000000: int_num_w <= 8'h03;
6196 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_21;
6197 11'b00000010000: int_num_w <= 8'h5e;
6198 11'b00000001000: int_num_w <= 8'h3c;
6199 11'b00000000100: int_num_w <= 8'h3d;
6200 11'b00000000010: int_num_w <= 8'h4f;
6201 11'b00000000001: int_num_w <= 8'h01;
6202 endcase
6203
6204 int_num_fx4 <= int_num_w;
6205 int_num_fx5 <= int_num_fx4;
6206 int_num_fb <= int_num_fx5;
6207 int_num_fw <= int_num_fb;
6208 int_num_fw1 <= int_num_fw;
6209 int_num_fw2 <= int_num_fw1;
6210 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
6211 begin // {
6212 `PR_INFO ("pli_int", `INFO,
6213 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
6214 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6215 end // }
6216
6217 // }}}
6218
6219/////////////////////////// Vectored Interrupt /////////////////////////// {{{
6220
6221 // Vectored Interrupt Recv Register Detection
6222 // Indicate when register changes due to arriving interrupt, and not
6223 // due to read of incoming register or ASI write ..
6224
6225
6226 // If any read occurs, send value right away.
6227 // While a read/write is pending, do not update delta.
6228 // Send non read/wr delta during fw2 ..
6229
6230
6231 if (!(`INT_VEC_RDWR_21 | `INT_VEC_RECV_ASIWR_21)) begin // {
6232 if (~`INT_VEC_RECV_ASIWR_21 &
6233 (int_vec_recv_reg !== `INT_VEC_RECV_REG_21 ))
6234 int_vec_recv_reg_delta <= 1'b1;
6235 int_vec_recv_reg <= `INT_VEC_RECV_REG_21;
6236 end // }
6237 else if (`INT_VEC_RECV_ASIWR_21)
6238 int_vec_recv_reg <= `TOP.nas_top.c2.t5.asi_updated_int_rec;
6239
6240 if ((`NAS_PIPE_FW2_21 & int_vec_recv_reg_delta ) |
6241 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
6242 `INT_VEC_RECV_ASIWR_21 ) begin // {
6243 `PR_INFO ("pli_int", `INFO,
6244 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
6245 mycid,mytid, int_vec_recv_reg);
6246 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6247 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
6248 64'h0, int_vec_recv_reg);
6249 end // }
6250 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_21 &
6251 (int_vec_recv_reg !== `INT_VEC_RECV_REG_21 ))))
6252 int_vec_recv_reg_delta <= 1'b0;
6253 end //}
6254
6255 int_vec_reg_rdwr <= `INT_VEC_RDWR_21 | `INT_VEC_RECV_ASIWR_21;
6256 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_21 & ~ inc_vec_reg_rd;
6257
6258 if (`INT_VEC_RECV_ASIWR_21)
6259 inc_vec_reg_rd <= 1'b1;
6260 if (`NAS_PIPE_FW2_21)
6261 inc_vec_reg_rd <= 1'b0;
6262
6263
6264/////////////////////////// Vectored Interrupt /////////////////////////// }}}
6265
6266/////////////////////////// Asynchronous Resets ////////////////////////// {{{
6267
6268
6269/////////////////////////// Asynchronous Resets ////////////////////////// }}}
6270
6271/////////////////////////// Softint ///////////////////////////////////// {{{
6272
6273 // Softint Register hardware Update Detection
6274
6275 // Non software updates (TM/SM)
6276
6277 // If any read occurs, send value right away.
6278 // While a read/write is pending, do not update delta.
6279 // Send non read/wr delta during fw2 ..
6280
6281 // RTL keeps pic_ovf indication in rd_softint and not softint.
6282 // So for set/clear writes, we send softint before the write ..,
6283 // and for read/asyncs we send rd_softint ..
6284
6285
6286 if (~`SOFTINT_RDWR_21) begin // {
6287 if (softint !== `RD_SOFTINT_REG_21 )
6288 softint_delta <= 1'b1;
6289 softint <= `RD_SOFTINT_REG_21;
6290 end // }
6291
6292 if ((`NAS_PIPE_FW2_21 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
6293 ) begin // {
6294 `PR_INFO ("pli_int", `INFO,
6295 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6296 mycid,mytid, {47'h0, softint});
6297 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6298 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6299 {47'h0, softint});
6300 end // }
6301 if (!(~`SOFTINT_RDWR_21&(softint !== `RD_SOFTINT_REG_21)))
6302 softint_delta <= 1'b0;
6303 end //}
6304 else if (`SPC2.tlu.asi_wr_clear_softint[5] |
6305 `SPC2.tlu.asi_wr_set_softint[5] ) begin // {
6306 `PR_INFO ("pli_int", `INFO,
6307 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6308 mycid,mytid, {47'h0, `RD_SOFTINT_REG_21});
6309 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6310 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6311 {47'h0, `RD_SOFTINT_REG_21});
6312 end // }
6313 end //}
6314
6315
6316 softint_rdwr <= `SOFTINT_RDWR_21 ;
6317 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_21;
6318
6319
6320/////////////////////////// Softint ///////////////////////////////////// }}}
6321
6322/////////////////////////// Hintp ///////////////////////////////////// {{{
6323
6324 // Hintp Register hardware Update Detection
6325
6326 // Non software updates (HSP)
6327 // If HINTP is already read/written by SW, then don't send
6328 // any async updates to Nas. Reads/Writes pending sstep is detected
6329 // by snooping nas_pipe ..
6330
6331 hintp <= `HINTP_REG_21 ;
6332 if (hstmatch_late)
6333 hintp_delta <= 1'b1;
6334
6335 if ((~hintp_rdwr & `NAS_PIPE_FW2_21 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
6336 (hintp_rdwr_late & hintp_delta) ) begin // {
6337 `PR_INFO ("pli_int", `INFO,
6338 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
6339 mycid,mytid, {63'h0, hintp});
6340 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6341 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
6342 {63'h0, hintp});
6343 end // }
6344 if (~(hintp_rdwr_late & hintp_delta))
6345 hintp_delta <= 1'b0;
6346 end //}
6347
6348 hintp_rdwr <= `HINTP_RDWR_21;
6349 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_21;
6350 hstmatch_late <= `HSTMATCH_21;
6351
6352
6353/////////////////////////// Hintp ///////////////////////////////////// }}}
6354
6355end //}
6356`endif
6357endmodule
6358
6359// }}}
6360
6361module int_c2t6 ();
6362`ifndef GATESIM
6363
6364// common defines
6365`include "defines.vh"
6366`include "ccx.vri"
6367`include "cmp.vri"
6368
6369wire [2:0] mycid;
6370wire [2:0] mytid;
6371wire [5:0] mytnum;
6372integer junk;
6373
6374reg [63:0] int_vec_recv_reg;
6375reg int_vec_recv_reg_delta;
6376reg int_vec_reg_rdwr;
6377reg inc_vec_reg_rd;
6378reg int_vec_reg_rdwr_late;
6379reg [16:0] softint;
6380reg softint_rdwr;
6381reg softint_rdwr_late;
6382reg softint_delta;
6383reg hintp;
6384reg hintp_rdwr;
6385reg hintp_rdwr_late;
6386reg hintp_delta;
6387reg hstmatch_late;
6388reg ready;
6389reg [7:0] int_num_w;
6390reg [7:0] int_num_fx4;
6391reg [7:0] int_num_fx5;
6392reg [7:0] int_num_fb;
6393reg [7:0] int_num_fw;
6394reg [7:0] int_num_fw1;
6395reg [7:0] int_num_fw2;
6396reg take_disrupting_w;
6397reg take_disrupting_fx4;
6398reg take_disrupting_fx5;
6399reg take_disrupting_fb;
6400reg take_disrupting_fw;
6401reg take_disrupting_fw1;
6402reg take_disrupting_fw2;
6403
6404 assign mycid = 2;
6405 assign mytid = 6;
6406 assign mytnum = 2*8 + 6;
6407
6408initial begin // {
6409 ready = 0; // Wait for socket setup ..
6410 inc_vec_reg_rd <= 1'b0;
6411 int_vec_recv_reg_delta <= 1'b0;
6412 softint_delta <= 1'b0;
6413 hintp_delta <= 1'b0;
6414 int_vec_recv_reg = 64'b0;
6415 @(posedge `BENCH_SPC2_GCLK) ;
6416 @(posedge `BENCH_SPC2_GCLK) ;
6417 ready = `PARGS.int_sync_on;
6418end //}
6419
6420
6421/////////////////////////////// Probes //////////////////////////////////// {{{
6422
6423`define INT_VEC_RECV_REG_22 `SPC2.tlu.cth.int_rec6
6424`define INT_VEC_RECV_ASIWR_22 (`TOP.nas_top.c2.t6.asi_wr_int_rec_delay)
6425`define INT_VEC_RDWR_22 (`TOP.nas_top.c2.t6.asi_rdwr_int_rec)
6426`define INT_VEC_TAKEN_22 `SPC2.tlu.trl1.take_ivt&`SPC2.tlu.trl1.trap[2]
6427
6428`define CPU_MONDO_TAKEN_22 `SPC2.tlu.trl1.take_mqr&`SPC2.tlu.trl1.trap[2]
6429`define DEV_MONDO_TAKEN_22 `SPC2.tlu.trl1.take_dqr&`SPC2.tlu.trl1.trap[2]
6430`define RES_MONDO_TAKEN_22 `SPC2.tlu.trl1.take_rqr&`SPC2.tlu.trl1.trap[2]
6431
6432`define XIR_TAKEN_22 `SPC2.tlu.trl1.take_xir&`SPC2.tlu.trl1.trap[2]
6433
6434`define SOFTINT_RDWR_22 (`TOP.nas_top.c2.t6.asi_rdwr_softint|`TOP.nas_top.c2.t6.asi_wr_softint_delay)
6435
6436`define SOFTINT_REG_22 `SPC2.tlu.trl1.softint2
6437`define RD_SOFTINT_REG_22 `SPC2.tlu.trl1.rd_softint2
6438`define INT_LEVEL_TAKEN_22 `SPC2.tlu.trl1.take_iln&`SPC2.tlu.trl1.trap[2]
6439`define INT_LEVEL_NUM_22 `SPC2.tlu.trl1.int_level_n
6440`define PMU_TAKEN_22 `SPC2.tlu.trl1.take_pmu&`SPC2.tlu.trl1.trap[2]
6441
6442`define HINTP_RDWR_22 (`TOP.nas_top.c2.t6.asi_rdwr_hintp | `TOP.nas_top.c2.t6.asi_wr_hintp_delay)
6443`define HINTP_WR_22 (`SPC2.tlu.asi_wr_hintp[22])
6444`define HSTMATCH_22 `SPC2.tlu.trl1.hstick2_compare
6445
6446`define HINTP_REG_22 `SPC2.tlu.trl1.hintp2
6447`define HSTM_TAKEN_22 `SPC2.tlu.trl1.take_hst&`SPC2.tlu.trl1.trap[2]
6448
6449`define NAS_PIPE_FW2_22 |`TOP.nas_top.c2.t6.complete_fw2
6450
6451`define CWQ_TAKEN_22 `SPC2.tlu.trl1.take_cwq&`SPC2.tlu.trl1.trap[2]
6452`define SMA_TAKEN_22 `SPC2.tlu.trl1.take_sma&`SPC2.tlu.trl1.trap[2]
6453
6454`define POR_TAKEN_22 `SPC2.tlu.trl1.take_por&`SPC2.tlu.trl1.trap[2]
6455
6456/////////////////////////////// Probes //////////////////////////////////// }}}
6457
6458always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
6459
6460 // {{{ DETECT, PIPE & SEND
6461 take_disrupting_w <= (`INT_VEC_TAKEN_22 || `CPU_MONDO_TAKEN_22 ||
6462 `DEV_MONDO_TAKEN_22 || `RES_MONDO_TAKEN_22 ||
6463 `XIR_TAKEN_22 || `INT_LEVEL_TAKEN_22 ||
6464 `HSTM_TAKEN_22 || `CWQ_TAKEN_22 ||
6465 `SMA_TAKEN_22 || `PMU_TAKEN_22 || `POR_TAKEN_22);
6466 take_disrupting_fx4 <= take_disrupting_w;
6467 take_disrupting_fx5 <= take_disrupting_fx4;
6468 take_disrupting_fb <= take_disrupting_fx5;
6469 take_disrupting_fw <= take_disrupting_fb;
6470 take_disrupting_fw1 <= take_disrupting_fw;
6471 take_disrupting_fw2 <= take_disrupting_fw1;
6472
6473 case ({`INT_VEC_TAKEN_22, `CPU_MONDO_TAKEN_22,
6474 `DEV_MONDO_TAKEN_22, `RES_MONDO_TAKEN_22,
6475 `XIR_TAKEN_22, `INT_LEVEL_TAKEN_22,
6476 `HSTM_TAKEN_22, `CWQ_TAKEN_22, `SMA_TAKEN_22 ,
6477 `PMU_TAKEN_22, `POR_TAKEN_22})
6478 11'b10000000000: int_num_w <= 8'h60;
6479 11'b01000000000: int_num_w <= 8'h7c;
6480 11'b00100000000: int_num_w <= 8'h7d;
6481 11'b00010000000: int_num_w <= 8'h7e;
6482 11'b00001000000: int_num_w <= 8'h03;
6483 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_22;
6484 11'b00000010000: int_num_w <= 8'h5e;
6485 11'b00000001000: int_num_w <= 8'h3c;
6486 11'b00000000100: int_num_w <= 8'h3d;
6487 11'b00000000010: int_num_w <= 8'h4f;
6488 11'b00000000001: int_num_w <= 8'h01;
6489 endcase
6490
6491 int_num_fx4 <= int_num_w;
6492 int_num_fx5 <= int_num_fx4;
6493 int_num_fb <= int_num_fx5;
6494 int_num_fw <= int_num_fb;
6495 int_num_fw1 <= int_num_fw;
6496 int_num_fw2 <= int_num_fw1;
6497 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
6498 begin // {
6499 `PR_INFO ("pli_int", `INFO,
6500 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
6501 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6502 end // }
6503
6504 // }}}
6505
6506/////////////////////////// Vectored Interrupt /////////////////////////// {{{
6507
6508 // Vectored Interrupt Recv Register Detection
6509 // Indicate when register changes due to arriving interrupt, and not
6510 // due to read of incoming register or ASI write ..
6511
6512
6513 // If any read occurs, send value right away.
6514 // While a read/write is pending, do not update delta.
6515 // Send non read/wr delta during fw2 ..
6516
6517
6518 if (!(`INT_VEC_RDWR_22 | `INT_VEC_RECV_ASIWR_22)) begin // {
6519 if (~`INT_VEC_RECV_ASIWR_22 &
6520 (int_vec_recv_reg !== `INT_VEC_RECV_REG_22 ))
6521 int_vec_recv_reg_delta <= 1'b1;
6522 int_vec_recv_reg <= `INT_VEC_RECV_REG_22;
6523 end // }
6524 else if (`INT_VEC_RECV_ASIWR_22)
6525 int_vec_recv_reg <= `TOP.nas_top.c2.t6.asi_updated_int_rec;
6526
6527 if ((`NAS_PIPE_FW2_22 & int_vec_recv_reg_delta ) |
6528 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
6529 `INT_VEC_RECV_ASIWR_22 ) begin // {
6530 `PR_INFO ("pli_int", `INFO,
6531 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
6532 mycid,mytid, int_vec_recv_reg);
6533 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6534 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
6535 64'h0, int_vec_recv_reg);
6536 end // }
6537 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_22 &
6538 (int_vec_recv_reg !== `INT_VEC_RECV_REG_22 ))))
6539 int_vec_recv_reg_delta <= 1'b0;
6540 end //}
6541
6542 int_vec_reg_rdwr <= `INT_VEC_RDWR_22 | `INT_VEC_RECV_ASIWR_22;
6543 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_22 & ~ inc_vec_reg_rd;
6544
6545 if (`INT_VEC_RECV_ASIWR_22)
6546 inc_vec_reg_rd <= 1'b1;
6547 if (`NAS_PIPE_FW2_22)
6548 inc_vec_reg_rd <= 1'b0;
6549
6550
6551/////////////////////////// Vectored Interrupt /////////////////////////// }}}
6552
6553/////////////////////////// Asynchronous Resets ////////////////////////// {{{
6554
6555
6556/////////////////////////// Asynchronous Resets ////////////////////////// }}}
6557
6558/////////////////////////// Softint ///////////////////////////////////// {{{
6559
6560 // Softint Register hardware Update Detection
6561
6562 // Non software updates (TM/SM)
6563
6564 // If any read occurs, send value right away.
6565 // While a read/write is pending, do not update delta.
6566 // Send non read/wr delta during fw2 ..
6567
6568 // RTL keeps pic_ovf indication in rd_softint and not softint.
6569 // So for set/clear writes, we send softint before the write ..,
6570 // and for read/asyncs we send rd_softint ..
6571
6572
6573 if (~`SOFTINT_RDWR_22) begin // {
6574 if (softint !== `RD_SOFTINT_REG_22 )
6575 softint_delta <= 1'b1;
6576 softint <= `RD_SOFTINT_REG_22;
6577 end // }
6578
6579 if ((`NAS_PIPE_FW2_22 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
6580 ) begin // {
6581 `PR_INFO ("pli_int", `INFO,
6582 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6583 mycid,mytid, {47'h0, softint});
6584 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6585 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6586 {47'h0, softint});
6587 end // }
6588 if (!(~`SOFTINT_RDWR_22&(softint !== `RD_SOFTINT_REG_22)))
6589 softint_delta <= 1'b0;
6590 end //}
6591 else if (`SPC2.tlu.asi_wr_clear_softint[6] |
6592 `SPC2.tlu.asi_wr_set_softint[6] ) begin // {
6593 `PR_INFO ("pli_int", `INFO,
6594 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6595 mycid,mytid, {47'h0, `RD_SOFTINT_REG_22});
6596 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6597 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6598 {47'h0, `RD_SOFTINT_REG_22});
6599 end // }
6600 end //}
6601
6602
6603 softint_rdwr <= `SOFTINT_RDWR_22 ;
6604 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_22;
6605
6606
6607/////////////////////////// Softint ///////////////////////////////////// }}}
6608
6609/////////////////////////// Hintp ///////////////////////////////////// {{{
6610
6611 // Hintp Register hardware Update Detection
6612
6613 // Non software updates (HSP)
6614 // If HINTP is already read/written by SW, then don't send
6615 // any async updates to Nas. Reads/Writes pending sstep is detected
6616 // by snooping nas_pipe ..
6617
6618 hintp <= `HINTP_REG_22 ;
6619 if (hstmatch_late)
6620 hintp_delta <= 1'b1;
6621
6622 if ((~hintp_rdwr & `NAS_PIPE_FW2_22 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
6623 (hintp_rdwr_late & hintp_delta) ) begin // {
6624 `PR_INFO ("pli_int", `INFO,
6625 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
6626 mycid,mytid, {63'h0, hintp});
6627 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6628 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
6629 {63'h0, hintp});
6630 end // }
6631 if (~(hintp_rdwr_late & hintp_delta))
6632 hintp_delta <= 1'b0;
6633 end //}
6634
6635 hintp_rdwr <= `HINTP_RDWR_22;
6636 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_22;
6637 hstmatch_late <= `HSTMATCH_22;
6638
6639
6640/////////////////////////// Hintp ///////////////////////////////////// }}}
6641
6642end //}
6643`endif
6644endmodule
6645
6646// }}}
6647
6648module int_c2t7 ();
6649`ifndef GATESIM
6650
6651// common defines
6652`include "defines.vh"
6653`include "ccx.vri"
6654`include "cmp.vri"
6655
6656wire [2:0] mycid;
6657wire [2:0] mytid;
6658wire [5:0] mytnum;
6659integer junk;
6660
6661reg [63:0] int_vec_recv_reg;
6662reg int_vec_recv_reg_delta;
6663reg int_vec_reg_rdwr;
6664reg inc_vec_reg_rd;
6665reg int_vec_reg_rdwr_late;
6666reg [16:0] softint;
6667reg softint_rdwr;
6668reg softint_rdwr_late;
6669reg softint_delta;
6670reg hintp;
6671reg hintp_rdwr;
6672reg hintp_rdwr_late;
6673reg hintp_delta;
6674reg hstmatch_late;
6675reg ready;
6676reg [7:0] int_num_w;
6677reg [7:0] int_num_fx4;
6678reg [7:0] int_num_fx5;
6679reg [7:0] int_num_fb;
6680reg [7:0] int_num_fw;
6681reg [7:0] int_num_fw1;
6682reg [7:0] int_num_fw2;
6683reg take_disrupting_w;
6684reg take_disrupting_fx4;
6685reg take_disrupting_fx5;
6686reg take_disrupting_fb;
6687reg take_disrupting_fw;
6688reg take_disrupting_fw1;
6689reg take_disrupting_fw2;
6690
6691 assign mycid = 2;
6692 assign mytid = 7;
6693 assign mytnum = 2*8 + 7;
6694
6695initial begin // {
6696 ready = 0; // Wait for socket setup ..
6697 inc_vec_reg_rd <= 1'b0;
6698 int_vec_recv_reg_delta <= 1'b0;
6699 softint_delta <= 1'b0;
6700 hintp_delta <= 1'b0;
6701 int_vec_recv_reg = 64'b0;
6702 @(posedge `BENCH_SPC2_GCLK) ;
6703 @(posedge `BENCH_SPC2_GCLK) ;
6704 ready = `PARGS.int_sync_on;
6705end //}
6706
6707
6708/////////////////////////////// Probes //////////////////////////////////// {{{
6709
6710`define INT_VEC_RECV_REG_23 `SPC2.tlu.cth.int_rec7
6711`define INT_VEC_RECV_ASIWR_23 (`TOP.nas_top.c2.t7.asi_wr_int_rec_delay)
6712`define INT_VEC_RDWR_23 (`TOP.nas_top.c2.t7.asi_rdwr_int_rec)
6713`define INT_VEC_TAKEN_23 `SPC2.tlu.trl1.take_ivt&`SPC2.tlu.trl1.trap[3]
6714
6715`define CPU_MONDO_TAKEN_23 `SPC2.tlu.trl1.take_mqr&`SPC2.tlu.trl1.trap[3]
6716`define DEV_MONDO_TAKEN_23 `SPC2.tlu.trl1.take_dqr&`SPC2.tlu.trl1.trap[3]
6717`define RES_MONDO_TAKEN_23 `SPC2.tlu.trl1.take_rqr&`SPC2.tlu.trl1.trap[3]
6718
6719`define XIR_TAKEN_23 `SPC2.tlu.trl1.take_xir&`SPC2.tlu.trl1.trap[3]
6720
6721`define SOFTINT_RDWR_23 (`TOP.nas_top.c2.t7.asi_rdwr_softint|`TOP.nas_top.c2.t7.asi_wr_softint_delay)
6722
6723`define SOFTINT_REG_23 `SPC2.tlu.trl1.softint3
6724`define RD_SOFTINT_REG_23 `SPC2.tlu.trl1.rd_softint3
6725`define INT_LEVEL_TAKEN_23 `SPC2.tlu.trl1.take_iln&`SPC2.tlu.trl1.trap[3]
6726`define INT_LEVEL_NUM_23 `SPC2.tlu.trl1.int_level_n
6727`define PMU_TAKEN_23 `SPC2.tlu.trl1.take_pmu&`SPC2.tlu.trl1.trap[3]
6728
6729`define HINTP_RDWR_23 (`TOP.nas_top.c2.t7.asi_rdwr_hintp | `TOP.nas_top.c2.t7.asi_wr_hintp_delay)
6730`define HINTP_WR_23 (`SPC2.tlu.asi_wr_hintp[23])
6731`define HSTMATCH_23 `SPC2.tlu.trl1.hstick3_compare
6732
6733`define HINTP_REG_23 `SPC2.tlu.trl1.hintp3
6734`define HSTM_TAKEN_23 `SPC2.tlu.trl1.take_hst&`SPC2.tlu.trl1.trap[3]
6735
6736`define NAS_PIPE_FW2_23 |`TOP.nas_top.c2.t7.complete_fw2
6737
6738`define CWQ_TAKEN_23 `SPC2.tlu.trl1.take_cwq&`SPC2.tlu.trl1.trap[3]
6739`define SMA_TAKEN_23 `SPC2.tlu.trl1.take_sma&`SPC2.tlu.trl1.trap[3]
6740
6741`define POR_TAKEN_23 `SPC2.tlu.trl1.take_por&`SPC2.tlu.trl1.trap[3]
6742
6743/////////////////////////////// Probes //////////////////////////////////// }}}
6744
6745always @(negedge (`BENCH_SPC2_GCLK & ready)) begin // {
6746
6747 // {{{ DETECT, PIPE & SEND
6748 take_disrupting_w <= (`INT_VEC_TAKEN_23 || `CPU_MONDO_TAKEN_23 ||
6749 `DEV_MONDO_TAKEN_23 || `RES_MONDO_TAKEN_23 ||
6750 `XIR_TAKEN_23 || `INT_LEVEL_TAKEN_23 ||
6751 `HSTM_TAKEN_23 || `CWQ_TAKEN_23 ||
6752 `SMA_TAKEN_23 || `PMU_TAKEN_23 || `POR_TAKEN_23);
6753 take_disrupting_fx4 <= take_disrupting_w;
6754 take_disrupting_fx5 <= take_disrupting_fx4;
6755 take_disrupting_fb <= take_disrupting_fx5;
6756 take_disrupting_fw <= take_disrupting_fb;
6757 take_disrupting_fw1 <= take_disrupting_fw;
6758 take_disrupting_fw2 <= take_disrupting_fw1;
6759
6760 case ({`INT_VEC_TAKEN_23, `CPU_MONDO_TAKEN_23,
6761 `DEV_MONDO_TAKEN_23, `RES_MONDO_TAKEN_23,
6762 `XIR_TAKEN_23, `INT_LEVEL_TAKEN_23,
6763 `HSTM_TAKEN_23, `CWQ_TAKEN_23, `SMA_TAKEN_23 ,
6764 `PMU_TAKEN_23, `POR_TAKEN_23})
6765 11'b10000000000: int_num_w <= 8'h60;
6766 11'b01000000000: int_num_w <= 8'h7c;
6767 11'b00100000000: int_num_w <= 8'h7d;
6768 11'b00010000000: int_num_w <= 8'h7e;
6769 11'b00001000000: int_num_w <= 8'h03;
6770 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_23;
6771 11'b00000010000: int_num_w <= 8'h5e;
6772 11'b00000001000: int_num_w <= 8'h3c;
6773 11'b00000000100: int_num_w <= 8'h3d;
6774 11'b00000000010: int_num_w <= 8'h4f;
6775 11'b00000000001: int_num_w <= 8'h01;
6776 endcase
6777
6778 int_num_fx4 <= int_num_w;
6779 int_num_fx5 <= int_num_fx4;
6780 int_num_fb <= int_num_fx5;
6781 int_num_fw <= int_num_fb;
6782 int_num_fw1 <= int_num_fw;
6783 int_num_fw2 <= int_num_fw1;
6784 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
6785 begin // {
6786 `PR_INFO ("pli_int", `INFO,
6787 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
6788 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
6789 end // }
6790
6791 // }}}
6792
6793/////////////////////////// Vectored Interrupt /////////////////////////// {{{
6794
6795 // Vectored Interrupt Recv Register Detection
6796 // Indicate when register changes due to arriving interrupt, and not
6797 // due to read of incoming register or ASI write ..
6798
6799
6800 // If any read occurs, send value right away.
6801 // While a read/write is pending, do not update delta.
6802 // Send non read/wr delta during fw2 ..
6803
6804
6805 if (!(`INT_VEC_RDWR_23 | `INT_VEC_RECV_ASIWR_23)) begin // {
6806 if (~`INT_VEC_RECV_ASIWR_23 &
6807 (int_vec_recv_reg !== `INT_VEC_RECV_REG_23 ))
6808 int_vec_recv_reg_delta <= 1'b1;
6809 int_vec_recv_reg <= `INT_VEC_RECV_REG_23;
6810 end // }
6811 else if (`INT_VEC_RECV_ASIWR_23)
6812 int_vec_recv_reg <= `TOP.nas_top.c2.t7.asi_updated_int_rec;
6813
6814 if ((`NAS_PIPE_FW2_23 & int_vec_recv_reg_delta ) |
6815 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
6816 `INT_VEC_RECV_ASIWR_23 ) begin // {
6817 `PR_INFO ("pli_int", `INFO,
6818 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
6819 mycid,mytid, int_vec_recv_reg);
6820 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6821 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
6822 64'h0, int_vec_recv_reg);
6823 end // }
6824 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_23 &
6825 (int_vec_recv_reg !== `INT_VEC_RECV_REG_23 ))))
6826 int_vec_recv_reg_delta <= 1'b0;
6827 end //}
6828
6829 int_vec_reg_rdwr <= `INT_VEC_RDWR_23 | `INT_VEC_RECV_ASIWR_23;
6830 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_23 & ~ inc_vec_reg_rd;
6831
6832 if (`INT_VEC_RECV_ASIWR_23)
6833 inc_vec_reg_rd <= 1'b1;
6834 if (`NAS_PIPE_FW2_23)
6835 inc_vec_reg_rd <= 1'b0;
6836
6837
6838/////////////////////////// Vectored Interrupt /////////////////////////// }}}
6839
6840/////////////////////////// Asynchronous Resets ////////////////////////// {{{
6841
6842
6843/////////////////////////// Asynchronous Resets ////////////////////////// }}}
6844
6845/////////////////////////// Softint ///////////////////////////////////// {{{
6846
6847 // Softint Register hardware Update Detection
6848
6849 // Non software updates (TM/SM)
6850
6851 // If any read occurs, send value right away.
6852 // While a read/write is pending, do not update delta.
6853 // Send non read/wr delta during fw2 ..
6854
6855 // RTL keeps pic_ovf indication in rd_softint and not softint.
6856 // So for set/clear writes, we send softint before the write ..,
6857 // and for read/asyncs we send rd_softint ..
6858
6859
6860 if (~`SOFTINT_RDWR_23) begin // {
6861 if (softint !== `RD_SOFTINT_REG_23 )
6862 softint_delta <= 1'b1;
6863 softint <= `RD_SOFTINT_REG_23;
6864 end // }
6865
6866 if ((`NAS_PIPE_FW2_23 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
6867 ) begin // {
6868 `PR_INFO ("pli_int", `INFO,
6869 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6870 mycid,mytid, {47'h0, softint});
6871 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6872 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6873 {47'h0, softint});
6874 end // }
6875 if (!(~`SOFTINT_RDWR_23&(softint !== `RD_SOFTINT_REG_23)))
6876 softint_delta <= 1'b0;
6877 end //}
6878 else if (`SPC2.tlu.asi_wr_clear_softint[7] |
6879 `SPC2.tlu.asi_wr_set_softint[7] ) begin // {
6880 `PR_INFO ("pli_int", `INFO,
6881 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
6882 mycid,mytid, {47'h0, `RD_SOFTINT_REG_23});
6883 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6884 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
6885 {47'h0, `RD_SOFTINT_REG_23});
6886 end // }
6887 end //}
6888
6889
6890 softint_rdwr <= `SOFTINT_RDWR_23 ;
6891 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_23;
6892
6893
6894/////////////////////////// Softint ///////////////////////////////////// }}}
6895
6896/////////////////////////// Hintp ///////////////////////////////////// {{{
6897
6898 // Hintp Register hardware Update Detection
6899
6900 // Non software updates (HSP)
6901 // If HINTP is already read/written by SW, then don't send
6902 // any async updates to Nas. Reads/Writes pending sstep is detected
6903 // by snooping nas_pipe ..
6904
6905 hintp <= `HINTP_REG_23 ;
6906 if (hstmatch_late)
6907 hintp_delta <= 1'b1;
6908
6909 if ((~hintp_rdwr & `NAS_PIPE_FW2_23 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
6910 (hintp_rdwr_late & hintp_delta) ) begin // {
6911 `PR_INFO ("pli_int", `INFO,
6912 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
6913 mycid,mytid, {63'h0, hintp});
6914 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
6915 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
6916 {63'h0, hintp});
6917 end // }
6918 if (~(hintp_rdwr_late & hintp_delta))
6919 hintp_delta <= 1'b0;
6920 end //}
6921
6922 hintp_rdwr <= `HINTP_RDWR_23;
6923 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_23;
6924 hstmatch_late <= `HSTMATCH_23;
6925
6926
6927/////////////////////////// Hintp ///////////////////////////////////// }}}
6928
6929end //}
6930`endif
6931endmodule
6932
6933`endif
6934`ifdef CORE_3
6935
6936// }}}
6937
6938module int_c3t0 ();
6939`ifndef GATESIM
6940
6941// common defines
6942`include "defines.vh"
6943`include "ccx.vri"
6944`include "cmp.vri"
6945
6946wire [2:0] mycid;
6947wire [2:0] mytid;
6948wire [5:0] mytnum;
6949integer junk;
6950
6951reg [63:0] int_vec_recv_reg;
6952reg int_vec_recv_reg_delta;
6953reg int_vec_reg_rdwr;
6954reg inc_vec_reg_rd;
6955reg int_vec_reg_rdwr_late;
6956reg [16:0] softint;
6957reg softint_rdwr;
6958reg softint_rdwr_late;
6959reg softint_delta;
6960reg hintp;
6961reg hintp_rdwr;
6962reg hintp_rdwr_late;
6963reg hintp_delta;
6964reg hstmatch_late;
6965reg ready;
6966reg [7:0] int_num_w;
6967reg [7:0] int_num_fx4;
6968reg [7:0] int_num_fx5;
6969reg [7:0] int_num_fb;
6970reg [7:0] int_num_fw;
6971reg [7:0] int_num_fw1;
6972reg [7:0] int_num_fw2;
6973reg take_disrupting_w;
6974reg take_disrupting_fx4;
6975reg take_disrupting_fx5;
6976reg take_disrupting_fb;
6977reg take_disrupting_fw;
6978reg take_disrupting_fw1;
6979reg take_disrupting_fw2;
6980
6981 assign mycid = 3;
6982 assign mytid = 0;
6983 assign mytnum = 3*8 + 0;
6984
6985initial begin // {
6986 ready = 0; // Wait for socket setup ..
6987 inc_vec_reg_rd <= 1'b0;
6988 int_vec_recv_reg_delta <= 1'b0;
6989 softint_delta <= 1'b0;
6990 hintp_delta <= 1'b0;
6991 int_vec_recv_reg = 64'b0;
6992 @(posedge `BENCH_SPC3_GCLK) ;
6993 @(posedge `BENCH_SPC3_GCLK) ;
6994 ready = `PARGS.int_sync_on;
6995end //}
6996
6997
6998/////////////////////////////// Probes //////////////////////////////////// {{{
6999
7000`define INT_VEC_RECV_REG_24 `SPC3.tlu.cth.int_rec0
7001`define INT_VEC_RECV_ASIWR_24 (`TOP.nas_top.c3.t0.asi_wr_int_rec_delay)
7002`define INT_VEC_RDWR_24 (`TOP.nas_top.c3.t0.asi_rdwr_int_rec)
7003`define INT_VEC_TAKEN_24 `SPC3.tlu.trl0.take_ivt&`SPC3.tlu.trl0.trap[0]
7004
7005`define CPU_MONDO_TAKEN_24 `SPC3.tlu.trl0.take_mqr&`SPC3.tlu.trl0.trap[0]
7006`define DEV_MONDO_TAKEN_24 `SPC3.tlu.trl0.take_dqr&`SPC3.tlu.trl0.trap[0]
7007`define RES_MONDO_TAKEN_24 `SPC3.tlu.trl0.take_rqr&`SPC3.tlu.trl0.trap[0]
7008
7009`define XIR_TAKEN_24 `SPC3.tlu.trl0.take_xir&`SPC3.tlu.trl0.trap[0]
7010
7011`define SOFTINT_RDWR_24 (`TOP.nas_top.c3.t0.asi_rdwr_softint|`TOP.nas_top.c3.t0.asi_wr_softint_delay)
7012
7013`define SOFTINT_REG_24 `SPC3.tlu.trl0.softint0
7014`define RD_SOFTINT_REG_24 `SPC3.tlu.trl0.rd_softint0
7015`define INT_LEVEL_TAKEN_24 `SPC3.tlu.trl0.take_iln&`SPC3.tlu.trl0.trap[0]
7016`define INT_LEVEL_NUM_24 `SPC3.tlu.trl0.int_level_n
7017`define PMU_TAKEN_24 `SPC3.tlu.trl0.take_pmu&`SPC3.tlu.trl0.trap[0]
7018
7019`define HINTP_RDWR_24 (`TOP.nas_top.c3.t0.asi_rdwr_hintp | `TOP.nas_top.c3.t0.asi_wr_hintp_delay)
7020`define HINTP_WR_24 (`SPC3.tlu.asi_wr_hintp[24])
7021`define HSTMATCH_24 `SPC3.tlu.trl0.hstick0_compare
7022
7023`define HINTP_REG_24 `SPC3.tlu.trl0.hintp0
7024`define HSTM_TAKEN_24 `SPC3.tlu.trl0.take_hst&`SPC3.tlu.trl0.trap[0]
7025
7026`define NAS_PIPE_FW2_24 |`TOP.nas_top.c3.t0.complete_fw2
7027
7028`define CWQ_TAKEN_24 `SPC3.tlu.trl0.take_cwq&`SPC3.tlu.trl0.trap[0]
7029`define SMA_TAKEN_24 `SPC3.tlu.trl0.take_sma&`SPC3.tlu.trl0.trap[0]
7030
7031`define POR_TAKEN_24 `SPC3.tlu.trl0.take_por&`SPC3.tlu.trl0.trap[0]
7032
7033/////////////////////////////// Probes //////////////////////////////////// }}}
7034
7035always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
7036
7037 // {{{ DETECT, PIPE & SEND
7038 take_disrupting_w <= (`INT_VEC_TAKEN_24 || `CPU_MONDO_TAKEN_24 ||
7039 `DEV_MONDO_TAKEN_24 || `RES_MONDO_TAKEN_24 ||
7040 `XIR_TAKEN_24 || `INT_LEVEL_TAKEN_24 ||
7041 `HSTM_TAKEN_24 || `CWQ_TAKEN_24 ||
7042 `SMA_TAKEN_24 || `PMU_TAKEN_24 || `POR_TAKEN_24);
7043 take_disrupting_fx4 <= take_disrupting_w;
7044 take_disrupting_fx5 <= take_disrupting_fx4;
7045 take_disrupting_fb <= take_disrupting_fx5;
7046 take_disrupting_fw <= take_disrupting_fb;
7047 take_disrupting_fw1 <= take_disrupting_fw;
7048 take_disrupting_fw2 <= take_disrupting_fw1;
7049
7050 case ({`INT_VEC_TAKEN_24, `CPU_MONDO_TAKEN_24,
7051 `DEV_MONDO_TAKEN_24, `RES_MONDO_TAKEN_24,
7052 `XIR_TAKEN_24, `INT_LEVEL_TAKEN_24,
7053 `HSTM_TAKEN_24, `CWQ_TAKEN_24, `SMA_TAKEN_24 ,
7054 `PMU_TAKEN_24, `POR_TAKEN_24})
7055 11'b10000000000: int_num_w <= 8'h60;
7056 11'b01000000000: int_num_w <= 8'h7c;
7057 11'b00100000000: int_num_w <= 8'h7d;
7058 11'b00010000000: int_num_w <= 8'h7e;
7059 11'b00001000000: int_num_w <= 8'h03;
7060 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_24;
7061 11'b00000010000: int_num_w <= 8'h5e;
7062 11'b00000001000: int_num_w <= 8'h3c;
7063 11'b00000000100: int_num_w <= 8'h3d;
7064 11'b00000000010: int_num_w <= 8'h4f;
7065 11'b00000000001: int_num_w <= 8'h01;
7066 endcase
7067
7068 int_num_fx4 <= int_num_w;
7069 int_num_fx5 <= int_num_fx4;
7070 int_num_fb <= int_num_fx5;
7071 int_num_fw <= int_num_fb;
7072 int_num_fw1 <= int_num_fw;
7073 int_num_fw2 <= int_num_fw1;
7074 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
7075 begin // {
7076 `PR_INFO ("pli_int", `INFO,
7077 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
7078 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7079 end // }
7080
7081 // }}}
7082
7083/////////////////////////// Vectored Interrupt /////////////////////////// {{{
7084
7085 // Vectored Interrupt Recv Register Detection
7086 // Indicate when register changes due to arriving interrupt, and not
7087 // due to read of incoming register or ASI write ..
7088
7089
7090 // If any read occurs, send value right away.
7091 // While a read/write is pending, do not update delta.
7092 // Send non read/wr delta during fw2 ..
7093
7094
7095 if (!(`INT_VEC_RDWR_24 | `INT_VEC_RECV_ASIWR_24)) begin // {
7096 if (~`INT_VEC_RECV_ASIWR_24 &
7097 (int_vec_recv_reg !== `INT_VEC_RECV_REG_24 ))
7098 int_vec_recv_reg_delta <= 1'b1;
7099 int_vec_recv_reg <= `INT_VEC_RECV_REG_24;
7100 end // }
7101 else if (`INT_VEC_RECV_ASIWR_24)
7102 int_vec_recv_reg <= `TOP.nas_top.c3.t0.asi_updated_int_rec;
7103
7104 if ((`NAS_PIPE_FW2_24 & int_vec_recv_reg_delta ) |
7105 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
7106 `INT_VEC_RECV_ASIWR_24 ) begin // {
7107 `PR_INFO ("pli_int", `INFO,
7108 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
7109 mycid,mytid, int_vec_recv_reg);
7110 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7111 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
7112 64'h0, int_vec_recv_reg);
7113 end // }
7114 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_24 &
7115 (int_vec_recv_reg !== `INT_VEC_RECV_REG_24 ))))
7116 int_vec_recv_reg_delta <= 1'b0;
7117 end //}
7118
7119 int_vec_reg_rdwr <= `INT_VEC_RDWR_24 | `INT_VEC_RECV_ASIWR_24;
7120 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_24 & ~ inc_vec_reg_rd;
7121
7122 if (`INT_VEC_RECV_ASIWR_24)
7123 inc_vec_reg_rd <= 1'b1;
7124 if (`NAS_PIPE_FW2_24)
7125 inc_vec_reg_rd <= 1'b0;
7126
7127
7128/////////////////////////// Vectored Interrupt /////////////////////////// }}}
7129
7130/////////////////////////// Asynchronous Resets ////////////////////////// {{{
7131
7132
7133/////////////////////////// Asynchronous Resets ////////////////////////// }}}
7134
7135/////////////////////////// Softint ///////////////////////////////////// {{{
7136
7137 // Softint Register hardware Update Detection
7138
7139 // Non software updates (TM/SM)
7140
7141 // If any read occurs, send value right away.
7142 // While a read/write is pending, do not update delta.
7143 // Send non read/wr delta during fw2 ..
7144
7145 // RTL keeps pic_ovf indication in rd_softint and not softint.
7146 // So for set/clear writes, we send softint before the write ..,
7147 // and for read/asyncs we send rd_softint ..
7148
7149
7150 if (~`SOFTINT_RDWR_24) begin // {
7151 if (softint !== `RD_SOFTINT_REG_24 )
7152 softint_delta <= 1'b1;
7153 softint <= `RD_SOFTINT_REG_24;
7154 end // }
7155
7156 if ((`NAS_PIPE_FW2_24 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
7157 ) begin // {
7158 `PR_INFO ("pli_int", `INFO,
7159 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
7160 mycid,mytid, {47'h0, softint});
7161 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7162 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
7163 {47'h0, softint});
7164 end // }
7165 if (!(~`SOFTINT_RDWR_24&(softint !== `RD_SOFTINT_REG_24)))
7166 softint_delta <= 1'b0;
7167 end //}
7168 else if (`SPC3.tlu.asi_wr_clear_softint[0] |
7169 `SPC3.tlu.asi_wr_set_softint[0] ) begin // {
7170 `PR_INFO ("pli_int", `INFO,
7171 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
7172 mycid,mytid, {47'h0, `RD_SOFTINT_REG_24});
7173 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7174 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
7175 {47'h0, `RD_SOFTINT_REG_24});
7176 end // }
7177 end //}
7178
7179
7180 softint_rdwr <= `SOFTINT_RDWR_24 ;
7181 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_24;
7182
7183
7184/////////////////////////// Softint ///////////////////////////////////// }}}
7185
7186/////////////////////////// Hintp ///////////////////////////////////// {{{
7187
7188 // Hintp Register hardware Update Detection
7189
7190 // Non software updates (HSP)
7191 // If HINTP is already read/written by SW, then don't send
7192 // any async updates to Nas. Reads/Writes pending sstep is detected
7193 // by snooping nas_pipe ..
7194
7195 hintp <= `HINTP_REG_24 ;
7196 if (hstmatch_late)
7197 hintp_delta <= 1'b1;
7198
7199 if ((~hintp_rdwr & `NAS_PIPE_FW2_24 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
7200 (hintp_rdwr_late & hintp_delta) ) begin // {
7201 `PR_INFO ("pli_int", `INFO,
7202 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
7203 mycid,mytid, {63'h0, hintp});
7204 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7205 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
7206 {63'h0, hintp});
7207 end // }
7208 if (~(hintp_rdwr_late & hintp_delta))
7209 hintp_delta <= 1'b0;
7210 end //}
7211
7212 hintp_rdwr <= `HINTP_RDWR_24;
7213 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_24;
7214 hstmatch_late <= `HSTMATCH_24;
7215
7216
7217/////////////////////////// Hintp ///////////////////////////////////// }}}
7218
7219end //}
7220`endif
7221endmodule
7222
7223// }}}
7224
7225module int_c3t1 ();
7226`ifndef GATESIM
7227
7228// common defines
7229`include "defines.vh"
7230`include "ccx.vri"
7231`include "cmp.vri"
7232
7233wire [2:0] mycid;
7234wire [2:0] mytid;
7235wire [5:0] mytnum;
7236integer junk;
7237
7238reg [63:0] int_vec_recv_reg;
7239reg int_vec_recv_reg_delta;
7240reg int_vec_reg_rdwr;
7241reg inc_vec_reg_rd;
7242reg int_vec_reg_rdwr_late;
7243reg [16:0] softint;
7244reg softint_rdwr;
7245reg softint_rdwr_late;
7246reg softint_delta;
7247reg hintp;
7248reg hintp_rdwr;
7249reg hintp_rdwr_late;
7250reg hintp_delta;
7251reg hstmatch_late;
7252reg ready;
7253reg [7:0] int_num_w;
7254reg [7:0] int_num_fx4;
7255reg [7:0] int_num_fx5;
7256reg [7:0] int_num_fb;
7257reg [7:0] int_num_fw;
7258reg [7:0] int_num_fw1;
7259reg [7:0] int_num_fw2;
7260reg take_disrupting_w;
7261reg take_disrupting_fx4;
7262reg take_disrupting_fx5;
7263reg take_disrupting_fb;
7264reg take_disrupting_fw;
7265reg take_disrupting_fw1;
7266reg take_disrupting_fw2;
7267
7268 assign mycid = 3;
7269 assign mytid = 1;
7270 assign mytnum = 3*8 + 1;
7271
7272initial begin // {
7273 ready = 0; // Wait for socket setup ..
7274 inc_vec_reg_rd <= 1'b0;
7275 int_vec_recv_reg_delta <= 1'b0;
7276 softint_delta <= 1'b0;
7277 hintp_delta <= 1'b0;
7278 int_vec_recv_reg = 64'b0;
7279 @(posedge `BENCH_SPC3_GCLK) ;
7280 @(posedge `BENCH_SPC3_GCLK) ;
7281 ready = `PARGS.int_sync_on;
7282end //}
7283
7284
7285/////////////////////////////// Probes //////////////////////////////////// {{{
7286
7287`define INT_VEC_RECV_REG_25 `SPC3.tlu.cth.int_rec1
7288`define INT_VEC_RECV_ASIWR_25 (`TOP.nas_top.c3.t1.asi_wr_int_rec_delay)
7289`define INT_VEC_RDWR_25 (`TOP.nas_top.c3.t1.asi_rdwr_int_rec)
7290`define INT_VEC_TAKEN_25 `SPC3.tlu.trl0.take_ivt&`SPC3.tlu.trl0.trap[1]
7291
7292`define CPU_MONDO_TAKEN_25 `SPC3.tlu.trl0.take_mqr&`SPC3.tlu.trl0.trap[1]
7293`define DEV_MONDO_TAKEN_25 `SPC3.tlu.trl0.take_dqr&`SPC3.tlu.trl0.trap[1]
7294`define RES_MONDO_TAKEN_25 `SPC3.tlu.trl0.take_rqr&`SPC3.tlu.trl0.trap[1]
7295
7296`define XIR_TAKEN_25 `SPC3.tlu.trl0.take_xir&`SPC3.tlu.trl0.trap[1]
7297
7298`define SOFTINT_RDWR_25 (`TOP.nas_top.c3.t1.asi_rdwr_softint|`TOP.nas_top.c3.t1.asi_wr_softint_delay)
7299
7300`define SOFTINT_REG_25 `SPC3.tlu.trl0.softint1
7301`define RD_SOFTINT_REG_25 `SPC3.tlu.trl0.rd_softint1
7302`define INT_LEVEL_TAKEN_25 `SPC3.tlu.trl0.take_iln&`SPC3.tlu.trl0.trap[1]
7303`define INT_LEVEL_NUM_25 `SPC3.tlu.trl0.int_level_n
7304`define PMU_TAKEN_25 `SPC3.tlu.trl0.take_pmu&`SPC3.tlu.trl0.trap[1]
7305
7306`define HINTP_RDWR_25 (`TOP.nas_top.c3.t1.asi_rdwr_hintp | `TOP.nas_top.c3.t1.asi_wr_hintp_delay)
7307`define HINTP_WR_25 (`SPC3.tlu.asi_wr_hintp[25])
7308`define HSTMATCH_25 `SPC3.tlu.trl0.hstick1_compare
7309
7310`define HINTP_REG_25 `SPC3.tlu.trl0.hintp1
7311`define HSTM_TAKEN_25 `SPC3.tlu.trl0.take_hst&`SPC3.tlu.trl0.trap[1]
7312
7313`define NAS_PIPE_FW2_25 |`TOP.nas_top.c3.t1.complete_fw2
7314
7315`define CWQ_TAKEN_25 `SPC3.tlu.trl0.take_cwq&`SPC3.tlu.trl0.trap[1]
7316`define SMA_TAKEN_25 `SPC3.tlu.trl0.take_sma&`SPC3.tlu.trl0.trap[1]
7317
7318`define POR_TAKEN_25 `SPC3.tlu.trl0.take_por&`SPC3.tlu.trl0.trap[1]
7319
7320/////////////////////////////// Probes //////////////////////////////////// }}}
7321
7322always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
7323
7324 // {{{ DETECT, PIPE & SEND
7325 take_disrupting_w <= (`INT_VEC_TAKEN_25 || `CPU_MONDO_TAKEN_25 ||
7326 `DEV_MONDO_TAKEN_25 || `RES_MONDO_TAKEN_25 ||
7327 `XIR_TAKEN_25 || `INT_LEVEL_TAKEN_25 ||
7328 `HSTM_TAKEN_25 || `CWQ_TAKEN_25 ||
7329 `SMA_TAKEN_25 || `PMU_TAKEN_25 || `POR_TAKEN_25);
7330 take_disrupting_fx4 <= take_disrupting_w;
7331 take_disrupting_fx5 <= take_disrupting_fx4;
7332 take_disrupting_fb <= take_disrupting_fx5;
7333 take_disrupting_fw <= take_disrupting_fb;
7334 take_disrupting_fw1 <= take_disrupting_fw;
7335 take_disrupting_fw2 <= take_disrupting_fw1;
7336
7337 case ({`INT_VEC_TAKEN_25, `CPU_MONDO_TAKEN_25,
7338 `DEV_MONDO_TAKEN_25, `RES_MONDO_TAKEN_25,
7339 `XIR_TAKEN_25, `INT_LEVEL_TAKEN_25,
7340 `HSTM_TAKEN_25, `CWQ_TAKEN_25, `SMA_TAKEN_25 ,
7341 `PMU_TAKEN_25, `POR_TAKEN_25})
7342 11'b10000000000: int_num_w <= 8'h60;
7343 11'b01000000000: int_num_w <= 8'h7c;
7344 11'b00100000000: int_num_w <= 8'h7d;
7345 11'b00010000000: int_num_w <= 8'h7e;
7346 11'b00001000000: int_num_w <= 8'h03;
7347 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_25;
7348 11'b00000010000: int_num_w <= 8'h5e;
7349 11'b00000001000: int_num_w <= 8'h3c;
7350 11'b00000000100: int_num_w <= 8'h3d;
7351 11'b00000000010: int_num_w <= 8'h4f;
7352 11'b00000000001: int_num_w <= 8'h01;
7353 endcase
7354
7355 int_num_fx4 <= int_num_w;
7356 int_num_fx5 <= int_num_fx4;
7357 int_num_fb <= int_num_fx5;
7358 int_num_fw <= int_num_fb;
7359 int_num_fw1 <= int_num_fw;
7360 int_num_fw2 <= int_num_fw1;
7361 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
7362 begin // {
7363 `PR_INFO ("pli_int", `INFO,
7364 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
7365 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7366 end // }
7367
7368 // }}}
7369
7370/////////////////////////// Vectored Interrupt /////////////////////////// {{{
7371
7372 // Vectored Interrupt Recv Register Detection
7373 // Indicate when register changes due to arriving interrupt, and not
7374 // due to read of incoming register or ASI write ..
7375
7376
7377 // If any read occurs, send value right away.
7378 // While a read/write is pending, do not update delta.
7379 // Send non read/wr delta during fw2 ..
7380
7381
7382 if (!(`INT_VEC_RDWR_25 | `INT_VEC_RECV_ASIWR_25)) begin // {
7383 if (~`INT_VEC_RECV_ASIWR_25 &
7384 (int_vec_recv_reg !== `INT_VEC_RECV_REG_25 ))
7385 int_vec_recv_reg_delta <= 1'b1;
7386 int_vec_recv_reg <= `INT_VEC_RECV_REG_25;
7387 end // }
7388 else if (`INT_VEC_RECV_ASIWR_25)
7389 int_vec_recv_reg <= `TOP.nas_top.c3.t1.asi_updated_int_rec;
7390
7391 if ((`NAS_PIPE_FW2_25 & int_vec_recv_reg_delta ) |
7392 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
7393 `INT_VEC_RECV_ASIWR_25 ) begin // {
7394 `PR_INFO ("pli_int", `INFO,
7395 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
7396 mycid,mytid, int_vec_recv_reg);
7397 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7398 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
7399 64'h0, int_vec_recv_reg);
7400 end // }
7401 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_25 &
7402 (int_vec_recv_reg !== `INT_VEC_RECV_REG_25 ))))
7403 int_vec_recv_reg_delta <= 1'b0;
7404 end //}
7405
7406 int_vec_reg_rdwr <= `INT_VEC_RDWR_25 | `INT_VEC_RECV_ASIWR_25;
7407 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_25 & ~ inc_vec_reg_rd;
7408
7409 if (`INT_VEC_RECV_ASIWR_25)
7410 inc_vec_reg_rd <= 1'b1;
7411 if (`NAS_PIPE_FW2_25)
7412 inc_vec_reg_rd <= 1'b0;
7413
7414
7415/////////////////////////// Vectored Interrupt /////////////////////////// }}}
7416
7417/////////////////////////// Asynchronous Resets ////////////////////////// {{{
7418
7419
7420/////////////////////////// Asynchronous Resets ////////////////////////// }}}
7421
7422/////////////////////////// Softint ///////////////////////////////////// {{{
7423
7424 // Softint Register hardware Update Detection
7425
7426 // Non software updates (TM/SM)
7427
7428 // If any read occurs, send value right away.
7429 // While a read/write is pending, do not update delta.
7430 // Send non read/wr delta during fw2 ..
7431
7432 // RTL keeps pic_ovf indication in rd_softint and not softint.
7433 // So for set/clear writes, we send softint before the write ..,
7434 // and for read/asyncs we send rd_softint ..
7435
7436
7437 if (~`SOFTINT_RDWR_25) begin // {
7438 if (softint !== `RD_SOFTINT_REG_25 )
7439 softint_delta <= 1'b1;
7440 softint <= `RD_SOFTINT_REG_25;
7441 end // }
7442
7443 if ((`NAS_PIPE_FW2_25 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
7444 ) begin // {
7445 `PR_INFO ("pli_int", `INFO,
7446 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
7447 mycid,mytid, {47'h0, softint});
7448 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7449 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
7450 {47'h0, softint});
7451 end // }
7452 if (!(~`SOFTINT_RDWR_25&(softint !== `RD_SOFTINT_REG_25)))
7453 softint_delta <= 1'b0;
7454 end //}
7455 else if (`SPC3.tlu.asi_wr_clear_softint[1] |
7456 `SPC3.tlu.asi_wr_set_softint[1] ) begin // {
7457 `PR_INFO ("pli_int", `INFO,
7458 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
7459 mycid,mytid, {47'h0, `RD_SOFTINT_REG_25});
7460 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7461 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
7462 {47'h0, `RD_SOFTINT_REG_25});
7463 end // }
7464 end //}
7465
7466
7467 softint_rdwr <= `SOFTINT_RDWR_25 ;
7468 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_25;
7469
7470
7471/////////////////////////// Softint ///////////////////////////////////// }}}
7472
7473/////////////////////////// Hintp ///////////////////////////////////// {{{
7474
7475 // Hintp Register hardware Update Detection
7476
7477 // Non software updates (HSP)
7478 // If HINTP is already read/written by SW, then don't send
7479 // any async updates to Nas. Reads/Writes pending sstep is detected
7480 // by snooping nas_pipe ..
7481
7482 hintp <= `HINTP_REG_25 ;
7483 if (hstmatch_late)
7484 hintp_delta <= 1'b1;
7485
7486 if ((~hintp_rdwr & `NAS_PIPE_FW2_25 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
7487 (hintp_rdwr_late & hintp_delta) ) begin // {
7488 `PR_INFO ("pli_int", `INFO,
7489 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
7490 mycid,mytid, {63'h0, hintp});
7491 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7492 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
7493 {63'h0, hintp});
7494 end // }
7495 if (~(hintp_rdwr_late & hintp_delta))
7496 hintp_delta <= 1'b0;
7497 end //}
7498
7499 hintp_rdwr <= `HINTP_RDWR_25;
7500 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_25;
7501 hstmatch_late <= `HSTMATCH_25;
7502
7503
7504/////////////////////////// Hintp ///////////////////////////////////// }}}
7505
7506end //}
7507`endif
7508endmodule
7509
7510// }}}
7511
7512module int_c3t2 ();
7513`ifndef GATESIM
7514
7515// common defines
7516`include "defines.vh"
7517`include "ccx.vri"
7518`include "cmp.vri"
7519
7520wire [2:0] mycid;
7521wire [2:0] mytid;
7522wire [5:0] mytnum;
7523integer junk;
7524
7525reg [63:0] int_vec_recv_reg;
7526reg int_vec_recv_reg_delta;
7527reg int_vec_reg_rdwr;
7528reg inc_vec_reg_rd;
7529reg int_vec_reg_rdwr_late;
7530reg [16:0] softint;
7531reg softint_rdwr;
7532reg softint_rdwr_late;
7533reg softint_delta;
7534reg hintp;
7535reg hintp_rdwr;
7536reg hintp_rdwr_late;
7537reg hintp_delta;
7538reg hstmatch_late;
7539reg ready;
7540reg [7:0] int_num_w;
7541reg [7:0] int_num_fx4;
7542reg [7:0] int_num_fx5;
7543reg [7:0] int_num_fb;
7544reg [7:0] int_num_fw;
7545reg [7:0] int_num_fw1;
7546reg [7:0] int_num_fw2;
7547reg take_disrupting_w;
7548reg take_disrupting_fx4;
7549reg take_disrupting_fx5;
7550reg take_disrupting_fb;
7551reg take_disrupting_fw;
7552reg take_disrupting_fw1;
7553reg take_disrupting_fw2;
7554
7555 assign mycid = 3;
7556 assign mytid = 2;
7557 assign mytnum = 3*8 + 2;
7558
7559initial begin // {
7560 ready = 0; // Wait for socket setup ..
7561 inc_vec_reg_rd <= 1'b0;
7562 int_vec_recv_reg_delta <= 1'b0;
7563 softint_delta <= 1'b0;
7564 hintp_delta <= 1'b0;
7565 int_vec_recv_reg = 64'b0;
7566 @(posedge `BENCH_SPC3_GCLK) ;
7567 @(posedge `BENCH_SPC3_GCLK) ;
7568 ready = `PARGS.int_sync_on;
7569end //}
7570
7571
7572/////////////////////////////// Probes //////////////////////////////////// {{{
7573
7574`define INT_VEC_RECV_REG_26 `SPC3.tlu.cth.int_rec2
7575`define INT_VEC_RECV_ASIWR_26 (`TOP.nas_top.c3.t2.asi_wr_int_rec_delay)
7576`define INT_VEC_RDWR_26 (`TOP.nas_top.c3.t2.asi_rdwr_int_rec)
7577`define INT_VEC_TAKEN_26 `SPC3.tlu.trl0.take_ivt&`SPC3.tlu.trl0.trap[2]
7578
7579`define CPU_MONDO_TAKEN_26 `SPC3.tlu.trl0.take_mqr&`SPC3.tlu.trl0.trap[2]
7580`define DEV_MONDO_TAKEN_26 `SPC3.tlu.trl0.take_dqr&`SPC3.tlu.trl0.trap[2]
7581`define RES_MONDO_TAKEN_26 `SPC3.tlu.trl0.take_rqr&`SPC3.tlu.trl0.trap[2]
7582
7583`define XIR_TAKEN_26 `SPC3.tlu.trl0.take_xir&`SPC3.tlu.trl0.trap[2]
7584
7585`define SOFTINT_RDWR_26 (`TOP.nas_top.c3.t2.asi_rdwr_softint|`TOP.nas_top.c3.t2.asi_wr_softint_delay)
7586
7587`define SOFTINT_REG_26 `SPC3.tlu.trl0.softint2
7588`define RD_SOFTINT_REG_26 `SPC3.tlu.trl0.rd_softint2
7589`define INT_LEVEL_TAKEN_26 `SPC3.tlu.trl0.take_iln&`SPC3.tlu.trl0.trap[2]
7590`define INT_LEVEL_NUM_26 `SPC3.tlu.trl0.int_level_n
7591`define PMU_TAKEN_26 `SPC3.tlu.trl0.take_pmu&`SPC3.tlu.trl0.trap[2]
7592
7593`define HINTP_RDWR_26 (`TOP.nas_top.c3.t2.asi_rdwr_hintp | `TOP.nas_top.c3.t2.asi_wr_hintp_delay)
7594`define HINTP_WR_26 (`SPC3.tlu.asi_wr_hintp[26])
7595`define HSTMATCH_26 `SPC3.tlu.trl0.hstick2_compare
7596
7597`define HINTP_REG_26 `SPC3.tlu.trl0.hintp2
7598`define HSTM_TAKEN_26 `SPC3.tlu.trl0.take_hst&`SPC3.tlu.trl0.trap[2]
7599
7600`define NAS_PIPE_FW2_26 |`TOP.nas_top.c3.t2.complete_fw2
7601
7602`define CWQ_TAKEN_26 `SPC3.tlu.trl0.take_cwq&`SPC3.tlu.trl0.trap[2]
7603`define SMA_TAKEN_26 `SPC3.tlu.trl0.take_sma&`SPC3.tlu.trl0.trap[2]
7604
7605`define POR_TAKEN_26 `SPC3.tlu.trl0.take_por&`SPC3.tlu.trl0.trap[2]
7606
7607/////////////////////////////// Probes //////////////////////////////////// }}}
7608
7609always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
7610
7611 // {{{ DETECT, PIPE & SEND
7612 take_disrupting_w <= (`INT_VEC_TAKEN_26 || `CPU_MONDO_TAKEN_26 ||
7613 `DEV_MONDO_TAKEN_26 || `RES_MONDO_TAKEN_26 ||
7614 `XIR_TAKEN_26 || `INT_LEVEL_TAKEN_26 ||
7615 `HSTM_TAKEN_26 || `CWQ_TAKEN_26 ||
7616 `SMA_TAKEN_26 || `PMU_TAKEN_26 || `POR_TAKEN_26);
7617 take_disrupting_fx4 <= take_disrupting_w;
7618 take_disrupting_fx5 <= take_disrupting_fx4;
7619 take_disrupting_fb <= take_disrupting_fx5;
7620 take_disrupting_fw <= take_disrupting_fb;
7621 take_disrupting_fw1 <= take_disrupting_fw;
7622 take_disrupting_fw2 <= take_disrupting_fw1;
7623
7624 case ({`INT_VEC_TAKEN_26, `CPU_MONDO_TAKEN_26,
7625 `DEV_MONDO_TAKEN_26, `RES_MONDO_TAKEN_26,
7626 `XIR_TAKEN_26, `INT_LEVEL_TAKEN_26,
7627 `HSTM_TAKEN_26, `CWQ_TAKEN_26, `SMA_TAKEN_26 ,
7628 `PMU_TAKEN_26, `POR_TAKEN_26})
7629 11'b10000000000: int_num_w <= 8'h60;
7630 11'b01000000000: int_num_w <= 8'h7c;
7631 11'b00100000000: int_num_w <= 8'h7d;
7632 11'b00010000000: int_num_w <= 8'h7e;
7633 11'b00001000000: int_num_w <= 8'h03;
7634 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_26;
7635 11'b00000010000: int_num_w <= 8'h5e;
7636 11'b00000001000: int_num_w <= 8'h3c;
7637 11'b00000000100: int_num_w <= 8'h3d;
7638 11'b00000000010: int_num_w <= 8'h4f;
7639 11'b00000000001: int_num_w <= 8'h01;
7640 endcase
7641
7642 int_num_fx4 <= int_num_w;
7643 int_num_fx5 <= int_num_fx4;
7644 int_num_fb <= int_num_fx5;
7645 int_num_fw <= int_num_fb;
7646 int_num_fw1 <= int_num_fw;
7647 int_num_fw2 <= int_num_fw1;
7648 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
7649 begin // {
7650 `PR_INFO ("pli_int", `INFO,
7651 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
7652 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7653 end // }
7654
7655 // }}}
7656
7657/////////////////////////// Vectored Interrupt /////////////////////////// {{{
7658
7659 // Vectored Interrupt Recv Register Detection
7660 // Indicate when register changes due to arriving interrupt, and not
7661 // due to read of incoming register or ASI write ..
7662
7663
7664 // If any read occurs, send value right away.
7665 // While a read/write is pending, do not update delta.
7666 // Send non read/wr delta during fw2 ..
7667
7668
7669 if (!(`INT_VEC_RDWR_26 | `INT_VEC_RECV_ASIWR_26)) begin // {
7670 if (~`INT_VEC_RECV_ASIWR_26 &
7671 (int_vec_recv_reg !== `INT_VEC_RECV_REG_26 ))
7672 int_vec_recv_reg_delta <= 1'b1;
7673 int_vec_recv_reg <= `INT_VEC_RECV_REG_26;
7674 end // }
7675 else if (`INT_VEC_RECV_ASIWR_26)
7676 int_vec_recv_reg <= `TOP.nas_top.c3.t2.asi_updated_int_rec;
7677
7678 if ((`NAS_PIPE_FW2_26 & int_vec_recv_reg_delta ) |
7679 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
7680 `INT_VEC_RECV_ASIWR_26 ) begin // {
7681 `PR_INFO ("pli_int", `INFO,
7682 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
7683 mycid,mytid, int_vec_recv_reg);
7684 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7685 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
7686 64'h0, int_vec_recv_reg);
7687 end // }
7688 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_26 &
7689 (int_vec_recv_reg !== `INT_VEC_RECV_REG_26 ))))
7690 int_vec_recv_reg_delta <= 1'b0;
7691 end //}
7692
7693 int_vec_reg_rdwr <= `INT_VEC_RDWR_26 | `INT_VEC_RECV_ASIWR_26;
7694 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_26 & ~ inc_vec_reg_rd;
7695
7696 if (`INT_VEC_RECV_ASIWR_26)
7697 inc_vec_reg_rd <= 1'b1;
7698 if (`NAS_PIPE_FW2_26)
7699 inc_vec_reg_rd <= 1'b0;
7700
7701
7702/////////////////////////// Vectored Interrupt /////////////////////////// }}}
7703
7704/////////////////////////// Asynchronous Resets ////////////////////////// {{{
7705
7706
7707/////////////////////////// Asynchronous Resets ////////////////////////// }}}
7708
7709/////////////////////////// Softint ///////////////////////////////////// {{{
7710
7711 // Softint Register hardware Update Detection
7712
7713 // Non software updates (TM/SM)
7714
7715 // If any read occurs, send value right away.
7716 // While a read/write is pending, do not update delta.
7717 // Send non read/wr delta during fw2 ..
7718
7719 // RTL keeps pic_ovf indication in rd_softint and not softint.
7720 // So for set/clear writes, we send softint before the write ..,
7721 // and for read/asyncs we send rd_softint ..
7722
7723
7724 if (~`SOFTINT_RDWR_26) begin // {
7725 if (softint !== `RD_SOFTINT_REG_26 )
7726 softint_delta <= 1'b1;
7727 softint <= `RD_SOFTINT_REG_26;
7728 end // }
7729
7730 if ((`NAS_PIPE_FW2_26 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
7731 ) begin // {
7732 `PR_INFO ("pli_int", `INFO,
7733 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
7734 mycid,mytid, {47'h0, softint});
7735 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7736 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
7737 {47'h0, softint});
7738 end // }
7739 if (!(~`SOFTINT_RDWR_26&(softint !== `RD_SOFTINT_REG_26)))
7740 softint_delta <= 1'b0;
7741 end //}
7742 else if (`SPC3.tlu.asi_wr_clear_softint[2] |
7743 `SPC3.tlu.asi_wr_set_softint[2] ) begin // {
7744 `PR_INFO ("pli_int", `INFO,
7745 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
7746 mycid,mytid, {47'h0, `RD_SOFTINT_REG_26});
7747 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7748 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
7749 {47'h0, `RD_SOFTINT_REG_26});
7750 end // }
7751 end //}
7752
7753
7754 softint_rdwr <= `SOFTINT_RDWR_26 ;
7755 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_26;
7756
7757
7758/////////////////////////// Softint ///////////////////////////////////// }}}
7759
7760/////////////////////////// Hintp ///////////////////////////////////// {{{
7761
7762 // Hintp Register hardware Update Detection
7763
7764 // Non software updates (HSP)
7765 // If HINTP is already read/written by SW, then don't send
7766 // any async updates to Nas. Reads/Writes pending sstep is detected
7767 // by snooping nas_pipe ..
7768
7769 hintp <= `HINTP_REG_26 ;
7770 if (hstmatch_late)
7771 hintp_delta <= 1'b1;
7772
7773 if ((~hintp_rdwr & `NAS_PIPE_FW2_26 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
7774 (hintp_rdwr_late & hintp_delta) ) begin // {
7775 `PR_INFO ("pli_int", `INFO,
7776 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
7777 mycid,mytid, {63'h0, hintp});
7778 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7779 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
7780 {63'h0, hintp});
7781 end // }
7782 if (~(hintp_rdwr_late & hintp_delta))
7783 hintp_delta <= 1'b0;
7784 end //}
7785
7786 hintp_rdwr <= `HINTP_RDWR_26;
7787 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_26;
7788 hstmatch_late <= `HSTMATCH_26;
7789
7790
7791/////////////////////////// Hintp ///////////////////////////////////// }}}
7792
7793end //}
7794`endif
7795endmodule
7796
7797// }}}
7798
7799module int_c3t3 ();
7800`ifndef GATESIM
7801
7802// common defines
7803`include "defines.vh"
7804`include "ccx.vri"
7805`include "cmp.vri"
7806
7807wire [2:0] mycid;
7808wire [2:0] mytid;
7809wire [5:0] mytnum;
7810integer junk;
7811
7812reg [63:0] int_vec_recv_reg;
7813reg int_vec_recv_reg_delta;
7814reg int_vec_reg_rdwr;
7815reg inc_vec_reg_rd;
7816reg int_vec_reg_rdwr_late;
7817reg [16:0] softint;
7818reg softint_rdwr;
7819reg softint_rdwr_late;
7820reg softint_delta;
7821reg hintp;
7822reg hintp_rdwr;
7823reg hintp_rdwr_late;
7824reg hintp_delta;
7825reg hstmatch_late;
7826reg ready;
7827reg [7:0] int_num_w;
7828reg [7:0] int_num_fx4;
7829reg [7:0] int_num_fx5;
7830reg [7:0] int_num_fb;
7831reg [7:0] int_num_fw;
7832reg [7:0] int_num_fw1;
7833reg [7:0] int_num_fw2;
7834reg take_disrupting_w;
7835reg take_disrupting_fx4;
7836reg take_disrupting_fx5;
7837reg take_disrupting_fb;
7838reg take_disrupting_fw;
7839reg take_disrupting_fw1;
7840reg take_disrupting_fw2;
7841
7842 assign mycid = 3;
7843 assign mytid = 3;
7844 assign mytnum = 3*8 + 3;
7845
7846initial begin // {
7847 ready = 0; // Wait for socket setup ..
7848 inc_vec_reg_rd <= 1'b0;
7849 int_vec_recv_reg_delta <= 1'b0;
7850 softint_delta <= 1'b0;
7851 hintp_delta <= 1'b0;
7852 int_vec_recv_reg = 64'b0;
7853 @(posedge `BENCH_SPC3_GCLK) ;
7854 @(posedge `BENCH_SPC3_GCLK) ;
7855 ready = `PARGS.int_sync_on;
7856end //}
7857
7858
7859/////////////////////////////// Probes //////////////////////////////////// {{{
7860
7861`define INT_VEC_RECV_REG_27 `SPC3.tlu.cth.int_rec3
7862`define INT_VEC_RECV_ASIWR_27 (`TOP.nas_top.c3.t3.asi_wr_int_rec_delay)
7863`define INT_VEC_RDWR_27 (`TOP.nas_top.c3.t3.asi_rdwr_int_rec)
7864`define INT_VEC_TAKEN_27 `SPC3.tlu.trl0.take_ivt&`SPC3.tlu.trl0.trap[3]
7865
7866`define CPU_MONDO_TAKEN_27 `SPC3.tlu.trl0.take_mqr&`SPC3.tlu.trl0.trap[3]
7867`define DEV_MONDO_TAKEN_27 `SPC3.tlu.trl0.take_dqr&`SPC3.tlu.trl0.trap[3]
7868`define RES_MONDO_TAKEN_27 `SPC3.tlu.trl0.take_rqr&`SPC3.tlu.trl0.trap[3]
7869
7870`define XIR_TAKEN_27 `SPC3.tlu.trl0.take_xir&`SPC3.tlu.trl0.trap[3]
7871
7872`define SOFTINT_RDWR_27 (`TOP.nas_top.c3.t3.asi_rdwr_softint|`TOP.nas_top.c3.t3.asi_wr_softint_delay)
7873
7874`define SOFTINT_REG_27 `SPC3.tlu.trl0.softint3
7875`define RD_SOFTINT_REG_27 `SPC3.tlu.trl0.rd_softint3
7876`define INT_LEVEL_TAKEN_27 `SPC3.tlu.trl0.take_iln&`SPC3.tlu.trl0.trap[3]
7877`define INT_LEVEL_NUM_27 `SPC3.tlu.trl0.int_level_n
7878`define PMU_TAKEN_27 `SPC3.tlu.trl0.take_pmu&`SPC3.tlu.trl0.trap[3]
7879
7880`define HINTP_RDWR_27 (`TOP.nas_top.c3.t3.asi_rdwr_hintp | `TOP.nas_top.c3.t3.asi_wr_hintp_delay)
7881`define HINTP_WR_27 (`SPC3.tlu.asi_wr_hintp[27])
7882`define HSTMATCH_27 `SPC3.tlu.trl0.hstick3_compare
7883
7884`define HINTP_REG_27 `SPC3.tlu.trl0.hintp3
7885`define HSTM_TAKEN_27 `SPC3.tlu.trl0.take_hst&`SPC3.tlu.trl0.trap[3]
7886
7887`define NAS_PIPE_FW2_27 |`TOP.nas_top.c3.t3.complete_fw2
7888
7889`define CWQ_TAKEN_27 `SPC3.tlu.trl0.take_cwq&`SPC3.tlu.trl0.trap[3]
7890`define SMA_TAKEN_27 `SPC3.tlu.trl0.take_sma&`SPC3.tlu.trl0.trap[3]
7891
7892`define POR_TAKEN_27 `SPC3.tlu.trl0.take_por&`SPC3.tlu.trl0.trap[3]
7893
7894/////////////////////////////// Probes //////////////////////////////////// }}}
7895
7896always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
7897
7898 // {{{ DETECT, PIPE & SEND
7899 take_disrupting_w <= (`INT_VEC_TAKEN_27 || `CPU_MONDO_TAKEN_27 ||
7900 `DEV_MONDO_TAKEN_27 || `RES_MONDO_TAKEN_27 ||
7901 `XIR_TAKEN_27 || `INT_LEVEL_TAKEN_27 ||
7902 `HSTM_TAKEN_27 || `CWQ_TAKEN_27 ||
7903 `SMA_TAKEN_27 || `PMU_TAKEN_27 || `POR_TAKEN_27);
7904 take_disrupting_fx4 <= take_disrupting_w;
7905 take_disrupting_fx5 <= take_disrupting_fx4;
7906 take_disrupting_fb <= take_disrupting_fx5;
7907 take_disrupting_fw <= take_disrupting_fb;
7908 take_disrupting_fw1 <= take_disrupting_fw;
7909 take_disrupting_fw2 <= take_disrupting_fw1;
7910
7911 case ({`INT_VEC_TAKEN_27, `CPU_MONDO_TAKEN_27,
7912 `DEV_MONDO_TAKEN_27, `RES_MONDO_TAKEN_27,
7913 `XIR_TAKEN_27, `INT_LEVEL_TAKEN_27,
7914 `HSTM_TAKEN_27, `CWQ_TAKEN_27, `SMA_TAKEN_27 ,
7915 `PMU_TAKEN_27, `POR_TAKEN_27})
7916 11'b10000000000: int_num_w <= 8'h60;
7917 11'b01000000000: int_num_w <= 8'h7c;
7918 11'b00100000000: int_num_w <= 8'h7d;
7919 11'b00010000000: int_num_w <= 8'h7e;
7920 11'b00001000000: int_num_w <= 8'h03;
7921 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_27;
7922 11'b00000010000: int_num_w <= 8'h5e;
7923 11'b00000001000: int_num_w <= 8'h3c;
7924 11'b00000000100: int_num_w <= 8'h3d;
7925 11'b00000000010: int_num_w <= 8'h4f;
7926 11'b00000000001: int_num_w <= 8'h01;
7927 endcase
7928
7929 int_num_fx4 <= int_num_w;
7930 int_num_fx5 <= int_num_fx4;
7931 int_num_fb <= int_num_fx5;
7932 int_num_fw <= int_num_fb;
7933 int_num_fw1 <= int_num_fw;
7934 int_num_fw2 <= int_num_fw1;
7935 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
7936 begin // {
7937 `PR_INFO ("pli_int", `INFO,
7938 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
7939 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
7940 end // }
7941
7942 // }}}
7943
7944/////////////////////////// Vectored Interrupt /////////////////////////// {{{
7945
7946 // Vectored Interrupt Recv Register Detection
7947 // Indicate when register changes due to arriving interrupt, and not
7948 // due to read of incoming register or ASI write ..
7949
7950
7951 // If any read occurs, send value right away.
7952 // While a read/write is pending, do not update delta.
7953 // Send non read/wr delta during fw2 ..
7954
7955
7956 if (!(`INT_VEC_RDWR_27 | `INT_VEC_RECV_ASIWR_27)) begin // {
7957 if (~`INT_VEC_RECV_ASIWR_27 &
7958 (int_vec_recv_reg !== `INT_VEC_RECV_REG_27 ))
7959 int_vec_recv_reg_delta <= 1'b1;
7960 int_vec_recv_reg <= `INT_VEC_RECV_REG_27;
7961 end // }
7962 else if (`INT_VEC_RECV_ASIWR_27)
7963 int_vec_recv_reg <= `TOP.nas_top.c3.t3.asi_updated_int_rec;
7964
7965 if ((`NAS_PIPE_FW2_27 & int_vec_recv_reg_delta ) |
7966 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
7967 `INT_VEC_RECV_ASIWR_27 ) begin // {
7968 `PR_INFO ("pli_int", `INFO,
7969 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
7970 mycid,mytid, int_vec_recv_reg);
7971 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
7972 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
7973 64'h0, int_vec_recv_reg);
7974 end // }
7975 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_27 &
7976 (int_vec_recv_reg !== `INT_VEC_RECV_REG_27 ))))
7977 int_vec_recv_reg_delta <= 1'b0;
7978 end //}
7979
7980 int_vec_reg_rdwr <= `INT_VEC_RDWR_27 | `INT_VEC_RECV_ASIWR_27;
7981 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_27 & ~ inc_vec_reg_rd;
7982
7983 if (`INT_VEC_RECV_ASIWR_27)
7984 inc_vec_reg_rd <= 1'b1;
7985 if (`NAS_PIPE_FW2_27)
7986 inc_vec_reg_rd <= 1'b0;
7987
7988
7989/////////////////////////// Vectored Interrupt /////////////////////////// }}}
7990
7991/////////////////////////// Asynchronous Resets ////////////////////////// {{{
7992
7993
7994/////////////////////////// Asynchronous Resets ////////////////////////// }}}
7995
7996/////////////////////////// Softint ///////////////////////////////////// {{{
7997
7998 // Softint Register hardware Update Detection
7999
8000 // Non software updates (TM/SM)
8001
8002 // If any read occurs, send value right away.
8003 // While a read/write is pending, do not update delta.
8004 // Send non read/wr delta during fw2 ..
8005
8006 // RTL keeps pic_ovf indication in rd_softint and not softint.
8007 // So for set/clear writes, we send softint before the write ..,
8008 // and for read/asyncs we send rd_softint ..
8009
8010
8011 if (~`SOFTINT_RDWR_27) begin // {
8012 if (softint !== `RD_SOFTINT_REG_27 )
8013 softint_delta <= 1'b1;
8014 softint <= `RD_SOFTINT_REG_27;
8015 end // }
8016
8017 if ((`NAS_PIPE_FW2_27 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
8018 ) begin // {
8019 `PR_INFO ("pli_int", `INFO,
8020 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8021 mycid,mytid, {47'h0, softint});
8022 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8023 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8024 {47'h0, softint});
8025 end // }
8026 if (!(~`SOFTINT_RDWR_27&(softint !== `RD_SOFTINT_REG_27)))
8027 softint_delta <= 1'b0;
8028 end //}
8029 else if (`SPC3.tlu.asi_wr_clear_softint[3] |
8030 `SPC3.tlu.asi_wr_set_softint[3] ) begin // {
8031 `PR_INFO ("pli_int", `INFO,
8032 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8033 mycid,mytid, {47'h0, `RD_SOFTINT_REG_27});
8034 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8035 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8036 {47'h0, `RD_SOFTINT_REG_27});
8037 end // }
8038 end //}
8039
8040
8041 softint_rdwr <= `SOFTINT_RDWR_27 ;
8042 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_27;
8043
8044
8045/////////////////////////// Softint ///////////////////////////////////// }}}
8046
8047/////////////////////////// Hintp ///////////////////////////////////// {{{
8048
8049 // Hintp Register hardware Update Detection
8050
8051 // Non software updates (HSP)
8052 // If HINTP is already read/written by SW, then don't send
8053 // any async updates to Nas. Reads/Writes pending sstep is detected
8054 // by snooping nas_pipe ..
8055
8056 hintp <= `HINTP_REG_27 ;
8057 if (hstmatch_late)
8058 hintp_delta <= 1'b1;
8059
8060 if ((~hintp_rdwr & `NAS_PIPE_FW2_27 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
8061 (hintp_rdwr_late & hintp_delta) ) begin // {
8062 `PR_INFO ("pli_int", `INFO,
8063 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
8064 mycid,mytid, {63'h0, hintp});
8065 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8066 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
8067 {63'h0, hintp});
8068 end // }
8069 if (~(hintp_rdwr_late & hintp_delta))
8070 hintp_delta <= 1'b0;
8071 end //}
8072
8073 hintp_rdwr <= `HINTP_RDWR_27;
8074 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_27;
8075 hstmatch_late <= `HSTMATCH_27;
8076
8077
8078/////////////////////////// Hintp ///////////////////////////////////// }}}
8079
8080end //}
8081`endif
8082endmodule
8083
8084// }}}
8085
8086module int_c3t4 ();
8087`ifndef GATESIM
8088
8089// common defines
8090`include "defines.vh"
8091`include "ccx.vri"
8092`include "cmp.vri"
8093
8094wire [2:0] mycid;
8095wire [2:0] mytid;
8096wire [5:0] mytnum;
8097integer junk;
8098
8099reg [63:0] int_vec_recv_reg;
8100reg int_vec_recv_reg_delta;
8101reg int_vec_reg_rdwr;
8102reg inc_vec_reg_rd;
8103reg int_vec_reg_rdwr_late;
8104reg [16:0] softint;
8105reg softint_rdwr;
8106reg softint_rdwr_late;
8107reg softint_delta;
8108reg hintp;
8109reg hintp_rdwr;
8110reg hintp_rdwr_late;
8111reg hintp_delta;
8112reg hstmatch_late;
8113reg ready;
8114reg [7:0] int_num_w;
8115reg [7:0] int_num_fx4;
8116reg [7:0] int_num_fx5;
8117reg [7:0] int_num_fb;
8118reg [7:0] int_num_fw;
8119reg [7:0] int_num_fw1;
8120reg [7:0] int_num_fw2;
8121reg take_disrupting_w;
8122reg take_disrupting_fx4;
8123reg take_disrupting_fx5;
8124reg take_disrupting_fb;
8125reg take_disrupting_fw;
8126reg take_disrupting_fw1;
8127reg take_disrupting_fw2;
8128
8129 assign mycid = 3;
8130 assign mytid = 4;
8131 assign mytnum = 3*8 + 4;
8132
8133initial begin // {
8134 ready = 0; // Wait for socket setup ..
8135 inc_vec_reg_rd <= 1'b0;
8136 int_vec_recv_reg_delta <= 1'b0;
8137 softint_delta <= 1'b0;
8138 hintp_delta <= 1'b0;
8139 int_vec_recv_reg = 64'b0;
8140 @(posedge `BENCH_SPC3_GCLK) ;
8141 @(posedge `BENCH_SPC3_GCLK) ;
8142 ready = `PARGS.int_sync_on;
8143end //}
8144
8145
8146/////////////////////////////// Probes //////////////////////////////////// {{{
8147
8148`define INT_VEC_RECV_REG_28 `SPC3.tlu.cth.int_rec4
8149`define INT_VEC_RECV_ASIWR_28 (`TOP.nas_top.c3.t4.asi_wr_int_rec_delay)
8150`define INT_VEC_RDWR_28 (`TOP.nas_top.c3.t4.asi_rdwr_int_rec)
8151`define INT_VEC_TAKEN_28 `SPC3.tlu.trl1.take_ivt&`SPC3.tlu.trl1.trap[0]
8152
8153`define CPU_MONDO_TAKEN_28 `SPC3.tlu.trl1.take_mqr&`SPC3.tlu.trl1.trap[0]
8154`define DEV_MONDO_TAKEN_28 `SPC3.tlu.trl1.take_dqr&`SPC3.tlu.trl1.trap[0]
8155`define RES_MONDO_TAKEN_28 `SPC3.tlu.trl1.take_rqr&`SPC3.tlu.trl1.trap[0]
8156
8157`define XIR_TAKEN_28 `SPC3.tlu.trl1.take_xir&`SPC3.tlu.trl1.trap[0]
8158
8159`define SOFTINT_RDWR_28 (`TOP.nas_top.c3.t4.asi_rdwr_softint|`TOP.nas_top.c3.t4.asi_wr_softint_delay)
8160
8161`define SOFTINT_REG_28 `SPC3.tlu.trl1.softint0
8162`define RD_SOFTINT_REG_28 `SPC3.tlu.trl1.rd_softint0
8163`define INT_LEVEL_TAKEN_28 `SPC3.tlu.trl1.take_iln&`SPC3.tlu.trl1.trap[0]
8164`define INT_LEVEL_NUM_28 `SPC3.tlu.trl1.int_level_n
8165`define PMU_TAKEN_28 `SPC3.tlu.trl1.take_pmu&`SPC3.tlu.trl1.trap[0]
8166
8167`define HINTP_RDWR_28 (`TOP.nas_top.c3.t4.asi_rdwr_hintp | `TOP.nas_top.c3.t4.asi_wr_hintp_delay)
8168`define HINTP_WR_28 (`SPC3.tlu.asi_wr_hintp[28])
8169`define HSTMATCH_28 `SPC3.tlu.trl1.hstick0_compare
8170
8171`define HINTP_REG_28 `SPC3.tlu.trl1.hintp0
8172`define HSTM_TAKEN_28 `SPC3.tlu.trl1.take_hst&`SPC3.tlu.trl1.trap[0]
8173
8174`define NAS_PIPE_FW2_28 |`TOP.nas_top.c3.t4.complete_fw2
8175
8176`define CWQ_TAKEN_28 `SPC3.tlu.trl1.take_cwq&`SPC3.tlu.trl1.trap[0]
8177`define SMA_TAKEN_28 `SPC3.tlu.trl1.take_sma&`SPC3.tlu.trl1.trap[0]
8178
8179`define POR_TAKEN_28 `SPC3.tlu.trl1.take_por&`SPC3.tlu.trl1.trap[0]
8180
8181/////////////////////////////// Probes //////////////////////////////////// }}}
8182
8183always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
8184
8185 // {{{ DETECT, PIPE & SEND
8186 take_disrupting_w <= (`INT_VEC_TAKEN_28 || `CPU_MONDO_TAKEN_28 ||
8187 `DEV_MONDO_TAKEN_28 || `RES_MONDO_TAKEN_28 ||
8188 `XIR_TAKEN_28 || `INT_LEVEL_TAKEN_28 ||
8189 `HSTM_TAKEN_28 || `CWQ_TAKEN_28 ||
8190 `SMA_TAKEN_28 || `PMU_TAKEN_28 || `POR_TAKEN_28);
8191 take_disrupting_fx4 <= take_disrupting_w;
8192 take_disrupting_fx5 <= take_disrupting_fx4;
8193 take_disrupting_fb <= take_disrupting_fx5;
8194 take_disrupting_fw <= take_disrupting_fb;
8195 take_disrupting_fw1 <= take_disrupting_fw;
8196 take_disrupting_fw2 <= take_disrupting_fw1;
8197
8198 case ({`INT_VEC_TAKEN_28, `CPU_MONDO_TAKEN_28,
8199 `DEV_MONDO_TAKEN_28, `RES_MONDO_TAKEN_28,
8200 `XIR_TAKEN_28, `INT_LEVEL_TAKEN_28,
8201 `HSTM_TAKEN_28, `CWQ_TAKEN_28, `SMA_TAKEN_28 ,
8202 `PMU_TAKEN_28, `POR_TAKEN_28})
8203 11'b10000000000: int_num_w <= 8'h60;
8204 11'b01000000000: int_num_w <= 8'h7c;
8205 11'b00100000000: int_num_w <= 8'h7d;
8206 11'b00010000000: int_num_w <= 8'h7e;
8207 11'b00001000000: int_num_w <= 8'h03;
8208 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_28;
8209 11'b00000010000: int_num_w <= 8'h5e;
8210 11'b00000001000: int_num_w <= 8'h3c;
8211 11'b00000000100: int_num_w <= 8'h3d;
8212 11'b00000000010: int_num_w <= 8'h4f;
8213 11'b00000000001: int_num_w <= 8'h01;
8214 endcase
8215
8216 int_num_fx4 <= int_num_w;
8217 int_num_fx5 <= int_num_fx4;
8218 int_num_fb <= int_num_fx5;
8219 int_num_fw <= int_num_fb;
8220 int_num_fw1 <= int_num_fw;
8221 int_num_fw2 <= int_num_fw1;
8222 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
8223 begin // {
8224 `PR_INFO ("pli_int", `INFO,
8225 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
8226 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8227 end // }
8228
8229 // }}}
8230
8231/////////////////////////// Vectored Interrupt /////////////////////////// {{{
8232
8233 // Vectored Interrupt Recv Register Detection
8234 // Indicate when register changes due to arriving interrupt, and not
8235 // due to read of incoming register or ASI write ..
8236
8237
8238 // If any read occurs, send value right away.
8239 // While a read/write is pending, do not update delta.
8240 // Send non read/wr delta during fw2 ..
8241
8242
8243 if (!(`INT_VEC_RDWR_28 | `INT_VEC_RECV_ASIWR_28)) begin // {
8244 if (~`INT_VEC_RECV_ASIWR_28 &
8245 (int_vec_recv_reg !== `INT_VEC_RECV_REG_28 ))
8246 int_vec_recv_reg_delta <= 1'b1;
8247 int_vec_recv_reg <= `INT_VEC_RECV_REG_28;
8248 end // }
8249 else if (`INT_VEC_RECV_ASIWR_28)
8250 int_vec_recv_reg <= `TOP.nas_top.c3.t4.asi_updated_int_rec;
8251
8252 if ((`NAS_PIPE_FW2_28 & int_vec_recv_reg_delta ) |
8253 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
8254 `INT_VEC_RECV_ASIWR_28 ) begin // {
8255 `PR_INFO ("pli_int", `INFO,
8256 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
8257 mycid,mytid, int_vec_recv_reg);
8258 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8259 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
8260 64'h0, int_vec_recv_reg);
8261 end // }
8262 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_28 &
8263 (int_vec_recv_reg !== `INT_VEC_RECV_REG_28 ))))
8264 int_vec_recv_reg_delta <= 1'b0;
8265 end //}
8266
8267 int_vec_reg_rdwr <= `INT_VEC_RDWR_28 | `INT_VEC_RECV_ASIWR_28;
8268 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_28 & ~ inc_vec_reg_rd;
8269
8270 if (`INT_VEC_RECV_ASIWR_28)
8271 inc_vec_reg_rd <= 1'b1;
8272 if (`NAS_PIPE_FW2_28)
8273 inc_vec_reg_rd <= 1'b0;
8274
8275
8276/////////////////////////// Vectored Interrupt /////////////////////////// }}}
8277
8278/////////////////////////// Asynchronous Resets ////////////////////////// {{{
8279
8280
8281/////////////////////////// Asynchronous Resets ////////////////////////// }}}
8282
8283/////////////////////////// Softint ///////////////////////////////////// {{{
8284
8285 // Softint Register hardware Update Detection
8286
8287 // Non software updates (TM/SM)
8288
8289 // If any read occurs, send value right away.
8290 // While a read/write is pending, do not update delta.
8291 // Send non read/wr delta during fw2 ..
8292
8293 // RTL keeps pic_ovf indication in rd_softint and not softint.
8294 // So for set/clear writes, we send softint before the write ..,
8295 // and for read/asyncs we send rd_softint ..
8296
8297
8298 if (~`SOFTINT_RDWR_28) begin // {
8299 if (softint !== `RD_SOFTINT_REG_28 )
8300 softint_delta <= 1'b1;
8301 softint <= `RD_SOFTINT_REG_28;
8302 end // }
8303
8304 if ((`NAS_PIPE_FW2_28 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
8305 ) begin // {
8306 `PR_INFO ("pli_int", `INFO,
8307 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8308 mycid,mytid, {47'h0, softint});
8309 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8310 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8311 {47'h0, softint});
8312 end // }
8313 if (!(~`SOFTINT_RDWR_28&(softint !== `RD_SOFTINT_REG_28)))
8314 softint_delta <= 1'b0;
8315 end //}
8316 else if (`SPC3.tlu.asi_wr_clear_softint[4] |
8317 `SPC3.tlu.asi_wr_set_softint[4] ) begin // {
8318 `PR_INFO ("pli_int", `INFO,
8319 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8320 mycid,mytid, {47'h0, `RD_SOFTINT_REG_28});
8321 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8322 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8323 {47'h0, `RD_SOFTINT_REG_28});
8324 end // }
8325 end //}
8326
8327
8328 softint_rdwr <= `SOFTINT_RDWR_28 ;
8329 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_28;
8330
8331
8332/////////////////////////// Softint ///////////////////////////////////// }}}
8333
8334/////////////////////////// Hintp ///////////////////////////////////// {{{
8335
8336 // Hintp Register hardware Update Detection
8337
8338 // Non software updates (HSP)
8339 // If HINTP is already read/written by SW, then don't send
8340 // any async updates to Nas. Reads/Writes pending sstep is detected
8341 // by snooping nas_pipe ..
8342
8343 hintp <= `HINTP_REG_28 ;
8344 if (hstmatch_late)
8345 hintp_delta <= 1'b1;
8346
8347 if ((~hintp_rdwr & `NAS_PIPE_FW2_28 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
8348 (hintp_rdwr_late & hintp_delta) ) begin // {
8349 `PR_INFO ("pli_int", `INFO,
8350 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
8351 mycid,mytid, {63'h0, hintp});
8352 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8353 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
8354 {63'h0, hintp});
8355 end // }
8356 if (~(hintp_rdwr_late & hintp_delta))
8357 hintp_delta <= 1'b0;
8358 end //}
8359
8360 hintp_rdwr <= `HINTP_RDWR_28;
8361 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_28;
8362 hstmatch_late <= `HSTMATCH_28;
8363
8364
8365/////////////////////////// Hintp ///////////////////////////////////// }}}
8366
8367end //}
8368`endif
8369endmodule
8370
8371// }}}
8372
8373module int_c3t5 ();
8374`ifndef GATESIM
8375
8376// common defines
8377`include "defines.vh"
8378`include "ccx.vri"
8379`include "cmp.vri"
8380
8381wire [2:0] mycid;
8382wire [2:0] mytid;
8383wire [5:0] mytnum;
8384integer junk;
8385
8386reg [63:0] int_vec_recv_reg;
8387reg int_vec_recv_reg_delta;
8388reg int_vec_reg_rdwr;
8389reg inc_vec_reg_rd;
8390reg int_vec_reg_rdwr_late;
8391reg [16:0] softint;
8392reg softint_rdwr;
8393reg softint_rdwr_late;
8394reg softint_delta;
8395reg hintp;
8396reg hintp_rdwr;
8397reg hintp_rdwr_late;
8398reg hintp_delta;
8399reg hstmatch_late;
8400reg ready;
8401reg [7:0] int_num_w;
8402reg [7:0] int_num_fx4;
8403reg [7:0] int_num_fx5;
8404reg [7:0] int_num_fb;
8405reg [7:0] int_num_fw;
8406reg [7:0] int_num_fw1;
8407reg [7:0] int_num_fw2;
8408reg take_disrupting_w;
8409reg take_disrupting_fx4;
8410reg take_disrupting_fx5;
8411reg take_disrupting_fb;
8412reg take_disrupting_fw;
8413reg take_disrupting_fw1;
8414reg take_disrupting_fw2;
8415
8416 assign mycid = 3;
8417 assign mytid = 5;
8418 assign mytnum = 3*8 + 5;
8419
8420initial begin // {
8421 ready = 0; // Wait for socket setup ..
8422 inc_vec_reg_rd <= 1'b0;
8423 int_vec_recv_reg_delta <= 1'b0;
8424 softint_delta <= 1'b0;
8425 hintp_delta <= 1'b0;
8426 int_vec_recv_reg = 64'b0;
8427 @(posedge `BENCH_SPC3_GCLK) ;
8428 @(posedge `BENCH_SPC3_GCLK) ;
8429 ready = `PARGS.int_sync_on;
8430end //}
8431
8432
8433/////////////////////////////// Probes //////////////////////////////////// {{{
8434
8435`define INT_VEC_RECV_REG_29 `SPC3.tlu.cth.int_rec5
8436`define INT_VEC_RECV_ASIWR_29 (`TOP.nas_top.c3.t5.asi_wr_int_rec_delay)
8437`define INT_VEC_RDWR_29 (`TOP.nas_top.c3.t5.asi_rdwr_int_rec)
8438`define INT_VEC_TAKEN_29 `SPC3.tlu.trl1.take_ivt&`SPC3.tlu.trl1.trap[1]
8439
8440`define CPU_MONDO_TAKEN_29 `SPC3.tlu.trl1.take_mqr&`SPC3.tlu.trl1.trap[1]
8441`define DEV_MONDO_TAKEN_29 `SPC3.tlu.trl1.take_dqr&`SPC3.tlu.trl1.trap[1]
8442`define RES_MONDO_TAKEN_29 `SPC3.tlu.trl1.take_rqr&`SPC3.tlu.trl1.trap[1]
8443
8444`define XIR_TAKEN_29 `SPC3.tlu.trl1.take_xir&`SPC3.tlu.trl1.trap[1]
8445
8446`define SOFTINT_RDWR_29 (`TOP.nas_top.c3.t5.asi_rdwr_softint|`TOP.nas_top.c3.t5.asi_wr_softint_delay)
8447
8448`define SOFTINT_REG_29 `SPC3.tlu.trl1.softint1
8449`define RD_SOFTINT_REG_29 `SPC3.tlu.trl1.rd_softint1
8450`define INT_LEVEL_TAKEN_29 `SPC3.tlu.trl1.take_iln&`SPC3.tlu.trl1.trap[1]
8451`define INT_LEVEL_NUM_29 `SPC3.tlu.trl1.int_level_n
8452`define PMU_TAKEN_29 `SPC3.tlu.trl1.take_pmu&`SPC3.tlu.trl1.trap[1]
8453
8454`define HINTP_RDWR_29 (`TOP.nas_top.c3.t5.asi_rdwr_hintp | `TOP.nas_top.c3.t5.asi_wr_hintp_delay)
8455`define HINTP_WR_29 (`SPC3.tlu.asi_wr_hintp[29])
8456`define HSTMATCH_29 `SPC3.tlu.trl1.hstick1_compare
8457
8458`define HINTP_REG_29 `SPC3.tlu.trl1.hintp1
8459`define HSTM_TAKEN_29 `SPC3.tlu.trl1.take_hst&`SPC3.tlu.trl1.trap[1]
8460
8461`define NAS_PIPE_FW2_29 |`TOP.nas_top.c3.t5.complete_fw2
8462
8463`define CWQ_TAKEN_29 `SPC3.tlu.trl1.take_cwq&`SPC3.tlu.trl1.trap[1]
8464`define SMA_TAKEN_29 `SPC3.tlu.trl1.take_sma&`SPC3.tlu.trl1.trap[1]
8465
8466`define POR_TAKEN_29 `SPC3.tlu.trl1.take_por&`SPC3.tlu.trl1.trap[1]
8467
8468/////////////////////////////// Probes //////////////////////////////////// }}}
8469
8470always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
8471
8472 // {{{ DETECT, PIPE & SEND
8473 take_disrupting_w <= (`INT_VEC_TAKEN_29 || `CPU_MONDO_TAKEN_29 ||
8474 `DEV_MONDO_TAKEN_29 || `RES_MONDO_TAKEN_29 ||
8475 `XIR_TAKEN_29 || `INT_LEVEL_TAKEN_29 ||
8476 `HSTM_TAKEN_29 || `CWQ_TAKEN_29 ||
8477 `SMA_TAKEN_29 || `PMU_TAKEN_29 || `POR_TAKEN_29);
8478 take_disrupting_fx4 <= take_disrupting_w;
8479 take_disrupting_fx5 <= take_disrupting_fx4;
8480 take_disrupting_fb <= take_disrupting_fx5;
8481 take_disrupting_fw <= take_disrupting_fb;
8482 take_disrupting_fw1 <= take_disrupting_fw;
8483 take_disrupting_fw2 <= take_disrupting_fw1;
8484
8485 case ({`INT_VEC_TAKEN_29, `CPU_MONDO_TAKEN_29,
8486 `DEV_MONDO_TAKEN_29, `RES_MONDO_TAKEN_29,
8487 `XIR_TAKEN_29, `INT_LEVEL_TAKEN_29,
8488 `HSTM_TAKEN_29, `CWQ_TAKEN_29, `SMA_TAKEN_29 ,
8489 `PMU_TAKEN_29, `POR_TAKEN_29})
8490 11'b10000000000: int_num_w <= 8'h60;
8491 11'b01000000000: int_num_w <= 8'h7c;
8492 11'b00100000000: int_num_w <= 8'h7d;
8493 11'b00010000000: int_num_w <= 8'h7e;
8494 11'b00001000000: int_num_w <= 8'h03;
8495 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_29;
8496 11'b00000010000: int_num_w <= 8'h5e;
8497 11'b00000001000: int_num_w <= 8'h3c;
8498 11'b00000000100: int_num_w <= 8'h3d;
8499 11'b00000000010: int_num_w <= 8'h4f;
8500 11'b00000000001: int_num_w <= 8'h01;
8501 endcase
8502
8503 int_num_fx4 <= int_num_w;
8504 int_num_fx5 <= int_num_fx4;
8505 int_num_fb <= int_num_fx5;
8506 int_num_fw <= int_num_fb;
8507 int_num_fw1 <= int_num_fw;
8508 int_num_fw2 <= int_num_fw1;
8509 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
8510 begin // {
8511 `PR_INFO ("pli_int", `INFO,
8512 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
8513 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8514 end // }
8515
8516 // }}}
8517
8518/////////////////////////// Vectored Interrupt /////////////////////////// {{{
8519
8520 // Vectored Interrupt Recv Register Detection
8521 // Indicate when register changes due to arriving interrupt, and not
8522 // due to read of incoming register or ASI write ..
8523
8524
8525 // If any read occurs, send value right away.
8526 // While a read/write is pending, do not update delta.
8527 // Send non read/wr delta during fw2 ..
8528
8529
8530 if (!(`INT_VEC_RDWR_29 | `INT_VEC_RECV_ASIWR_29)) begin // {
8531 if (~`INT_VEC_RECV_ASIWR_29 &
8532 (int_vec_recv_reg !== `INT_VEC_RECV_REG_29 ))
8533 int_vec_recv_reg_delta <= 1'b1;
8534 int_vec_recv_reg <= `INT_VEC_RECV_REG_29;
8535 end // }
8536 else if (`INT_VEC_RECV_ASIWR_29)
8537 int_vec_recv_reg <= `TOP.nas_top.c3.t5.asi_updated_int_rec;
8538
8539 if ((`NAS_PIPE_FW2_29 & int_vec_recv_reg_delta ) |
8540 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
8541 `INT_VEC_RECV_ASIWR_29 ) begin // {
8542 `PR_INFO ("pli_int", `INFO,
8543 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
8544 mycid,mytid, int_vec_recv_reg);
8545 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8546 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
8547 64'h0, int_vec_recv_reg);
8548 end // }
8549 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_29 &
8550 (int_vec_recv_reg !== `INT_VEC_RECV_REG_29 ))))
8551 int_vec_recv_reg_delta <= 1'b0;
8552 end //}
8553
8554 int_vec_reg_rdwr <= `INT_VEC_RDWR_29 | `INT_VEC_RECV_ASIWR_29;
8555 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_29 & ~ inc_vec_reg_rd;
8556
8557 if (`INT_VEC_RECV_ASIWR_29)
8558 inc_vec_reg_rd <= 1'b1;
8559 if (`NAS_PIPE_FW2_29)
8560 inc_vec_reg_rd <= 1'b0;
8561
8562
8563/////////////////////////// Vectored Interrupt /////////////////////////// }}}
8564
8565/////////////////////////// Asynchronous Resets ////////////////////////// {{{
8566
8567
8568/////////////////////////// Asynchronous Resets ////////////////////////// }}}
8569
8570/////////////////////////// Softint ///////////////////////////////////// {{{
8571
8572 // Softint Register hardware Update Detection
8573
8574 // Non software updates (TM/SM)
8575
8576 // If any read occurs, send value right away.
8577 // While a read/write is pending, do not update delta.
8578 // Send non read/wr delta during fw2 ..
8579
8580 // RTL keeps pic_ovf indication in rd_softint and not softint.
8581 // So for set/clear writes, we send softint before the write ..,
8582 // and for read/asyncs we send rd_softint ..
8583
8584
8585 if (~`SOFTINT_RDWR_29) begin // {
8586 if (softint !== `RD_SOFTINT_REG_29 )
8587 softint_delta <= 1'b1;
8588 softint <= `RD_SOFTINT_REG_29;
8589 end // }
8590
8591 if ((`NAS_PIPE_FW2_29 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
8592 ) begin // {
8593 `PR_INFO ("pli_int", `INFO,
8594 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8595 mycid,mytid, {47'h0, softint});
8596 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8597 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8598 {47'h0, softint});
8599 end // }
8600 if (!(~`SOFTINT_RDWR_29&(softint !== `RD_SOFTINT_REG_29)))
8601 softint_delta <= 1'b0;
8602 end //}
8603 else if (`SPC3.tlu.asi_wr_clear_softint[5] |
8604 `SPC3.tlu.asi_wr_set_softint[5] ) begin // {
8605 `PR_INFO ("pli_int", `INFO,
8606 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8607 mycid,mytid, {47'h0, `RD_SOFTINT_REG_29});
8608 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8609 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8610 {47'h0, `RD_SOFTINT_REG_29});
8611 end // }
8612 end //}
8613
8614
8615 softint_rdwr <= `SOFTINT_RDWR_29 ;
8616 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_29;
8617
8618
8619/////////////////////////// Softint ///////////////////////////////////// }}}
8620
8621/////////////////////////// Hintp ///////////////////////////////////// {{{
8622
8623 // Hintp Register hardware Update Detection
8624
8625 // Non software updates (HSP)
8626 // If HINTP is already read/written by SW, then don't send
8627 // any async updates to Nas. Reads/Writes pending sstep is detected
8628 // by snooping nas_pipe ..
8629
8630 hintp <= `HINTP_REG_29 ;
8631 if (hstmatch_late)
8632 hintp_delta <= 1'b1;
8633
8634 if ((~hintp_rdwr & `NAS_PIPE_FW2_29 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
8635 (hintp_rdwr_late & hintp_delta) ) begin // {
8636 `PR_INFO ("pli_int", `INFO,
8637 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
8638 mycid,mytid, {63'h0, hintp});
8639 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8640 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
8641 {63'h0, hintp});
8642 end // }
8643 if (~(hintp_rdwr_late & hintp_delta))
8644 hintp_delta <= 1'b0;
8645 end //}
8646
8647 hintp_rdwr <= `HINTP_RDWR_29;
8648 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_29;
8649 hstmatch_late <= `HSTMATCH_29;
8650
8651
8652/////////////////////////// Hintp ///////////////////////////////////// }}}
8653
8654end //}
8655`endif
8656endmodule
8657
8658// }}}
8659
8660module int_c3t6 ();
8661`ifndef GATESIM
8662
8663// common defines
8664`include "defines.vh"
8665`include "ccx.vri"
8666`include "cmp.vri"
8667
8668wire [2:0] mycid;
8669wire [2:0] mytid;
8670wire [5:0] mytnum;
8671integer junk;
8672
8673reg [63:0] int_vec_recv_reg;
8674reg int_vec_recv_reg_delta;
8675reg int_vec_reg_rdwr;
8676reg inc_vec_reg_rd;
8677reg int_vec_reg_rdwr_late;
8678reg [16:0] softint;
8679reg softint_rdwr;
8680reg softint_rdwr_late;
8681reg softint_delta;
8682reg hintp;
8683reg hintp_rdwr;
8684reg hintp_rdwr_late;
8685reg hintp_delta;
8686reg hstmatch_late;
8687reg ready;
8688reg [7:0] int_num_w;
8689reg [7:0] int_num_fx4;
8690reg [7:0] int_num_fx5;
8691reg [7:0] int_num_fb;
8692reg [7:0] int_num_fw;
8693reg [7:0] int_num_fw1;
8694reg [7:0] int_num_fw2;
8695reg take_disrupting_w;
8696reg take_disrupting_fx4;
8697reg take_disrupting_fx5;
8698reg take_disrupting_fb;
8699reg take_disrupting_fw;
8700reg take_disrupting_fw1;
8701reg take_disrupting_fw2;
8702
8703 assign mycid = 3;
8704 assign mytid = 6;
8705 assign mytnum = 3*8 + 6;
8706
8707initial begin // {
8708 ready = 0; // Wait for socket setup ..
8709 inc_vec_reg_rd <= 1'b0;
8710 int_vec_recv_reg_delta <= 1'b0;
8711 softint_delta <= 1'b0;
8712 hintp_delta <= 1'b0;
8713 int_vec_recv_reg = 64'b0;
8714 @(posedge `BENCH_SPC3_GCLK) ;
8715 @(posedge `BENCH_SPC3_GCLK) ;
8716 ready = `PARGS.int_sync_on;
8717end //}
8718
8719
8720/////////////////////////////// Probes //////////////////////////////////// {{{
8721
8722`define INT_VEC_RECV_REG_30 `SPC3.tlu.cth.int_rec6
8723`define INT_VEC_RECV_ASIWR_30 (`TOP.nas_top.c3.t6.asi_wr_int_rec_delay)
8724`define INT_VEC_RDWR_30 (`TOP.nas_top.c3.t6.asi_rdwr_int_rec)
8725`define INT_VEC_TAKEN_30 `SPC3.tlu.trl1.take_ivt&`SPC3.tlu.trl1.trap[2]
8726
8727`define CPU_MONDO_TAKEN_30 `SPC3.tlu.trl1.take_mqr&`SPC3.tlu.trl1.trap[2]
8728`define DEV_MONDO_TAKEN_30 `SPC3.tlu.trl1.take_dqr&`SPC3.tlu.trl1.trap[2]
8729`define RES_MONDO_TAKEN_30 `SPC3.tlu.trl1.take_rqr&`SPC3.tlu.trl1.trap[2]
8730
8731`define XIR_TAKEN_30 `SPC3.tlu.trl1.take_xir&`SPC3.tlu.trl1.trap[2]
8732
8733`define SOFTINT_RDWR_30 (`TOP.nas_top.c3.t6.asi_rdwr_softint|`TOP.nas_top.c3.t6.asi_wr_softint_delay)
8734
8735`define SOFTINT_REG_30 `SPC3.tlu.trl1.softint2
8736`define RD_SOFTINT_REG_30 `SPC3.tlu.trl1.rd_softint2
8737`define INT_LEVEL_TAKEN_30 `SPC3.tlu.trl1.take_iln&`SPC3.tlu.trl1.trap[2]
8738`define INT_LEVEL_NUM_30 `SPC3.tlu.trl1.int_level_n
8739`define PMU_TAKEN_30 `SPC3.tlu.trl1.take_pmu&`SPC3.tlu.trl1.trap[2]
8740
8741`define HINTP_RDWR_30 (`TOP.nas_top.c3.t6.asi_rdwr_hintp | `TOP.nas_top.c3.t6.asi_wr_hintp_delay)
8742`define HINTP_WR_30 (`SPC3.tlu.asi_wr_hintp[30])
8743`define HSTMATCH_30 `SPC3.tlu.trl1.hstick2_compare
8744
8745`define HINTP_REG_30 `SPC3.tlu.trl1.hintp2
8746`define HSTM_TAKEN_30 `SPC3.tlu.trl1.take_hst&`SPC3.tlu.trl1.trap[2]
8747
8748`define NAS_PIPE_FW2_30 |`TOP.nas_top.c3.t6.complete_fw2
8749
8750`define CWQ_TAKEN_30 `SPC3.tlu.trl1.take_cwq&`SPC3.tlu.trl1.trap[2]
8751`define SMA_TAKEN_30 `SPC3.tlu.trl1.take_sma&`SPC3.tlu.trl1.trap[2]
8752
8753`define POR_TAKEN_30 `SPC3.tlu.trl1.take_por&`SPC3.tlu.trl1.trap[2]
8754
8755/////////////////////////////// Probes //////////////////////////////////// }}}
8756
8757always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
8758
8759 // {{{ DETECT, PIPE & SEND
8760 take_disrupting_w <= (`INT_VEC_TAKEN_30 || `CPU_MONDO_TAKEN_30 ||
8761 `DEV_MONDO_TAKEN_30 || `RES_MONDO_TAKEN_30 ||
8762 `XIR_TAKEN_30 || `INT_LEVEL_TAKEN_30 ||
8763 `HSTM_TAKEN_30 || `CWQ_TAKEN_30 ||
8764 `SMA_TAKEN_30 || `PMU_TAKEN_30 || `POR_TAKEN_30);
8765 take_disrupting_fx4 <= take_disrupting_w;
8766 take_disrupting_fx5 <= take_disrupting_fx4;
8767 take_disrupting_fb <= take_disrupting_fx5;
8768 take_disrupting_fw <= take_disrupting_fb;
8769 take_disrupting_fw1 <= take_disrupting_fw;
8770 take_disrupting_fw2 <= take_disrupting_fw1;
8771
8772 case ({`INT_VEC_TAKEN_30, `CPU_MONDO_TAKEN_30,
8773 `DEV_MONDO_TAKEN_30, `RES_MONDO_TAKEN_30,
8774 `XIR_TAKEN_30, `INT_LEVEL_TAKEN_30,
8775 `HSTM_TAKEN_30, `CWQ_TAKEN_30, `SMA_TAKEN_30 ,
8776 `PMU_TAKEN_30, `POR_TAKEN_30})
8777 11'b10000000000: int_num_w <= 8'h60;
8778 11'b01000000000: int_num_w <= 8'h7c;
8779 11'b00100000000: int_num_w <= 8'h7d;
8780 11'b00010000000: int_num_w <= 8'h7e;
8781 11'b00001000000: int_num_w <= 8'h03;
8782 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_30;
8783 11'b00000010000: int_num_w <= 8'h5e;
8784 11'b00000001000: int_num_w <= 8'h3c;
8785 11'b00000000100: int_num_w <= 8'h3d;
8786 11'b00000000010: int_num_w <= 8'h4f;
8787 11'b00000000001: int_num_w <= 8'h01;
8788 endcase
8789
8790 int_num_fx4 <= int_num_w;
8791 int_num_fx5 <= int_num_fx4;
8792 int_num_fb <= int_num_fx5;
8793 int_num_fw <= int_num_fb;
8794 int_num_fw1 <= int_num_fw;
8795 int_num_fw2 <= int_num_fw1;
8796 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
8797 begin // {
8798 `PR_INFO ("pli_int", `INFO,
8799 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
8800 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
8801 end // }
8802
8803 // }}}
8804
8805/////////////////////////// Vectored Interrupt /////////////////////////// {{{
8806
8807 // Vectored Interrupt Recv Register Detection
8808 // Indicate when register changes due to arriving interrupt, and not
8809 // due to read of incoming register or ASI write ..
8810
8811
8812 // If any read occurs, send value right away.
8813 // While a read/write is pending, do not update delta.
8814 // Send non read/wr delta during fw2 ..
8815
8816
8817 if (!(`INT_VEC_RDWR_30 | `INT_VEC_RECV_ASIWR_30)) begin // {
8818 if (~`INT_VEC_RECV_ASIWR_30 &
8819 (int_vec_recv_reg !== `INT_VEC_RECV_REG_30 ))
8820 int_vec_recv_reg_delta <= 1'b1;
8821 int_vec_recv_reg <= `INT_VEC_RECV_REG_30;
8822 end // }
8823 else if (`INT_VEC_RECV_ASIWR_30)
8824 int_vec_recv_reg <= `TOP.nas_top.c3.t6.asi_updated_int_rec;
8825
8826 if ((`NAS_PIPE_FW2_30 & int_vec_recv_reg_delta ) |
8827 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
8828 `INT_VEC_RECV_ASIWR_30 ) begin // {
8829 `PR_INFO ("pli_int", `INFO,
8830 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
8831 mycid,mytid, int_vec_recv_reg);
8832 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8833 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
8834 64'h0, int_vec_recv_reg);
8835 end // }
8836 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_30 &
8837 (int_vec_recv_reg !== `INT_VEC_RECV_REG_30 ))))
8838 int_vec_recv_reg_delta <= 1'b0;
8839 end //}
8840
8841 int_vec_reg_rdwr <= `INT_VEC_RDWR_30 | `INT_VEC_RECV_ASIWR_30;
8842 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_30 & ~ inc_vec_reg_rd;
8843
8844 if (`INT_VEC_RECV_ASIWR_30)
8845 inc_vec_reg_rd <= 1'b1;
8846 if (`NAS_PIPE_FW2_30)
8847 inc_vec_reg_rd <= 1'b0;
8848
8849
8850/////////////////////////// Vectored Interrupt /////////////////////////// }}}
8851
8852/////////////////////////// Asynchronous Resets ////////////////////////// {{{
8853
8854
8855/////////////////////////// Asynchronous Resets ////////////////////////// }}}
8856
8857/////////////////////////// Softint ///////////////////////////////////// {{{
8858
8859 // Softint Register hardware Update Detection
8860
8861 // Non software updates (TM/SM)
8862
8863 // If any read occurs, send value right away.
8864 // While a read/write is pending, do not update delta.
8865 // Send non read/wr delta during fw2 ..
8866
8867 // RTL keeps pic_ovf indication in rd_softint and not softint.
8868 // So for set/clear writes, we send softint before the write ..,
8869 // and for read/asyncs we send rd_softint ..
8870
8871
8872 if (~`SOFTINT_RDWR_30) begin // {
8873 if (softint !== `RD_SOFTINT_REG_30 )
8874 softint_delta <= 1'b1;
8875 softint <= `RD_SOFTINT_REG_30;
8876 end // }
8877
8878 if ((`NAS_PIPE_FW2_30 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
8879 ) begin // {
8880 `PR_INFO ("pli_int", `INFO,
8881 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8882 mycid,mytid, {47'h0, softint});
8883 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8884 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8885 {47'h0, softint});
8886 end // }
8887 if (!(~`SOFTINT_RDWR_30&(softint !== `RD_SOFTINT_REG_30)))
8888 softint_delta <= 1'b0;
8889 end //}
8890 else if (`SPC3.tlu.asi_wr_clear_softint[6] |
8891 `SPC3.tlu.asi_wr_set_softint[6] ) begin // {
8892 `PR_INFO ("pli_int", `INFO,
8893 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
8894 mycid,mytid, {47'h0, `RD_SOFTINT_REG_30});
8895 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8896 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
8897 {47'h0, `RD_SOFTINT_REG_30});
8898 end // }
8899 end //}
8900
8901
8902 softint_rdwr <= `SOFTINT_RDWR_30 ;
8903 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_30;
8904
8905
8906/////////////////////////// Softint ///////////////////////////////////// }}}
8907
8908/////////////////////////// Hintp ///////////////////////////////////// {{{
8909
8910 // Hintp Register hardware Update Detection
8911
8912 // Non software updates (HSP)
8913 // If HINTP is already read/written by SW, then don't send
8914 // any async updates to Nas. Reads/Writes pending sstep is detected
8915 // by snooping nas_pipe ..
8916
8917 hintp <= `HINTP_REG_30 ;
8918 if (hstmatch_late)
8919 hintp_delta <= 1'b1;
8920
8921 if ((~hintp_rdwr & `NAS_PIPE_FW2_30 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
8922 (hintp_rdwr_late & hintp_delta) ) begin // {
8923 `PR_INFO ("pli_int", `INFO,
8924 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
8925 mycid,mytid, {63'h0, hintp});
8926 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
8927 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
8928 {63'h0, hintp});
8929 end // }
8930 if (~(hintp_rdwr_late & hintp_delta))
8931 hintp_delta <= 1'b0;
8932 end //}
8933
8934 hintp_rdwr <= `HINTP_RDWR_30;
8935 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_30;
8936 hstmatch_late <= `HSTMATCH_30;
8937
8938
8939/////////////////////////// Hintp ///////////////////////////////////// }}}
8940
8941end //}
8942`endif
8943endmodule
8944
8945// }}}
8946
8947module int_c3t7 ();
8948`ifndef GATESIM
8949
8950// common defines
8951`include "defines.vh"
8952`include "ccx.vri"
8953`include "cmp.vri"
8954
8955wire [2:0] mycid;
8956wire [2:0] mytid;
8957wire [5:0] mytnum;
8958integer junk;
8959
8960reg [63:0] int_vec_recv_reg;
8961reg int_vec_recv_reg_delta;
8962reg int_vec_reg_rdwr;
8963reg inc_vec_reg_rd;
8964reg int_vec_reg_rdwr_late;
8965reg [16:0] softint;
8966reg softint_rdwr;
8967reg softint_rdwr_late;
8968reg softint_delta;
8969reg hintp;
8970reg hintp_rdwr;
8971reg hintp_rdwr_late;
8972reg hintp_delta;
8973reg hstmatch_late;
8974reg ready;
8975reg [7:0] int_num_w;
8976reg [7:0] int_num_fx4;
8977reg [7:0] int_num_fx5;
8978reg [7:0] int_num_fb;
8979reg [7:0] int_num_fw;
8980reg [7:0] int_num_fw1;
8981reg [7:0] int_num_fw2;
8982reg take_disrupting_w;
8983reg take_disrupting_fx4;
8984reg take_disrupting_fx5;
8985reg take_disrupting_fb;
8986reg take_disrupting_fw;
8987reg take_disrupting_fw1;
8988reg take_disrupting_fw2;
8989
8990 assign mycid = 3;
8991 assign mytid = 7;
8992 assign mytnum = 3*8 + 7;
8993
8994initial begin // {
8995 ready = 0; // Wait for socket setup ..
8996 inc_vec_reg_rd <= 1'b0;
8997 int_vec_recv_reg_delta <= 1'b0;
8998 softint_delta <= 1'b0;
8999 hintp_delta <= 1'b0;
9000 int_vec_recv_reg = 64'b0;
9001 @(posedge `BENCH_SPC3_GCLK) ;
9002 @(posedge `BENCH_SPC3_GCLK) ;
9003 ready = `PARGS.int_sync_on;
9004end //}
9005
9006
9007/////////////////////////////// Probes //////////////////////////////////// {{{
9008
9009`define INT_VEC_RECV_REG_31 `SPC3.tlu.cth.int_rec7
9010`define INT_VEC_RECV_ASIWR_31 (`TOP.nas_top.c3.t7.asi_wr_int_rec_delay)
9011`define INT_VEC_RDWR_31 (`TOP.nas_top.c3.t7.asi_rdwr_int_rec)
9012`define INT_VEC_TAKEN_31 `SPC3.tlu.trl1.take_ivt&`SPC3.tlu.trl1.trap[3]
9013
9014`define CPU_MONDO_TAKEN_31 `SPC3.tlu.trl1.take_mqr&`SPC3.tlu.trl1.trap[3]
9015`define DEV_MONDO_TAKEN_31 `SPC3.tlu.trl1.take_dqr&`SPC3.tlu.trl1.trap[3]
9016`define RES_MONDO_TAKEN_31 `SPC3.tlu.trl1.take_rqr&`SPC3.tlu.trl1.trap[3]
9017
9018`define XIR_TAKEN_31 `SPC3.tlu.trl1.take_xir&`SPC3.tlu.trl1.trap[3]
9019
9020`define SOFTINT_RDWR_31 (`TOP.nas_top.c3.t7.asi_rdwr_softint|`TOP.nas_top.c3.t7.asi_wr_softint_delay)
9021
9022`define SOFTINT_REG_31 `SPC3.tlu.trl1.softint3
9023`define RD_SOFTINT_REG_31 `SPC3.tlu.trl1.rd_softint3
9024`define INT_LEVEL_TAKEN_31 `SPC3.tlu.trl1.take_iln&`SPC3.tlu.trl1.trap[3]
9025`define INT_LEVEL_NUM_31 `SPC3.tlu.trl1.int_level_n
9026`define PMU_TAKEN_31 `SPC3.tlu.trl1.take_pmu&`SPC3.tlu.trl1.trap[3]
9027
9028`define HINTP_RDWR_31 (`TOP.nas_top.c3.t7.asi_rdwr_hintp | `TOP.nas_top.c3.t7.asi_wr_hintp_delay)
9029`define HINTP_WR_31 (`SPC3.tlu.asi_wr_hintp[31])
9030`define HSTMATCH_31 `SPC3.tlu.trl1.hstick3_compare
9031
9032`define HINTP_REG_31 `SPC3.tlu.trl1.hintp3
9033`define HSTM_TAKEN_31 `SPC3.tlu.trl1.take_hst&`SPC3.tlu.trl1.trap[3]
9034
9035`define NAS_PIPE_FW2_31 |`TOP.nas_top.c3.t7.complete_fw2
9036
9037`define CWQ_TAKEN_31 `SPC3.tlu.trl1.take_cwq&`SPC3.tlu.trl1.trap[3]
9038`define SMA_TAKEN_31 `SPC3.tlu.trl1.take_sma&`SPC3.tlu.trl1.trap[3]
9039
9040`define POR_TAKEN_31 `SPC3.tlu.trl1.take_por&`SPC3.tlu.trl1.trap[3]
9041
9042/////////////////////////////// Probes //////////////////////////////////// }}}
9043
9044always @(negedge (`BENCH_SPC3_GCLK & ready)) begin // {
9045
9046 // {{{ DETECT, PIPE & SEND
9047 take_disrupting_w <= (`INT_VEC_TAKEN_31 || `CPU_MONDO_TAKEN_31 ||
9048 `DEV_MONDO_TAKEN_31 || `RES_MONDO_TAKEN_31 ||
9049 `XIR_TAKEN_31 || `INT_LEVEL_TAKEN_31 ||
9050 `HSTM_TAKEN_31 || `CWQ_TAKEN_31 ||
9051 `SMA_TAKEN_31 || `PMU_TAKEN_31 || `POR_TAKEN_31);
9052 take_disrupting_fx4 <= take_disrupting_w;
9053 take_disrupting_fx5 <= take_disrupting_fx4;
9054 take_disrupting_fb <= take_disrupting_fx5;
9055 take_disrupting_fw <= take_disrupting_fb;
9056 take_disrupting_fw1 <= take_disrupting_fw;
9057 take_disrupting_fw2 <= take_disrupting_fw1;
9058
9059 case ({`INT_VEC_TAKEN_31, `CPU_MONDO_TAKEN_31,
9060 `DEV_MONDO_TAKEN_31, `RES_MONDO_TAKEN_31,
9061 `XIR_TAKEN_31, `INT_LEVEL_TAKEN_31,
9062 `HSTM_TAKEN_31, `CWQ_TAKEN_31, `SMA_TAKEN_31 ,
9063 `PMU_TAKEN_31, `POR_TAKEN_31})
9064 11'b10000000000: int_num_w <= 8'h60;
9065 11'b01000000000: int_num_w <= 8'h7c;
9066 11'b00100000000: int_num_w <= 8'h7d;
9067 11'b00010000000: int_num_w <= 8'h7e;
9068 11'b00001000000: int_num_w <= 8'h03;
9069 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_31;
9070 11'b00000010000: int_num_w <= 8'h5e;
9071 11'b00000001000: int_num_w <= 8'h3c;
9072 11'b00000000100: int_num_w <= 8'h3d;
9073 11'b00000000010: int_num_w <= 8'h4f;
9074 11'b00000000001: int_num_w <= 8'h01;
9075 endcase
9076
9077 int_num_fx4 <= int_num_w;
9078 int_num_fx5 <= int_num_fx4;
9079 int_num_fb <= int_num_fx5;
9080 int_num_fw <= int_num_fb;
9081 int_num_fw1 <= int_num_fw;
9082 int_num_fw2 <= int_num_fw1;
9083 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
9084 begin // {
9085 `PR_INFO ("pli_int", `INFO,
9086 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
9087 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9088 end // }
9089
9090 // }}}
9091
9092/////////////////////////// Vectored Interrupt /////////////////////////// {{{
9093
9094 // Vectored Interrupt Recv Register Detection
9095 // Indicate when register changes due to arriving interrupt, and not
9096 // due to read of incoming register or ASI write ..
9097
9098
9099 // If any read occurs, send value right away.
9100 // While a read/write is pending, do not update delta.
9101 // Send non read/wr delta during fw2 ..
9102
9103
9104 if (!(`INT_VEC_RDWR_31 | `INT_VEC_RECV_ASIWR_31)) begin // {
9105 if (~`INT_VEC_RECV_ASIWR_31 &
9106 (int_vec_recv_reg !== `INT_VEC_RECV_REG_31 ))
9107 int_vec_recv_reg_delta <= 1'b1;
9108 int_vec_recv_reg <= `INT_VEC_RECV_REG_31;
9109 end // }
9110 else if (`INT_VEC_RECV_ASIWR_31)
9111 int_vec_recv_reg <= `TOP.nas_top.c3.t7.asi_updated_int_rec;
9112
9113 if ((`NAS_PIPE_FW2_31 & int_vec_recv_reg_delta ) |
9114 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
9115 `INT_VEC_RECV_ASIWR_31 ) begin // {
9116 `PR_INFO ("pli_int", `INFO,
9117 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
9118 mycid,mytid, int_vec_recv_reg);
9119 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9120 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
9121 64'h0, int_vec_recv_reg);
9122 end // }
9123 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_31 &
9124 (int_vec_recv_reg !== `INT_VEC_RECV_REG_31 ))))
9125 int_vec_recv_reg_delta <= 1'b0;
9126 end //}
9127
9128 int_vec_reg_rdwr <= `INT_VEC_RDWR_31 | `INT_VEC_RECV_ASIWR_31;
9129 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_31 & ~ inc_vec_reg_rd;
9130
9131 if (`INT_VEC_RECV_ASIWR_31)
9132 inc_vec_reg_rd <= 1'b1;
9133 if (`NAS_PIPE_FW2_31)
9134 inc_vec_reg_rd <= 1'b0;
9135
9136
9137/////////////////////////// Vectored Interrupt /////////////////////////// }}}
9138
9139/////////////////////////// Asynchronous Resets ////////////////////////// {{{
9140
9141
9142/////////////////////////// Asynchronous Resets ////////////////////////// }}}
9143
9144/////////////////////////// Softint ///////////////////////////////////// {{{
9145
9146 // Softint Register hardware Update Detection
9147
9148 // Non software updates (TM/SM)
9149
9150 // If any read occurs, send value right away.
9151 // While a read/write is pending, do not update delta.
9152 // Send non read/wr delta during fw2 ..
9153
9154 // RTL keeps pic_ovf indication in rd_softint and not softint.
9155 // So for set/clear writes, we send softint before the write ..,
9156 // and for read/asyncs we send rd_softint ..
9157
9158
9159 if (~`SOFTINT_RDWR_31) begin // {
9160 if (softint !== `RD_SOFTINT_REG_31 )
9161 softint_delta <= 1'b1;
9162 softint <= `RD_SOFTINT_REG_31;
9163 end // }
9164
9165 if ((`NAS_PIPE_FW2_31 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
9166 ) begin // {
9167 `PR_INFO ("pli_int", `INFO,
9168 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
9169 mycid,mytid, {47'h0, softint});
9170 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9171 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
9172 {47'h0, softint});
9173 end // }
9174 if (!(~`SOFTINT_RDWR_31&(softint !== `RD_SOFTINT_REG_31)))
9175 softint_delta <= 1'b0;
9176 end //}
9177 else if (`SPC3.tlu.asi_wr_clear_softint[7] |
9178 `SPC3.tlu.asi_wr_set_softint[7] ) begin // {
9179 `PR_INFO ("pli_int", `INFO,
9180 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
9181 mycid,mytid, {47'h0, `RD_SOFTINT_REG_31});
9182 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9183 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
9184 {47'h0, `RD_SOFTINT_REG_31});
9185 end // }
9186 end //}
9187
9188
9189 softint_rdwr <= `SOFTINT_RDWR_31 ;
9190 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_31;
9191
9192
9193/////////////////////////// Softint ///////////////////////////////////// }}}
9194
9195/////////////////////////// Hintp ///////////////////////////////////// {{{
9196
9197 // Hintp Register hardware Update Detection
9198
9199 // Non software updates (HSP)
9200 // If HINTP is already read/written by SW, then don't send
9201 // any async updates to Nas. Reads/Writes pending sstep is detected
9202 // by snooping nas_pipe ..
9203
9204 hintp <= `HINTP_REG_31 ;
9205 if (hstmatch_late)
9206 hintp_delta <= 1'b1;
9207
9208 if ((~hintp_rdwr & `NAS_PIPE_FW2_31 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
9209 (hintp_rdwr_late & hintp_delta) ) begin // {
9210 `PR_INFO ("pli_int", `INFO,
9211 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
9212 mycid,mytid, {63'h0, hintp});
9213 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9214 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
9215 {63'h0, hintp});
9216 end // }
9217 if (~(hintp_rdwr_late & hintp_delta))
9218 hintp_delta <= 1'b0;
9219 end //}
9220
9221 hintp_rdwr <= `HINTP_RDWR_31;
9222 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_31;
9223 hstmatch_late <= `HSTMATCH_31;
9224
9225
9226/////////////////////////// Hintp ///////////////////////////////////// }}}
9227
9228end //}
9229`endif
9230endmodule
9231
9232`endif
9233`ifdef CORE_4
9234
9235// }}}
9236
9237module int_c4t0 ();
9238`ifndef GATESIM
9239
9240// common defines
9241`include "defines.vh"
9242`include "ccx.vri"
9243`include "cmp.vri"
9244
9245wire [2:0] mycid;
9246wire [2:0] mytid;
9247wire [5:0] mytnum;
9248integer junk;
9249
9250reg [63:0] int_vec_recv_reg;
9251reg int_vec_recv_reg_delta;
9252reg int_vec_reg_rdwr;
9253reg inc_vec_reg_rd;
9254reg int_vec_reg_rdwr_late;
9255reg [16:0] softint;
9256reg softint_rdwr;
9257reg softint_rdwr_late;
9258reg softint_delta;
9259reg hintp;
9260reg hintp_rdwr;
9261reg hintp_rdwr_late;
9262reg hintp_delta;
9263reg hstmatch_late;
9264reg ready;
9265reg [7:0] int_num_w;
9266reg [7:0] int_num_fx4;
9267reg [7:0] int_num_fx5;
9268reg [7:0] int_num_fb;
9269reg [7:0] int_num_fw;
9270reg [7:0] int_num_fw1;
9271reg [7:0] int_num_fw2;
9272reg take_disrupting_w;
9273reg take_disrupting_fx4;
9274reg take_disrupting_fx5;
9275reg take_disrupting_fb;
9276reg take_disrupting_fw;
9277reg take_disrupting_fw1;
9278reg take_disrupting_fw2;
9279
9280 assign mycid = 4;
9281 assign mytid = 0;
9282 assign mytnum = 4*8 + 0;
9283
9284initial begin // {
9285 ready = 0; // Wait for socket setup ..
9286 inc_vec_reg_rd <= 1'b0;
9287 int_vec_recv_reg_delta <= 1'b0;
9288 softint_delta <= 1'b0;
9289 hintp_delta <= 1'b0;
9290 int_vec_recv_reg = 64'b0;
9291 @(posedge `BENCH_SPC4_GCLK) ;
9292 @(posedge `BENCH_SPC4_GCLK) ;
9293 ready = `PARGS.int_sync_on;
9294end //}
9295
9296
9297/////////////////////////////// Probes //////////////////////////////////// {{{
9298
9299`define INT_VEC_RECV_REG_32 `SPC4.tlu.cth.int_rec0
9300`define INT_VEC_RECV_ASIWR_32 (`TOP.nas_top.c4.t0.asi_wr_int_rec_delay)
9301`define INT_VEC_RDWR_32 (`TOP.nas_top.c4.t0.asi_rdwr_int_rec)
9302`define INT_VEC_TAKEN_32 `SPC4.tlu.trl0.take_ivt&`SPC4.tlu.trl0.trap[0]
9303
9304`define CPU_MONDO_TAKEN_32 `SPC4.tlu.trl0.take_mqr&`SPC4.tlu.trl0.trap[0]
9305`define DEV_MONDO_TAKEN_32 `SPC4.tlu.trl0.take_dqr&`SPC4.tlu.trl0.trap[0]
9306`define RES_MONDO_TAKEN_32 `SPC4.tlu.trl0.take_rqr&`SPC4.tlu.trl0.trap[0]
9307
9308`define XIR_TAKEN_32 `SPC4.tlu.trl0.take_xir&`SPC4.tlu.trl0.trap[0]
9309
9310`define SOFTINT_RDWR_32 (`TOP.nas_top.c4.t0.asi_rdwr_softint|`TOP.nas_top.c4.t0.asi_wr_softint_delay)
9311
9312`define SOFTINT_REG_32 `SPC4.tlu.trl0.softint0
9313`define RD_SOFTINT_REG_32 `SPC4.tlu.trl0.rd_softint0
9314`define INT_LEVEL_TAKEN_32 `SPC4.tlu.trl0.take_iln&`SPC4.tlu.trl0.trap[0]
9315`define INT_LEVEL_NUM_32 `SPC4.tlu.trl0.int_level_n
9316`define PMU_TAKEN_32 `SPC4.tlu.trl0.take_pmu&`SPC4.tlu.trl0.trap[0]
9317
9318`define HINTP_RDWR_32 (`TOP.nas_top.c4.t0.asi_rdwr_hintp | `TOP.nas_top.c4.t0.asi_wr_hintp_delay)
9319`define HINTP_WR_32 (`SPC4.tlu.asi_wr_hintp[32])
9320`define HSTMATCH_32 `SPC4.tlu.trl0.hstick0_compare
9321
9322`define HINTP_REG_32 `SPC4.tlu.trl0.hintp0
9323`define HSTM_TAKEN_32 `SPC4.tlu.trl0.take_hst&`SPC4.tlu.trl0.trap[0]
9324
9325`define NAS_PIPE_FW2_32 |`TOP.nas_top.c4.t0.complete_fw2
9326
9327`define CWQ_TAKEN_32 `SPC4.tlu.trl0.take_cwq&`SPC4.tlu.trl0.trap[0]
9328`define SMA_TAKEN_32 `SPC4.tlu.trl0.take_sma&`SPC4.tlu.trl0.trap[0]
9329
9330`define POR_TAKEN_32 `SPC4.tlu.trl0.take_por&`SPC4.tlu.trl0.trap[0]
9331
9332/////////////////////////////// Probes //////////////////////////////////// }}}
9333
9334always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
9335
9336 // {{{ DETECT, PIPE & SEND
9337 take_disrupting_w <= (`INT_VEC_TAKEN_32 || `CPU_MONDO_TAKEN_32 ||
9338 `DEV_MONDO_TAKEN_32 || `RES_MONDO_TAKEN_32 ||
9339 `XIR_TAKEN_32 || `INT_LEVEL_TAKEN_32 ||
9340 `HSTM_TAKEN_32 || `CWQ_TAKEN_32 ||
9341 `SMA_TAKEN_32 || `PMU_TAKEN_32 || `POR_TAKEN_32);
9342 take_disrupting_fx4 <= take_disrupting_w;
9343 take_disrupting_fx5 <= take_disrupting_fx4;
9344 take_disrupting_fb <= take_disrupting_fx5;
9345 take_disrupting_fw <= take_disrupting_fb;
9346 take_disrupting_fw1 <= take_disrupting_fw;
9347 take_disrupting_fw2 <= take_disrupting_fw1;
9348
9349 case ({`INT_VEC_TAKEN_32, `CPU_MONDO_TAKEN_32,
9350 `DEV_MONDO_TAKEN_32, `RES_MONDO_TAKEN_32,
9351 `XIR_TAKEN_32, `INT_LEVEL_TAKEN_32,
9352 `HSTM_TAKEN_32, `CWQ_TAKEN_32, `SMA_TAKEN_32 ,
9353 `PMU_TAKEN_32, `POR_TAKEN_32})
9354 11'b10000000000: int_num_w <= 8'h60;
9355 11'b01000000000: int_num_w <= 8'h7c;
9356 11'b00100000000: int_num_w <= 8'h7d;
9357 11'b00010000000: int_num_w <= 8'h7e;
9358 11'b00001000000: int_num_w <= 8'h03;
9359 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_32;
9360 11'b00000010000: int_num_w <= 8'h5e;
9361 11'b00000001000: int_num_w <= 8'h3c;
9362 11'b00000000100: int_num_w <= 8'h3d;
9363 11'b00000000010: int_num_w <= 8'h4f;
9364 11'b00000000001: int_num_w <= 8'h01;
9365 endcase
9366
9367 int_num_fx4 <= int_num_w;
9368 int_num_fx5 <= int_num_fx4;
9369 int_num_fb <= int_num_fx5;
9370 int_num_fw <= int_num_fb;
9371 int_num_fw1 <= int_num_fw;
9372 int_num_fw2 <= int_num_fw1;
9373 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
9374 begin // {
9375 `PR_INFO ("pli_int", `INFO,
9376 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
9377 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9378 end // }
9379
9380 // }}}
9381
9382/////////////////////////// Vectored Interrupt /////////////////////////// {{{
9383
9384 // Vectored Interrupt Recv Register Detection
9385 // Indicate when register changes due to arriving interrupt, and not
9386 // due to read of incoming register or ASI write ..
9387
9388
9389 // If any read occurs, send value right away.
9390 // While a read/write is pending, do not update delta.
9391 // Send non read/wr delta during fw2 ..
9392
9393
9394 if (!(`INT_VEC_RDWR_32 | `INT_VEC_RECV_ASIWR_32)) begin // {
9395 if (~`INT_VEC_RECV_ASIWR_32 &
9396 (int_vec_recv_reg !== `INT_VEC_RECV_REG_32 ))
9397 int_vec_recv_reg_delta <= 1'b1;
9398 int_vec_recv_reg <= `INT_VEC_RECV_REG_32;
9399 end // }
9400 else if (`INT_VEC_RECV_ASIWR_32)
9401 int_vec_recv_reg <= `TOP.nas_top.c4.t0.asi_updated_int_rec;
9402
9403 if ((`NAS_PIPE_FW2_32 & int_vec_recv_reg_delta ) |
9404 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
9405 `INT_VEC_RECV_ASIWR_32 ) begin // {
9406 `PR_INFO ("pli_int", `INFO,
9407 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
9408 mycid,mytid, int_vec_recv_reg);
9409 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9410 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
9411 64'h0, int_vec_recv_reg);
9412 end // }
9413 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_32 &
9414 (int_vec_recv_reg !== `INT_VEC_RECV_REG_32 ))))
9415 int_vec_recv_reg_delta <= 1'b0;
9416 end //}
9417
9418 int_vec_reg_rdwr <= `INT_VEC_RDWR_32 | `INT_VEC_RECV_ASIWR_32;
9419 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_32 & ~ inc_vec_reg_rd;
9420
9421 if (`INT_VEC_RECV_ASIWR_32)
9422 inc_vec_reg_rd <= 1'b1;
9423 if (`NAS_PIPE_FW2_32)
9424 inc_vec_reg_rd <= 1'b0;
9425
9426
9427/////////////////////////// Vectored Interrupt /////////////////////////// }}}
9428
9429/////////////////////////// Asynchronous Resets ////////////////////////// {{{
9430
9431
9432/////////////////////////// Asynchronous Resets ////////////////////////// }}}
9433
9434/////////////////////////// Softint ///////////////////////////////////// {{{
9435
9436 // Softint Register hardware Update Detection
9437
9438 // Non software updates (TM/SM)
9439
9440 // If any read occurs, send value right away.
9441 // While a read/write is pending, do not update delta.
9442 // Send non read/wr delta during fw2 ..
9443
9444 // RTL keeps pic_ovf indication in rd_softint and not softint.
9445 // So for set/clear writes, we send softint before the write ..,
9446 // and for read/asyncs we send rd_softint ..
9447
9448
9449 if (~`SOFTINT_RDWR_32) begin // {
9450 if (softint !== `RD_SOFTINT_REG_32 )
9451 softint_delta <= 1'b1;
9452 softint <= `RD_SOFTINT_REG_32;
9453 end // }
9454
9455 if ((`NAS_PIPE_FW2_32 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
9456 ) begin // {
9457 `PR_INFO ("pli_int", `INFO,
9458 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
9459 mycid,mytid, {47'h0, softint});
9460 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9461 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
9462 {47'h0, softint});
9463 end // }
9464 if (!(~`SOFTINT_RDWR_32&(softint !== `RD_SOFTINT_REG_32)))
9465 softint_delta <= 1'b0;
9466 end //}
9467 else if (`SPC4.tlu.asi_wr_clear_softint[0] |
9468 `SPC4.tlu.asi_wr_set_softint[0] ) begin // {
9469 `PR_INFO ("pli_int", `INFO,
9470 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
9471 mycid,mytid, {47'h0, `RD_SOFTINT_REG_32});
9472 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9473 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
9474 {47'h0, `RD_SOFTINT_REG_32});
9475 end // }
9476 end //}
9477
9478
9479 softint_rdwr <= `SOFTINT_RDWR_32 ;
9480 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_32;
9481
9482
9483/////////////////////////// Softint ///////////////////////////////////// }}}
9484
9485/////////////////////////// Hintp ///////////////////////////////////// {{{
9486
9487 // Hintp Register hardware Update Detection
9488
9489 // Non software updates (HSP)
9490 // If HINTP is already read/written by SW, then don't send
9491 // any async updates to Nas. Reads/Writes pending sstep is detected
9492 // by snooping nas_pipe ..
9493
9494 hintp <= `HINTP_REG_32 ;
9495 if (hstmatch_late)
9496 hintp_delta <= 1'b1;
9497
9498 if ((~hintp_rdwr & `NAS_PIPE_FW2_32 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
9499 (hintp_rdwr_late & hintp_delta) ) begin // {
9500 `PR_INFO ("pli_int", `INFO,
9501 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
9502 mycid,mytid, {63'h0, hintp});
9503 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9504 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
9505 {63'h0, hintp});
9506 end // }
9507 if (~(hintp_rdwr_late & hintp_delta))
9508 hintp_delta <= 1'b0;
9509 end //}
9510
9511 hintp_rdwr <= `HINTP_RDWR_32;
9512 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_32;
9513 hstmatch_late <= `HSTMATCH_32;
9514
9515
9516/////////////////////////// Hintp ///////////////////////////////////// }}}
9517
9518end //}
9519`endif
9520endmodule
9521
9522// }}}
9523
9524module int_c4t1 ();
9525`ifndef GATESIM
9526
9527// common defines
9528`include "defines.vh"
9529`include "ccx.vri"
9530`include "cmp.vri"
9531
9532wire [2:0] mycid;
9533wire [2:0] mytid;
9534wire [5:0] mytnum;
9535integer junk;
9536
9537reg [63:0] int_vec_recv_reg;
9538reg int_vec_recv_reg_delta;
9539reg int_vec_reg_rdwr;
9540reg inc_vec_reg_rd;
9541reg int_vec_reg_rdwr_late;
9542reg [16:0] softint;
9543reg softint_rdwr;
9544reg softint_rdwr_late;
9545reg softint_delta;
9546reg hintp;
9547reg hintp_rdwr;
9548reg hintp_rdwr_late;
9549reg hintp_delta;
9550reg hstmatch_late;
9551reg ready;
9552reg [7:0] int_num_w;
9553reg [7:0] int_num_fx4;
9554reg [7:0] int_num_fx5;
9555reg [7:0] int_num_fb;
9556reg [7:0] int_num_fw;
9557reg [7:0] int_num_fw1;
9558reg [7:0] int_num_fw2;
9559reg take_disrupting_w;
9560reg take_disrupting_fx4;
9561reg take_disrupting_fx5;
9562reg take_disrupting_fb;
9563reg take_disrupting_fw;
9564reg take_disrupting_fw1;
9565reg take_disrupting_fw2;
9566
9567 assign mycid = 4;
9568 assign mytid = 1;
9569 assign mytnum = 4*8 + 1;
9570
9571initial begin // {
9572 ready = 0; // Wait for socket setup ..
9573 inc_vec_reg_rd <= 1'b0;
9574 int_vec_recv_reg_delta <= 1'b0;
9575 softint_delta <= 1'b0;
9576 hintp_delta <= 1'b0;
9577 int_vec_recv_reg = 64'b0;
9578 @(posedge `BENCH_SPC4_GCLK) ;
9579 @(posedge `BENCH_SPC4_GCLK) ;
9580 ready = `PARGS.int_sync_on;
9581end //}
9582
9583
9584/////////////////////////////// Probes //////////////////////////////////// {{{
9585
9586`define INT_VEC_RECV_REG_33 `SPC4.tlu.cth.int_rec1
9587`define INT_VEC_RECV_ASIWR_33 (`TOP.nas_top.c4.t1.asi_wr_int_rec_delay)
9588`define INT_VEC_RDWR_33 (`TOP.nas_top.c4.t1.asi_rdwr_int_rec)
9589`define INT_VEC_TAKEN_33 `SPC4.tlu.trl0.take_ivt&`SPC4.tlu.trl0.trap[1]
9590
9591`define CPU_MONDO_TAKEN_33 `SPC4.tlu.trl0.take_mqr&`SPC4.tlu.trl0.trap[1]
9592`define DEV_MONDO_TAKEN_33 `SPC4.tlu.trl0.take_dqr&`SPC4.tlu.trl0.trap[1]
9593`define RES_MONDO_TAKEN_33 `SPC4.tlu.trl0.take_rqr&`SPC4.tlu.trl0.trap[1]
9594
9595`define XIR_TAKEN_33 `SPC4.tlu.trl0.take_xir&`SPC4.tlu.trl0.trap[1]
9596
9597`define SOFTINT_RDWR_33 (`TOP.nas_top.c4.t1.asi_rdwr_softint|`TOP.nas_top.c4.t1.asi_wr_softint_delay)
9598
9599`define SOFTINT_REG_33 `SPC4.tlu.trl0.softint1
9600`define RD_SOFTINT_REG_33 `SPC4.tlu.trl0.rd_softint1
9601`define INT_LEVEL_TAKEN_33 `SPC4.tlu.trl0.take_iln&`SPC4.tlu.trl0.trap[1]
9602`define INT_LEVEL_NUM_33 `SPC4.tlu.trl0.int_level_n
9603`define PMU_TAKEN_33 `SPC4.tlu.trl0.take_pmu&`SPC4.tlu.trl0.trap[1]
9604
9605`define HINTP_RDWR_33 (`TOP.nas_top.c4.t1.asi_rdwr_hintp | `TOP.nas_top.c4.t1.asi_wr_hintp_delay)
9606`define HINTP_WR_33 (`SPC4.tlu.asi_wr_hintp[33])
9607`define HSTMATCH_33 `SPC4.tlu.trl0.hstick1_compare
9608
9609`define HINTP_REG_33 `SPC4.tlu.trl0.hintp1
9610`define HSTM_TAKEN_33 `SPC4.tlu.trl0.take_hst&`SPC4.tlu.trl0.trap[1]
9611
9612`define NAS_PIPE_FW2_33 |`TOP.nas_top.c4.t1.complete_fw2
9613
9614`define CWQ_TAKEN_33 `SPC4.tlu.trl0.take_cwq&`SPC4.tlu.trl0.trap[1]
9615`define SMA_TAKEN_33 `SPC4.tlu.trl0.take_sma&`SPC4.tlu.trl0.trap[1]
9616
9617`define POR_TAKEN_33 `SPC4.tlu.trl0.take_por&`SPC4.tlu.trl0.trap[1]
9618
9619/////////////////////////////// Probes //////////////////////////////////// }}}
9620
9621always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
9622
9623 // {{{ DETECT, PIPE & SEND
9624 take_disrupting_w <= (`INT_VEC_TAKEN_33 || `CPU_MONDO_TAKEN_33 ||
9625 `DEV_MONDO_TAKEN_33 || `RES_MONDO_TAKEN_33 ||
9626 `XIR_TAKEN_33 || `INT_LEVEL_TAKEN_33 ||
9627 `HSTM_TAKEN_33 || `CWQ_TAKEN_33 ||
9628 `SMA_TAKEN_33 || `PMU_TAKEN_33 || `POR_TAKEN_33);
9629 take_disrupting_fx4 <= take_disrupting_w;
9630 take_disrupting_fx5 <= take_disrupting_fx4;
9631 take_disrupting_fb <= take_disrupting_fx5;
9632 take_disrupting_fw <= take_disrupting_fb;
9633 take_disrupting_fw1 <= take_disrupting_fw;
9634 take_disrupting_fw2 <= take_disrupting_fw1;
9635
9636 case ({`INT_VEC_TAKEN_33, `CPU_MONDO_TAKEN_33,
9637 `DEV_MONDO_TAKEN_33, `RES_MONDO_TAKEN_33,
9638 `XIR_TAKEN_33, `INT_LEVEL_TAKEN_33,
9639 `HSTM_TAKEN_33, `CWQ_TAKEN_33, `SMA_TAKEN_33 ,
9640 `PMU_TAKEN_33, `POR_TAKEN_33})
9641 11'b10000000000: int_num_w <= 8'h60;
9642 11'b01000000000: int_num_w <= 8'h7c;
9643 11'b00100000000: int_num_w <= 8'h7d;
9644 11'b00010000000: int_num_w <= 8'h7e;
9645 11'b00001000000: int_num_w <= 8'h03;
9646 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_33;
9647 11'b00000010000: int_num_w <= 8'h5e;
9648 11'b00000001000: int_num_w <= 8'h3c;
9649 11'b00000000100: int_num_w <= 8'h3d;
9650 11'b00000000010: int_num_w <= 8'h4f;
9651 11'b00000000001: int_num_w <= 8'h01;
9652 endcase
9653
9654 int_num_fx4 <= int_num_w;
9655 int_num_fx5 <= int_num_fx4;
9656 int_num_fb <= int_num_fx5;
9657 int_num_fw <= int_num_fb;
9658 int_num_fw1 <= int_num_fw;
9659 int_num_fw2 <= int_num_fw1;
9660 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
9661 begin // {
9662 `PR_INFO ("pli_int", `INFO,
9663 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
9664 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9665 end // }
9666
9667 // }}}
9668
9669/////////////////////////// Vectored Interrupt /////////////////////////// {{{
9670
9671 // Vectored Interrupt Recv Register Detection
9672 // Indicate when register changes due to arriving interrupt, and not
9673 // due to read of incoming register or ASI write ..
9674
9675
9676 // If any read occurs, send value right away.
9677 // While a read/write is pending, do not update delta.
9678 // Send non read/wr delta during fw2 ..
9679
9680
9681 if (!(`INT_VEC_RDWR_33 | `INT_VEC_RECV_ASIWR_33)) begin // {
9682 if (~`INT_VEC_RECV_ASIWR_33 &
9683 (int_vec_recv_reg !== `INT_VEC_RECV_REG_33 ))
9684 int_vec_recv_reg_delta <= 1'b1;
9685 int_vec_recv_reg <= `INT_VEC_RECV_REG_33;
9686 end // }
9687 else if (`INT_VEC_RECV_ASIWR_33)
9688 int_vec_recv_reg <= `TOP.nas_top.c4.t1.asi_updated_int_rec;
9689
9690 if ((`NAS_PIPE_FW2_33 & int_vec_recv_reg_delta ) |
9691 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
9692 `INT_VEC_RECV_ASIWR_33 ) begin // {
9693 `PR_INFO ("pli_int", `INFO,
9694 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
9695 mycid,mytid, int_vec_recv_reg);
9696 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9697 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
9698 64'h0, int_vec_recv_reg);
9699 end // }
9700 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_33 &
9701 (int_vec_recv_reg !== `INT_VEC_RECV_REG_33 ))))
9702 int_vec_recv_reg_delta <= 1'b0;
9703 end //}
9704
9705 int_vec_reg_rdwr <= `INT_VEC_RDWR_33 | `INT_VEC_RECV_ASIWR_33;
9706 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_33 & ~ inc_vec_reg_rd;
9707
9708 if (`INT_VEC_RECV_ASIWR_33)
9709 inc_vec_reg_rd <= 1'b1;
9710 if (`NAS_PIPE_FW2_33)
9711 inc_vec_reg_rd <= 1'b0;
9712
9713
9714/////////////////////////// Vectored Interrupt /////////////////////////// }}}
9715
9716/////////////////////////// Asynchronous Resets ////////////////////////// {{{
9717
9718
9719/////////////////////////// Asynchronous Resets ////////////////////////// }}}
9720
9721/////////////////////////// Softint ///////////////////////////////////// {{{
9722
9723 // Softint Register hardware Update Detection
9724
9725 // Non software updates (TM/SM)
9726
9727 // If any read occurs, send value right away.
9728 // While a read/write is pending, do not update delta.
9729 // Send non read/wr delta during fw2 ..
9730
9731 // RTL keeps pic_ovf indication in rd_softint and not softint.
9732 // So for set/clear writes, we send softint before the write ..,
9733 // and for read/asyncs we send rd_softint ..
9734
9735
9736 if (~`SOFTINT_RDWR_33) begin // {
9737 if (softint !== `RD_SOFTINT_REG_33 )
9738 softint_delta <= 1'b1;
9739 softint <= `RD_SOFTINT_REG_33;
9740 end // }
9741
9742 if ((`NAS_PIPE_FW2_33 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
9743 ) begin // {
9744 `PR_INFO ("pli_int", `INFO,
9745 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
9746 mycid,mytid, {47'h0, softint});
9747 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9748 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
9749 {47'h0, softint});
9750 end // }
9751 if (!(~`SOFTINT_RDWR_33&(softint !== `RD_SOFTINT_REG_33)))
9752 softint_delta <= 1'b0;
9753 end //}
9754 else if (`SPC4.tlu.asi_wr_clear_softint[1] |
9755 `SPC4.tlu.asi_wr_set_softint[1] ) begin // {
9756 `PR_INFO ("pli_int", `INFO,
9757 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
9758 mycid,mytid, {47'h0, `RD_SOFTINT_REG_33});
9759 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9760 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
9761 {47'h0, `RD_SOFTINT_REG_33});
9762 end // }
9763 end //}
9764
9765
9766 softint_rdwr <= `SOFTINT_RDWR_33 ;
9767 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_33;
9768
9769
9770/////////////////////////// Softint ///////////////////////////////////// }}}
9771
9772/////////////////////////// Hintp ///////////////////////////////////// {{{
9773
9774 // Hintp Register hardware Update Detection
9775
9776 // Non software updates (HSP)
9777 // If HINTP is already read/written by SW, then don't send
9778 // any async updates to Nas. Reads/Writes pending sstep is detected
9779 // by snooping nas_pipe ..
9780
9781 hintp <= `HINTP_REG_33 ;
9782 if (hstmatch_late)
9783 hintp_delta <= 1'b1;
9784
9785 if ((~hintp_rdwr & `NAS_PIPE_FW2_33 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
9786 (hintp_rdwr_late & hintp_delta) ) begin // {
9787 `PR_INFO ("pli_int", `INFO,
9788 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
9789 mycid,mytid, {63'h0, hintp});
9790 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9791 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
9792 {63'h0, hintp});
9793 end // }
9794 if (~(hintp_rdwr_late & hintp_delta))
9795 hintp_delta <= 1'b0;
9796 end //}
9797
9798 hintp_rdwr <= `HINTP_RDWR_33;
9799 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_33;
9800 hstmatch_late <= `HSTMATCH_33;
9801
9802
9803/////////////////////////// Hintp ///////////////////////////////////// }}}
9804
9805end //}
9806`endif
9807endmodule
9808
9809// }}}
9810
9811module int_c4t2 ();
9812`ifndef GATESIM
9813
9814// common defines
9815`include "defines.vh"
9816`include "ccx.vri"
9817`include "cmp.vri"
9818
9819wire [2:0] mycid;
9820wire [2:0] mytid;
9821wire [5:0] mytnum;
9822integer junk;
9823
9824reg [63:0] int_vec_recv_reg;
9825reg int_vec_recv_reg_delta;
9826reg int_vec_reg_rdwr;
9827reg inc_vec_reg_rd;
9828reg int_vec_reg_rdwr_late;
9829reg [16:0] softint;
9830reg softint_rdwr;
9831reg softint_rdwr_late;
9832reg softint_delta;
9833reg hintp;
9834reg hintp_rdwr;
9835reg hintp_rdwr_late;
9836reg hintp_delta;
9837reg hstmatch_late;
9838reg ready;
9839reg [7:0] int_num_w;
9840reg [7:0] int_num_fx4;
9841reg [7:0] int_num_fx5;
9842reg [7:0] int_num_fb;
9843reg [7:0] int_num_fw;
9844reg [7:0] int_num_fw1;
9845reg [7:0] int_num_fw2;
9846reg take_disrupting_w;
9847reg take_disrupting_fx4;
9848reg take_disrupting_fx5;
9849reg take_disrupting_fb;
9850reg take_disrupting_fw;
9851reg take_disrupting_fw1;
9852reg take_disrupting_fw2;
9853
9854 assign mycid = 4;
9855 assign mytid = 2;
9856 assign mytnum = 4*8 + 2;
9857
9858initial begin // {
9859 ready = 0; // Wait for socket setup ..
9860 inc_vec_reg_rd <= 1'b0;
9861 int_vec_recv_reg_delta <= 1'b0;
9862 softint_delta <= 1'b0;
9863 hintp_delta <= 1'b0;
9864 int_vec_recv_reg = 64'b0;
9865 @(posedge `BENCH_SPC4_GCLK) ;
9866 @(posedge `BENCH_SPC4_GCLK) ;
9867 ready = `PARGS.int_sync_on;
9868end //}
9869
9870
9871/////////////////////////////// Probes //////////////////////////////////// {{{
9872
9873`define INT_VEC_RECV_REG_34 `SPC4.tlu.cth.int_rec2
9874`define INT_VEC_RECV_ASIWR_34 (`TOP.nas_top.c4.t2.asi_wr_int_rec_delay)
9875`define INT_VEC_RDWR_34 (`TOP.nas_top.c4.t2.asi_rdwr_int_rec)
9876`define INT_VEC_TAKEN_34 `SPC4.tlu.trl0.take_ivt&`SPC4.tlu.trl0.trap[2]
9877
9878`define CPU_MONDO_TAKEN_34 `SPC4.tlu.trl0.take_mqr&`SPC4.tlu.trl0.trap[2]
9879`define DEV_MONDO_TAKEN_34 `SPC4.tlu.trl0.take_dqr&`SPC4.tlu.trl0.trap[2]
9880`define RES_MONDO_TAKEN_34 `SPC4.tlu.trl0.take_rqr&`SPC4.tlu.trl0.trap[2]
9881
9882`define XIR_TAKEN_34 `SPC4.tlu.trl0.take_xir&`SPC4.tlu.trl0.trap[2]
9883
9884`define SOFTINT_RDWR_34 (`TOP.nas_top.c4.t2.asi_rdwr_softint|`TOP.nas_top.c4.t2.asi_wr_softint_delay)
9885
9886`define SOFTINT_REG_34 `SPC4.tlu.trl0.softint2
9887`define RD_SOFTINT_REG_34 `SPC4.tlu.trl0.rd_softint2
9888`define INT_LEVEL_TAKEN_34 `SPC4.tlu.trl0.take_iln&`SPC4.tlu.trl0.trap[2]
9889`define INT_LEVEL_NUM_34 `SPC4.tlu.trl0.int_level_n
9890`define PMU_TAKEN_34 `SPC4.tlu.trl0.take_pmu&`SPC4.tlu.trl0.trap[2]
9891
9892`define HINTP_RDWR_34 (`TOP.nas_top.c4.t2.asi_rdwr_hintp | `TOP.nas_top.c4.t2.asi_wr_hintp_delay)
9893`define HINTP_WR_34 (`SPC4.tlu.asi_wr_hintp[34])
9894`define HSTMATCH_34 `SPC4.tlu.trl0.hstick2_compare
9895
9896`define HINTP_REG_34 `SPC4.tlu.trl0.hintp2
9897`define HSTM_TAKEN_34 `SPC4.tlu.trl0.take_hst&`SPC4.tlu.trl0.trap[2]
9898
9899`define NAS_PIPE_FW2_34 |`TOP.nas_top.c4.t2.complete_fw2
9900
9901`define CWQ_TAKEN_34 `SPC4.tlu.trl0.take_cwq&`SPC4.tlu.trl0.trap[2]
9902`define SMA_TAKEN_34 `SPC4.tlu.trl0.take_sma&`SPC4.tlu.trl0.trap[2]
9903
9904`define POR_TAKEN_34 `SPC4.tlu.trl0.take_por&`SPC4.tlu.trl0.trap[2]
9905
9906/////////////////////////////// Probes //////////////////////////////////// }}}
9907
9908always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
9909
9910 // {{{ DETECT, PIPE & SEND
9911 take_disrupting_w <= (`INT_VEC_TAKEN_34 || `CPU_MONDO_TAKEN_34 ||
9912 `DEV_MONDO_TAKEN_34 || `RES_MONDO_TAKEN_34 ||
9913 `XIR_TAKEN_34 || `INT_LEVEL_TAKEN_34 ||
9914 `HSTM_TAKEN_34 || `CWQ_TAKEN_34 ||
9915 `SMA_TAKEN_34 || `PMU_TAKEN_34 || `POR_TAKEN_34);
9916 take_disrupting_fx4 <= take_disrupting_w;
9917 take_disrupting_fx5 <= take_disrupting_fx4;
9918 take_disrupting_fb <= take_disrupting_fx5;
9919 take_disrupting_fw <= take_disrupting_fb;
9920 take_disrupting_fw1 <= take_disrupting_fw;
9921 take_disrupting_fw2 <= take_disrupting_fw1;
9922
9923 case ({`INT_VEC_TAKEN_34, `CPU_MONDO_TAKEN_34,
9924 `DEV_MONDO_TAKEN_34, `RES_MONDO_TAKEN_34,
9925 `XIR_TAKEN_34, `INT_LEVEL_TAKEN_34,
9926 `HSTM_TAKEN_34, `CWQ_TAKEN_34, `SMA_TAKEN_34 ,
9927 `PMU_TAKEN_34, `POR_TAKEN_34})
9928 11'b10000000000: int_num_w <= 8'h60;
9929 11'b01000000000: int_num_w <= 8'h7c;
9930 11'b00100000000: int_num_w <= 8'h7d;
9931 11'b00010000000: int_num_w <= 8'h7e;
9932 11'b00001000000: int_num_w <= 8'h03;
9933 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_34;
9934 11'b00000010000: int_num_w <= 8'h5e;
9935 11'b00000001000: int_num_w <= 8'h3c;
9936 11'b00000000100: int_num_w <= 8'h3d;
9937 11'b00000000010: int_num_w <= 8'h4f;
9938 11'b00000000001: int_num_w <= 8'h01;
9939 endcase
9940
9941 int_num_fx4 <= int_num_w;
9942 int_num_fx5 <= int_num_fx4;
9943 int_num_fb <= int_num_fx5;
9944 int_num_fw <= int_num_fb;
9945 int_num_fw1 <= int_num_fw;
9946 int_num_fw2 <= int_num_fw1;
9947 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
9948 begin // {
9949 `PR_INFO ("pli_int", `INFO,
9950 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
9951 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
9952 end // }
9953
9954 // }}}
9955
9956/////////////////////////// Vectored Interrupt /////////////////////////// {{{
9957
9958 // Vectored Interrupt Recv Register Detection
9959 // Indicate when register changes due to arriving interrupt, and not
9960 // due to read of incoming register or ASI write ..
9961
9962
9963 // If any read occurs, send value right away.
9964 // While a read/write is pending, do not update delta.
9965 // Send non read/wr delta during fw2 ..
9966
9967
9968 if (!(`INT_VEC_RDWR_34 | `INT_VEC_RECV_ASIWR_34)) begin // {
9969 if (~`INT_VEC_RECV_ASIWR_34 &
9970 (int_vec_recv_reg !== `INT_VEC_RECV_REG_34 ))
9971 int_vec_recv_reg_delta <= 1'b1;
9972 int_vec_recv_reg <= `INT_VEC_RECV_REG_34;
9973 end // }
9974 else if (`INT_VEC_RECV_ASIWR_34)
9975 int_vec_recv_reg <= `TOP.nas_top.c4.t2.asi_updated_int_rec;
9976
9977 if ((`NAS_PIPE_FW2_34 & int_vec_recv_reg_delta ) |
9978 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
9979 `INT_VEC_RECV_ASIWR_34 ) begin // {
9980 `PR_INFO ("pli_int", `INFO,
9981 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
9982 mycid,mytid, int_vec_recv_reg);
9983 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
9984 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
9985 64'h0, int_vec_recv_reg);
9986 end // }
9987 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_34 &
9988 (int_vec_recv_reg !== `INT_VEC_RECV_REG_34 ))))
9989 int_vec_recv_reg_delta <= 1'b0;
9990 end //}
9991
9992 int_vec_reg_rdwr <= `INT_VEC_RDWR_34 | `INT_VEC_RECV_ASIWR_34;
9993 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_34 & ~ inc_vec_reg_rd;
9994
9995 if (`INT_VEC_RECV_ASIWR_34)
9996 inc_vec_reg_rd <= 1'b1;
9997 if (`NAS_PIPE_FW2_34)
9998 inc_vec_reg_rd <= 1'b0;
9999
10000
10001/////////////////////////// Vectored Interrupt /////////////////////////// }}}
10002
10003/////////////////////////// Asynchronous Resets ////////////////////////// {{{
10004
10005
10006/////////////////////////// Asynchronous Resets ////////////////////////// }}}
10007
10008/////////////////////////// Softint ///////////////////////////////////// {{{
10009
10010 // Softint Register hardware Update Detection
10011
10012 // Non software updates (TM/SM)
10013
10014 // If any read occurs, send value right away.
10015 // While a read/write is pending, do not update delta.
10016 // Send non read/wr delta during fw2 ..
10017
10018 // RTL keeps pic_ovf indication in rd_softint and not softint.
10019 // So for set/clear writes, we send softint before the write ..,
10020 // and for read/asyncs we send rd_softint ..
10021
10022
10023 if (~`SOFTINT_RDWR_34) begin // {
10024 if (softint !== `RD_SOFTINT_REG_34 )
10025 softint_delta <= 1'b1;
10026 softint <= `RD_SOFTINT_REG_34;
10027 end // }
10028
10029 if ((`NAS_PIPE_FW2_34 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
10030 ) begin // {
10031 `PR_INFO ("pli_int", `INFO,
10032 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10033 mycid,mytid, {47'h0, softint});
10034 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10035 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10036 {47'h0, softint});
10037 end // }
10038 if (!(~`SOFTINT_RDWR_34&(softint !== `RD_SOFTINT_REG_34)))
10039 softint_delta <= 1'b0;
10040 end //}
10041 else if (`SPC4.tlu.asi_wr_clear_softint[2] |
10042 `SPC4.tlu.asi_wr_set_softint[2] ) begin // {
10043 `PR_INFO ("pli_int", `INFO,
10044 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10045 mycid,mytid, {47'h0, `RD_SOFTINT_REG_34});
10046 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10047 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10048 {47'h0, `RD_SOFTINT_REG_34});
10049 end // }
10050 end //}
10051
10052
10053 softint_rdwr <= `SOFTINT_RDWR_34 ;
10054 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_34;
10055
10056
10057/////////////////////////// Softint ///////////////////////////////////// }}}
10058
10059/////////////////////////// Hintp ///////////////////////////////////// {{{
10060
10061 // Hintp Register hardware Update Detection
10062
10063 // Non software updates (HSP)
10064 // If HINTP is already read/written by SW, then don't send
10065 // any async updates to Nas. Reads/Writes pending sstep is detected
10066 // by snooping nas_pipe ..
10067
10068 hintp <= `HINTP_REG_34 ;
10069 if (hstmatch_late)
10070 hintp_delta <= 1'b1;
10071
10072 if ((~hintp_rdwr & `NAS_PIPE_FW2_34 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
10073 (hintp_rdwr_late & hintp_delta) ) begin // {
10074 `PR_INFO ("pli_int", `INFO,
10075 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
10076 mycid,mytid, {63'h0, hintp});
10077 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10078 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
10079 {63'h0, hintp});
10080 end // }
10081 if (~(hintp_rdwr_late & hintp_delta))
10082 hintp_delta <= 1'b0;
10083 end //}
10084
10085 hintp_rdwr <= `HINTP_RDWR_34;
10086 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_34;
10087 hstmatch_late <= `HSTMATCH_34;
10088
10089
10090/////////////////////////// Hintp ///////////////////////////////////// }}}
10091
10092end //}
10093`endif
10094endmodule
10095
10096// }}}
10097
10098module int_c4t3 ();
10099`ifndef GATESIM
10100
10101// common defines
10102`include "defines.vh"
10103`include "ccx.vri"
10104`include "cmp.vri"
10105
10106wire [2:0] mycid;
10107wire [2:0] mytid;
10108wire [5:0] mytnum;
10109integer junk;
10110
10111reg [63:0] int_vec_recv_reg;
10112reg int_vec_recv_reg_delta;
10113reg int_vec_reg_rdwr;
10114reg inc_vec_reg_rd;
10115reg int_vec_reg_rdwr_late;
10116reg [16:0] softint;
10117reg softint_rdwr;
10118reg softint_rdwr_late;
10119reg softint_delta;
10120reg hintp;
10121reg hintp_rdwr;
10122reg hintp_rdwr_late;
10123reg hintp_delta;
10124reg hstmatch_late;
10125reg ready;
10126reg [7:0] int_num_w;
10127reg [7:0] int_num_fx4;
10128reg [7:0] int_num_fx5;
10129reg [7:0] int_num_fb;
10130reg [7:0] int_num_fw;
10131reg [7:0] int_num_fw1;
10132reg [7:0] int_num_fw2;
10133reg take_disrupting_w;
10134reg take_disrupting_fx4;
10135reg take_disrupting_fx5;
10136reg take_disrupting_fb;
10137reg take_disrupting_fw;
10138reg take_disrupting_fw1;
10139reg take_disrupting_fw2;
10140
10141 assign mycid = 4;
10142 assign mytid = 3;
10143 assign mytnum = 4*8 + 3;
10144
10145initial begin // {
10146 ready = 0; // Wait for socket setup ..
10147 inc_vec_reg_rd <= 1'b0;
10148 int_vec_recv_reg_delta <= 1'b0;
10149 softint_delta <= 1'b0;
10150 hintp_delta <= 1'b0;
10151 int_vec_recv_reg = 64'b0;
10152 @(posedge `BENCH_SPC4_GCLK) ;
10153 @(posedge `BENCH_SPC4_GCLK) ;
10154 ready = `PARGS.int_sync_on;
10155end //}
10156
10157
10158/////////////////////////////// Probes //////////////////////////////////// {{{
10159
10160`define INT_VEC_RECV_REG_35 `SPC4.tlu.cth.int_rec3
10161`define INT_VEC_RECV_ASIWR_35 (`TOP.nas_top.c4.t3.asi_wr_int_rec_delay)
10162`define INT_VEC_RDWR_35 (`TOP.nas_top.c4.t3.asi_rdwr_int_rec)
10163`define INT_VEC_TAKEN_35 `SPC4.tlu.trl0.take_ivt&`SPC4.tlu.trl0.trap[3]
10164
10165`define CPU_MONDO_TAKEN_35 `SPC4.tlu.trl0.take_mqr&`SPC4.tlu.trl0.trap[3]
10166`define DEV_MONDO_TAKEN_35 `SPC4.tlu.trl0.take_dqr&`SPC4.tlu.trl0.trap[3]
10167`define RES_MONDO_TAKEN_35 `SPC4.tlu.trl0.take_rqr&`SPC4.tlu.trl0.trap[3]
10168
10169`define XIR_TAKEN_35 `SPC4.tlu.trl0.take_xir&`SPC4.tlu.trl0.trap[3]
10170
10171`define SOFTINT_RDWR_35 (`TOP.nas_top.c4.t3.asi_rdwr_softint|`TOP.nas_top.c4.t3.asi_wr_softint_delay)
10172
10173`define SOFTINT_REG_35 `SPC4.tlu.trl0.softint3
10174`define RD_SOFTINT_REG_35 `SPC4.tlu.trl0.rd_softint3
10175`define INT_LEVEL_TAKEN_35 `SPC4.tlu.trl0.take_iln&`SPC4.tlu.trl0.trap[3]
10176`define INT_LEVEL_NUM_35 `SPC4.tlu.trl0.int_level_n
10177`define PMU_TAKEN_35 `SPC4.tlu.trl0.take_pmu&`SPC4.tlu.trl0.trap[3]
10178
10179`define HINTP_RDWR_35 (`TOP.nas_top.c4.t3.asi_rdwr_hintp | `TOP.nas_top.c4.t3.asi_wr_hintp_delay)
10180`define HINTP_WR_35 (`SPC4.tlu.asi_wr_hintp[35])
10181`define HSTMATCH_35 `SPC4.tlu.trl0.hstick3_compare
10182
10183`define HINTP_REG_35 `SPC4.tlu.trl0.hintp3
10184`define HSTM_TAKEN_35 `SPC4.tlu.trl0.take_hst&`SPC4.tlu.trl0.trap[3]
10185
10186`define NAS_PIPE_FW2_35 |`TOP.nas_top.c4.t3.complete_fw2
10187
10188`define CWQ_TAKEN_35 `SPC4.tlu.trl0.take_cwq&`SPC4.tlu.trl0.trap[3]
10189`define SMA_TAKEN_35 `SPC4.tlu.trl0.take_sma&`SPC4.tlu.trl0.trap[3]
10190
10191`define POR_TAKEN_35 `SPC4.tlu.trl0.take_por&`SPC4.tlu.trl0.trap[3]
10192
10193/////////////////////////////// Probes //////////////////////////////////// }}}
10194
10195always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
10196
10197 // {{{ DETECT, PIPE & SEND
10198 take_disrupting_w <= (`INT_VEC_TAKEN_35 || `CPU_MONDO_TAKEN_35 ||
10199 `DEV_MONDO_TAKEN_35 || `RES_MONDO_TAKEN_35 ||
10200 `XIR_TAKEN_35 || `INT_LEVEL_TAKEN_35 ||
10201 `HSTM_TAKEN_35 || `CWQ_TAKEN_35 ||
10202 `SMA_TAKEN_35 || `PMU_TAKEN_35 || `POR_TAKEN_35);
10203 take_disrupting_fx4 <= take_disrupting_w;
10204 take_disrupting_fx5 <= take_disrupting_fx4;
10205 take_disrupting_fb <= take_disrupting_fx5;
10206 take_disrupting_fw <= take_disrupting_fb;
10207 take_disrupting_fw1 <= take_disrupting_fw;
10208 take_disrupting_fw2 <= take_disrupting_fw1;
10209
10210 case ({`INT_VEC_TAKEN_35, `CPU_MONDO_TAKEN_35,
10211 `DEV_MONDO_TAKEN_35, `RES_MONDO_TAKEN_35,
10212 `XIR_TAKEN_35, `INT_LEVEL_TAKEN_35,
10213 `HSTM_TAKEN_35, `CWQ_TAKEN_35, `SMA_TAKEN_35 ,
10214 `PMU_TAKEN_35, `POR_TAKEN_35})
10215 11'b10000000000: int_num_w <= 8'h60;
10216 11'b01000000000: int_num_w <= 8'h7c;
10217 11'b00100000000: int_num_w <= 8'h7d;
10218 11'b00010000000: int_num_w <= 8'h7e;
10219 11'b00001000000: int_num_w <= 8'h03;
10220 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_35;
10221 11'b00000010000: int_num_w <= 8'h5e;
10222 11'b00000001000: int_num_w <= 8'h3c;
10223 11'b00000000100: int_num_w <= 8'h3d;
10224 11'b00000000010: int_num_w <= 8'h4f;
10225 11'b00000000001: int_num_w <= 8'h01;
10226 endcase
10227
10228 int_num_fx4 <= int_num_w;
10229 int_num_fx5 <= int_num_fx4;
10230 int_num_fb <= int_num_fx5;
10231 int_num_fw <= int_num_fb;
10232 int_num_fw1 <= int_num_fw;
10233 int_num_fw2 <= int_num_fw1;
10234 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
10235 begin // {
10236 `PR_INFO ("pli_int", `INFO,
10237 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
10238 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10239 end // }
10240
10241 // }}}
10242
10243/////////////////////////// Vectored Interrupt /////////////////////////// {{{
10244
10245 // Vectored Interrupt Recv Register Detection
10246 // Indicate when register changes due to arriving interrupt, and not
10247 // due to read of incoming register or ASI write ..
10248
10249
10250 // If any read occurs, send value right away.
10251 // While a read/write is pending, do not update delta.
10252 // Send non read/wr delta during fw2 ..
10253
10254
10255 if (!(`INT_VEC_RDWR_35 | `INT_VEC_RECV_ASIWR_35)) begin // {
10256 if (~`INT_VEC_RECV_ASIWR_35 &
10257 (int_vec_recv_reg !== `INT_VEC_RECV_REG_35 ))
10258 int_vec_recv_reg_delta <= 1'b1;
10259 int_vec_recv_reg <= `INT_VEC_RECV_REG_35;
10260 end // }
10261 else if (`INT_VEC_RECV_ASIWR_35)
10262 int_vec_recv_reg <= `TOP.nas_top.c4.t3.asi_updated_int_rec;
10263
10264 if ((`NAS_PIPE_FW2_35 & int_vec_recv_reg_delta ) |
10265 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
10266 `INT_VEC_RECV_ASIWR_35 ) begin // {
10267 `PR_INFO ("pli_int", `INFO,
10268 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
10269 mycid,mytid, int_vec_recv_reg);
10270 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10271 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
10272 64'h0, int_vec_recv_reg);
10273 end // }
10274 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_35 &
10275 (int_vec_recv_reg !== `INT_VEC_RECV_REG_35 ))))
10276 int_vec_recv_reg_delta <= 1'b0;
10277 end //}
10278
10279 int_vec_reg_rdwr <= `INT_VEC_RDWR_35 | `INT_VEC_RECV_ASIWR_35;
10280 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_35 & ~ inc_vec_reg_rd;
10281
10282 if (`INT_VEC_RECV_ASIWR_35)
10283 inc_vec_reg_rd <= 1'b1;
10284 if (`NAS_PIPE_FW2_35)
10285 inc_vec_reg_rd <= 1'b0;
10286
10287
10288/////////////////////////// Vectored Interrupt /////////////////////////// }}}
10289
10290/////////////////////////// Asynchronous Resets ////////////////////////// {{{
10291
10292
10293/////////////////////////// Asynchronous Resets ////////////////////////// }}}
10294
10295/////////////////////////// Softint ///////////////////////////////////// {{{
10296
10297 // Softint Register hardware Update Detection
10298
10299 // Non software updates (TM/SM)
10300
10301 // If any read occurs, send value right away.
10302 // While a read/write is pending, do not update delta.
10303 // Send non read/wr delta during fw2 ..
10304
10305 // RTL keeps pic_ovf indication in rd_softint and not softint.
10306 // So for set/clear writes, we send softint before the write ..,
10307 // and for read/asyncs we send rd_softint ..
10308
10309
10310 if (~`SOFTINT_RDWR_35) begin // {
10311 if (softint !== `RD_SOFTINT_REG_35 )
10312 softint_delta <= 1'b1;
10313 softint <= `RD_SOFTINT_REG_35;
10314 end // }
10315
10316 if ((`NAS_PIPE_FW2_35 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
10317 ) begin // {
10318 `PR_INFO ("pli_int", `INFO,
10319 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10320 mycid,mytid, {47'h0, softint});
10321 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10322 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10323 {47'h0, softint});
10324 end // }
10325 if (!(~`SOFTINT_RDWR_35&(softint !== `RD_SOFTINT_REG_35)))
10326 softint_delta <= 1'b0;
10327 end //}
10328 else if (`SPC4.tlu.asi_wr_clear_softint[3] |
10329 `SPC4.tlu.asi_wr_set_softint[3] ) begin // {
10330 `PR_INFO ("pli_int", `INFO,
10331 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10332 mycid,mytid, {47'h0, `RD_SOFTINT_REG_35});
10333 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10334 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10335 {47'h0, `RD_SOFTINT_REG_35});
10336 end // }
10337 end //}
10338
10339
10340 softint_rdwr <= `SOFTINT_RDWR_35 ;
10341 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_35;
10342
10343
10344/////////////////////////// Softint ///////////////////////////////////// }}}
10345
10346/////////////////////////// Hintp ///////////////////////////////////// {{{
10347
10348 // Hintp Register hardware Update Detection
10349
10350 // Non software updates (HSP)
10351 // If HINTP is already read/written by SW, then don't send
10352 // any async updates to Nas. Reads/Writes pending sstep is detected
10353 // by snooping nas_pipe ..
10354
10355 hintp <= `HINTP_REG_35 ;
10356 if (hstmatch_late)
10357 hintp_delta <= 1'b1;
10358
10359 if ((~hintp_rdwr & `NAS_PIPE_FW2_35 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
10360 (hintp_rdwr_late & hintp_delta) ) begin // {
10361 `PR_INFO ("pli_int", `INFO,
10362 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
10363 mycid,mytid, {63'h0, hintp});
10364 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10365 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
10366 {63'h0, hintp});
10367 end // }
10368 if (~(hintp_rdwr_late & hintp_delta))
10369 hintp_delta <= 1'b0;
10370 end //}
10371
10372 hintp_rdwr <= `HINTP_RDWR_35;
10373 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_35;
10374 hstmatch_late <= `HSTMATCH_35;
10375
10376
10377/////////////////////////// Hintp ///////////////////////////////////// }}}
10378
10379end //}
10380`endif
10381endmodule
10382
10383// }}}
10384
10385module int_c4t4 ();
10386`ifndef GATESIM
10387
10388// common defines
10389`include "defines.vh"
10390`include "ccx.vri"
10391`include "cmp.vri"
10392
10393wire [2:0] mycid;
10394wire [2:0] mytid;
10395wire [5:0] mytnum;
10396integer junk;
10397
10398reg [63:0] int_vec_recv_reg;
10399reg int_vec_recv_reg_delta;
10400reg int_vec_reg_rdwr;
10401reg inc_vec_reg_rd;
10402reg int_vec_reg_rdwr_late;
10403reg [16:0] softint;
10404reg softint_rdwr;
10405reg softint_rdwr_late;
10406reg softint_delta;
10407reg hintp;
10408reg hintp_rdwr;
10409reg hintp_rdwr_late;
10410reg hintp_delta;
10411reg hstmatch_late;
10412reg ready;
10413reg [7:0] int_num_w;
10414reg [7:0] int_num_fx4;
10415reg [7:0] int_num_fx5;
10416reg [7:0] int_num_fb;
10417reg [7:0] int_num_fw;
10418reg [7:0] int_num_fw1;
10419reg [7:0] int_num_fw2;
10420reg take_disrupting_w;
10421reg take_disrupting_fx4;
10422reg take_disrupting_fx5;
10423reg take_disrupting_fb;
10424reg take_disrupting_fw;
10425reg take_disrupting_fw1;
10426reg take_disrupting_fw2;
10427
10428 assign mycid = 4;
10429 assign mytid = 4;
10430 assign mytnum = 4*8 + 4;
10431
10432initial begin // {
10433 ready = 0; // Wait for socket setup ..
10434 inc_vec_reg_rd <= 1'b0;
10435 int_vec_recv_reg_delta <= 1'b0;
10436 softint_delta <= 1'b0;
10437 hintp_delta <= 1'b0;
10438 int_vec_recv_reg = 64'b0;
10439 @(posedge `BENCH_SPC4_GCLK) ;
10440 @(posedge `BENCH_SPC4_GCLK) ;
10441 ready = `PARGS.int_sync_on;
10442end //}
10443
10444
10445/////////////////////////////// Probes //////////////////////////////////// {{{
10446
10447`define INT_VEC_RECV_REG_36 `SPC4.tlu.cth.int_rec4
10448`define INT_VEC_RECV_ASIWR_36 (`TOP.nas_top.c4.t4.asi_wr_int_rec_delay)
10449`define INT_VEC_RDWR_36 (`TOP.nas_top.c4.t4.asi_rdwr_int_rec)
10450`define INT_VEC_TAKEN_36 `SPC4.tlu.trl1.take_ivt&`SPC4.tlu.trl1.trap[0]
10451
10452`define CPU_MONDO_TAKEN_36 `SPC4.tlu.trl1.take_mqr&`SPC4.tlu.trl1.trap[0]
10453`define DEV_MONDO_TAKEN_36 `SPC4.tlu.trl1.take_dqr&`SPC4.tlu.trl1.trap[0]
10454`define RES_MONDO_TAKEN_36 `SPC4.tlu.trl1.take_rqr&`SPC4.tlu.trl1.trap[0]
10455
10456`define XIR_TAKEN_36 `SPC4.tlu.trl1.take_xir&`SPC4.tlu.trl1.trap[0]
10457
10458`define SOFTINT_RDWR_36 (`TOP.nas_top.c4.t4.asi_rdwr_softint|`TOP.nas_top.c4.t4.asi_wr_softint_delay)
10459
10460`define SOFTINT_REG_36 `SPC4.tlu.trl1.softint0
10461`define RD_SOFTINT_REG_36 `SPC4.tlu.trl1.rd_softint0
10462`define INT_LEVEL_TAKEN_36 `SPC4.tlu.trl1.take_iln&`SPC4.tlu.trl1.trap[0]
10463`define INT_LEVEL_NUM_36 `SPC4.tlu.trl1.int_level_n
10464`define PMU_TAKEN_36 `SPC4.tlu.trl1.take_pmu&`SPC4.tlu.trl1.trap[0]
10465
10466`define HINTP_RDWR_36 (`TOP.nas_top.c4.t4.asi_rdwr_hintp | `TOP.nas_top.c4.t4.asi_wr_hintp_delay)
10467`define HINTP_WR_36 (`SPC4.tlu.asi_wr_hintp[36])
10468`define HSTMATCH_36 `SPC4.tlu.trl1.hstick0_compare
10469
10470`define HINTP_REG_36 `SPC4.tlu.trl1.hintp0
10471`define HSTM_TAKEN_36 `SPC4.tlu.trl1.take_hst&`SPC4.tlu.trl1.trap[0]
10472
10473`define NAS_PIPE_FW2_36 |`TOP.nas_top.c4.t4.complete_fw2
10474
10475`define CWQ_TAKEN_36 `SPC4.tlu.trl1.take_cwq&`SPC4.tlu.trl1.trap[0]
10476`define SMA_TAKEN_36 `SPC4.tlu.trl1.take_sma&`SPC4.tlu.trl1.trap[0]
10477
10478`define POR_TAKEN_36 `SPC4.tlu.trl1.take_por&`SPC4.tlu.trl1.trap[0]
10479
10480/////////////////////////////// Probes //////////////////////////////////// }}}
10481
10482always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
10483
10484 // {{{ DETECT, PIPE & SEND
10485 take_disrupting_w <= (`INT_VEC_TAKEN_36 || `CPU_MONDO_TAKEN_36 ||
10486 `DEV_MONDO_TAKEN_36 || `RES_MONDO_TAKEN_36 ||
10487 `XIR_TAKEN_36 || `INT_LEVEL_TAKEN_36 ||
10488 `HSTM_TAKEN_36 || `CWQ_TAKEN_36 ||
10489 `SMA_TAKEN_36 || `PMU_TAKEN_36 || `POR_TAKEN_36);
10490 take_disrupting_fx4 <= take_disrupting_w;
10491 take_disrupting_fx5 <= take_disrupting_fx4;
10492 take_disrupting_fb <= take_disrupting_fx5;
10493 take_disrupting_fw <= take_disrupting_fb;
10494 take_disrupting_fw1 <= take_disrupting_fw;
10495 take_disrupting_fw2 <= take_disrupting_fw1;
10496
10497 case ({`INT_VEC_TAKEN_36, `CPU_MONDO_TAKEN_36,
10498 `DEV_MONDO_TAKEN_36, `RES_MONDO_TAKEN_36,
10499 `XIR_TAKEN_36, `INT_LEVEL_TAKEN_36,
10500 `HSTM_TAKEN_36, `CWQ_TAKEN_36, `SMA_TAKEN_36 ,
10501 `PMU_TAKEN_36, `POR_TAKEN_36})
10502 11'b10000000000: int_num_w <= 8'h60;
10503 11'b01000000000: int_num_w <= 8'h7c;
10504 11'b00100000000: int_num_w <= 8'h7d;
10505 11'b00010000000: int_num_w <= 8'h7e;
10506 11'b00001000000: int_num_w <= 8'h03;
10507 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_36;
10508 11'b00000010000: int_num_w <= 8'h5e;
10509 11'b00000001000: int_num_w <= 8'h3c;
10510 11'b00000000100: int_num_w <= 8'h3d;
10511 11'b00000000010: int_num_w <= 8'h4f;
10512 11'b00000000001: int_num_w <= 8'h01;
10513 endcase
10514
10515 int_num_fx4 <= int_num_w;
10516 int_num_fx5 <= int_num_fx4;
10517 int_num_fb <= int_num_fx5;
10518 int_num_fw <= int_num_fb;
10519 int_num_fw1 <= int_num_fw;
10520 int_num_fw2 <= int_num_fw1;
10521 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
10522 begin // {
10523 `PR_INFO ("pli_int", `INFO,
10524 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
10525 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10526 end // }
10527
10528 // }}}
10529
10530/////////////////////////// Vectored Interrupt /////////////////////////// {{{
10531
10532 // Vectored Interrupt Recv Register Detection
10533 // Indicate when register changes due to arriving interrupt, and not
10534 // due to read of incoming register or ASI write ..
10535
10536
10537 // If any read occurs, send value right away.
10538 // While a read/write is pending, do not update delta.
10539 // Send non read/wr delta during fw2 ..
10540
10541
10542 if (!(`INT_VEC_RDWR_36 | `INT_VEC_RECV_ASIWR_36)) begin // {
10543 if (~`INT_VEC_RECV_ASIWR_36 &
10544 (int_vec_recv_reg !== `INT_VEC_RECV_REG_36 ))
10545 int_vec_recv_reg_delta <= 1'b1;
10546 int_vec_recv_reg <= `INT_VEC_RECV_REG_36;
10547 end // }
10548 else if (`INT_VEC_RECV_ASIWR_36)
10549 int_vec_recv_reg <= `TOP.nas_top.c4.t4.asi_updated_int_rec;
10550
10551 if ((`NAS_PIPE_FW2_36 & int_vec_recv_reg_delta ) |
10552 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
10553 `INT_VEC_RECV_ASIWR_36 ) begin // {
10554 `PR_INFO ("pli_int", `INFO,
10555 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
10556 mycid,mytid, int_vec_recv_reg);
10557 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10558 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
10559 64'h0, int_vec_recv_reg);
10560 end // }
10561 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_36 &
10562 (int_vec_recv_reg !== `INT_VEC_RECV_REG_36 ))))
10563 int_vec_recv_reg_delta <= 1'b0;
10564 end //}
10565
10566 int_vec_reg_rdwr <= `INT_VEC_RDWR_36 | `INT_VEC_RECV_ASIWR_36;
10567 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_36 & ~ inc_vec_reg_rd;
10568
10569 if (`INT_VEC_RECV_ASIWR_36)
10570 inc_vec_reg_rd <= 1'b1;
10571 if (`NAS_PIPE_FW2_36)
10572 inc_vec_reg_rd <= 1'b0;
10573
10574
10575/////////////////////////// Vectored Interrupt /////////////////////////// }}}
10576
10577/////////////////////////// Asynchronous Resets ////////////////////////// {{{
10578
10579
10580/////////////////////////// Asynchronous Resets ////////////////////////// }}}
10581
10582/////////////////////////// Softint ///////////////////////////////////// {{{
10583
10584 // Softint Register hardware Update Detection
10585
10586 // Non software updates (TM/SM)
10587
10588 // If any read occurs, send value right away.
10589 // While a read/write is pending, do not update delta.
10590 // Send non read/wr delta during fw2 ..
10591
10592 // RTL keeps pic_ovf indication in rd_softint and not softint.
10593 // So for set/clear writes, we send softint before the write ..,
10594 // and for read/asyncs we send rd_softint ..
10595
10596
10597 if (~`SOFTINT_RDWR_36) begin // {
10598 if (softint !== `RD_SOFTINT_REG_36 )
10599 softint_delta <= 1'b1;
10600 softint <= `RD_SOFTINT_REG_36;
10601 end // }
10602
10603 if ((`NAS_PIPE_FW2_36 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
10604 ) begin // {
10605 `PR_INFO ("pli_int", `INFO,
10606 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10607 mycid,mytid, {47'h0, softint});
10608 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10609 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10610 {47'h0, softint});
10611 end // }
10612 if (!(~`SOFTINT_RDWR_36&(softint !== `RD_SOFTINT_REG_36)))
10613 softint_delta <= 1'b0;
10614 end //}
10615 else if (`SPC4.tlu.asi_wr_clear_softint[4] |
10616 `SPC4.tlu.asi_wr_set_softint[4] ) begin // {
10617 `PR_INFO ("pli_int", `INFO,
10618 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10619 mycid,mytid, {47'h0, `RD_SOFTINT_REG_36});
10620 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10621 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10622 {47'h0, `RD_SOFTINT_REG_36});
10623 end // }
10624 end //}
10625
10626
10627 softint_rdwr <= `SOFTINT_RDWR_36 ;
10628 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_36;
10629
10630
10631/////////////////////////// Softint ///////////////////////////////////// }}}
10632
10633/////////////////////////// Hintp ///////////////////////////////////// {{{
10634
10635 // Hintp Register hardware Update Detection
10636
10637 // Non software updates (HSP)
10638 // If HINTP is already read/written by SW, then don't send
10639 // any async updates to Nas. Reads/Writes pending sstep is detected
10640 // by snooping nas_pipe ..
10641
10642 hintp <= `HINTP_REG_36 ;
10643 if (hstmatch_late)
10644 hintp_delta <= 1'b1;
10645
10646 if ((~hintp_rdwr & `NAS_PIPE_FW2_36 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
10647 (hintp_rdwr_late & hintp_delta) ) begin // {
10648 `PR_INFO ("pli_int", `INFO,
10649 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
10650 mycid,mytid, {63'h0, hintp});
10651 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10652 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
10653 {63'h0, hintp});
10654 end // }
10655 if (~(hintp_rdwr_late & hintp_delta))
10656 hintp_delta <= 1'b0;
10657 end //}
10658
10659 hintp_rdwr <= `HINTP_RDWR_36;
10660 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_36;
10661 hstmatch_late <= `HSTMATCH_36;
10662
10663
10664/////////////////////////// Hintp ///////////////////////////////////// }}}
10665
10666end //}
10667`endif
10668endmodule
10669
10670// }}}
10671
10672module int_c4t5 ();
10673`ifndef GATESIM
10674
10675// common defines
10676`include "defines.vh"
10677`include "ccx.vri"
10678`include "cmp.vri"
10679
10680wire [2:0] mycid;
10681wire [2:0] mytid;
10682wire [5:0] mytnum;
10683integer junk;
10684
10685reg [63:0] int_vec_recv_reg;
10686reg int_vec_recv_reg_delta;
10687reg int_vec_reg_rdwr;
10688reg inc_vec_reg_rd;
10689reg int_vec_reg_rdwr_late;
10690reg [16:0] softint;
10691reg softint_rdwr;
10692reg softint_rdwr_late;
10693reg softint_delta;
10694reg hintp;
10695reg hintp_rdwr;
10696reg hintp_rdwr_late;
10697reg hintp_delta;
10698reg hstmatch_late;
10699reg ready;
10700reg [7:0] int_num_w;
10701reg [7:0] int_num_fx4;
10702reg [7:0] int_num_fx5;
10703reg [7:0] int_num_fb;
10704reg [7:0] int_num_fw;
10705reg [7:0] int_num_fw1;
10706reg [7:0] int_num_fw2;
10707reg take_disrupting_w;
10708reg take_disrupting_fx4;
10709reg take_disrupting_fx5;
10710reg take_disrupting_fb;
10711reg take_disrupting_fw;
10712reg take_disrupting_fw1;
10713reg take_disrupting_fw2;
10714
10715 assign mycid = 4;
10716 assign mytid = 5;
10717 assign mytnum = 4*8 + 5;
10718
10719initial begin // {
10720 ready = 0; // Wait for socket setup ..
10721 inc_vec_reg_rd <= 1'b0;
10722 int_vec_recv_reg_delta <= 1'b0;
10723 softint_delta <= 1'b0;
10724 hintp_delta <= 1'b0;
10725 int_vec_recv_reg = 64'b0;
10726 @(posedge `BENCH_SPC4_GCLK) ;
10727 @(posedge `BENCH_SPC4_GCLK) ;
10728 ready = `PARGS.int_sync_on;
10729end //}
10730
10731
10732/////////////////////////////// Probes //////////////////////////////////// {{{
10733
10734`define INT_VEC_RECV_REG_37 `SPC4.tlu.cth.int_rec5
10735`define INT_VEC_RECV_ASIWR_37 (`TOP.nas_top.c4.t5.asi_wr_int_rec_delay)
10736`define INT_VEC_RDWR_37 (`TOP.nas_top.c4.t5.asi_rdwr_int_rec)
10737`define INT_VEC_TAKEN_37 `SPC4.tlu.trl1.take_ivt&`SPC4.tlu.trl1.trap[1]
10738
10739`define CPU_MONDO_TAKEN_37 `SPC4.tlu.trl1.take_mqr&`SPC4.tlu.trl1.trap[1]
10740`define DEV_MONDO_TAKEN_37 `SPC4.tlu.trl1.take_dqr&`SPC4.tlu.trl1.trap[1]
10741`define RES_MONDO_TAKEN_37 `SPC4.tlu.trl1.take_rqr&`SPC4.tlu.trl1.trap[1]
10742
10743`define XIR_TAKEN_37 `SPC4.tlu.trl1.take_xir&`SPC4.tlu.trl1.trap[1]
10744
10745`define SOFTINT_RDWR_37 (`TOP.nas_top.c4.t5.asi_rdwr_softint|`TOP.nas_top.c4.t5.asi_wr_softint_delay)
10746
10747`define SOFTINT_REG_37 `SPC4.tlu.trl1.softint1
10748`define RD_SOFTINT_REG_37 `SPC4.tlu.trl1.rd_softint1
10749`define INT_LEVEL_TAKEN_37 `SPC4.tlu.trl1.take_iln&`SPC4.tlu.trl1.trap[1]
10750`define INT_LEVEL_NUM_37 `SPC4.tlu.trl1.int_level_n
10751`define PMU_TAKEN_37 `SPC4.tlu.trl1.take_pmu&`SPC4.tlu.trl1.trap[1]
10752
10753`define HINTP_RDWR_37 (`TOP.nas_top.c4.t5.asi_rdwr_hintp | `TOP.nas_top.c4.t5.asi_wr_hintp_delay)
10754`define HINTP_WR_37 (`SPC4.tlu.asi_wr_hintp[37])
10755`define HSTMATCH_37 `SPC4.tlu.trl1.hstick1_compare
10756
10757`define HINTP_REG_37 `SPC4.tlu.trl1.hintp1
10758`define HSTM_TAKEN_37 `SPC4.tlu.trl1.take_hst&`SPC4.tlu.trl1.trap[1]
10759
10760`define NAS_PIPE_FW2_37 |`TOP.nas_top.c4.t5.complete_fw2
10761
10762`define CWQ_TAKEN_37 `SPC4.tlu.trl1.take_cwq&`SPC4.tlu.trl1.trap[1]
10763`define SMA_TAKEN_37 `SPC4.tlu.trl1.take_sma&`SPC4.tlu.trl1.trap[1]
10764
10765`define POR_TAKEN_37 `SPC4.tlu.trl1.take_por&`SPC4.tlu.trl1.trap[1]
10766
10767/////////////////////////////// Probes //////////////////////////////////// }}}
10768
10769always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
10770
10771 // {{{ DETECT, PIPE & SEND
10772 take_disrupting_w <= (`INT_VEC_TAKEN_37 || `CPU_MONDO_TAKEN_37 ||
10773 `DEV_MONDO_TAKEN_37 || `RES_MONDO_TAKEN_37 ||
10774 `XIR_TAKEN_37 || `INT_LEVEL_TAKEN_37 ||
10775 `HSTM_TAKEN_37 || `CWQ_TAKEN_37 ||
10776 `SMA_TAKEN_37 || `PMU_TAKEN_37 || `POR_TAKEN_37);
10777 take_disrupting_fx4 <= take_disrupting_w;
10778 take_disrupting_fx5 <= take_disrupting_fx4;
10779 take_disrupting_fb <= take_disrupting_fx5;
10780 take_disrupting_fw <= take_disrupting_fb;
10781 take_disrupting_fw1 <= take_disrupting_fw;
10782 take_disrupting_fw2 <= take_disrupting_fw1;
10783
10784 case ({`INT_VEC_TAKEN_37, `CPU_MONDO_TAKEN_37,
10785 `DEV_MONDO_TAKEN_37, `RES_MONDO_TAKEN_37,
10786 `XIR_TAKEN_37, `INT_LEVEL_TAKEN_37,
10787 `HSTM_TAKEN_37, `CWQ_TAKEN_37, `SMA_TAKEN_37 ,
10788 `PMU_TAKEN_37, `POR_TAKEN_37})
10789 11'b10000000000: int_num_w <= 8'h60;
10790 11'b01000000000: int_num_w <= 8'h7c;
10791 11'b00100000000: int_num_w <= 8'h7d;
10792 11'b00010000000: int_num_w <= 8'h7e;
10793 11'b00001000000: int_num_w <= 8'h03;
10794 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_37;
10795 11'b00000010000: int_num_w <= 8'h5e;
10796 11'b00000001000: int_num_w <= 8'h3c;
10797 11'b00000000100: int_num_w <= 8'h3d;
10798 11'b00000000010: int_num_w <= 8'h4f;
10799 11'b00000000001: int_num_w <= 8'h01;
10800 endcase
10801
10802 int_num_fx4 <= int_num_w;
10803 int_num_fx5 <= int_num_fx4;
10804 int_num_fb <= int_num_fx5;
10805 int_num_fw <= int_num_fb;
10806 int_num_fw1 <= int_num_fw;
10807 int_num_fw2 <= int_num_fw1;
10808 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
10809 begin // {
10810 `PR_INFO ("pli_int", `INFO,
10811 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
10812 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
10813 end // }
10814
10815 // }}}
10816
10817/////////////////////////// Vectored Interrupt /////////////////////////// {{{
10818
10819 // Vectored Interrupt Recv Register Detection
10820 // Indicate when register changes due to arriving interrupt, and not
10821 // due to read of incoming register or ASI write ..
10822
10823
10824 // If any read occurs, send value right away.
10825 // While a read/write is pending, do not update delta.
10826 // Send non read/wr delta during fw2 ..
10827
10828
10829 if (!(`INT_VEC_RDWR_37 | `INT_VEC_RECV_ASIWR_37)) begin // {
10830 if (~`INT_VEC_RECV_ASIWR_37 &
10831 (int_vec_recv_reg !== `INT_VEC_RECV_REG_37 ))
10832 int_vec_recv_reg_delta <= 1'b1;
10833 int_vec_recv_reg <= `INT_VEC_RECV_REG_37;
10834 end // }
10835 else if (`INT_VEC_RECV_ASIWR_37)
10836 int_vec_recv_reg <= `TOP.nas_top.c4.t5.asi_updated_int_rec;
10837
10838 if ((`NAS_PIPE_FW2_37 & int_vec_recv_reg_delta ) |
10839 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
10840 `INT_VEC_RECV_ASIWR_37 ) begin // {
10841 `PR_INFO ("pli_int", `INFO,
10842 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
10843 mycid,mytid, int_vec_recv_reg);
10844 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10845 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
10846 64'h0, int_vec_recv_reg);
10847 end // }
10848 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_37 &
10849 (int_vec_recv_reg !== `INT_VEC_RECV_REG_37 ))))
10850 int_vec_recv_reg_delta <= 1'b0;
10851 end //}
10852
10853 int_vec_reg_rdwr <= `INT_VEC_RDWR_37 | `INT_VEC_RECV_ASIWR_37;
10854 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_37 & ~ inc_vec_reg_rd;
10855
10856 if (`INT_VEC_RECV_ASIWR_37)
10857 inc_vec_reg_rd <= 1'b1;
10858 if (`NAS_PIPE_FW2_37)
10859 inc_vec_reg_rd <= 1'b0;
10860
10861
10862/////////////////////////// Vectored Interrupt /////////////////////////// }}}
10863
10864/////////////////////////// Asynchronous Resets ////////////////////////// {{{
10865
10866
10867/////////////////////////// Asynchronous Resets ////////////////////////// }}}
10868
10869/////////////////////////// Softint ///////////////////////////////////// {{{
10870
10871 // Softint Register hardware Update Detection
10872
10873 // Non software updates (TM/SM)
10874
10875 // If any read occurs, send value right away.
10876 // While a read/write is pending, do not update delta.
10877 // Send non read/wr delta during fw2 ..
10878
10879 // RTL keeps pic_ovf indication in rd_softint and not softint.
10880 // So for set/clear writes, we send softint before the write ..,
10881 // and for read/asyncs we send rd_softint ..
10882
10883
10884 if (~`SOFTINT_RDWR_37) begin // {
10885 if (softint !== `RD_SOFTINT_REG_37 )
10886 softint_delta <= 1'b1;
10887 softint <= `RD_SOFTINT_REG_37;
10888 end // }
10889
10890 if ((`NAS_PIPE_FW2_37 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
10891 ) begin // {
10892 `PR_INFO ("pli_int", `INFO,
10893 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10894 mycid,mytid, {47'h0, softint});
10895 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10896 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10897 {47'h0, softint});
10898 end // }
10899 if (!(~`SOFTINT_RDWR_37&(softint !== `RD_SOFTINT_REG_37)))
10900 softint_delta <= 1'b0;
10901 end //}
10902 else if (`SPC4.tlu.asi_wr_clear_softint[5] |
10903 `SPC4.tlu.asi_wr_set_softint[5] ) begin // {
10904 `PR_INFO ("pli_int", `INFO,
10905 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
10906 mycid,mytid, {47'h0, `RD_SOFTINT_REG_37});
10907 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10908 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
10909 {47'h0, `RD_SOFTINT_REG_37});
10910 end // }
10911 end //}
10912
10913
10914 softint_rdwr <= `SOFTINT_RDWR_37 ;
10915 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_37;
10916
10917
10918/////////////////////////// Softint ///////////////////////////////////// }}}
10919
10920/////////////////////////// Hintp ///////////////////////////////////// {{{
10921
10922 // Hintp Register hardware Update Detection
10923
10924 // Non software updates (HSP)
10925 // If HINTP is already read/written by SW, then don't send
10926 // any async updates to Nas. Reads/Writes pending sstep is detected
10927 // by snooping nas_pipe ..
10928
10929 hintp <= `HINTP_REG_37 ;
10930 if (hstmatch_late)
10931 hintp_delta <= 1'b1;
10932
10933 if ((~hintp_rdwr & `NAS_PIPE_FW2_37 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
10934 (hintp_rdwr_late & hintp_delta) ) begin // {
10935 `PR_INFO ("pli_int", `INFO,
10936 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
10937 mycid,mytid, {63'h0, hintp});
10938 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
10939 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
10940 {63'h0, hintp});
10941 end // }
10942 if (~(hintp_rdwr_late & hintp_delta))
10943 hintp_delta <= 1'b0;
10944 end //}
10945
10946 hintp_rdwr <= `HINTP_RDWR_37;
10947 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_37;
10948 hstmatch_late <= `HSTMATCH_37;
10949
10950
10951/////////////////////////// Hintp ///////////////////////////////////// }}}
10952
10953end //}
10954`endif
10955endmodule
10956
10957// }}}
10958
10959module int_c4t6 ();
10960`ifndef GATESIM
10961
10962// common defines
10963`include "defines.vh"
10964`include "ccx.vri"
10965`include "cmp.vri"
10966
10967wire [2:0] mycid;
10968wire [2:0] mytid;
10969wire [5:0] mytnum;
10970integer junk;
10971
10972reg [63:0] int_vec_recv_reg;
10973reg int_vec_recv_reg_delta;
10974reg int_vec_reg_rdwr;
10975reg inc_vec_reg_rd;
10976reg int_vec_reg_rdwr_late;
10977reg [16:0] softint;
10978reg softint_rdwr;
10979reg softint_rdwr_late;
10980reg softint_delta;
10981reg hintp;
10982reg hintp_rdwr;
10983reg hintp_rdwr_late;
10984reg hintp_delta;
10985reg hstmatch_late;
10986reg ready;
10987reg [7:0] int_num_w;
10988reg [7:0] int_num_fx4;
10989reg [7:0] int_num_fx5;
10990reg [7:0] int_num_fb;
10991reg [7:0] int_num_fw;
10992reg [7:0] int_num_fw1;
10993reg [7:0] int_num_fw2;
10994reg take_disrupting_w;
10995reg take_disrupting_fx4;
10996reg take_disrupting_fx5;
10997reg take_disrupting_fb;
10998reg take_disrupting_fw;
10999reg take_disrupting_fw1;
11000reg take_disrupting_fw2;
11001
11002 assign mycid = 4;
11003 assign mytid = 6;
11004 assign mytnum = 4*8 + 6;
11005
11006initial begin // {
11007 ready = 0; // Wait for socket setup ..
11008 inc_vec_reg_rd <= 1'b0;
11009 int_vec_recv_reg_delta <= 1'b0;
11010 softint_delta <= 1'b0;
11011 hintp_delta <= 1'b0;
11012 int_vec_recv_reg = 64'b0;
11013 @(posedge `BENCH_SPC4_GCLK) ;
11014 @(posedge `BENCH_SPC4_GCLK) ;
11015 ready = `PARGS.int_sync_on;
11016end //}
11017
11018
11019/////////////////////////////// Probes //////////////////////////////////// {{{
11020
11021`define INT_VEC_RECV_REG_38 `SPC4.tlu.cth.int_rec6
11022`define INT_VEC_RECV_ASIWR_38 (`TOP.nas_top.c4.t6.asi_wr_int_rec_delay)
11023`define INT_VEC_RDWR_38 (`TOP.nas_top.c4.t6.asi_rdwr_int_rec)
11024`define INT_VEC_TAKEN_38 `SPC4.tlu.trl1.take_ivt&`SPC4.tlu.trl1.trap[2]
11025
11026`define CPU_MONDO_TAKEN_38 `SPC4.tlu.trl1.take_mqr&`SPC4.tlu.trl1.trap[2]
11027`define DEV_MONDO_TAKEN_38 `SPC4.tlu.trl1.take_dqr&`SPC4.tlu.trl1.trap[2]
11028`define RES_MONDO_TAKEN_38 `SPC4.tlu.trl1.take_rqr&`SPC4.tlu.trl1.trap[2]
11029
11030`define XIR_TAKEN_38 `SPC4.tlu.trl1.take_xir&`SPC4.tlu.trl1.trap[2]
11031
11032`define SOFTINT_RDWR_38 (`TOP.nas_top.c4.t6.asi_rdwr_softint|`TOP.nas_top.c4.t6.asi_wr_softint_delay)
11033
11034`define SOFTINT_REG_38 `SPC4.tlu.trl1.softint2
11035`define RD_SOFTINT_REG_38 `SPC4.tlu.trl1.rd_softint2
11036`define INT_LEVEL_TAKEN_38 `SPC4.tlu.trl1.take_iln&`SPC4.tlu.trl1.trap[2]
11037`define INT_LEVEL_NUM_38 `SPC4.tlu.trl1.int_level_n
11038`define PMU_TAKEN_38 `SPC4.tlu.trl1.take_pmu&`SPC4.tlu.trl1.trap[2]
11039
11040`define HINTP_RDWR_38 (`TOP.nas_top.c4.t6.asi_rdwr_hintp | `TOP.nas_top.c4.t6.asi_wr_hintp_delay)
11041`define HINTP_WR_38 (`SPC4.tlu.asi_wr_hintp[38])
11042`define HSTMATCH_38 `SPC4.tlu.trl1.hstick2_compare
11043
11044`define HINTP_REG_38 `SPC4.tlu.trl1.hintp2
11045`define HSTM_TAKEN_38 `SPC4.tlu.trl1.take_hst&`SPC4.tlu.trl1.trap[2]
11046
11047`define NAS_PIPE_FW2_38 |`TOP.nas_top.c4.t6.complete_fw2
11048
11049`define CWQ_TAKEN_38 `SPC4.tlu.trl1.take_cwq&`SPC4.tlu.trl1.trap[2]
11050`define SMA_TAKEN_38 `SPC4.tlu.trl1.take_sma&`SPC4.tlu.trl1.trap[2]
11051
11052`define POR_TAKEN_38 `SPC4.tlu.trl1.take_por&`SPC4.tlu.trl1.trap[2]
11053
11054/////////////////////////////// Probes //////////////////////////////////// }}}
11055
11056always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
11057
11058 // {{{ DETECT, PIPE & SEND
11059 take_disrupting_w <= (`INT_VEC_TAKEN_38 || `CPU_MONDO_TAKEN_38 ||
11060 `DEV_MONDO_TAKEN_38 || `RES_MONDO_TAKEN_38 ||
11061 `XIR_TAKEN_38 || `INT_LEVEL_TAKEN_38 ||
11062 `HSTM_TAKEN_38 || `CWQ_TAKEN_38 ||
11063 `SMA_TAKEN_38 || `PMU_TAKEN_38 || `POR_TAKEN_38);
11064 take_disrupting_fx4 <= take_disrupting_w;
11065 take_disrupting_fx5 <= take_disrupting_fx4;
11066 take_disrupting_fb <= take_disrupting_fx5;
11067 take_disrupting_fw <= take_disrupting_fb;
11068 take_disrupting_fw1 <= take_disrupting_fw;
11069 take_disrupting_fw2 <= take_disrupting_fw1;
11070
11071 case ({`INT_VEC_TAKEN_38, `CPU_MONDO_TAKEN_38,
11072 `DEV_MONDO_TAKEN_38, `RES_MONDO_TAKEN_38,
11073 `XIR_TAKEN_38, `INT_LEVEL_TAKEN_38,
11074 `HSTM_TAKEN_38, `CWQ_TAKEN_38, `SMA_TAKEN_38 ,
11075 `PMU_TAKEN_38, `POR_TAKEN_38})
11076 11'b10000000000: int_num_w <= 8'h60;
11077 11'b01000000000: int_num_w <= 8'h7c;
11078 11'b00100000000: int_num_w <= 8'h7d;
11079 11'b00010000000: int_num_w <= 8'h7e;
11080 11'b00001000000: int_num_w <= 8'h03;
11081 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_38;
11082 11'b00000010000: int_num_w <= 8'h5e;
11083 11'b00000001000: int_num_w <= 8'h3c;
11084 11'b00000000100: int_num_w <= 8'h3d;
11085 11'b00000000010: int_num_w <= 8'h4f;
11086 11'b00000000001: int_num_w <= 8'h01;
11087 endcase
11088
11089 int_num_fx4 <= int_num_w;
11090 int_num_fx5 <= int_num_fx4;
11091 int_num_fb <= int_num_fx5;
11092 int_num_fw <= int_num_fb;
11093 int_num_fw1 <= int_num_fw;
11094 int_num_fw2 <= int_num_fw1;
11095 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
11096 begin // {
11097 `PR_INFO ("pli_int", `INFO,
11098 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
11099 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11100 end // }
11101
11102 // }}}
11103
11104/////////////////////////// Vectored Interrupt /////////////////////////// {{{
11105
11106 // Vectored Interrupt Recv Register Detection
11107 // Indicate when register changes due to arriving interrupt, and not
11108 // due to read of incoming register or ASI write ..
11109
11110
11111 // If any read occurs, send value right away.
11112 // While a read/write is pending, do not update delta.
11113 // Send non read/wr delta during fw2 ..
11114
11115
11116 if (!(`INT_VEC_RDWR_38 | `INT_VEC_RECV_ASIWR_38)) begin // {
11117 if (~`INT_VEC_RECV_ASIWR_38 &
11118 (int_vec_recv_reg !== `INT_VEC_RECV_REG_38 ))
11119 int_vec_recv_reg_delta <= 1'b1;
11120 int_vec_recv_reg <= `INT_VEC_RECV_REG_38;
11121 end // }
11122 else if (`INT_VEC_RECV_ASIWR_38)
11123 int_vec_recv_reg <= `TOP.nas_top.c4.t6.asi_updated_int_rec;
11124
11125 if ((`NAS_PIPE_FW2_38 & int_vec_recv_reg_delta ) |
11126 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
11127 `INT_VEC_RECV_ASIWR_38 ) begin // {
11128 `PR_INFO ("pli_int", `INFO,
11129 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
11130 mycid,mytid, int_vec_recv_reg);
11131 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11132 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
11133 64'h0, int_vec_recv_reg);
11134 end // }
11135 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_38 &
11136 (int_vec_recv_reg !== `INT_VEC_RECV_REG_38 ))))
11137 int_vec_recv_reg_delta <= 1'b0;
11138 end //}
11139
11140 int_vec_reg_rdwr <= `INT_VEC_RDWR_38 | `INT_VEC_RECV_ASIWR_38;
11141 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_38 & ~ inc_vec_reg_rd;
11142
11143 if (`INT_VEC_RECV_ASIWR_38)
11144 inc_vec_reg_rd <= 1'b1;
11145 if (`NAS_PIPE_FW2_38)
11146 inc_vec_reg_rd <= 1'b0;
11147
11148
11149/////////////////////////// Vectored Interrupt /////////////////////////// }}}
11150
11151/////////////////////////// Asynchronous Resets ////////////////////////// {{{
11152
11153
11154/////////////////////////// Asynchronous Resets ////////////////////////// }}}
11155
11156/////////////////////////// Softint ///////////////////////////////////// {{{
11157
11158 // Softint Register hardware Update Detection
11159
11160 // Non software updates (TM/SM)
11161
11162 // If any read occurs, send value right away.
11163 // While a read/write is pending, do not update delta.
11164 // Send non read/wr delta during fw2 ..
11165
11166 // RTL keeps pic_ovf indication in rd_softint and not softint.
11167 // So for set/clear writes, we send softint before the write ..,
11168 // and for read/asyncs we send rd_softint ..
11169
11170
11171 if (~`SOFTINT_RDWR_38) begin // {
11172 if (softint !== `RD_SOFTINT_REG_38 )
11173 softint_delta <= 1'b1;
11174 softint <= `RD_SOFTINT_REG_38;
11175 end // }
11176
11177 if ((`NAS_PIPE_FW2_38 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
11178 ) begin // {
11179 `PR_INFO ("pli_int", `INFO,
11180 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
11181 mycid,mytid, {47'h0, softint});
11182 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11183 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
11184 {47'h0, softint});
11185 end // }
11186 if (!(~`SOFTINT_RDWR_38&(softint !== `RD_SOFTINT_REG_38)))
11187 softint_delta <= 1'b0;
11188 end //}
11189 else if (`SPC4.tlu.asi_wr_clear_softint[6] |
11190 `SPC4.tlu.asi_wr_set_softint[6] ) begin // {
11191 `PR_INFO ("pli_int", `INFO,
11192 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
11193 mycid,mytid, {47'h0, `RD_SOFTINT_REG_38});
11194 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11195 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
11196 {47'h0, `RD_SOFTINT_REG_38});
11197 end // }
11198 end //}
11199
11200
11201 softint_rdwr <= `SOFTINT_RDWR_38 ;
11202 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_38;
11203
11204
11205/////////////////////////// Softint ///////////////////////////////////// }}}
11206
11207/////////////////////////// Hintp ///////////////////////////////////// {{{
11208
11209 // Hintp Register hardware Update Detection
11210
11211 // Non software updates (HSP)
11212 // If HINTP is already read/written by SW, then don't send
11213 // any async updates to Nas. Reads/Writes pending sstep is detected
11214 // by snooping nas_pipe ..
11215
11216 hintp <= `HINTP_REG_38 ;
11217 if (hstmatch_late)
11218 hintp_delta <= 1'b1;
11219
11220 if ((~hintp_rdwr & `NAS_PIPE_FW2_38 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
11221 (hintp_rdwr_late & hintp_delta) ) begin // {
11222 `PR_INFO ("pli_int", `INFO,
11223 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
11224 mycid,mytid, {63'h0, hintp});
11225 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11226 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
11227 {63'h0, hintp});
11228 end // }
11229 if (~(hintp_rdwr_late & hintp_delta))
11230 hintp_delta <= 1'b0;
11231 end //}
11232
11233 hintp_rdwr <= `HINTP_RDWR_38;
11234 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_38;
11235 hstmatch_late <= `HSTMATCH_38;
11236
11237
11238/////////////////////////// Hintp ///////////////////////////////////// }}}
11239
11240end //}
11241`endif
11242endmodule
11243
11244// }}}
11245
11246module int_c4t7 ();
11247`ifndef GATESIM
11248
11249// common defines
11250`include "defines.vh"
11251`include "ccx.vri"
11252`include "cmp.vri"
11253
11254wire [2:0] mycid;
11255wire [2:0] mytid;
11256wire [5:0] mytnum;
11257integer junk;
11258
11259reg [63:0] int_vec_recv_reg;
11260reg int_vec_recv_reg_delta;
11261reg int_vec_reg_rdwr;
11262reg inc_vec_reg_rd;
11263reg int_vec_reg_rdwr_late;
11264reg [16:0] softint;
11265reg softint_rdwr;
11266reg softint_rdwr_late;
11267reg softint_delta;
11268reg hintp;
11269reg hintp_rdwr;
11270reg hintp_rdwr_late;
11271reg hintp_delta;
11272reg hstmatch_late;
11273reg ready;
11274reg [7:0] int_num_w;
11275reg [7:0] int_num_fx4;
11276reg [7:0] int_num_fx5;
11277reg [7:0] int_num_fb;
11278reg [7:0] int_num_fw;
11279reg [7:0] int_num_fw1;
11280reg [7:0] int_num_fw2;
11281reg take_disrupting_w;
11282reg take_disrupting_fx4;
11283reg take_disrupting_fx5;
11284reg take_disrupting_fb;
11285reg take_disrupting_fw;
11286reg take_disrupting_fw1;
11287reg take_disrupting_fw2;
11288
11289 assign mycid = 4;
11290 assign mytid = 7;
11291 assign mytnum = 4*8 + 7;
11292
11293initial begin // {
11294 ready = 0; // Wait for socket setup ..
11295 inc_vec_reg_rd <= 1'b0;
11296 int_vec_recv_reg_delta <= 1'b0;
11297 softint_delta <= 1'b0;
11298 hintp_delta <= 1'b0;
11299 int_vec_recv_reg = 64'b0;
11300 @(posedge `BENCH_SPC4_GCLK) ;
11301 @(posedge `BENCH_SPC4_GCLK) ;
11302 ready = `PARGS.int_sync_on;
11303end //}
11304
11305
11306/////////////////////////////// Probes //////////////////////////////////// {{{
11307
11308`define INT_VEC_RECV_REG_39 `SPC4.tlu.cth.int_rec7
11309`define INT_VEC_RECV_ASIWR_39 (`TOP.nas_top.c4.t7.asi_wr_int_rec_delay)
11310`define INT_VEC_RDWR_39 (`TOP.nas_top.c4.t7.asi_rdwr_int_rec)
11311`define INT_VEC_TAKEN_39 `SPC4.tlu.trl1.take_ivt&`SPC4.tlu.trl1.trap[3]
11312
11313`define CPU_MONDO_TAKEN_39 `SPC4.tlu.trl1.take_mqr&`SPC4.tlu.trl1.trap[3]
11314`define DEV_MONDO_TAKEN_39 `SPC4.tlu.trl1.take_dqr&`SPC4.tlu.trl1.trap[3]
11315`define RES_MONDO_TAKEN_39 `SPC4.tlu.trl1.take_rqr&`SPC4.tlu.trl1.trap[3]
11316
11317`define XIR_TAKEN_39 `SPC4.tlu.trl1.take_xir&`SPC4.tlu.trl1.trap[3]
11318
11319`define SOFTINT_RDWR_39 (`TOP.nas_top.c4.t7.asi_rdwr_softint|`TOP.nas_top.c4.t7.asi_wr_softint_delay)
11320
11321`define SOFTINT_REG_39 `SPC4.tlu.trl1.softint3
11322`define RD_SOFTINT_REG_39 `SPC4.tlu.trl1.rd_softint3
11323`define INT_LEVEL_TAKEN_39 `SPC4.tlu.trl1.take_iln&`SPC4.tlu.trl1.trap[3]
11324`define INT_LEVEL_NUM_39 `SPC4.tlu.trl1.int_level_n
11325`define PMU_TAKEN_39 `SPC4.tlu.trl1.take_pmu&`SPC4.tlu.trl1.trap[3]
11326
11327`define HINTP_RDWR_39 (`TOP.nas_top.c4.t7.asi_rdwr_hintp | `TOP.nas_top.c4.t7.asi_wr_hintp_delay)
11328`define HINTP_WR_39 (`SPC4.tlu.asi_wr_hintp[39])
11329`define HSTMATCH_39 `SPC4.tlu.trl1.hstick3_compare
11330
11331`define HINTP_REG_39 `SPC4.tlu.trl1.hintp3
11332`define HSTM_TAKEN_39 `SPC4.tlu.trl1.take_hst&`SPC4.tlu.trl1.trap[3]
11333
11334`define NAS_PIPE_FW2_39 |`TOP.nas_top.c4.t7.complete_fw2
11335
11336`define CWQ_TAKEN_39 `SPC4.tlu.trl1.take_cwq&`SPC4.tlu.trl1.trap[3]
11337`define SMA_TAKEN_39 `SPC4.tlu.trl1.take_sma&`SPC4.tlu.trl1.trap[3]
11338
11339`define POR_TAKEN_39 `SPC4.tlu.trl1.take_por&`SPC4.tlu.trl1.trap[3]
11340
11341/////////////////////////////// Probes //////////////////////////////////// }}}
11342
11343always @(negedge (`BENCH_SPC4_GCLK & ready)) begin // {
11344
11345 // {{{ DETECT, PIPE & SEND
11346 take_disrupting_w <= (`INT_VEC_TAKEN_39 || `CPU_MONDO_TAKEN_39 ||
11347 `DEV_MONDO_TAKEN_39 || `RES_MONDO_TAKEN_39 ||
11348 `XIR_TAKEN_39 || `INT_LEVEL_TAKEN_39 ||
11349 `HSTM_TAKEN_39 || `CWQ_TAKEN_39 ||
11350 `SMA_TAKEN_39 || `PMU_TAKEN_39 || `POR_TAKEN_39);
11351 take_disrupting_fx4 <= take_disrupting_w;
11352 take_disrupting_fx5 <= take_disrupting_fx4;
11353 take_disrupting_fb <= take_disrupting_fx5;
11354 take_disrupting_fw <= take_disrupting_fb;
11355 take_disrupting_fw1 <= take_disrupting_fw;
11356 take_disrupting_fw2 <= take_disrupting_fw1;
11357
11358 case ({`INT_VEC_TAKEN_39, `CPU_MONDO_TAKEN_39,
11359 `DEV_MONDO_TAKEN_39, `RES_MONDO_TAKEN_39,
11360 `XIR_TAKEN_39, `INT_LEVEL_TAKEN_39,
11361 `HSTM_TAKEN_39, `CWQ_TAKEN_39, `SMA_TAKEN_39 ,
11362 `PMU_TAKEN_39, `POR_TAKEN_39})
11363 11'b10000000000: int_num_w <= 8'h60;
11364 11'b01000000000: int_num_w <= 8'h7c;
11365 11'b00100000000: int_num_w <= 8'h7d;
11366 11'b00010000000: int_num_w <= 8'h7e;
11367 11'b00001000000: int_num_w <= 8'h03;
11368 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_39;
11369 11'b00000010000: int_num_w <= 8'h5e;
11370 11'b00000001000: int_num_w <= 8'h3c;
11371 11'b00000000100: int_num_w <= 8'h3d;
11372 11'b00000000010: int_num_w <= 8'h4f;
11373 11'b00000000001: int_num_w <= 8'h01;
11374 endcase
11375
11376 int_num_fx4 <= int_num_w;
11377 int_num_fx5 <= int_num_fx4;
11378 int_num_fb <= int_num_fx5;
11379 int_num_fw <= int_num_fb;
11380 int_num_fw1 <= int_num_fw;
11381 int_num_fw2 <= int_num_fw1;
11382 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
11383 begin // {
11384 `PR_INFO ("pli_int", `INFO,
11385 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
11386 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11387 end // }
11388
11389 // }}}
11390
11391/////////////////////////// Vectored Interrupt /////////////////////////// {{{
11392
11393 // Vectored Interrupt Recv Register Detection
11394 // Indicate when register changes due to arriving interrupt, and not
11395 // due to read of incoming register or ASI write ..
11396
11397
11398 // If any read occurs, send value right away.
11399 // While a read/write is pending, do not update delta.
11400 // Send non read/wr delta during fw2 ..
11401
11402
11403 if (!(`INT_VEC_RDWR_39 | `INT_VEC_RECV_ASIWR_39)) begin // {
11404 if (~`INT_VEC_RECV_ASIWR_39 &
11405 (int_vec_recv_reg !== `INT_VEC_RECV_REG_39 ))
11406 int_vec_recv_reg_delta <= 1'b1;
11407 int_vec_recv_reg <= `INT_VEC_RECV_REG_39;
11408 end // }
11409 else if (`INT_VEC_RECV_ASIWR_39)
11410 int_vec_recv_reg <= `TOP.nas_top.c4.t7.asi_updated_int_rec;
11411
11412 if ((`NAS_PIPE_FW2_39 & int_vec_recv_reg_delta ) |
11413 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
11414 `INT_VEC_RECV_ASIWR_39 ) begin // {
11415 `PR_INFO ("pli_int", `INFO,
11416 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
11417 mycid,mytid, int_vec_recv_reg);
11418 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11419 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
11420 64'h0, int_vec_recv_reg);
11421 end // }
11422 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_39 &
11423 (int_vec_recv_reg !== `INT_VEC_RECV_REG_39 ))))
11424 int_vec_recv_reg_delta <= 1'b0;
11425 end //}
11426
11427 int_vec_reg_rdwr <= `INT_VEC_RDWR_39 | `INT_VEC_RECV_ASIWR_39;
11428 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_39 & ~ inc_vec_reg_rd;
11429
11430 if (`INT_VEC_RECV_ASIWR_39)
11431 inc_vec_reg_rd <= 1'b1;
11432 if (`NAS_PIPE_FW2_39)
11433 inc_vec_reg_rd <= 1'b0;
11434
11435
11436/////////////////////////// Vectored Interrupt /////////////////////////// }}}
11437
11438/////////////////////////// Asynchronous Resets ////////////////////////// {{{
11439
11440
11441/////////////////////////// Asynchronous Resets ////////////////////////// }}}
11442
11443/////////////////////////// Softint ///////////////////////////////////// {{{
11444
11445 // Softint Register hardware Update Detection
11446
11447 // Non software updates (TM/SM)
11448
11449 // If any read occurs, send value right away.
11450 // While a read/write is pending, do not update delta.
11451 // Send non read/wr delta during fw2 ..
11452
11453 // RTL keeps pic_ovf indication in rd_softint and not softint.
11454 // So for set/clear writes, we send softint before the write ..,
11455 // and for read/asyncs we send rd_softint ..
11456
11457
11458 if (~`SOFTINT_RDWR_39) begin // {
11459 if (softint !== `RD_SOFTINT_REG_39 )
11460 softint_delta <= 1'b1;
11461 softint <= `RD_SOFTINT_REG_39;
11462 end // }
11463
11464 if ((`NAS_PIPE_FW2_39 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
11465 ) begin // {
11466 `PR_INFO ("pli_int", `INFO,
11467 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
11468 mycid,mytid, {47'h0, softint});
11469 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11470 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
11471 {47'h0, softint});
11472 end // }
11473 if (!(~`SOFTINT_RDWR_39&(softint !== `RD_SOFTINT_REG_39)))
11474 softint_delta <= 1'b0;
11475 end //}
11476 else if (`SPC4.tlu.asi_wr_clear_softint[7] |
11477 `SPC4.tlu.asi_wr_set_softint[7] ) begin // {
11478 `PR_INFO ("pli_int", `INFO,
11479 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
11480 mycid,mytid, {47'h0, `RD_SOFTINT_REG_39});
11481 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11482 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
11483 {47'h0, `RD_SOFTINT_REG_39});
11484 end // }
11485 end //}
11486
11487
11488 softint_rdwr <= `SOFTINT_RDWR_39 ;
11489 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_39;
11490
11491
11492/////////////////////////// Softint ///////////////////////////////////// }}}
11493
11494/////////////////////////// Hintp ///////////////////////////////////// {{{
11495
11496 // Hintp Register hardware Update Detection
11497
11498 // Non software updates (HSP)
11499 // If HINTP is already read/written by SW, then don't send
11500 // any async updates to Nas. Reads/Writes pending sstep is detected
11501 // by snooping nas_pipe ..
11502
11503 hintp <= `HINTP_REG_39 ;
11504 if (hstmatch_late)
11505 hintp_delta <= 1'b1;
11506
11507 if ((~hintp_rdwr & `NAS_PIPE_FW2_39 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
11508 (hintp_rdwr_late & hintp_delta) ) begin // {
11509 `PR_INFO ("pli_int", `INFO,
11510 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
11511 mycid,mytid, {63'h0, hintp});
11512 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11513 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
11514 {63'h0, hintp});
11515 end // }
11516 if (~(hintp_rdwr_late & hintp_delta))
11517 hintp_delta <= 1'b0;
11518 end //}
11519
11520 hintp_rdwr <= `HINTP_RDWR_39;
11521 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_39;
11522 hstmatch_late <= `HSTMATCH_39;
11523
11524
11525/////////////////////////// Hintp ///////////////////////////////////// }}}
11526
11527end //}
11528`endif
11529endmodule
11530
11531`endif
11532`ifdef CORE_5
11533
11534// }}}
11535
11536module int_c5t0 ();
11537`ifndef GATESIM
11538
11539// common defines
11540`include "defines.vh"
11541`include "ccx.vri"
11542`include "cmp.vri"
11543
11544wire [2:0] mycid;
11545wire [2:0] mytid;
11546wire [5:0] mytnum;
11547integer junk;
11548
11549reg [63:0] int_vec_recv_reg;
11550reg int_vec_recv_reg_delta;
11551reg int_vec_reg_rdwr;
11552reg inc_vec_reg_rd;
11553reg int_vec_reg_rdwr_late;
11554reg [16:0] softint;
11555reg softint_rdwr;
11556reg softint_rdwr_late;
11557reg softint_delta;
11558reg hintp;
11559reg hintp_rdwr;
11560reg hintp_rdwr_late;
11561reg hintp_delta;
11562reg hstmatch_late;
11563reg ready;
11564reg [7:0] int_num_w;
11565reg [7:0] int_num_fx4;
11566reg [7:0] int_num_fx5;
11567reg [7:0] int_num_fb;
11568reg [7:0] int_num_fw;
11569reg [7:0] int_num_fw1;
11570reg [7:0] int_num_fw2;
11571reg take_disrupting_w;
11572reg take_disrupting_fx4;
11573reg take_disrupting_fx5;
11574reg take_disrupting_fb;
11575reg take_disrupting_fw;
11576reg take_disrupting_fw1;
11577reg take_disrupting_fw2;
11578
11579 assign mycid = 5;
11580 assign mytid = 0;
11581 assign mytnum = 5*8 + 0;
11582
11583initial begin // {
11584 ready = 0; // Wait for socket setup ..
11585 inc_vec_reg_rd <= 1'b0;
11586 int_vec_recv_reg_delta <= 1'b0;
11587 softint_delta <= 1'b0;
11588 hintp_delta <= 1'b0;
11589 int_vec_recv_reg = 64'b0;
11590 @(posedge `BENCH_SPC5_GCLK) ;
11591 @(posedge `BENCH_SPC5_GCLK) ;
11592 ready = `PARGS.int_sync_on;
11593end //}
11594
11595
11596/////////////////////////////// Probes //////////////////////////////////// {{{
11597
11598`define INT_VEC_RECV_REG_40 `SPC5.tlu.cth.int_rec0
11599`define INT_VEC_RECV_ASIWR_40 (`TOP.nas_top.c5.t0.asi_wr_int_rec_delay)
11600`define INT_VEC_RDWR_40 (`TOP.nas_top.c5.t0.asi_rdwr_int_rec)
11601`define INT_VEC_TAKEN_40 `SPC5.tlu.trl0.take_ivt&`SPC5.tlu.trl0.trap[0]
11602
11603`define CPU_MONDO_TAKEN_40 `SPC5.tlu.trl0.take_mqr&`SPC5.tlu.trl0.trap[0]
11604`define DEV_MONDO_TAKEN_40 `SPC5.tlu.trl0.take_dqr&`SPC5.tlu.trl0.trap[0]
11605`define RES_MONDO_TAKEN_40 `SPC5.tlu.trl0.take_rqr&`SPC5.tlu.trl0.trap[0]
11606
11607`define XIR_TAKEN_40 `SPC5.tlu.trl0.take_xir&`SPC5.tlu.trl0.trap[0]
11608
11609`define SOFTINT_RDWR_40 (`TOP.nas_top.c5.t0.asi_rdwr_softint|`TOP.nas_top.c5.t0.asi_wr_softint_delay)
11610
11611`define SOFTINT_REG_40 `SPC5.tlu.trl0.softint0
11612`define RD_SOFTINT_REG_40 `SPC5.tlu.trl0.rd_softint0
11613`define INT_LEVEL_TAKEN_40 `SPC5.tlu.trl0.take_iln&`SPC5.tlu.trl0.trap[0]
11614`define INT_LEVEL_NUM_40 `SPC5.tlu.trl0.int_level_n
11615`define PMU_TAKEN_40 `SPC5.tlu.trl0.take_pmu&`SPC5.tlu.trl0.trap[0]
11616
11617`define HINTP_RDWR_40 (`TOP.nas_top.c5.t0.asi_rdwr_hintp | `TOP.nas_top.c5.t0.asi_wr_hintp_delay)
11618`define HINTP_WR_40 (`SPC5.tlu.asi_wr_hintp[40])
11619`define HSTMATCH_40 `SPC5.tlu.trl0.hstick0_compare
11620
11621`define HINTP_REG_40 `SPC5.tlu.trl0.hintp0
11622`define HSTM_TAKEN_40 `SPC5.tlu.trl0.take_hst&`SPC5.tlu.trl0.trap[0]
11623
11624`define NAS_PIPE_FW2_40 |`TOP.nas_top.c5.t0.complete_fw2
11625
11626`define CWQ_TAKEN_40 `SPC5.tlu.trl0.take_cwq&`SPC5.tlu.trl0.trap[0]
11627`define SMA_TAKEN_40 `SPC5.tlu.trl0.take_sma&`SPC5.tlu.trl0.trap[0]
11628
11629`define POR_TAKEN_40 `SPC5.tlu.trl0.take_por&`SPC5.tlu.trl0.trap[0]
11630
11631/////////////////////////////// Probes //////////////////////////////////// }}}
11632
11633always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
11634
11635 // {{{ DETECT, PIPE & SEND
11636 take_disrupting_w <= (`INT_VEC_TAKEN_40 || `CPU_MONDO_TAKEN_40 ||
11637 `DEV_MONDO_TAKEN_40 || `RES_MONDO_TAKEN_40 ||
11638 `XIR_TAKEN_40 || `INT_LEVEL_TAKEN_40 ||
11639 `HSTM_TAKEN_40 || `CWQ_TAKEN_40 ||
11640 `SMA_TAKEN_40 || `PMU_TAKEN_40 || `POR_TAKEN_40);
11641 take_disrupting_fx4 <= take_disrupting_w;
11642 take_disrupting_fx5 <= take_disrupting_fx4;
11643 take_disrupting_fb <= take_disrupting_fx5;
11644 take_disrupting_fw <= take_disrupting_fb;
11645 take_disrupting_fw1 <= take_disrupting_fw;
11646 take_disrupting_fw2 <= take_disrupting_fw1;
11647
11648 case ({`INT_VEC_TAKEN_40, `CPU_MONDO_TAKEN_40,
11649 `DEV_MONDO_TAKEN_40, `RES_MONDO_TAKEN_40,
11650 `XIR_TAKEN_40, `INT_LEVEL_TAKEN_40,
11651 `HSTM_TAKEN_40, `CWQ_TAKEN_40, `SMA_TAKEN_40 ,
11652 `PMU_TAKEN_40, `POR_TAKEN_40})
11653 11'b10000000000: int_num_w <= 8'h60;
11654 11'b01000000000: int_num_w <= 8'h7c;
11655 11'b00100000000: int_num_w <= 8'h7d;
11656 11'b00010000000: int_num_w <= 8'h7e;
11657 11'b00001000000: int_num_w <= 8'h03;
11658 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_40;
11659 11'b00000010000: int_num_w <= 8'h5e;
11660 11'b00000001000: int_num_w <= 8'h3c;
11661 11'b00000000100: int_num_w <= 8'h3d;
11662 11'b00000000010: int_num_w <= 8'h4f;
11663 11'b00000000001: int_num_w <= 8'h01;
11664 endcase
11665
11666 int_num_fx4 <= int_num_w;
11667 int_num_fx5 <= int_num_fx4;
11668 int_num_fb <= int_num_fx5;
11669 int_num_fw <= int_num_fb;
11670 int_num_fw1 <= int_num_fw;
11671 int_num_fw2 <= int_num_fw1;
11672 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
11673 begin // {
11674 `PR_INFO ("pli_int", `INFO,
11675 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
11676 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11677 end // }
11678
11679 // }}}
11680
11681/////////////////////////// Vectored Interrupt /////////////////////////// {{{
11682
11683 // Vectored Interrupt Recv Register Detection
11684 // Indicate when register changes due to arriving interrupt, and not
11685 // due to read of incoming register or ASI write ..
11686
11687
11688 // If any read occurs, send value right away.
11689 // While a read/write is pending, do not update delta.
11690 // Send non read/wr delta during fw2 ..
11691
11692
11693 if (!(`INT_VEC_RDWR_40 | `INT_VEC_RECV_ASIWR_40)) begin // {
11694 if (~`INT_VEC_RECV_ASIWR_40 &
11695 (int_vec_recv_reg !== `INT_VEC_RECV_REG_40 ))
11696 int_vec_recv_reg_delta <= 1'b1;
11697 int_vec_recv_reg <= `INT_VEC_RECV_REG_40;
11698 end // }
11699 else if (`INT_VEC_RECV_ASIWR_40)
11700 int_vec_recv_reg <= `TOP.nas_top.c5.t0.asi_updated_int_rec;
11701
11702 if ((`NAS_PIPE_FW2_40 & int_vec_recv_reg_delta ) |
11703 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
11704 `INT_VEC_RECV_ASIWR_40 ) begin // {
11705 `PR_INFO ("pli_int", `INFO,
11706 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
11707 mycid,mytid, int_vec_recv_reg);
11708 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11709 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
11710 64'h0, int_vec_recv_reg);
11711 end // }
11712 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_40 &
11713 (int_vec_recv_reg !== `INT_VEC_RECV_REG_40 ))))
11714 int_vec_recv_reg_delta <= 1'b0;
11715 end //}
11716
11717 int_vec_reg_rdwr <= `INT_VEC_RDWR_40 | `INT_VEC_RECV_ASIWR_40;
11718 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_40 & ~ inc_vec_reg_rd;
11719
11720 if (`INT_VEC_RECV_ASIWR_40)
11721 inc_vec_reg_rd <= 1'b1;
11722 if (`NAS_PIPE_FW2_40)
11723 inc_vec_reg_rd <= 1'b0;
11724
11725
11726/////////////////////////// Vectored Interrupt /////////////////////////// }}}
11727
11728/////////////////////////// Asynchronous Resets ////////////////////////// {{{
11729
11730
11731/////////////////////////// Asynchronous Resets ////////////////////////// }}}
11732
11733/////////////////////////// Softint ///////////////////////////////////// {{{
11734
11735 // Softint Register hardware Update Detection
11736
11737 // Non software updates (TM/SM)
11738
11739 // If any read occurs, send value right away.
11740 // While a read/write is pending, do not update delta.
11741 // Send non read/wr delta during fw2 ..
11742
11743 // RTL keeps pic_ovf indication in rd_softint and not softint.
11744 // So for set/clear writes, we send softint before the write ..,
11745 // and for read/asyncs we send rd_softint ..
11746
11747
11748 if (~`SOFTINT_RDWR_40) begin // {
11749 if (softint !== `RD_SOFTINT_REG_40 )
11750 softint_delta <= 1'b1;
11751 softint <= `RD_SOFTINT_REG_40;
11752 end // }
11753
11754 if ((`NAS_PIPE_FW2_40 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
11755 ) begin // {
11756 `PR_INFO ("pli_int", `INFO,
11757 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
11758 mycid,mytid, {47'h0, softint});
11759 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11760 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
11761 {47'h0, softint});
11762 end // }
11763 if (!(~`SOFTINT_RDWR_40&(softint !== `RD_SOFTINT_REG_40)))
11764 softint_delta <= 1'b0;
11765 end //}
11766 else if (`SPC5.tlu.asi_wr_clear_softint[0] |
11767 `SPC5.tlu.asi_wr_set_softint[0] ) begin // {
11768 `PR_INFO ("pli_int", `INFO,
11769 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
11770 mycid,mytid, {47'h0, `RD_SOFTINT_REG_40});
11771 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11772 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
11773 {47'h0, `RD_SOFTINT_REG_40});
11774 end // }
11775 end //}
11776
11777
11778 softint_rdwr <= `SOFTINT_RDWR_40 ;
11779 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_40;
11780
11781
11782/////////////////////////// Softint ///////////////////////////////////// }}}
11783
11784/////////////////////////// Hintp ///////////////////////////////////// {{{
11785
11786 // Hintp Register hardware Update Detection
11787
11788 // Non software updates (HSP)
11789 // If HINTP is already read/written by SW, then don't send
11790 // any async updates to Nas. Reads/Writes pending sstep is detected
11791 // by snooping nas_pipe ..
11792
11793 hintp <= `HINTP_REG_40 ;
11794 if (hstmatch_late)
11795 hintp_delta <= 1'b1;
11796
11797 if ((~hintp_rdwr & `NAS_PIPE_FW2_40 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
11798 (hintp_rdwr_late & hintp_delta) ) begin // {
11799 `PR_INFO ("pli_int", `INFO,
11800 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
11801 mycid,mytid, {63'h0, hintp});
11802 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11803 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
11804 {63'h0, hintp});
11805 end // }
11806 if (~(hintp_rdwr_late & hintp_delta))
11807 hintp_delta <= 1'b0;
11808 end //}
11809
11810 hintp_rdwr <= `HINTP_RDWR_40;
11811 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_40;
11812 hstmatch_late <= `HSTMATCH_40;
11813
11814
11815/////////////////////////// Hintp ///////////////////////////////////// }}}
11816
11817end //}
11818`endif
11819endmodule
11820
11821// }}}
11822
11823module int_c5t1 ();
11824`ifndef GATESIM
11825
11826// common defines
11827`include "defines.vh"
11828`include "ccx.vri"
11829`include "cmp.vri"
11830
11831wire [2:0] mycid;
11832wire [2:0] mytid;
11833wire [5:0] mytnum;
11834integer junk;
11835
11836reg [63:0] int_vec_recv_reg;
11837reg int_vec_recv_reg_delta;
11838reg int_vec_reg_rdwr;
11839reg inc_vec_reg_rd;
11840reg int_vec_reg_rdwr_late;
11841reg [16:0] softint;
11842reg softint_rdwr;
11843reg softint_rdwr_late;
11844reg softint_delta;
11845reg hintp;
11846reg hintp_rdwr;
11847reg hintp_rdwr_late;
11848reg hintp_delta;
11849reg hstmatch_late;
11850reg ready;
11851reg [7:0] int_num_w;
11852reg [7:0] int_num_fx4;
11853reg [7:0] int_num_fx5;
11854reg [7:0] int_num_fb;
11855reg [7:0] int_num_fw;
11856reg [7:0] int_num_fw1;
11857reg [7:0] int_num_fw2;
11858reg take_disrupting_w;
11859reg take_disrupting_fx4;
11860reg take_disrupting_fx5;
11861reg take_disrupting_fb;
11862reg take_disrupting_fw;
11863reg take_disrupting_fw1;
11864reg take_disrupting_fw2;
11865
11866 assign mycid = 5;
11867 assign mytid = 1;
11868 assign mytnum = 5*8 + 1;
11869
11870initial begin // {
11871 ready = 0; // Wait for socket setup ..
11872 inc_vec_reg_rd <= 1'b0;
11873 int_vec_recv_reg_delta <= 1'b0;
11874 softint_delta <= 1'b0;
11875 hintp_delta <= 1'b0;
11876 int_vec_recv_reg = 64'b0;
11877 @(posedge `BENCH_SPC5_GCLK) ;
11878 @(posedge `BENCH_SPC5_GCLK) ;
11879 ready = `PARGS.int_sync_on;
11880end //}
11881
11882
11883/////////////////////////////// Probes //////////////////////////////////// {{{
11884
11885`define INT_VEC_RECV_REG_41 `SPC5.tlu.cth.int_rec1
11886`define INT_VEC_RECV_ASIWR_41 (`TOP.nas_top.c5.t1.asi_wr_int_rec_delay)
11887`define INT_VEC_RDWR_41 (`TOP.nas_top.c5.t1.asi_rdwr_int_rec)
11888`define INT_VEC_TAKEN_41 `SPC5.tlu.trl0.take_ivt&`SPC5.tlu.trl0.trap[1]
11889
11890`define CPU_MONDO_TAKEN_41 `SPC5.tlu.trl0.take_mqr&`SPC5.tlu.trl0.trap[1]
11891`define DEV_MONDO_TAKEN_41 `SPC5.tlu.trl0.take_dqr&`SPC5.tlu.trl0.trap[1]
11892`define RES_MONDO_TAKEN_41 `SPC5.tlu.trl0.take_rqr&`SPC5.tlu.trl0.trap[1]
11893
11894`define XIR_TAKEN_41 `SPC5.tlu.trl0.take_xir&`SPC5.tlu.trl0.trap[1]
11895
11896`define SOFTINT_RDWR_41 (`TOP.nas_top.c5.t1.asi_rdwr_softint|`TOP.nas_top.c5.t1.asi_wr_softint_delay)
11897
11898`define SOFTINT_REG_41 `SPC5.tlu.trl0.softint1
11899`define RD_SOFTINT_REG_41 `SPC5.tlu.trl0.rd_softint1
11900`define INT_LEVEL_TAKEN_41 `SPC5.tlu.trl0.take_iln&`SPC5.tlu.trl0.trap[1]
11901`define INT_LEVEL_NUM_41 `SPC5.tlu.trl0.int_level_n
11902`define PMU_TAKEN_41 `SPC5.tlu.trl0.take_pmu&`SPC5.tlu.trl0.trap[1]
11903
11904`define HINTP_RDWR_41 (`TOP.nas_top.c5.t1.asi_rdwr_hintp | `TOP.nas_top.c5.t1.asi_wr_hintp_delay)
11905`define HINTP_WR_41 (`SPC5.tlu.asi_wr_hintp[41])
11906`define HSTMATCH_41 `SPC5.tlu.trl0.hstick1_compare
11907
11908`define HINTP_REG_41 `SPC5.tlu.trl0.hintp1
11909`define HSTM_TAKEN_41 `SPC5.tlu.trl0.take_hst&`SPC5.tlu.trl0.trap[1]
11910
11911`define NAS_PIPE_FW2_41 |`TOP.nas_top.c5.t1.complete_fw2
11912
11913`define CWQ_TAKEN_41 `SPC5.tlu.trl0.take_cwq&`SPC5.tlu.trl0.trap[1]
11914`define SMA_TAKEN_41 `SPC5.tlu.trl0.take_sma&`SPC5.tlu.trl0.trap[1]
11915
11916`define POR_TAKEN_41 `SPC5.tlu.trl0.take_por&`SPC5.tlu.trl0.trap[1]
11917
11918/////////////////////////////// Probes //////////////////////////////////// }}}
11919
11920always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
11921
11922 // {{{ DETECT, PIPE & SEND
11923 take_disrupting_w <= (`INT_VEC_TAKEN_41 || `CPU_MONDO_TAKEN_41 ||
11924 `DEV_MONDO_TAKEN_41 || `RES_MONDO_TAKEN_41 ||
11925 `XIR_TAKEN_41 || `INT_LEVEL_TAKEN_41 ||
11926 `HSTM_TAKEN_41 || `CWQ_TAKEN_41 ||
11927 `SMA_TAKEN_41 || `PMU_TAKEN_41 || `POR_TAKEN_41);
11928 take_disrupting_fx4 <= take_disrupting_w;
11929 take_disrupting_fx5 <= take_disrupting_fx4;
11930 take_disrupting_fb <= take_disrupting_fx5;
11931 take_disrupting_fw <= take_disrupting_fb;
11932 take_disrupting_fw1 <= take_disrupting_fw;
11933 take_disrupting_fw2 <= take_disrupting_fw1;
11934
11935 case ({`INT_VEC_TAKEN_41, `CPU_MONDO_TAKEN_41,
11936 `DEV_MONDO_TAKEN_41, `RES_MONDO_TAKEN_41,
11937 `XIR_TAKEN_41, `INT_LEVEL_TAKEN_41,
11938 `HSTM_TAKEN_41, `CWQ_TAKEN_41, `SMA_TAKEN_41 ,
11939 `PMU_TAKEN_41, `POR_TAKEN_41})
11940 11'b10000000000: int_num_w <= 8'h60;
11941 11'b01000000000: int_num_w <= 8'h7c;
11942 11'b00100000000: int_num_w <= 8'h7d;
11943 11'b00010000000: int_num_w <= 8'h7e;
11944 11'b00001000000: int_num_w <= 8'h03;
11945 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_41;
11946 11'b00000010000: int_num_w <= 8'h5e;
11947 11'b00000001000: int_num_w <= 8'h3c;
11948 11'b00000000100: int_num_w <= 8'h3d;
11949 11'b00000000010: int_num_w <= 8'h4f;
11950 11'b00000000001: int_num_w <= 8'h01;
11951 endcase
11952
11953 int_num_fx4 <= int_num_w;
11954 int_num_fx5 <= int_num_fx4;
11955 int_num_fb <= int_num_fx5;
11956 int_num_fw <= int_num_fb;
11957 int_num_fw1 <= int_num_fw;
11958 int_num_fw2 <= int_num_fw1;
11959 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
11960 begin // {
11961 `PR_INFO ("pli_int", `INFO,
11962 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
11963 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
11964 end // }
11965
11966 // }}}
11967
11968/////////////////////////// Vectored Interrupt /////////////////////////// {{{
11969
11970 // Vectored Interrupt Recv Register Detection
11971 // Indicate when register changes due to arriving interrupt, and not
11972 // due to read of incoming register or ASI write ..
11973
11974
11975 // If any read occurs, send value right away.
11976 // While a read/write is pending, do not update delta.
11977 // Send non read/wr delta during fw2 ..
11978
11979
11980 if (!(`INT_VEC_RDWR_41 | `INT_VEC_RECV_ASIWR_41)) begin // {
11981 if (~`INT_VEC_RECV_ASIWR_41 &
11982 (int_vec_recv_reg !== `INT_VEC_RECV_REG_41 ))
11983 int_vec_recv_reg_delta <= 1'b1;
11984 int_vec_recv_reg <= `INT_VEC_RECV_REG_41;
11985 end // }
11986 else if (`INT_VEC_RECV_ASIWR_41)
11987 int_vec_recv_reg <= `TOP.nas_top.c5.t1.asi_updated_int_rec;
11988
11989 if ((`NAS_PIPE_FW2_41 & int_vec_recv_reg_delta ) |
11990 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
11991 `INT_VEC_RECV_ASIWR_41 ) begin // {
11992 `PR_INFO ("pli_int", `INFO,
11993 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
11994 mycid,mytid, int_vec_recv_reg);
11995 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
11996 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
11997 64'h0, int_vec_recv_reg);
11998 end // }
11999 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_41 &
12000 (int_vec_recv_reg !== `INT_VEC_RECV_REG_41 ))))
12001 int_vec_recv_reg_delta <= 1'b0;
12002 end //}
12003
12004 int_vec_reg_rdwr <= `INT_VEC_RDWR_41 | `INT_VEC_RECV_ASIWR_41;
12005 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_41 & ~ inc_vec_reg_rd;
12006
12007 if (`INT_VEC_RECV_ASIWR_41)
12008 inc_vec_reg_rd <= 1'b1;
12009 if (`NAS_PIPE_FW2_41)
12010 inc_vec_reg_rd <= 1'b0;
12011
12012
12013/////////////////////////// Vectored Interrupt /////////////////////////// }}}
12014
12015/////////////////////////// Asynchronous Resets ////////////////////////// {{{
12016
12017
12018/////////////////////////// Asynchronous Resets ////////////////////////// }}}
12019
12020/////////////////////////// Softint ///////////////////////////////////// {{{
12021
12022 // Softint Register hardware Update Detection
12023
12024 // Non software updates (TM/SM)
12025
12026 // If any read occurs, send value right away.
12027 // While a read/write is pending, do not update delta.
12028 // Send non read/wr delta during fw2 ..
12029
12030 // RTL keeps pic_ovf indication in rd_softint and not softint.
12031 // So for set/clear writes, we send softint before the write ..,
12032 // and for read/asyncs we send rd_softint ..
12033
12034
12035 if (~`SOFTINT_RDWR_41) begin // {
12036 if (softint !== `RD_SOFTINT_REG_41 )
12037 softint_delta <= 1'b1;
12038 softint <= `RD_SOFTINT_REG_41;
12039 end // }
12040
12041 if ((`NAS_PIPE_FW2_41 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
12042 ) begin // {
12043 `PR_INFO ("pli_int", `INFO,
12044 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12045 mycid,mytid, {47'h0, softint});
12046 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12047 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12048 {47'h0, softint});
12049 end // }
12050 if (!(~`SOFTINT_RDWR_41&(softint !== `RD_SOFTINT_REG_41)))
12051 softint_delta <= 1'b0;
12052 end //}
12053 else if (`SPC5.tlu.asi_wr_clear_softint[1] |
12054 `SPC5.tlu.asi_wr_set_softint[1] ) begin // {
12055 `PR_INFO ("pli_int", `INFO,
12056 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12057 mycid,mytid, {47'h0, `RD_SOFTINT_REG_41});
12058 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12059 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12060 {47'h0, `RD_SOFTINT_REG_41});
12061 end // }
12062 end //}
12063
12064
12065 softint_rdwr <= `SOFTINT_RDWR_41 ;
12066 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_41;
12067
12068
12069/////////////////////////// Softint ///////////////////////////////////// }}}
12070
12071/////////////////////////// Hintp ///////////////////////////////////// {{{
12072
12073 // Hintp Register hardware Update Detection
12074
12075 // Non software updates (HSP)
12076 // If HINTP is already read/written by SW, then don't send
12077 // any async updates to Nas. Reads/Writes pending sstep is detected
12078 // by snooping nas_pipe ..
12079
12080 hintp <= `HINTP_REG_41 ;
12081 if (hstmatch_late)
12082 hintp_delta <= 1'b1;
12083
12084 if ((~hintp_rdwr & `NAS_PIPE_FW2_41 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
12085 (hintp_rdwr_late & hintp_delta) ) begin // {
12086 `PR_INFO ("pli_int", `INFO,
12087 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
12088 mycid,mytid, {63'h0, hintp});
12089 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12090 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
12091 {63'h0, hintp});
12092 end // }
12093 if (~(hintp_rdwr_late & hintp_delta))
12094 hintp_delta <= 1'b0;
12095 end //}
12096
12097 hintp_rdwr <= `HINTP_RDWR_41;
12098 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_41;
12099 hstmatch_late <= `HSTMATCH_41;
12100
12101
12102/////////////////////////// Hintp ///////////////////////////////////// }}}
12103
12104end //}
12105`endif
12106endmodule
12107
12108// }}}
12109
12110module int_c5t2 ();
12111`ifndef GATESIM
12112
12113// common defines
12114`include "defines.vh"
12115`include "ccx.vri"
12116`include "cmp.vri"
12117
12118wire [2:0] mycid;
12119wire [2:0] mytid;
12120wire [5:0] mytnum;
12121integer junk;
12122
12123reg [63:0] int_vec_recv_reg;
12124reg int_vec_recv_reg_delta;
12125reg int_vec_reg_rdwr;
12126reg inc_vec_reg_rd;
12127reg int_vec_reg_rdwr_late;
12128reg [16:0] softint;
12129reg softint_rdwr;
12130reg softint_rdwr_late;
12131reg softint_delta;
12132reg hintp;
12133reg hintp_rdwr;
12134reg hintp_rdwr_late;
12135reg hintp_delta;
12136reg hstmatch_late;
12137reg ready;
12138reg [7:0] int_num_w;
12139reg [7:0] int_num_fx4;
12140reg [7:0] int_num_fx5;
12141reg [7:0] int_num_fb;
12142reg [7:0] int_num_fw;
12143reg [7:0] int_num_fw1;
12144reg [7:0] int_num_fw2;
12145reg take_disrupting_w;
12146reg take_disrupting_fx4;
12147reg take_disrupting_fx5;
12148reg take_disrupting_fb;
12149reg take_disrupting_fw;
12150reg take_disrupting_fw1;
12151reg take_disrupting_fw2;
12152
12153 assign mycid = 5;
12154 assign mytid = 2;
12155 assign mytnum = 5*8 + 2;
12156
12157initial begin // {
12158 ready = 0; // Wait for socket setup ..
12159 inc_vec_reg_rd <= 1'b0;
12160 int_vec_recv_reg_delta <= 1'b0;
12161 softint_delta <= 1'b0;
12162 hintp_delta <= 1'b0;
12163 int_vec_recv_reg = 64'b0;
12164 @(posedge `BENCH_SPC5_GCLK) ;
12165 @(posedge `BENCH_SPC5_GCLK) ;
12166 ready = `PARGS.int_sync_on;
12167end //}
12168
12169
12170/////////////////////////////// Probes //////////////////////////////////// {{{
12171
12172`define INT_VEC_RECV_REG_42 `SPC5.tlu.cth.int_rec2
12173`define INT_VEC_RECV_ASIWR_42 (`TOP.nas_top.c5.t2.asi_wr_int_rec_delay)
12174`define INT_VEC_RDWR_42 (`TOP.nas_top.c5.t2.asi_rdwr_int_rec)
12175`define INT_VEC_TAKEN_42 `SPC5.tlu.trl0.take_ivt&`SPC5.tlu.trl0.trap[2]
12176
12177`define CPU_MONDO_TAKEN_42 `SPC5.tlu.trl0.take_mqr&`SPC5.tlu.trl0.trap[2]
12178`define DEV_MONDO_TAKEN_42 `SPC5.tlu.trl0.take_dqr&`SPC5.tlu.trl0.trap[2]
12179`define RES_MONDO_TAKEN_42 `SPC5.tlu.trl0.take_rqr&`SPC5.tlu.trl0.trap[2]
12180
12181`define XIR_TAKEN_42 `SPC5.tlu.trl0.take_xir&`SPC5.tlu.trl0.trap[2]
12182
12183`define SOFTINT_RDWR_42 (`TOP.nas_top.c5.t2.asi_rdwr_softint|`TOP.nas_top.c5.t2.asi_wr_softint_delay)
12184
12185`define SOFTINT_REG_42 `SPC5.tlu.trl0.softint2
12186`define RD_SOFTINT_REG_42 `SPC5.tlu.trl0.rd_softint2
12187`define INT_LEVEL_TAKEN_42 `SPC5.tlu.trl0.take_iln&`SPC5.tlu.trl0.trap[2]
12188`define INT_LEVEL_NUM_42 `SPC5.tlu.trl0.int_level_n
12189`define PMU_TAKEN_42 `SPC5.tlu.trl0.take_pmu&`SPC5.tlu.trl0.trap[2]
12190
12191`define HINTP_RDWR_42 (`TOP.nas_top.c5.t2.asi_rdwr_hintp | `TOP.nas_top.c5.t2.asi_wr_hintp_delay)
12192`define HINTP_WR_42 (`SPC5.tlu.asi_wr_hintp[42])
12193`define HSTMATCH_42 `SPC5.tlu.trl0.hstick2_compare
12194
12195`define HINTP_REG_42 `SPC5.tlu.trl0.hintp2
12196`define HSTM_TAKEN_42 `SPC5.tlu.trl0.take_hst&`SPC5.tlu.trl0.trap[2]
12197
12198`define NAS_PIPE_FW2_42 |`TOP.nas_top.c5.t2.complete_fw2
12199
12200`define CWQ_TAKEN_42 `SPC5.tlu.trl0.take_cwq&`SPC5.tlu.trl0.trap[2]
12201`define SMA_TAKEN_42 `SPC5.tlu.trl0.take_sma&`SPC5.tlu.trl0.trap[2]
12202
12203`define POR_TAKEN_42 `SPC5.tlu.trl0.take_por&`SPC5.tlu.trl0.trap[2]
12204
12205/////////////////////////////// Probes //////////////////////////////////// }}}
12206
12207always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
12208
12209 // {{{ DETECT, PIPE & SEND
12210 take_disrupting_w <= (`INT_VEC_TAKEN_42 || `CPU_MONDO_TAKEN_42 ||
12211 `DEV_MONDO_TAKEN_42 || `RES_MONDO_TAKEN_42 ||
12212 `XIR_TAKEN_42 || `INT_LEVEL_TAKEN_42 ||
12213 `HSTM_TAKEN_42 || `CWQ_TAKEN_42 ||
12214 `SMA_TAKEN_42 || `PMU_TAKEN_42 || `POR_TAKEN_42);
12215 take_disrupting_fx4 <= take_disrupting_w;
12216 take_disrupting_fx5 <= take_disrupting_fx4;
12217 take_disrupting_fb <= take_disrupting_fx5;
12218 take_disrupting_fw <= take_disrupting_fb;
12219 take_disrupting_fw1 <= take_disrupting_fw;
12220 take_disrupting_fw2 <= take_disrupting_fw1;
12221
12222 case ({`INT_VEC_TAKEN_42, `CPU_MONDO_TAKEN_42,
12223 `DEV_MONDO_TAKEN_42, `RES_MONDO_TAKEN_42,
12224 `XIR_TAKEN_42, `INT_LEVEL_TAKEN_42,
12225 `HSTM_TAKEN_42, `CWQ_TAKEN_42, `SMA_TAKEN_42 ,
12226 `PMU_TAKEN_42, `POR_TAKEN_42})
12227 11'b10000000000: int_num_w <= 8'h60;
12228 11'b01000000000: int_num_w <= 8'h7c;
12229 11'b00100000000: int_num_w <= 8'h7d;
12230 11'b00010000000: int_num_w <= 8'h7e;
12231 11'b00001000000: int_num_w <= 8'h03;
12232 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_42;
12233 11'b00000010000: int_num_w <= 8'h5e;
12234 11'b00000001000: int_num_w <= 8'h3c;
12235 11'b00000000100: int_num_w <= 8'h3d;
12236 11'b00000000010: int_num_w <= 8'h4f;
12237 11'b00000000001: int_num_w <= 8'h01;
12238 endcase
12239
12240 int_num_fx4 <= int_num_w;
12241 int_num_fx5 <= int_num_fx4;
12242 int_num_fb <= int_num_fx5;
12243 int_num_fw <= int_num_fb;
12244 int_num_fw1 <= int_num_fw;
12245 int_num_fw2 <= int_num_fw1;
12246 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
12247 begin // {
12248 `PR_INFO ("pli_int", `INFO,
12249 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
12250 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
12251 end // }
12252
12253 // }}}
12254
12255/////////////////////////// Vectored Interrupt /////////////////////////// {{{
12256
12257 // Vectored Interrupt Recv Register Detection
12258 // Indicate when register changes due to arriving interrupt, and not
12259 // due to read of incoming register or ASI write ..
12260
12261
12262 // If any read occurs, send value right away.
12263 // While a read/write is pending, do not update delta.
12264 // Send non read/wr delta during fw2 ..
12265
12266
12267 if (!(`INT_VEC_RDWR_42 | `INT_VEC_RECV_ASIWR_42)) begin // {
12268 if (~`INT_VEC_RECV_ASIWR_42 &
12269 (int_vec_recv_reg !== `INT_VEC_RECV_REG_42 ))
12270 int_vec_recv_reg_delta <= 1'b1;
12271 int_vec_recv_reg <= `INT_VEC_RECV_REG_42;
12272 end // }
12273 else if (`INT_VEC_RECV_ASIWR_42)
12274 int_vec_recv_reg <= `TOP.nas_top.c5.t2.asi_updated_int_rec;
12275
12276 if ((`NAS_PIPE_FW2_42 & int_vec_recv_reg_delta ) |
12277 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
12278 `INT_VEC_RECV_ASIWR_42 ) begin // {
12279 `PR_INFO ("pli_int", `INFO,
12280 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
12281 mycid,mytid, int_vec_recv_reg);
12282 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12283 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
12284 64'h0, int_vec_recv_reg);
12285 end // }
12286 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_42 &
12287 (int_vec_recv_reg !== `INT_VEC_RECV_REG_42 ))))
12288 int_vec_recv_reg_delta <= 1'b0;
12289 end //}
12290
12291 int_vec_reg_rdwr <= `INT_VEC_RDWR_42 | `INT_VEC_RECV_ASIWR_42;
12292 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_42 & ~ inc_vec_reg_rd;
12293
12294 if (`INT_VEC_RECV_ASIWR_42)
12295 inc_vec_reg_rd <= 1'b1;
12296 if (`NAS_PIPE_FW2_42)
12297 inc_vec_reg_rd <= 1'b0;
12298
12299
12300/////////////////////////// Vectored Interrupt /////////////////////////// }}}
12301
12302/////////////////////////// Asynchronous Resets ////////////////////////// {{{
12303
12304
12305/////////////////////////// Asynchronous Resets ////////////////////////// }}}
12306
12307/////////////////////////// Softint ///////////////////////////////////// {{{
12308
12309 // Softint Register hardware Update Detection
12310
12311 // Non software updates (TM/SM)
12312
12313 // If any read occurs, send value right away.
12314 // While a read/write is pending, do not update delta.
12315 // Send non read/wr delta during fw2 ..
12316
12317 // RTL keeps pic_ovf indication in rd_softint and not softint.
12318 // So for set/clear writes, we send softint before the write ..,
12319 // and for read/asyncs we send rd_softint ..
12320
12321
12322 if (~`SOFTINT_RDWR_42) begin // {
12323 if (softint !== `RD_SOFTINT_REG_42 )
12324 softint_delta <= 1'b1;
12325 softint <= `RD_SOFTINT_REG_42;
12326 end // }
12327
12328 if ((`NAS_PIPE_FW2_42 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
12329 ) begin // {
12330 `PR_INFO ("pli_int", `INFO,
12331 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12332 mycid,mytid, {47'h0, softint});
12333 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12334 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12335 {47'h0, softint});
12336 end // }
12337 if (!(~`SOFTINT_RDWR_42&(softint !== `RD_SOFTINT_REG_42)))
12338 softint_delta <= 1'b0;
12339 end //}
12340 else if (`SPC5.tlu.asi_wr_clear_softint[2] |
12341 `SPC5.tlu.asi_wr_set_softint[2] ) begin // {
12342 `PR_INFO ("pli_int", `INFO,
12343 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12344 mycid,mytid, {47'h0, `RD_SOFTINT_REG_42});
12345 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12346 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12347 {47'h0, `RD_SOFTINT_REG_42});
12348 end // }
12349 end //}
12350
12351
12352 softint_rdwr <= `SOFTINT_RDWR_42 ;
12353 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_42;
12354
12355
12356/////////////////////////// Softint ///////////////////////////////////// }}}
12357
12358/////////////////////////// Hintp ///////////////////////////////////// {{{
12359
12360 // Hintp Register hardware Update Detection
12361
12362 // Non software updates (HSP)
12363 // If HINTP is already read/written by SW, then don't send
12364 // any async updates to Nas. Reads/Writes pending sstep is detected
12365 // by snooping nas_pipe ..
12366
12367 hintp <= `HINTP_REG_42 ;
12368 if (hstmatch_late)
12369 hintp_delta <= 1'b1;
12370
12371 if ((~hintp_rdwr & `NAS_PIPE_FW2_42 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
12372 (hintp_rdwr_late & hintp_delta) ) begin // {
12373 `PR_INFO ("pli_int", `INFO,
12374 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
12375 mycid,mytid, {63'h0, hintp});
12376 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12377 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
12378 {63'h0, hintp});
12379 end // }
12380 if (~(hintp_rdwr_late & hintp_delta))
12381 hintp_delta <= 1'b0;
12382 end //}
12383
12384 hintp_rdwr <= `HINTP_RDWR_42;
12385 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_42;
12386 hstmatch_late <= `HSTMATCH_42;
12387
12388
12389/////////////////////////// Hintp ///////////////////////////////////// }}}
12390
12391end //}
12392`endif
12393endmodule
12394
12395// }}}
12396
12397module int_c5t3 ();
12398`ifndef GATESIM
12399
12400// common defines
12401`include "defines.vh"
12402`include "ccx.vri"
12403`include "cmp.vri"
12404
12405wire [2:0] mycid;
12406wire [2:0] mytid;
12407wire [5:0] mytnum;
12408integer junk;
12409
12410reg [63:0] int_vec_recv_reg;
12411reg int_vec_recv_reg_delta;
12412reg int_vec_reg_rdwr;
12413reg inc_vec_reg_rd;
12414reg int_vec_reg_rdwr_late;
12415reg [16:0] softint;
12416reg softint_rdwr;
12417reg softint_rdwr_late;
12418reg softint_delta;
12419reg hintp;
12420reg hintp_rdwr;
12421reg hintp_rdwr_late;
12422reg hintp_delta;
12423reg hstmatch_late;
12424reg ready;
12425reg [7:0] int_num_w;
12426reg [7:0] int_num_fx4;
12427reg [7:0] int_num_fx5;
12428reg [7:0] int_num_fb;
12429reg [7:0] int_num_fw;
12430reg [7:0] int_num_fw1;
12431reg [7:0] int_num_fw2;
12432reg take_disrupting_w;
12433reg take_disrupting_fx4;
12434reg take_disrupting_fx5;
12435reg take_disrupting_fb;
12436reg take_disrupting_fw;
12437reg take_disrupting_fw1;
12438reg take_disrupting_fw2;
12439
12440 assign mycid = 5;
12441 assign mytid = 3;
12442 assign mytnum = 5*8 + 3;
12443
12444initial begin // {
12445 ready = 0; // Wait for socket setup ..
12446 inc_vec_reg_rd <= 1'b0;
12447 int_vec_recv_reg_delta <= 1'b0;
12448 softint_delta <= 1'b0;
12449 hintp_delta <= 1'b0;
12450 int_vec_recv_reg = 64'b0;
12451 @(posedge `BENCH_SPC5_GCLK) ;
12452 @(posedge `BENCH_SPC5_GCLK) ;
12453 ready = `PARGS.int_sync_on;
12454end //}
12455
12456
12457/////////////////////////////// Probes //////////////////////////////////// {{{
12458
12459`define INT_VEC_RECV_REG_43 `SPC5.tlu.cth.int_rec3
12460`define INT_VEC_RECV_ASIWR_43 (`TOP.nas_top.c5.t3.asi_wr_int_rec_delay)
12461`define INT_VEC_RDWR_43 (`TOP.nas_top.c5.t3.asi_rdwr_int_rec)
12462`define INT_VEC_TAKEN_43 `SPC5.tlu.trl0.take_ivt&`SPC5.tlu.trl0.trap[3]
12463
12464`define CPU_MONDO_TAKEN_43 `SPC5.tlu.trl0.take_mqr&`SPC5.tlu.trl0.trap[3]
12465`define DEV_MONDO_TAKEN_43 `SPC5.tlu.trl0.take_dqr&`SPC5.tlu.trl0.trap[3]
12466`define RES_MONDO_TAKEN_43 `SPC5.tlu.trl0.take_rqr&`SPC5.tlu.trl0.trap[3]
12467
12468`define XIR_TAKEN_43 `SPC5.tlu.trl0.take_xir&`SPC5.tlu.trl0.trap[3]
12469
12470`define SOFTINT_RDWR_43 (`TOP.nas_top.c5.t3.asi_rdwr_softint|`TOP.nas_top.c5.t3.asi_wr_softint_delay)
12471
12472`define SOFTINT_REG_43 `SPC5.tlu.trl0.softint3
12473`define RD_SOFTINT_REG_43 `SPC5.tlu.trl0.rd_softint3
12474`define INT_LEVEL_TAKEN_43 `SPC5.tlu.trl0.take_iln&`SPC5.tlu.trl0.trap[3]
12475`define INT_LEVEL_NUM_43 `SPC5.tlu.trl0.int_level_n
12476`define PMU_TAKEN_43 `SPC5.tlu.trl0.take_pmu&`SPC5.tlu.trl0.trap[3]
12477
12478`define HINTP_RDWR_43 (`TOP.nas_top.c5.t3.asi_rdwr_hintp | `TOP.nas_top.c5.t3.asi_wr_hintp_delay)
12479`define HINTP_WR_43 (`SPC5.tlu.asi_wr_hintp[43])
12480`define HSTMATCH_43 `SPC5.tlu.trl0.hstick3_compare
12481
12482`define HINTP_REG_43 `SPC5.tlu.trl0.hintp3
12483`define HSTM_TAKEN_43 `SPC5.tlu.trl0.take_hst&`SPC5.tlu.trl0.trap[3]
12484
12485`define NAS_PIPE_FW2_43 |`TOP.nas_top.c5.t3.complete_fw2
12486
12487`define CWQ_TAKEN_43 `SPC5.tlu.trl0.take_cwq&`SPC5.tlu.trl0.trap[3]
12488`define SMA_TAKEN_43 `SPC5.tlu.trl0.take_sma&`SPC5.tlu.trl0.trap[3]
12489
12490`define POR_TAKEN_43 `SPC5.tlu.trl0.take_por&`SPC5.tlu.trl0.trap[3]
12491
12492/////////////////////////////// Probes //////////////////////////////////// }}}
12493
12494always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
12495
12496 // {{{ DETECT, PIPE & SEND
12497 take_disrupting_w <= (`INT_VEC_TAKEN_43 || `CPU_MONDO_TAKEN_43 ||
12498 `DEV_MONDO_TAKEN_43 || `RES_MONDO_TAKEN_43 ||
12499 `XIR_TAKEN_43 || `INT_LEVEL_TAKEN_43 ||
12500 `HSTM_TAKEN_43 || `CWQ_TAKEN_43 ||
12501 `SMA_TAKEN_43 || `PMU_TAKEN_43 || `POR_TAKEN_43);
12502 take_disrupting_fx4 <= take_disrupting_w;
12503 take_disrupting_fx5 <= take_disrupting_fx4;
12504 take_disrupting_fb <= take_disrupting_fx5;
12505 take_disrupting_fw <= take_disrupting_fb;
12506 take_disrupting_fw1 <= take_disrupting_fw;
12507 take_disrupting_fw2 <= take_disrupting_fw1;
12508
12509 case ({`INT_VEC_TAKEN_43, `CPU_MONDO_TAKEN_43,
12510 `DEV_MONDO_TAKEN_43, `RES_MONDO_TAKEN_43,
12511 `XIR_TAKEN_43, `INT_LEVEL_TAKEN_43,
12512 `HSTM_TAKEN_43, `CWQ_TAKEN_43, `SMA_TAKEN_43 ,
12513 `PMU_TAKEN_43, `POR_TAKEN_43})
12514 11'b10000000000: int_num_w <= 8'h60;
12515 11'b01000000000: int_num_w <= 8'h7c;
12516 11'b00100000000: int_num_w <= 8'h7d;
12517 11'b00010000000: int_num_w <= 8'h7e;
12518 11'b00001000000: int_num_w <= 8'h03;
12519 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_43;
12520 11'b00000010000: int_num_w <= 8'h5e;
12521 11'b00000001000: int_num_w <= 8'h3c;
12522 11'b00000000100: int_num_w <= 8'h3d;
12523 11'b00000000010: int_num_w <= 8'h4f;
12524 11'b00000000001: int_num_w <= 8'h01;
12525 endcase
12526
12527 int_num_fx4 <= int_num_w;
12528 int_num_fx5 <= int_num_fx4;
12529 int_num_fb <= int_num_fx5;
12530 int_num_fw <= int_num_fb;
12531 int_num_fw1 <= int_num_fw;
12532 int_num_fw2 <= int_num_fw1;
12533 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
12534 begin // {
12535 `PR_INFO ("pli_int", `INFO,
12536 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
12537 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
12538 end // }
12539
12540 // }}}
12541
12542/////////////////////////// Vectored Interrupt /////////////////////////// {{{
12543
12544 // Vectored Interrupt Recv Register Detection
12545 // Indicate when register changes due to arriving interrupt, and not
12546 // due to read of incoming register or ASI write ..
12547
12548
12549 // If any read occurs, send value right away.
12550 // While a read/write is pending, do not update delta.
12551 // Send non read/wr delta during fw2 ..
12552
12553
12554 if (!(`INT_VEC_RDWR_43 | `INT_VEC_RECV_ASIWR_43)) begin // {
12555 if (~`INT_VEC_RECV_ASIWR_43 &
12556 (int_vec_recv_reg !== `INT_VEC_RECV_REG_43 ))
12557 int_vec_recv_reg_delta <= 1'b1;
12558 int_vec_recv_reg <= `INT_VEC_RECV_REG_43;
12559 end // }
12560 else if (`INT_VEC_RECV_ASIWR_43)
12561 int_vec_recv_reg <= `TOP.nas_top.c5.t3.asi_updated_int_rec;
12562
12563 if ((`NAS_PIPE_FW2_43 & int_vec_recv_reg_delta ) |
12564 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
12565 `INT_VEC_RECV_ASIWR_43 ) begin // {
12566 `PR_INFO ("pli_int", `INFO,
12567 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
12568 mycid,mytid, int_vec_recv_reg);
12569 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12570 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
12571 64'h0, int_vec_recv_reg);
12572 end // }
12573 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_43 &
12574 (int_vec_recv_reg !== `INT_VEC_RECV_REG_43 ))))
12575 int_vec_recv_reg_delta <= 1'b0;
12576 end //}
12577
12578 int_vec_reg_rdwr <= `INT_VEC_RDWR_43 | `INT_VEC_RECV_ASIWR_43;
12579 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_43 & ~ inc_vec_reg_rd;
12580
12581 if (`INT_VEC_RECV_ASIWR_43)
12582 inc_vec_reg_rd <= 1'b1;
12583 if (`NAS_PIPE_FW2_43)
12584 inc_vec_reg_rd <= 1'b0;
12585
12586
12587/////////////////////////// Vectored Interrupt /////////////////////////// }}}
12588
12589/////////////////////////// Asynchronous Resets ////////////////////////// {{{
12590
12591
12592/////////////////////////// Asynchronous Resets ////////////////////////// }}}
12593
12594/////////////////////////// Softint ///////////////////////////////////// {{{
12595
12596 // Softint Register hardware Update Detection
12597
12598 // Non software updates (TM/SM)
12599
12600 // If any read occurs, send value right away.
12601 // While a read/write is pending, do not update delta.
12602 // Send non read/wr delta during fw2 ..
12603
12604 // RTL keeps pic_ovf indication in rd_softint and not softint.
12605 // So for set/clear writes, we send softint before the write ..,
12606 // and for read/asyncs we send rd_softint ..
12607
12608
12609 if (~`SOFTINT_RDWR_43) begin // {
12610 if (softint !== `RD_SOFTINT_REG_43 )
12611 softint_delta <= 1'b1;
12612 softint <= `RD_SOFTINT_REG_43;
12613 end // }
12614
12615 if ((`NAS_PIPE_FW2_43 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
12616 ) begin // {
12617 `PR_INFO ("pli_int", `INFO,
12618 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12619 mycid,mytid, {47'h0, softint});
12620 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12621 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12622 {47'h0, softint});
12623 end // }
12624 if (!(~`SOFTINT_RDWR_43&(softint !== `RD_SOFTINT_REG_43)))
12625 softint_delta <= 1'b0;
12626 end //}
12627 else if (`SPC5.tlu.asi_wr_clear_softint[3] |
12628 `SPC5.tlu.asi_wr_set_softint[3] ) begin // {
12629 `PR_INFO ("pli_int", `INFO,
12630 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12631 mycid,mytid, {47'h0, `RD_SOFTINT_REG_43});
12632 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12633 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12634 {47'h0, `RD_SOFTINT_REG_43});
12635 end // }
12636 end //}
12637
12638
12639 softint_rdwr <= `SOFTINT_RDWR_43 ;
12640 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_43;
12641
12642
12643/////////////////////////// Softint ///////////////////////////////////// }}}
12644
12645/////////////////////////// Hintp ///////////////////////////////////// {{{
12646
12647 // Hintp Register hardware Update Detection
12648
12649 // Non software updates (HSP)
12650 // If HINTP is already read/written by SW, then don't send
12651 // any async updates to Nas. Reads/Writes pending sstep is detected
12652 // by snooping nas_pipe ..
12653
12654 hintp <= `HINTP_REG_43 ;
12655 if (hstmatch_late)
12656 hintp_delta <= 1'b1;
12657
12658 if ((~hintp_rdwr & `NAS_PIPE_FW2_43 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
12659 (hintp_rdwr_late & hintp_delta) ) begin // {
12660 `PR_INFO ("pli_int", `INFO,
12661 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
12662 mycid,mytid, {63'h0, hintp});
12663 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12664 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
12665 {63'h0, hintp});
12666 end // }
12667 if (~(hintp_rdwr_late & hintp_delta))
12668 hintp_delta <= 1'b0;
12669 end //}
12670
12671 hintp_rdwr <= `HINTP_RDWR_43;
12672 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_43;
12673 hstmatch_late <= `HSTMATCH_43;
12674
12675
12676/////////////////////////// Hintp ///////////////////////////////////// }}}
12677
12678end //}
12679`endif
12680endmodule
12681
12682// }}}
12683
12684module int_c5t4 ();
12685`ifndef GATESIM
12686
12687// common defines
12688`include "defines.vh"
12689`include "ccx.vri"
12690`include "cmp.vri"
12691
12692wire [2:0] mycid;
12693wire [2:0] mytid;
12694wire [5:0] mytnum;
12695integer junk;
12696
12697reg [63:0] int_vec_recv_reg;
12698reg int_vec_recv_reg_delta;
12699reg int_vec_reg_rdwr;
12700reg inc_vec_reg_rd;
12701reg int_vec_reg_rdwr_late;
12702reg [16:0] softint;
12703reg softint_rdwr;
12704reg softint_rdwr_late;
12705reg softint_delta;
12706reg hintp;
12707reg hintp_rdwr;
12708reg hintp_rdwr_late;
12709reg hintp_delta;
12710reg hstmatch_late;
12711reg ready;
12712reg [7:0] int_num_w;
12713reg [7:0] int_num_fx4;
12714reg [7:0] int_num_fx5;
12715reg [7:0] int_num_fb;
12716reg [7:0] int_num_fw;
12717reg [7:0] int_num_fw1;
12718reg [7:0] int_num_fw2;
12719reg take_disrupting_w;
12720reg take_disrupting_fx4;
12721reg take_disrupting_fx5;
12722reg take_disrupting_fb;
12723reg take_disrupting_fw;
12724reg take_disrupting_fw1;
12725reg take_disrupting_fw2;
12726
12727 assign mycid = 5;
12728 assign mytid = 4;
12729 assign mytnum = 5*8 + 4;
12730
12731initial begin // {
12732 ready = 0; // Wait for socket setup ..
12733 inc_vec_reg_rd <= 1'b0;
12734 int_vec_recv_reg_delta <= 1'b0;
12735 softint_delta <= 1'b0;
12736 hintp_delta <= 1'b0;
12737 int_vec_recv_reg = 64'b0;
12738 @(posedge `BENCH_SPC5_GCLK) ;
12739 @(posedge `BENCH_SPC5_GCLK) ;
12740 ready = `PARGS.int_sync_on;
12741end //}
12742
12743
12744/////////////////////////////// Probes //////////////////////////////////// {{{
12745
12746`define INT_VEC_RECV_REG_44 `SPC5.tlu.cth.int_rec4
12747`define INT_VEC_RECV_ASIWR_44 (`TOP.nas_top.c5.t4.asi_wr_int_rec_delay)
12748`define INT_VEC_RDWR_44 (`TOP.nas_top.c5.t4.asi_rdwr_int_rec)
12749`define INT_VEC_TAKEN_44 `SPC5.tlu.trl1.take_ivt&`SPC5.tlu.trl1.trap[0]
12750
12751`define CPU_MONDO_TAKEN_44 `SPC5.tlu.trl1.take_mqr&`SPC5.tlu.trl1.trap[0]
12752`define DEV_MONDO_TAKEN_44 `SPC5.tlu.trl1.take_dqr&`SPC5.tlu.trl1.trap[0]
12753`define RES_MONDO_TAKEN_44 `SPC5.tlu.trl1.take_rqr&`SPC5.tlu.trl1.trap[0]
12754
12755`define XIR_TAKEN_44 `SPC5.tlu.trl1.take_xir&`SPC5.tlu.trl1.trap[0]
12756
12757`define SOFTINT_RDWR_44 (`TOP.nas_top.c5.t4.asi_rdwr_softint|`TOP.nas_top.c5.t4.asi_wr_softint_delay)
12758
12759`define SOFTINT_REG_44 `SPC5.tlu.trl1.softint0
12760`define RD_SOFTINT_REG_44 `SPC5.tlu.trl1.rd_softint0
12761`define INT_LEVEL_TAKEN_44 `SPC5.tlu.trl1.take_iln&`SPC5.tlu.trl1.trap[0]
12762`define INT_LEVEL_NUM_44 `SPC5.tlu.trl1.int_level_n
12763`define PMU_TAKEN_44 `SPC5.tlu.trl1.take_pmu&`SPC5.tlu.trl1.trap[0]
12764
12765`define HINTP_RDWR_44 (`TOP.nas_top.c5.t4.asi_rdwr_hintp | `TOP.nas_top.c5.t4.asi_wr_hintp_delay)
12766`define HINTP_WR_44 (`SPC5.tlu.asi_wr_hintp[44])
12767`define HSTMATCH_44 `SPC5.tlu.trl1.hstick0_compare
12768
12769`define HINTP_REG_44 `SPC5.tlu.trl1.hintp0
12770`define HSTM_TAKEN_44 `SPC5.tlu.trl1.take_hst&`SPC5.tlu.trl1.trap[0]
12771
12772`define NAS_PIPE_FW2_44 |`TOP.nas_top.c5.t4.complete_fw2
12773
12774`define CWQ_TAKEN_44 `SPC5.tlu.trl1.take_cwq&`SPC5.tlu.trl1.trap[0]
12775`define SMA_TAKEN_44 `SPC5.tlu.trl1.take_sma&`SPC5.tlu.trl1.trap[0]
12776
12777`define POR_TAKEN_44 `SPC5.tlu.trl1.take_por&`SPC5.tlu.trl1.trap[0]
12778
12779/////////////////////////////// Probes //////////////////////////////////// }}}
12780
12781always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
12782
12783 // {{{ DETECT, PIPE & SEND
12784 take_disrupting_w <= (`INT_VEC_TAKEN_44 || `CPU_MONDO_TAKEN_44 ||
12785 `DEV_MONDO_TAKEN_44 || `RES_MONDO_TAKEN_44 ||
12786 `XIR_TAKEN_44 || `INT_LEVEL_TAKEN_44 ||
12787 `HSTM_TAKEN_44 || `CWQ_TAKEN_44 ||
12788 `SMA_TAKEN_44 || `PMU_TAKEN_44 || `POR_TAKEN_44);
12789 take_disrupting_fx4 <= take_disrupting_w;
12790 take_disrupting_fx5 <= take_disrupting_fx4;
12791 take_disrupting_fb <= take_disrupting_fx5;
12792 take_disrupting_fw <= take_disrupting_fb;
12793 take_disrupting_fw1 <= take_disrupting_fw;
12794 take_disrupting_fw2 <= take_disrupting_fw1;
12795
12796 case ({`INT_VEC_TAKEN_44, `CPU_MONDO_TAKEN_44,
12797 `DEV_MONDO_TAKEN_44, `RES_MONDO_TAKEN_44,
12798 `XIR_TAKEN_44, `INT_LEVEL_TAKEN_44,
12799 `HSTM_TAKEN_44, `CWQ_TAKEN_44, `SMA_TAKEN_44 ,
12800 `PMU_TAKEN_44, `POR_TAKEN_44})
12801 11'b10000000000: int_num_w <= 8'h60;
12802 11'b01000000000: int_num_w <= 8'h7c;
12803 11'b00100000000: int_num_w <= 8'h7d;
12804 11'b00010000000: int_num_w <= 8'h7e;
12805 11'b00001000000: int_num_w <= 8'h03;
12806 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_44;
12807 11'b00000010000: int_num_w <= 8'h5e;
12808 11'b00000001000: int_num_w <= 8'h3c;
12809 11'b00000000100: int_num_w <= 8'h3d;
12810 11'b00000000010: int_num_w <= 8'h4f;
12811 11'b00000000001: int_num_w <= 8'h01;
12812 endcase
12813
12814 int_num_fx4 <= int_num_w;
12815 int_num_fx5 <= int_num_fx4;
12816 int_num_fb <= int_num_fx5;
12817 int_num_fw <= int_num_fb;
12818 int_num_fw1 <= int_num_fw;
12819 int_num_fw2 <= int_num_fw1;
12820 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
12821 begin // {
12822 `PR_INFO ("pli_int", `INFO,
12823 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
12824 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
12825 end // }
12826
12827 // }}}
12828
12829/////////////////////////// Vectored Interrupt /////////////////////////// {{{
12830
12831 // Vectored Interrupt Recv Register Detection
12832 // Indicate when register changes due to arriving interrupt, and not
12833 // due to read of incoming register or ASI write ..
12834
12835
12836 // If any read occurs, send value right away.
12837 // While a read/write is pending, do not update delta.
12838 // Send non read/wr delta during fw2 ..
12839
12840
12841 if (!(`INT_VEC_RDWR_44 | `INT_VEC_RECV_ASIWR_44)) begin // {
12842 if (~`INT_VEC_RECV_ASIWR_44 &
12843 (int_vec_recv_reg !== `INT_VEC_RECV_REG_44 ))
12844 int_vec_recv_reg_delta <= 1'b1;
12845 int_vec_recv_reg <= `INT_VEC_RECV_REG_44;
12846 end // }
12847 else if (`INT_VEC_RECV_ASIWR_44)
12848 int_vec_recv_reg <= `TOP.nas_top.c5.t4.asi_updated_int_rec;
12849
12850 if ((`NAS_PIPE_FW2_44 & int_vec_recv_reg_delta ) |
12851 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
12852 `INT_VEC_RECV_ASIWR_44 ) begin // {
12853 `PR_INFO ("pli_int", `INFO,
12854 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
12855 mycid,mytid, int_vec_recv_reg);
12856 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12857 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
12858 64'h0, int_vec_recv_reg);
12859 end // }
12860 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_44 &
12861 (int_vec_recv_reg !== `INT_VEC_RECV_REG_44 ))))
12862 int_vec_recv_reg_delta <= 1'b0;
12863 end //}
12864
12865 int_vec_reg_rdwr <= `INT_VEC_RDWR_44 | `INT_VEC_RECV_ASIWR_44;
12866 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_44 & ~ inc_vec_reg_rd;
12867
12868 if (`INT_VEC_RECV_ASIWR_44)
12869 inc_vec_reg_rd <= 1'b1;
12870 if (`NAS_PIPE_FW2_44)
12871 inc_vec_reg_rd <= 1'b0;
12872
12873
12874/////////////////////////// Vectored Interrupt /////////////////////////// }}}
12875
12876/////////////////////////// Asynchronous Resets ////////////////////////// {{{
12877
12878
12879/////////////////////////// Asynchronous Resets ////////////////////////// }}}
12880
12881/////////////////////////// Softint ///////////////////////////////////// {{{
12882
12883 // Softint Register hardware Update Detection
12884
12885 // Non software updates (TM/SM)
12886
12887 // If any read occurs, send value right away.
12888 // While a read/write is pending, do not update delta.
12889 // Send non read/wr delta during fw2 ..
12890
12891 // RTL keeps pic_ovf indication in rd_softint and not softint.
12892 // So for set/clear writes, we send softint before the write ..,
12893 // and for read/asyncs we send rd_softint ..
12894
12895
12896 if (~`SOFTINT_RDWR_44) begin // {
12897 if (softint !== `RD_SOFTINT_REG_44 )
12898 softint_delta <= 1'b1;
12899 softint <= `RD_SOFTINT_REG_44;
12900 end // }
12901
12902 if ((`NAS_PIPE_FW2_44 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
12903 ) begin // {
12904 `PR_INFO ("pli_int", `INFO,
12905 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12906 mycid,mytid, {47'h0, softint});
12907 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12908 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12909 {47'h0, softint});
12910 end // }
12911 if (!(~`SOFTINT_RDWR_44&(softint !== `RD_SOFTINT_REG_44)))
12912 softint_delta <= 1'b0;
12913 end //}
12914 else if (`SPC5.tlu.asi_wr_clear_softint[4] |
12915 `SPC5.tlu.asi_wr_set_softint[4] ) begin // {
12916 `PR_INFO ("pli_int", `INFO,
12917 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
12918 mycid,mytid, {47'h0, `RD_SOFTINT_REG_44});
12919 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12920 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
12921 {47'h0, `RD_SOFTINT_REG_44});
12922 end // }
12923 end //}
12924
12925
12926 softint_rdwr <= `SOFTINT_RDWR_44 ;
12927 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_44;
12928
12929
12930/////////////////////////// Softint ///////////////////////////////////// }}}
12931
12932/////////////////////////// Hintp ///////////////////////////////////// {{{
12933
12934 // Hintp Register hardware Update Detection
12935
12936 // Non software updates (HSP)
12937 // If HINTP is already read/written by SW, then don't send
12938 // any async updates to Nas. Reads/Writes pending sstep is detected
12939 // by snooping nas_pipe ..
12940
12941 hintp <= `HINTP_REG_44 ;
12942 if (hstmatch_late)
12943 hintp_delta <= 1'b1;
12944
12945 if ((~hintp_rdwr & `NAS_PIPE_FW2_44 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
12946 (hintp_rdwr_late & hintp_delta) ) begin // {
12947 `PR_INFO ("pli_int", `INFO,
12948 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
12949 mycid,mytid, {63'h0, hintp});
12950 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
12951 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
12952 {63'h0, hintp});
12953 end // }
12954 if (~(hintp_rdwr_late & hintp_delta))
12955 hintp_delta <= 1'b0;
12956 end //}
12957
12958 hintp_rdwr <= `HINTP_RDWR_44;
12959 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_44;
12960 hstmatch_late <= `HSTMATCH_44;
12961
12962
12963/////////////////////////// Hintp ///////////////////////////////////// }}}
12964
12965end //}
12966`endif
12967endmodule
12968
12969// }}}
12970
12971module int_c5t5 ();
12972`ifndef GATESIM
12973
12974// common defines
12975`include "defines.vh"
12976`include "ccx.vri"
12977`include "cmp.vri"
12978
12979wire [2:0] mycid;
12980wire [2:0] mytid;
12981wire [5:0] mytnum;
12982integer junk;
12983
12984reg [63:0] int_vec_recv_reg;
12985reg int_vec_recv_reg_delta;
12986reg int_vec_reg_rdwr;
12987reg inc_vec_reg_rd;
12988reg int_vec_reg_rdwr_late;
12989reg [16:0] softint;
12990reg softint_rdwr;
12991reg softint_rdwr_late;
12992reg softint_delta;
12993reg hintp;
12994reg hintp_rdwr;
12995reg hintp_rdwr_late;
12996reg hintp_delta;
12997reg hstmatch_late;
12998reg ready;
12999reg [7:0] int_num_w;
13000reg [7:0] int_num_fx4;
13001reg [7:0] int_num_fx5;
13002reg [7:0] int_num_fb;
13003reg [7:0] int_num_fw;
13004reg [7:0] int_num_fw1;
13005reg [7:0] int_num_fw2;
13006reg take_disrupting_w;
13007reg take_disrupting_fx4;
13008reg take_disrupting_fx5;
13009reg take_disrupting_fb;
13010reg take_disrupting_fw;
13011reg take_disrupting_fw1;
13012reg take_disrupting_fw2;
13013
13014 assign mycid = 5;
13015 assign mytid = 5;
13016 assign mytnum = 5*8 + 5;
13017
13018initial begin // {
13019 ready = 0; // Wait for socket setup ..
13020 inc_vec_reg_rd <= 1'b0;
13021 int_vec_recv_reg_delta <= 1'b0;
13022 softint_delta <= 1'b0;
13023 hintp_delta <= 1'b0;
13024 int_vec_recv_reg = 64'b0;
13025 @(posedge `BENCH_SPC5_GCLK) ;
13026 @(posedge `BENCH_SPC5_GCLK) ;
13027 ready = `PARGS.int_sync_on;
13028end //}
13029
13030
13031/////////////////////////////// Probes //////////////////////////////////// {{{
13032
13033`define INT_VEC_RECV_REG_45 `SPC5.tlu.cth.int_rec5
13034`define INT_VEC_RECV_ASIWR_45 (`TOP.nas_top.c5.t5.asi_wr_int_rec_delay)
13035`define INT_VEC_RDWR_45 (`TOP.nas_top.c5.t5.asi_rdwr_int_rec)
13036`define INT_VEC_TAKEN_45 `SPC5.tlu.trl1.take_ivt&`SPC5.tlu.trl1.trap[1]
13037
13038`define CPU_MONDO_TAKEN_45 `SPC5.tlu.trl1.take_mqr&`SPC5.tlu.trl1.trap[1]
13039`define DEV_MONDO_TAKEN_45 `SPC5.tlu.trl1.take_dqr&`SPC5.tlu.trl1.trap[1]
13040`define RES_MONDO_TAKEN_45 `SPC5.tlu.trl1.take_rqr&`SPC5.tlu.trl1.trap[1]
13041
13042`define XIR_TAKEN_45 `SPC5.tlu.trl1.take_xir&`SPC5.tlu.trl1.trap[1]
13043
13044`define SOFTINT_RDWR_45 (`TOP.nas_top.c5.t5.asi_rdwr_softint|`TOP.nas_top.c5.t5.asi_wr_softint_delay)
13045
13046`define SOFTINT_REG_45 `SPC5.tlu.trl1.softint1
13047`define RD_SOFTINT_REG_45 `SPC5.tlu.trl1.rd_softint1
13048`define INT_LEVEL_TAKEN_45 `SPC5.tlu.trl1.take_iln&`SPC5.tlu.trl1.trap[1]
13049`define INT_LEVEL_NUM_45 `SPC5.tlu.trl1.int_level_n
13050`define PMU_TAKEN_45 `SPC5.tlu.trl1.take_pmu&`SPC5.tlu.trl1.trap[1]
13051
13052`define HINTP_RDWR_45 (`TOP.nas_top.c5.t5.asi_rdwr_hintp | `TOP.nas_top.c5.t5.asi_wr_hintp_delay)
13053`define HINTP_WR_45 (`SPC5.tlu.asi_wr_hintp[45])
13054`define HSTMATCH_45 `SPC5.tlu.trl1.hstick1_compare
13055
13056`define HINTP_REG_45 `SPC5.tlu.trl1.hintp1
13057`define HSTM_TAKEN_45 `SPC5.tlu.trl1.take_hst&`SPC5.tlu.trl1.trap[1]
13058
13059`define NAS_PIPE_FW2_45 |`TOP.nas_top.c5.t5.complete_fw2
13060
13061`define CWQ_TAKEN_45 `SPC5.tlu.trl1.take_cwq&`SPC5.tlu.trl1.trap[1]
13062`define SMA_TAKEN_45 `SPC5.tlu.trl1.take_sma&`SPC5.tlu.trl1.trap[1]
13063
13064`define POR_TAKEN_45 `SPC5.tlu.trl1.take_por&`SPC5.tlu.trl1.trap[1]
13065
13066/////////////////////////////// Probes //////////////////////////////////// }}}
13067
13068always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
13069
13070 // {{{ DETECT, PIPE & SEND
13071 take_disrupting_w <= (`INT_VEC_TAKEN_45 || `CPU_MONDO_TAKEN_45 ||
13072 `DEV_MONDO_TAKEN_45 || `RES_MONDO_TAKEN_45 ||
13073 `XIR_TAKEN_45 || `INT_LEVEL_TAKEN_45 ||
13074 `HSTM_TAKEN_45 || `CWQ_TAKEN_45 ||
13075 `SMA_TAKEN_45 || `PMU_TAKEN_45 || `POR_TAKEN_45);
13076 take_disrupting_fx4 <= take_disrupting_w;
13077 take_disrupting_fx5 <= take_disrupting_fx4;
13078 take_disrupting_fb <= take_disrupting_fx5;
13079 take_disrupting_fw <= take_disrupting_fb;
13080 take_disrupting_fw1 <= take_disrupting_fw;
13081 take_disrupting_fw2 <= take_disrupting_fw1;
13082
13083 case ({`INT_VEC_TAKEN_45, `CPU_MONDO_TAKEN_45,
13084 `DEV_MONDO_TAKEN_45, `RES_MONDO_TAKEN_45,
13085 `XIR_TAKEN_45, `INT_LEVEL_TAKEN_45,
13086 `HSTM_TAKEN_45, `CWQ_TAKEN_45, `SMA_TAKEN_45 ,
13087 `PMU_TAKEN_45, `POR_TAKEN_45})
13088 11'b10000000000: int_num_w <= 8'h60;
13089 11'b01000000000: int_num_w <= 8'h7c;
13090 11'b00100000000: int_num_w <= 8'h7d;
13091 11'b00010000000: int_num_w <= 8'h7e;
13092 11'b00001000000: int_num_w <= 8'h03;
13093 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_45;
13094 11'b00000010000: int_num_w <= 8'h5e;
13095 11'b00000001000: int_num_w <= 8'h3c;
13096 11'b00000000100: int_num_w <= 8'h3d;
13097 11'b00000000010: int_num_w <= 8'h4f;
13098 11'b00000000001: int_num_w <= 8'h01;
13099 endcase
13100
13101 int_num_fx4 <= int_num_w;
13102 int_num_fx5 <= int_num_fx4;
13103 int_num_fb <= int_num_fx5;
13104 int_num_fw <= int_num_fb;
13105 int_num_fw1 <= int_num_fw;
13106 int_num_fw2 <= int_num_fw1;
13107 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
13108 begin // {
13109 `PR_INFO ("pli_int", `INFO,
13110 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
13111 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13112 end // }
13113
13114 // }}}
13115
13116/////////////////////////// Vectored Interrupt /////////////////////////// {{{
13117
13118 // Vectored Interrupt Recv Register Detection
13119 // Indicate when register changes due to arriving interrupt, and not
13120 // due to read of incoming register or ASI write ..
13121
13122
13123 // If any read occurs, send value right away.
13124 // While a read/write is pending, do not update delta.
13125 // Send non read/wr delta during fw2 ..
13126
13127
13128 if (!(`INT_VEC_RDWR_45 | `INT_VEC_RECV_ASIWR_45)) begin // {
13129 if (~`INT_VEC_RECV_ASIWR_45 &
13130 (int_vec_recv_reg !== `INT_VEC_RECV_REG_45 ))
13131 int_vec_recv_reg_delta <= 1'b1;
13132 int_vec_recv_reg <= `INT_VEC_RECV_REG_45;
13133 end // }
13134 else if (`INT_VEC_RECV_ASIWR_45)
13135 int_vec_recv_reg <= `TOP.nas_top.c5.t5.asi_updated_int_rec;
13136
13137 if ((`NAS_PIPE_FW2_45 & int_vec_recv_reg_delta ) |
13138 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
13139 `INT_VEC_RECV_ASIWR_45 ) begin // {
13140 `PR_INFO ("pli_int", `INFO,
13141 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
13142 mycid,mytid, int_vec_recv_reg);
13143 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13144 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
13145 64'h0, int_vec_recv_reg);
13146 end // }
13147 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_45 &
13148 (int_vec_recv_reg !== `INT_VEC_RECV_REG_45 ))))
13149 int_vec_recv_reg_delta <= 1'b0;
13150 end //}
13151
13152 int_vec_reg_rdwr <= `INT_VEC_RDWR_45 | `INT_VEC_RECV_ASIWR_45;
13153 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_45 & ~ inc_vec_reg_rd;
13154
13155 if (`INT_VEC_RECV_ASIWR_45)
13156 inc_vec_reg_rd <= 1'b1;
13157 if (`NAS_PIPE_FW2_45)
13158 inc_vec_reg_rd <= 1'b0;
13159
13160
13161/////////////////////////// Vectored Interrupt /////////////////////////// }}}
13162
13163/////////////////////////// Asynchronous Resets ////////////////////////// {{{
13164
13165
13166/////////////////////////// Asynchronous Resets ////////////////////////// }}}
13167
13168/////////////////////////// Softint ///////////////////////////////////// {{{
13169
13170 // Softint Register hardware Update Detection
13171
13172 // Non software updates (TM/SM)
13173
13174 // If any read occurs, send value right away.
13175 // While a read/write is pending, do not update delta.
13176 // Send non read/wr delta during fw2 ..
13177
13178 // RTL keeps pic_ovf indication in rd_softint and not softint.
13179 // So for set/clear writes, we send softint before the write ..,
13180 // and for read/asyncs we send rd_softint ..
13181
13182
13183 if (~`SOFTINT_RDWR_45) begin // {
13184 if (softint !== `RD_SOFTINT_REG_45 )
13185 softint_delta <= 1'b1;
13186 softint <= `RD_SOFTINT_REG_45;
13187 end // }
13188
13189 if ((`NAS_PIPE_FW2_45 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
13190 ) begin // {
13191 `PR_INFO ("pli_int", `INFO,
13192 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
13193 mycid,mytid, {47'h0, softint});
13194 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13195 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
13196 {47'h0, softint});
13197 end // }
13198 if (!(~`SOFTINT_RDWR_45&(softint !== `RD_SOFTINT_REG_45)))
13199 softint_delta <= 1'b0;
13200 end //}
13201 else if (`SPC5.tlu.asi_wr_clear_softint[5] |
13202 `SPC5.tlu.asi_wr_set_softint[5] ) begin // {
13203 `PR_INFO ("pli_int", `INFO,
13204 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
13205 mycid,mytid, {47'h0, `RD_SOFTINT_REG_45});
13206 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13207 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
13208 {47'h0, `RD_SOFTINT_REG_45});
13209 end // }
13210 end //}
13211
13212
13213 softint_rdwr <= `SOFTINT_RDWR_45 ;
13214 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_45;
13215
13216
13217/////////////////////////// Softint ///////////////////////////////////// }}}
13218
13219/////////////////////////// Hintp ///////////////////////////////////// {{{
13220
13221 // Hintp Register hardware Update Detection
13222
13223 // Non software updates (HSP)
13224 // If HINTP is already read/written by SW, then don't send
13225 // any async updates to Nas. Reads/Writes pending sstep is detected
13226 // by snooping nas_pipe ..
13227
13228 hintp <= `HINTP_REG_45 ;
13229 if (hstmatch_late)
13230 hintp_delta <= 1'b1;
13231
13232 if ((~hintp_rdwr & `NAS_PIPE_FW2_45 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
13233 (hintp_rdwr_late & hintp_delta) ) begin // {
13234 `PR_INFO ("pli_int", `INFO,
13235 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
13236 mycid,mytid, {63'h0, hintp});
13237 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13238 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
13239 {63'h0, hintp});
13240 end // }
13241 if (~(hintp_rdwr_late & hintp_delta))
13242 hintp_delta <= 1'b0;
13243 end //}
13244
13245 hintp_rdwr <= `HINTP_RDWR_45;
13246 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_45;
13247 hstmatch_late <= `HSTMATCH_45;
13248
13249
13250/////////////////////////// Hintp ///////////////////////////////////// }}}
13251
13252end //}
13253`endif
13254endmodule
13255
13256// }}}
13257
13258module int_c5t6 ();
13259`ifndef GATESIM
13260
13261// common defines
13262`include "defines.vh"
13263`include "ccx.vri"
13264`include "cmp.vri"
13265
13266wire [2:0] mycid;
13267wire [2:0] mytid;
13268wire [5:0] mytnum;
13269integer junk;
13270
13271reg [63:0] int_vec_recv_reg;
13272reg int_vec_recv_reg_delta;
13273reg int_vec_reg_rdwr;
13274reg inc_vec_reg_rd;
13275reg int_vec_reg_rdwr_late;
13276reg [16:0] softint;
13277reg softint_rdwr;
13278reg softint_rdwr_late;
13279reg softint_delta;
13280reg hintp;
13281reg hintp_rdwr;
13282reg hintp_rdwr_late;
13283reg hintp_delta;
13284reg hstmatch_late;
13285reg ready;
13286reg [7:0] int_num_w;
13287reg [7:0] int_num_fx4;
13288reg [7:0] int_num_fx5;
13289reg [7:0] int_num_fb;
13290reg [7:0] int_num_fw;
13291reg [7:0] int_num_fw1;
13292reg [7:0] int_num_fw2;
13293reg take_disrupting_w;
13294reg take_disrupting_fx4;
13295reg take_disrupting_fx5;
13296reg take_disrupting_fb;
13297reg take_disrupting_fw;
13298reg take_disrupting_fw1;
13299reg take_disrupting_fw2;
13300
13301 assign mycid = 5;
13302 assign mytid = 6;
13303 assign mytnum = 5*8 + 6;
13304
13305initial begin // {
13306 ready = 0; // Wait for socket setup ..
13307 inc_vec_reg_rd <= 1'b0;
13308 int_vec_recv_reg_delta <= 1'b0;
13309 softint_delta <= 1'b0;
13310 hintp_delta <= 1'b0;
13311 int_vec_recv_reg = 64'b0;
13312 @(posedge `BENCH_SPC5_GCLK) ;
13313 @(posedge `BENCH_SPC5_GCLK) ;
13314 ready = `PARGS.int_sync_on;
13315end //}
13316
13317
13318/////////////////////////////// Probes //////////////////////////////////// {{{
13319
13320`define INT_VEC_RECV_REG_46 `SPC5.tlu.cth.int_rec6
13321`define INT_VEC_RECV_ASIWR_46 (`TOP.nas_top.c5.t6.asi_wr_int_rec_delay)
13322`define INT_VEC_RDWR_46 (`TOP.nas_top.c5.t6.asi_rdwr_int_rec)
13323`define INT_VEC_TAKEN_46 `SPC5.tlu.trl1.take_ivt&`SPC5.tlu.trl1.trap[2]
13324
13325`define CPU_MONDO_TAKEN_46 `SPC5.tlu.trl1.take_mqr&`SPC5.tlu.trl1.trap[2]
13326`define DEV_MONDO_TAKEN_46 `SPC5.tlu.trl1.take_dqr&`SPC5.tlu.trl1.trap[2]
13327`define RES_MONDO_TAKEN_46 `SPC5.tlu.trl1.take_rqr&`SPC5.tlu.trl1.trap[2]
13328
13329`define XIR_TAKEN_46 `SPC5.tlu.trl1.take_xir&`SPC5.tlu.trl1.trap[2]
13330
13331`define SOFTINT_RDWR_46 (`TOP.nas_top.c5.t6.asi_rdwr_softint|`TOP.nas_top.c5.t6.asi_wr_softint_delay)
13332
13333`define SOFTINT_REG_46 `SPC5.tlu.trl1.softint2
13334`define RD_SOFTINT_REG_46 `SPC5.tlu.trl1.rd_softint2
13335`define INT_LEVEL_TAKEN_46 `SPC5.tlu.trl1.take_iln&`SPC5.tlu.trl1.trap[2]
13336`define INT_LEVEL_NUM_46 `SPC5.tlu.trl1.int_level_n
13337`define PMU_TAKEN_46 `SPC5.tlu.trl1.take_pmu&`SPC5.tlu.trl1.trap[2]
13338
13339`define HINTP_RDWR_46 (`TOP.nas_top.c5.t6.asi_rdwr_hintp | `TOP.nas_top.c5.t6.asi_wr_hintp_delay)
13340`define HINTP_WR_46 (`SPC5.tlu.asi_wr_hintp[46])
13341`define HSTMATCH_46 `SPC5.tlu.trl1.hstick2_compare
13342
13343`define HINTP_REG_46 `SPC5.tlu.trl1.hintp2
13344`define HSTM_TAKEN_46 `SPC5.tlu.trl1.take_hst&`SPC5.tlu.trl1.trap[2]
13345
13346`define NAS_PIPE_FW2_46 |`TOP.nas_top.c5.t6.complete_fw2
13347
13348`define CWQ_TAKEN_46 `SPC5.tlu.trl1.take_cwq&`SPC5.tlu.trl1.trap[2]
13349`define SMA_TAKEN_46 `SPC5.tlu.trl1.take_sma&`SPC5.tlu.trl1.trap[2]
13350
13351`define POR_TAKEN_46 `SPC5.tlu.trl1.take_por&`SPC5.tlu.trl1.trap[2]
13352
13353/////////////////////////////// Probes //////////////////////////////////// }}}
13354
13355always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
13356
13357 // {{{ DETECT, PIPE & SEND
13358 take_disrupting_w <= (`INT_VEC_TAKEN_46 || `CPU_MONDO_TAKEN_46 ||
13359 `DEV_MONDO_TAKEN_46 || `RES_MONDO_TAKEN_46 ||
13360 `XIR_TAKEN_46 || `INT_LEVEL_TAKEN_46 ||
13361 `HSTM_TAKEN_46 || `CWQ_TAKEN_46 ||
13362 `SMA_TAKEN_46 || `PMU_TAKEN_46 || `POR_TAKEN_46);
13363 take_disrupting_fx4 <= take_disrupting_w;
13364 take_disrupting_fx5 <= take_disrupting_fx4;
13365 take_disrupting_fb <= take_disrupting_fx5;
13366 take_disrupting_fw <= take_disrupting_fb;
13367 take_disrupting_fw1 <= take_disrupting_fw;
13368 take_disrupting_fw2 <= take_disrupting_fw1;
13369
13370 case ({`INT_VEC_TAKEN_46, `CPU_MONDO_TAKEN_46,
13371 `DEV_MONDO_TAKEN_46, `RES_MONDO_TAKEN_46,
13372 `XIR_TAKEN_46, `INT_LEVEL_TAKEN_46,
13373 `HSTM_TAKEN_46, `CWQ_TAKEN_46, `SMA_TAKEN_46 ,
13374 `PMU_TAKEN_46, `POR_TAKEN_46})
13375 11'b10000000000: int_num_w <= 8'h60;
13376 11'b01000000000: int_num_w <= 8'h7c;
13377 11'b00100000000: int_num_w <= 8'h7d;
13378 11'b00010000000: int_num_w <= 8'h7e;
13379 11'b00001000000: int_num_w <= 8'h03;
13380 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_46;
13381 11'b00000010000: int_num_w <= 8'h5e;
13382 11'b00000001000: int_num_w <= 8'h3c;
13383 11'b00000000100: int_num_w <= 8'h3d;
13384 11'b00000000010: int_num_w <= 8'h4f;
13385 11'b00000000001: int_num_w <= 8'h01;
13386 endcase
13387
13388 int_num_fx4 <= int_num_w;
13389 int_num_fx5 <= int_num_fx4;
13390 int_num_fb <= int_num_fx5;
13391 int_num_fw <= int_num_fb;
13392 int_num_fw1 <= int_num_fw;
13393 int_num_fw2 <= int_num_fw1;
13394 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
13395 begin // {
13396 `PR_INFO ("pli_int", `INFO,
13397 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
13398 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13399 end // }
13400
13401 // }}}
13402
13403/////////////////////////// Vectored Interrupt /////////////////////////// {{{
13404
13405 // Vectored Interrupt Recv Register Detection
13406 // Indicate when register changes due to arriving interrupt, and not
13407 // due to read of incoming register or ASI write ..
13408
13409
13410 // If any read occurs, send value right away.
13411 // While a read/write is pending, do not update delta.
13412 // Send non read/wr delta during fw2 ..
13413
13414
13415 if (!(`INT_VEC_RDWR_46 | `INT_VEC_RECV_ASIWR_46)) begin // {
13416 if (~`INT_VEC_RECV_ASIWR_46 &
13417 (int_vec_recv_reg !== `INT_VEC_RECV_REG_46 ))
13418 int_vec_recv_reg_delta <= 1'b1;
13419 int_vec_recv_reg <= `INT_VEC_RECV_REG_46;
13420 end // }
13421 else if (`INT_VEC_RECV_ASIWR_46)
13422 int_vec_recv_reg <= `TOP.nas_top.c5.t6.asi_updated_int_rec;
13423
13424 if ((`NAS_PIPE_FW2_46 & int_vec_recv_reg_delta ) |
13425 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
13426 `INT_VEC_RECV_ASIWR_46 ) begin // {
13427 `PR_INFO ("pli_int", `INFO,
13428 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
13429 mycid,mytid, int_vec_recv_reg);
13430 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13431 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
13432 64'h0, int_vec_recv_reg);
13433 end // }
13434 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_46 &
13435 (int_vec_recv_reg !== `INT_VEC_RECV_REG_46 ))))
13436 int_vec_recv_reg_delta <= 1'b0;
13437 end //}
13438
13439 int_vec_reg_rdwr <= `INT_VEC_RDWR_46 | `INT_VEC_RECV_ASIWR_46;
13440 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_46 & ~ inc_vec_reg_rd;
13441
13442 if (`INT_VEC_RECV_ASIWR_46)
13443 inc_vec_reg_rd <= 1'b1;
13444 if (`NAS_PIPE_FW2_46)
13445 inc_vec_reg_rd <= 1'b0;
13446
13447
13448/////////////////////////// Vectored Interrupt /////////////////////////// }}}
13449
13450/////////////////////////// Asynchronous Resets ////////////////////////// {{{
13451
13452
13453/////////////////////////// Asynchronous Resets ////////////////////////// }}}
13454
13455/////////////////////////// Softint ///////////////////////////////////// {{{
13456
13457 // Softint Register hardware Update Detection
13458
13459 // Non software updates (TM/SM)
13460
13461 // If any read occurs, send value right away.
13462 // While a read/write is pending, do not update delta.
13463 // Send non read/wr delta during fw2 ..
13464
13465 // RTL keeps pic_ovf indication in rd_softint and not softint.
13466 // So for set/clear writes, we send softint before the write ..,
13467 // and for read/asyncs we send rd_softint ..
13468
13469
13470 if (~`SOFTINT_RDWR_46) begin // {
13471 if (softint !== `RD_SOFTINT_REG_46 )
13472 softint_delta <= 1'b1;
13473 softint <= `RD_SOFTINT_REG_46;
13474 end // }
13475
13476 if ((`NAS_PIPE_FW2_46 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
13477 ) begin // {
13478 `PR_INFO ("pli_int", `INFO,
13479 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
13480 mycid,mytid, {47'h0, softint});
13481 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13482 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
13483 {47'h0, softint});
13484 end // }
13485 if (!(~`SOFTINT_RDWR_46&(softint !== `RD_SOFTINT_REG_46)))
13486 softint_delta <= 1'b0;
13487 end //}
13488 else if (`SPC5.tlu.asi_wr_clear_softint[6] |
13489 `SPC5.tlu.asi_wr_set_softint[6] ) begin // {
13490 `PR_INFO ("pli_int", `INFO,
13491 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
13492 mycid,mytid, {47'h0, `RD_SOFTINT_REG_46});
13493 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13494 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
13495 {47'h0, `RD_SOFTINT_REG_46});
13496 end // }
13497 end //}
13498
13499
13500 softint_rdwr <= `SOFTINT_RDWR_46 ;
13501 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_46;
13502
13503
13504/////////////////////////// Softint ///////////////////////////////////// }}}
13505
13506/////////////////////////// Hintp ///////////////////////////////////// {{{
13507
13508 // Hintp Register hardware Update Detection
13509
13510 // Non software updates (HSP)
13511 // If HINTP is already read/written by SW, then don't send
13512 // any async updates to Nas. Reads/Writes pending sstep is detected
13513 // by snooping nas_pipe ..
13514
13515 hintp <= `HINTP_REG_46 ;
13516 if (hstmatch_late)
13517 hintp_delta <= 1'b1;
13518
13519 if ((~hintp_rdwr & `NAS_PIPE_FW2_46 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
13520 (hintp_rdwr_late & hintp_delta) ) begin // {
13521 `PR_INFO ("pli_int", `INFO,
13522 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
13523 mycid,mytid, {63'h0, hintp});
13524 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13525 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
13526 {63'h0, hintp});
13527 end // }
13528 if (~(hintp_rdwr_late & hintp_delta))
13529 hintp_delta <= 1'b0;
13530 end //}
13531
13532 hintp_rdwr <= `HINTP_RDWR_46;
13533 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_46;
13534 hstmatch_late <= `HSTMATCH_46;
13535
13536
13537/////////////////////////// Hintp ///////////////////////////////////// }}}
13538
13539end //}
13540`endif
13541endmodule
13542
13543// }}}
13544
13545module int_c5t7 ();
13546`ifndef GATESIM
13547
13548// common defines
13549`include "defines.vh"
13550`include "ccx.vri"
13551`include "cmp.vri"
13552
13553wire [2:0] mycid;
13554wire [2:0] mytid;
13555wire [5:0] mytnum;
13556integer junk;
13557
13558reg [63:0] int_vec_recv_reg;
13559reg int_vec_recv_reg_delta;
13560reg int_vec_reg_rdwr;
13561reg inc_vec_reg_rd;
13562reg int_vec_reg_rdwr_late;
13563reg [16:0] softint;
13564reg softint_rdwr;
13565reg softint_rdwr_late;
13566reg softint_delta;
13567reg hintp;
13568reg hintp_rdwr;
13569reg hintp_rdwr_late;
13570reg hintp_delta;
13571reg hstmatch_late;
13572reg ready;
13573reg [7:0] int_num_w;
13574reg [7:0] int_num_fx4;
13575reg [7:0] int_num_fx5;
13576reg [7:0] int_num_fb;
13577reg [7:0] int_num_fw;
13578reg [7:0] int_num_fw1;
13579reg [7:0] int_num_fw2;
13580reg take_disrupting_w;
13581reg take_disrupting_fx4;
13582reg take_disrupting_fx5;
13583reg take_disrupting_fb;
13584reg take_disrupting_fw;
13585reg take_disrupting_fw1;
13586reg take_disrupting_fw2;
13587
13588 assign mycid = 5;
13589 assign mytid = 7;
13590 assign mytnum = 5*8 + 7;
13591
13592initial begin // {
13593 ready = 0; // Wait for socket setup ..
13594 inc_vec_reg_rd <= 1'b0;
13595 int_vec_recv_reg_delta <= 1'b0;
13596 softint_delta <= 1'b0;
13597 hintp_delta <= 1'b0;
13598 int_vec_recv_reg = 64'b0;
13599 @(posedge `BENCH_SPC5_GCLK) ;
13600 @(posedge `BENCH_SPC5_GCLK) ;
13601 ready = `PARGS.int_sync_on;
13602end //}
13603
13604
13605/////////////////////////////// Probes //////////////////////////////////// {{{
13606
13607`define INT_VEC_RECV_REG_47 `SPC5.tlu.cth.int_rec7
13608`define INT_VEC_RECV_ASIWR_47 (`TOP.nas_top.c5.t7.asi_wr_int_rec_delay)
13609`define INT_VEC_RDWR_47 (`TOP.nas_top.c5.t7.asi_rdwr_int_rec)
13610`define INT_VEC_TAKEN_47 `SPC5.tlu.trl1.take_ivt&`SPC5.tlu.trl1.trap[3]
13611
13612`define CPU_MONDO_TAKEN_47 `SPC5.tlu.trl1.take_mqr&`SPC5.tlu.trl1.trap[3]
13613`define DEV_MONDO_TAKEN_47 `SPC5.tlu.trl1.take_dqr&`SPC5.tlu.trl1.trap[3]
13614`define RES_MONDO_TAKEN_47 `SPC5.tlu.trl1.take_rqr&`SPC5.tlu.trl1.trap[3]
13615
13616`define XIR_TAKEN_47 `SPC5.tlu.trl1.take_xir&`SPC5.tlu.trl1.trap[3]
13617
13618`define SOFTINT_RDWR_47 (`TOP.nas_top.c5.t7.asi_rdwr_softint|`TOP.nas_top.c5.t7.asi_wr_softint_delay)
13619
13620`define SOFTINT_REG_47 `SPC5.tlu.trl1.softint3
13621`define RD_SOFTINT_REG_47 `SPC5.tlu.trl1.rd_softint3
13622`define INT_LEVEL_TAKEN_47 `SPC5.tlu.trl1.take_iln&`SPC5.tlu.trl1.trap[3]
13623`define INT_LEVEL_NUM_47 `SPC5.tlu.trl1.int_level_n
13624`define PMU_TAKEN_47 `SPC5.tlu.trl1.take_pmu&`SPC5.tlu.trl1.trap[3]
13625
13626`define HINTP_RDWR_47 (`TOP.nas_top.c5.t7.asi_rdwr_hintp | `TOP.nas_top.c5.t7.asi_wr_hintp_delay)
13627`define HINTP_WR_47 (`SPC5.tlu.asi_wr_hintp[47])
13628`define HSTMATCH_47 `SPC5.tlu.trl1.hstick3_compare
13629
13630`define HINTP_REG_47 `SPC5.tlu.trl1.hintp3
13631`define HSTM_TAKEN_47 `SPC5.tlu.trl1.take_hst&`SPC5.tlu.trl1.trap[3]
13632
13633`define NAS_PIPE_FW2_47 |`TOP.nas_top.c5.t7.complete_fw2
13634
13635`define CWQ_TAKEN_47 `SPC5.tlu.trl1.take_cwq&`SPC5.tlu.trl1.trap[3]
13636`define SMA_TAKEN_47 `SPC5.tlu.trl1.take_sma&`SPC5.tlu.trl1.trap[3]
13637
13638`define POR_TAKEN_47 `SPC5.tlu.trl1.take_por&`SPC5.tlu.trl1.trap[3]
13639
13640/////////////////////////////// Probes //////////////////////////////////// }}}
13641
13642always @(negedge (`BENCH_SPC5_GCLK & ready)) begin // {
13643
13644 // {{{ DETECT, PIPE & SEND
13645 take_disrupting_w <= (`INT_VEC_TAKEN_47 || `CPU_MONDO_TAKEN_47 ||
13646 `DEV_MONDO_TAKEN_47 || `RES_MONDO_TAKEN_47 ||
13647 `XIR_TAKEN_47 || `INT_LEVEL_TAKEN_47 ||
13648 `HSTM_TAKEN_47 || `CWQ_TAKEN_47 ||
13649 `SMA_TAKEN_47 || `PMU_TAKEN_47 || `POR_TAKEN_47);
13650 take_disrupting_fx4 <= take_disrupting_w;
13651 take_disrupting_fx5 <= take_disrupting_fx4;
13652 take_disrupting_fb <= take_disrupting_fx5;
13653 take_disrupting_fw <= take_disrupting_fb;
13654 take_disrupting_fw1 <= take_disrupting_fw;
13655 take_disrupting_fw2 <= take_disrupting_fw1;
13656
13657 case ({`INT_VEC_TAKEN_47, `CPU_MONDO_TAKEN_47,
13658 `DEV_MONDO_TAKEN_47, `RES_MONDO_TAKEN_47,
13659 `XIR_TAKEN_47, `INT_LEVEL_TAKEN_47,
13660 `HSTM_TAKEN_47, `CWQ_TAKEN_47, `SMA_TAKEN_47 ,
13661 `PMU_TAKEN_47, `POR_TAKEN_47})
13662 11'b10000000000: int_num_w <= 8'h60;
13663 11'b01000000000: int_num_w <= 8'h7c;
13664 11'b00100000000: int_num_w <= 8'h7d;
13665 11'b00010000000: int_num_w <= 8'h7e;
13666 11'b00001000000: int_num_w <= 8'h03;
13667 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_47;
13668 11'b00000010000: int_num_w <= 8'h5e;
13669 11'b00000001000: int_num_w <= 8'h3c;
13670 11'b00000000100: int_num_w <= 8'h3d;
13671 11'b00000000010: int_num_w <= 8'h4f;
13672 11'b00000000001: int_num_w <= 8'h01;
13673 endcase
13674
13675 int_num_fx4 <= int_num_w;
13676 int_num_fx5 <= int_num_fx4;
13677 int_num_fb <= int_num_fx5;
13678 int_num_fw <= int_num_fb;
13679 int_num_fw1 <= int_num_fw;
13680 int_num_fw2 <= int_num_fw1;
13681 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
13682 begin // {
13683 `PR_INFO ("pli_int", `INFO,
13684 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
13685 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13686 end // }
13687
13688 // }}}
13689
13690/////////////////////////// Vectored Interrupt /////////////////////////// {{{
13691
13692 // Vectored Interrupt Recv Register Detection
13693 // Indicate when register changes due to arriving interrupt, and not
13694 // due to read of incoming register or ASI write ..
13695
13696
13697 // If any read occurs, send value right away.
13698 // While a read/write is pending, do not update delta.
13699 // Send non read/wr delta during fw2 ..
13700
13701
13702 if (!(`INT_VEC_RDWR_47 | `INT_VEC_RECV_ASIWR_47)) begin // {
13703 if (~`INT_VEC_RECV_ASIWR_47 &
13704 (int_vec_recv_reg !== `INT_VEC_RECV_REG_47 ))
13705 int_vec_recv_reg_delta <= 1'b1;
13706 int_vec_recv_reg <= `INT_VEC_RECV_REG_47;
13707 end // }
13708 else if (`INT_VEC_RECV_ASIWR_47)
13709 int_vec_recv_reg <= `TOP.nas_top.c5.t7.asi_updated_int_rec;
13710
13711 if ((`NAS_PIPE_FW2_47 & int_vec_recv_reg_delta ) |
13712 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
13713 `INT_VEC_RECV_ASIWR_47 ) begin // {
13714 `PR_INFO ("pli_int", `INFO,
13715 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
13716 mycid,mytid, int_vec_recv_reg);
13717 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13718 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
13719 64'h0, int_vec_recv_reg);
13720 end // }
13721 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_47 &
13722 (int_vec_recv_reg !== `INT_VEC_RECV_REG_47 ))))
13723 int_vec_recv_reg_delta <= 1'b0;
13724 end //}
13725
13726 int_vec_reg_rdwr <= `INT_VEC_RDWR_47 | `INT_VEC_RECV_ASIWR_47;
13727 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_47 & ~ inc_vec_reg_rd;
13728
13729 if (`INT_VEC_RECV_ASIWR_47)
13730 inc_vec_reg_rd <= 1'b1;
13731 if (`NAS_PIPE_FW2_47)
13732 inc_vec_reg_rd <= 1'b0;
13733
13734
13735/////////////////////////// Vectored Interrupt /////////////////////////// }}}
13736
13737/////////////////////////// Asynchronous Resets ////////////////////////// {{{
13738
13739
13740/////////////////////////// Asynchronous Resets ////////////////////////// }}}
13741
13742/////////////////////////// Softint ///////////////////////////////////// {{{
13743
13744 // Softint Register hardware Update Detection
13745
13746 // Non software updates (TM/SM)
13747
13748 // If any read occurs, send value right away.
13749 // While a read/write is pending, do not update delta.
13750 // Send non read/wr delta during fw2 ..
13751
13752 // RTL keeps pic_ovf indication in rd_softint and not softint.
13753 // So for set/clear writes, we send softint before the write ..,
13754 // and for read/asyncs we send rd_softint ..
13755
13756
13757 if (~`SOFTINT_RDWR_47) begin // {
13758 if (softint !== `RD_SOFTINT_REG_47 )
13759 softint_delta <= 1'b1;
13760 softint <= `RD_SOFTINT_REG_47;
13761 end // }
13762
13763 if ((`NAS_PIPE_FW2_47 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
13764 ) begin // {
13765 `PR_INFO ("pli_int", `INFO,
13766 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
13767 mycid,mytid, {47'h0, softint});
13768 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13769 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
13770 {47'h0, softint});
13771 end // }
13772 if (!(~`SOFTINT_RDWR_47&(softint !== `RD_SOFTINT_REG_47)))
13773 softint_delta <= 1'b0;
13774 end //}
13775 else if (`SPC5.tlu.asi_wr_clear_softint[7] |
13776 `SPC5.tlu.asi_wr_set_softint[7] ) begin // {
13777 `PR_INFO ("pli_int", `INFO,
13778 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
13779 mycid,mytid, {47'h0, `RD_SOFTINT_REG_47});
13780 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13781 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
13782 {47'h0, `RD_SOFTINT_REG_47});
13783 end // }
13784 end //}
13785
13786
13787 softint_rdwr <= `SOFTINT_RDWR_47 ;
13788 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_47;
13789
13790
13791/////////////////////////// Softint ///////////////////////////////////// }}}
13792
13793/////////////////////////// Hintp ///////////////////////////////////// {{{
13794
13795 // Hintp Register hardware Update Detection
13796
13797 // Non software updates (HSP)
13798 // If HINTP is already read/written by SW, then don't send
13799 // any async updates to Nas. Reads/Writes pending sstep is detected
13800 // by snooping nas_pipe ..
13801
13802 hintp <= `HINTP_REG_47 ;
13803 if (hstmatch_late)
13804 hintp_delta <= 1'b1;
13805
13806 if ((~hintp_rdwr & `NAS_PIPE_FW2_47 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
13807 (hintp_rdwr_late & hintp_delta) ) begin // {
13808 `PR_INFO ("pli_int", `INFO,
13809 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
13810 mycid,mytid, {63'h0, hintp});
13811 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
13812 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
13813 {63'h0, hintp});
13814 end // }
13815 if (~(hintp_rdwr_late & hintp_delta))
13816 hintp_delta <= 1'b0;
13817 end //}
13818
13819 hintp_rdwr <= `HINTP_RDWR_47;
13820 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_47;
13821 hstmatch_late <= `HSTMATCH_47;
13822
13823
13824/////////////////////////// Hintp ///////////////////////////////////// }}}
13825
13826end //}
13827`endif
13828endmodule
13829
13830`endif
13831`ifdef CORE_6
13832
13833// }}}
13834
13835module int_c6t0 ();
13836`ifndef GATESIM
13837
13838// common defines
13839`include "defines.vh"
13840`include "ccx.vri"
13841`include "cmp.vri"
13842
13843wire [2:0] mycid;
13844wire [2:0] mytid;
13845wire [5:0] mytnum;
13846integer junk;
13847
13848reg [63:0] int_vec_recv_reg;
13849reg int_vec_recv_reg_delta;
13850reg int_vec_reg_rdwr;
13851reg inc_vec_reg_rd;
13852reg int_vec_reg_rdwr_late;
13853reg [16:0] softint;
13854reg softint_rdwr;
13855reg softint_rdwr_late;
13856reg softint_delta;
13857reg hintp;
13858reg hintp_rdwr;
13859reg hintp_rdwr_late;
13860reg hintp_delta;
13861reg hstmatch_late;
13862reg ready;
13863reg [7:0] int_num_w;
13864reg [7:0] int_num_fx4;
13865reg [7:0] int_num_fx5;
13866reg [7:0] int_num_fb;
13867reg [7:0] int_num_fw;
13868reg [7:0] int_num_fw1;
13869reg [7:0] int_num_fw2;
13870reg take_disrupting_w;
13871reg take_disrupting_fx4;
13872reg take_disrupting_fx5;
13873reg take_disrupting_fb;
13874reg take_disrupting_fw;
13875reg take_disrupting_fw1;
13876reg take_disrupting_fw2;
13877
13878 assign mycid = 6;
13879 assign mytid = 0;
13880 assign mytnum = 6*8 + 0;
13881
13882initial begin // {
13883 ready = 0; // Wait for socket setup ..
13884 inc_vec_reg_rd <= 1'b0;
13885 int_vec_recv_reg_delta <= 1'b0;
13886 softint_delta <= 1'b0;
13887 hintp_delta <= 1'b0;
13888 int_vec_recv_reg = 64'b0;
13889 @(posedge `BENCH_SPC6_GCLK) ;
13890 @(posedge `BENCH_SPC6_GCLK) ;
13891 ready = `PARGS.int_sync_on;
13892end //}
13893
13894
13895/////////////////////////////// Probes //////////////////////////////////// {{{
13896
13897`define INT_VEC_RECV_REG_48 `SPC6.tlu.cth.int_rec0
13898`define INT_VEC_RECV_ASIWR_48 (`TOP.nas_top.c6.t0.asi_wr_int_rec_delay)
13899`define INT_VEC_RDWR_48 (`TOP.nas_top.c6.t0.asi_rdwr_int_rec)
13900`define INT_VEC_TAKEN_48 `SPC6.tlu.trl0.take_ivt&`SPC6.tlu.trl0.trap[0]
13901
13902`define CPU_MONDO_TAKEN_48 `SPC6.tlu.trl0.take_mqr&`SPC6.tlu.trl0.trap[0]
13903`define DEV_MONDO_TAKEN_48 `SPC6.tlu.trl0.take_dqr&`SPC6.tlu.trl0.trap[0]
13904`define RES_MONDO_TAKEN_48 `SPC6.tlu.trl0.take_rqr&`SPC6.tlu.trl0.trap[0]
13905
13906`define XIR_TAKEN_48 `SPC6.tlu.trl0.take_xir&`SPC6.tlu.trl0.trap[0]
13907
13908`define SOFTINT_RDWR_48 (`TOP.nas_top.c6.t0.asi_rdwr_softint|`TOP.nas_top.c6.t0.asi_wr_softint_delay)
13909
13910`define SOFTINT_REG_48 `SPC6.tlu.trl0.softint0
13911`define RD_SOFTINT_REG_48 `SPC6.tlu.trl0.rd_softint0
13912`define INT_LEVEL_TAKEN_48 `SPC6.tlu.trl0.take_iln&`SPC6.tlu.trl0.trap[0]
13913`define INT_LEVEL_NUM_48 `SPC6.tlu.trl0.int_level_n
13914`define PMU_TAKEN_48 `SPC6.tlu.trl0.take_pmu&`SPC6.tlu.trl0.trap[0]
13915
13916`define HINTP_RDWR_48 (`TOP.nas_top.c6.t0.asi_rdwr_hintp | `TOP.nas_top.c6.t0.asi_wr_hintp_delay)
13917`define HINTP_WR_48 (`SPC6.tlu.asi_wr_hintp[48])
13918`define HSTMATCH_48 `SPC6.tlu.trl0.hstick0_compare
13919
13920`define HINTP_REG_48 `SPC6.tlu.trl0.hintp0
13921`define HSTM_TAKEN_48 `SPC6.tlu.trl0.take_hst&`SPC6.tlu.trl0.trap[0]
13922
13923`define NAS_PIPE_FW2_48 |`TOP.nas_top.c6.t0.complete_fw2
13924
13925`define CWQ_TAKEN_48 `SPC6.tlu.trl0.take_cwq&`SPC6.tlu.trl0.trap[0]
13926`define SMA_TAKEN_48 `SPC6.tlu.trl0.take_sma&`SPC6.tlu.trl0.trap[0]
13927
13928`define POR_TAKEN_48 `SPC6.tlu.trl0.take_por&`SPC6.tlu.trl0.trap[0]
13929
13930/////////////////////////////// Probes //////////////////////////////////// }}}
13931
13932always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
13933
13934 // {{{ DETECT, PIPE & SEND
13935 take_disrupting_w <= (`INT_VEC_TAKEN_48 || `CPU_MONDO_TAKEN_48 ||
13936 `DEV_MONDO_TAKEN_48 || `RES_MONDO_TAKEN_48 ||
13937 `XIR_TAKEN_48 || `INT_LEVEL_TAKEN_48 ||
13938 `HSTM_TAKEN_48 || `CWQ_TAKEN_48 ||
13939 `SMA_TAKEN_48 || `PMU_TAKEN_48 || `POR_TAKEN_48);
13940 take_disrupting_fx4 <= take_disrupting_w;
13941 take_disrupting_fx5 <= take_disrupting_fx4;
13942 take_disrupting_fb <= take_disrupting_fx5;
13943 take_disrupting_fw <= take_disrupting_fb;
13944 take_disrupting_fw1 <= take_disrupting_fw;
13945 take_disrupting_fw2 <= take_disrupting_fw1;
13946
13947 case ({`INT_VEC_TAKEN_48, `CPU_MONDO_TAKEN_48,
13948 `DEV_MONDO_TAKEN_48, `RES_MONDO_TAKEN_48,
13949 `XIR_TAKEN_48, `INT_LEVEL_TAKEN_48,
13950 `HSTM_TAKEN_48, `CWQ_TAKEN_48, `SMA_TAKEN_48 ,
13951 `PMU_TAKEN_48, `POR_TAKEN_48})
13952 11'b10000000000: int_num_w <= 8'h60;
13953 11'b01000000000: int_num_w <= 8'h7c;
13954 11'b00100000000: int_num_w <= 8'h7d;
13955 11'b00010000000: int_num_w <= 8'h7e;
13956 11'b00001000000: int_num_w <= 8'h03;
13957 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_48;
13958 11'b00000010000: int_num_w <= 8'h5e;
13959 11'b00000001000: int_num_w <= 8'h3c;
13960 11'b00000000100: int_num_w <= 8'h3d;
13961 11'b00000000010: int_num_w <= 8'h4f;
13962 11'b00000000001: int_num_w <= 8'h01;
13963 endcase
13964
13965 int_num_fx4 <= int_num_w;
13966 int_num_fx5 <= int_num_fx4;
13967 int_num_fb <= int_num_fx5;
13968 int_num_fw <= int_num_fb;
13969 int_num_fw1 <= int_num_fw;
13970 int_num_fw2 <= int_num_fw1;
13971 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
13972 begin // {
13973 `PR_INFO ("pli_int", `INFO,
13974 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
13975 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
13976 end // }
13977
13978 // }}}
13979
13980/////////////////////////// Vectored Interrupt /////////////////////////// {{{
13981
13982 // Vectored Interrupt Recv Register Detection
13983 // Indicate when register changes due to arriving interrupt, and not
13984 // due to read of incoming register or ASI write ..
13985
13986
13987 // If any read occurs, send value right away.
13988 // While a read/write is pending, do not update delta.
13989 // Send non read/wr delta during fw2 ..
13990
13991
13992 if (!(`INT_VEC_RDWR_48 | `INT_VEC_RECV_ASIWR_48)) begin // {
13993 if (~`INT_VEC_RECV_ASIWR_48 &
13994 (int_vec_recv_reg !== `INT_VEC_RECV_REG_48 ))
13995 int_vec_recv_reg_delta <= 1'b1;
13996 int_vec_recv_reg <= `INT_VEC_RECV_REG_48;
13997 end // }
13998 else if (`INT_VEC_RECV_ASIWR_48)
13999 int_vec_recv_reg <= `TOP.nas_top.c6.t0.asi_updated_int_rec;
14000
14001 if ((`NAS_PIPE_FW2_48 & int_vec_recv_reg_delta ) |
14002 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
14003 `INT_VEC_RECV_ASIWR_48 ) begin // {
14004 `PR_INFO ("pli_int", `INFO,
14005 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
14006 mycid,mytid, int_vec_recv_reg);
14007 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14008 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
14009 64'h0, int_vec_recv_reg);
14010 end // }
14011 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_48 &
14012 (int_vec_recv_reg !== `INT_VEC_RECV_REG_48 ))))
14013 int_vec_recv_reg_delta <= 1'b0;
14014 end //}
14015
14016 int_vec_reg_rdwr <= `INT_VEC_RDWR_48 | `INT_VEC_RECV_ASIWR_48;
14017 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_48 & ~ inc_vec_reg_rd;
14018
14019 if (`INT_VEC_RECV_ASIWR_48)
14020 inc_vec_reg_rd <= 1'b1;
14021 if (`NAS_PIPE_FW2_48)
14022 inc_vec_reg_rd <= 1'b0;
14023
14024
14025/////////////////////////// Vectored Interrupt /////////////////////////// }}}
14026
14027/////////////////////////// Asynchronous Resets ////////////////////////// {{{
14028
14029
14030/////////////////////////// Asynchronous Resets ////////////////////////// }}}
14031
14032/////////////////////////// Softint ///////////////////////////////////// {{{
14033
14034 // Softint Register hardware Update Detection
14035
14036 // Non software updates (TM/SM)
14037
14038 // If any read occurs, send value right away.
14039 // While a read/write is pending, do not update delta.
14040 // Send non read/wr delta during fw2 ..
14041
14042 // RTL keeps pic_ovf indication in rd_softint and not softint.
14043 // So for set/clear writes, we send softint before the write ..,
14044 // and for read/asyncs we send rd_softint ..
14045
14046
14047 if (~`SOFTINT_RDWR_48) begin // {
14048 if (softint !== `RD_SOFTINT_REG_48 )
14049 softint_delta <= 1'b1;
14050 softint <= `RD_SOFTINT_REG_48;
14051 end // }
14052
14053 if ((`NAS_PIPE_FW2_48 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
14054 ) begin // {
14055 `PR_INFO ("pli_int", `INFO,
14056 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14057 mycid,mytid, {47'h0, softint});
14058 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14059 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14060 {47'h0, softint});
14061 end // }
14062 if (!(~`SOFTINT_RDWR_48&(softint !== `RD_SOFTINT_REG_48)))
14063 softint_delta <= 1'b0;
14064 end //}
14065 else if (`SPC6.tlu.asi_wr_clear_softint[0] |
14066 `SPC6.tlu.asi_wr_set_softint[0] ) begin // {
14067 `PR_INFO ("pli_int", `INFO,
14068 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14069 mycid,mytid, {47'h0, `RD_SOFTINT_REG_48});
14070 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14071 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14072 {47'h0, `RD_SOFTINT_REG_48});
14073 end // }
14074 end //}
14075
14076
14077 softint_rdwr <= `SOFTINT_RDWR_48 ;
14078 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_48;
14079
14080
14081/////////////////////////// Softint ///////////////////////////////////// }}}
14082
14083/////////////////////////// Hintp ///////////////////////////////////// {{{
14084
14085 // Hintp Register hardware Update Detection
14086
14087 // Non software updates (HSP)
14088 // If HINTP is already read/written by SW, then don't send
14089 // any async updates to Nas. Reads/Writes pending sstep is detected
14090 // by snooping nas_pipe ..
14091
14092 hintp <= `HINTP_REG_48 ;
14093 if (hstmatch_late)
14094 hintp_delta <= 1'b1;
14095
14096 if ((~hintp_rdwr & `NAS_PIPE_FW2_48 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
14097 (hintp_rdwr_late & hintp_delta) ) begin // {
14098 `PR_INFO ("pli_int", `INFO,
14099 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
14100 mycid,mytid, {63'h0, hintp});
14101 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14102 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
14103 {63'h0, hintp});
14104 end // }
14105 if (~(hintp_rdwr_late & hintp_delta))
14106 hintp_delta <= 1'b0;
14107 end //}
14108
14109 hintp_rdwr <= `HINTP_RDWR_48;
14110 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_48;
14111 hstmatch_late <= `HSTMATCH_48;
14112
14113
14114/////////////////////////// Hintp ///////////////////////////////////// }}}
14115
14116end //}
14117`endif
14118endmodule
14119
14120// }}}
14121
14122module int_c6t1 ();
14123`ifndef GATESIM
14124
14125// common defines
14126`include "defines.vh"
14127`include "ccx.vri"
14128`include "cmp.vri"
14129
14130wire [2:0] mycid;
14131wire [2:0] mytid;
14132wire [5:0] mytnum;
14133integer junk;
14134
14135reg [63:0] int_vec_recv_reg;
14136reg int_vec_recv_reg_delta;
14137reg int_vec_reg_rdwr;
14138reg inc_vec_reg_rd;
14139reg int_vec_reg_rdwr_late;
14140reg [16:0] softint;
14141reg softint_rdwr;
14142reg softint_rdwr_late;
14143reg softint_delta;
14144reg hintp;
14145reg hintp_rdwr;
14146reg hintp_rdwr_late;
14147reg hintp_delta;
14148reg hstmatch_late;
14149reg ready;
14150reg [7:0] int_num_w;
14151reg [7:0] int_num_fx4;
14152reg [7:0] int_num_fx5;
14153reg [7:0] int_num_fb;
14154reg [7:0] int_num_fw;
14155reg [7:0] int_num_fw1;
14156reg [7:0] int_num_fw2;
14157reg take_disrupting_w;
14158reg take_disrupting_fx4;
14159reg take_disrupting_fx5;
14160reg take_disrupting_fb;
14161reg take_disrupting_fw;
14162reg take_disrupting_fw1;
14163reg take_disrupting_fw2;
14164
14165 assign mycid = 6;
14166 assign mytid = 1;
14167 assign mytnum = 6*8 + 1;
14168
14169initial begin // {
14170 ready = 0; // Wait for socket setup ..
14171 inc_vec_reg_rd <= 1'b0;
14172 int_vec_recv_reg_delta <= 1'b0;
14173 softint_delta <= 1'b0;
14174 hintp_delta <= 1'b0;
14175 int_vec_recv_reg = 64'b0;
14176 @(posedge `BENCH_SPC6_GCLK) ;
14177 @(posedge `BENCH_SPC6_GCLK) ;
14178 ready = `PARGS.int_sync_on;
14179end //}
14180
14181
14182/////////////////////////////// Probes //////////////////////////////////// {{{
14183
14184`define INT_VEC_RECV_REG_49 `SPC6.tlu.cth.int_rec1
14185`define INT_VEC_RECV_ASIWR_49 (`TOP.nas_top.c6.t1.asi_wr_int_rec_delay)
14186`define INT_VEC_RDWR_49 (`TOP.nas_top.c6.t1.asi_rdwr_int_rec)
14187`define INT_VEC_TAKEN_49 `SPC6.tlu.trl0.take_ivt&`SPC6.tlu.trl0.trap[1]
14188
14189`define CPU_MONDO_TAKEN_49 `SPC6.tlu.trl0.take_mqr&`SPC6.tlu.trl0.trap[1]
14190`define DEV_MONDO_TAKEN_49 `SPC6.tlu.trl0.take_dqr&`SPC6.tlu.trl0.trap[1]
14191`define RES_MONDO_TAKEN_49 `SPC6.tlu.trl0.take_rqr&`SPC6.tlu.trl0.trap[1]
14192
14193`define XIR_TAKEN_49 `SPC6.tlu.trl0.take_xir&`SPC6.tlu.trl0.trap[1]
14194
14195`define SOFTINT_RDWR_49 (`TOP.nas_top.c6.t1.asi_rdwr_softint|`TOP.nas_top.c6.t1.asi_wr_softint_delay)
14196
14197`define SOFTINT_REG_49 `SPC6.tlu.trl0.softint1
14198`define RD_SOFTINT_REG_49 `SPC6.tlu.trl0.rd_softint1
14199`define INT_LEVEL_TAKEN_49 `SPC6.tlu.trl0.take_iln&`SPC6.tlu.trl0.trap[1]
14200`define INT_LEVEL_NUM_49 `SPC6.tlu.trl0.int_level_n
14201`define PMU_TAKEN_49 `SPC6.tlu.trl0.take_pmu&`SPC6.tlu.trl0.trap[1]
14202
14203`define HINTP_RDWR_49 (`TOP.nas_top.c6.t1.asi_rdwr_hintp | `TOP.nas_top.c6.t1.asi_wr_hintp_delay)
14204`define HINTP_WR_49 (`SPC6.tlu.asi_wr_hintp[49])
14205`define HSTMATCH_49 `SPC6.tlu.trl0.hstick1_compare
14206
14207`define HINTP_REG_49 `SPC6.tlu.trl0.hintp1
14208`define HSTM_TAKEN_49 `SPC6.tlu.trl0.take_hst&`SPC6.tlu.trl0.trap[1]
14209
14210`define NAS_PIPE_FW2_49 |`TOP.nas_top.c6.t1.complete_fw2
14211
14212`define CWQ_TAKEN_49 `SPC6.tlu.trl0.take_cwq&`SPC6.tlu.trl0.trap[1]
14213`define SMA_TAKEN_49 `SPC6.tlu.trl0.take_sma&`SPC6.tlu.trl0.trap[1]
14214
14215`define POR_TAKEN_49 `SPC6.tlu.trl0.take_por&`SPC6.tlu.trl0.trap[1]
14216
14217/////////////////////////////// Probes //////////////////////////////////// }}}
14218
14219always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
14220
14221 // {{{ DETECT, PIPE & SEND
14222 take_disrupting_w <= (`INT_VEC_TAKEN_49 || `CPU_MONDO_TAKEN_49 ||
14223 `DEV_MONDO_TAKEN_49 || `RES_MONDO_TAKEN_49 ||
14224 `XIR_TAKEN_49 || `INT_LEVEL_TAKEN_49 ||
14225 `HSTM_TAKEN_49 || `CWQ_TAKEN_49 ||
14226 `SMA_TAKEN_49 || `PMU_TAKEN_49 || `POR_TAKEN_49);
14227 take_disrupting_fx4 <= take_disrupting_w;
14228 take_disrupting_fx5 <= take_disrupting_fx4;
14229 take_disrupting_fb <= take_disrupting_fx5;
14230 take_disrupting_fw <= take_disrupting_fb;
14231 take_disrupting_fw1 <= take_disrupting_fw;
14232 take_disrupting_fw2 <= take_disrupting_fw1;
14233
14234 case ({`INT_VEC_TAKEN_49, `CPU_MONDO_TAKEN_49,
14235 `DEV_MONDO_TAKEN_49, `RES_MONDO_TAKEN_49,
14236 `XIR_TAKEN_49, `INT_LEVEL_TAKEN_49,
14237 `HSTM_TAKEN_49, `CWQ_TAKEN_49, `SMA_TAKEN_49 ,
14238 `PMU_TAKEN_49, `POR_TAKEN_49})
14239 11'b10000000000: int_num_w <= 8'h60;
14240 11'b01000000000: int_num_w <= 8'h7c;
14241 11'b00100000000: int_num_w <= 8'h7d;
14242 11'b00010000000: int_num_w <= 8'h7e;
14243 11'b00001000000: int_num_w <= 8'h03;
14244 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_49;
14245 11'b00000010000: int_num_w <= 8'h5e;
14246 11'b00000001000: int_num_w <= 8'h3c;
14247 11'b00000000100: int_num_w <= 8'h3d;
14248 11'b00000000010: int_num_w <= 8'h4f;
14249 11'b00000000001: int_num_w <= 8'h01;
14250 endcase
14251
14252 int_num_fx4 <= int_num_w;
14253 int_num_fx5 <= int_num_fx4;
14254 int_num_fb <= int_num_fx5;
14255 int_num_fw <= int_num_fb;
14256 int_num_fw1 <= int_num_fw;
14257 int_num_fw2 <= int_num_fw1;
14258 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
14259 begin // {
14260 `PR_INFO ("pli_int", `INFO,
14261 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
14262 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
14263 end // }
14264
14265 // }}}
14266
14267/////////////////////////// Vectored Interrupt /////////////////////////// {{{
14268
14269 // Vectored Interrupt Recv Register Detection
14270 // Indicate when register changes due to arriving interrupt, and not
14271 // due to read of incoming register or ASI write ..
14272
14273
14274 // If any read occurs, send value right away.
14275 // While a read/write is pending, do not update delta.
14276 // Send non read/wr delta during fw2 ..
14277
14278
14279 if (!(`INT_VEC_RDWR_49 | `INT_VEC_RECV_ASIWR_49)) begin // {
14280 if (~`INT_VEC_RECV_ASIWR_49 &
14281 (int_vec_recv_reg !== `INT_VEC_RECV_REG_49 ))
14282 int_vec_recv_reg_delta <= 1'b1;
14283 int_vec_recv_reg <= `INT_VEC_RECV_REG_49;
14284 end // }
14285 else if (`INT_VEC_RECV_ASIWR_49)
14286 int_vec_recv_reg <= `TOP.nas_top.c6.t1.asi_updated_int_rec;
14287
14288 if ((`NAS_PIPE_FW2_49 & int_vec_recv_reg_delta ) |
14289 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
14290 `INT_VEC_RECV_ASIWR_49 ) begin // {
14291 `PR_INFO ("pli_int", `INFO,
14292 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
14293 mycid,mytid, int_vec_recv_reg);
14294 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14295 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
14296 64'h0, int_vec_recv_reg);
14297 end // }
14298 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_49 &
14299 (int_vec_recv_reg !== `INT_VEC_RECV_REG_49 ))))
14300 int_vec_recv_reg_delta <= 1'b0;
14301 end //}
14302
14303 int_vec_reg_rdwr <= `INT_VEC_RDWR_49 | `INT_VEC_RECV_ASIWR_49;
14304 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_49 & ~ inc_vec_reg_rd;
14305
14306 if (`INT_VEC_RECV_ASIWR_49)
14307 inc_vec_reg_rd <= 1'b1;
14308 if (`NAS_PIPE_FW2_49)
14309 inc_vec_reg_rd <= 1'b0;
14310
14311
14312/////////////////////////// Vectored Interrupt /////////////////////////// }}}
14313
14314/////////////////////////// Asynchronous Resets ////////////////////////// {{{
14315
14316
14317/////////////////////////// Asynchronous Resets ////////////////////////// }}}
14318
14319/////////////////////////// Softint ///////////////////////////////////// {{{
14320
14321 // Softint Register hardware Update Detection
14322
14323 // Non software updates (TM/SM)
14324
14325 // If any read occurs, send value right away.
14326 // While a read/write is pending, do not update delta.
14327 // Send non read/wr delta during fw2 ..
14328
14329 // RTL keeps pic_ovf indication in rd_softint and not softint.
14330 // So for set/clear writes, we send softint before the write ..,
14331 // and for read/asyncs we send rd_softint ..
14332
14333
14334 if (~`SOFTINT_RDWR_49) begin // {
14335 if (softint !== `RD_SOFTINT_REG_49 )
14336 softint_delta <= 1'b1;
14337 softint <= `RD_SOFTINT_REG_49;
14338 end // }
14339
14340 if ((`NAS_PIPE_FW2_49 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
14341 ) begin // {
14342 `PR_INFO ("pli_int", `INFO,
14343 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14344 mycid,mytid, {47'h0, softint});
14345 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14346 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14347 {47'h0, softint});
14348 end // }
14349 if (!(~`SOFTINT_RDWR_49&(softint !== `RD_SOFTINT_REG_49)))
14350 softint_delta <= 1'b0;
14351 end //}
14352 else if (`SPC6.tlu.asi_wr_clear_softint[1] |
14353 `SPC6.tlu.asi_wr_set_softint[1] ) begin // {
14354 `PR_INFO ("pli_int", `INFO,
14355 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14356 mycid,mytid, {47'h0, `RD_SOFTINT_REG_49});
14357 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14358 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14359 {47'h0, `RD_SOFTINT_REG_49});
14360 end // }
14361 end //}
14362
14363
14364 softint_rdwr <= `SOFTINT_RDWR_49 ;
14365 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_49;
14366
14367
14368/////////////////////////// Softint ///////////////////////////////////// }}}
14369
14370/////////////////////////// Hintp ///////////////////////////////////// {{{
14371
14372 // Hintp Register hardware Update Detection
14373
14374 // Non software updates (HSP)
14375 // If HINTP is already read/written by SW, then don't send
14376 // any async updates to Nas. Reads/Writes pending sstep is detected
14377 // by snooping nas_pipe ..
14378
14379 hintp <= `HINTP_REG_49 ;
14380 if (hstmatch_late)
14381 hintp_delta <= 1'b1;
14382
14383 if ((~hintp_rdwr & `NAS_PIPE_FW2_49 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
14384 (hintp_rdwr_late & hintp_delta) ) begin // {
14385 `PR_INFO ("pli_int", `INFO,
14386 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
14387 mycid,mytid, {63'h0, hintp});
14388 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14389 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
14390 {63'h0, hintp});
14391 end // }
14392 if (~(hintp_rdwr_late & hintp_delta))
14393 hintp_delta <= 1'b0;
14394 end //}
14395
14396 hintp_rdwr <= `HINTP_RDWR_49;
14397 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_49;
14398 hstmatch_late <= `HSTMATCH_49;
14399
14400
14401/////////////////////////// Hintp ///////////////////////////////////// }}}
14402
14403end //}
14404`endif
14405endmodule
14406
14407// }}}
14408
14409module int_c6t2 ();
14410`ifndef GATESIM
14411
14412// common defines
14413`include "defines.vh"
14414`include "ccx.vri"
14415`include "cmp.vri"
14416
14417wire [2:0] mycid;
14418wire [2:0] mytid;
14419wire [5:0] mytnum;
14420integer junk;
14421
14422reg [63:0] int_vec_recv_reg;
14423reg int_vec_recv_reg_delta;
14424reg int_vec_reg_rdwr;
14425reg inc_vec_reg_rd;
14426reg int_vec_reg_rdwr_late;
14427reg [16:0] softint;
14428reg softint_rdwr;
14429reg softint_rdwr_late;
14430reg softint_delta;
14431reg hintp;
14432reg hintp_rdwr;
14433reg hintp_rdwr_late;
14434reg hintp_delta;
14435reg hstmatch_late;
14436reg ready;
14437reg [7:0] int_num_w;
14438reg [7:0] int_num_fx4;
14439reg [7:0] int_num_fx5;
14440reg [7:0] int_num_fb;
14441reg [7:0] int_num_fw;
14442reg [7:0] int_num_fw1;
14443reg [7:0] int_num_fw2;
14444reg take_disrupting_w;
14445reg take_disrupting_fx4;
14446reg take_disrupting_fx5;
14447reg take_disrupting_fb;
14448reg take_disrupting_fw;
14449reg take_disrupting_fw1;
14450reg take_disrupting_fw2;
14451
14452 assign mycid = 6;
14453 assign mytid = 2;
14454 assign mytnum = 6*8 + 2;
14455
14456initial begin // {
14457 ready = 0; // Wait for socket setup ..
14458 inc_vec_reg_rd <= 1'b0;
14459 int_vec_recv_reg_delta <= 1'b0;
14460 softint_delta <= 1'b0;
14461 hintp_delta <= 1'b0;
14462 int_vec_recv_reg = 64'b0;
14463 @(posedge `BENCH_SPC6_GCLK) ;
14464 @(posedge `BENCH_SPC6_GCLK) ;
14465 ready = `PARGS.int_sync_on;
14466end //}
14467
14468
14469/////////////////////////////// Probes //////////////////////////////////// {{{
14470
14471`define INT_VEC_RECV_REG_50 `SPC6.tlu.cth.int_rec2
14472`define INT_VEC_RECV_ASIWR_50 (`TOP.nas_top.c6.t2.asi_wr_int_rec_delay)
14473`define INT_VEC_RDWR_50 (`TOP.nas_top.c6.t2.asi_rdwr_int_rec)
14474`define INT_VEC_TAKEN_50 `SPC6.tlu.trl0.take_ivt&`SPC6.tlu.trl0.trap[2]
14475
14476`define CPU_MONDO_TAKEN_50 `SPC6.tlu.trl0.take_mqr&`SPC6.tlu.trl0.trap[2]
14477`define DEV_MONDO_TAKEN_50 `SPC6.tlu.trl0.take_dqr&`SPC6.tlu.trl0.trap[2]
14478`define RES_MONDO_TAKEN_50 `SPC6.tlu.trl0.take_rqr&`SPC6.tlu.trl0.trap[2]
14479
14480`define XIR_TAKEN_50 `SPC6.tlu.trl0.take_xir&`SPC6.tlu.trl0.trap[2]
14481
14482`define SOFTINT_RDWR_50 (`TOP.nas_top.c6.t2.asi_rdwr_softint|`TOP.nas_top.c6.t2.asi_wr_softint_delay)
14483
14484`define SOFTINT_REG_50 `SPC6.tlu.trl0.softint2
14485`define RD_SOFTINT_REG_50 `SPC6.tlu.trl0.rd_softint2
14486`define INT_LEVEL_TAKEN_50 `SPC6.tlu.trl0.take_iln&`SPC6.tlu.trl0.trap[2]
14487`define INT_LEVEL_NUM_50 `SPC6.tlu.trl0.int_level_n
14488`define PMU_TAKEN_50 `SPC6.tlu.trl0.take_pmu&`SPC6.tlu.trl0.trap[2]
14489
14490`define HINTP_RDWR_50 (`TOP.nas_top.c6.t2.asi_rdwr_hintp | `TOP.nas_top.c6.t2.asi_wr_hintp_delay)
14491`define HINTP_WR_50 (`SPC6.tlu.asi_wr_hintp[50])
14492`define HSTMATCH_50 `SPC6.tlu.trl0.hstick2_compare
14493
14494`define HINTP_REG_50 `SPC6.tlu.trl0.hintp2
14495`define HSTM_TAKEN_50 `SPC6.tlu.trl0.take_hst&`SPC6.tlu.trl0.trap[2]
14496
14497`define NAS_PIPE_FW2_50 |`TOP.nas_top.c6.t2.complete_fw2
14498
14499`define CWQ_TAKEN_50 `SPC6.tlu.trl0.take_cwq&`SPC6.tlu.trl0.trap[2]
14500`define SMA_TAKEN_50 `SPC6.tlu.trl0.take_sma&`SPC6.tlu.trl0.trap[2]
14501
14502`define POR_TAKEN_50 `SPC6.tlu.trl0.take_por&`SPC6.tlu.trl0.trap[2]
14503
14504/////////////////////////////// Probes //////////////////////////////////// }}}
14505
14506always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
14507
14508 // {{{ DETECT, PIPE & SEND
14509 take_disrupting_w <= (`INT_VEC_TAKEN_50 || `CPU_MONDO_TAKEN_50 ||
14510 `DEV_MONDO_TAKEN_50 || `RES_MONDO_TAKEN_50 ||
14511 `XIR_TAKEN_50 || `INT_LEVEL_TAKEN_50 ||
14512 `HSTM_TAKEN_50 || `CWQ_TAKEN_50 ||
14513 `SMA_TAKEN_50 || `PMU_TAKEN_50 || `POR_TAKEN_50);
14514 take_disrupting_fx4 <= take_disrupting_w;
14515 take_disrupting_fx5 <= take_disrupting_fx4;
14516 take_disrupting_fb <= take_disrupting_fx5;
14517 take_disrupting_fw <= take_disrupting_fb;
14518 take_disrupting_fw1 <= take_disrupting_fw;
14519 take_disrupting_fw2 <= take_disrupting_fw1;
14520
14521 case ({`INT_VEC_TAKEN_50, `CPU_MONDO_TAKEN_50,
14522 `DEV_MONDO_TAKEN_50, `RES_MONDO_TAKEN_50,
14523 `XIR_TAKEN_50, `INT_LEVEL_TAKEN_50,
14524 `HSTM_TAKEN_50, `CWQ_TAKEN_50, `SMA_TAKEN_50 ,
14525 `PMU_TAKEN_50, `POR_TAKEN_50})
14526 11'b10000000000: int_num_w <= 8'h60;
14527 11'b01000000000: int_num_w <= 8'h7c;
14528 11'b00100000000: int_num_w <= 8'h7d;
14529 11'b00010000000: int_num_w <= 8'h7e;
14530 11'b00001000000: int_num_w <= 8'h03;
14531 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_50;
14532 11'b00000010000: int_num_w <= 8'h5e;
14533 11'b00000001000: int_num_w <= 8'h3c;
14534 11'b00000000100: int_num_w <= 8'h3d;
14535 11'b00000000010: int_num_w <= 8'h4f;
14536 11'b00000000001: int_num_w <= 8'h01;
14537 endcase
14538
14539 int_num_fx4 <= int_num_w;
14540 int_num_fx5 <= int_num_fx4;
14541 int_num_fb <= int_num_fx5;
14542 int_num_fw <= int_num_fb;
14543 int_num_fw1 <= int_num_fw;
14544 int_num_fw2 <= int_num_fw1;
14545 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
14546 begin // {
14547 `PR_INFO ("pli_int", `INFO,
14548 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
14549 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
14550 end // }
14551
14552 // }}}
14553
14554/////////////////////////// Vectored Interrupt /////////////////////////// {{{
14555
14556 // Vectored Interrupt Recv Register Detection
14557 // Indicate when register changes due to arriving interrupt, and not
14558 // due to read of incoming register or ASI write ..
14559
14560
14561 // If any read occurs, send value right away.
14562 // While a read/write is pending, do not update delta.
14563 // Send non read/wr delta during fw2 ..
14564
14565
14566 if (!(`INT_VEC_RDWR_50 | `INT_VEC_RECV_ASIWR_50)) begin // {
14567 if (~`INT_VEC_RECV_ASIWR_50 &
14568 (int_vec_recv_reg !== `INT_VEC_RECV_REG_50 ))
14569 int_vec_recv_reg_delta <= 1'b1;
14570 int_vec_recv_reg <= `INT_VEC_RECV_REG_50;
14571 end // }
14572 else if (`INT_VEC_RECV_ASIWR_50)
14573 int_vec_recv_reg <= `TOP.nas_top.c6.t2.asi_updated_int_rec;
14574
14575 if ((`NAS_PIPE_FW2_50 & int_vec_recv_reg_delta ) |
14576 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
14577 `INT_VEC_RECV_ASIWR_50 ) begin // {
14578 `PR_INFO ("pli_int", `INFO,
14579 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
14580 mycid,mytid, int_vec_recv_reg);
14581 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14582 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
14583 64'h0, int_vec_recv_reg);
14584 end // }
14585 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_50 &
14586 (int_vec_recv_reg !== `INT_VEC_RECV_REG_50 ))))
14587 int_vec_recv_reg_delta <= 1'b0;
14588 end //}
14589
14590 int_vec_reg_rdwr <= `INT_VEC_RDWR_50 | `INT_VEC_RECV_ASIWR_50;
14591 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_50 & ~ inc_vec_reg_rd;
14592
14593 if (`INT_VEC_RECV_ASIWR_50)
14594 inc_vec_reg_rd <= 1'b1;
14595 if (`NAS_PIPE_FW2_50)
14596 inc_vec_reg_rd <= 1'b0;
14597
14598
14599/////////////////////////// Vectored Interrupt /////////////////////////// }}}
14600
14601/////////////////////////// Asynchronous Resets ////////////////////////// {{{
14602
14603
14604/////////////////////////// Asynchronous Resets ////////////////////////// }}}
14605
14606/////////////////////////// Softint ///////////////////////////////////// {{{
14607
14608 // Softint Register hardware Update Detection
14609
14610 // Non software updates (TM/SM)
14611
14612 // If any read occurs, send value right away.
14613 // While a read/write is pending, do not update delta.
14614 // Send non read/wr delta during fw2 ..
14615
14616 // RTL keeps pic_ovf indication in rd_softint and not softint.
14617 // So for set/clear writes, we send softint before the write ..,
14618 // and for read/asyncs we send rd_softint ..
14619
14620
14621 if (~`SOFTINT_RDWR_50) begin // {
14622 if (softint !== `RD_SOFTINT_REG_50 )
14623 softint_delta <= 1'b1;
14624 softint <= `RD_SOFTINT_REG_50;
14625 end // }
14626
14627 if ((`NAS_PIPE_FW2_50 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
14628 ) begin // {
14629 `PR_INFO ("pli_int", `INFO,
14630 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14631 mycid,mytid, {47'h0, softint});
14632 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14633 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14634 {47'h0, softint});
14635 end // }
14636 if (!(~`SOFTINT_RDWR_50&(softint !== `RD_SOFTINT_REG_50)))
14637 softint_delta <= 1'b0;
14638 end //}
14639 else if (`SPC6.tlu.asi_wr_clear_softint[2] |
14640 `SPC6.tlu.asi_wr_set_softint[2] ) begin // {
14641 `PR_INFO ("pli_int", `INFO,
14642 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14643 mycid,mytid, {47'h0, `RD_SOFTINT_REG_50});
14644 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14645 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14646 {47'h0, `RD_SOFTINT_REG_50});
14647 end // }
14648 end //}
14649
14650
14651 softint_rdwr <= `SOFTINT_RDWR_50 ;
14652 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_50;
14653
14654
14655/////////////////////////// Softint ///////////////////////////////////// }}}
14656
14657/////////////////////////// Hintp ///////////////////////////////////// {{{
14658
14659 // Hintp Register hardware Update Detection
14660
14661 // Non software updates (HSP)
14662 // If HINTP is already read/written by SW, then don't send
14663 // any async updates to Nas. Reads/Writes pending sstep is detected
14664 // by snooping nas_pipe ..
14665
14666 hintp <= `HINTP_REG_50 ;
14667 if (hstmatch_late)
14668 hintp_delta <= 1'b1;
14669
14670 if ((~hintp_rdwr & `NAS_PIPE_FW2_50 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
14671 (hintp_rdwr_late & hintp_delta) ) begin // {
14672 `PR_INFO ("pli_int", `INFO,
14673 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
14674 mycid,mytid, {63'h0, hintp});
14675 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14676 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
14677 {63'h0, hintp});
14678 end // }
14679 if (~(hintp_rdwr_late & hintp_delta))
14680 hintp_delta <= 1'b0;
14681 end //}
14682
14683 hintp_rdwr <= `HINTP_RDWR_50;
14684 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_50;
14685 hstmatch_late <= `HSTMATCH_50;
14686
14687
14688/////////////////////////// Hintp ///////////////////////////////////// }}}
14689
14690end //}
14691`endif
14692endmodule
14693
14694// }}}
14695
14696module int_c6t3 ();
14697`ifndef GATESIM
14698
14699// common defines
14700`include "defines.vh"
14701`include "ccx.vri"
14702`include "cmp.vri"
14703
14704wire [2:0] mycid;
14705wire [2:0] mytid;
14706wire [5:0] mytnum;
14707integer junk;
14708
14709reg [63:0] int_vec_recv_reg;
14710reg int_vec_recv_reg_delta;
14711reg int_vec_reg_rdwr;
14712reg inc_vec_reg_rd;
14713reg int_vec_reg_rdwr_late;
14714reg [16:0] softint;
14715reg softint_rdwr;
14716reg softint_rdwr_late;
14717reg softint_delta;
14718reg hintp;
14719reg hintp_rdwr;
14720reg hintp_rdwr_late;
14721reg hintp_delta;
14722reg hstmatch_late;
14723reg ready;
14724reg [7:0] int_num_w;
14725reg [7:0] int_num_fx4;
14726reg [7:0] int_num_fx5;
14727reg [7:0] int_num_fb;
14728reg [7:0] int_num_fw;
14729reg [7:0] int_num_fw1;
14730reg [7:0] int_num_fw2;
14731reg take_disrupting_w;
14732reg take_disrupting_fx4;
14733reg take_disrupting_fx5;
14734reg take_disrupting_fb;
14735reg take_disrupting_fw;
14736reg take_disrupting_fw1;
14737reg take_disrupting_fw2;
14738
14739 assign mycid = 6;
14740 assign mytid = 3;
14741 assign mytnum = 6*8 + 3;
14742
14743initial begin // {
14744 ready = 0; // Wait for socket setup ..
14745 inc_vec_reg_rd <= 1'b0;
14746 int_vec_recv_reg_delta <= 1'b0;
14747 softint_delta <= 1'b0;
14748 hintp_delta <= 1'b0;
14749 int_vec_recv_reg = 64'b0;
14750 @(posedge `BENCH_SPC6_GCLK) ;
14751 @(posedge `BENCH_SPC6_GCLK) ;
14752 ready = `PARGS.int_sync_on;
14753end //}
14754
14755
14756/////////////////////////////// Probes //////////////////////////////////// {{{
14757
14758`define INT_VEC_RECV_REG_51 `SPC6.tlu.cth.int_rec3
14759`define INT_VEC_RECV_ASIWR_51 (`TOP.nas_top.c6.t3.asi_wr_int_rec_delay)
14760`define INT_VEC_RDWR_51 (`TOP.nas_top.c6.t3.asi_rdwr_int_rec)
14761`define INT_VEC_TAKEN_51 `SPC6.tlu.trl0.take_ivt&`SPC6.tlu.trl0.trap[3]
14762
14763`define CPU_MONDO_TAKEN_51 `SPC6.tlu.trl0.take_mqr&`SPC6.tlu.trl0.trap[3]
14764`define DEV_MONDO_TAKEN_51 `SPC6.tlu.trl0.take_dqr&`SPC6.tlu.trl0.trap[3]
14765`define RES_MONDO_TAKEN_51 `SPC6.tlu.trl0.take_rqr&`SPC6.tlu.trl0.trap[3]
14766
14767`define XIR_TAKEN_51 `SPC6.tlu.trl0.take_xir&`SPC6.tlu.trl0.trap[3]
14768
14769`define SOFTINT_RDWR_51 (`TOP.nas_top.c6.t3.asi_rdwr_softint|`TOP.nas_top.c6.t3.asi_wr_softint_delay)
14770
14771`define SOFTINT_REG_51 `SPC6.tlu.trl0.softint3
14772`define RD_SOFTINT_REG_51 `SPC6.tlu.trl0.rd_softint3
14773`define INT_LEVEL_TAKEN_51 `SPC6.tlu.trl0.take_iln&`SPC6.tlu.trl0.trap[3]
14774`define INT_LEVEL_NUM_51 `SPC6.tlu.trl0.int_level_n
14775`define PMU_TAKEN_51 `SPC6.tlu.trl0.take_pmu&`SPC6.tlu.trl0.trap[3]
14776
14777`define HINTP_RDWR_51 (`TOP.nas_top.c6.t3.asi_rdwr_hintp | `TOP.nas_top.c6.t3.asi_wr_hintp_delay)
14778`define HINTP_WR_51 (`SPC6.tlu.asi_wr_hintp[51])
14779`define HSTMATCH_51 `SPC6.tlu.trl0.hstick3_compare
14780
14781`define HINTP_REG_51 `SPC6.tlu.trl0.hintp3
14782`define HSTM_TAKEN_51 `SPC6.tlu.trl0.take_hst&`SPC6.tlu.trl0.trap[3]
14783
14784`define NAS_PIPE_FW2_51 |`TOP.nas_top.c6.t3.complete_fw2
14785
14786`define CWQ_TAKEN_51 `SPC6.tlu.trl0.take_cwq&`SPC6.tlu.trl0.trap[3]
14787`define SMA_TAKEN_51 `SPC6.tlu.trl0.take_sma&`SPC6.tlu.trl0.trap[3]
14788
14789`define POR_TAKEN_51 `SPC6.tlu.trl0.take_por&`SPC6.tlu.trl0.trap[3]
14790
14791/////////////////////////////// Probes //////////////////////////////////// }}}
14792
14793always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
14794
14795 // {{{ DETECT, PIPE & SEND
14796 take_disrupting_w <= (`INT_VEC_TAKEN_51 || `CPU_MONDO_TAKEN_51 ||
14797 `DEV_MONDO_TAKEN_51 || `RES_MONDO_TAKEN_51 ||
14798 `XIR_TAKEN_51 || `INT_LEVEL_TAKEN_51 ||
14799 `HSTM_TAKEN_51 || `CWQ_TAKEN_51 ||
14800 `SMA_TAKEN_51 || `PMU_TAKEN_51 || `POR_TAKEN_51);
14801 take_disrupting_fx4 <= take_disrupting_w;
14802 take_disrupting_fx5 <= take_disrupting_fx4;
14803 take_disrupting_fb <= take_disrupting_fx5;
14804 take_disrupting_fw <= take_disrupting_fb;
14805 take_disrupting_fw1 <= take_disrupting_fw;
14806 take_disrupting_fw2 <= take_disrupting_fw1;
14807
14808 case ({`INT_VEC_TAKEN_51, `CPU_MONDO_TAKEN_51,
14809 `DEV_MONDO_TAKEN_51, `RES_MONDO_TAKEN_51,
14810 `XIR_TAKEN_51, `INT_LEVEL_TAKEN_51,
14811 `HSTM_TAKEN_51, `CWQ_TAKEN_51, `SMA_TAKEN_51 ,
14812 `PMU_TAKEN_51, `POR_TAKEN_51})
14813 11'b10000000000: int_num_w <= 8'h60;
14814 11'b01000000000: int_num_w <= 8'h7c;
14815 11'b00100000000: int_num_w <= 8'h7d;
14816 11'b00010000000: int_num_w <= 8'h7e;
14817 11'b00001000000: int_num_w <= 8'h03;
14818 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_51;
14819 11'b00000010000: int_num_w <= 8'h5e;
14820 11'b00000001000: int_num_w <= 8'h3c;
14821 11'b00000000100: int_num_w <= 8'h3d;
14822 11'b00000000010: int_num_w <= 8'h4f;
14823 11'b00000000001: int_num_w <= 8'h01;
14824 endcase
14825
14826 int_num_fx4 <= int_num_w;
14827 int_num_fx5 <= int_num_fx4;
14828 int_num_fb <= int_num_fx5;
14829 int_num_fw <= int_num_fb;
14830 int_num_fw1 <= int_num_fw;
14831 int_num_fw2 <= int_num_fw1;
14832 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
14833 begin // {
14834 `PR_INFO ("pli_int", `INFO,
14835 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
14836 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
14837 end // }
14838
14839 // }}}
14840
14841/////////////////////////// Vectored Interrupt /////////////////////////// {{{
14842
14843 // Vectored Interrupt Recv Register Detection
14844 // Indicate when register changes due to arriving interrupt, and not
14845 // due to read of incoming register or ASI write ..
14846
14847
14848 // If any read occurs, send value right away.
14849 // While a read/write is pending, do not update delta.
14850 // Send non read/wr delta during fw2 ..
14851
14852
14853 if (!(`INT_VEC_RDWR_51 | `INT_VEC_RECV_ASIWR_51)) begin // {
14854 if (~`INT_VEC_RECV_ASIWR_51 &
14855 (int_vec_recv_reg !== `INT_VEC_RECV_REG_51 ))
14856 int_vec_recv_reg_delta <= 1'b1;
14857 int_vec_recv_reg <= `INT_VEC_RECV_REG_51;
14858 end // }
14859 else if (`INT_VEC_RECV_ASIWR_51)
14860 int_vec_recv_reg <= `TOP.nas_top.c6.t3.asi_updated_int_rec;
14861
14862 if ((`NAS_PIPE_FW2_51 & int_vec_recv_reg_delta ) |
14863 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
14864 `INT_VEC_RECV_ASIWR_51 ) begin // {
14865 `PR_INFO ("pli_int", `INFO,
14866 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
14867 mycid,mytid, int_vec_recv_reg);
14868 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14869 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
14870 64'h0, int_vec_recv_reg);
14871 end // }
14872 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_51 &
14873 (int_vec_recv_reg !== `INT_VEC_RECV_REG_51 ))))
14874 int_vec_recv_reg_delta <= 1'b0;
14875 end //}
14876
14877 int_vec_reg_rdwr <= `INT_VEC_RDWR_51 | `INT_VEC_RECV_ASIWR_51;
14878 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_51 & ~ inc_vec_reg_rd;
14879
14880 if (`INT_VEC_RECV_ASIWR_51)
14881 inc_vec_reg_rd <= 1'b1;
14882 if (`NAS_PIPE_FW2_51)
14883 inc_vec_reg_rd <= 1'b0;
14884
14885
14886/////////////////////////// Vectored Interrupt /////////////////////////// }}}
14887
14888/////////////////////////// Asynchronous Resets ////////////////////////// {{{
14889
14890
14891/////////////////////////// Asynchronous Resets ////////////////////////// }}}
14892
14893/////////////////////////// Softint ///////////////////////////////////// {{{
14894
14895 // Softint Register hardware Update Detection
14896
14897 // Non software updates (TM/SM)
14898
14899 // If any read occurs, send value right away.
14900 // While a read/write is pending, do not update delta.
14901 // Send non read/wr delta during fw2 ..
14902
14903 // RTL keeps pic_ovf indication in rd_softint and not softint.
14904 // So for set/clear writes, we send softint before the write ..,
14905 // and for read/asyncs we send rd_softint ..
14906
14907
14908 if (~`SOFTINT_RDWR_51) begin // {
14909 if (softint !== `RD_SOFTINT_REG_51 )
14910 softint_delta <= 1'b1;
14911 softint <= `RD_SOFTINT_REG_51;
14912 end // }
14913
14914 if ((`NAS_PIPE_FW2_51 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
14915 ) begin // {
14916 `PR_INFO ("pli_int", `INFO,
14917 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14918 mycid,mytid, {47'h0, softint});
14919 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14920 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14921 {47'h0, softint});
14922 end // }
14923 if (!(~`SOFTINT_RDWR_51&(softint !== `RD_SOFTINT_REG_51)))
14924 softint_delta <= 1'b0;
14925 end //}
14926 else if (`SPC6.tlu.asi_wr_clear_softint[3] |
14927 `SPC6.tlu.asi_wr_set_softint[3] ) begin // {
14928 `PR_INFO ("pli_int", `INFO,
14929 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
14930 mycid,mytid, {47'h0, `RD_SOFTINT_REG_51});
14931 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14932 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
14933 {47'h0, `RD_SOFTINT_REG_51});
14934 end // }
14935 end //}
14936
14937
14938 softint_rdwr <= `SOFTINT_RDWR_51 ;
14939 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_51;
14940
14941
14942/////////////////////////// Softint ///////////////////////////////////// }}}
14943
14944/////////////////////////// Hintp ///////////////////////////////////// {{{
14945
14946 // Hintp Register hardware Update Detection
14947
14948 // Non software updates (HSP)
14949 // If HINTP is already read/written by SW, then don't send
14950 // any async updates to Nas. Reads/Writes pending sstep is detected
14951 // by snooping nas_pipe ..
14952
14953 hintp <= `HINTP_REG_51 ;
14954 if (hstmatch_late)
14955 hintp_delta <= 1'b1;
14956
14957 if ((~hintp_rdwr & `NAS_PIPE_FW2_51 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
14958 (hintp_rdwr_late & hintp_delta) ) begin // {
14959 `PR_INFO ("pli_int", `INFO,
14960 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
14961 mycid,mytid, {63'h0, hintp});
14962 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
14963 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
14964 {63'h0, hintp});
14965 end // }
14966 if (~(hintp_rdwr_late & hintp_delta))
14967 hintp_delta <= 1'b0;
14968 end //}
14969
14970 hintp_rdwr <= `HINTP_RDWR_51;
14971 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_51;
14972 hstmatch_late <= `HSTMATCH_51;
14973
14974
14975/////////////////////////// Hintp ///////////////////////////////////// }}}
14976
14977end //}
14978`endif
14979endmodule
14980
14981// }}}
14982
14983module int_c6t4 ();
14984`ifndef GATESIM
14985
14986// common defines
14987`include "defines.vh"
14988`include "ccx.vri"
14989`include "cmp.vri"
14990
14991wire [2:0] mycid;
14992wire [2:0] mytid;
14993wire [5:0] mytnum;
14994integer junk;
14995
14996reg [63:0] int_vec_recv_reg;
14997reg int_vec_recv_reg_delta;
14998reg int_vec_reg_rdwr;
14999reg inc_vec_reg_rd;
15000reg int_vec_reg_rdwr_late;
15001reg [16:0] softint;
15002reg softint_rdwr;
15003reg softint_rdwr_late;
15004reg softint_delta;
15005reg hintp;
15006reg hintp_rdwr;
15007reg hintp_rdwr_late;
15008reg hintp_delta;
15009reg hstmatch_late;
15010reg ready;
15011reg [7:0] int_num_w;
15012reg [7:0] int_num_fx4;
15013reg [7:0] int_num_fx5;
15014reg [7:0] int_num_fb;
15015reg [7:0] int_num_fw;
15016reg [7:0] int_num_fw1;
15017reg [7:0] int_num_fw2;
15018reg take_disrupting_w;
15019reg take_disrupting_fx4;
15020reg take_disrupting_fx5;
15021reg take_disrupting_fb;
15022reg take_disrupting_fw;
15023reg take_disrupting_fw1;
15024reg take_disrupting_fw2;
15025
15026 assign mycid = 6;
15027 assign mytid = 4;
15028 assign mytnum = 6*8 + 4;
15029
15030initial begin // {
15031 ready = 0; // Wait for socket setup ..
15032 inc_vec_reg_rd <= 1'b0;
15033 int_vec_recv_reg_delta <= 1'b0;
15034 softint_delta <= 1'b0;
15035 hintp_delta <= 1'b0;
15036 int_vec_recv_reg = 64'b0;
15037 @(posedge `BENCH_SPC6_GCLK) ;
15038 @(posedge `BENCH_SPC6_GCLK) ;
15039 ready = `PARGS.int_sync_on;
15040end //}
15041
15042
15043/////////////////////////////// Probes //////////////////////////////////// {{{
15044
15045`define INT_VEC_RECV_REG_52 `SPC6.tlu.cth.int_rec4
15046`define INT_VEC_RECV_ASIWR_52 (`TOP.nas_top.c6.t4.asi_wr_int_rec_delay)
15047`define INT_VEC_RDWR_52 (`TOP.nas_top.c6.t4.asi_rdwr_int_rec)
15048`define INT_VEC_TAKEN_52 `SPC6.tlu.trl1.take_ivt&`SPC6.tlu.trl1.trap[0]
15049
15050`define CPU_MONDO_TAKEN_52 `SPC6.tlu.trl1.take_mqr&`SPC6.tlu.trl1.trap[0]
15051`define DEV_MONDO_TAKEN_52 `SPC6.tlu.trl1.take_dqr&`SPC6.tlu.trl1.trap[0]
15052`define RES_MONDO_TAKEN_52 `SPC6.tlu.trl1.take_rqr&`SPC6.tlu.trl1.trap[0]
15053
15054`define XIR_TAKEN_52 `SPC6.tlu.trl1.take_xir&`SPC6.tlu.trl1.trap[0]
15055
15056`define SOFTINT_RDWR_52 (`TOP.nas_top.c6.t4.asi_rdwr_softint|`TOP.nas_top.c6.t4.asi_wr_softint_delay)
15057
15058`define SOFTINT_REG_52 `SPC6.tlu.trl1.softint0
15059`define RD_SOFTINT_REG_52 `SPC6.tlu.trl1.rd_softint0
15060`define INT_LEVEL_TAKEN_52 `SPC6.tlu.trl1.take_iln&`SPC6.tlu.trl1.trap[0]
15061`define INT_LEVEL_NUM_52 `SPC6.tlu.trl1.int_level_n
15062`define PMU_TAKEN_52 `SPC6.tlu.trl1.take_pmu&`SPC6.tlu.trl1.trap[0]
15063
15064`define HINTP_RDWR_52 (`TOP.nas_top.c6.t4.asi_rdwr_hintp | `TOP.nas_top.c6.t4.asi_wr_hintp_delay)
15065`define HINTP_WR_52 (`SPC6.tlu.asi_wr_hintp[52])
15066`define HSTMATCH_52 `SPC6.tlu.trl1.hstick0_compare
15067
15068`define HINTP_REG_52 `SPC6.tlu.trl1.hintp0
15069`define HSTM_TAKEN_52 `SPC6.tlu.trl1.take_hst&`SPC6.tlu.trl1.trap[0]
15070
15071`define NAS_PIPE_FW2_52 |`TOP.nas_top.c6.t4.complete_fw2
15072
15073`define CWQ_TAKEN_52 `SPC6.tlu.trl1.take_cwq&`SPC6.tlu.trl1.trap[0]
15074`define SMA_TAKEN_52 `SPC6.tlu.trl1.take_sma&`SPC6.tlu.trl1.trap[0]
15075
15076`define POR_TAKEN_52 `SPC6.tlu.trl1.take_por&`SPC6.tlu.trl1.trap[0]
15077
15078/////////////////////////////// Probes //////////////////////////////////// }}}
15079
15080always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
15081
15082 // {{{ DETECT, PIPE & SEND
15083 take_disrupting_w <= (`INT_VEC_TAKEN_52 || `CPU_MONDO_TAKEN_52 ||
15084 `DEV_MONDO_TAKEN_52 || `RES_MONDO_TAKEN_52 ||
15085 `XIR_TAKEN_52 || `INT_LEVEL_TAKEN_52 ||
15086 `HSTM_TAKEN_52 || `CWQ_TAKEN_52 ||
15087 `SMA_TAKEN_52 || `PMU_TAKEN_52 || `POR_TAKEN_52);
15088 take_disrupting_fx4 <= take_disrupting_w;
15089 take_disrupting_fx5 <= take_disrupting_fx4;
15090 take_disrupting_fb <= take_disrupting_fx5;
15091 take_disrupting_fw <= take_disrupting_fb;
15092 take_disrupting_fw1 <= take_disrupting_fw;
15093 take_disrupting_fw2 <= take_disrupting_fw1;
15094
15095 case ({`INT_VEC_TAKEN_52, `CPU_MONDO_TAKEN_52,
15096 `DEV_MONDO_TAKEN_52, `RES_MONDO_TAKEN_52,
15097 `XIR_TAKEN_52, `INT_LEVEL_TAKEN_52,
15098 `HSTM_TAKEN_52, `CWQ_TAKEN_52, `SMA_TAKEN_52 ,
15099 `PMU_TAKEN_52, `POR_TAKEN_52})
15100 11'b10000000000: int_num_w <= 8'h60;
15101 11'b01000000000: int_num_w <= 8'h7c;
15102 11'b00100000000: int_num_w <= 8'h7d;
15103 11'b00010000000: int_num_w <= 8'h7e;
15104 11'b00001000000: int_num_w <= 8'h03;
15105 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_52;
15106 11'b00000010000: int_num_w <= 8'h5e;
15107 11'b00000001000: int_num_w <= 8'h3c;
15108 11'b00000000100: int_num_w <= 8'h3d;
15109 11'b00000000010: int_num_w <= 8'h4f;
15110 11'b00000000001: int_num_w <= 8'h01;
15111 endcase
15112
15113 int_num_fx4 <= int_num_w;
15114 int_num_fx5 <= int_num_fx4;
15115 int_num_fb <= int_num_fx5;
15116 int_num_fw <= int_num_fb;
15117 int_num_fw1 <= int_num_fw;
15118 int_num_fw2 <= int_num_fw1;
15119 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
15120 begin // {
15121 `PR_INFO ("pli_int", `INFO,
15122 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
15123 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15124 end // }
15125
15126 // }}}
15127
15128/////////////////////////// Vectored Interrupt /////////////////////////// {{{
15129
15130 // Vectored Interrupt Recv Register Detection
15131 // Indicate when register changes due to arriving interrupt, and not
15132 // due to read of incoming register or ASI write ..
15133
15134
15135 // If any read occurs, send value right away.
15136 // While a read/write is pending, do not update delta.
15137 // Send non read/wr delta during fw2 ..
15138
15139
15140 if (!(`INT_VEC_RDWR_52 | `INT_VEC_RECV_ASIWR_52)) begin // {
15141 if (~`INT_VEC_RECV_ASIWR_52 &
15142 (int_vec_recv_reg !== `INT_VEC_RECV_REG_52 ))
15143 int_vec_recv_reg_delta <= 1'b1;
15144 int_vec_recv_reg <= `INT_VEC_RECV_REG_52;
15145 end // }
15146 else if (`INT_VEC_RECV_ASIWR_52)
15147 int_vec_recv_reg <= `TOP.nas_top.c6.t4.asi_updated_int_rec;
15148
15149 if ((`NAS_PIPE_FW2_52 & int_vec_recv_reg_delta ) |
15150 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
15151 `INT_VEC_RECV_ASIWR_52 ) begin // {
15152 `PR_INFO ("pli_int", `INFO,
15153 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
15154 mycid,mytid, int_vec_recv_reg);
15155 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15156 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
15157 64'h0, int_vec_recv_reg);
15158 end // }
15159 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_52 &
15160 (int_vec_recv_reg !== `INT_VEC_RECV_REG_52 ))))
15161 int_vec_recv_reg_delta <= 1'b0;
15162 end //}
15163
15164 int_vec_reg_rdwr <= `INT_VEC_RDWR_52 | `INT_VEC_RECV_ASIWR_52;
15165 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_52 & ~ inc_vec_reg_rd;
15166
15167 if (`INT_VEC_RECV_ASIWR_52)
15168 inc_vec_reg_rd <= 1'b1;
15169 if (`NAS_PIPE_FW2_52)
15170 inc_vec_reg_rd <= 1'b0;
15171
15172
15173/////////////////////////// Vectored Interrupt /////////////////////////// }}}
15174
15175/////////////////////////// Asynchronous Resets ////////////////////////// {{{
15176
15177
15178/////////////////////////// Asynchronous Resets ////////////////////////// }}}
15179
15180/////////////////////////// Softint ///////////////////////////////////// {{{
15181
15182 // Softint Register hardware Update Detection
15183
15184 // Non software updates (TM/SM)
15185
15186 // If any read occurs, send value right away.
15187 // While a read/write is pending, do not update delta.
15188 // Send non read/wr delta during fw2 ..
15189
15190 // RTL keeps pic_ovf indication in rd_softint and not softint.
15191 // So for set/clear writes, we send softint before the write ..,
15192 // and for read/asyncs we send rd_softint ..
15193
15194
15195 if (~`SOFTINT_RDWR_52) begin // {
15196 if (softint !== `RD_SOFTINT_REG_52 )
15197 softint_delta <= 1'b1;
15198 softint <= `RD_SOFTINT_REG_52;
15199 end // }
15200
15201 if ((`NAS_PIPE_FW2_52 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
15202 ) begin // {
15203 `PR_INFO ("pli_int", `INFO,
15204 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
15205 mycid,mytid, {47'h0, softint});
15206 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15207 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
15208 {47'h0, softint});
15209 end // }
15210 if (!(~`SOFTINT_RDWR_52&(softint !== `RD_SOFTINT_REG_52)))
15211 softint_delta <= 1'b0;
15212 end //}
15213 else if (`SPC6.tlu.asi_wr_clear_softint[4] |
15214 `SPC6.tlu.asi_wr_set_softint[4] ) begin // {
15215 `PR_INFO ("pli_int", `INFO,
15216 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
15217 mycid,mytid, {47'h0, `RD_SOFTINT_REG_52});
15218 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15219 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
15220 {47'h0, `RD_SOFTINT_REG_52});
15221 end // }
15222 end //}
15223
15224
15225 softint_rdwr <= `SOFTINT_RDWR_52 ;
15226 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_52;
15227
15228
15229/////////////////////////// Softint ///////////////////////////////////// }}}
15230
15231/////////////////////////// Hintp ///////////////////////////////////// {{{
15232
15233 // Hintp Register hardware Update Detection
15234
15235 // Non software updates (HSP)
15236 // If HINTP is already read/written by SW, then don't send
15237 // any async updates to Nas. Reads/Writes pending sstep is detected
15238 // by snooping nas_pipe ..
15239
15240 hintp <= `HINTP_REG_52 ;
15241 if (hstmatch_late)
15242 hintp_delta <= 1'b1;
15243
15244 if ((~hintp_rdwr & `NAS_PIPE_FW2_52 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
15245 (hintp_rdwr_late & hintp_delta) ) begin // {
15246 `PR_INFO ("pli_int", `INFO,
15247 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
15248 mycid,mytid, {63'h0, hintp});
15249 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15250 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
15251 {63'h0, hintp});
15252 end // }
15253 if (~(hintp_rdwr_late & hintp_delta))
15254 hintp_delta <= 1'b0;
15255 end //}
15256
15257 hintp_rdwr <= `HINTP_RDWR_52;
15258 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_52;
15259 hstmatch_late <= `HSTMATCH_52;
15260
15261
15262/////////////////////////// Hintp ///////////////////////////////////// }}}
15263
15264end //}
15265`endif
15266endmodule
15267
15268// }}}
15269
15270module int_c6t5 ();
15271`ifndef GATESIM
15272
15273// common defines
15274`include "defines.vh"
15275`include "ccx.vri"
15276`include "cmp.vri"
15277
15278wire [2:0] mycid;
15279wire [2:0] mytid;
15280wire [5:0] mytnum;
15281integer junk;
15282
15283reg [63:0] int_vec_recv_reg;
15284reg int_vec_recv_reg_delta;
15285reg int_vec_reg_rdwr;
15286reg inc_vec_reg_rd;
15287reg int_vec_reg_rdwr_late;
15288reg [16:0] softint;
15289reg softint_rdwr;
15290reg softint_rdwr_late;
15291reg softint_delta;
15292reg hintp;
15293reg hintp_rdwr;
15294reg hintp_rdwr_late;
15295reg hintp_delta;
15296reg hstmatch_late;
15297reg ready;
15298reg [7:0] int_num_w;
15299reg [7:0] int_num_fx4;
15300reg [7:0] int_num_fx5;
15301reg [7:0] int_num_fb;
15302reg [7:0] int_num_fw;
15303reg [7:0] int_num_fw1;
15304reg [7:0] int_num_fw2;
15305reg take_disrupting_w;
15306reg take_disrupting_fx4;
15307reg take_disrupting_fx5;
15308reg take_disrupting_fb;
15309reg take_disrupting_fw;
15310reg take_disrupting_fw1;
15311reg take_disrupting_fw2;
15312
15313 assign mycid = 6;
15314 assign mytid = 5;
15315 assign mytnum = 6*8 + 5;
15316
15317initial begin // {
15318 ready = 0; // Wait for socket setup ..
15319 inc_vec_reg_rd <= 1'b0;
15320 int_vec_recv_reg_delta <= 1'b0;
15321 softint_delta <= 1'b0;
15322 hintp_delta <= 1'b0;
15323 int_vec_recv_reg = 64'b0;
15324 @(posedge `BENCH_SPC6_GCLK) ;
15325 @(posedge `BENCH_SPC6_GCLK) ;
15326 ready = `PARGS.int_sync_on;
15327end //}
15328
15329
15330/////////////////////////////// Probes //////////////////////////////////// {{{
15331
15332`define INT_VEC_RECV_REG_53 `SPC6.tlu.cth.int_rec5
15333`define INT_VEC_RECV_ASIWR_53 (`TOP.nas_top.c6.t5.asi_wr_int_rec_delay)
15334`define INT_VEC_RDWR_53 (`TOP.nas_top.c6.t5.asi_rdwr_int_rec)
15335`define INT_VEC_TAKEN_53 `SPC6.tlu.trl1.take_ivt&`SPC6.tlu.trl1.trap[1]
15336
15337`define CPU_MONDO_TAKEN_53 `SPC6.tlu.trl1.take_mqr&`SPC6.tlu.trl1.trap[1]
15338`define DEV_MONDO_TAKEN_53 `SPC6.tlu.trl1.take_dqr&`SPC6.tlu.trl1.trap[1]
15339`define RES_MONDO_TAKEN_53 `SPC6.tlu.trl1.take_rqr&`SPC6.tlu.trl1.trap[1]
15340
15341`define XIR_TAKEN_53 `SPC6.tlu.trl1.take_xir&`SPC6.tlu.trl1.trap[1]
15342
15343`define SOFTINT_RDWR_53 (`TOP.nas_top.c6.t5.asi_rdwr_softint|`TOP.nas_top.c6.t5.asi_wr_softint_delay)
15344
15345`define SOFTINT_REG_53 `SPC6.tlu.trl1.softint1
15346`define RD_SOFTINT_REG_53 `SPC6.tlu.trl1.rd_softint1
15347`define INT_LEVEL_TAKEN_53 `SPC6.tlu.trl1.take_iln&`SPC6.tlu.trl1.trap[1]
15348`define INT_LEVEL_NUM_53 `SPC6.tlu.trl1.int_level_n
15349`define PMU_TAKEN_53 `SPC6.tlu.trl1.take_pmu&`SPC6.tlu.trl1.trap[1]
15350
15351`define HINTP_RDWR_53 (`TOP.nas_top.c6.t5.asi_rdwr_hintp | `TOP.nas_top.c6.t5.asi_wr_hintp_delay)
15352`define HINTP_WR_53 (`SPC6.tlu.asi_wr_hintp[53])
15353`define HSTMATCH_53 `SPC6.tlu.trl1.hstick1_compare
15354
15355`define HINTP_REG_53 `SPC6.tlu.trl1.hintp1
15356`define HSTM_TAKEN_53 `SPC6.tlu.trl1.take_hst&`SPC6.tlu.trl1.trap[1]
15357
15358`define NAS_PIPE_FW2_53 |`TOP.nas_top.c6.t5.complete_fw2
15359
15360`define CWQ_TAKEN_53 `SPC6.tlu.trl1.take_cwq&`SPC6.tlu.trl1.trap[1]
15361`define SMA_TAKEN_53 `SPC6.tlu.trl1.take_sma&`SPC6.tlu.trl1.trap[1]
15362
15363`define POR_TAKEN_53 `SPC6.tlu.trl1.take_por&`SPC6.tlu.trl1.trap[1]
15364
15365/////////////////////////////// Probes //////////////////////////////////// }}}
15366
15367always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
15368
15369 // {{{ DETECT, PIPE & SEND
15370 take_disrupting_w <= (`INT_VEC_TAKEN_53 || `CPU_MONDO_TAKEN_53 ||
15371 `DEV_MONDO_TAKEN_53 || `RES_MONDO_TAKEN_53 ||
15372 `XIR_TAKEN_53 || `INT_LEVEL_TAKEN_53 ||
15373 `HSTM_TAKEN_53 || `CWQ_TAKEN_53 ||
15374 `SMA_TAKEN_53 || `PMU_TAKEN_53 || `POR_TAKEN_53);
15375 take_disrupting_fx4 <= take_disrupting_w;
15376 take_disrupting_fx5 <= take_disrupting_fx4;
15377 take_disrupting_fb <= take_disrupting_fx5;
15378 take_disrupting_fw <= take_disrupting_fb;
15379 take_disrupting_fw1 <= take_disrupting_fw;
15380 take_disrupting_fw2 <= take_disrupting_fw1;
15381
15382 case ({`INT_VEC_TAKEN_53, `CPU_MONDO_TAKEN_53,
15383 `DEV_MONDO_TAKEN_53, `RES_MONDO_TAKEN_53,
15384 `XIR_TAKEN_53, `INT_LEVEL_TAKEN_53,
15385 `HSTM_TAKEN_53, `CWQ_TAKEN_53, `SMA_TAKEN_53 ,
15386 `PMU_TAKEN_53, `POR_TAKEN_53})
15387 11'b10000000000: int_num_w <= 8'h60;
15388 11'b01000000000: int_num_w <= 8'h7c;
15389 11'b00100000000: int_num_w <= 8'h7d;
15390 11'b00010000000: int_num_w <= 8'h7e;
15391 11'b00001000000: int_num_w <= 8'h03;
15392 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_53;
15393 11'b00000010000: int_num_w <= 8'h5e;
15394 11'b00000001000: int_num_w <= 8'h3c;
15395 11'b00000000100: int_num_w <= 8'h3d;
15396 11'b00000000010: int_num_w <= 8'h4f;
15397 11'b00000000001: int_num_w <= 8'h01;
15398 endcase
15399
15400 int_num_fx4 <= int_num_w;
15401 int_num_fx5 <= int_num_fx4;
15402 int_num_fb <= int_num_fx5;
15403 int_num_fw <= int_num_fb;
15404 int_num_fw1 <= int_num_fw;
15405 int_num_fw2 <= int_num_fw1;
15406 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
15407 begin // {
15408 `PR_INFO ("pli_int", `INFO,
15409 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
15410 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15411 end // }
15412
15413 // }}}
15414
15415/////////////////////////// Vectored Interrupt /////////////////////////// {{{
15416
15417 // Vectored Interrupt Recv Register Detection
15418 // Indicate when register changes due to arriving interrupt, and not
15419 // due to read of incoming register or ASI write ..
15420
15421
15422 // If any read occurs, send value right away.
15423 // While a read/write is pending, do not update delta.
15424 // Send non read/wr delta during fw2 ..
15425
15426
15427 if (!(`INT_VEC_RDWR_53 | `INT_VEC_RECV_ASIWR_53)) begin // {
15428 if (~`INT_VEC_RECV_ASIWR_53 &
15429 (int_vec_recv_reg !== `INT_VEC_RECV_REG_53 ))
15430 int_vec_recv_reg_delta <= 1'b1;
15431 int_vec_recv_reg <= `INT_VEC_RECV_REG_53;
15432 end // }
15433 else if (`INT_VEC_RECV_ASIWR_53)
15434 int_vec_recv_reg <= `TOP.nas_top.c6.t5.asi_updated_int_rec;
15435
15436 if ((`NAS_PIPE_FW2_53 & int_vec_recv_reg_delta ) |
15437 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
15438 `INT_VEC_RECV_ASIWR_53 ) begin // {
15439 `PR_INFO ("pli_int", `INFO,
15440 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
15441 mycid,mytid, int_vec_recv_reg);
15442 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15443 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
15444 64'h0, int_vec_recv_reg);
15445 end // }
15446 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_53 &
15447 (int_vec_recv_reg !== `INT_VEC_RECV_REG_53 ))))
15448 int_vec_recv_reg_delta <= 1'b0;
15449 end //}
15450
15451 int_vec_reg_rdwr <= `INT_VEC_RDWR_53 | `INT_VEC_RECV_ASIWR_53;
15452 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_53 & ~ inc_vec_reg_rd;
15453
15454 if (`INT_VEC_RECV_ASIWR_53)
15455 inc_vec_reg_rd <= 1'b1;
15456 if (`NAS_PIPE_FW2_53)
15457 inc_vec_reg_rd <= 1'b0;
15458
15459
15460/////////////////////////// Vectored Interrupt /////////////////////////// }}}
15461
15462/////////////////////////// Asynchronous Resets ////////////////////////// {{{
15463
15464
15465/////////////////////////// Asynchronous Resets ////////////////////////// }}}
15466
15467/////////////////////////// Softint ///////////////////////////////////// {{{
15468
15469 // Softint Register hardware Update Detection
15470
15471 // Non software updates (TM/SM)
15472
15473 // If any read occurs, send value right away.
15474 // While a read/write is pending, do not update delta.
15475 // Send non read/wr delta during fw2 ..
15476
15477 // RTL keeps pic_ovf indication in rd_softint and not softint.
15478 // So for set/clear writes, we send softint before the write ..,
15479 // and for read/asyncs we send rd_softint ..
15480
15481
15482 if (~`SOFTINT_RDWR_53) begin // {
15483 if (softint !== `RD_SOFTINT_REG_53 )
15484 softint_delta <= 1'b1;
15485 softint <= `RD_SOFTINT_REG_53;
15486 end // }
15487
15488 if ((`NAS_PIPE_FW2_53 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
15489 ) begin // {
15490 `PR_INFO ("pli_int", `INFO,
15491 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
15492 mycid,mytid, {47'h0, softint});
15493 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15494 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
15495 {47'h0, softint});
15496 end // }
15497 if (!(~`SOFTINT_RDWR_53&(softint !== `RD_SOFTINT_REG_53)))
15498 softint_delta <= 1'b0;
15499 end //}
15500 else if (`SPC6.tlu.asi_wr_clear_softint[5] |
15501 `SPC6.tlu.asi_wr_set_softint[5] ) begin // {
15502 `PR_INFO ("pli_int", `INFO,
15503 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
15504 mycid,mytid, {47'h0, `RD_SOFTINT_REG_53});
15505 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15506 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
15507 {47'h0, `RD_SOFTINT_REG_53});
15508 end // }
15509 end //}
15510
15511
15512 softint_rdwr <= `SOFTINT_RDWR_53 ;
15513 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_53;
15514
15515
15516/////////////////////////// Softint ///////////////////////////////////// }}}
15517
15518/////////////////////////// Hintp ///////////////////////////////////// {{{
15519
15520 // Hintp Register hardware Update Detection
15521
15522 // Non software updates (HSP)
15523 // If HINTP is already read/written by SW, then don't send
15524 // any async updates to Nas. Reads/Writes pending sstep is detected
15525 // by snooping nas_pipe ..
15526
15527 hintp <= `HINTP_REG_53 ;
15528 if (hstmatch_late)
15529 hintp_delta <= 1'b1;
15530
15531 if ((~hintp_rdwr & `NAS_PIPE_FW2_53 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
15532 (hintp_rdwr_late & hintp_delta) ) begin // {
15533 `PR_INFO ("pli_int", `INFO,
15534 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
15535 mycid,mytid, {63'h0, hintp});
15536 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15537 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
15538 {63'h0, hintp});
15539 end // }
15540 if (~(hintp_rdwr_late & hintp_delta))
15541 hintp_delta <= 1'b0;
15542 end //}
15543
15544 hintp_rdwr <= `HINTP_RDWR_53;
15545 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_53;
15546 hstmatch_late <= `HSTMATCH_53;
15547
15548
15549/////////////////////////// Hintp ///////////////////////////////////// }}}
15550
15551end //}
15552`endif
15553endmodule
15554
15555// }}}
15556
15557module int_c6t6 ();
15558`ifndef GATESIM
15559
15560// common defines
15561`include "defines.vh"
15562`include "ccx.vri"
15563`include "cmp.vri"
15564
15565wire [2:0] mycid;
15566wire [2:0] mytid;
15567wire [5:0] mytnum;
15568integer junk;
15569
15570reg [63:0] int_vec_recv_reg;
15571reg int_vec_recv_reg_delta;
15572reg int_vec_reg_rdwr;
15573reg inc_vec_reg_rd;
15574reg int_vec_reg_rdwr_late;
15575reg [16:0] softint;
15576reg softint_rdwr;
15577reg softint_rdwr_late;
15578reg softint_delta;
15579reg hintp;
15580reg hintp_rdwr;
15581reg hintp_rdwr_late;
15582reg hintp_delta;
15583reg hstmatch_late;
15584reg ready;
15585reg [7:0] int_num_w;
15586reg [7:0] int_num_fx4;
15587reg [7:0] int_num_fx5;
15588reg [7:0] int_num_fb;
15589reg [7:0] int_num_fw;
15590reg [7:0] int_num_fw1;
15591reg [7:0] int_num_fw2;
15592reg take_disrupting_w;
15593reg take_disrupting_fx4;
15594reg take_disrupting_fx5;
15595reg take_disrupting_fb;
15596reg take_disrupting_fw;
15597reg take_disrupting_fw1;
15598reg take_disrupting_fw2;
15599
15600 assign mycid = 6;
15601 assign mytid = 6;
15602 assign mytnum = 6*8 + 6;
15603
15604initial begin // {
15605 ready = 0; // Wait for socket setup ..
15606 inc_vec_reg_rd <= 1'b0;
15607 int_vec_recv_reg_delta <= 1'b0;
15608 softint_delta <= 1'b0;
15609 hintp_delta <= 1'b0;
15610 int_vec_recv_reg = 64'b0;
15611 @(posedge `BENCH_SPC6_GCLK) ;
15612 @(posedge `BENCH_SPC6_GCLK) ;
15613 ready = `PARGS.int_sync_on;
15614end //}
15615
15616
15617/////////////////////////////// Probes //////////////////////////////////// {{{
15618
15619`define INT_VEC_RECV_REG_54 `SPC6.tlu.cth.int_rec6
15620`define INT_VEC_RECV_ASIWR_54 (`TOP.nas_top.c6.t6.asi_wr_int_rec_delay)
15621`define INT_VEC_RDWR_54 (`TOP.nas_top.c6.t6.asi_rdwr_int_rec)
15622`define INT_VEC_TAKEN_54 `SPC6.tlu.trl1.take_ivt&`SPC6.tlu.trl1.trap[2]
15623
15624`define CPU_MONDO_TAKEN_54 `SPC6.tlu.trl1.take_mqr&`SPC6.tlu.trl1.trap[2]
15625`define DEV_MONDO_TAKEN_54 `SPC6.tlu.trl1.take_dqr&`SPC6.tlu.trl1.trap[2]
15626`define RES_MONDO_TAKEN_54 `SPC6.tlu.trl1.take_rqr&`SPC6.tlu.trl1.trap[2]
15627
15628`define XIR_TAKEN_54 `SPC6.tlu.trl1.take_xir&`SPC6.tlu.trl1.trap[2]
15629
15630`define SOFTINT_RDWR_54 (`TOP.nas_top.c6.t6.asi_rdwr_softint|`TOP.nas_top.c6.t6.asi_wr_softint_delay)
15631
15632`define SOFTINT_REG_54 `SPC6.tlu.trl1.softint2
15633`define RD_SOFTINT_REG_54 `SPC6.tlu.trl1.rd_softint2
15634`define INT_LEVEL_TAKEN_54 `SPC6.tlu.trl1.take_iln&`SPC6.tlu.trl1.trap[2]
15635`define INT_LEVEL_NUM_54 `SPC6.tlu.trl1.int_level_n
15636`define PMU_TAKEN_54 `SPC6.tlu.trl1.take_pmu&`SPC6.tlu.trl1.trap[2]
15637
15638`define HINTP_RDWR_54 (`TOP.nas_top.c6.t6.asi_rdwr_hintp | `TOP.nas_top.c6.t6.asi_wr_hintp_delay)
15639`define HINTP_WR_54 (`SPC6.tlu.asi_wr_hintp[54])
15640`define HSTMATCH_54 `SPC6.tlu.trl1.hstick2_compare
15641
15642`define HINTP_REG_54 `SPC6.tlu.trl1.hintp2
15643`define HSTM_TAKEN_54 `SPC6.tlu.trl1.take_hst&`SPC6.tlu.trl1.trap[2]
15644
15645`define NAS_PIPE_FW2_54 |`TOP.nas_top.c6.t6.complete_fw2
15646
15647`define CWQ_TAKEN_54 `SPC6.tlu.trl1.take_cwq&`SPC6.tlu.trl1.trap[2]
15648`define SMA_TAKEN_54 `SPC6.tlu.trl1.take_sma&`SPC6.tlu.trl1.trap[2]
15649
15650`define POR_TAKEN_54 `SPC6.tlu.trl1.take_por&`SPC6.tlu.trl1.trap[2]
15651
15652/////////////////////////////// Probes //////////////////////////////////// }}}
15653
15654always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
15655
15656 // {{{ DETECT, PIPE & SEND
15657 take_disrupting_w <= (`INT_VEC_TAKEN_54 || `CPU_MONDO_TAKEN_54 ||
15658 `DEV_MONDO_TAKEN_54 || `RES_MONDO_TAKEN_54 ||
15659 `XIR_TAKEN_54 || `INT_LEVEL_TAKEN_54 ||
15660 `HSTM_TAKEN_54 || `CWQ_TAKEN_54 ||
15661 `SMA_TAKEN_54 || `PMU_TAKEN_54 || `POR_TAKEN_54);
15662 take_disrupting_fx4 <= take_disrupting_w;
15663 take_disrupting_fx5 <= take_disrupting_fx4;
15664 take_disrupting_fb <= take_disrupting_fx5;
15665 take_disrupting_fw <= take_disrupting_fb;
15666 take_disrupting_fw1 <= take_disrupting_fw;
15667 take_disrupting_fw2 <= take_disrupting_fw1;
15668
15669 case ({`INT_VEC_TAKEN_54, `CPU_MONDO_TAKEN_54,
15670 `DEV_MONDO_TAKEN_54, `RES_MONDO_TAKEN_54,
15671 `XIR_TAKEN_54, `INT_LEVEL_TAKEN_54,
15672 `HSTM_TAKEN_54, `CWQ_TAKEN_54, `SMA_TAKEN_54 ,
15673 `PMU_TAKEN_54, `POR_TAKEN_54})
15674 11'b10000000000: int_num_w <= 8'h60;
15675 11'b01000000000: int_num_w <= 8'h7c;
15676 11'b00100000000: int_num_w <= 8'h7d;
15677 11'b00010000000: int_num_w <= 8'h7e;
15678 11'b00001000000: int_num_w <= 8'h03;
15679 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_54;
15680 11'b00000010000: int_num_w <= 8'h5e;
15681 11'b00000001000: int_num_w <= 8'h3c;
15682 11'b00000000100: int_num_w <= 8'h3d;
15683 11'b00000000010: int_num_w <= 8'h4f;
15684 11'b00000000001: int_num_w <= 8'h01;
15685 endcase
15686
15687 int_num_fx4 <= int_num_w;
15688 int_num_fx5 <= int_num_fx4;
15689 int_num_fb <= int_num_fx5;
15690 int_num_fw <= int_num_fb;
15691 int_num_fw1 <= int_num_fw;
15692 int_num_fw2 <= int_num_fw1;
15693 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
15694 begin // {
15695 `PR_INFO ("pli_int", `INFO,
15696 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
15697 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15698 end // }
15699
15700 // }}}
15701
15702/////////////////////////// Vectored Interrupt /////////////////////////// {{{
15703
15704 // Vectored Interrupt Recv Register Detection
15705 // Indicate when register changes due to arriving interrupt, and not
15706 // due to read of incoming register or ASI write ..
15707
15708
15709 // If any read occurs, send value right away.
15710 // While a read/write is pending, do not update delta.
15711 // Send non read/wr delta during fw2 ..
15712
15713
15714 if (!(`INT_VEC_RDWR_54 | `INT_VEC_RECV_ASIWR_54)) begin // {
15715 if (~`INT_VEC_RECV_ASIWR_54 &
15716 (int_vec_recv_reg !== `INT_VEC_RECV_REG_54 ))
15717 int_vec_recv_reg_delta <= 1'b1;
15718 int_vec_recv_reg <= `INT_VEC_RECV_REG_54;
15719 end // }
15720 else if (`INT_VEC_RECV_ASIWR_54)
15721 int_vec_recv_reg <= `TOP.nas_top.c6.t6.asi_updated_int_rec;
15722
15723 if ((`NAS_PIPE_FW2_54 & int_vec_recv_reg_delta ) |
15724 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
15725 `INT_VEC_RECV_ASIWR_54 ) begin // {
15726 `PR_INFO ("pli_int", `INFO,
15727 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
15728 mycid,mytid, int_vec_recv_reg);
15729 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15730 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
15731 64'h0, int_vec_recv_reg);
15732 end // }
15733 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_54 &
15734 (int_vec_recv_reg !== `INT_VEC_RECV_REG_54 ))))
15735 int_vec_recv_reg_delta <= 1'b0;
15736 end //}
15737
15738 int_vec_reg_rdwr <= `INT_VEC_RDWR_54 | `INT_VEC_RECV_ASIWR_54;
15739 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_54 & ~ inc_vec_reg_rd;
15740
15741 if (`INT_VEC_RECV_ASIWR_54)
15742 inc_vec_reg_rd <= 1'b1;
15743 if (`NAS_PIPE_FW2_54)
15744 inc_vec_reg_rd <= 1'b0;
15745
15746
15747/////////////////////////// Vectored Interrupt /////////////////////////// }}}
15748
15749/////////////////////////// Asynchronous Resets ////////////////////////// {{{
15750
15751
15752/////////////////////////// Asynchronous Resets ////////////////////////// }}}
15753
15754/////////////////////////// Softint ///////////////////////////////////// {{{
15755
15756 // Softint Register hardware Update Detection
15757
15758 // Non software updates (TM/SM)
15759
15760 // If any read occurs, send value right away.
15761 // While a read/write is pending, do not update delta.
15762 // Send non read/wr delta during fw2 ..
15763
15764 // RTL keeps pic_ovf indication in rd_softint and not softint.
15765 // So for set/clear writes, we send softint before the write ..,
15766 // and for read/asyncs we send rd_softint ..
15767
15768
15769 if (~`SOFTINT_RDWR_54) begin // {
15770 if (softint !== `RD_SOFTINT_REG_54 )
15771 softint_delta <= 1'b1;
15772 softint <= `RD_SOFTINT_REG_54;
15773 end // }
15774
15775 if ((`NAS_PIPE_FW2_54 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
15776 ) begin // {
15777 `PR_INFO ("pli_int", `INFO,
15778 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
15779 mycid,mytid, {47'h0, softint});
15780 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15781 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
15782 {47'h0, softint});
15783 end // }
15784 if (!(~`SOFTINT_RDWR_54&(softint !== `RD_SOFTINT_REG_54)))
15785 softint_delta <= 1'b0;
15786 end //}
15787 else if (`SPC6.tlu.asi_wr_clear_softint[6] |
15788 `SPC6.tlu.asi_wr_set_softint[6] ) begin // {
15789 `PR_INFO ("pli_int", `INFO,
15790 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
15791 mycid,mytid, {47'h0, `RD_SOFTINT_REG_54});
15792 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15793 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
15794 {47'h0, `RD_SOFTINT_REG_54});
15795 end // }
15796 end //}
15797
15798
15799 softint_rdwr <= `SOFTINT_RDWR_54 ;
15800 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_54;
15801
15802
15803/////////////////////////// Softint ///////////////////////////////////// }}}
15804
15805/////////////////////////// Hintp ///////////////////////////////////// {{{
15806
15807 // Hintp Register hardware Update Detection
15808
15809 // Non software updates (HSP)
15810 // If HINTP is already read/written by SW, then don't send
15811 // any async updates to Nas. Reads/Writes pending sstep is detected
15812 // by snooping nas_pipe ..
15813
15814 hintp <= `HINTP_REG_54 ;
15815 if (hstmatch_late)
15816 hintp_delta <= 1'b1;
15817
15818 if ((~hintp_rdwr & `NAS_PIPE_FW2_54 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
15819 (hintp_rdwr_late & hintp_delta) ) begin // {
15820 `PR_INFO ("pli_int", `INFO,
15821 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
15822 mycid,mytid, {63'h0, hintp});
15823 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
15824 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
15825 {63'h0, hintp});
15826 end // }
15827 if (~(hintp_rdwr_late & hintp_delta))
15828 hintp_delta <= 1'b0;
15829 end //}
15830
15831 hintp_rdwr <= `HINTP_RDWR_54;
15832 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_54;
15833 hstmatch_late <= `HSTMATCH_54;
15834
15835
15836/////////////////////////// Hintp ///////////////////////////////////// }}}
15837
15838end //}
15839`endif
15840endmodule
15841
15842// }}}
15843
15844module int_c6t7 ();
15845`ifndef GATESIM
15846
15847// common defines
15848`include "defines.vh"
15849`include "ccx.vri"
15850`include "cmp.vri"
15851
15852wire [2:0] mycid;
15853wire [2:0] mytid;
15854wire [5:0] mytnum;
15855integer junk;
15856
15857reg [63:0] int_vec_recv_reg;
15858reg int_vec_recv_reg_delta;
15859reg int_vec_reg_rdwr;
15860reg inc_vec_reg_rd;
15861reg int_vec_reg_rdwr_late;
15862reg [16:0] softint;
15863reg softint_rdwr;
15864reg softint_rdwr_late;
15865reg softint_delta;
15866reg hintp;
15867reg hintp_rdwr;
15868reg hintp_rdwr_late;
15869reg hintp_delta;
15870reg hstmatch_late;
15871reg ready;
15872reg [7:0] int_num_w;
15873reg [7:0] int_num_fx4;
15874reg [7:0] int_num_fx5;
15875reg [7:0] int_num_fb;
15876reg [7:0] int_num_fw;
15877reg [7:0] int_num_fw1;
15878reg [7:0] int_num_fw2;
15879reg take_disrupting_w;
15880reg take_disrupting_fx4;
15881reg take_disrupting_fx5;
15882reg take_disrupting_fb;
15883reg take_disrupting_fw;
15884reg take_disrupting_fw1;
15885reg take_disrupting_fw2;
15886
15887 assign mycid = 6;
15888 assign mytid = 7;
15889 assign mytnum = 6*8 + 7;
15890
15891initial begin // {
15892 ready = 0; // Wait for socket setup ..
15893 inc_vec_reg_rd <= 1'b0;
15894 int_vec_recv_reg_delta <= 1'b0;
15895 softint_delta <= 1'b0;
15896 hintp_delta <= 1'b0;
15897 int_vec_recv_reg = 64'b0;
15898 @(posedge `BENCH_SPC6_GCLK) ;
15899 @(posedge `BENCH_SPC6_GCLK) ;
15900 ready = `PARGS.int_sync_on;
15901end //}
15902
15903
15904/////////////////////////////// Probes //////////////////////////////////// {{{
15905
15906`define INT_VEC_RECV_REG_55 `SPC6.tlu.cth.int_rec7
15907`define INT_VEC_RECV_ASIWR_55 (`TOP.nas_top.c6.t7.asi_wr_int_rec_delay)
15908`define INT_VEC_RDWR_55 (`TOP.nas_top.c6.t7.asi_rdwr_int_rec)
15909`define INT_VEC_TAKEN_55 `SPC6.tlu.trl1.take_ivt&`SPC6.tlu.trl1.trap[3]
15910
15911`define CPU_MONDO_TAKEN_55 `SPC6.tlu.trl1.take_mqr&`SPC6.tlu.trl1.trap[3]
15912`define DEV_MONDO_TAKEN_55 `SPC6.tlu.trl1.take_dqr&`SPC6.tlu.trl1.trap[3]
15913`define RES_MONDO_TAKEN_55 `SPC6.tlu.trl1.take_rqr&`SPC6.tlu.trl1.trap[3]
15914
15915`define XIR_TAKEN_55 `SPC6.tlu.trl1.take_xir&`SPC6.tlu.trl1.trap[3]
15916
15917`define SOFTINT_RDWR_55 (`TOP.nas_top.c6.t7.asi_rdwr_softint|`TOP.nas_top.c6.t7.asi_wr_softint_delay)
15918
15919`define SOFTINT_REG_55 `SPC6.tlu.trl1.softint3
15920`define RD_SOFTINT_REG_55 `SPC6.tlu.trl1.rd_softint3
15921`define INT_LEVEL_TAKEN_55 `SPC6.tlu.trl1.take_iln&`SPC6.tlu.trl1.trap[3]
15922`define INT_LEVEL_NUM_55 `SPC6.tlu.trl1.int_level_n
15923`define PMU_TAKEN_55 `SPC6.tlu.trl1.take_pmu&`SPC6.tlu.trl1.trap[3]
15924
15925`define HINTP_RDWR_55 (`TOP.nas_top.c6.t7.asi_rdwr_hintp | `TOP.nas_top.c6.t7.asi_wr_hintp_delay)
15926`define HINTP_WR_55 (`SPC6.tlu.asi_wr_hintp[55])
15927`define HSTMATCH_55 `SPC6.tlu.trl1.hstick3_compare
15928
15929`define HINTP_REG_55 `SPC6.tlu.trl1.hintp3
15930`define HSTM_TAKEN_55 `SPC6.tlu.trl1.take_hst&`SPC6.tlu.trl1.trap[3]
15931
15932`define NAS_PIPE_FW2_55 |`TOP.nas_top.c6.t7.complete_fw2
15933
15934`define CWQ_TAKEN_55 `SPC6.tlu.trl1.take_cwq&`SPC6.tlu.trl1.trap[3]
15935`define SMA_TAKEN_55 `SPC6.tlu.trl1.take_sma&`SPC6.tlu.trl1.trap[3]
15936
15937`define POR_TAKEN_55 `SPC6.tlu.trl1.take_por&`SPC6.tlu.trl1.trap[3]
15938
15939/////////////////////////////// Probes //////////////////////////////////// }}}
15940
15941always @(negedge (`BENCH_SPC6_GCLK & ready)) begin // {
15942
15943 // {{{ DETECT, PIPE & SEND
15944 take_disrupting_w <= (`INT_VEC_TAKEN_55 || `CPU_MONDO_TAKEN_55 ||
15945 `DEV_MONDO_TAKEN_55 || `RES_MONDO_TAKEN_55 ||
15946 `XIR_TAKEN_55 || `INT_LEVEL_TAKEN_55 ||
15947 `HSTM_TAKEN_55 || `CWQ_TAKEN_55 ||
15948 `SMA_TAKEN_55 || `PMU_TAKEN_55 || `POR_TAKEN_55);
15949 take_disrupting_fx4 <= take_disrupting_w;
15950 take_disrupting_fx5 <= take_disrupting_fx4;
15951 take_disrupting_fb <= take_disrupting_fx5;
15952 take_disrupting_fw <= take_disrupting_fb;
15953 take_disrupting_fw1 <= take_disrupting_fw;
15954 take_disrupting_fw2 <= take_disrupting_fw1;
15955
15956 case ({`INT_VEC_TAKEN_55, `CPU_MONDO_TAKEN_55,
15957 `DEV_MONDO_TAKEN_55, `RES_MONDO_TAKEN_55,
15958 `XIR_TAKEN_55, `INT_LEVEL_TAKEN_55,
15959 `HSTM_TAKEN_55, `CWQ_TAKEN_55, `SMA_TAKEN_55 ,
15960 `PMU_TAKEN_55, `POR_TAKEN_55})
15961 11'b10000000000: int_num_w <= 8'h60;
15962 11'b01000000000: int_num_w <= 8'h7c;
15963 11'b00100000000: int_num_w <= 8'h7d;
15964 11'b00010000000: int_num_w <= 8'h7e;
15965 11'b00001000000: int_num_w <= 8'h03;
15966 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_55;
15967 11'b00000010000: int_num_w <= 8'h5e;
15968 11'b00000001000: int_num_w <= 8'h3c;
15969 11'b00000000100: int_num_w <= 8'h3d;
15970 11'b00000000010: int_num_w <= 8'h4f;
15971 11'b00000000001: int_num_w <= 8'h01;
15972 endcase
15973
15974 int_num_fx4 <= int_num_w;
15975 int_num_fx5 <= int_num_fx4;
15976 int_num_fb <= int_num_fx5;
15977 int_num_fw <= int_num_fb;
15978 int_num_fw1 <= int_num_fw;
15979 int_num_fw2 <= int_num_fw1;
15980 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
15981 begin // {
15982 `PR_INFO ("pli_int", `INFO,
15983 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
15984 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
15985 end // }
15986
15987 // }}}
15988
15989/////////////////////////// Vectored Interrupt /////////////////////////// {{{
15990
15991 // Vectored Interrupt Recv Register Detection
15992 // Indicate when register changes due to arriving interrupt, and not
15993 // due to read of incoming register or ASI write ..
15994
15995
15996 // If any read occurs, send value right away.
15997 // While a read/write is pending, do not update delta.
15998 // Send non read/wr delta during fw2 ..
15999
16000
16001 if (!(`INT_VEC_RDWR_55 | `INT_VEC_RECV_ASIWR_55)) begin // {
16002 if (~`INT_VEC_RECV_ASIWR_55 &
16003 (int_vec_recv_reg !== `INT_VEC_RECV_REG_55 ))
16004 int_vec_recv_reg_delta <= 1'b1;
16005 int_vec_recv_reg <= `INT_VEC_RECV_REG_55;
16006 end // }
16007 else if (`INT_VEC_RECV_ASIWR_55)
16008 int_vec_recv_reg <= `TOP.nas_top.c6.t7.asi_updated_int_rec;
16009
16010 if ((`NAS_PIPE_FW2_55 & int_vec_recv_reg_delta ) |
16011 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
16012 `INT_VEC_RECV_ASIWR_55 ) begin // {
16013 `PR_INFO ("pli_int", `INFO,
16014 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
16015 mycid,mytid, int_vec_recv_reg);
16016 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16017 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
16018 64'h0, int_vec_recv_reg);
16019 end // }
16020 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_55 &
16021 (int_vec_recv_reg !== `INT_VEC_RECV_REG_55 ))))
16022 int_vec_recv_reg_delta <= 1'b0;
16023 end //}
16024
16025 int_vec_reg_rdwr <= `INT_VEC_RDWR_55 | `INT_VEC_RECV_ASIWR_55;
16026 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_55 & ~ inc_vec_reg_rd;
16027
16028 if (`INT_VEC_RECV_ASIWR_55)
16029 inc_vec_reg_rd <= 1'b1;
16030 if (`NAS_PIPE_FW2_55)
16031 inc_vec_reg_rd <= 1'b0;
16032
16033
16034/////////////////////////// Vectored Interrupt /////////////////////////// }}}
16035
16036/////////////////////////// Asynchronous Resets ////////////////////////// {{{
16037
16038
16039/////////////////////////// Asynchronous Resets ////////////////////////// }}}
16040
16041/////////////////////////// Softint ///////////////////////////////////// {{{
16042
16043 // Softint Register hardware Update Detection
16044
16045 // Non software updates (TM/SM)
16046
16047 // If any read occurs, send value right away.
16048 // While a read/write is pending, do not update delta.
16049 // Send non read/wr delta during fw2 ..
16050
16051 // RTL keeps pic_ovf indication in rd_softint and not softint.
16052 // So for set/clear writes, we send softint before the write ..,
16053 // and for read/asyncs we send rd_softint ..
16054
16055
16056 if (~`SOFTINT_RDWR_55) begin // {
16057 if (softint !== `RD_SOFTINT_REG_55 )
16058 softint_delta <= 1'b1;
16059 softint <= `RD_SOFTINT_REG_55;
16060 end // }
16061
16062 if ((`NAS_PIPE_FW2_55 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
16063 ) begin // {
16064 `PR_INFO ("pli_int", `INFO,
16065 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16066 mycid,mytid, {47'h0, softint});
16067 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16068 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16069 {47'h0, softint});
16070 end // }
16071 if (!(~`SOFTINT_RDWR_55&(softint !== `RD_SOFTINT_REG_55)))
16072 softint_delta <= 1'b0;
16073 end //}
16074 else if (`SPC6.tlu.asi_wr_clear_softint[7] |
16075 `SPC6.tlu.asi_wr_set_softint[7] ) begin // {
16076 `PR_INFO ("pli_int", `INFO,
16077 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16078 mycid,mytid, {47'h0, `RD_SOFTINT_REG_55});
16079 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16080 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16081 {47'h0, `RD_SOFTINT_REG_55});
16082 end // }
16083 end //}
16084
16085
16086 softint_rdwr <= `SOFTINT_RDWR_55 ;
16087 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_55;
16088
16089
16090/////////////////////////// Softint ///////////////////////////////////// }}}
16091
16092/////////////////////////// Hintp ///////////////////////////////////// {{{
16093
16094 // Hintp Register hardware Update Detection
16095
16096 // Non software updates (HSP)
16097 // If HINTP is already read/written by SW, then don't send
16098 // any async updates to Nas. Reads/Writes pending sstep is detected
16099 // by snooping nas_pipe ..
16100
16101 hintp <= `HINTP_REG_55 ;
16102 if (hstmatch_late)
16103 hintp_delta <= 1'b1;
16104
16105 if ((~hintp_rdwr & `NAS_PIPE_FW2_55 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
16106 (hintp_rdwr_late & hintp_delta) ) begin // {
16107 `PR_INFO ("pli_int", `INFO,
16108 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
16109 mycid,mytid, {63'h0, hintp});
16110 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16111 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
16112 {63'h0, hintp});
16113 end // }
16114 if (~(hintp_rdwr_late & hintp_delta))
16115 hintp_delta <= 1'b0;
16116 end //}
16117
16118 hintp_rdwr <= `HINTP_RDWR_55;
16119 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_55;
16120 hstmatch_late <= `HSTMATCH_55;
16121
16122
16123/////////////////////////// Hintp ///////////////////////////////////// }}}
16124
16125end //}
16126`endif
16127endmodule
16128
16129`endif
16130`ifdef CORE_7
16131
16132// }}}
16133
16134module int_c7t0 ();
16135`ifndef GATESIM
16136
16137// common defines
16138`include "defines.vh"
16139`include "ccx.vri"
16140`include "cmp.vri"
16141
16142wire [2:0] mycid;
16143wire [2:0] mytid;
16144wire [5:0] mytnum;
16145integer junk;
16146
16147reg [63:0] int_vec_recv_reg;
16148reg int_vec_recv_reg_delta;
16149reg int_vec_reg_rdwr;
16150reg inc_vec_reg_rd;
16151reg int_vec_reg_rdwr_late;
16152reg [16:0] softint;
16153reg softint_rdwr;
16154reg softint_rdwr_late;
16155reg softint_delta;
16156reg hintp;
16157reg hintp_rdwr;
16158reg hintp_rdwr_late;
16159reg hintp_delta;
16160reg hstmatch_late;
16161reg ready;
16162reg [7:0] int_num_w;
16163reg [7:0] int_num_fx4;
16164reg [7:0] int_num_fx5;
16165reg [7:0] int_num_fb;
16166reg [7:0] int_num_fw;
16167reg [7:0] int_num_fw1;
16168reg [7:0] int_num_fw2;
16169reg take_disrupting_w;
16170reg take_disrupting_fx4;
16171reg take_disrupting_fx5;
16172reg take_disrupting_fb;
16173reg take_disrupting_fw;
16174reg take_disrupting_fw1;
16175reg take_disrupting_fw2;
16176
16177 assign mycid = 7;
16178 assign mytid = 0;
16179 assign mytnum = 7*8 + 0;
16180
16181initial begin // {
16182 ready = 0; // Wait for socket setup ..
16183 inc_vec_reg_rd <= 1'b0;
16184 int_vec_recv_reg_delta <= 1'b0;
16185 softint_delta <= 1'b0;
16186 hintp_delta <= 1'b0;
16187 int_vec_recv_reg = 64'b0;
16188 @(posedge `BENCH_SPC7_GCLK) ;
16189 @(posedge `BENCH_SPC7_GCLK) ;
16190 ready = `PARGS.int_sync_on;
16191end //}
16192
16193
16194/////////////////////////////// Probes //////////////////////////////////// {{{
16195
16196`define INT_VEC_RECV_REG_56 `SPC7.tlu.cth.int_rec0
16197`define INT_VEC_RECV_ASIWR_56 (`TOP.nas_top.c7.t0.asi_wr_int_rec_delay)
16198`define INT_VEC_RDWR_56 (`TOP.nas_top.c7.t0.asi_rdwr_int_rec)
16199`define INT_VEC_TAKEN_56 `SPC7.tlu.trl0.take_ivt&`SPC7.tlu.trl0.trap[0]
16200
16201`define CPU_MONDO_TAKEN_56 `SPC7.tlu.trl0.take_mqr&`SPC7.tlu.trl0.trap[0]
16202`define DEV_MONDO_TAKEN_56 `SPC7.tlu.trl0.take_dqr&`SPC7.tlu.trl0.trap[0]
16203`define RES_MONDO_TAKEN_56 `SPC7.tlu.trl0.take_rqr&`SPC7.tlu.trl0.trap[0]
16204
16205`define XIR_TAKEN_56 `SPC7.tlu.trl0.take_xir&`SPC7.tlu.trl0.trap[0]
16206
16207`define SOFTINT_RDWR_56 (`TOP.nas_top.c7.t0.asi_rdwr_softint|`TOP.nas_top.c7.t0.asi_wr_softint_delay)
16208
16209`define SOFTINT_REG_56 `SPC7.tlu.trl0.softint0
16210`define RD_SOFTINT_REG_56 `SPC7.tlu.trl0.rd_softint0
16211`define INT_LEVEL_TAKEN_56 `SPC7.tlu.trl0.take_iln&`SPC7.tlu.trl0.trap[0]
16212`define INT_LEVEL_NUM_56 `SPC7.tlu.trl0.int_level_n
16213`define PMU_TAKEN_56 `SPC7.tlu.trl0.take_pmu&`SPC7.tlu.trl0.trap[0]
16214
16215`define HINTP_RDWR_56 (`TOP.nas_top.c7.t0.asi_rdwr_hintp | `TOP.nas_top.c7.t0.asi_wr_hintp_delay)
16216`define HINTP_WR_56 (`SPC7.tlu.asi_wr_hintp[56])
16217`define HSTMATCH_56 `SPC7.tlu.trl0.hstick0_compare
16218
16219`define HINTP_REG_56 `SPC7.tlu.trl0.hintp0
16220`define HSTM_TAKEN_56 `SPC7.tlu.trl0.take_hst&`SPC7.tlu.trl0.trap[0]
16221
16222`define NAS_PIPE_FW2_56 |`TOP.nas_top.c7.t0.complete_fw2
16223
16224`define CWQ_TAKEN_56 `SPC7.tlu.trl0.take_cwq&`SPC7.tlu.trl0.trap[0]
16225`define SMA_TAKEN_56 `SPC7.tlu.trl0.take_sma&`SPC7.tlu.trl0.trap[0]
16226
16227`define POR_TAKEN_56 `SPC7.tlu.trl0.take_por&`SPC7.tlu.trl0.trap[0]
16228
16229/////////////////////////////// Probes //////////////////////////////////// }}}
16230
16231always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
16232
16233 // {{{ DETECT, PIPE & SEND
16234 take_disrupting_w <= (`INT_VEC_TAKEN_56 || `CPU_MONDO_TAKEN_56 ||
16235 `DEV_MONDO_TAKEN_56 || `RES_MONDO_TAKEN_56 ||
16236 `XIR_TAKEN_56 || `INT_LEVEL_TAKEN_56 ||
16237 `HSTM_TAKEN_56 || `CWQ_TAKEN_56 ||
16238 `SMA_TAKEN_56 || `PMU_TAKEN_56 || `POR_TAKEN_56);
16239 take_disrupting_fx4 <= take_disrupting_w;
16240 take_disrupting_fx5 <= take_disrupting_fx4;
16241 take_disrupting_fb <= take_disrupting_fx5;
16242 take_disrupting_fw <= take_disrupting_fb;
16243 take_disrupting_fw1 <= take_disrupting_fw;
16244 take_disrupting_fw2 <= take_disrupting_fw1;
16245
16246 case ({`INT_VEC_TAKEN_56, `CPU_MONDO_TAKEN_56,
16247 `DEV_MONDO_TAKEN_56, `RES_MONDO_TAKEN_56,
16248 `XIR_TAKEN_56, `INT_LEVEL_TAKEN_56,
16249 `HSTM_TAKEN_56, `CWQ_TAKEN_56, `SMA_TAKEN_56 ,
16250 `PMU_TAKEN_56, `POR_TAKEN_56})
16251 11'b10000000000: int_num_w <= 8'h60;
16252 11'b01000000000: int_num_w <= 8'h7c;
16253 11'b00100000000: int_num_w <= 8'h7d;
16254 11'b00010000000: int_num_w <= 8'h7e;
16255 11'b00001000000: int_num_w <= 8'h03;
16256 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_56;
16257 11'b00000010000: int_num_w <= 8'h5e;
16258 11'b00000001000: int_num_w <= 8'h3c;
16259 11'b00000000100: int_num_w <= 8'h3d;
16260 11'b00000000010: int_num_w <= 8'h4f;
16261 11'b00000000001: int_num_w <= 8'h01;
16262 endcase
16263
16264 int_num_fx4 <= int_num_w;
16265 int_num_fx5 <= int_num_fx4;
16266 int_num_fb <= int_num_fx5;
16267 int_num_fw <= int_num_fb;
16268 int_num_fw1 <= int_num_fw;
16269 int_num_fw2 <= int_num_fw1;
16270 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
16271 begin // {
16272 `PR_INFO ("pli_int", `INFO,
16273 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
16274 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
16275 end // }
16276
16277 // }}}
16278
16279/////////////////////////// Vectored Interrupt /////////////////////////// {{{
16280
16281 // Vectored Interrupt Recv Register Detection
16282 // Indicate when register changes due to arriving interrupt, and not
16283 // due to read of incoming register or ASI write ..
16284
16285
16286 // If any read occurs, send value right away.
16287 // While a read/write is pending, do not update delta.
16288 // Send non read/wr delta during fw2 ..
16289
16290
16291 if (!(`INT_VEC_RDWR_56 | `INT_VEC_RECV_ASIWR_56)) begin // {
16292 if (~`INT_VEC_RECV_ASIWR_56 &
16293 (int_vec_recv_reg !== `INT_VEC_RECV_REG_56 ))
16294 int_vec_recv_reg_delta <= 1'b1;
16295 int_vec_recv_reg <= `INT_VEC_RECV_REG_56;
16296 end // }
16297 else if (`INT_VEC_RECV_ASIWR_56)
16298 int_vec_recv_reg <= `TOP.nas_top.c7.t0.asi_updated_int_rec;
16299
16300 if ((`NAS_PIPE_FW2_56 & int_vec_recv_reg_delta ) |
16301 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
16302 `INT_VEC_RECV_ASIWR_56 ) begin // {
16303 `PR_INFO ("pli_int", `INFO,
16304 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
16305 mycid,mytid, int_vec_recv_reg);
16306 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16307 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
16308 64'h0, int_vec_recv_reg);
16309 end // }
16310 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_56 &
16311 (int_vec_recv_reg !== `INT_VEC_RECV_REG_56 ))))
16312 int_vec_recv_reg_delta <= 1'b0;
16313 end //}
16314
16315 int_vec_reg_rdwr <= `INT_VEC_RDWR_56 | `INT_VEC_RECV_ASIWR_56;
16316 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_56 & ~ inc_vec_reg_rd;
16317
16318 if (`INT_VEC_RECV_ASIWR_56)
16319 inc_vec_reg_rd <= 1'b1;
16320 if (`NAS_PIPE_FW2_56)
16321 inc_vec_reg_rd <= 1'b0;
16322
16323
16324/////////////////////////// Vectored Interrupt /////////////////////////// }}}
16325
16326/////////////////////////// Asynchronous Resets ////////////////////////// {{{
16327
16328
16329/////////////////////////// Asynchronous Resets ////////////////////////// }}}
16330
16331/////////////////////////// Softint ///////////////////////////////////// {{{
16332
16333 // Softint Register hardware Update Detection
16334
16335 // Non software updates (TM/SM)
16336
16337 // If any read occurs, send value right away.
16338 // While a read/write is pending, do not update delta.
16339 // Send non read/wr delta during fw2 ..
16340
16341 // RTL keeps pic_ovf indication in rd_softint and not softint.
16342 // So for set/clear writes, we send softint before the write ..,
16343 // and for read/asyncs we send rd_softint ..
16344
16345
16346 if (~`SOFTINT_RDWR_56) begin // {
16347 if (softint !== `RD_SOFTINT_REG_56 )
16348 softint_delta <= 1'b1;
16349 softint <= `RD_SOFTINT_REG_56;
16350 end // }
16351
16352 if ((`NAS_PIPE_FW2_56 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
16353 ) begin // {
16354 `PR_INFO ("pli_int", `INFO,
16355 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16356 mycid,mytid, {47'h0, softint});
16357 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16358 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16359 {47'h0, softint});
16360 end // }
16361 if (!(~`SOFTINT_RDWR_56&(softint !== `RD_SOFTINT_REG_56)))
16362 softint_delta <= 1'b0;
16363 end //}
16364 else if (`SPC7.tlu.asi_wr_clear_softint[0] |
16365 `SPC7.tlu.asi_wr_set_softint[0] ) begin // {
16366 `PR_INFO ("pli_int", `INFO,
16367 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16368 mycid,mytid, {47'h0, `RD_SOFTINT_REG_56});
16369 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16370 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16371 {47'h0, `RD_SOFTINT_REG_56});
16372 end // }
16373 end //}
16374
16375
16376 softint_rdwr <= `SOFTINT_RDWR_56 ;
16377 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_56;
16378
16379
16380/////////////////////////// Softint ///////////////////////////////////// }}}
16381
16382/////////////////////////// Hintp ///////////////////////////////////// {{{
16383
16384 // Hintp Register hardware Update Detection
16385
16386 // Non software updates (HSP)
16387 // If HINTP is already read/written by SW, then don't send
16388 // any async updates to Nas. Reads/Writes pending sstep is detected
16389 // by snooping nas_pipe ..
16390
16391 hintp <= `HINTP_REG_56 ;
16392 if (hstmatch_late)
16393 hintp_delta <= 1'b1;
16394
16395 if ((~hintp_rdwr & `NAS_PIPE_FW2_56 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
16396 (hintp_rdwr_late & hintp_delta) ) begin // {
16397 `PR_INFO ("pli_int", `INFO,
16398 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
16399 mycid,mytid, {63'h0, hintp});
16400 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16401 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
16402 {63'h0, hintp});
16403 end // }
16404 if (~(hintp_rdwr_late & hintp_delta))
16405 hintp_delta <= 1'b0;
16406 end //}
16407
16408 hintp_rdwr <= `HINTP_RDWR_56;
16409 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_56;
16410 hstmatch_late <= `HSTMATCH_56;
16411
16412
16413/////////////////////////// Hintp ///////////////////////////////////// }}}
16414
16415end //}
16416`endif
16417endmodule
16418
16419// }}}
16420
16421module int_c7t1 ();
16422`ifndef GATESIM
16423
16424// common defines
16425`include "defines.vh"
16426`include "ccx.vri"
16427`include "cmp.vri"
16428
16429wire [2:0] mycid;
16430wire [2:0] mytid;
16431wire [5:0] mytnum;
16432integer junk;
16433
16434reg [63:0] int_vec_recv_reg;
16435reg int_vec_recv_reg_delta;
16436reg int_vec_reg_rdwr;
16437reg inc_vec_reg_rd;
16438reg int_vec_reg_rdwr_late;
16439reg [16:0] softint;
16440reg softint_rdwr;
16441reg softint_rdwr_late;
16442reg softint_delta;
16443reg hintp;
16444reg hintp_rdwr;
16445reg hintp_rdwr_late;
16446reg hintp_delta;
16447reg hstmatch_late;
16448reg ready;
16449reg [7:0] int_num_w;
16450reg [7:0] int_num_fx4;
16451reg [7:0] int_num_fx5;
16452reg [7:0] int_num_fb;
16453reg [7:0] int_num_fw;
16454reg [7:0] int_num_fw1;
16455reg [7:0] int_num_fw2;
16456reg take_disrupting_w;
16457reg take_disrupting_fx4;
16458reg take_disrupting_fx5;
16459reg take_disrupting_fb;
16460reg take_disrupting_fw;
16461reg take_disrupting_fw1;
16462reg take_disrupting_fw2;
16463
16464 assign mycid = 7;
16465 assign mytid = 1;
16466 assign mytnum = 7*8 + 1;
16467
16468initial begin // {
16469 ready = 0; // Wait for socket setup ..
16470 inc_vec_reg_rd <= 1'b0;
16471 int_vec_recv_reg_delta <= 1'b0;
16472 softint_delta <= 1'b0;
16473 hintp_delta <= 1'b0;
16474 int_vec_recv_reg = 64'b0;
16475 @(posedge `BENCH_SPC7_GCLK) ;
16476 @(posedge `BENCH_SPC7_GCLK) ;
16477 ready = `PARGS.int_sync_on;
16478end //}
16479
16480
16481/////////////////////////////// Probes //////////////////////////////////// {{{
16482
16483`define INT_VEC_RECV_REG_57 `SPC7.tlu.cth.int_rec1
16484`define INT_VEC_RECV_ASIWR_57 (`TOP.nas_top.c7.t1.asi_wr_int_rec_delay)
16485`define INT_VEC_RDWR_57 (`TOP.nas_top.c7.t1.asi_rdwr_int_rec)
16486`define INT_VEC_TAKEN_57 `SPC7.tlu.trl0.take_ivt&`SPC7.tlu.trl0.trap[1]
16487
16488`define CPU_MONDO_TAKEN_57 `SPC7.tlu.trl0.take_mqr&`SPC7.tlu.trl0.trap[1]
16489`define DEV_MONDO_TAKEN_57 `SPC7.tlu.trl0.take_dqr&`SPC7.tlu.trl0.trap[1]
16490`define RES_MONDO_TAKEN_57 `SPC7.tlu.trl0.take_rqr&`SPC7.tlu.trl0.trap[1]
16491
16492`define XIR_TAKEN_57 `SPC7.tlu.trl0.take_xir&`SPC7.tlu.trl0.trap[1]
16493
16494`define SOFTINT_RDWR_57 (`TOP.nas_top.c7.t1.asi_rdwr_softint|`TOP.nas_top.c7.t1.asi_wr_softint_delay)
16495
16496`define SOFTINT_REG_57 `SPC7.tlu.trl0.softint1
16497`define RD_SOFTINT_REG_57 `SPC7.tlu.trl0.rd_softint1
16498`define INT_LEVEL_TAKEN_57 `SPC7.tlu.trl0.take_iln&`SPC7.tlu.trl0.trap[1]
16499`define INT_LEVEL_NUM_57 `SPC7.tlu.trl0.int_level_n
16500`define PMU_TAKEN_57 `SPC7.tlu.trl0.take_pmu&`SPC7.tlu.trl0.trap[1]
16501
16502`define HINTP_RDWR_57 (`TOP.nas_top.c7.t1.asi_rdwr_hintp | `TOP.nas_top.c7.t1.asi_wr_hintp_delay)
16503`define HINTP_WR_57 (`SPC7.tlu.asi_wr_hintp[57])
16504`define HSTMATCH_57 `SPC7.tlu.trl0.hstick1_compare
16505
16506`define HINTP_REG_57 `SPC7.tlu.trl0.hintp1
16507`define HSTM_TAKEN_57 `SPC7.tlu.trl0.take_hst&`SPC7.tlu.trl0.trap[1]
16508
16509`define NAS_PIPE_FW2_57 |`TOP.nas_top.c7.t1.complete_fw2
16510
16511`define CWQ_TAKEN_57 `SPC7.tlu.trl0.take_cwq&`SPC7.tlu.trl0.trap[1]
16512`define SMA_TAKEN_57 `SPC7.tlu.trl0.take_sma&`SPC7.tlu.trl0.trap[1]
16513
16514`define POR_TAKEN_57 `SPC7.tlu.trl0.take_por&`SPC7.tlu.trl0.trap[1]
16515
16516/////////////////////////////// Probes //////////////////////////////////// }}}
16517
16518always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
16519
16520 // {{{ DETECT, PIPE & SEND
16521 take_disrupting_w <= (`INT_VEC_TAKEN_57 || `CPU_MONDO_TAKEN_57 ||
16522 `DEV_MONDO_TAKEN_57 || `RES_MONDO_TAKEN_57 ||
16523 `XIR_TAKEN_57 || `INT_LEVEL_TAKEN_57 ||
16524 `HSTM_TAKEN_57 || `CWQ_TAKEN_57 ||
16525 `SMA_TAKEN_57 || `PMU_TAKEN_57 || `POR_TAKEN_57);
16526 take_disrupting_fx4 <= take_disrupting_w;
16527 take_disrupting_fx5 <= take_disrupting_fx4;
16528 take_disrupting_fb <= take_disrupting_fx5;
16529 take_disrupting_fw <= take_disrupting_fb;
16530 take_disrupting_fw1 <= take_disrupting_fw;
16531 take_disrupting_fw2 <= take_disrupting_fw1;
16532
16533 case ({`INT_VEC_TAKEN_57, `CPU_MONDO_TAKEN_57,
16534 `DEV_MONDO_TAKEN_57, `RES_MONDO_TAKEN_57,
16535 `XIR_TAKEN_57, `INT_LEVEL_TAKEN_57,
16536 `HSTM_TAKEN_57, `CWQ_TAKEN_57, `SMA_TAKEN_57 ,
16537 `PMU_TAKEN_57, `POR_TAKEN_57})
16538 11'b10000000000: int_num_w <= 8'h60;
16539 11'b01000000000: int_num_w <= 8'h7c;
16540 11'b00100000000: int_num_w <= 8'h7d;
16541 11'b00010000000: int_num_w <= 8'h7e;
16542 11'b00001000000: int_num_w <= 8'h03;
16543 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_57;
16544 11'b00000010000: int_num_w <= 8'h5e;
16545 11'b00000001000: int_num_w <= 8'h3c;
16546 11'b00000000100: int_num_w <= 8'h3d;
16547 11'b00000000010: int_num_w <= 8'h4f;
16548 11'b00000000001: int_num_w <= 8'h01;
16549 endcase
16550
16551 int_num_fx4 <= int_num_w;
16552 int_num_fx5 <= int_num_fx4;
16553 int_num_fb <= int_num_fx5;
16554 int_num_fw <= int_num_fb;
16555 int_num_fw1 <= int_num_fw;
16556 int_num_fw2 <= int_num_fw1;
16557 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
16558 begin // {
16559 `PR_INFO ("pli_int", `INFO,
16560 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
16561 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
16562 end // }
16563
16564 // }}}
16565
16566/////////////////////////// Vectored Interrupt /////////////////////////// {{{
16567
16568 // Vectored Interrupt Recv Register Detection
16569 // Indicate when register changes due to arriving interrupt, and not
16570 // due to read of incoming register or ASI write ..
16571
16572
16573 // If any read occurs, send value right away.
16574 // While a read/write is pending, do not update delta.
16575 // Send non read/wr delta during fw2 ..
16576
16577
16578 if (!(`INT_VEC_RDWR_57 | `INT_VEC_RECV_ASIWR_57)) begin // {
16579 if (~`INT_VEC_RECV_ASIWR_57 &
16580 (int_vec_recv_reg !== `INT_VEC_RECV_REG_57 ))
16581 int_vec_recv_reg_delta <= 1'b1;
16582 int_vec_recv_reg <= `INT_VEC_RECV_REG_57;
16583 end // }
16584 else if (`INT_VEC_RECV_ASIWR_57)
16585 int_vec_recv_reg <= `TOP.nas_top.c7.t1.asi_updated_int_rec;
16586
16587 if ((`NAS_PIPE_FW2_57 & int_vec_recv_reg_delta ) |
16588 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
16589 `INT_VEC_RECV_ASIWR_57 ) begin // {
16590 `PR_INFO ("pli_int", `INFO,
16591 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
16592 mycid,mytid, int_vec_recv_reg);
16593 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16594 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
16595 64'h0, int_vec_recv_reg);
16596 end // }
16597 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_57 &
16598 (int_vec_recv_reg !== `INT_VEC_RECV_REG_57 ))))
16599 int_vec_recv_reg_delta <= 1'b0;
16600 end //}
16601
16602 int_vec_reg_rdwr <= `INT_VEC_RDWR_57 | `INT_VEC_RECV_ASIWR_57;
16603 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_57 & ~ inc_vec_reg_rd;
16604
16605 if (`INT_VEC_RECV_ASIWR_57)
16606 inc_vec_reg_rd <= 1'b1;
16607 if (`NAS_PIPE_FW2_57)
16608 inc_vec_reg_rd <= 1'b0;
16609
16610
16611/////////////////////////// Vectored Interrupt /////////////////////////// }}}
16612
16613/////////////////////////// Asynchronous Resets ////////////////////////// {{{
16614
16615
16616/////////////////////////// Asynchronous Resets ////////////////////////// }}}
16617
16618/////////////////////////// Softint ///////////////////////////////////// {{{
16619
16620 // Softint Register hardware Update Detection
16621
16622 // Non software updates (TM/SM)
16623
16624 // If any read occurs, send value right away.
16625 // While a read/write is pending, do not update delta.
16626 // Send non read/wr delta during fw2 ..
16627
16628 // RTL keeps pic_ovf indication in rd_softint and not softint.
16629 // So for set/clear writes, we send softint before the write ..,
16630 // and for read/asyncs we send rd_softint ..
16631
16632
16633 if (~`SOFTINT_RDWR_57) begin // {
16634 if (softint !== `RD_SOFTINT_REG_57 )
16635 softint_delta <= 1'b1;
16636 softint <= `RD_SOFTINT_REG_57;
16637 end // }
16638
16639 if ((`NAS_PIPE_FW2_57 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
16640 ) begin // {
16641 `PR_INFO ("pli_int", `INFO,
16642 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16643 mycid,mytid, {47'h0, softint});
16644 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16645 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16646 {47'h0, softint});
16647 end // }
16648 if (!(~`SOFTINT_RDWR_57&(softint !== `RD_SOFTINT_REG_57)))
16649 softint_delta <= 1'b0;
16650 end //}
16651 else if (`SPC7.tlu.asi_wr_clear_softint[1] |
16652 `SPC7.tlu.asi_wr_set_softint[1] ) begin // {
16653 `PR_INFO ("pli_int", `INFO,
16654 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16655 mycid,mytid, {47'h0, `RD_SOFTINT_REG_57});
16656 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16657 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16658 {47'h0, `RD_SOFTINT_REG_57});
16659 end // }
16660 end //}
16661
16662
16663 softint_rdwr <= `SOFTINT_RDWR_57 ;
16664 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_57;
16665
16666
16667/////////////////////////// Softint ///////////////////////////////////// }}}
16668
16669/////////////////////////// Hintp ///////////////////////////////////// {{{
16670
16671 // Hintp Register hardware Update Detection
16672
16673 // Non software updates (HSP)
16674 // If HINTP is already read/written by SW, then don't send
16675 // any async updates to Nas. Reads/Writes pending sstep is detected
16676 // by snooping nas_pipe ..
16677
16678 hintp <= `HINTP_REG_57 ;
16679 if (hstmatch_late)
16680 hintp_delta <= 1'b1;
16681
16682 if ((~hintp_rdwr & `NAS_PIPE_FW2_57 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
16683 (hintp_rdwr_late & hintp_delta) ) begin // {
16684 `PR_INFO ("pli_int", `INFO,
16685 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
16686 mycid,mytid, {63'h0, hintp});
16687 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16688 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
16689 {63'h0, hintp});
16690 end // }
16691 if (~(hintp_rdwr_late & hintp_delta))
16692 hintp_delta <= 1'b0;
16693 end //}
16694
16695 hintp_rdwr <= `HINTP_RDWR_57;
16696 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_57;
16697 hstmatch_late <= `HSTMATCH_57;
16698
16699
16700/////////////////////////// Hintp ///////////////////////////////////// }}}
16701
16702end //}
16703`endif
16704endmodule
16705
16706// }}}
16707
16708module int_c7t2 ();
16709`ifndef GATESIM
16710
16711// common defines
16712`include "defines.vh"
16713`include "ccx.vri"
16714`include "cmp.vri"
16715
16716wire [2:0] mycid;
16717wire [2:0] mytid;
16718wire [5:0] mytnum;
16719integer junk;
16720
16721reg [63:0] int_vec_recv_reg;
16722reg int_vec_recv_reg_delta;
16723reg int_vec_reg_rdwr;
16724reg inc_vec_reg_rd;
16725reg int_vec_reg_rdwr_late;
16726reg [16:0] softint;
16727reg softint_rdwr;
16728reg softint_rdwr_late;
16729reg softint_delta;
16730reg hintp;
16731reg hintp_rdwr;
16732reg hintp_rdwr_late;
16733reg hintp_delta;
16734reg hstmatch_late;
16735reg ready;
16736reg [7:0] int_num_w;
16737reg [7:0] int_num_fx4;
16738reg [7:0] int_num_fx5;
16739reg [7:0] int_num_fb;
16740reg [7:0] int_num_fw;
16741reg [7:0] int_num_fw1;
16742reg [7:0] int_num_fw2;
16743reg take_disrupting_w;
16744reg take_disrupting_fx4;
16745reg take_disrupting_fx5;
16746reg take_disrupting_fb;
16747reg take_disrupting_fw;
16748reg take_disrupting_fw1;
16749reg take_disrupting_fw2;
16750
16751 assign mycid = 7;
16752 assign mytid = 2;
16753 assign mytnum = 7*8 + 2;
16754
16755initial begin // {
16756 ready = 0; // Wait for socket setup ..
16757 inc_vec_reg_rd <= 1'b0;
16758 int_vec_recv_reg_delta <= 1'b0;
16759 softint_delta <= 1'b0;
16760 hintp_delta <= 1'b0;
16761 int_vec_recv_reg = 64'b0;
16762 @(posedge `BENCH_SPC7_GCLK) ;
16763 @(posedge `BENCH_SPC7_GCLK) ;
16764 ready = `PARGS.int_sync_on;
16765end //}
16766
16767
16768/////////////////////////////// Probes //////////////////////////////////// {{{
16769
16770`define INT_VEC_RECV_REG_58 `SPC7.tlu.cth.int_rec2
16771`define INT_VEC_RECV_ASIWR_58 (`TOP.nas_top.c7.t2.asi_wr_int_rec_delay)
16772`define INT_VEC_RDWR_58 (`TOP.nas_top.c7.t2.asi_rdwr_int_rec)
16773`define INT_VEC_TAKEN_58 `SPC7.tlu.trl0.take_ivt&`SPC7.tlu.trl0.trap[2]
16774
16775`define CPU_MONDO_TAKEN_58 `SPC7.tlu.trl0.take_mqr&`SPC7.tlu.trl0.trap[2]
16776`define DEV_MONDO_TAKEN_58 `SPC7.tlu.trl0.take_dqr&`SPC7.tlu.trl0.trap[2]
16777`define RES_MONDO_TAKEN_58 `SPC7.tlu.trl0.take_rqr&`SPC7.tlu.trl0.trap[2]
16778
16779`define XIR_TAKEN_58 `SPC7.tlu.trl0.take_xir&`SPC7.tlu.trl0.trap[2]
16780
16781`define SOFTINT_RDWR_58 (`TOP.nas_top.c7.t2.asi_rdwr_softint|`TOP.nas_top.c7.t2.asi_wr_softint_delay)
16782
16783`define SOFTINT_REG_58 `SPC7.tlu.trl0.softint2
16784`define RD_SOFTINT_REG_58 `SPC7.tlu.trl0.rd_softint2
16785`define INT_LEVEL_TAKEN_58 `SPC7.tlu.trl0.take_iln&`SPC7.tlu.trl0.trap[2]
16786`define INT_LEVEL_NUM_58 `SPC7.tlu.trl0.int_level_n
16787`define PMU_TAKEN_58 `SPC7.tlu.trl0.take_pmu&`SPC7.tlu.trl0.trap[2]
16788
16789`define HINTP_RDWR_58 (`TOP.nas_top.c7.t2.asi_rdwr_hintp | `TOP.nas_top.c7.t2.asi_wr_hintp_delay)
16790`define HINTP_WR_58 (`SPC7.tlu.asi_wr_hintp[58])
16791`define HSTMATCH_58 `SPC7.tlu.trl0.hstick2_compare
16792
16793`define HINTP_REG_58 `SPC7.tlu.trl0.hintp2
16794`define HSTM_TAKEN_58 `SPC7.tlu.trl0.take_hst&`SPC7.tlu.trl0.trap[2]
16795
16796`define NAS_PIPE_FW2_58 |`TOP.nas_top.c7.t2.complete_fw2
16797
16798`define CWQ_TAKEN_58 `SPC7.tlu.trl0.take_cwq&`SPC7.tlu.trl0.trap[2]
16799`define SMA_TAKEN_58 `SPC7.tlu.trl0.take_sma&`SPC7.tlu.trl0.trap[2]
16800
16801`define POR_TAKEN_58 `SPC7.tlu.trl0.take_por&`SPC7.tlu.trl0.trap[2]
16802
16803/////////////////////////////// Probes //////////////////////////////////// }}}
16804
16805always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
16806
16807 // {{{ DETECT, PIPE & SEND
16808 take_disrupting_w <= (`INT_VEC_TAKEN_58 || `CPU_MONDO_TAKEN_58 ||
16809 `DEV_MONDO_TAKEN_58 || `RES_MONDO_TAKEN_58 ||
16810 `XIR_TAKEN_58 || `INT_LEVEL_TAKEN_58 ||
16811 `HSTM_TAKEN_58 || `CWQ_TAKEN_58 ||
16812 `SMA_TAKEN_58 || `PMU_TAKEN_58 || `POR_TAKEN_58);
16813 take_disrupting_fx4 <= take_disrupting_w;
16814 take_disrupting_fx5 <= take_disrupting_fx4;
16815 take_disrupting_fb <= take_disrupting_fx5;
16816 take_disrupting_fw <= take_disrupting_fb;
16817 take_disrupting_fw1 <= take_disrupting_fw;
16818 take_disrupting_fw2 <= take_disrupting_fw1;
16819
16820 case ({`INT_VEC_TAKEN_58, `CPU_MONDO_TAKEN_58,
16821 `DEV_MONDO_TAKEN_58, `RES_MONDO_TAKEN_58,
16822 `XIR_TAKEN_58, `INT_LEVEL_TAKEN_58,
16823 `HSTM_TAKEN_58, `CWQ_TAKEN_58, `SMA_TAKEN_58 ,
16824 `PMU_TAKEN_58, `POR_TAKEN_58})
16825 11'b10000000000: int_num_w <= 8'h60;
16826 11'b01000000000: int_num_w <= 8'h7c;
16827 11'b00100000000: int_num_w <= 8'h7d;
16828 11'b00010000000: int_num_w <= 8'h7e;
16829 11'b00001000000: int_num_w <= 8'h03;
16830 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_58;
16831 11'b00000010000: int_num_w <= 8'h5e;
16832 11'b00000001000: int_num_w <= 8'h3c;
16833 11'b00000000100: int_num_w <= 8'h3d;
16834 11'b00000000010: int_num_w <= 8'h4f;
16835 11'b00000000001: int_num_w <= 8'h01;
16836 endcase
16837
16838 int_num_fx4 <= int_num_w;
16839 int_num_fx5 <= int_num_fx4;
16840 int_num_fb <= int_num_fx5;
16841 int_num_fw <= int_num_fb;
16842 int_num_fw1 <= int_num_fw;
16843 int_num_fw2 <= int_num_fw1;
16844 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
16845 begin // {
16846 `PR_INFO ("pli_int", `INFO,
16847 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
16848 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
16849 end // }
16850
16851 // }}}
16852
16853/////////////////////////// Vectored Interrupt /////////////////////////// {{{
16854
16855 // Vectored Interrupt Recv Register Detection
16856 // Indicate when register changes due to arriving interrupt, and not
16857 // due to read of incoming register or ASI write ..
16858
16859
16860 // If any read occurs, send value right away.
16861 // While a read/write is pending, do not update delta.
16862 // Send non read/wr delta during fw2 ..
16863
16864
16865 if (!(`INT_VEC_RDWR_58 | `INT_VEC_RECV_ASIWR_58)) begin // {
16866 if (~`INT_VEC_RECV_ASIWR_58 &
16867 (int_vec_recv_reg !== `INT_VEC_RECV_REG_58 ))
16868 int_vec_recv_reg_delta <= 1'b1;
16869 int_vec_recv_reg <= `INT_VEC_RECV_REG_58;
16870 end // }
16871 else if (`INT_VEC_RECV_ASIWR_58)
16872 int_vec_recv_reg <= `TOP.nas_top.c7.t2.asi_updated_int_rec;
16873
16874 if ((`NAS_PIPE_FW2_58 & int_vec_recv_reg_delta ) |
16875 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
16876 `INT_VEC_RECV_ASIWR_58 ) begin // {
16877 `PR_INFO ("pli_int", `INFO,
16878 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
16879 mycid,mytid, int_vec_recv_reg);
16880 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16881 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
16882 64'h0, int_vec_recv_reg);
16883 end // }
16884 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_58 &
16885 (int_vec_recv_reg !== `INT_VEC_RECV_REG_58 ))))
16886 int_vec_recv_reg_delta <= 1'b0;
16887 end //}
16888
16889 int_vec_reg_rdwr <= `INT_VEC_RDWR_58 | `INT_VEC_RECV_ASIWR_58;
16890 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_58 & ~ inc_vec_reg_rd;
16891
16892 if (`INT_VEC_RECV_ASIWR_58)
16893 inc_vec_reg_rd <= 1'b1;
16894 if (`NAS_PIPE_FW2_58)
16895 inc_vec_reg_rd <= 1'b0;
16896
16897
16898/////////////////////////// Vectored Interrupt /////////////////////////// }}}
16899
16900/////////////////////////// Asynchronous Resets ////////////////////////// {{{
16901
16902
16903/////////////////////////// Asynchronous Resets ////////////////////////// }}}
16904
16905/////////////////////////// Softint ///////////////////////////////////// {{{
16906
16907 // Softint Register hardware Update Detection
16908
16909 // Non software updates (TM/SM)
16910
16911 // If any read occurs, send value right away.
16912 // While a read/write is pending, do not update delta.
16913 // Send non read/wr delta during fw2 ..
16914
16915 // RTL keeps pic_ovf indication in rd_softint and not softint.
16916 // So for set/clear writes, we send softint before the write ..,
16917 // and for read/asyncs we send rd_softint ..
16918
16919
16920 if (~`SOFTINT_RDWR_58) begin // {
16921 if (softint !== `RD_SOFTINT_REG_58 )
16922 softint_delta <= 1'b1;
16923 softint <= `RD_SOFTINT_REG_58;
16924 end // }
16925
16926 if ((`NAS_PIPE_FW2_58 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
16927 ) begin // {
16928 `PR_INFO ("pli_int", `INFO,
16929 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16930 mycid,mytid, {47'h0, softint});
16931 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16932 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16933 {47'h0, softint});
16934 end // }
16935 if (!(~`SOFTINT_RDWR_58&(softint !== `RD_SOFTINT_REG_58)))
16936 softint_delta <= 1'b0;
16937 end //}
16938 else if (`SPC7.tlu.asi_wr_clear_softint[2] |
16939 `SPC7.tlu.asi_wr_set_softint[2] ) begin // {
16940 `PR_INFO ("pli_int", `INFO,
16941 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
16942 mycid,mytid, {47'h0, `RD_SOFTINT_REG_58});
16943 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16944 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
16945 {47'h0, `RD_SOFTINT_REG_58});
16946 end // }
16947 end //}
16948
16949
16950 softint_rdwr <= `SOFTINT_RDWR_58 ;
16951 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_58;
16952
16953
16954/////////////////////////// Softint ///////////////////////////////////// }}}
16955
16956/////////////////////////// Hintp ///////////////////////////////////// {{{
16957
16958 // Hintp Register hardware Update Detection
16959
16960 // Non software updates (HSP)
16961 // If HINTP is already read/written by SW, then don't send
16962 // any async updates to Nas. Reads/Writes pending sstep is detected
16963 // by snooping nas_pipe ..
16964
16965 hintp <= `HINTP_REG_58 ;
16966 if (hstmatch_late)
16967 hintp_delta <= 1'b1;
16968
16969 if ((~hintp_rdwr & `NAS_PIPE_FW2_58 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
16970 (hintp_rdwr_late & hintp_delta) ) begin // {
16971 `PR_INFO ("pli_int", `INFO,
16972 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
16973 mycid,mytid, {63'h0, hintp});
16974 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
16975 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
16976 {63'h0, hintp});
16977 end // }
16978 if (~(hintp_rdwr_late & hintp_delta))
16979 hintp_delta <= 1'b0;
16980 end //}
16981
16982 hintp_rdwr <= `HINTP_RDWR_58;
16983 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_58;
16984 hstmatch_late <= `HSTMATCH_58;
16985
16986
16987/////////////////////////// Hintp ///////////////////////////////////// }}}
16988
16989end //}
16990`endif
16991endmodule
16992
16993// }}}
16994
16995module int_c7t3 ();
16996`ifndef GATESIM
16997
16998// common defines
16999`include "defines.vh"
17000`include "ccx.vri"
17001`include "cmp.vri"
17002
17003wire [2:0] mycid;
17004wire [2:0] mytid;
17005wire [5:0] mytnum;
17006integer junk;
17007
17008reg [63:0] int_vec_recv_reg;
17009reg int_vec_recv_reg_delta;
17010reg int_vec_reg_rdwr;
17011reg inc_vec_reg_rd;
17012reg int_vec_reg_rdwr_late;
17013reg [16:0] softint;
17014reg softint_rdwr;
17015reg softint_rdwr_late;
17016reg softint_delta;
17017reg hintp;
17018reg hintp_rdwr;
17019reg hintp_rdwr_late;
17020reg hintp_delta;
17021reg hstmatch_late;
17022reg ready;
17023reg [7:0] int_num_w;
17024reg [7:0] int_num_fx4;
17025reg [7:0] int_num_fx5;
17026reg [7:0] int_num_fb;
17027reg [7:0] int_num_fw;
17028reg [7:0] int_num_fw1;
17029reg [7:0] int_num_fw2;
17030reg take_disrupting_w;
17031reg take_disrupting_fx4;
17032reg take_disrupting_fx5;
17033reg take_disrupting_fb;
17034reg take_disrupting_fw;
17035reg take_disrupting_fw1;
17036reg take_disrupting_fw2;
17037
17038 assign mycid = 7;
17039 assign mytid = 3;
17040 assign mytnum = 7*8 + 3;
17041
17042initial begin // {
17043 ready = 0; // Wait for socket setup ..
17044 inc_vec_reg_rd <= 1'b0;
17045 int_vec_recv_reg_delta <= 1'b0;
17046 softint_delta <= 1'b0;
17047 hintp_delta <= 1'b0;
17048 int_vec_recv_reg = 64'b0;
17049 @(posedge `BENCH_SPC7_GCLK) ;
17050 @(posedge `BENCH_SPC7_GCLK) ;
17051 ready = `PARGS.int_sync_on;
17052end //}
17053
17054
17055/////////////////////////////// Probes //////////////////////////////////// {{{
17056
17057`define INT_VEC_RECV_REG_59 `SPC7.tlu.cth.int_rec3
17058`define INT_VEC_RECV_ASIWR_59 (`TOP.nas_top.c7.t3.asi_wr_int_rec_delay)
17059`define INT_VEC_RDWR_59 (`TOP.nas_top.c7.t3.asi_rdwr_int_rec)
17060`define INT_VEC_TAKEN_59 `SPC7.tlu.trl0.take_ivt&`SPC7.tlu.trl0.trap[3]
17061
17062`define CPU_MONDO_TAKEN_59 `SPC7.tlu.trl0.take_mqr&`SPC7.tlu.trl0.trap[3]
17063`define DEV_MONDO_TAKEN_59 `SPC7.tlu.trl0.take_dqr&`SPC7.tlu.trl0.trap[3]
17064`define RES_MONDO_TAKEN_59 `SPC7.tlu.trl0.take_rqr&`SPC7.tlu.trl0.trap[3]
17065
17066`define XIR_TAKEN_59 `SPC7.tlu.trl0.take_xir&`SPC7.tlu.trl0.trap[3]
17067
17068`define SOFTINT_RDWR_59 (`TOP.nas_top.c7.t3.asi_rdwr_softint|`TOP.nas_top.c7.t3.asi_wr_softint_delay)
17069
17070`define SOFTINT_REG_59 `SPC7.tlu.trl0.softint3
17071`define RD_SOFTINT_REG_59 `SPC7.tlu.trl0.rd_softint3
17072`define INT_LEVEL_TAKEN_59 `SPC7.tlu.trl0.take_iln&`SPC7.tlu.trl0.trap[3]
17073`define INT_LEVEL_NUM_59 `SPC7.tlu.trl0.int_level_n
17074`define PMU_TAKEN_59 `SPC7.tlu.trl0.take_pmu&`SPC7.tlu.trl0.trap[3]
17075
17076`define HINTP_RDWR_59 (`TOP.nas_top.c7.t3.asi_rdwr_hintp | `TOP.nas_top.c7.t3.asi_wr_hintp_delay)
17077`define HINTP_WR_59 (`SPC7.tlu.asi_wr_hintp[59])
17078`define HSTMATCH_59 `SPC7.tlu.trl0.hstick3_compare
17079
17080`define HINTP_REG_59 `SPC7.tlu.trl0.hintp3
17081`define HSTM_TAKEN_59 `SPC7.tlu.trl0.take_hst&`SPC7.tlu.trl0.trap[3]
17082
17083`define NAS_PIPE_FW2_59 |`TOP.nas_top.c7.t3.complete_fw2
17084
17085`define CWQ_TAKEN_59 `SPC7.tlu.trl0.take_cwq&`SPC7.tlu.trl0.trap[3]
17086`define SMA_TAKEN_59 `SPC7.tlu.trl0.take_sma&`SPC7.tlu.trl0.trap[3]
17087
17088`define POR_TAKEN_59 `SPC7.tlu.trl0.take_por&`SPC7.tlu.trl0.trap[3]
17089
17090/////////////////////////////// Probes //////////////////////////////////// }}}
17091
17092always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
17093
17094 // {{{ DETECT, PIPE & SEND
17095 take_disrupting_w <= (`INT_VEC_TAKEN_59 || `CPU_MONDO_TAKEN_59 ||
17096 `DEV_MONDO_TAKEN_59 || `RES_MONDO_TAKEN_59 ||
17097 `XIR_TAKEN_59 || `INT_LEVEL_TAKEN_59 ||
17098 `HSTM_TAKEN_59 || `CWQ_TAKEN_59 ||
17099 `SMA_TAKEN_59 || `PMU_TAKEN_59 || `POR_TAKEN_59);
17100 take_disrupting_fx4 <= take_disrupting_w;
17101 take_disrupting_fx5 <= take_disrupting_fx4;
17102 take_disrupting_fb <= take_disrupting_fx5;
17103 take_disrupting_fw <= take_disrupting_fb;
17104 take_disrupting_fw1 <= take_disrupting_fw;
17105 take_disrupting_fw2 <= take_disrupting_fw1;
17106
17107 case ({`INT_VEC_TAKEN_59, `CPU_MONDO_TAKEN_59,
17108 `DEV_MONDO_TAKEN_59, `RES_MONDO_TAKEN_59,
17109 `XIR_TAKEN_59, `INT_LEVEL_TAKEN_59,
17110 `HSTM_TAKEN_59, `CWQ_TAKEN_59, `SMA_TAKEN_59 ,
17111 `PMU_TAKEN_59, `POR_TAKEN_59})
17112 11'b10000000000: int_num_w <= 8'h60;
17113 11'b01000000000: int_num_w <= 8'h7c;
17114 11'b00100000000: int_num_w <= 8'h7d;
17115 11'b00010000000: int_num_w <= 8'h7e;
17116 11'b00001000000: int_num_w <= 8'h03;
17117 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_59;
17118 11'b00000010000: int_num_w <= 8'h5e;
17119 11'b00000001000: int_num_w <= 8'h3c;
17120 11'b00000000100: int_num_w <= 8'h3d;
17121 11'b00000000010: int_num_w <= 8'h4f;
17122 11'b00000000001: int_num_w <= 8'h01;
17123 endcase
17124
17125 int_num_fx4 <= int_num_w;
17126 int_num_fx5 <= int_num_fx4;
17127 int_num_fb <= int_num_fx5;
17128 int_num_fw <= int_num_fb;
17129 int_num_fw1 <= int_num_fw;
17130 int_num_fw2 <= int_num_fw1;
17131 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
17132 begin // {
17133 `PR_INFO ("pli_int", `INFO,
17134 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
17135 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17136 end // }
17137
17138 // }}}
17139
17140/////////////////////////// Vectored Interrupt /////////////////////////// {{{
17141
17142 // Vectored Interrupt Recv Register Detection
17143 // Indicate when register changes due to arriving interrupt, and not
17144 // due to read of incoming register or ASI write ..
17145
17146
17147 // If any read occurs, send value right away.
17148 // While a read/write is pending, do not update delta.
17149 // Send non read/wr delta during fw2 ..
17150
17151
17152 if (!(`INT_VEC_RDWR_59 | `INT_VEC_RECV_ASIWR_59)) begin // {
17153 if (~`INT_VEC_RECV_ASIWR_59 &
17154 (int_vec_recv_reg !== `INT_VEC_RECV_REG_59 ))
17155 int_vec_recv_reg_delta <= 1'b1;
17156 int_vec_recv_reg <= `INT_VEC_RECV_REG_59;
17157 end // }
17158 else if (`INT_VEC_RECV_ASIWR_59)
17159 int_vec_recv_reg <= `TOP.nas_top.c7.t3.asi_updated_int_rec;
17160
17161 if ((`NAS_PIPE_FW2_59 & int_vec_recv_reg_delta ) |
17162 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
17163 `INT_VEC_RECV_ASIWR_59 ) begin // {
17164 `PR_INFO ("pli_int", `INFO,
17165 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
17166 mycid,mytid, int_vec_recv_reg);
17167 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17168 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
17169 64'h0, int_vec_recv_reg);
17170 end // }
17171 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_59 &
17172 (int_vec_recv_reg !== `INT_VEC_RECV_REG_59 ))))
17173 int_vec_recv_reg_delta <= 1'b0;
17174 end //}
17175
17176 int_vec_reg_rdwr <= `INT_VEC_RDWR_59 | `INT_VEC_RECV_ASIWR_59;
17177 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_59 & ~ inc_vec_reg_rd;
17178
17179 if (`INT_VEC_RECV_ASIWR_59)
17180 inc_vec_reg_rd <= 1'b1;
17181 if (`NAS_PIPE_FW2_59)
17182 inc_vec_reg_rd <= 1'b0;
17183
17184
17185/////////////////////////// Vectored Interrupt /////////////////////////// }}}
17186
17187/////////////////////////// Asynchronous Resets ////////////////////////// {{{
17188
17189
17190/////////////////////////// Asynchronous Resets ////////////////////////// }}}
17191
17192/////////////////////////// Softint ///////////////////////////////////// {{{
17193
17194 // Softint Register hardware Update Detection
17195
17196 // Non software updates (TM/SM)
17197
17198 // If any read occurs, send value right away.
17199 // While a read/write is pending, do not update delta.
17200 // Send non read/wr delta during fw2 ..
17201
17202 // RTL keeps pic_ovf indication in rd_softint and not softint.
17203 // So for set/clear writes, we send softint before the write ..,
17204 // and for read/asyncs we send rd_softint ..
17205
17206
17207 if (~`SOFTINT_RDWR_59) begin // {
17208 if (softint !== `RD_SOFTINT_REG_59 )
17209 softint_delta <= 1'b1;
17210 softint <= `RD_SOFTINT_REG_59;
17211 end // }
17212
17213 if ((`NAS_PIPE_FW2_59 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
17214 ) begin // {
17215 `PR_INFO ("pli_int", `INFO,
17216 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
17217 mycid,mytid, {47'h0, softint});
17218 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17219 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
17220 {47'h0, softint});
17221 end // }
17222 if (!(~`SOFTINT_RDWR_59&(softint !== `RD_SOFTINT_REG_59)))
17223 softint_delta <= 1'b0;
17224 end //}
17225 else if (`SPC7.tlu.asi_wr_clear_softint[3] |
17226 `SPC7.tlu.asi_wr_set_softint[3] ) begin // {
17227 `PR_INFO ("pli_int", `INFO,
17228 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
17229 mycid,mytid, {47'h0, `RD_SOFTINT_REG_59});
17230 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17231 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
17232 {47'h0, `RD_SOFTINT_REG_59});
17233 end // }
17234 end //}
17235
17236
17237 softint_rdwr <= `SOFTINT_RDWR_59 ;
17238 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_59;
17239
17240
17241/////////////////////////// Softint ///////////////////////////////////// }}}
17242
17243/////////////////////////// Hintp ///////////////////////////////////// {{{
17244
17245 // Hintp Register hardware Update Detection
17246
17247 // Non software updates (HSP)
17248 // If HINTP is already read/written by SW, then don't send
17249 // any async updates to Nas. Reads/Writes pending sstep is detected
17250 // by snooping nas_pipe ..
17251
17252 hintp <= `HINTP_REG_59 ;
17253 if (hstmatch_late)
17254 hintp_delta <= 1'b1;
17255
17256 if ((~hintp_rdwr & `NAS_PIPE_FW2_59 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
17257 (hintp_rdwr_late & hintp_delta) ) begin // {
17258 `PR_INFO ("pli_int", `INFO,
17259 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
17260 mycid,mytid, {63'h0, hintp});
17261 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17262 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
17263 {63'h0, hintp});
17264 end // }
17265 if (~(hintp_rdwr_late & hintp_delta))
17266 hintp_delta <= 1'b0;
17267 end //}
17268
17269 hintp_rdwr <= `HINTP_RDWR_59;
17270 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_59;
17271 hstmatch_late <= `HSTMATCH_59;
17272
17273
17274/////////////////////////// Hintp ///////////////////////////////////// }}}
17275
17276end //}
17277`endif
17278endmodule
17279
17280// }}}
17281
17282module int_c7t4 ();
17283`ifndef GATESIM
17284
17285// common defines
17286`include "defines.vh"
17287`include "ccx.vri"
17288`include "cmp.vri"
17289
17290wire [2:0] mycid;
17291wire [2:0] mytid;
17292wire [5:0] mytnum;
17293integer junk;
17294
17295reg [63:0] int_vec_recv_reg;
17296reg int_vec_recv_reg_delta;
17297reg int_vec_reg_rdwr;
17298reg inc_vec_reg_rd;
17299reg int_vec_reg_rdwr_late;
17300reg [16:0] softint;
17301reg softint_rdwr;
17302reg softint_rdwr_late;
17303reg softint_delta;
17304reg hintp;
17305reg hintp_rdwr;
17306reg hintp_rdwr_late;
17307reg hintp_delta;
17308reg hstmatch_late;
17309reg ready;
17310reg [7:0] int_num_w;
17311reg [7:0] int_num_fx4;
17312reg [7:0] int_num_fx5;
17313reg [7:0] int_num_fb;
17314reg [7:0] int_num_fw;
17315reg [7:0] int_num_fw1;
17316reg [7:0] int_num_fw2;
17317reg take_disrupting_w;
17318reg take_disrupting_fx4;
17319reg take_disrupting_fx5;
17320reg take_disrupting_fb;
17321reg take_disrupting_fw;
17322reg take_disrupting_fw1;
17323reg take_disrupting_fw2;
17324
17325 assign mycid = 7;
17326 assign mytid = 4;
17327 assign mytnum = 7*8 + 4;
17328
17329initial begin // {
17330 ready = 0; // Wait for socket setup ..
17331 inc_vec_reg_rd <= 1'b0;
17332 int_vec_recv_reg_delta <= 1'b0;
17333 softint_delta <= 1'b0;
17334 hintp_delta <= 1'b0;
17335 int_vec_recv_reg = 64'b0;
17336 @(posedge `BENCH_SPC7_GCLK) ;
17337 @(posedge `BENCH_SPC7_GCLK) ;
17338 ready = `PARGS.int_sync_on;
17339end //}
17340
17341
17342/////////////////////////////// Probes //////////////////////////////////// {{{
17343
17344`define INT_VEC_RECV_REG_60 `SPC7.tlu.cth.int_rec4
17345`define INT_VEC_RECV_ASIWR_60 (`TOP.nas_top.c7.t4.asi_wr_int_rec_delay)
17346`define INT_VEC_RDWR_60 (`TOP.nas_top.c7.t4.asi_rdwr_int_rec)
17347`define INT_VEC_TAKEN_60 `SPC7.tlu.trl1.take_ivt&`SPC7.tlu.trl1.trap[0]
17348
17349`define CPU_MONDO_TAKEN_60 `SPC7.tlu.trl1.take_mqr&`SPC7.tlu.trl1.trap[0]
17350`define DEV_MONDO_TAKEN_60 `SPC7.tlu.trl1.take_dqr&`SPC7.tlu.trl1.trap[0]
17351`define RES_MONDO_TAKEN_60 `SPC7.tlu.trl1.take_rqr&`SPC7.tlu.trl1.trap[0]
17352
17353`define XIR_TAKEN_60 `SPC7.tlu.trl1.take_xir&`SPC7.tlu.trl1.trap[0]
17354
17355`define SOFTINT_RDWR_60 (`TOP.nas_top.c7.t4.asi_rdwr_softint|`TOP.nas_top.c7.t4.asi_wr_softint_delay)
17356
17357`define SOFTINT_REG_60 `SPC7.tlu.trl1.softint0
17358`define RD_SOFTINT_REG_60 `SPC7.tlu.trl1.rd_softint0
17359`define INT_LEVEL_TAKEN_60 `SPC7.tlu.trl1.take_iln&`SPC7.tlu.trl1.trap[0]
17360`define INT_LEVEL_NUM_60 `SPC7.tlu.trl1.int_level_n
17361`define PMU_TAKEN_60 `SPC7.tlu.trl1.take_pmu&`SPC7.tlu.trl1.trap[0]
17362
17363`define HINTP_RDWR_60 (`TOP.nas_top.c7.t4.asi_rdwr_hintp | `TOP.nas_top.c7.t4.asi_wr_hintp_delay)
17364`define HINTP_WR_60 (`SPC7.tlu.asi_wr_hintp[60])
17365`define HSTMATCH_60 `SPC7.tlu.trl1.hstick0_compare
17366
17367`define HINTP_REG_60 `SPC7.tlu.trl1.hintp0
17368`define HSTM_TAKEN_60 `SPC7.tlu.trl1.take_hst&`SPC7.tlu.trl1.trap[0]
17369
17370`define NAS_PIPE_FW2_60 |`TOP.nas_top.c7.t4.complete_fw2
17371
17372`define CWQ_TAKEN_60 `SPC7.tlu.trl1.take_cwq&`SPC7.tlu.trl1.trap[0]
17373`define SMA_TAKEN_60 `SPC7.tlu.trl1.take_sma&`SPC7.tlu.trl1.trap[0]
17374
17375`define POR_TAKEN_60 `SPC7.tlu.trl1.take_por&`SPC7.tlu.trl1.trap[0]
17376
17377/////////////////////////////// Probes //////////////////////////////////// }}}
17378
17379always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
17380
17381 // {{{ DETECT, PIPE & SEND
17382 take_disrupting_w <= (`INT_VEC_TAKEN_60 || `CPU_MONDO_TAKEN_60 ||
17383 `DEV_MONDO_TAKEN_60 || `RES_MONDO_TAKEN_60 ||
17384 `XIR_TAKEN_60 || `INT_LEVEL_TAKEN_60 ||
17385 `HSTM_TAKEN_60 || `CWQ_TAKEN_60 ||
17386 `SMA_TAKEN_60 || `PMU_TAKEN_60 || `POR_TAKEN_60);
17387 take_disrupting_fx4 <= take_disrupting_w;
17388 take_disrupting_fx5 <= take_disrupting_fx4;
17389 take_disrupting_fb <= take_disrupting_fx5;
17390 take_disrupting_fw <= take_disrupting_fb;
17391 take_disrupting_fw1 <= take_disrupting_fw;
17392 take_disrupting_fw2 <= take_disrupting_fw1;
17393
17394 case ({`INT_VEC_TAKEN_60, `CPU_MONDO_TAKEN_60,
17395 `DEV_MONDO_TAKEN_60, `RES_MONDO_TAKEN_60,
17396 `XIR_TAKEN_60, `INT_LEVEL_TAKEN_60,
17397 `HSTM_TAKEN_60, `CWQ_TAKEN_60, `SMA_TAKEN_60 ,
17398 `PMU_TAKEN_60, `POR_TAKEN_60})
17399 11'b10000000000: int_num_w <= 8'h60;
17400 11'b01000000000: int_num_w <= 8'h7c;
17401 11'b00100000000: int_num_w <= 8'h7d;
17402 11'b00010000000: int_num_w <= 8'h7e;
17403 11'b00001000000: int_num_w <= 8'h03;
17404 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_60;
17405 11'b00000010000: int_num_w <= 8'h5e;
17406 11'b00000001000: int_num_w <= 8'h3c;
17407 11'b00000000100: int_num_w <= 8'h3d;
17408 11'b00000000010: int_num_w <= 8'h4f;
17409 11'b00000000001: int_num_w <= 8'h01;
17410 endcase
17411
17412 int_num_fx4 <= int_num_w;
17413 int_num_fx5 <= int_num_fx4;
17414 int_num_fb <= int_num_fx5;
17415 int_num_fw <= int_num_fb;
17416 int_num_fw1 <= int_num_fw;
17417 int_num_fw2 <= int_num_fw1;
17418 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
17419 begin // {
17420 `PR_INFO ("pli_int", `INFO,
17421 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
17422 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17423 end // }
17424
17425 // }}}
17426
17427/////////////////////////// Vectored Interrupt /////////////////////////// {{{
17428
17429 // Vectored Interrupt Recv Register Detection
17430 // Indicate when register changes due to arriving interrupt, and not
17431 // due to read of incoming register or ASI write ..
17432
17433
17434 // If any read occurs, send value right away.
17435 // While a read/write is pending, do not update delta.
17436 // Send non read/wr delta during fw2 ..
17437
17438
17439 if (!(`INT_VEC_RDWR_60 | `INT_VEC_RECV_ASIWR_60)) begin // {
17440 if (~`INT_VEC_RECV_ASIWR_60 &
17441 (int_vec_recv_reg !== `INT_VEC_RECV_REG_60 ))
17442 int_vec_recv_reg_delta <= 1'b1;
17443 int_vec_recv_reg <= `INT_VEC_RECV_REG_60;
17444 end // }
17445 else if (`INT_VEC_RECV_ASIWR_60)
17446 int_vec_recv_reg <= `TOP.nas_top.c7.t4.asi_updated_int_rec;
17447
17448 if ((`NAS_PIPE_FW2_60 & int_vec_recv_reg_delta ) |
17449 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
17450 `INT_VEC_RECV_ASIWR_60 ) begin // {
17451 `PR_INFO ("pli_int", `INFO,
17452 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
17453 mycid,mytid, int_vec_recv_reg);
17454 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17455 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
17456 64'h0, int_vec_recv_reg);
17457 end // }
17458 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_60 &
17459 (int_vec_recv_reg !== `INT_VEC_RECV_REG_60 ))))
17460 int_vec_recv_reg_delta <= 1'b0;
17461 end //}
17462
17463 int_vec_reg_rdwr <= `INT_VEC_RDWR_60 | `INT_VEC_RECV_ASIWR_60;
17464 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_60 & ~ inc_vec_reg_rd;
17465
17466 if (`INT_VEC_RECV_ASIWR_60)
17467 inc_vec_reg_rd <= 1'b1;
17468 if (`NAS_PIPE_FW2_60)
17469 inc_vec_reg_rd <= 1'b0;
17470
17471
17472/////////////////////////// Vectored Interrupt /////////////////////////// }}}
17473
17474/////////////////////////// Asynchronous Resets ////////////////////////// {{{
17475
17476
17477/////////////////////////// Asynchronous Resets ////////////////////////// }}}
17478
17479/////////////////////////// Softint ///////////////////////////////////// {{{
17480
17481 // Softint Register hardware Update Detection
17482
17483 // Non software updates (TM/SM)
17484
17485 // If any read occurs, send value right away.
17486 // While a read/write is pending, do not update delta.
17487 // Send non read/wr delta during fw2 ..
17488
17489 // RTL keeps pic_ovf indication in rd_softint and not softint.
17490 // So for set/clear writes, we send softint before the write ..,
17491 // and for read/asyncs we send rd_softint ..
17492
17493
17494 if (~`SOFTINT_RDWR_60) begin // {
17495 if (softint !== `RD_SOFTINT_REG_60 )
17496 softint_delta <= 1'b1;
17497 softint <= `RD_SOFTINT_REG_60;
17498 end // }
17499
17500 if ((`NAS_PIPE_FW2_60 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
17501 ) begin // {
17502 `PR_INFO ("pli_int", `INFO,
17503 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
17504 mycid,mytid, {47'h0, softint});
17505 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17506 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
17507 {47'h0, softint});
17508 end // }
17509 if (!(~`SOFTINT_RDWR_60&(softint !== `RD_SOFTINT_REG_60)))
17510 softint_delta <= 1'b0;
17511 end //}
17512 else if (`SPC7.tlu.asi_wr_clear_softint[4] |
17513 `SPC7.tlu.asi_wr_set_softint[4] ) begin // {
17514 `PR_INFO ("pli_int", `INFO,
17515 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
17516 mycid,mytid, {47'h0, `RD_SOFTINT_REG_60});
17517 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17518 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
17519 {47'h0, `RD_SOFTINT_REG_60});
17520 end // }
17521 end //}
17522
17523
17524 softint_rdwr <= `SOFTINT_RDWR_60 ;
17525 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_60;
17526
17527
17528/////////////////////////// Softint ///////////////////////////////////// }}}
17529
17530/////////////////////////// Hintp ///////////////////////////////////// {{{
17531
17532 // Hintp Register hardware Update Detection
17533
17534 // Non software updates (HSP)
17535 // If HINTP is already read/written by SW, then don't send
17536 // any async updates to Nas. Reads/Writes pending sstep is detected
17537 // by snooping nas_pipe ..
17538
17539 hintp <= `HINTP_REG_60 ;
17540 if (hstmatch_late)
17541 hintp_delta <= 1'b1;
17542
17543 if ((~hintp_rdwr & `NAS_PIPE_FW2_60 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
17544 (hintp_rdwr_late & hintp_delta) ) begin // {
17545 `PR_INFO ("pli_int", `INFO,
17546 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
17547 mycid,mytid, {63'h0, hintp});
17548 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17549 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
17550 {63'h0, hintp});
17551 end // }
17552 if (~(hintp_rdwr_late & hintp_delta))
17553 hintp_delta <= 1'b0;
17554 end //}
17555
17556 hintp_rdwr <= `HINTP_RDWR_60;
17557 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_60;
17558 hstmatch_late <= `HSTMATCH_60;
17559
17560
17561/////////////////////////// Hintp ///////////////////////////////////// }}}
17562
17563end //}
17564`endif
17565endmodule
17566
17567// }}}
17568
17569module int_c7t5 ();
17570`ifndef GATESIM
17571
17572// common defines
17573`include "defines.vh"
17574`include "ccx.vri"
17575`include "cmp.vri"
17576
17577wire [2:0] mycid;
17578wire [2:0] mytid;
17579wire [5:0] mytnum;
17580integer junk;
17581
17582reg [63:0] int_vec_recv_reg;
17583reg int_vec_recv_reg_delta;
17584reg int_vec_reg_rdwr;
17585reg inc_vec_reg_rd;
17586reg int_vec_reg_rdwr_late;
17587reg [16:0] softint;
17588reg softint_rdwr;
17589reg softint_rdwr_late;
17590reg softint_delta;
17591reg hintp;
17592reg hintp_rdwr;
17593reg hintp_rdwr_late;
17594reg hintp_delta;
17595reg hstmatch_late;
17596reg ready;
17597reg [7:0] int_num_w;
17598reg [7:0] int_num_fx4;
17599reg [7:0] int_num_fx5;
17600reg [7:0] int_num_fb;
17601reg [7:0] int_num_fw;
17602reg [7:0] int_num_fw1;
17603reg [7:0] int_num_fw2;
17604reg take_disrupting_w;
17605reg take_disrupting_fx4;
17606reg take_disrupting_fx5;
17607reg take_disrupting_fb;
17608reg take_disrupting_fw;
17609reg take_disrupting_fw1;
17610reg take_disrupting_fw2;
17611
17612 assign mycid = 7;
17613 assign mytid = 5;
17614 assign mytnum = 7*8 + 5;
17615
17616initial begin // {
17617 ready = 0; // Wait for socket setup ..
17618 inc_vec_reg_rd <= 1'b0;
17619 int_vec_recv_reg_delta <= 1'b0;
17620 softint_delta <= 1'b0;
17621 hintp_delta <= 1'b0;
17622 int_vec_recv_reg = 64'b0;
17623 @(posedge `BENCH_SPC7_GCLK) ;
17624 @(posedge `BENCH_SPC7_GCLK) ;
17625 ready = `PARGS.int_sync_on;
17626end //}
17627
17628
17629/////////////////////////////// Probes //////////////////////////////////// {{{
17630
17631`define INT_VEC_RECV_REG_61 `SPC7.tlu.cth.int_rec5
17632`define INT_VEC_RECV_ASIWR_61 (`TOP.nas_top.c7.t5.asi_wr_int_rec_delay)
17633`define INT_VEC_RDWR_61 (`TOP.nas_top.c7.t5.asi_rdwr_int_rec)
17634`define INT_VEC_TAKEN_61 `SPC7.tlu.trl1.take_ivt&`SPC7.tlu.trl1.trap[1]
17635
17636`define CPU_MONDO_TAKEN_61 `SPC7.tlu.trl1.take_mqr&`SPC7.tlu.trl1.trap[1]
17637`define DEV_MONDO_TAKEN_61 `SPC7.tlu.trl1.take_dqr&`SPC7.tlu.trl1.trap[1]
17638`define RES_MONDO_TAKEN_61 `SPC7.tlu.trl1.take_rqr&`SPC7.tlu.trl1.trap[1]
17639
17640`define XIR_TAKEN_61 `SPC7.tlu.trl1.take_xir&`SPC7.tlu.trl1.trap[1]
17641
17642`define SOFTINT_RDWR_61 (`TOP.nas_top.c7.t5.asi_rdwr_softint|`TOP.nas_top.c7.t5.asi_wr_softint_delay)
17643
17644`define SOFTINT_REG_61 `SPC7.tlu.trl1.softint1
17645`define RD_SOFTINT_REG_61 `SPC7.tlu.trl1.rd_softint1
17646`define INT_LEVEL_TAKEN_61 `SPC7.tlu.trl1.take_iln&`SPC7.tlu.trl1.trap[1]
17647`define INT_LEVEL_NUM_61 `SPC7.tlu.trl1.int_level_n
17648`define PMU_TAKEN_61 `SPC7.tlu.trl1.take_pmu&`SPC7.tlu.trl1.trap[1]
17649
17650`define HINTP_RDWR_61 (`TOP.nas_top.c7.t5.asi_rdwr_hintp | `TOP.nas_top.c7.t5.asi_wr_hintp_delay)
17651`define HINTP_WR_61 (`SPC7.tlu.asi_wr_hintp[61])
17652`define HSTMATCH_61 `SPC7.tlu.trl1.hstick1_compare
17653
17654`define HINTP_REG_61 `SPC7.tlu.trl1.hintp1
17655`define HSTM_TAKEN_61 `SPC7.tlu.trl1.take_hst&`SPC7.tlu.trl1.trap[1]
17656
17657`define NAS_PIPE_FW2_61 |`TOP.nas_top.c7.t5.complete_fw2
17658
17659`define CWQ_TAKEN_61 `SPC7.tlu.trl1.take_cwq&`SPC7.tlu.trl1.trap[1]
17660`define SMA_TAKEN_61 `SPC7.tlu.trl1.take_sma&`SPC7.tlu.trl1.trap[1]
17661
17662`define POR_TAKEN_61 `SPC7.tlu.trl1.take_por&`SPC7.tlu.trl1.trap[1]
17663
17664/////////////////////////////// Probes //////////////////////////////////// }}}
17665
17666always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
17667
17668 // {{{ DETECT, PIPE & SEND
17669 take_disrupting_w <= (`INT_VEC_TAKEN_61 || `CPU_MONDO_TAKEN_61 ||
17670 `DEV_MONDO_TAKEN_61 || `RES_MONDO_TAKEN_61 ||
17671 `XIR_TAKEN_61 || `INT_LEVEL_TAKEN_61 ||
17672 `HSTM_TAKEN_61 || `CWQ_TAKEN_61 ||
17673 `SMA_TAKEN_61 || `PMU_TAKEN_61 || `POR_TAKEN_61);
17674 take_disrupting_fx4 <= take_disrupting_w;
17675 take_disrupting_fx5 <= take_disrupting_fx4;
17676 take_disrupting_fb <= take_disrupting_fx5;
17677 take_disrupting_fw <= take_disrupting_fb;
17678 take_disrupting_fw1 <= take_disrupting_fw;
17679 take_disrupting_fw2 <= take_disrupting_fw1;
17680
17681 case ({`INT_VEC_TAKEN_61, `CPU_MONDO_TAKEN_61,
17682 `DEV_MONDO_TAKEN_61, `RES_MONDO_TAKEN_61,
17683 `XIR_TAKEN_61, `INT_LEVEL_TAKEN_61,
17684 `HSTM_TAKEN_61, `CWQ_TAKEN_61, `SMA_TAKEN_61 ,
17685 `PMU_TAKEN_61, `POR_TAKEN_61})
17686 11'b10000000000: int_num_w <= 8'h60;
17687 11'b01000000000: int_num_w <= 8'h7c;
17688 11'b00100000000: int_num_w <= 8'h7d;
17689 11'b00010000000: int_num_w <= 8'h7e;
17690 11'b00001000000: int_num_w <= 8'h03;
17691 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_61;
17692 11'b00000010000: int_num_w <= 8'h5e;
17693 11'b00000001000: int_num_w <= 8'h3c;
17694 11'b00000000100: int_num_w <= 8'h3d;
17695 11'b00000000010: int_num_w <= 8'h4f;
17696 11'b00000000001: int_num_w <= 8'h01;
17697 endcase
17698
17699 int_num_fx4 <= int_num_w;
17700 int_num_fx5 <= int_num_fx4;
17701 int_num_fb <= int_num_fx5;
17702 int_num_fw <= int_num_fb;
17703 int_num_fw1 <= int_num_fw;
17704 int_num_fw2 <= int_num_fw1;
17705 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
17706 begin // {
17707 `PR_INFO ("pli_int", `INFO,
17708 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
17709 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17710 end // }
17711
17712 // }}}
17713
17714/////////////////////////// Vectored Interrupt /////////////////////////// {{{
17715
17716 // Vectored Interrupt Recv Register Detection
17717 // Indicate when register changes due to arriving interrupt, and not
17718 // due to read of incoming register or ASI write ..
17719
17720
17721 // If any read occurs, send value right away.
17722 // While a read/write is pending, do not update delta.
17723 // Send non read/wr delta during fw2 ..
17724
17725
17726 if (!(`INT_VEC_RDWR_61 | `INT_VEC_RECV_ASIWR_61)) begin // {
17727 if (~`INT_VEC_RECV_ASIWR_61 &
17728 (int_vec_recv_reg !== `INT_VEC_RECV_REG_61 ))
17729 int_vec_recv_reg_delta <= 1'b1;
17730 int_vec_recv_reg <= `INT_VEC_RECV_REG_61;
17731 end // }
17732 else if (`INT_VEC_RECV_ASIWR_61)
17733 int_vec_recv_reg <= `TOP.nas_top.c7.t5.asi_updated_int_rec;
17734
17735 if ((`NAS_PIPE_FW2_61 & int_vec_recv_reg_delta ) |
17736 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
17737 `INT_VEC_RECV_ASIWR_61 ) begin // {
17738 `PR_INFO ("pli_int", `INFO,
17739 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
17740 mycid,mytid, int_vec_recv_reg);
17741 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17742 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
17743 64'h0, int_vec_recv_reg);
17744 end // }
17745 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_61 &
17746 (int_vec_recv_reg !== `INT_VEC_RECV_REG_61 ))))
17747 int_vec_recv_reg_delta <= 1'b0;
17748 end //}
17749
17750 int_vec_reg_rdwr <= `INT_VEC_RDWR_61 | `INT_VEC_RECV_ASIWR_61;
17751 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_61 & ~ inc_vec_reg_rd;
17752
17753 if (`INT_VEC_RECV_ASIWR_61)
17754 inc_vec_reg_rd <= 1'b1;
17755 if (`NAS_PIPE_FW2_61)
17756 inc_vec_reg_rd <= 1'b0;
17757
17758
17759/////////////////////////// Vectored Interrupt /////////////////////////// }}}
17760
17761/////////////////////////// Asynchronous Resets ////////////////////////// {{{
17762
17763
17764/////////////////////////// Asynchronous Resets ////////////////////////// }}}
17765
17766/////////////////////////// Softint ///////////////////////////////////// {{{
17767
17768 // Softint Register hardware Update Detection
17769
17770 // Non software updates (TM/SM)
17771
17772 // If any read occurs, send value right away.
17773 // While a read/write is pending, do not update delta.
17774 // Send non read/wr delta during fw2 ..
17775
17776 // RTL keeps pic_ovf indication in rd_softint and not softint.
17777 // So for set/clear writes, we send softint before the write ..,
17778 // and for read/asyncs we send rd_softint ..
17779
17780
17781 if (~`SOFTINT_RDWR_61) begin // {
17782 if (softint !== `RD_SOFTINT_REG_61 )
17783 softint_delta <= 1'b1;
17784 softint <= `RD_SOFTINT_REG_61;
17785 end // }
17786
17787 if ((`NAS_PIPE_FW2_61 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
17788 ) begin // {
17789 `PR_INFO ("pli_int", `INFO,
17790 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
17791 mycid,mytid, {47'h0, softint});
17792 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17793 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
17794 {47'h0, softint});
17795 end // }
17796 if (!(~`SOFTINT_RDWR_61&(softint !== `RD_SOFTINT_REG_61)))
17797 softint_delta <= 1'b0;
17798 end //}
17799 else if (`SPC7.tlu.asi_wr_clear_softint[5] |
17800 `SPC7.tlu.asi_wr_set_softint[5] ) begin // {
17801 `PR_INFO ("pli_int", `INFO,
17802 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
17803 mycid,mytid, {47'h0, `RD_SOFTINT_REG_61});
17804 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17805 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
17806 {47'h0, `RD_SOFTINT_REG_61});
17807 end // }
17808 end //}
17809
17810
17811 softint_rdwr <= `SOFTINT_RDWR_61 ;
17812 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_61;
17813
17814
17815/////////////////////////// Softint ///////////////////////////////////// }}}
17816
17817/////////////////////////// Hintp ///////////////////////////////////// {{{
17818
17819 // Hintp Register hardware Update Detection
17820
17821 // Non software updates (HSP)
17822 // If HINTP is already read/written by SW, then don't send
17823 // any async updates to Nas. Reads/Writes pending sstep is detected
17824 // by snooping nas_pipe ..
17825
17826 hintp <= `HINTP_REG_61 ;
17827 if (hstmatch_late)
17828 hintp_delta <= 1'b1;
17829
17830 if ((~hintp_rdwr & `NAS_PIPE_FW2_61 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
17831 (hintp_rdwr_late & hintp_delta) ) begin // {
17832 `PR_INFO ("pli_int", `INFO,
17833 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
17834 mycid,mytid, {63'h0, hintp});
17835 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
17836 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
17837 {63'h0, hintp});
17838 end // }
17839 if (~(hintp_rdwr_late & hintp_delta))
17840 hintp_delta <= 1'b0;
17841 end //}
17842
17843 hintp_rdwr <= `HINTP_RDWR_61;
17844 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_61;
17845 hstmatch_late <= `HSTMATCH_61;
17846
17847
17848/////////////////////////// Hintp ///////////////////////////////////// }}}
17849
17850end //}
17851`endif
17852endmodule
17853
17854// }}}
17855
17856module int_c7t6 ();
17857`ifndef GATESIM
17858
17859// common defines
17860`include "defines.vh"
17861`include "ccx.vri"
17862`include "cmp.vri"
17863
17864wire [2:0] mycid;
17865wire [2:0] mytid;
17866wire [5:0] mytnum;
17867integer junk;
17868
17869reg [63:0] int_vec_recv_reg;
17870reg int_vec_recv_reg_delta;
17871reg int_vec_reg_rdwr;
17872reg inc_vec_reg_rd;
17873reg int_vec_reg_rdwr_late;
17874reg [16:0] softint;
17875reg softint_rdwr;
17876reg softint_rdwr_late;
17877reg softint_delta;
17878reg hintp;
17879reg hintp_rdwr;
17880reg hintp_rdwr_late;
17881reg hintp_delta;
17882reg hstmatch_late;
17883reg ready;
17884reg [7:0] int_num_w;
17885reg [7:0] int_num_fx4;
17886reg [7:0] int_num_fx5;
17887reg [7:0] int_num_fb;
17888reg [7:0] int_num_fw;
17889reg [7:0] int_num_fw1;
17890reg [7:0] int_num_fw2;
17891reg take_disrupting_w;
17892reg take_disrupting_fx4;
17893reg take_disrupting_fx5;
17894reg take_disrupting_fb;
17895reg take_disrupting_fw;
17896reg take_disrupting_fw1;
17897reg take_disrupting_fw2;
17898
17899 assign mycid = 7;
17900 assign mytid = 6;
17901 assign mytnum = 7*8 + 6;
17902
17903initial begin // {
17904 ready = 0; // Wait for socket setup ..
17905 inc_vec_reg_rd <= 1'b0;
17906 int_vec_recv_reg_delta <= 1'b0;
17907 softint_delta <= 1'b0;
17908 hintp_delta <= 1'b0;
17909 int_vec_recv_reg = 64'b0;
17910 @(posedge `BENCH_SPC7_GCLK) ;
17911 @(posedge `BENCH_SPC7_GCLK) ;
17912 ready = `PARGS.int_sync_on;
17913end //}
17914
17915
17916/////////////////////////////// Probes //////////////////////////////////// {{{
17917
17918`define INT_VEC_RECV_REG_62 `SPC7.tlu.cth.int_rec6
17919`define INT_VEC_RECV_ASIWR_62 (`TOP.nas_top.c7.t6.asi_wr_int_rec_delay)
17920`define INT_VEC_RDWR_62 (`TOP.nas_top.c7.t6.asi_rdwr_int_rec)
17921`define INT_VEC_TAKEN_62 `SPC7.tlu.trl1.take_ivt&`SPC7.tlu.trl1.trap[2]
17922
17923`define CPU_MONDO_TAKEN_62 `SPC7.tlu.trl1.take_mqr&`SPC7.tlu.trl1.trap[2]
17924`define DEV_MONDO_TAKEN_62 `SPC7.tlu.trl1.take_dqr&`SPC7.tlu.trl1.trap[2]
17925`define RES_MONDO_TAKEN_62 `SPC7.tlu.trl1.take_rqr&`SPC7.tlu.trl1.trap[2]
17926
17927`define XIR_TAKEN_62 `SPC7.tlu.trl1.take_xir&`SPC7.tlu.trl1.trap[2]
17928
17929`define SOFTINT_RDWR_62 (`TOP.nas_top.c7.t6.asi_rdwr_softint|`TOP.nas_top.c7.t6.asi_wr_softint_delay)
17930
17931`define SOFTINT_REG_62 `SPC7.tlu.trl1.softint2
17932`define RD_SOFTINT_REG_62 `SPC7.tlu.trl1.rd_softint2
17933`define INT_LEVEL_TAKEN_62 `SPC7.tlu.trl1.take_iln&`SPC7.tlu.trl1.trap[2]
17934`define INT_LEVEL_NUM_62 `SPC7.tlu.trl1.int_level_n
17935`define PMU_TAKEN_62 `SPC7.tlu.trl1.take_pmu&`SPC7.tlu.trl1.trap[2]
17936
17937`define HINTP_RDWR_62 (`TOP.nas_top.c7.t6.asi_rdwr_hintp | `TOP.nas_top.c7.t6.asi_wr_hintp_delay)
17938`define HINTP_WR_62 (`SPC7.tlu.asi_wr_hintp[62])
17939`define HSTMATCH_62 `SPC7.tlu.trl1.hstick2_compare
17940
17941`define HINTP_REG_62 `SPC7.tlu.trl1.hintp2
17942`define HSTM_TAKEN_62 `SPC7.tlu.trl1.take_hst&`SPC7.tlu.trl1.trap[2]
17943
17944`define NAS_PIPE_FW2_62 |`TOP.nas_top.c7.t6.complete_fw2
17945
17946`define CWQ_TAKEN_62 `SPC7.tlu.trl1.take_cwq&`SPC7.tlu.trl1.trap[2]
17947`define SMA_TAKEN_62 `SPC7.tlu.trl1.take_sma&`SPC7.tlu.trl1.trap[2]
17948
17949`define POR_TAKEN_62 `SPC7.tlu.trl1.take_por&`SPC7.tlu.trl1.trap[2]
17950
17951/////////////////////////////// Probes //////////////////////////////////// }}}
17952
17953always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
17954
17955 // {{{ DETECT, PIPE & SEND
17956 take_disrupting_w <= (`INT_VEC_TAKEN_62 || `CPU_MONDO_TAKEN_62 ||
17957 `DEV_MONDO_TAKEN_62 || `RES_MONDO_TAKEN_62 ||
17958 `XIR_TAKEN_62 || `INT_LEVEL_TAKEN_62 ||
17959 `HSTM_TAKEN_62 || `CWQ_TAKEN_62 ||
17960 `SMA_TAKEN_62 || `PMU_TAKEN_62 || `POR_TAKEN_62);
17961 take_disrupting_fx4 <= take_disrupting_w;
17962 take_disrupting_fx5 <= take_disrupting_fx4;
17963 take_disrupting_fb <= take_disrupting_fx5;
17964 take_disrupting_fw <= take_disrupting_fb;
17965 take_disrupting_fw1 <= take_disrupting_fw;
17966 take_disrupting_fw2 <= take_disrupting_fw1;
17967
17968 case ({`INT_VEC_TAKEN_62, `CPU_MONDO_TAKEN_62,
17969 `DEV_MONDO_TAKEN_62, `RES_MONDO_TAKEN_62,
17970 `XIR_TAKEN_62, `INT_LEVEL_TAKEN_62,
17971 `HSTM_TAKEN_62, `CWQ_TAKEN_62, `SMA_TAKEN_62 ,
17972 `PMU_TAKEN_62, `POR_TAKEN_62})
17973 11'b10000000000: int_num_w <= 8'h60;
17974 11'b01000000000: int_num_w <= 8'h7c;
17975 11'b00100000000: int_num_w <= 8'h7d;
17976 11'b00010000000: int_num_w <= 8'h7e;
17977 11'b00001000000: int_num_w <= 8'h03;
17978 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_62;
17979 11'b00000010000: int_num_w <= 8'h5e;
17980 11'b00000001000: int_num_w <= 8'h3c;
17981 11'b00000000100: int_num_w <= 8'h3d;
17982 11'b00000000010: int_num_w <= 8'h4f;
17983 11'b00000000001: int_num_w <= 8'h01;
17984 endcase
17985
17986 int_num_fx4 <= int_num_w;
17987 int_num_fx5 <= int_num_fx4;
17988 int_num_fb <= int_num_fx5;
17989 int_num_fw <= int_num_fb;
17990 int_num_fw1 <= int_num_fw;
17991 int_num_fw2 <= int_num_fw1;
17992 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
17993 begin // {
17994 `PR_INFO ("pli_int", `INFO,
17995 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
17996 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
17997 end // }
17998
17999 // }}}
18000
18001/////////////////////////// Vectored Interrupt /////////////////////////// {{{
18002
18003 // Vectored Interrupt Recv Register Detection
18004 // Indicate when register changes due to arriving interrupt, and not
18005 // due to read of incoming register or ASI write ..
18006
18007
18008 // If any read occurs, send value right away.
18009 // While a read/write is pending, do not update delta.
18010 // Send non read/wr delta during fw2 ..
18011
18012
18013 if (!(`INT_VEC_RDWR_62 | `INT_VEC_RECV_ASIWR_62)) begin // {
18014 if (~`INT_VEC_RECV_ASIWR_62 &
18015 (int_vec_recv_reg !== `INT_VEC_RECV_REG_62 ))
18016 int_vec_recv_reg_delta <= 1'b1;
18017 int_vec_recv_reg <= `INT_VEC_RECV_REG_62;
18018 end // }
18019 else if (`INT_VEC_RECV_ASIWR_62)
18020 int_vec_recv_reg <= `TOP.nas_top.c7.t6.asi_updated_int_rec;
18021
18022 if ((`NAS_PIPE_FW2_62 & int_vec_recv_reg_delta ) |
18023 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
18024 `INT_VEC_RECV_ASIWR_62 ) begin // {
18025 `PR_INFO ("pli_int", `INFO,
18026 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
18027 mycid,mytid, int_vec_recv_reg);
18028 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18029 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
18030 64'h0, int_vec_recv_reg);
18031 end // }
18032 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_62 &
18033 (int_vec_recv_reg !== `INT_VEC_RECV_REG_62 ))))
18034 int_vec_recv_reg_delta <= 1'b0;
18035 end //}
18036
18037 int_vec_reg_rdwr <= `INT_VEC_RDWR_62 | `INT_VEC_RECV_ASIWR_62;
18038 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_62 & ~ inc_vec_reg_rd;
18039
18040 if (`INT_VEC_RECV_ASIWR_62)
18041 inc_vec_reg_rd <= 1'b1;
18042 if (`NAS_PIPE_FW2_62)
18043 inc_vec_reg_rd <= 1'b0;
18044
18045
18046/////////////////////////// Vectored Interrupt /////////////////////////// }}}
18047
18048/////////////////////////// Asynchronous Resets ////////////////////////// {{{
18049
18050
18051/////////////////////////// Asynchronous Resets ////////////////////////// }}}
18052
18053/////////////////////////// Softint ///////////////////////////////////// {{{
18054
18055 // Softint Register hardware Update Detection
18056
18057 // Non software updates (TM/SM)
18058
18059 // If any read occurs, send value right away.
18060 // While a read/write is pending, do not update delta.
18061 // Send non read/wr delta during fw2 ..
18062
18063 // RTL keeps pic_ovf indication in rd_softint and not softint.
18064 // So for set/clear writes, we send softint before the write ..,
18065 // and for read/asyncs we send rd_softint ..
18066
18067
18068 if (~`SOFTINT_RDWR_62) begin // {
18069 if (softint !== `RD_SOFTINT_REG_62 )
18070 softint_delta <= 1'b1;
18071 softint <= `RD_SOFTINT_REG_62;
18072 end // }
18073
18074 if ((`NAS_PIPE_FW2_62 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
18075 ) begin // {
18076 `PR_INFO ("pli_int", `INFO,
18077 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
18078 mycid,mytid, {47'h0, softint});
18079 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18080 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
18081 {47'h0, softint});
18082 end // }
18083 if (!(~`SOFTINT_RDWR_62&(softint !== `RD_SOFTINT_REG_62)))
18084 softint_delta <= 1'b0;
18085 end //}
18086 else if (`SPC7.tlu.asi_wr_clear_softint[6] |
18087 `SPC7.tlu.asi_wr_set_softint[6] ) begin // {
18088 `PR_INFO ("pli_int", `INFO,
18089 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
18090 mycid,mytid, {47'h0, `RD_SOFTINT_REG_62});
18091 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18092 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
18093 {47'h0, `RD_SOFTINT_REG_62});
18094 end // }
18095 end //}
18096
18097
18098 softint_rdwr <= `SOFTINT_RDWR_62 ;
18099 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_62;
18100
18101
18102/////////////////////////// Softint ///////////////////////////////////// }}}
18103
18104/////////////////////////// Hintp ///////////////////////////////////// {{{
18105
18106 // Hintp Register hardware Update Detection
18107
18108 // Non software updates (HSP)
18109 // If HINTP is already read/written by SW, then don't send
18110 // any async updates to Nas. Reads/Writes pending sstep is detected
18111 // by snooping nas_pipe ..
18112
18113 hintp <= `HINTP_REG_62 ;
18114 if (hstmatch_late)
18115 hintp_delta <= 1'b1;
18116
18117 if ((~hintp_rdwr & `NAS_PIPE_FW2_62 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
18118 (hintp_rdwr_late & hintp_delta) ) begin // {
18119 `PR_INFO ("pli_int", `INFO,
18120 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
18121 mycid,mytid, {63'h0, hintp});
18122 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18123 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
18124 {63'h0, hintp});
18125 end // }
18126 if (~(hintp_rdwr_late & hintp_delta))
18127 hintp_delta <= 1'b0;
18128 end //}
18129
18130 hintp_rdwr <= `HINTP_RDWR_62;
18131 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_62;
18132 hstmatch_late <= `HSTMATCH_62;
18133
18134
18135/////////////////////////// Hintp ///////////////////////////////////// }}}
18136
18137end //}
18138`endif
18139endmodule
18140
18141// }}}
18142
18143module int_c7t7 ();
18144`ifndef GATESIM
18145
18146// common defines
18147`include "defines.vh"
18148`include "ccx.vri"
18149`include "cmp.vri"
18150
18151wire [2:0] mycid;
18152wire [2:0] mytid;
18153wire [5:0] mytnum;
18154integer junk;
18155
18156reg [63:0] int_vec_recv_reg;
18157reg int_vec_recv_reg_delta;
18158reg int_vec_reg_rdwr;
18159reg inc_vec_reg_rd;
18160reg int_vec_reg_rdwr_late;
18161reg [16:0] softint;
18162reg softint_rdwr;
18163reg softint_rdwr_late;
18164reg softint_delta;
18165reg hintp;
18166reg hintp_rdwr;
18167reg hintp_rdwr_late;
18168reg hintp_delta;
18169reg hstmatch_late;
18170reg ready;
18171reg [7:0] int_num_w;
18172reg [7:0] int_num_fx4;
18173reg [7:0] int_num_fx5;
18174reg [7:0] int_num_fb;
18175reg [7:0] int_num_fw;
18176reg [7:0] int_num_fw1;
18177reg [7:0] int_num_fw2;
18178reg take_disrupting_w;
18179reg take_disrupting_fx4;
18180reg take_disrupting_fx5;
18181reg take_disrupting_fb;
18182reg take_disrupting_fw;
18183reg take_disrupting_fw1;
18184reg take_disrupting_fw2;
18185
18186 assign mycid = 7;
18187 assign mytid = 7;
18188 assign mytnum = 7*8 + 7;
18189
18190initial begin // {
18191 ready = 0; // Wait for socket setup ..
18192 inc_vec_reg_rd <= 1'b0;
18193 int_vec_recv_reg_delta <= 1'b0;
18194 softint_delta <= 1'b0;
18195 hintp_delta <= 1'b0;
18196 int_vec_recv_reg = 64'b0;
18197 @(posedge `BENCH_SPC7_GCLK) ;
18198 @(posedge `BENCH_SPC7_GCLK) ;
18199 ready = `PARGS.int_sync_on;
18200end //}
18201
18202
18203/////////////////////////////// Probes //////////////////////////////////// {{{
18204
18205`define INT_VEC_RECV_REG_63 `SPC7.tlu.cth.int_rec7
18206`define INT_VEC_RECV_ASIWR_63 (`TOP.nas_top.c7.t7.asi_wr_int_rec_delay)
18207`define INT_VEC_RDWR_63 (`TOP.nas_top.c7.t7.asi_rdwr_int_rec)
18208`define INT_VEC_TAKEN_63 `SPC7.tlu.trl1.take_ivt&`SPC7.tlu.trl1.trap[3]
18209
18210`define CPU_MONDO_TAKEN_63 `SPC7.tlu.trl1.take_mqr&`SPC7.tlu.trl1.trap[3]
18211`define DEV_MONDO_TAKEN_63 `SPC7.tlu.trl1.take_dqr&`SPC7.tlu.trl1.trap[3]
18212`define RES_MONDO_TAKEN_63 `SPC7.tlu.trl1.take_rqr&`SPC7.tlu.trl1.trap[3]
18213
18214`define XIR_TAKEN_63 `SPC7.tlu.trl1.take_xir&`SPC7.tlu.trl1.trap[3]
18215
18216`define SOFTINT_RDWR_63 (`TOP.nas_top.c7.t7.asi_rdwr_softint|`TOP.nas_top.c7.t7.asi_wr_softint_delay)
18217
18218`define SOFTINT_REG_63 `SPC7.tlu.trl1.softint3
18219`define RD_SOFTINT_REG_63 `SPC7.tlu.trl1.rd_softint3
18220`define INT_LEVEL_TAKEN_63 `SPC7.tlu.trl1.take_iln&`SPC7.tlu.trl1.trap[3]
18221`define INT_LEVEL_NUM_63 `SPC7.tlu.trl1.int_level_n
18222`define PMU_TAKEN_63 `SPC7.tlu.trl1.take_pmu&`SPC7.tlu.trl1.trap[3]
18223
18224`define HINTP_RDWR_63 (`TOP.nas_top.c7.t7.asi_rdwr_hintp | `TOP.nas_top.c7.t7.asi_wr_hintp_delay)
18225`define HINTP_WR_63 (`SPC7.tlu.asi_wr_hintp[63])
18226`define HSTMATCH_63 `SPC7.tlu.trl1.hstick3_compare
18227
18228`define HINTP_REG_63 `SPC7.tlu.trl1.hintp3
18229`define HSTM_TAKEN_63 `SPC7.tlu.trl1.take_hst&`SPC7.tlu.trl1.trap[3]
18230
18231`define NAS_PIPE_FW2_63 |`TOP.nas_top.c7.t7.complete_fw2
18232
18233`define CWQ_TAKEN_63 `SPC7.tlu.trl1.take_cwq&`SPC7.tlu.trl1.trap[3]
18234`define SMA_TAKEN_63 `SPC7.tlu.trl1.take_sma&`SPC7.tlu.trl1.trap[3]
18235
18236`define POR_TAKEN_63 `SPC7.tlu.trl1.take_por&`SPC7.tlu.trl1.trap[3]
18237
18238/////////////////////////////// Probes //////////////////////////////////// }}}
18239
18240always @(negedge (`BENCH_SPC7_GCLK & ready)) begin // {
18241
18242 // {{{ DETECT, PIPE & SEND
18243 take_disrupting_w <= (`INT_VEC_TAKEN_63 || `CPU_MONDO_TAKEN_63 ||
18244 `DEV_MONDO_TAKEN_63 || `RES_MONDO_TAKEN_63 ||
18245 `XIR_TAKEN_63 || `INT_LEVEL_TAKEN_63 ||
18246 `HSTM_TAKEN_63 || `CWQ_TAKEN_63 ||
18247 `SMA_TAKEN_63 || `PMU_TAKEN_63 || `POR_TAKEN_63);
18248 take_disrupting_fx4 <= take_disrupting_w;
18249 take_disrupting_fx5 <= take_disrupting_fx4;
18250 take_disrupting_fb <= take_disrupting_fx5;
18251 take_disrupting_fw <= take_disrupting_fb;
18252 take_disrupting_fw1 <= take_disrupting_fw;
18253 take_disrupting_fw2 <= take_disrupting_fw1;
18254
18255 case ({`INT_VEC_TAKEN_63, `CPU_MONDO_TAKEN_63,
18256 `DEV_MONDO_TAKEN_63, `RES_MONDO_TAKEN_63,
18257 `XIR_TAKEN_63, `INT_LEVEL_TAKEN_63,
18258 `HSTM_TAKEN_63, `CWQ_TAKEN_63, `SMA_TAKEN_63 ,
18259 `PMU_TAKEN_63, `POR_TAKEN_63})
18260 11'b10000000000: int_num_w <= 8'h60;
18261 11'b01000000000: int_num_w <= 8'h7c;
18262 11'b00100000000: int_num_w <= 8'h7d;
18263 11'b00010000000: int_num_w <= 8'h7e;
18264 11'b00001000000: int_num_w <= 8'h03;
18265 11'b00000100000: int_num_w <= 8'h40 + `INT_LEVEL_NUM_63;
18266 11'b00000010000: int_num_w <= 8'h5e;
18267 11'b00000001000: int_num_w <= 8'h3c;
18268 11'b00000000100: int_num_w <= 8'h3d;
18269 11'b00000000010: int_num_w <= 8'h4f;
18270 11'b00000000001: int_num_w <= 8'h01;
18271 endcase
18272
18273 int_num_fx4 <= int_num_w;
18274 int_num_fx5 <= int_num_fx4;
18275 int_num_fb <= int_num_fx5;
18276 int_num_fw <= int_num_fb;
18277 int_num_fw1 <= int_num_fw;
18278 int_num_fw2 <= int_num_fw1;
18279 if (`PARGS.nas_check_on && `PARGS.int_sync_on && take_disrupting_fw2)
18280 begin // {
18281 `PR_INFO ("pli_int", `INFO,
18282 "C%0d T%0d PLI_INT_INTP 0x%h", mycid,mytid, int_num_fw2);
18283 junk = $sim_send(`PLI_INT_INTP, mytnum, int_num_fw2);
18284 end // }
18285
18286 // }}}
18287
18288/////////////////////////// Vectored Interrupt /////////////////////////// {{{
18289
18290 // Vectored Interrupt Recv Register Detection
18291 // Indicate when register changes due to arriving interrupt, and not
18292 // due to read of incoming register or ASI write ..
18293
18294
18295 // If any read occurs, send value right away.
18296 // While a read/write is pending, do not update delta.
18297 // Send non read/wr delta during fw2 ..
18298
18299
18300 if (!(`INT_VEC_RDWR_63 | `INT_VEC_RECV_ASIWR_63)) begin // {
18301 if (~`INT_VEC_RECV_ASIWR_63 &
18302 (int_vec_recv_reg !== `INT_VEC_RECV_REG_63 ))
18303 int_vec_recv_reg_delta <= 1'b1;
18304 int_vec_recv_reg <= `INT_VEC_RECV_REG_63;
18305 end // }
18306 else if (`INT_VEC_RECV_ASIWR_63)
18307 int_vec_recv_reg <= `TOP.nas_top.c7.t7.asi_updated_int_rec;
18308
18309 if ((`NAS_PIPE_FW2_63 & int_vec_recv_reg_delta ) |
18310 int_vec_reg_rdwr_late & ~inc_vec_reg_rd |
18311 `INT_VEC_RECV_ASIWR_63 ) begin // {
18312 `PR_INFO ("pli_int", `INFO,
18313 "C%0d T%0d PLI_ASI_WRITE ASI=0x72 VA=0x0 val=0x%h",
18314 mycid,mytid, int_vec_recv_reg);
18315 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18316 junk = $sim_send(`PLI_ASI_WRITE, mytnum ,8'h72,
18317 64'h0, int_vec_recv_reg);
18318 end // }
18319 if (!(~int_vec_reg_rdwr & (~`INT_VEC_RECV_ASIWR_63 &
18320 (int_vec_recv_reg !== `INT_VEC_RECV_REG_63 ))))
18321 int_vec_recv_reg_delta <= 1'b0;
18322 end //}
18323
18324 int_vec_reg_rdwr <= `INT_VEC_RDWR_63 | `INT_VEC_RECV_ASIWR_63;
18325 int_vec_reg_rdwr_late <= int_vec_reg_rdwr & ~`INT_VEC_RDWR_63 & ~ inc_vec_reg_rd;
18326
18327 if (`INT_VEC_RECV_ASIWR_63)
18328 inc_vec_reg_rd <= 1'b1;
18329 if (`NAS_PIPE_FW2_63)
18330 inc_vec_reg_rd <= 1'b0;
18331
18332
18333/////////////////////////// Vectored Interrupt /////////////////////////// }}}
18334
18335/////////////////////////// Asynchronous Resets ////////////////////////// {{{
18336
18337
18338/////////////////////////// Asynchronous Resets ////////////////////////// }}}
18339
18340/////////////////////////// Softint ///////////////////////////////////// {{{
18341
18342 // Softint Register hardware Update Detection
18343
18344 // Non software updates (TM/SM)
18345
18346 // If any read occurs, send value right away.
18347 // While a read/write is pending, do not update delta.
18348 // Send non read/wr delta during fw2 ..
18349
18350 // RTL keeps pic_ovf indication in rd_softint and not softint.
18351 // So for set/clear writes, we send softint before the write ..,
18352 // and for read/asyncs we send rd_softint ..
18353
18354
18355 if (~`SOFTINT_RDWR_63) begin // {
18356 if (softint !== `RD_SOFTINT_REG_63 )
18357 softint_delta <= 1'b1;
18358 softint <= `RD_SOFTINT_REG_63;
18359 end // }
18360
18361 if ((`NAS_PIPE_FW2_63 & !`TOP.nas_top.sstep_early[mytnum] & softint_delta ) | softint_rdwr_late
18362 ) begin // {
18363 `PR_INFO ("pli_int", `INFO,
18364 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
18365 mycid,mytid, {47'h0, softint});
18366 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18367 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
18368 {47'h0, softint});
18369 end // }
18370 if (!(~`SOFTINT_RDWR_63&(softint !== `RD_SOFTINT_REG_63)))
18371 softint_delta <= 1'b0;
18372 end //}
18373 else if (`SPC7.tlu.asi_wr_clear_softint[7] |
18374 `SPC7.tlu.asi_wr_set_softint[7] ) begin // {
18375 `PR_INFO ("pli_int", `INFO,
18376 "C%0d T%0d PLI_ASR_WRITE ASR=0x16 val=0x%h",
18377 mycid,mytid, {47'h0, `RD_SOFTINT_REG_63});
18378 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18379 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h16,
18380 {47'h0, `RD_SOFTINT_REG_63});
18381 end // }
18382 end //}
18383
18384
18385 softint_rdwr <= `SOFTINT_RDWR_63 ;
18386 softint_rdwr_late <= softint_rdwr & ~`SOFTINT_RDWR_63;
18387
18388
18389/////////////////////////// Softint ///////////////////////////////////// }}}
18390
18391/////////////////////////// Hintp ///////////////////////////////////// {{{
18392
18393 // Hintp Register hardware Update Detection
18394
18395 // Non software updates (HSP)
18396 // If HINTP is already read/written by SW, then don't send
18397 // any async updates to Nas. Reads/Writes pending sstep is detected
18398 // by snooping nas_pipe ..
18399
18400 hintp <= `HINTP_REG_63 ;
18401 if (hstmatch_late)
18402 hintp_delta <= 1'b1;
18403
18404 if ((~hintp_rdwr & `NAS_PIPE_FW2_63 & hintp_delta & !`TOP.nas_top.sstep_early[mytnum]) |
18405 (hintp_rdwr_late & hintp_delta) ) begin // {
18406 `PR_INFO ("pli_int", `INFO,
18407 "C%0d T%0d PLI_ASR_WRITE ASR=0x43 val=0x%h",
18408 mycid,mytid, {63'h0, hintp});
18409 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18410 junk = $sim_send(`PLI_ASR_WRITE, mytnum,8'h43,
18411 {63'h0, hintp});
18412 end // }
18413 if (~(hintp_rdwr_late & hintp_delta))
18414 hintp_delta <= 1'b0;
18415 end //}
18416
18417 hintp_rdwr <= `HINTP_RDWR_63;
18418 hintp_rdwr_late <= hintp_rdwr & ~`HINTP_RDWR_63;
18419 hstmatch_late <= `HSTMATCH_63;
18420
18421
18422/////////////////////////// Hintp ///////////////////////////////////// }}}
18423
18424end //}
18425`endif
18426endmodule
18427
18428`endif
18429
18430//----------------------------------------------------------
18431/////////////////////////// CMP //////////////////////////////////////// {{{
18432
18433module int_cmp ();
18434`ifndef GATESIM
18435 // CMP Register hardware Update & Read Detection
18436
18437`ifdef NCURTL
18438`define NCU_PCX_ADDR (`CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[103:64]&40'hff03ffffff)
18439`define NCU_PCX_VLD (`CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_vld&&`CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifc_ctl.pcx_ncu_data_rdy&(`CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[128:124]==0))
18440`define NCU_PCX_TID (`CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifd_ctl.pcx_ncu_data[122:117])
18441`define NCU_CPX_REQ (`CPU.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfd_ctl.ncu_cpx_req_cq)
18442`define NCU_CPX_CMP_RET (`CPU.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfd_ctl.ncu_cpx_data_ca[145:141]=='b11000)
18443`define NCU_CPX_DATA (`CPU.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfd_ctl.ncu_cpx_data_ca[63:0])
18444`define NCU_CPX_TID (`CPU.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfd_ctl.ncu_cpx_data_ca[136:134])
18445`define CMP_CORE_RUNNING_STATUS `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_core_running_status
18446`define CMP_CORE_RUNNING_RW `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.core_running
18447`define CMP_CORE_ENABLE_STATUS `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_core_enable_status
18448`define READ_CMP_CORE_RUNNING_STATUS (cmp_ld_pending[asi_read_tid] & cmp_ld_type[asi_read_tid] & ~cmp_ld_type2[asi_read_tid])
18449`define READ_CMP_CORE_ENABLE_STATUS (cmp_ld_pending[asi_read_tid] & ~cmp_ld_type[asi_read_tid])
18450`define READ_CMP_CORE_RUNNING_RW cmp_ld_type2[asi_read_tid]
18451`define DATA_CMP_CORE_ asi_read_data[63:0]
18452`define TID_CMP_CORE_ asi_read_tid
18453`define ASI_READ_EDGE asi_read_edge
18454`define NCUCLK `CPU.ncu.l2clk
18455`else
18456`define CMP_CORE_RUNNING_STATUS `TOP.cmp_core_running_status
18457`define CMP_CORE_ENABLE_STATUS `TOP.cmp_core_enable_status
18458`define CMP_CORE_RUNNING_RW `TOP.cmp_core_running_rw
18459`define READ_CMP_CORE_RUNNING_STATUS (`TOP.asi_read_addr[25:18]==`ASI_CMP_CORE & `TOP.asi_read_addr[17:00]==`ASI_CMP_CORE_RUNNING_STATUS)
18460`define READ_CMP_CORE_ENABLE_STATUS (`TOP.asi_read_addr[25:18]==`ASI_CMP_CORE & `TOP.asi_read_addr[17:00]==`ASI_CMP_CORE_ENABLED)
18461`define READ_CMP_CORE_RUNNING_RW (`TOP.asi_read_addr[25:18]==`ASI_CMP_CORE & `TOP.asi_read_addr[17:00]==`ASI_CMP_CORE_RUNNING_RW)
18462`define DATA_CMP_CORE_ (`TOP.asi_read_data[63:0])
18463`define TID_CMP_CORE_ (`TOP.asi_read_tid)
18464`define ASI_READ_EDGE (`TOP.asi_read_edge)
18465`define NCUCLK `SYSTEMCLOCK
18466`endif
18467`define ASI_WMR_VEC_MASK `CPU.ncu_wmr_vec_mask
18468`ifdef FC_BENCH
18469`define RESET_STATUS_REG `CPU.rst.rst_fsm_ctl.rset_stat_q
18470`else
18471`ifndef NCURTL
18472`define RESET_STATUS_REG `TOP.asi_reset_stat[11:0]
18473`else
18474// FOR CCM1NCU, reset_status_register is not implemented.
18475// Using dummy register for compilation ..
18476`define RESET_STATUS_REG 12'h4
18477`endif
18478`endif
18479
18480reg [63:0] core_running_status;
18481reg [63:0] core_running_rw;
18482reg [63:0] core_enable_status;
18483reg asi_read_edge_last;
18484reg asi_read_valid;
18485reg asi_wmr_vec_mask;
18486reg ready;
18487reg wmr;
18488integer junk;
18489reg wmr_sync;
18490reg [11:0] reset_status_reg;
18491
18492initial begin // {
18493 wmr_sync = 0;
18494 ready = 0;
18495 wmr = 1;
18496 asi_wmr_vec_mask = 1'b0;
18497 core_running_status = 64'b0;
18498 core_running_rw = 64'b0;
18499 core_enable_status = 64'b0;
18500 asi_read_valid = 1'b0;
18501 asi_read_edge_last = 1'b0;
18502 @(posedge `NCUCLK) ;
18503 @(posedge `NCUCLK) ;
18504 ready = `PARGS.int_sync_on;
18505 wmr_sync = 1;
18506 reset_status_reg = 0;
18507
18508
18509 // Send HVER to RS
18510 if (`PARGS.nas_check_on) begin // {
18511 `PR_INFO ("pli_int", `INFO,
18512 "C0 T0 PLI_ASR_WRITE ASR=0x46 val=0x%h", `SPC0.tlu.asi.hver_value);
18513 junk = $sim_send(`PLI_ASR_WRITE, 8'h0, 8'h46, `SPC0.tlu.asi.hver_value);
18514 end //}
18515end //}
18516
18517// NCU RTL {{{
18518`ifdef NCURTL
18519reg [8:0] ncu_cpx_req;
18520reg [63:0] cmp_ld_pending;
18521reg [63:0] cmp_ld_type; // 0 = enable_status, 1=running_status
18522reg [63:0] cmp_ld_type2; // 0 = x, 1=running_rw
18523reg [63:0] asi_read_data;
18524reg [5:0] asi_read_tid;
18525reg asi_read_edge;
18526
18527
18528initial begin // {
18529 ncu_cpx_req <= 0;
18530 cmp_ld_pending <= 0;
18531 cmp_ld_type <= 0;
18532 cmp_ld_type2 <= 0;
18533 asi_read_data <= 0;
18534 asi_read_tid <= 0;
18535 asi_read_edge <= 0;
18536end // }
18537
18538always @(posedge (`NCUCLK & ready)) begin // {
18539 if ((`NCU_PCX_VLD) && (`NCU_PCX_ADDR == 40'h9001040010 ||
18540 `NCU_PCX_ADDR == 40'h9001040058 ||
18541 `NCU_PCX_ADDR == 40'h9001040050)) begin // {
18542 cmp_ld_pending[`NCU_PCX_TID] = 1'b1;
18543 if (`NCU_PCX_ADDR == 40'h9001040010)
18544 cmp_ld_type[`NCU_PCX_TID] <= 1'b0;
18545 else
18546 cmp_ld_type[`NCU_PCX_TID] <= 1'b1;
18547
18548 if (`NCU_PCX_ADDR == 40'h9001040050)
18549 cmp_ld_type2[`NCU_PCX_TID] <= 1'b1;
18550 else
18551 cmp_ld_type2[`NCU_PCX_TID] <= 1'b0;
18552 end //}
18553 if (|ncu_cpx_req && `NCU_CPX_CMP_RET) begin // {
18554 case (ncu_cpx_req)
18555 8'h1: asi_read_tid <= {3'b000, `NCU_CPX_TID};
18556 8'h2: asi_read_tid <= {3'b001, `NCU_CPX_TID};
18557 8'h4: asi_read_tid <= {3'b010, `NCU_CPX_TID};
18558 8'h8: asi_read_tid <= {3'b011, `NCU_CPX_TID};
18559 8'h10: asi_read_tid <= {3'b100, `NCU_CPX_TID};
18560 8'h20: asi_read_tid <= {3'b101, `NCU_CPX_TID};
18561 8'h40: asi_read_tid <= {3'b110, `NCU_CPX_TID};
18562 8'h80: asi_read_tid <= {3'b111, `NCU_CPX_TID};
18563 endcase
18564 asi_read_data <= `NCU_CPX_DATA ;
18565 asi_read_edge <= ~asi_read_edge;
18566 end // }
18567 ncu_cpx_req <= `NCU_CPX_REQ ;
18568
18569 if (asi_read_edge_last !== `ASI_READ_EDGE) begin // {
18570 cmp_ld_pending[asi_read_tid] <= 0;
18571 end // }
18572end //}
18573`endif
18574//}}}
18575
18576always @(posedge (`NCUCLK & ready)) begin // {{{
18577
18578 if (wmr_sync && wmr && (wmr != `CPU.rst_wmr_protect)) begin /// {
18579 repeat (10) @(posedge `NCUCLK) ; // Wait for any nas_pipe to drain
18580 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18581 `PR_INFO ("pli_int", `INFO, "Reset: PLI_INT_INTP 0x0");
18582 junk = $sim_send(`PLI_INT_INTP, 8'h0, 8'h0);
18583 end // }
18584 end // }
18585 wmr <= `CPU.rst_wmr_protect ;
18586
18587 if (core_running_rw !== `CMP_CORE_RUNNING_RW ) begin //{
18588 `PR_INFO ("pli_int", `INFO,
18589 "PLI_CMP_WRITE va=0x50, val=0x%h", `CMP_CORE_RUNNING_RW);
18590 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18591 junk = $sim_send(`PLI_CMP_WRITE, 8'h50, `CMP_CORE_RUNNING_RW);
18592 end // }
18593 end //}
18594 core_running_rw <= `CMP_CORE_RUNNING_RW ;
18595
18596 if (core_running_status !== `CMP_CORE_RUNNING_STATUS ) begin //{
18597 `PR_INFO ("pli_int", `INFO,
18598 "PLI_CMP_WRITE va=0x58, val=0x%h", `CMP_CORE_RUNNING_STATUS);
18599 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18600 junk = $sim_send(`PLI_CMP_WRITE, 8'h58, `CMP_CORE_RUNNING_STATUS);
18601 end // }
18602 for (junk=0;junk<=63;junk=junk+1) begin // {
18603 if (core_running_status[junk]&~`CMP_CORE_RUNNING_STATUS [junk])
18604 `PR_NORMAL("nas_top", `NORMAL, "@%d T%d Parked", $time,junk);
18605 if (~core_running_status[junk]&`CMP_CORE_RUNNING_STATUS [junk])
18606 `PR_NORMAL("nas_top", `NORMAL, "@%d T%d Unparked", $time,junk);
18607 end // }
18608 end //}
18609
18610 core_running_status <= `CMP_CORE_RUNNING_STATUS ;
18611
18612 if (core_enable_status !== `CMP_CORE_ENABLE_STATUS ) begin //{
18613 `PR_INFO ("pli_int", `INFO,
18614 "PLI_CMP_WRITE va=0x10, val=0x%h", `CMP_CORE_ENABLE_STATUS);
18615 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18616 junk = $sim_send(`PLI_CMP_WRITE, 8'h10, `CMP_CORE_ENABLE_STATUS);
18617 end // }
18618 end //}
18619
18620 core_enable_status <= `CMP_CORE_ENABLE_STATUS ;
18621
18622 if (asi_read_edge_last !== `ASI_READ_EDGE) begin // {
18623 asi_read_valid <= 1'b1;
18624 if (`READ_CMP_CORE_RUNNING_STATUS) begin // {
18625 `PR_INFO ("pli_int", `INFO,
18626 "PLI_ASI_READ tid=%0d asi=0x41 va=0x58, val=0x%h",
18627 `TID_CMP_CORE_, `DATA_CMP_CORE_);
18628 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18629 junk = $sim_send(`PLI_ASI_READ, `TID_CMP_CORE_,
18630 8'h41, 64'h58, `DATA_CMP_CORE_);
18631 end // }
18632 end // }
18633 else if (`READ_CMP_CORE_ENABLE_STATUS) begin // {
18634 `PR_INFO ("pli_int", `INFO,
18635 "PLI_ASI_READ tid=%0d asi=0x41 va=0x10, val=0x%h",
18636 `TID_CMP_CORE_, `DATA_CMP_CORE_);
18637 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18638 junk = $sim_send(`PLI_ASI_READ, `TID_CMP_CORE_,
18639 8'h41, 64'h10, `DATA_CMP_CORE_);
18640 end // }
18641 end // }
18642 else if (`READ_CMP_CORE_RUNNING_RW) begin // {
18643 `PR_INFO ("pli_int", `INFO,
18644 "PLI_ASI_READ tid=%0d asi=0x41 va=0x50, val=0x%h",
18645 `TID_CMP_CORE_, `DATA_CMP_CORE_);
18646 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18647 junk = $sim_send(`PLI_ASI_READ, `TID_CMP_CORE_,
18648 8'h41, 64'h50, `DATA_CMP_CORE_);
18649 end // }
18650 end // }
18651 end // }
18652 else begin // {
18653 asi_read_valid <= 'b0;
18654 end // }
18655
18656 asi_read_edge_last <= `ASI_READ_EDGE ;
18657
18658/////////////////////////// ASI_WMR_VEC_MASK ///////////////////////////
18659
18660 if (asi_wmr_vec_mask !== `ASI_WMR_VEC_MASK ) begin //{
18661 `PR_INFO ("pli_int", `INFO,
18662 "PLI_ASI_WRITE ASI=0x45 VA=0x18 val=0x%h",
18663 {63'h0,`ASI_WMR_VEC_MASK});
18664 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18665 junk = $sim_send(`PLI_ASI_WRITE, 8'h0 , 8'h45,
18666 64'h18, {63'h0,`ASI_WMR_VEC_MASK});
18667 end // }
18668 end //}
18669 asi_wmr_vec_mask <= `ASI_WMR_VEC_MASK ;
18670
18671/////////////////////////// RESET_STATUS_REG ///////////////////////////
18672
18673 if (reset_status_reg != `RESET_STATUS_REG ) begin // {
18674 `PR_INFO ("pli_int", `INFO,
18675 "PLI_MEM_SLAM PA=0x8900000810 data=%h mask=ff, ts=%0d)",
18676 {52'h0,`RESET_STATUS_REG}, `TOP.core_cycle_cnt);
18677 if (`PARGS.nas_check_on && `PARGS.int_sync_on) begin // {
18678 junk = $sim_send(`PLI_MEM_SLAM, 40'h8900000810 , {52'h0,`RESET_STATUS_REG},
18679 8'hff, `TOP.core_cycle_cnt);
18680 end // }
18681 end // }
18682 reset_status_reg <= `RESET_STATUS_REG ;
18683
18684end //}}}
18685
18686`endif
18687endmodule
18688
18689/////////////////////////// CMP /////////////////////////////////////// }}}
18690
18691
18692//----------------------------------------------------------
Full OpenSPARC design & verification tarball including full HDL.