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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: defines.vh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef INC_COM_DEFINE | |
36 | ||
37 | `else | |
38 | ||
39 | `define INC_COM_DEFINE | |
40 | ||
41 | `ifdef AXIS | |
42 | `include "dispmonDefines.vh" | |
43 | `endif | |
44 | ||
45 | `define SYSTEMCLOCK tb_top.SystemClock | |
46 | ||
47 | `define TOP tb_top | |
48 | `define CPU tb_top.cpu | |
49 | `define PARGS tb_top.verif_args | |
50 | `define LDST_NCU tb_top.ldst_sync.ldst_ncu | |
51 | `define LDST_L2 tb_top.ldst_sync.ldst_l2 | |
52 | ||
53 | `define PC_MASK 64'h0000_00ff_ffff_ffff | |
54 | `define MASK_48 64'h0000_ffff_ffff_ffff | |
55 | `define BAD_PC 64'hffff_ffff_ffff_ffff | |
56 | ||
57 | ||
58 | `ifdef AXIS | |
59 | `define TIMEOUT 500000 | |
60 | `else | |
61 | `define TIMEOUT 300 | |
62 | `endif | |
63 | ||
64 | // Defines number of bits in scan_in & scan_out pins (spc.sv) | |
65 | `define SCAN_WIDTH 2 | |
66 | ||
67 | `define TS_WIDTH 32 | |
68 | ||
69 | //---------------------------------------------------------- | |
70 | // Defines for NAS PLI commands | |
71 | ||
72 | // basic PLI commands, 8'h00 - 8'h0f | |
73 | `define PLI_QUIT 8'h01 | |
74 | `define PLI_SSTEP 8'h02 | |
75 | `define PLI_READ_TH_REG 8'h03 | |
76 | `define PLI_READ_TH_CTL_REG 8'h04 | |
77 | `define PLI_READ_TH_FP_REG_I 8'h05 | |
78 | `define PLI_READ_TH_FP_REG_X 8'h06 | |
79 | `define PLI_RTL_DATA 8'h07 | |
80 | `define PLI_RTL_CYCLE 8'h08 | |
81 | `define PLI_WRITE_TH_XCC_REG 8'h09 | |
82 | `define PLI_WRITE_TH_REG_HI 8'h0a | |
83 | `define PLI_WRITE_TH_REG 8'h0b | |
84 | `define PLI_WRITE_TH_CTL_REG 8'h0c | |
85 | `define PLI_WRITE_TH_FP_REG_I 8'h0d | |
86 | `define PLI_WRITE_TH_FP_REG_X 8'h0e | |
87 | `define PLI_FORCE_TRAP_TYPE 8'h0f | |
88 | ||
89 | // TLB & HWTW commands, 8'h10 - 8'h1f | |
90 | `define PLI_RESET_TLB_ENTRY 8'h10 | |
91 | `define PLI_IHWTW 8'h11 | |
92 | `define PLI_DHWTW 8'h12 | |
93 | `define PLI_ITLBREAD 8'h13 | |
94 | `define PLI_DTLBREAD 8'h14 | |
95 | `define PLI_ITLBWRITE 8'h15 | |
96 | `define PLI_DTLBWRITE 8'h16 | |
97 | `define PLI_TLBLOOKUP 8'h17 | |
98 | `define PLI_DTLBREAD_POP 8'h18 | |
99 | ||
100 | // memory model commands, 8'h20 - 8'h3f | |
101 | `define PLI_MEM_ST_ISSUE 8'h20 | |
102 | `define PLI_MEM_ST_L2_COMMIT 8'h21 | |
103 | `define PLI_MEM_ST_INV 8'h22 | |
104 | `define PLI_MEM_ST_UPDATE 8'h23 | |
105 | `define PLI_MEM_ST_ACK 8'h24 | |
106 | `define PLI_MEM_LD_ISSUE 8'h25 | |
107 | `define PLI_MEM_LD_DATA 8'h26 | |
108 | `define PLI_MEM_LD_FILL 8'h27 | |
109 | `define PLI_MEM_EVICT 8'h28 | |
110 | `define PLI_MEM_EVICT_INV 8'h29 | |
111 | `define PLI_MEM_SLAM 8'h30 | |
112 | `define PLI_MEM_LD_POP 8'h31 | |
113 | `define PLI_MEM_ST_POP 8'h32 | |
114 | `define PLI_MEM_CHECK 8'h33 | |
115 | `define PLI_MEM_DMA_ST 8'h34 | |
116 | ||
117 | // INT Sync commands, 8'h40 - 8'h4f | |
118 | `define PLI_INT_INTP 8'h40 | |
119 | `define PLI_ASR_WRITE 8'h41 | |
120 | `define PLI_ASI_WRITE 8'h42 | |
121 | `define PLI_ASI_READ 8'h43 | |
122 | `define PLI_CMP_WRITE 8'h44 | |
123 | `define PLI_ASR_READ 8'h45 | |
124 | `define PLI_CSR_WRITE 8'h46 | |
125 | `define PLI_CSR_READ 8'h47 | |
126 | ||
127 | /* %1=pa(8),%2=value(8),%3=littleEndian(1),%4=size(1) */ | |
128 | `define PLI_PIO_READ 8'h49 | |
129 | ||
130 | // memory model commands, 8'h70 - 8'h7f | |
131 | `define PLI_MEM_IFETCH 8'h70 | |
132 | `define PLI_MEM_IFETCH_FILL 8'h71 | |
133 | `define PLI_MEM_IFETCH_POP_TOP 8'h72 | |
134 | `define PLI_MEM_IFETCH_POP_NEW 8'h73 | |
135 | `define PLI_MEM_IFETCH_POP_ONE 8'h74 | |
136 | ||
137 | // constants used by memory model commands | |
138 | // instr type | |
139 | `define ITYPE_NO 0 | |
140 | `define ITYPE_LOAD 1 | |
141 | `define ITYPE_BLOCK_LOAD 2 | |
142 | `define ITYPE_DOUBLE_LOAD 3 | |
143 | `define ITYPE_QUAD_LOAD 4 | |
144 | `define ITYPE_PREFETCH 5 | |
145 | `define ITYPE_STORE 6 | |
146 | `define ITYPE_BLOCK_STORE 7 | |
147 | `define ITYPE_ATOMIC 8 | |
148 | `define ITYPE_BLK_INIT_ST 9 | |
149 | ||
150 | // load data source | |
151 | `define DSRC_NO 0 | |
152 | `define DSRC_STB 1 | |
153 | `define DSRC_L1 2 | |
154 | `define DSRC_L2_MEMORY 3 | |
155 | ||
156 | //---------------------------------------------------------- | |
157 | // POR Values for Control Registers | |
158 | `define POR_PC 48'hfffff0000020 | |
159 | `define POR_GL 3'h3 | |
160 | ||
161 | //---------------------------------------------------------- | |
162 | // CMP Registers | |
163 | `define ASI_CMP_CORE 8'h41 | |
164 | `define ASI_CMP_CORE_AVAIL 18'h000 | |
165 | `define ASI_CMP_CORE_ENABLED 18'h010 | |
166 | `define ASI_CMP_CORE_ENABLE_STATUS 18'h010 | |
167 | `define ASI_CMP_CORE_ENABLE 18'h020 | |
168 | `define ASI_CMP_XIR_STEERING 18'h030 | |
169 | `define ASI_CMP_ERROR_STEERING 18'h040 | |
170 | `define ASI_CMP_CORE_RUNNING_RW 18'h050 | |
171 | `define ASI_CMP_CORE_RUNNING_STATUS 18'h058 | |
172 | `define ASI_CMP_CORE_RUNNING_W1S 18'h060 | |
173 | `define ASI_CMP_CORE_RUNNING_W1C 18'h068 | |
174 | ||
175 | // SIM_STATUS bit positions | |
176 | `define ASM_PASS 0 | |
177 | `define ASM_ERR 1 | |
178 | ||
179 | // Defines for TRAP address extraction | |
180 | `define MAX_TRAP_ADDRS 64 | |
181 | `define TRAP_ADDR_WIDTH 40 | |
182 | `define TRAP_ADDR_CHARS `TRAP_ADDR_WIDTH/4 | |
183 | ||
184 | ||
185 | `endif | |
186 | //---------------------------------------------------------- | |
187 | // END OF FILE | |
188 | //---------------------------------------------------------- |