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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: errorCountTasks.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `include "dispmonDefines.vh" | |
36 | // Assumes `TOP is defined!!! | |
37 | ||
38 | reg quiet; | |
39 | reg debug; | |
40 | reg info; | |
41 | reg [31:0] error_count; | |
42 | reg [31:0] warning_count; | |
43 | reg [31:0] maxerror; | |
44 | reg [31:0] maxwarning; | |
45 | reg [31:0] wait_cycle_to_kill; | |
46 | reg no_verilog_finish; | |
47 | integer start_debug; | |
48 | integer start_info; | |
49 | reg [512*8:0] arg_str; | |
50 | reg [31:0] bad_end_called; | |
51 | ||
52 | // Needed for optional dissabling of dispmon at time zero. | |
53 | // Needed by certain benches that have X's at time zero and time one. | |
54 | // If you don't need, ignore it. It can be X by default. | |
55 | // This has to go in the bench top. | |
56 | reg dispmon_disable; | |
57 | ||
58 | ||
59 | initial begin | |
60 | quiet = 0; | |
61 | debug = 0; | |
62 | info = 0; | |
63 | error_count = 0; | |
64 | warning_count = 0; | |
65 | maxerror = 1; | |
66 | maxwarning = 5; | |
67 | wait_cycle_to_kill = 5; | |
68 | no_verilog_finish = 0; | |
69 | start_debug = 0; | |
70 | start_info = 0; | |
71 | bad_end_called = 0; | |
72 | ||
73 | // #0; | |
74 | ||
75 | // Wait Cycles to End .. | |
76 | if ($value$plusargs("wait_cycle_to_kill=%d", wait_cycle_to_kill)) begin // { | |
77 | `PR_ALWAYS("arg", `ALWAYS, "Wait Cycles before End set to: %0d\n", | |
78 | wait_cycle_to_kill); | |
79 | end // } | |
80 | ||
81 | // max errors and warns | |
82 | if ($value$plusargs("maxerror=%d", maxerror)) begin // { | |
83 | `PR_ALWAYS("arg", `ALWAYS, "maxerror set to: %0d\n", | |
84 | maxerror); | |
85 | end // } | |
86 | ||
87 | if ($value$plusargs("maxwarning=%d", maxwarning)) begin // { | |
88 | `PR_ALWAYS("arg", `ALWAYS, "maxwarning set to: %0d\n", | |
89 | maxwarning); | |
90 | end // } | |
91 | ||
92 | if ($test$plusargs("debug_all") || $test$plusargs("debug")) begin // { | |
93 | debug = 1; | |
94 | info = 1; | |
95 | quiet = 0; | |
96 | end // } | |
97 | ||
98 | if ($test$plusargs("info_all") || $test$plusargs("info")) begin //{ | |
99 | info = 1; | |
100 | quiet = 0; | |
101 | end //} | |
102 | ||
103 | if ($test$plusargs("quiet") && !$test$plusargs("noquiet")) begin //{ | |
104 | debug = 0; | |
105 | info = 0; | |
106 | quiet = 1; | |
107 | end //} | |
108 | ||
109 | // User sets this when Vera wants to do a delayed exit | |
110 | // after asm code has finished. | |
111 | if ($test$plusargs("no_verilog_finish") || $test$plusargs("noVerilogFinish")) begin // { | |
112 | no_verilog_finish = 1; | |
113 | end // } | |
114 | ||
115 | end | |
116 | ||
117 | ||
118 | initial begin// { | |
119 | `ifdef PALLADIUM | |
120 | `elsif AXIS_TL | |
121 | `else | |
122 | #5 | |
123 | `endif | |
124 | if ($test$plusargs("show_delta")) begin // { | |
125 | if (quiet) `PR_ALWAYS ("arg", `ALWAYS, "Show Delta Enabled, turning off quiet."); | |
126 | quiet = 0; | |
127 | end // } | |
128 | end | |
129 | ||
130 | `ifdef PALLADIUM | |
131 | `elsif AXIS_TL | |
132 | `else | |
133 | //---------------------------------------------------------- | |
134 | // Debug Start | |
135 | initial begin// { | |
136 | if ($value$plusargs ("start_debug=%d", start_debug)) begin // { | |
137 | while (start_debug > $time) begin #100 ; end // Wait for start_debug | |
138 | `PR_NORMAL("arg", `NORMAL, "Start debug at %d time units", $time) ; | |
139 | debug = 1; info = 1; quiet = 0; | |
140 | if ($test$plusargs("debug_all")) begin // { | |
141 | $ch_dispmon("all", `DEBUG, 1); | |
142 | end //} | |
143 | // need this? | |
144 | if ($test$plusargs ("mon+")) begin // { | |
145 | if ($value$plusargs ("mon+%s", arg_str)) begin // { | |
146 | $parse_ch_dispmon(arg_str); | |
147 | end //} | |
148 | end //} | |
149 | end //} | |
150 | end //} | |
151 | ||
152 | // Info Start | |
153 | initial begin// { | |
154 | if ($value$plusargs ("start_info=%d", start_info)) begin // { | |
155 | while (start_info > $time) begin #100 ; end // Wait for start_info | |
156 | `PR_NORMAL("arg", `NORMAL, "Start info at %d time units", $time) ; | |
157 | info = 1; quiet = 0; | |
158 | if ($test$plusargs("info_all")) begin // { | |
159 | $ch_dispmon("all", `INFO, 1); | |
160 | end //} | |
161 | // need this? | |
162 | if ($test$plusargs ("mon+")) begin // { | |
163 | if ($value$plusargs ("mon+%s", arg_str)) begin // { | |
164 | $parse_ch_dispmon(arg_str); | |
165 | end //} | |
166 | end //} | |
167 | end //} | |
168 | end //} | |
169 | `endif //PALLADIUM | |
170 | ||
171 | ||
172 | // normal case is to define BAD_END as bad_end. | |
173 | `ifdef BAD_END | |
174 | always @(error_count) if (error_count >= maxerror && !bad_end_called) `BAD_END; | |
175 | always @(warning_count) if (warning_count >= maxwarning && !bad_end_called) `BAD_END; | |
176 | `endif | |
177 | ||
178 | // see dispmonDefines.vh to see why we have these. | |
179 | // they never return zero which is essential | |
180 | function [31:0] incErr; | |
181 | input [31:0] in; | |
182 | ||
183 | begin | |
184 | if ((!(`TOP.dispmon_disable === 1'b1)) || in == 9999) begin | |
185 | error_count = error_count + in; | |
186 | incErr = error_count; | |
187 | end | |
188 | else begin | |
189 | incErr = 0; | |
190 | `ifndef AXIS_TL | |
191 | `PR_ALWAYS ("top", `ALWAYS, "\n\nDispmon * ERRO R * message was just surpressed by dispmon_disable!!!\n"); | |
192 | `PR_ALWAYS ("top", `ALWAYS, "dispmon_disable is going away! Must handle message suppression at the source!\n\n\n"); | |
193 | `endif | |
194 | end | |
195 | end | |
196 | endfunction | |
197 | ||
198 | ||
199 | function [31:0] incWarn; | |
200 | input [31:0] in; | |
201 | begin | |
202 | if ((!(`TOP.dispmon_disable === 1'b1)) || in == 9999) begin | |
203 | warning_count = warning_count + in; | |
204 | incWarn = warning_count; | |
205 | end | |
206 | else begin | |
207 | incWarn = 0; | |
208 | `PR_ALWAYS ("top", `ALWAYS, "\n\nDispmon * WARN I N G * message was just surpressed by dispmon_disable!!!\n"); | |
209 | `PR_ALWAYS ("top", `ALWAYS, "dispmon_disable is going away! Must handle message suppression at the source!\n\n\n"); | |
210 | end | |
211 | end | |
212 | endfunction | |
213 | ||
214 | task set_no_verilog_finish; | |
215 | begin | |
216 | no_verilog_finish = 1; // used in misc_tasks.v | |
217 | `PR_ALWAYS ("top", `ALWAYS, "Setting no_verilog_finish, simulation will continue after asm completes!"); | |
218 | end | |
219 | endtask | |
220 |