Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / esrserdes_l0mon.v

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// OpenSPARC T2 Processor File: esrserdes_l0mon.v
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`timescale 1ps/1ps

module esrserdes_l0mon ();

reg enabled;
reg serdes_mon;
reg mac0_l0_d;
reg mac1_l0_d;
initial
begin
  enabled = 1'b1;
  serdes_mon = 1'b1;
  if ($test$plusargs("fsrserdes_l0mon_disable")) begin
    serdes_mon = 1'b0;
    enabled = 1'b0;
  end
end

wire flush_reset_complete = `TOP.flush_reset_complete;

always @ (flush_reset_complete)
begin
  if (flush_reset_complete == 1'b0)
    enabled = 1'b0;

  if ((flush_reset_complete == 1'b1) && serdes_mon)
    enabled = 1'b1;
end
//--------------------------------------------------------------------------------------
wire mac0_l0link = `CPU.xaui_link_led_0;
wire mac1_l0link = `CPU.xaui_link_led_1;

wire mac0_l0_ltoh = mac0_l0link & ~mac0_l0_d;  
wire mac0_l0_htol = ~mac0_l0link & mac0_l0_d;

wire mac1_l0_ltoh = mac1_l0link & ~mac1_l0_d; 
wire mac1_l0_htol = ~mac1_l0link & mac1_l0_d;

always @(posedge (`CPU.mac.niu_clk & enabled))
begin
   mac0_l0_d <= mac0_l0link;
   mac1_l0_d <= mac1_l0link;

   if (mac0_l0_ltoh) 
      `PR_NORMAL("mac0_l0mon", `NORMAL, "MAC0 L0 LINK is up" );
   if (mac1_l0_ltoh) 
      `PR_NORMAL("mac1_l0mon", `NORMAL, "MAC1 L0 LINK is up" );

   if (mac0_l0_htol) 
      `PR_INFO("mac0_l0mon", `INFO, "MAC0 L0 LINK HAS LOST SYNC");
   if (mac1_l0_htol) 
      `PR_INFO("mac1_l0mon", `INFO, "MAC1 L0 LINK HAS LOST SYNC");
end

//if (`TOP.info===1'b1) $dispmon("NCU_MON", `INFO," NIU->NCU::	 TYPE %0h; THR_ID %0h; PA = %0h; DATA = %0h;",	i2c_pkt[3:0], i2c_pkt[9:4], i2c_pkt[54:15], i2c_pkt[127:64] );
//`CPU.peu.l2t_etp_link

endmodule