Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / fsrserdes_l0mon.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fsrserdes_l0mon.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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35`timescale 1ps/1ps
36
37module fsrserdes_l0mon ();
38
39reg enabled;
40reg serdes_mon;
41reg mcu0_l0_d;
42reg mcu1_l0_d;
43reg mcu2_l0_d;
44reg mcu3_l0_d;
45initial
46begin
47 enabled = 1'b1;
48 serdes_mon = 1'b1;
49 if ($test$plusargs("fsrserdes_l0mon_disable")) begin
50 serdes_mon = 1'b0;
51 enabled = 1'b0;
52 end
53end
54
55wire flush_reset_complete = `TOP.flush_reset_complete;
56
57always @ (flush_reset_complete)
58begin
59 if (flush_reset_complete == 1'b0)
60 enabled = 1'b0;
61
62 if ((flush_reset_complete == 1'b1) && serdes_mon)
63 enabled = 1'b1;
64end
65//--------------------------------------------------------------------------------------
66wire mcu0_l0link = (`CPU.mcu0.fbdic.fbdic_fbd_state[2:0] == 3'h6);
67wire mcu1_l0link = (`CPU.mcu1.fbdic.fbdic_fbd_state[2:0] == 3'h6);
68wire mcu2_l0link = (`CPU.mcu2.fbdic.fbdic_fbd_state[2:0] == 3'h6);
69wire mcu3_l0link = (`CPU.mcu3.fbdic.fbdic_fbd_state[2:0] == 3'h6);
70
71wire mcu0_l0_ltoh = mcu0_l0link & ~mcu0_l0_d;
72wire mcu0_l0_htol = ~mcu0_l0link & mcu0_l0_d;
73
74wire mcu1_l0_ltoh = mcu1_l0link & ~mcu1_l0_d;
75wire mcu1_l0_htol = ~mcu1_l0link & mcu1_l0_d;
76
77wire mcu2_l0_ltoh = mcu2_l0link & ~mcu2_l0_d;
78wire mcu2_l0_htol = ~mcu2_l0link & mcu2_l0_d;
79
80wire mcu3_l0_ltoh = mcu3_l0link & ~mcu3_l0_d;
81wire mcu3_l0_htol = ~mcu3_l0link & mcu3_l0_d;
82
83always @(posedge (`CPU.mcu0.fbdic.l1clk & enabled))
84begin
85 mcu0_l0_d <= mcu0_l0link;
86 mcu1_l0_d <= mcu1_l0link;
87 mcu2_l0_d <= mcu2_l0link;
88 mcu3_l0_d <= mcu3_l0link;
89
90 if (mcu0_l0_ltoh)
91 `PR_NORMAL("mcu0_l0mon", `NORMAL, "MCU0 L0 LINK is up" );
92 if (mcu1_l0_ltoh)
93 `PR_NORMAL("mcu1_l0mon", `NORMAL, "MCU1 L0 LINK is up" );
94 if (mcu2_l0_ltoh)
95 `PR_NORMAL("mcu2_l0mon", `NORMAL, "MCU2 L0 LINK is up" );
96 if (mcu3_l0_ltoh)
97 `PR_NORMAL("mcu3_l0mon", `NORMAL, "MCU3 L0 LINK is up" );
98
99 if (mcu0_l0_htol)
100 `PR_INFO("mcu0_l0mon", `INFO, "MCU0 L0 LINK HAS LOST SYNC");
101 if (mcu1_l0_htol)
102 `PR_INFO("mcu1_l0mon", `INFO, "MCU1 L0 LINK HAS LOST SYNC");
103 if (mcu2_l0_htol)
104 `PR_INFO("mcu2_l0mon", `INFO, "MCU2 L0 LINK HAS LOST SYNC");
105 if (mcu3_l0_htol)
106 `PR_INFO("mcu3_l0mon", `INFO, "MCU3 L0 LINK HAS LOST SYNC");
107end
108
109//if (`TOP.info===1'b1) $dispmon("NCU_MON", `INFO," NIU->NCU:: TYPE %0h; THR_ID %0h; PA = %0h; DATA = %0h;", i2c_pkt[3:0], i2c_pkt[9:4], i2c_pkt[54:15], i2c_pkt[127:64] );
110//`CPU.peu.l2t_etp_link
111
112endmodule