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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fsrserdes_l0mon.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1ps/1ps | |
36 | ||
37 | module fsrserdes_l0mon (); | |
38 | ||
39 | reg enabled; | |
40 | reg serdes_mon; | |
41 | reg mcu0_l0_d; | |
42 | reg mcu1_l0_d; | |
43 | reg mcu2_l0_d; | |
44 | reg mcu3_l0_d; | |
45 | initial | |
46 | begin | |
47 | enabled = 1'b1; | |
48 | serdes_mon = 1'b1; | |
49 | if ($test$plusargs("fsrserdes_l0mon_disable")) begin | |
50 | serdes_mon = 1'b0; | |
51 | enabled = 1'b0; | |
52 | end | |
53 | end | |
54 | ||
55 | wire flush_reset_complete = `TOP.flush_reset_complete; | |
56 | ||
57 | always @ (flush_reset_complete) | |
58 | begin | |
59 | if (flush_reset_complete == 1'b0) | |
60 | enabled = 1'b0; | |
61 | ||
62 | if ((flush_reset_complete == 1'b1) && serdes_mon) | |
63 | enabled = 1'b1; | |
64 | end | |
65 | //-------------------------------------------------------------------------------------- | |
66 | wire mcu0_l0link = (`CPU.mcu0.fbdic.fbdic_fbd_state[2:0] == 3'h6); | |
67 | wire mcu1_l0link = (`CPU.mcu1.fbdic.fbdic_fbd_state[2:0] == 3'h6); | |
68 | wire mcu2_l0link = (`CPU.mcu2.fbdic.fbdic_fbd_state[2:0] == 3'h6); | |
69 | wire mcu3_l0link = (`CPU.mcu3.fbdic.fbdic_fbd_state[2:0] == 3'h6); | |
70 | ||
71 | wire mcu0_l0_ltoh = mcu0_l0link & ~mcu0_l0_d; | |
72 | wire mcu0_l0_htol = ~mcu0_l0link & mcu0_l0_d; | |
73 | ||
74 | wire mcu1_l0_ltoh = mcu1_l0link & ~mcu1_l0_d; | |
75 | wire mcu1_l0_htol = ~mcu1_l0link & mcu1_l0_d; | |
76 | ||
77 | wire mcu2_l0_ltoh = mcu2_l0link & ~mcu2_l0_d; | |
78 | wire mcu2_l0_htol = ~mcu2_l0link & mcu2_l0_d; | |
79 | ||
80 | wire mcu3_l0_ltoh = mcu3_l0link & ~mcu3_l0_d; | |
81 | wire mcu3_l0_htol = ~mcu3_l0link & mcu3_l0_d; | |
82 | ||
83 | always @(posedge (`CPU.mcu0.fbdic.l1clk & enabled)) | |
84 | begin | |
85 | mcu0_l0_d <= mcu0_l0link; | |
86 | mcu1_l0_d <= mcu1_l0link; | |
87 | mcu2_l0_d <= mcu2_l0link; | |
88 | mcu3_l0_d <= mcu3_l0link; | |
89 | ||
90 | if (mcu0_l0_ltoh) | |
91 | `PR_NORMAL("mcu0_l0mon", `NORMAL, "MCU0 L0 LINK is up" ); | |
92 | if (mcu1_l0_ltoh) | |
93 | `PR_NORMAL("mcu1_l0mon", `NORMAL, "MCU1 L0 LINK is up" ); | |
94 | if (mcu2_l0_ltoh) | |
95 | `PR_NORMAL("mcu2_l0mon", `NORMAL, "MCU2 L0 LINK is up" ); | |
96 | if (mcu3_l0_ltoh) | |
97 | `PR_NORMAL("mcu3_l0mon", `NORMAL, "MCU3 L0 LINK is up" ); | |
98 | ||
99 | if (mcu0_l0_htol) | |
100 | `PR_INFO("mcu0_l0mon", `INFO, "MCU0 L0 LINK HAS LOST SYNC"); | |
101 | if (mcu1_l0_htol) | |
102 | `PR_INFO("mcu1_l0mon", `INFO, "MCU1 L0 LINK HAS LOST SYNC"); | |
103 | if (mcu2_l0_htol) | |
104 | `PR_INFO("mcu2_l0mon", `INFO, "MCU2 L0 LINK HAS LOST SYNC"); | |
105 | if (mcu3_l0_htol) | |
106 | `PR_INFO("mcu3_l0mon", `INFO, "MCU3 L0 LINK HAS LOST SYNC"); | |
107 | end | |
108 | ||
109 | //if (`TOP.info===1'b1) $dispmon("NCU_MON", `INFO," NIU->NCU:: TYPE %0h; THR_ID %0h; PA = %0h; DATA = %0h;", i2c_pkt[3:0], i2c_pkt[9:4], i2c_pkt[54:15], i2c_pkt[127:64] ); | |
110 | //`CPU.peu.l2t_etp_link | |
111 | ||
112 | endmodule |