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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / global_chkr.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: global_chkr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module global_chkr;
36`ifndef GATESIM
37`ifndef NO_MONITORS
38`ifndef SPC_BENCH
39`ifndef AXIS
40`ifndef NOL2RTL
41
42reg [7:0] active;
43reg [7:0] core_set_mask;
44reg enabled;
45integer bank;
46integer dc_err;
47integer ic_err;
48integer bank_err;
49integer exc_err;
50initial
51begin
52 active = 8'b0;
53 enabled = 1'b0;
54 dc_err = 0;
55 ic_err = 0;
56 exc_err = 0;
57 bank_err = 0;
58 core_set_mask = 8'b0;
59 @(posedge `SPC0.l2clk);
60 @(negedge `SPC0.l2clk);
61 if (`PARGS.gchkr_on)
62 begin //{
63 enabled = 1;
64
65 if ((`PARGS.bank_set_mask !== 0) || (`PARGS.bank_set_mask_csr !== 0))
66 begin
67 enabled = 0;
68 `PR_ALWAYS("global_chkr", `ALWAYS, "GLOBAL_CHKR DISABLED (diag run in partial bank mode)\n");
69 end
70 else
71 begin //{
72 if ($test$plusargs("core_set_mask"))
73 begin
74 if ($value$plusargs("core_set_mask=%0h", core_set_mask))
75 begin
76 `PR_INFO("global_chkr", 22, "Partial core mode. core_set_mask = %0h", core_set_mask);
77 end
78 end
79 end //}
80 end //}
81end
82
83//core_set_mask and bank_set_mask are used to specify efuse settings and are used in file
84// /import/n2-tools/exe/efa_gen to generate the efuse mask.
85
86always @ (posedge (tb_top.sim_status[0] & enabled))
87begin //{
88
89 `ifdef CORE_0 active[0] = 1; `endif
90 `ifdef CORE_1 active[1] = 1; `endif
91 `ifdef CORE_2 active[2] = 1; `endif
92 `ifdef CORE_3 active[3] = 1; `endif
93 `ifdef CORE_4 active[4] = 1; `endif
94 `ifdef CORE_5 active[5] = 1; `endif
95 `ifdef CORE_6 active[6] = 1; `endif
96 `ifdef CORE_7 active[7] = 1; `endif
97if (core_set_mask == 8'b0)
98 core_set_mask = active;
99
100 `PR_ALWAYS("global_chkr", `ALWAYS, "L2-L1 chk started .....\n");
101
102 `PR_INFO("global_chkr", 22, "calling global_chkr_l1dump pli. active = %0h, core_set_mask = %0h", active, core_set_mask);
103
104 $global_chkr_l1dump(
105 core_set_mask,
106 active,
107 `ifdef CORE_0
108 `SPC0.lsu.dta.way0.mem,
109 `SPC0.lsu.dta.way1.mem,
110 `SPC0.lsu.dta.way2.mem,
111 `SPC0.lsu.dta.way3.mem,
112
113 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
114 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
115 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
116 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
117 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
118 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
119 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
120 `SPC0.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
121
122 `SPC0.lsu.dva.array.mem,
123 `SPC0.ifu_ftu.ftu_icv_cust.array.mem,
124 `endif
125
126 `ifdef CORE_1
127 `SPC1.lsu.dta.way0.mem,
128 `SPC1.lsu.dta.way1.mem,
129 `SPC1.lsu.dta.way2.mem,
130 `SPC1.lsu.dta.way3.mem,
131
132 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
133 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
134 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
135 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
136 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
137 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
138 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
139 `SPC1.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
140
141 `SPC1.lsu.dva.array.mem,
142 `SPC1.ifu_ftu.ftu_icv_cust.array.mem,
143 `endif
144
145 `ifdef CORE_2
146 `SPC2.lsu.dta.way0.mem,
147 `SPC2.lsu.dta.way1.mem,
148 `SPC2.lsu.dta.way2.mem,
149 `SPC2.lsu.dta.way3.mem,
150
151 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
152 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
153 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
154 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
155 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
156 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
157 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
158 `SPC2.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
159
160 `SPC2.lsu.dva.array.mem,
161 `SPC2.ifu_ftu.ftu_icv_cust.array.mem,
162 `endif
163
164 `ifdef CORE_3
165 `SPC3.lsu.dta.way0.mem,
166 `SPC3.lsu.dta.way1.mem,
167 `SPC3.lsu.dta.way2.mem,
168 `SPC3.lsu.dta.way3.mem,
169
170 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
171 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
172 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
173 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
174 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
175 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
176 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
177 `SPC3.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
178
179 `SPC3.lsu.dva.array.mem,
180 `SPC3.ifu_ftu.ftu_icv_cust.array.mem,
181 `endif
182
183 `ifdef CORE_4
184 `SPC4.lsu.dta.way0.mem,
185 `SPC4.lsu.dta.way1.mem,
186 `SPC4.lsu.dta.way2.mem,
187 `SPC4.lsu.dta.way3.mem,
188
189 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
190 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
191 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
192 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
193 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
194 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
195 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
196 `SPC4.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
197
198 `SPC4.lsu.dva.array.mem,
199 `SPC4.ifu_ftu.ftu_icv_cust.array.mem,
200 `endif
201
202 `ifdef CORE_5
203 `SPC5.lsu.dta.way0.mem,
204 `SPC5.lsu.dta.way1.mem,
205 `SPC5.lsu.dta.way2.mem,
206 `SPC5.lsu.dta.way3.mem,
207
208 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
209 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
210 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
211 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
212 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
213 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
214 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
215 `SPC5.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
216
217 `SPC5.lsu.dva.array.mem,
218 `SPC5.ifu_ftu.ftu_icv_cust.array.mem,
219 `endif
220
221 `ifdef CORE_6
222 `SPC6.lsu.dta.way0.mem,
223 `SPC6.lsu.dta.way1.mem,
224 `SPC6.lsu.dta.way2.mem,
225 `SPC6.lsu.dta.way3.mem,
226
227 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
228 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
229 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
230 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
231 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
232 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
233 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
234 `SPC6.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
235
236 `SPC6.lsu.dva.array.mem,
237 `SPC6.ifu_ftu.ftu_icv_cust.array.mem,
238 `endif
239
240 `ifdef CORE_7
241 `SPC7.lsu.dta.way0.mem,
242 `SPC7.lsu.dta.way1.mem,
243 `SPC7.lsu.dta.way2.mem,
244 `SPC7.lsu.dta.way3.mem,
245
246 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_0.mem,
247 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_1.mem,
248 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_2.mem,
249 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_3.mem,
250 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_4.mem,
251 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_5.mem,
252 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_6.mem,
253 `SPC7.ifu_ftu.ftu_ict_cust.tag_way_7.mem,
254
255 `SPC7.lsu.dva.array.mem,
256 `SPC7.ifu_ftu.ftu_icv_cust.array.mem
257 `endif
258
259 );
260
261 `PR_INFO("global_chkr", 22, "calling global_chkr_read_l2_tag pli.");
262
263 $global_chkr_read_l2_tag(
264 tb_top.cpu.l2t0.tag.quad0.bank0.l2t_array.mem_lft,
265 tb_top.cpu.l2t0.tag.quad0.bank0.l2t_array.mem_rgt,
266 tb_top.cpu.l2t0.tag.quad0.bank1.l2t_array.mem_lft,
267 tb_top.cpu.l2t0.tag.quad0.bank1.l2t_array.mem_rgt,
268
269 tb_top.cpu.l2t0.tag.quad1.bank0.l2t_array.mem_lft,
270 tb_top.cpu.l2t0.tag.quad1.bank0.l2t_array.mem_rgt,
271 tb_top.cpu.l2t0.tag.quad1.bank1.l2t_array.mem_lft,
272 tb_top.cpu.l2t0.tag.quad1.bank1.l2t_array.mem_rgt,
273
274 tb_top.cpu.l2t0.tag.quad2.bank0.l2t_array.mem_lft,
275 tb_top.cpu.l2t0.tag.quad2.bank0.l2t_array.mem_rgt,
276 tb_top.cpu.l2t0.tag.quad2.bank1.l2t_array.mem_lft,
277 tb_top.cpu.l2t0.tag.quad2.bank1.l2t_array.mem_rgt,
278
279 tb_top.cpu.l2t0.tag.quad3.bank0.l2t_array.mem_lft,
280 tb_top.cpu.l2t0.tag.quad3.bank0.l2t_array.mem_rgt,
281 tb_top.cpu.l2t0.tag.quad3.bank1.l2t_array.mem_lft,
282 tb_top.cpu.l2t0.tag.quad3.bank1.l2t_array.mem_rgt,
283
284 tb_top.cpu.l2t1.tag.quad0.bank0.l2t_array.mem_lft,
285 tb_top.cpu.l2t1.tag.quad0.bank0.l2t_array.mem_rgt,
286 tb_top.cpu.l2t1.tag.quad0.bank1.l2t_array.mem_lft,
287 tb_top.cpu.l2t1.tag.quad0.bank1.l2t_array.mem_rgt,
288
289 tb_top.cpu.l2t1.tag.quad1.bank0.l2t_array.mem_lft,
290 tb_top.cpu.l2t1.tag.quad1.bank0.l2t_array.mem_rgt,
291 tb_top.cpu.l2t1.tag.quad1.bank1.l2t_array.mem_lft,
292 tb_top.cpu.l2t1.tag.quad1.bank1.l2t_array.mem_rgt,
293
294 tb_top.cpu.l2t1.tag.quad2.bank0.l2t_array.mem_lft,
295 tb_top.cpu.l2t1.tag.quad2.bank0.l2t_array.mem_rgt,
296 tb_top.cpu.l2t1.tag.quad2.bank1.l2t_array.mem_lft,
297 tb_top.cpu.l2t1.tag.quad2.bank1.l2t_array.mem_rgt,
298
299 tb_top.cpu.l2t1.tag.quad3.bank0.l2t_array.mem_lft,
300 tb_top.cpu.l2t1.tag.quad3.bank0.l2t_array.mem_rgt,
301 tb_top.cpu.l2t1.tag.quad3.bank1.l2t_array.mem_lft,
302 tb_top.cpu.l2t1.tag.quad3.bank1.l2t_array.mem_rgt,
303
304 tb_top.cpu.l2t2.tag.quad0.bank0.l2t_array.mem_lft,
305 tb_top.cpu.l2t2.tag.quad0.bank0.l2t_array.mem_rgt,
306 tb_top.cpu.l2t2.tag.quad0.bank1.l2t_array.mem_lft,
307 tb_top.cpu.l2t2.tag.quad0.bank1.l2t_array.mem_rgt,
308
309 tb_top.cpu.l2t2.tag.quad1.bank0.l2t_array.mem_lft,
310 tb_top.cpu.l2t2.tag.quad1.bank0.l2t_array.mem_rgt,
311 tb_top.cpu.l2t2.tag.quad1.bank1.l2t_array.mem_lft,
312 tb_top.cpu.l2t2.tag.quad1.bank1.l2t_array.mem_rgt,
313
314 tb_top.cpu.l2t2.tag.quad2.bank0.l2t_array.mem_lft,
315 tb_top.cpu.l2t2.tag.quad2.bank0.l2t_array.mem_rgt,
316 tb_top.cpu.l2t2.tag.quad2.bank1.l2t_array.mem_lft,
317 tb_top.cpu.l2t2.tag.quad2.bank1.l2t_array.mem_rgt,
318
319 tb_top.cpu.l2t2.tag.quad3.bank0.l2t_array.mem_lft,
320 tb_top.cpu.l2t2.tag.quad3.bank0.l2t_array.mem_rgt,
321 tb_top.cpu.l2t2.tag.quad3.bank1.l2t_array.mem_lft,
322 tb_top.cpu.l2t2.tag.quad3.bank1.l2t_array.mem_rgt,
323
324 tb_top.cpu.l2t3.tag.quad0.bank0.l2t_array.mem_lft,
325 tb_top.cpu.l2t3.tag.quad0.bank0.l2t_array.mem_rgt,
326 tb_top.cpu.l2t3.tag.quad0.bank1.l2t_array.mem_lft,
327 tb_top.cpu.l2t3.tag.quad0.bank1.l2t_array.mem_rgt,
328
329 tb_top.cpu.l2t3.tag.quad1.bank0.l2t_array.mem_lft,
330 tb_top.cpu.l2t3.tag.quad1.bank0.l2t_array.mem_rgt,
331 tb_top.cpu.l2t3.tag.quad1.bank1.l2t_array.mem_lft,
332 tb_top.cpu.l2t3.tag.quad1.bank1.l2t_array.mem_rgt,
333
334 tb_top.cpu.l2t3.tag.quad2.bank0.l2t_array.mem_lft,
335 tb_top.cpu.l2t3.tag.quad2.bank0.l2t_array.mem_rgt,
336 tb_top.cpu.l2t3.tag.quad2.bank1.l2t_array.mem_lft,
337 tb_top.cpu.l2t3.tag.quad2.bank1.l2t_array.mem_rgt,
338
339 tb_top.cpu.l2t3.tag.quad3.bank0.l2t_array.mem_lft,
340 tb_top.cpu.l2t3.tag.quad3.bank0.l2t_array.mem_rgt,
341 tb_top.cpu.l2t3.tag.quad3.bank1.l2t_array.mem_lft,
342 tb_top.cpu.l2t3.tag.quad3.bank1.l2t_array.mem_rgt,
343
344 tb_top.cpu.l2t4.tag.quad0.bank0.l2t_array.mem_lft,
345 tb_top.cpu.l2t4.tag.quad0.bank0.l2t_array.mem_rgt,
346 tb_top.cpu.l2t4.tag.quad0.bank1.l2t_array.mem_lft,
347 tb_top.cpu.l2t4.tag.quad0.bank1.l2t_array.mem_rgt,
348
349 tb_top.cpu.l2t4.tag.quad1.bank0.l2t_array.mem_lft,
350 tb_top.cpu.l2t4.tag.quad1.bank0.l2t_array.mem_rgt,
351 tb_top.cpu.l2t4.tag.quad1.bank1.l2t_array.mem_lft,
352 tb_top.cpu.l2t4.tag.quad1.bank1.l2t_array.mem_rgt,
353
354 tb_top.cpu.l2t4.tag.quad2.bank0.l2t_array.mem_lft,
355 tb_top.cpu.l2t4.tag.quad2.bank0.l2t_array.mem_rgt,
356 tb_top.cpu.l2t4.tag.quad2.bank1.l2t_array.mem_lft,
357 tb_top.cpu.l2t4.tag.quad2.bank1.l2t_array.mem_rgt,
358
359 tb_top.cpu.l2t4.tag.quad3.bank0.l2t_array.mem_lft,
360 tb_top.cpu.l2t4.tag.quad3.bank0.l2t_array.mem_rgt,
361 tb_top.cpu.l2t4.tag.quad3.bank1.l2t_array.mem_lft,
362 tb_top.cpu.l2t4.tag.quad3.bank1.l2t_array.mem_rgt,
363
364 tb_top.cpu.l2t5.tag.quad0.bank0.l2t_array.mem_lft,
365 tb_top.cpu.l2t5.tag.quad0.bank0.l2t_array.mem_rgt,
366 tb_top.cpu.l2t5.tag.quad0.bank1.l2t_array.mem_lft,
367 tb_top.cpu.l2t5.tag.quad0.bank1.l2t_array.mem_rgt,
368
369 tb_top.cpu.l2t5.tag.quad1.bank0.l2t_array.mem_lft,
370 tb_top.cpu.l2t5.tag.quad1.bank0.l2t_array.mem_rgt,
371 tb_top.cpu.l2t5.tag.quad1.bank1.l2t_array.mem_lft,
372 tb_top.cpu.l2t5.tag.quad1.bank1.l2t_array.mem_rgt,
373
374 tb_top.cpu.l2t5.tag.quad2.bank0.l2t_array.mem_lft,
375 tb_top.cpu.l2t5.tag.quad2.bank0.l2t_array.mem_rgt,
376 tb_top.cpu.l2t5.tag.quad2.bank1.l2t_array.mem_lft,
377 tb_top.cpu.l2t5.tag.quad2.bank1.l2t_array.mem_rgt,
378
379 tb_top.cpu.l2t5.tag.quad3.bank0.l2t_array.mem_lft,
380 tb_top.cpu.l2t5.tag.quad3.bank0.l2t_array.mem_rgt,
381 tb_top.cpu.l2t5.tag.quad3.bank1.l2t_array.mem_lft,
382 tb_top.cpu.l2t5.tag.quad3.bank1.l2t_array.mem_rgt,
383
384 tb_top.cpu.l2t6.tag.quad0.bank0.l2t_array.mem_lft,
385 tb_top.cpu.l2t6.tag.quad0.bank0.l2t_array.mem_rgt,
386 tb_top.cpu.l2t6.tag.quad0.bank1.l2t_array.mem_lft,
387 tb_top.cpu.l2t6.tag.quad0.bank1.l2t_array.mem_rgt,
388
389 tb_top.cpu.l2t6.tag.quad1.bank0.l2t_array.mem_lft,
390 tb_top.cpu.l2t6.tag.quad1.bank0.l2t_array.mem_rgt,
391 tb_top.cpu.l2t6.tag.quad1.bank1.l2t_array.mem_lft,
392 tb_top.cpu.l2t6.tag.quad1.bank1.l2t_array.mem_rgt,
393
394 tb_top.cpu.l2t6.tag.quad2.bank0.l2t_array.mem_lft,
395 tb_top.cpu.l2t6.tag.quad2.bank0.l2t_array.mem_rgt,
396 tb_top.cpu.l2t6.tag.quad2.bank1.l2t_array.mem_lft,
397 tb_top.cpu.l2t6.tag.quad2.bank1.l2t_array.mem_rgt,
398
399 tb_top.cpu.l2t6.tag.quad3.bank0.l2t_array.mem_lft,
400 tb_top.cpu.l2t6.tag.quad3.bank0.l2t_array.mem_rgt,
401 tb_top.cpu.l2t6.tag.quad3.bank1.l2t_array.mem_lft,
402 tb_top.cpu.l2t6.tag.quad3.bank1.l2t_array.mem_rgt,
403
404 tb_top.cpu.l2t7.tag.quad0.bank0.l2t_array.mem_lft,
405 tb_top.cpu.l2t7.tag.quad0.bank0.l2t_array.mem_rgt,
406 tb_top.cpu.l2t7.tag.quad0.bank1.l2t_array.mem_lft,
407 tb_top.cpu.l2t7.tag.quad0.bank1.l2t_array.mem_rgt,
408
409 tb_top.cpu.l2t7.tag.quad1.bank0.l2t_array.mem_lft,
410 tb_top.cpu.l2t7.tag.quad1.bank0.l2t_array.mem_rgt,
411 tb_top.cpu.l2t7.tag.quad1.bank1.l2t_array.mem_lft,
412 tb_top.cpu.l2t7.tag.quad1.bank1.l2t_array.mem_rgt,
413
414 tb_top.cpu.l2t7.tag.quad2.bank0.l2t_array.mem_lft,
415 tb_top.cpu.l2t7.tag.quad2.bank0.l2t_array.mem_rgt,
416 tb_top.cpu.l2t7.tag.quad2.bank1.l2t_array.mem_lft,
417 tb_top.cpu.l2t7.tag.quad2.bank1.l2t_array.mem_rgt,
418
419 tb_top.cpu.l2t7.tag.quad3.bank0.l2t_array.mem_lft,
420 tb_top.cpu.l2t7.tag.quad3.bank0.l2t_array.mem_rgt,
421 tb_top.cpu.l2t7.tag.quad3.bank1.l2t_array.mem_lft,
422 tb_top.cpu.l2t7.tag.quad3.bank1.l2t_array.mem_rgt
423
424 );
425
426 `PR_INFO("global_chkr", 22, "calling global_chkr_read_l2_dc_dir pli.");
427
428 $global_chkr_read_l2_dc_dir(
429 tb_top.cpu.l2t0.dc_row0.panel0.array.addr_array,
430 tb_top.cpu.l2t0.dc_row0.panel0.array.valid,
431 tb_top.cpu.l2t0.dc_row0.panel1.array.addr_array,
432 tb_top.cpu.l2t0.dc_row0.panel1.array.valid,
433 tb_top.cpu.l2t0.dc_row0.panel2.array.addr_array,
434 tb_top.cpu.l2t0.dc_row0.panel2.array.valid,
435 tb_top.cpu.l2t0.dc_row0.panel3.array.addr_array,
436 tb_top.cpu.l2t0.dc_row0.panel3.array.valid,
437
438 tb_top.cpu.l2t0.dc_row2.panel0.array.addr_array,
439 tb_top.cpu.l2t0.dc_row2.panel0.array.valid,
440 tb_top.cpu.l2t0.dc_row2.panel1.array.addr_array,
441 tb_top.cpu.l2t0.dc_row2.panel1.array.valid,
442 tb_top.cpu.l2t0.dc_row2.panel2.array.addr_array,
443 tb_top.cpu.l2t0.dc_row2.panel2.array.valid,
444 tb_top.cpu.l2t0.dc_row2.panel3.array.addr_array,
445 tb_top.cpu.l2t0.dc_row2.panel3.array.valid,
446
447 tb_top.cpu.l2t1.dc_row0.panel0.array.addr_array,
448 tb_top.cpu.l2t1.dc_row0.panel0.array.valid,
449 tb_top.cpu.l2t1.dc_row0.panel1.array.addr_array,
450 tb_top.cpu.l2t1.dc_row0.panel1.array.valid,
451 tb_top.cpu.l2t1.dc_row0.panel2.array.addr_array,
452 tb_top.cpu.l2t1.dc_row0.panel2.array.valid,
453 tb_top.cpu.l2t1.dc_row0.panel3.array.addr_array,
454 tb_top.cpu.l2t1.dc_row0.panel3.array.valid,
455
456 tb_top.cpu.l2t1.dc_row2.panel0.array.addr_array,
457 tb_top.cpu.l2t1.dc_row2.panel0.array.valid,
458 tb_top.cpu.l2t1.dc_row2.panel1.array.addr_array,
459 tb_top.cpu.l2t1.dc_row2.panel1.array.valid,
460 tb_top.cpu.l2t1.dc_row2.panel2.array.addr_array,
461 tb_top.cpu.l2t1.dc_row2.panel2.array.valid,
462 tb_top.cpu.l2t1.dc_row2.panel3.array.addr_array,
463 tb_top.cpu.l2t1.dc_row2.panel3.array.valid,
464
465 tb_top.cpu.l2t2.dc_row0.panel0.array.addr_array,
466 tb_top.cpu.l2t2.dc_row0.panel0.array.valid,
467 tb_top.cpu.l2t2.dc_row0.panel1.array.addr_array,
468 tb_top.cpu.l2t2.dc_row0.panel1.array.valid,
469 tb_top.cpu.l2t2.dc_row0.panel2.array.addr_array,
470 tb_top.cpu.l2t2.dc_row0.panel2.array.valid,
471 tb_top.cpu.l2t2.dc_row0.panel3.array.addr_array,
472 tb_top.cpu.l2t2.dc_row0.panel3.array.valid,
473
474 tb_top.cpu.l2t2.dc_row2.panel0.array.addr_array,
475 tb_top.cpu.l2t2.dc_row2.panel0.array.valid,
476 tb_top.cpu.l2t2.dc_row2.panel1.array.addr_array,
477 tb_top.cpu.l2t2.dc_row2.panel1.array.valid,
478 tb_top.cpu.l2t2.dc_row2.panel2.array.addr_array,
479 tb_top.cpu.l2t2.dc_row2.panel2.array.valid,
480 tb_top.cpu.l2t2.dc_row2.panel3.array.addr_array,
481 tb_top.cpu.l2t2.dc_row2.panel3.array.valid,
482
483 tb_top.cpu.l2t3.dc_row0.panel0.array.addr_array,
484 tb_top.cpu.l2t3.dc_row0.panel0.array.valid,
485 tb_top.cpu.l2t3.dc_row0.panel1.array.addr_array,
486 tb_top.cpu.l2t3.dc_row0.panel1.array.valid,
487 tb_top.cpu.l2t3.dc_row0.panel2.array.addr_array,
488 tb_top.cpu.l2t3.dc_row0.panel2.array.valid,
489 tb_top.cpu.l2t3.dc_row0.panel3.array.addr_array,
490 tb_top.cpu.l2t3.dc_row0.panel3.array.valid,
491
492 tb_top.cpu.l2t3.dc_row2.panel0.array.addr_array,
493 tb_top.cpu.l2t3.dc_row2.panel0.array.valid,
494 tb_top.cpu.l2t3.dc_row2.panel1.array.addr_array,
495 tb_top.cpu.l2t3.dc_row2.panel1.array.valid,
496 tb_top.cpu.l2t3.dc_row2.panel2.array.addr_array,
497 tb_top.cpu.l2t3.dc_row2.panel2.array.valid,
498 tb_top.cpu.l2t3.dc_row2.panel3.array.addr_array,
499 tb_top.cpu.l2t3.dc_row2.panel3.array.valid,
500
501 tb_top.cpu.l2t4.dc_row0.panel0.array.addr_array,
502 tb_top.cpu.l2t4.dc_row0.panel0.array.valid,
503 tb_top.cpu.l2t4.dc_row0.panel1.array.addr_array,
504 tb_top.cpu.l2t4.dc_row0.panel1.array.valid,
505 tb_top.cpu.l2t4.dc_row0.panel2.array.addr_array,
506 tb_top.cpu.l2t4.dc_row0.panel2.array.valid,
507 tb_top.cpu.l2t4.dc_row0.panel3.array.addr_array,
508 tb_top.cpu.l2t4.dc_row0.panel3.array.valid,
509
510 tb_top.cpu.l2t4.dc_row2.panel0.array.addr_array,
511 tb_top.cpu.l2t4.dc_row2.panel0.array.valid,
512 tb_top.cpu.l2t4.dc_row2.panel1.array.addr_array,
513 tb_top.cpu.l2t4.dc_row2.panel1.array.valid,
514 tb_top.cpu.l2t4.dc_row2.panel2.array.addr_array,
515 tb_top.cpu.l2t4.dc_row2.panel2.array.valid,
516 tb_top.cpu.l2t4.dc_row2.panel3.array.addr_array,
517 tb_top.cpu.l2t4.dc_row2.panel3.array.valid,
518
519 tb_top.cpu.l2t5.dc_row0.panel0.array.addr_array,
520 tb_top.cpu.l2t5.dc_row0.panel0.array.valid,
521 tb_top.cpu.l2t5.dc_row0.panel1.array.addr_array,
522 tb_top.cpu.l2t5.dc_row0.panel1.array.valid,
523 tb_top.cpu.l2t5.dc_row0.panel2.array.addr_array,
524 tb_top.cpu.l2t5.dc_row0.panel2.array.valid,
525 tb_top.cpu.l2t5.dc_row0.panel3.array.addr_array,
526 tb_top.cpu.l2t5.dc_row0.panel3.array.valid,
527
528 tb_top.cpu.l2t5.dc_row2.panel0.array.addr_array,
529 tb_top.cpu.l2t5.dc_row2.panel0.array.valid,
530 tb_top.cpu.l2t5.dc_row2.panel1.array.addr_array,
531 tb_top.cpu.l2t5.dc_row2.panel1.array.valid,
532 tb_top.cpu.l2t5.dc_row2.panel2.array.addr_array,
533 tb_top.cpu.l2t5.dc_row2.panel2.array.valid,
534 tb_top.cpu.l2t5.dc_row2.panel3.array.addr_array,
535 tb_top.cpu.l2t5.dc_row2.panel3.array.valid,
536
537 tb_top.cpu.l2t6.dc_row0.panel0.array.addr_array,
538 tb_top.cpu.l2t6.dc_row0.panel0.array.valid,
539 tb_top.cpu.l2t6.dc_row0.panel1.array.addr_array,
540 tb_top.cpu.l2t6.dc_row0.panel1.array.valid,
541 tb_top.cpu.l2t6.dc_row0.panel2.array.addr_array,
542 tb_top.cpu.l2t6.dc_row0.panel2.array.valid,
543 tb_top.cpu.l2t6.dc_row0.panel3.array.addr_array,
544 tb_top.cpu.l2t6.dc_row0.panel3.array.valid,
545
546 tb_top.cpu.l2t6.dc_row2.panel0.array.addr_array,
547 tb_top.cpu.l2t6.dc_row2.panel0.array.valid,
548 tb_top.cpu.l2t6.dc_row2.panel1.array.addr_array,
549 tb_top.cpu.l2t6.dc_row2.panel1.array.valid,
550 tb_top.cpu.l2t6.dc_row2.panel2.array.addr_array,
551 tb_top.cpu.l2t6.dc_row2.panel2.array.valid,
552 tb_top.cpu.l2t6.dc_row2.panel3.array.addr_array,
553 tb_top.cpu.l2t6.dc_row2.panel3.array.valid,
554
555 tb_top.cpu.l2t7.dc_row0.panel0.array.addr_array,
556 tb_top.cpu.l2t7.dc_row0.panel0.array.valid,
557 tb_top.cpu.l2t7.dc_row0.panel1.array.addr_array,
558 tb_top.cpu.l2t7.dc_row0.panel1.array.valid,
559 tb_top.cpu.l2t7.dc_row0.panel2.array.addr_array,
560 tb_top.cpu.l2t7.dc_row0.panel2.array.valid,
561 tb_top.cpu.l2t7.dc_row0.panel3.array.addr_array,
562 tb_top.cpu.l2t7.dc_row0.panel3.array.valid,
563
564 tb_top.cpu.l2t7.dc_row2.panel0.array.addr_array,
565 tb_top.cpu.l2t7.dc_row2.panel0.array.valid,
566 tb_top.cpu.l2t7.dc_row2.panel1.array.addr_array,
567 tb_top.cpu.l2t7.dc_row2.panel1.array.valid,
568 tb_top.cpu.l2t7.dc_row2.panel2.array.addr_array,
569 tb_top.cpu.l2t7.dc_row2.panel2.array.valid,
570 tb_top.cpu.l2t7.dc_row2.panel3.array.addr_array,
571 tb_top.cpu.l2t7.dc_row2.panel3.array.valid
572
573 );
574
575 `PR_INFO("global_chkr", 22, "calling global_chkr_read_l2_ic_dir pli.");
576
577 $global_chkr_read_l2_ic_dir(
578 tb_top.cpu.l2t0.ic_row0.panel0.array.addr_array,
579 tb_top.cpu.l2t0.ic_row0.panel0.array.valid,
580 tb_top.cpu.l2t0.ic_row0.panel1.array.addr_array,
581 tb_top.cpu.l2t0.ic_row0.panel1.array.valid,
582 tb_top.cpu.l2t0.ic_row0.panel2.array.addr_array,
583 tb_top.cpu.l2t0.ic_row0.panel2.array.valid,
584 tb_top.cpu.l2t0.ic_row0.panel3.array.addr_array,
585 tb_top.cpu.l2t0.ic_row0.panel3.array.valid,
586
587 tb_top.cpu.l2t0.ic_row2.panel0.array.addr_array,
588 tb_top.cpu.l2t0.ic_row2.panel0.array.valid,
589 tb_top.cpu.l2t0.ic_row2.panel1.array.addr_array,
590 tb_top.cpu.l2t0.ic_row2.panel1.array.valid,
591 tb_top.cpu.l2t0.ic_row2.panel2.array.addr_array,
592 tb_top.cpu.l2t0.ic_row2.panel2.array.valid,
593 tb_top.cpu.l2t0.ic_row2.panel3.array.addr_array,
594 tb_top.cpu.l2t0.ic_row2.panel3.array.valid,
595
596 tb_top.cpu.l2t1.ic_row0.panel0.array.addr_array,
597 tb_top.cpu.l2t1.ic_row0.panel0.array.valid,
598 tb_top.cpu.l2t1.ic_row0.panel1.array.addr_array,
599 tb_top.cpu.l2t1.ic_row0.panel1.array.valid,
600 tb_top.cpu.l2t1.ic_row0.panel2.array.addr_array,
601 tb_top.cpu.l2t1.ic_row0.panel2.array.valid,
602 tb_top.cpu.l2t1.ic_row0.panel3.array.addr_array,
603 tb_top.cpu.l2t1.ic_row0.panel3.array.valid,
604
605 tb_top.cpu.l2t1.ic_row2.panel0.array.addr_array,
606 tb_top.cpu.l2t1.ic_row2.panel0.array.valid,
607 tb_top.cpu.l2t1.ic_row2.panel1.array.addr_array,
608 tb_top.cpu.l2t1.ic_row2.panel1.array.valid,
609 tb_top.cpu.l2t1.ic_row2.panel2.array.addr_array,
610 tb_top.cpu.l2t1.ic_row2.panel2.array.valid,
611 tb_top.cpu.l2t1.ic_row2.panel3.array.addr_array,
612 tb_top.cpu.l2t1.ic_row2.panel3.array.valid,
613
614 tb_top.cpu.l2t2.ic_row0.panel0.array.addr_array,
615 tb_top.cpu.l2t2.ic_row0.panel0.array.valid,
616 tb_top.cpu.l2t2.ic_row0.panel1.array.addr_array,
617 tb_top.cpu.l2t2.ic_row0.panel1.array.valid,
618 tb_top.cpu.l2t2.ic_row0.panel2.array.addr_array,
619 tb_top.cpu.l2t2.ic_row0.panel2.array.valid,
620 tb_top.cpu.l2t2.ic_row0.panel3.array.addr_array,
621 tb_top.cpu.l2t2.ic_row0.panel3.array.valid,
622
623 tb_top.cpu.l2t2.ic_row2.panel0.array.addr_array,
624 tb_top.cpu.l2t2.ic_row2.panel0.array.valid,
625 tb_top.cpu.l2t2.ic_row2.panel1.array.addr_array,
626 tb_top.cpu.l2t2.ic_row2.panel1.array.valid,
627 tb_top.cpu.l2t2.ic_row2.panel2.array.addr_array,
628 tb_top.cpu.l2t2.ic_row2.panel2.array.valid,
629 tb_top.cpu.l2t2.ic_row2.panel3.array.addr_array,
630 tb_top.cpu.l2t2.ic_row2.panel3.array.valid,
631
632 tb_top.cpu.l2t3.ic_row0.panel0.array.addr_array,
633 tb_top.cpu.l2t3.ic_row0.panel0.array.valid,
634 tb_top.cpu.l2t3.ic_row0.panel1.array.addr_array,
635 tb_top.cpu.l2t3.ic_row0.panel1.array.valid,
636 tb_top.cpu.l2t3.ic_row0.panel2.array.addr_array,
637 tb_top.cpu.l2t3.ic_row0.panel2.array.valid,
638 tb_top.cpu.l2t3.ic_row0.panel3.array.addr_array,
639 tb_top.cpu.l2t3.ic_row0.panel3.array.valid,
640
641 tb_top.cpu.l2t3.ic_row2.panel0.array.addr_array,
642 tb_top.cpu.l2t3.ic_row2.panel0.array.valid,
643 tb_top.cpu.l2t3.ic_row2.panel1.array.addr_array,
644 tb_top.cpu.l2t3.ic_row2.panel1.array.valid,
645 tb_top.cpu.l2t3.ic_row2.panel2.array.addr_array,
646 tb_top.cpu.l2t3.ic_row2.panel2.array.valid,
647 tb_top.cpu.l2t3.ic_row2.panel3.array.addr_array,
648 tb_top.cpu.l2t3.ic_row2.panel3.array.valid,
649
650 tb_top.cpu.l2t4.ic_row0.panel0.array.addr_array,
651 tb_top.cpu.l2t4.ic_row0.panel0.array.valid,
652 tb_top.cpu.l2t4.ic_row0.panel1.array.addr_array,
653 tb_top.cpu.l2t4.ic_row0.panel1.array.valid,
654 tb_top.cpu.l2t4.ic_row0.panel2.array.addr_array,
655 tb_top.cpu.l2t4.ic_row0.panel2.array.valid,
656 tb_top.cpu.l2t4.ic_row0.panel3.array.addr_array,
657 tb_top.cpu.l2t4.ic_row0.panel3.array.valid,
658
659 tb_top.cpu.l2t4.ic_row2.panel0.array.addr_array,
660 tb_top.cpu.l2t4.ic_row2.panel0.array.valid,
661 tb_top.cpu.l2t4.ic_row2.panel1.array.addr_array,
662 tb_top.cpu.l2t4.ic_row2.panel1.array.valid,
663 tb_top.cpu.l2t4.ic_row2.panel2.array.addr_array,
664 tb_top.cpu.l2t4.ic_row2.panel2.array.valid,
665 tb_top.cpu.l2t4.ic_row2.panel3.array.addr_array,
666 tb_top.cpu.l2t4.ic_row2.panel3.array.valid,
667
668 tb_top.cpu.l2t5.ic_row0.panel0.array.addr_array,
669 tb_top.cpu.l2t5.ic_row0.panel0.array.valid,
670 tb_top.cpu.l2t5.ic_row0.panel1.array.addr_array,
671 tb_top.cpu.l2t5.ic_row0.panel1.array.valid,
672 tb_top.cpu.l2t5.ic_row0.panel2.array.addr_array,
673 tb_top.cpu.l2t5.ic_row0.panel2.array.valid,
674 tb_top.cpu.l2t5.ic_row0.panel3.array.addr_array,
675 tb_top.cpu.l2t5.ic_row0.panel3.array.valid,
676
677 tb_top.cpu.l2t5.ic_row2.panel0.array.addr_array,
678 tb_top.cpu.l2t5.ic_row2.panel0.array.valid,
679 tb_top.cpu.l2t5.ic_row2.panel1.array.addr_array,
680 tb_top.cpu.l2t5.ic_row2.panel1.array.valid,
681 tb_top.cpu.l2t5.ic_row2.panel2.array.addr_array,
682 tb_top.cpu.l2t5.ic_row2.panel2.array.valid,
683 tb_top.cpu.l2t5.ic_row2.panel3.array.addr_array,
684 tb_top.cpu.l2t5.ic_row2.panel3.array.valid,
685
686 tb_top.cpu.l2t6.ic_row0.panel0.array.addr_array,
687 tb_top.cpu.l2t6.ic_row0.panel0.array.valid,
688 tb_top.cpu.l2t6.ic_row0.panel1.array.addr_array,
689 tb_top.cpu.l2t6.ic_row0.panel1.array.valid,
690 tb_top.cpu.l2t6.ic_row0.panel2.array.addr_array,
691 tb_top.cpu.l2t6.ic_row0.panel2.array.valid,
692 tb_top.cpu.l2t6.ic_row0.panel3.array.addr_array,
693 tb_top.cpu.l2t6.ic_row0.panel3.array.valid,
694
695 tb_top.cpu.l2t6.ic_row2.panel0.array.addr_array,
696 tb_top.cpu.l2t6.ic_row2.panel0.array.valid,
697 tb_top.cpu.l2t6.ic_row2.panel1.array.addr_array,
698 tb_top.cpu.l2t6.ic_row2.panel1.array.valid,
699 tb_top.cpu.l2t6.ic_row2.panel2.array.addr_array,
700 tb_top.cpu.l2t6.ic_row2.panel2.array.valid,
701 tb_top.cpu.l2t6.ic_row2.panel3.array.addr_array,
702 tb_top.cpu.l2t6.ic_row2.panel3.array.valid,
703
704 tb_top.cpu.l2t7.ic_row0.panel0.array.addr_array,
705 tb_top.cpu.l2t7.ic_row0.panel0.array.valid,
706 tb_top.cpu.l2t7.ic_row0.panel1.array.addr_array,
707 tb_top.cpu.l2t7.ic_row0.panel1.array.valid,
708 tb_top.cpu.l2t7.ic_row0.panel2.array.addr_array,
709 tb_top.cpu.l2t7.ic_row0.panel2.array.valid,
710 tb_top.cpu.l2t7.ic_row0.panel3.array.addr_array,
711 tb_top.cpu.l2t7.ic_row0.panel3.array.valid,
712
713 tb_top.cpu.l2t7.ic_row2.panel0.array.addr_array,
714 tb_top.cpu.l2t7.ic_row2.panel0.array.valid,
715 tb_top.cpu.l2t7.ic_row2.panel1.array.addr_array,
716 tb_top.cpu.l2t7.ic_row2.panel1.array.valid,
717 tb_top.cpu.l2t7.ic_row2.panel2.array.addr_array,
718 tb_top.cpu.l2t7.ic_row2.panel2.array.valid,
719 tb_top.cpu.l2t7.ic_row2.panel3.array.addr_array,
720 tb_top.cpu.l2t7.ic_row2.panel3.array.valid
721
722 );
723
724 for (bank = 0; bank < 8; bank = bank + 1)
725 begin //{
726 dc_err = 0;
727 ic_err = 0;
728 exc_err = 0;
729 `PR_INFO("global_chkr", 22, "Bank%0d calling global_chkr_cmp_l2_dir pli.", bank);
730 $global_chkr_cmp_l1_data(bank, dc_err, ic_err, exc_err);
731 if (dc_err)
732 begin
733 bank_err = bank_err + 1;
734 `PR_ALWAYS("global_chkr", `ALWAYS, "L2$ Bank %0d: D data mismatch with L1 # 0f mismatches=%d", bank, dc_err);
735 end
736 if (ic_err)
737 begin
738 bank_err = bank_err + 1;
739 `PR_ALWAYS("global_chkr", `ALWAYS, "L2$ Bank %0d: I data mismatch with L1 # 0f mismatches=%d", bank, ic_err);
740 end
741 if (exc_err)
742 begin
743 bank_err = bank_err + 1;
744 `PR_ALWAYS("global_chkr", `ALWAYS, "L2$ Bank %0d: I$-D$ mutual exclusion violation. # 0f mismatches=%d", bank, exc_err);
745 end
746 end //}
747 if (bank_err)
748 `PR_ERROR("global_chkr", `ERROR, "L2 L1$ data mismatch. Pl. run simulation with plusarg gchkr_debug, -vcs_run_args=+show_pa and -vcs_run_args=+ccxPktPrint=spc for more info.");
749
750end //}
751
752`endif
753`endif
754`endif
755`endif
756`endif
757
758endmodule
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