projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: l2_tagstate_mon.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `define TB_TOP0 tb_top.cpu.l2t0 | |
| 36 | `define TB_TOP1 tb_top.cpu.l2t1 | |
| 37 | `define TB_TOP2 tb_top.cpu.l2t2 | |
| 38 | `define TB_TOP3 tb_top.cpu.l2t3 | |
| 39 | `define TB_TOP4 tb_top.cpu.l2t4 | |
| 40 | `define TB_TOP5 tb_top.cpu.l2t5 | |
| 41 | `define TB_TOP6 tb_top.cpu.l2t6 | |
| 42 | `define TB_TOP7 tb_top.cpu.l2t7 | |
| 43 | ||
| 44 | module l2_tagstate_mon() ; | |
| 45 | ||
| 46 | reg l2_tagstate_mon; | |
| 47 | ||
| 48 | initial | |
| 49 | begin | |
| 50 | l2_tagstate_mon = 1; //Enabled by default | |
| 51 | if(("l2_tagstate_mon_off")) | |
| 52 | l2_tagstate_mon = 0; | |
| 53 | end | |
| 54 | ||
| 55 | //-------------------------------------------------------------------------------------- | |
| 56 | // Enable/Disable support : MAQ | |
| 57 | //-------------------------------------------------------------------------------------- | |
| 58 | ||
| 59 | wire flush_reset_complete = `TOP.flush_reset_complete; | |
| 60 | ||
| 61 | reg enabled; | |
| 62 | initial | |
| 63 | begin | |
| 64 | enabled = 1'b1; | |
| 65 | if ($test$plusargs("l2_tagstate_mon_off")) | |
| 66 | enabled = 1'b0; | |
| 67 | end | |
| 68 | ||
| 69 | always @ (flush_reset_complete) | |
| 70 | begin | |
| 71 | if (flush_reset_complete == 1'b0) | |
| 72 | enabled = 1'b0; | |
| 73 | ||
| 74 | if ((flush_reset_complete == 1'b1) && (!($test$plusargs("l2_tagstate_mon_off")))) | |
| 75 | enabled = 1'b1; | |
| 76 | end | |
| 77 | ||
| 78 | wire cmp_clk = (tb_top.cpu.l2clk & enabled); | |
| 79 | ||
| 80 | //-------------------------------------------------------------------------------------- | |
| 81 | ||
| 82 | ||
| 83 | // MAQ: wire cmp_clk = tb_top.cpu.l2clk; | |
| 84 | wire cmp_rst_l = tb_top.cpu.rst_l2_por_; | |
| 85 | ||
| 86 | ||
| 87 | ||
| 88 | //---------------------------------------------------------------------------------------- | |
| 89 | // Tag and VUAD update signals | |
| 90 | //---------------------------------------------------------------------------------------- | |
| 91 | ||
| 92 | wire [8:0] l2t0_tag_index = `TB_TOP0.tag.index0[8:0]; | |
| 93 | wire l2t0_wr_en = `TB_TOP0.tag.wr_en0; | |
| 94 | wire [15:0] l2t0_way = `TB_TOP0.tag.way[15:0]; | |
| 95 | wire [27:0] l2t0_wrdata = `TB_TOP0.tag.wrdata0[27:0]; | |
| 96 | wire [21:0] l2t0_tag = `TB_TOP0.tag.wrdata0[27:6]; | |
| 97 | ||
| 98 | wire [39:0] l2t0_addr = `TB_TOP0.arbadr.arbdp_addr_c2[39:0]; | |
| 99 | wire l2t0_inst_vld = `TB_TOP0.arb.arb_inst_vld_c2; | |
| 100 | wire [15:0] l2t0_used = `TB_TOP0.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 101 | wire [15:0] l2t0_alloc = `TB_TOP0.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 102 | wire [15:0] l2t0_valid = `TB_TOP0.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 103 | wire [15:0] l2t0_dirty = `TB_TOP0.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 104 | wire [8:0] l2t0_vuad_index = `TB_TOP0.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 105 | wire l2t0_vuad_wr = `TB_TOP0.vuad.vuad_array_wr_en0_c3; | |
| 106 | ||
| 107 | wire l2t0_tagonly_hit = `TB_TOP0.tagctl.tag_hit_c2; | |
| 108 | ||
| 109 | ||
| 110 | //---------------------------------------------------------------------------------------- | |
| 111 | // Tag and VUAD update signals | |
| 112 | //---------------------------------------------------------------------------------------- | |
| 113 | ||
| 114 | wire [8:0] l2t1_tag_index = `TB_TOP1.tag.index0[8:0]; | |
| 115 | wire l2t1_wr_en = `TB_TOP1.tag.wr_en0; | |
| 116 | wire [15:0] l2t1_way = `TB_TOP1.tag.way[15:0]; | |
| 117 | wire [27:0] l2t1_wrdata = `TB_TOP1.tag.wrdata0[27:0]; | |
| 118 | wire [21:0] l2t1_tag = `TB_TOP1.tag.wrdata0[27:6]; | |
| 119 | ||
| 120 | wire [39:0] l2t1_addr = `TB_TOP1.arbadr.arbdp_addr_c2[39:0]; | |
| 121 | wire l2t1_inst_vld = `TB_TOP1.arb.arb_inst_vld_c2; | |
| 122 | wire [15:0] l2t1_used = `TB_TOP1.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 123 | wire [15:0] l2t1_alloc = `TB_TOP1.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 124 | wire [15:0] l2t1_valid = `TB_TOP1.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 125 | wire [15:0] l2t1_dirty = `TB_TOP1.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 126 | wire [8:0] l2t1_vuad_index = `TB_TOP1.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 127 | wire l2t1_vuad_wr = `TB_TOP1.vuad.vuad_array_wr_en0_c3; | |
| 128 | ||
| 129 | wire l2t1_tagonly_hit = `TB_TOP1.tagctl.tag_hit_c2; | |
| 130 | ||
| 131 | ||
| 132 | //---------------------------------------------------------------------------------------- | |
| 133 | // Tag and VUAD update signals | |
| 134 | //---------------------------------------------------------------------------------------- | |
| 135 | ||
| 136 | wire [8:0] l2t2_tag_index = `TB_TOP2.tag.index0[8:0]; | |
| 137 | wire l2t2_wr_en = `TB_TOP2.tag.wr_en0; | |
| 138 | wire [15:0] l2t2_way = `TB_TOP2.tag.way[15:0]; | |
| 139 | wire [27:0] l2t2_wrdata = `TB_TOP2.tag.wrdata0[27:0]; | |
| 140 | wire [21:0] l2t2_tag = `TB_TOP2.tag.wrdata0[27:6]; | |
| 141 | ||
| 142 | wire [39:0] l2t2_addr = `TB_TOP2.arbadr.arbdp_addr_c2[39:0]; | |
| 143 | wire l2t2_inst_vld = `TB_TOP2.arb.arb_inst_vld_c2; | |
| 144 | wire [15:0] l2t2_used = `TB_TOP2.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 145 | wire [15:0] l2t2_alloc = `TB_TOP2.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 146 | wire [15:0] l2t2_valid = `TB_TOP2.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 147 | wire [15:0] l2t2_dirty = `TB_TOP2.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 148 | wire [8:0] l2t2_vuad_index = `TB_TOP2.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 149 | wire l2t2_vuad_wr = `TB_TOP2.vuad.vuad_array_wr_en0_c3; | |
| 150 | ||
| 151 | wire l2t2_tagonly_hit = `TB_TOP2.tagctl.tag_hit_c2; | |
| 152 | ||
| 153 | ||
| 154 | //---------------------------------------------------------------------------------------- | |
| 155 | // Tag and VUAD update signals | |
| 156 | //---------------------------------------------------------------------------------------- | |
| 157 | ||
| 158 | wire [8:0] l2t3_tag_index = `TB_TOP3.tag.index0[8:0]; | |
| 159 | wire l2t3_wr_en = `TB_TOP3.tag.wr_en0; | |
| 160 | wire [15:0] l2t3_way = `TB_TOP3.tag.way[15:0]; | |
| 161 | wire [27:0] l2t3_wrdata = `TB_TOP3.tag.wrdata0[27:0]; | |
| 162 | wire [21:0] l2t3_tag = `TB_TOP3.tag.wrdata0[27:6]; | |
| 163 | ||
| 164 | wire [39:0] l2t3_addr = `TB_TOP3.arbadr.arbdp_addr_c2[39:0]; | |
| 165 | wire l2t3_inst_vld = `TB_TOP3.arb.arb_inst_vld_c2; | |
| 166 | wire [15:0] l2t3_used = `TB_TOP3.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 167 | wire [15:0] l2t3_alloc = `TB_TOP3.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 168 | wire [15:0] l2t3_valid = `TB_TOP3.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 169 | wire [15:0] l2t3_dirty = `TB_TOP3.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 170 | wire [8:0] l2t3_vuad_index = `TB_TOP3.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 171 | wire l2t3_vuad_wr = `TB_TOP3.vuad.vuad_array_wr_en0_c3; | |
| 172 | ||
| 173 | wire l2t3_tagonly_hit = `TB_TOP3.tagctl.tag_hit_c2; | |
| 174 | ||
| 175 | ||
| 176 | //---------------------------------------------------------------------------------------- | |
| 177 | // Tag and VUAD update signals | |
| 178 | //---------------------------------------------------------------------------------------- | |
| 179 | ||
| 180 | wire [8:0] l2t4_tag_index = `TB_TOP4.tag.index0[8:0]; | |
| 181 | wire l2t4_wr_en = `TB_TOP4.tag.wr_en0; | |
| 182 | wire [15:0] l2t4_way = `TB_TOP4.tag.way[15:0]; | |
| 183 | wire [27:0] l2t4_wrdata = `TB_TOP4.tag.wrdata0[27:0]; | |
| 184 | wire [21:0] l2t4_tag = `TB_TOP4.tag.wrdata0[27:6]; | |
| 185 | ||
| 186 | wire [39:0] l2t4_addr = `TB_TOP4.arbadr.arbdp_addr_c2[39:0]; | |
| 187 | wire l2t4_inst_vld = `TB_TOP4.arb.arb_inst_vld_c2; | |
| 188 | wire [15:0] l2t4_used = `TB_TOP4.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 189 | wire [15:0] l2t4_alloc = `TB_TOP4.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 190 | wire [15:0] l2t4_valid = `TB_TOP4.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 191 | wire [15:0] l2t4_dirty = `TB_TOP4.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 192 | wire [8:0] l2t4_vuad_index = `TB_TOP4.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 193 | wire l2t4_vuad_wr = `TB_TOP4.vuad.vuad_array_wr_en0_c3; | |
| 194 | ||
| 195 | wire l2t4_tagonly_hit = `TB_TOP4.tagctl.tag_hit_c2; | |
| 196 | ||
| 197 | ||
| 198 | //---------------------------------------------------------------------------------------- | |
| 199 | // Tag and VUAD update signals | |
| 200 | //---------------------------------------------------------------------------------------- | |
| 201 | ||
| 202 | wire [8:0] l2t5_tag_index = `TB_TOP5.tag.index0[8:0]; | |
| 203 | wire l2t5_wr_en = `TB_TOP5.tag.wr_en0; | |
| 204 | wire [15:0] l2t5_way = `TB_TOP5.tag.way[15:0]; | |
| 205 | wire [27:0] l2t5_wrdata = `TB_TOP5.tag.wrdata0[27:0]; | |
| 206 | wire [21:0] l2t5_tag = `TB_TOP5.tag.wrdata0[27:6]; | |
| 207 | ||
| 208 | wire [39:0] l2t5_addr = `TB_TOP5.arbadr.arbdp_addr_c2[39:0]; | |
| 209 | wire l2t5_inst_vld = `TB_TOP5.arb.arb_inst_vld_c2; | |
| 210 | wire [15:0] l2t5_used = `TB_TOP5.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 211 | wire [15:0] l2t5_alloc = `TB_TOP5.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 212 | wire [15:0] l2t5_valid = `TB_TOP5.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 213 | wire [15:0] l2t5_dirty = `TB_TOP5.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 214 | wire [8:0] l2t5_vuad_index = `TB_TOP5.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 215 | wire l2t5_vuad_wr = `TB_TOP5.vuad.vuad_array_wr_en0_c3; | |
| 216 | ||
| 217 | wire l2t5_tagonly_hit = `TB_TOP5.tagctl.tag_hit_c2; | |
| 218 | ||
| 219 | ||
| 220 | //---------------------------------------------------------------------------------------- | |
| 221 | // Tag and VUAD update signals | |
| 222 | //---------------------------------------------------------------------------------------- | |
| 223 | ||
| 224 | wire [8:0] l2t6_tag_index = `TB_TOP6.tag.index0[8:0]; | |
| 225 | wire l2t6_wr_en = `TB_TOP6.tag.wr_en0; | |
| 226 | wire [15:0] l2t6_way = `TB_TOP6.tag.way[15:0]; | |
| 227 | wire [27:0] l2t6_wrdata = `TB_TOP6.tag.wrdata0[27:0]; | |
| 228 | wire [21:0] l2t6_tag = `TB_TOP6.tag.wrdata0[27:6]; | |
| 229 | ||
| 230 | wire [39:0] l2t6_addr = `TB_TOP6.arbadr.arbdp_addr_c2[39:0]; | |
| 231 | wire l2t6_inst_vld = `TB_TOP6.arb.arb_inst_vld_c2; | |
| 232 | wire [15:0] l2t6_used = `TB_TOP6.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 233 | wire [15:0] l2t6_alloc = `TB_TOP6.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 234 | wire [15:0] l2t6_valid = `TB_TOP6.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 235 | wire [15:0] l2t6_dirty = `TB_TOP6.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 236 | wire [8:0] l2t6_vuad_index = `TB_TOP6.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 237 | wire l2t6_vuad_wr = `TB_TOP6.vuad.vuad_array_wr_en0_c3; | |
| 238 | ||
| 239 | wire l2t6_tagonly_hit = `TB_TOP6.tagctl.tag_hit_c2; | |
| 240 | ||
| 241 | ||
| 242 | //---------------------------------------------------------------------------------------- | |
| 243 | // Tag and VUAD update signals | |
| 244 | //---------------------------------------------------------------------------------------- | |
| 245 | ||
| 246 | wire [8:0] l2t7_tag_index = `TB_TOP7.tag.index0[8:0]; | |
| 247 | wire l2t7_wr_en = `TB_TOP7.tag.wr_en0; | |
| 248 | wire [15:0] l2t7_way = `TB_TOP7.tag.way[15:0]; | |
| 249 | wire [27:0] l2t7_wrdata = `TB_TOP7.tag.wrdata0[27:0]; | |
| 250 | wire [21:0] l2t7_tag = `TB_TOP7.tag.wrdata0[27:6]; | |
| 251 | ||
| 252 | wire [39:0] l2t7_addr = `TB_TOP7.arbadr.arbdp_addr_c2[39:0]; | |
| 253 | wire l2t7_inst_vld = `TB_TOP7.arb.arb_inst_vld_c2; | |
| 254 | wire [15:0] l2t7_used = `TB_TOP7.usaloc.usaloc_vuad_array_wr_data_c4[70:55]; | |
| 255 | wire [15:0] l2t7_alloc = `TB_TOP7.usaloc.usaloc_vuad_array_wr_data_c4[54:39]; | |
| 256 | wire [15:0] l2t7_valid = `TB_TOP7.vlddir.vlddir_vuad_array_wr_data_c4[31:16]; | |
| 257 | wire [15:0] l2t7_dirty = `TB_TOP7.vlddir.vlddir_vuad_array_wr_data_c4[15:0]; | |
| 258 | wire [8:0] l2t7_vuad_index = `TB_TOP7.vuad.vuaddp_vuad_idx_c4[8:0]; | |
| 259 | wire l2t7_vuad_wr = `TB_TOP7.vuad.vuad_array_wr_en0_c3; | |
| 260 | ||
| 261 | wire l2t7_tagonly_hit = `TB_TOP7.tagctl.tag_hit_c2; | |
| 262 | ||
| 263 | ||
| 264 | ||
| 265 | //===================================================================== | |
| 266 | // Monitor to print out L2-DRAM RD/WR and RD Response | |
| 267 | //===================================================================== | |
| 268 | ||
| 269 | ||
| 270 | ||
| 271 | ||
| 272 | ||
| 273 | reg [8:0] l2t0_tag_index_c1, l2t0_tag_index_c2, l2t0_tag_index_c3, l2t0_tag_index_c4; | |
| 274 | reg l2t0_wr_en_c1, l2t0_wr_en_c2, l2t0_wr_en_c3, l2t0_wr_en_c4; | |
| 275 | reg [15:0] l2t0_way_c1, l2t0_way_c2, l2t0_way_c3, l2t0_way_c4; | |
| 276 | reg [21:0] l2t0_tag_c1, l2t0_tag_c2, l2t0_tag_c3, l2t0_tag_c4; | |
| 277 | ||
| 278 | reg [39:0] l2t0_addr_c3, l2t0_addr_c4; | |
| 279 | reg l2t0_inst_vld_c3, l2t0_inst_vld_c4; | |
| 280 | reg l2t0_tagonly_hit_c3, l2t0_tagonly_hit_c4; | |
| 281 | ||
| 282 | reg l2t0_vuad_wr_c4; | |
| 283 | ||
| 284 | reg [3:0] way_0; | |
| 285 | ||
| 286 | initial | |
| 287 | begin | |
| 288 | l2t0_tag_index_c1 = 0; | |
| 289 | l2t0_wr_en_c1 = 0; | |
| 290 | l2t0_way_c1 = 0; | |
| 291 | l2t0_tag_c1 = 0; | |
| 292 | l2t0_tag_index_c2 = 0; | |
| 293 | l2t0_wr_en_c2 = 0; | |
| 294 | l2t0_way_c2 = 0; | |
| 295 | l2t0_tag_c2 = 0; | |
| 296 | l2t0_tag_index_c3 = 0; | |
| 297 | l2t0_wr_en_c3 = 0; | |
| 298 | l2t0_way_c3 = 0; | |
| 299 | l2t0_tag_c3 = 0; | |
| 300 | l2t0_tag_index_c4 = 0; | |
| 301 | l2t0_wr_en_c4 = 0; | |
| 302 | l2t0_way_c4 = 0; | |
| 303 | l2t0_tag_c4 = 0; | |
| 304 | l2t0_addr_c3 = 0; | |
| 305 | l2t0_inst_vld_c3 = 0; | |
| 306 | l2t0_addr_c4 = 0; | |
| 307 | l2t0_inst_vld_c4 = 0; | |
| 308 | l2t0_vuad_wr_c4 = 0; | |
| 309 | end | |
| 310 | ||
| 311 | always @ (posedge cmp_clk) | |
| 312 | begin | |
| 313 | if (cmp_rst_l) begin | |
| 314 | ||
| 315 | l2t0_tag_index_c1 <= l2t0_tag_index ; | |
| 316 | l2t0_tag_index_c2 <= l2t0_tag_index_c1 ; | |
| 317 | l2t0_tag_index_c3 <= l2t0_tag_index_c2 ; | |
| 318 | l2t0_tag_index_c4 <= l2t0_tag_index_c3 ; | |
| 319 | ||
| 320 | l2t0_wr_en_c1 <= l2t0_wr_en; | |
| 321 | l2t0_wr_en_c2 <= l2t0_wr_en_c1; | |
| 322 | l2t0_wr_en_c3 <= l2t0_wr_en_c2; | |
| 323 | l2t0_wr_en_c4 <= l2t0_wr_en_c3; | |
| 324 | ||
| 325 | l2t0_way_c1 <= l2t0_way; | |
| 326 | l2t0_way_c2 <= l2t0_way_c1; | |
| 327 | l2t0_way_c3 <= l2t0_way_c2; | |
| 328 | l2t0_way_c4 <= l2t0_way_c3; | |
| 329 | ||
| 330 | l2t0_tag_c1 <= l2t0_tag; | |
| 331 | l2t0_tag_c2 <= l2t0_tag_c1; | |
| 332 | l2t0_tag_c3 <= l2t0_tag_c2; | |
| 333 | l2t0_tag_c4 <= l2t0_tag_c3; | |
| 334 | ||
| 335 | l2t0_addr_c3 <= l2t0_addr; | |
| 336 | l2t0_addr_c4 <= l2t0_addr_c3; | |
| 337 | ||
| 338 | l2t0_inst_vld_c3 <= l2t0_inst_vld; | |
| 339 | l2t0_inst_vld_c4 <= l2t0_inst_vld_c3; | |
| 340 | ||
| 341 | l2t0_tagonly_hit_c3 <= l2t0_tagonly_hit; | |
| 342 | l2t0_tagonly_hit_c4 <= l2t0_tagonly_hit_c3; | |
| 343 | ||
| 344 | l2t0_vuad_wr_c4 <= l2t0_vuad_wr; | |
| 345 | ||
| 346 | case (l2t0_way_c4) | |
| 347 | 16'h1: way_0 = 4'b0; | |
| 348 | 16'h2: way_0 = 4'h1; | |
| 349 | 16'h4: way_0 = 4'h2; | |
| 350 | 16'h8: way_0 = 4'h3; | |
| 351 | 16'h10: way_0 = 4'h4; | |
| 352 | 16'h20: way_0 = 4'h5; | |
| 353 | 16'h40: way_0 = 4'h6; | |
| 354 | 16'h80: way_0 = 4'h7; | |
| 355 | 16'h100: way_0 = 4'h8; | |
| 356 | 16'h200: way_0 = 4'h9; | |
| 357 | 16'h400: way_0 = 4'ha; | |
| 358 | 16'h800: way_0 = 4'hb; | |
| 359 | 16'h1000: way_0 = 4'hc; | |
| 360 | 16'h2000: way_0 = 4'hd; | |
| 361 | 16'h4000: way_0 = 4'he; | |
| 362 | 16'h8000: way_0 = 4'hf; | |
| 363 | endcase | |
| 364 | ||
| 365 | ||
| 366 | // VUAD write Req | |
| 367 | if (l2t0_vuad_wr_c4 ) begin | |
| 368 | // VUAD & Tag Write | |
| 369 | if (l2t0_wr_en_c4 ) begin | |
| 370 | if (l2t0_tag_index_c4 != l2t0_vuad_index) begin | |
| 371 | ||
| 372 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,0, l2t0_tagonly_hit_c4, l2t0_addr_c4, l2t0_tag_c4, l2t0_tag_index_c4, 0, way_0, l2t0_valid, l2t0_used, l2t0_alloc, l2t0_dirty); | |
| 373 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,0, l2t0_tag_index_c4, l2t0_vuad_index); | |
| 374 | /* | |
| 375 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,0, l2t0_addr_c4, l2t0_tag_c4, l2t0_tag_index_c4, 0, way_0, l2t0_valid, l2t0_used, l2t0_alloc, l2t0_dirty); | |
| 376 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,0, l2t0_tag_index_c4, l2t0_vuad_index); | |
| 377 | */ | |
| 378 | end else begin | |
| 379 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,0,l2t0_tagonly_hit_c4, l2t0_addr_c4, l2t0_tag_c4, l2t0_tag_index_c4, 0, way_0, l2t0_valid, l2t0_used, l2t0_alloc, l2t0_dirty); | |
| 380 | /* | |
| 381 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,0, l2t0_addr_c4, l2t0_tag_c4, l2t0_tag_index_c4, 0, way_0, l2t0_valid, l2t0_used, l2t0_alloc, l2t0_dirty); | |
| 382 | */ | |
| 383 | end | |
| 384 | end else begin | |
| 385 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,0, l2t0_tagonly_hit_c4, l2t0_addr_c4, l2t0_vuad_index, 0, l2t0_valid, l2t0_used, l2t0_alloc, l2t0_dirty); | |
| 386 | /* | |
| 387 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,0, l2t0_addr_c4, l2t0_vuad_index, 0, l2t0_valid, l2t0_used, l2t0_alloc, l2t0_dirty); | |
| 388 | */ | |
| 389 | end | |
| 390 | end | |
| 391 | ||
| 392 | end else begin | |
| 393 | if (!l2t0_vuad_wr_c4 && l2t0_wr_en_c4) begin | |
| 394 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,0,l2t0_tagonly_hit_c4, l2t0_addr_c4, l2t0_tag_c4, l2t0_tag_index_c4, 0, way_0); | |
| 395 | /* | |
| 396 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,0, l2t0_addr_c4, l2t0_tag_c4, l2t0_tag_index_c4, 0, way_0); | |
| 397 | */ | |
| 398 | end | |
| 399 | end | |
| 400 | ||
| 401 | end | |
| 402 | ||
| 403 | ||
| 404 | ||
| 405 | ||
| 406 | reg [8:0] l2t1_tag_index_c1, l2t1_tag_index_c2, l2t1_tag_index_c3, l2t1_tag_index_c4; | |
| 407 | reg l2t1_wr_en_c1, l2t1_wr_en_c2, l2t1_wr_en_c3, l2t1_wr_en_c4; | |
| 408 | reg [15:0] l2t1_way_c1, l2t1_way_c2, l2t1_way_c3, l2t1_way_c4; | |
| 409 | reg [21:0] l2t1_tag_c1, l2t1_tag_c2, l2t1_tag_c3, l2t1_tag_c4; | |
| 410 | ||
| 411 | reg [39:0] l2t1_addr_c3, l2t1_addr_c4; | |
| 412 | reg l2t1_inst_vld_c3, l2t1_inst_vld_c4; | |
| 413 | reg l2t1_tagonly_hit_c3, l2t1_tagonly_hit_c4; | |
| 414 | ||
| 415 | reg l2t1_vuad_wr_c4; | |
| 416 | ||
| 417 | reg [3:0] way_1; | |
| 418 | ||
| 419 | initial | |
| 420 | begin | |
| 421 | l2t1_tag_index_c1 = 0; | |
| 422 | l2t1_wr_en_c1 = 0; | |
| 423 | l2t1_way_c1 = 0; | |
| 424 | l2t1_tag_c1 = 0; | |
| 425 | l2t1_tag_index_c2 = 0; | |
| 426 | l2t1_wr_en_c2 = 0; | |
| 427 | l2t1_way_c2 = 0; | |
| 428 | l2t1_tag_c2 = 0; | |
| 429 | l2t1_tag_index_c3 = 0; | |
| 430 | l2t1_wr_en_c3 = 0; | |
| 431 | l2t1_way_c3 = 0; | |
| 432 | l2t1_tag_c3 = 0; | |
| 433 | l2t1_tag_index_c4 = 0; | |
| 434 | l2t1_wr_en_c4 = 0; | |
| 435 | l2t1_way_c4 = 0; | |
| 436 | l2t1_tag_c4 = 0; | |
| 437 | l2t1_addr_c3 = 0; | |
| 438 | l2t1_inst_vld_c3 = 0; | |
| 439 | l2t1_addr_c4 = 0; | |
| 440 | l2t1_inst_vld_c4 = 0; | |
| 441 | l2t1_vuad_wr_c4 = 0; | |
| 442 | end | |
| 443 | ||
| 444 | always @ (posedge cmp_clk) | |
| 445 | begin | |
| 446 | if (cmp_rst_l) begin | |
| 447 | ||
| 448 | l2t1_tag_index_c1 <= l2t1_tag_index ; | |
| 449 | l2t1_tag_index_c2 <= l2t1_tag_index_c1 ; | |
| 450 | l2t1_tag_index_c3 <= l2t1_tag_index_c2 ; | |
| 451 | l2t1_tag_index_c4 <= l2t1_tag_index_c3 ; | |
| 452 | ||
| 453 | l2t1_wr_en_c1 <= l2t1_wr_en; | |
| 454 | l2t1_wr_en_c2 <= l2t1_wr_en_c1; | |
| 455 | l2t1_wr_en_c3 <= l2t1_wr_en_c2; | |
| 456 | l2t1_wr_en_c4 <= l2t1_wr_en_c3; | |
| 457 | ||
| 458 | l2t1_way_c1 <= l2t1_way; | |
| 459 | l2t1_way_c2 <= l2t1_way_c1; | |
| 460 | l2t1_way_c3 <= l2t1_way_c2; | |
| 461 | l2t1_way_c4 <= l2t1_way_c3; | |
| 462 | ||
| 463 | l2t1_tag_c1 <= l2t1_tag; | |
| 464 | l2t1_tag_c2 <= l2t1_tag_c1; | |
| 465 | l2t1_tag_c3 <= l2t1_tag_c2; | |
| 466 | l2t1_tag_c4 <= l2t1_tag_c3; | |
| 467 | ||
| 468 | l2t1_addr_c3 <= l2t1_addr; | |
| 469 | l2t1_addr_c4 <= l2t1_addr_c3; | |
| 470 | ||
| 471 | l2t1_inst_vld_c3 <= l2t1_inst_vld; | |
| 472 | l2t1_inst_vld_c4 <= l2t1_inst_vld_c3; | |
| 473 | ||
| 474 | l2t1_tagonly_hit_c3 <= l2t1_tagonly_hit; | |
| 475 | l2t1_tagonly_hit_c4 <= l2t1_tagonly_hit_c3; | |
| 476 | ||
| 477 | l2t1_vuad_wr_c4 <= l2t1_vuad_wr; | |
| 478 | ||
| 479 | case (l2t1_way_c4) | |
| 480 | 16'h1: way_1 = 4'b0; | |
| 481 | 16'h2: way_1 = 4'h1; | |
| 482 | 16'h4: way_1 = 4'h2; | |
| 483 | 16'h8: way_1 = 4'h3; | |
| 484 | 16'h10: way_1 = 4'h4; | |
| 485 | 16'h20: way_1 = 4'h5; | |
| 486 | 16'h40: way_1 = 4'h6; | |
| 487 | 16'h80: way_1 = 4'h7; | |
| 488 | 16'h100: way_1 = 4'h8; | |
| 489 | 16'h200: way_1 = 4'h9; | |
| 490 | 16'h400: way_1 = 4'ha; | |
| 491 | 16'h800: way_1 = 4'hb; | |
| 492 | 16'h1000: way_1 = 4'hc; | |
| 493 | 16'h2000: way_1 = 4'hd; | |
| 494 | 16'h4000: way_1 = 4'he; | |
| 495 | 16'h8000: way_1 = 4'hf; | |
| 496 | endcase | |
| 497 | ||
| 498 | ||
| 499 | // VUAD write Req | |
| 500 | if (l2t1_vuad_wr_c4 ) begin | |
| 501 | // VUAD & Tag Write | |
| 502 | if (l2t1_wr_en_c4 ) begin | |
| 503 | if (l2t1_tag_index_c4 != l2t1_vuad_index) begin | |
| 504 | ||
| 505 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,1, l2t1_tagonly_hit_c4, l2t1_addr_c4, l2t1_tag_c4, l2t1_tag_index_c4, 1, way_1, l2t1_valid, l2t1_used, l2t1_alloc, l2t1_dirty); | |
| 506 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,1, l2t1_tag_index_c4, l2t1_vuad_index); | |
| 507 | /* | |
| 508 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,1, l2t1_addr_c4, l2t1_tag_c4, l2t1_tag_index_c4, 1, way_1, l2t1_valid, l2t1_used, l2t1_alloc, l2t1_dirty); | |
| 509 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,1, l2t1_tag_index_c4, l2t1_vuad_index); | |
| 510 | */ | |
| 511 | end else begin | |
| 512 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,1,l2t1_tagonly_hit_c4, l2t1_addr_c4, l2t1_tag_c4, l2t1_tag_index_c4, 1, way_1, l2t1_valid, l2t1_used, l2t1_alloc, l2t1_dirty); | |
| 513 | /* | |
| 514 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,1, l2t1_addr_c4, l2t1_tag_c4, l2t1_tag_index_c4, 1, way_1, l2t1_valid, l2t1_used, l2t1_alloc, l2t1_dirty); | |
| 515 | */ | |
| 516 | end | |
| 517 | end else begin | |
| 518 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,1, l2t1_tagonly_hit_c4, l2t1_addr_c4, l2t1_vuad_index, 1, l2t1_valid, l2t1_used, l2t1_alloc, l2t1_dirty); | |
| 519 | /* | |
| 520 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,1, l2t1_addr_c4, l2t1_vuad_index, 1, l2t1_valid, l2t1_used, l2t1_alloc, l2t1_dirty); | |
| 521 | */ | |
| 522 | end | |
| 523 | end | |
| 524 | ||
| 525 | end else begin | |
| 526 | if (!l2t1_vuad_wr_c4 && l2t1_wr_en_c4) begin | |
| 527 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,1,l2t1_tagonly_hit_c4, l2t1_addr_c4, l2t1_tag_c4, l2t1_tag_index_c4, 1, way_1); | |
| 528 | /* | |
| 529 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,1, l2t1_addr_c4, l2t1_tag_c4, l2t1_tag_index_c4, 1, way_1); | |
| 530 | */ | |
| 531 | end | |
| 532 | end | |
| 533 | ||
| 534 | end | |
| 535 | ||
| 536 | ||
| 537 | ||
| 538 | ||
| 539 | reg [8:0] l2t2_tag_index_c1, l2t2_tag_index_c2, l2t2_tag_index_c3, l2t2_tag_index_c4; | |
| 540 | reg l2t2_wr_en_c1, l2t2_wr_en_c2, l2t2_wr_en_c3, l2t2_wr_en_c4; | |
| 541 | reg [15:0] l2t2_way_c1, l2t2_way_c2, l2t2_way_c3, l2t2_way_c4; | |
| 542 | reg [21:0] l2t2_tag_c1, l2t2_tag_c2, l2t2_tag_c3, l2t2_tag_c4; | |
| 543 | ||
| 544 | reg [39:0] l2t2_addr_c3, l2t2_addr_c4; | |
| 545 | reg l2t2_inst_vld_c3, l2t2_inst_vld_c4; | |
| 546 | reg l2t2_tagonly_hit_c3, l2t2_tagonly_hit_c4; | |
| 547 | ||
| 548 | reg l2t2_vuad_wr_c4; | |
| 549 | ||
| 550 | reg [3:0] way_2; | |
| 551 | ||
| 552 | initial | |
| 553 | begin | |
| 554 | l2t2_tag_index_c1 = 0; | |
| 555 | l2t2_wr_en_c1 = 0; | |
| 556 | l2t2_way_c1 = 0; | |
| 557 | l2t2_tag_c1 = 0; | |
| 558 | l2t2_tag_index_c2 = 0; | |
| 559 | l2t2_wr_en_c2 = 0; | |
| 560 | l2t2_way_c2 = 0; | |
| 561 | l2t2_tag_c2 = 0; | |
| 562 | l2t2_tag_index_c3 = 0; | |
| 563 | l2t2_wr_en_c3 = 0; | |
| 564 | l2t2_way_c3 = 0; | |
| 565 | l2t2_tag_c3 = 0; | |
| 566 | l2t2_tag_index_c4 = 0; | |
| 567 | l2t2_wr_en_c4 = 0; | |
| 568 | l2t2_way_c4 = 0; | |
| 569 | l2t2_tag_c4 = 0; | |
| 570 | l2t2_addr_c3 = 0; | |
| 571 | l2t2_inst_vld_c3 = 0; | |
| 572 | l2t2_addr_c4 = 0; | |
| 573 | l2t2_inst_vld_c4 = 0; | |
| 574 | l2t2_vuad_wr_c4 = 0; | |
| 575 | end | |
| 576 | ||
| 577 | always @ (posedge cmp_clk) | |
| 578 | begin | |
| 579 | if (cmp_rst_l) begin | |
| 580 | ||
| 581 | l2t2_tag_index_c1 <= l2t2_tag_index ; | |
| 582 | l2t2_tag_index_c2 <= l2t2_tag_index_c1 ; | |
| 583 | l2t2_tag_index_c3 <= l2t2_tag_index_c2 ; | |
| 584 | l2t2_tag_index_c4 <= l2t2_tag_index_c3 ; | |
| 585 | ||
| 586 | l2t2_wr_en_c1 <= l2t2_wr_en; | |
| 587 | l2t2_wr_en_c2 <= l2t2_wr_en_c1; | |
| 588 | l2t2_wr_en_c3 <= l2t2_wr_en_c2; | |
| 589 | l2t2_wr_en_c4 <= l2t2_wr_en_c3; | |
| 590 | ||
| 591 | l2t2_way_c1 <= l2t2_way; | |
| 592 | l2t2_way_c2 <= l2t2_way_c1; | |
| 593 | l2t2_way_c3 <= l2t2_way_c2; | |
| 594 | l2t2_way_c4 <= l2t2_way_c3; | |
| 595 | ||
| 596 | l2t2_tag_c1 <= l2t2_tag; | |
| 597 | l2t2_tag_c2 <= l2t2_tag_c1; | |
| 598 | l2t2_tag_c3 <= l2t2_tag_c2; | |
| 599 | l2t2_tag_c4 <= l2t2_tag_c3; | |
| 600 | ||
| 601 | l2t2_addr_c3 <= l2t2_addr; | |
| 602 | l2t2_addr_c4 <= l2t2_addr_c3; | |
| 603 | ||
| 604 | l2t2_inst_vld_c3 <= l2t2_inst_vld; | |
| 605 | l2t2_inst_vld_c4 <= l2t2_inst_vld_c3; | |
| 606 | ||
| 607 | l2t2_tagonly_hit_c3 <= l2t2_tagonly_hit; | |
| 608 | l2t2_tagonly_hit_c4 <= l2t2_tagonly_hit_c3; | |
| 609 | ||
| 610 | l2t2_vuad_wr_c4 <= l2t2_vuad_wr; | |
| 611 | ||
| 612 | case (l2t2_way_c4) | |
| 613 | 16'h1: way_2 = 4'b0; | |
| 614 | 16'h2: way_2 = 4'h1; | |
| 615 | 16'h4: way_2 = 4'h2; | |
| 616 | 16'h8: way_2 = 4'h3; | |
| 617 | 16'h10: way_2 = 4'h4; | |
| 618 | 16'h20: way_2 = 4'h5; | |
| 619 | 16'h40: way_2 = 4'h6; | |
| 620 | 16'h80: way_2 = 4'h7; | |
| 621 | 16'h100: way_2 = 4'h8; | |
| 622 | 16'h200: way_2 = 4'h9; | |
| 623 | 16'h400: way_2 = 4'ha; | |
| 624 | 16'h800: way_2 = 4'hb; | |
| 625 | 16'h1000: way_2 = 4'hc; | |
| 626 | 16'h2000: way_2 = 4'hd; | |
| 627 | 16'h4000: way_2 = 4'he; | |
| 628 | 16'h8000: way_2 = 4'hf; | |
| 629 | endcase | |
| 630 | ||
| 631 | ||
| 632 | // VUAD write Req | |
| 633 | if (l2t2_vuad_wr_c4 ) begin | |
| 634 | // VUAD & Tag Write | |
| 635 | if (l2t2_wr_en_c4 ) begin | |
| 636 | if (l2t2_tag_index_c4 != l2t2_vuad_index) begin | |
| 637 | ||
| 638 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,2, l2t2_tagonly_hit_c4, l2t2_addr_c4, l2t2_tag_c4, l2t2_tag_index_c4, 2, way_2, l2t2_valid, l2t2_used, l2t2_alloc, l2t2_dirty); | |
| 639 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,2, l2t2_tag_index_c4, l2t2_vuad_index); | |
| 640 | /* | |
| 641 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,2, l2t2_addr_c4, l2t2_tag_c4, l2t2_tag_index_c4, 2, way_2, l2t2_valid, l2t2_used, l2t2_alloc, l2t2_dirty); | |
| 642 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,2, l2t2_tag_index_c4, l2t2_vuad_index); | |
| 643 | */ | |
| 644 | end else begin | |
| 645 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,2,l2t2_tagonly_hit_c4, l2t2_addr_c4, l2t2_tag_c4, l2t2_tag_index_c4, 2, way_2, l2t2_valid, l2t2_used, l2t2_alloc, l2t2_dirty); | |
| 646 | /* | |
| 647 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,2, l2t2_addr_c4, l2t2_tag_c4, l2t2_tag_index_c4, 2, way_2, l2t2_valid, l2t2_used, l2t2_alloc, l2t2_dirty); | |
| 648 | */ | |
| 649 | end | |
| 650 | end else begin | |
| 651 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,2, l2t2_tagonly_hit_c4, l2t2_addr_c4, l2t2_vuad_index, 2, l2t2_valid, l2t2_used, l2t2_alloc, l2t2_dirty); | |
| 652 | /* | |
| 653 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,2, l2t2_addr_c4, l2t2_vuad_index, 2, l2t2_valid, l2t2_used, l2t2_alloc, l2t2_dirty); | |
| 654 | */ | |
| 655 | end | |
| 656 | end | |
| 657 | ||
| 658 | end else begin | |
| 659 | if (!l2t2_vuad_wr_c4 && l2t2_wr_en_c4) begin | |
| 660 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,2,l2t2_tagonly_hit_c4, l2t2_addr_c4, l2t2_tag_c4, l2t2_tag_index_c4, 2, way_2); | |
| 661 | /* | |
| 662 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,2, l2t2_addr_c4, l2t2_tag_c4, l2t2_tag_index_c4, 2, way_2); | |
| 663 | */ | |
| 664 | end | |
| 665 | end | |
| 666 | ||
| 667 | end | |
| 668 | ||
| 669 | ||
| 670 | ||
| 671 | ||
| 672 | reg [8:0] l2t3_tag_index_c1, l2t3_tag_index_c2, l2t3_tag_index_c3, l2t3_tag_index_c4; | |
| 673 | reg l2t3_wr_en_c1, l2t3_wr_en_c2, l2t3_wr_en_c3, l2t3_wr_en_c4; | |
| 674 | reg [15:0] l2t3_way_c1, l2t3_way_c2, l2t3_way_c3, l2t3_way_c4; | |
| 675 | reg [21:0] l2t3_tag_c1, l2t3_tag_c2, l2t3_tag_c3, l2t3_tag_c4; | |
| 676 | ||
| 677 | reg [39:0] l2t3_addr_c3, l2t3_addr_c4; | |
| 678 | reg l2t3_inst_vld_c3, l2t3_inst_vld_c4; | |
| 679 | reg l2t3_tagonly_hit_c3, l2t3_tagonly_hit_c4; | |
| 680 | ||
| 681 | reg l2t3_vuad_wr_c4; | |
| 682 | ||
| 683 | reg [3:0] way_3; | |
| 684 | ||
| 685 | initial | |
| 686 | begin | |
| 687 | l2t3_tag_index_c1 = 0; | |
| 688 | l2t3_wr_en_c1 = 0; | |
| 689 | l2t3_way_c1 = 0; | |
| 690 | l2t3_tag_c1 = 0; | |
| 691 | l2t3_tag_index_c2 = 0; | |
| 692 | l2t3_wr_en_c2 = 0; | |
| 693 | l2t3_way_c2 = 0; | |
| 694 | l2t3_tag_c2 = 0; | |
| 695 | l2t3_tag_index_c3 = 0; | |
| 696 | l2t3_wr_en_c3 = 0; | |
| 697 | l2t3_way_c3 = 0; | |
| 698 | l2t3_tag_c3 = 0; | |
| 699 | l2t3_tag_index_c4 = 0; | |
| 700 | l2t3_wr_en_c4 = 0; | |
| 701 | l2t3_way_c4 = 0; | |
| 702 | l2t3_tag_c4 = 0; | |
| 703 | l2t3_addr_c3 = 0; | |
| 704 | l2t3_inst_vld_c3 = 0; | |
| 705 | l2t3_addr_c4 = 0; | |
| 706 | l2t3_inst_vld_c4 = 0; | |
| 707 | l2t3_vuad_wr_c4 = 0; | |
| 708 | end | |
| 709 | ||
| 710 | always @ (posedge cmp_clk) | |
| 711 | begin | |
| 712 | if (cmp_rst_l) begin | |
| 713 | ||
| 714 | l2t3_tag_index_c1 <= l2t3_tag_index ; | |
| 715 | l2t3_tag_index_c2 <= l2t3_tag_index_c1 ; | |
| 716 | l2t3_tag_index_c3 <= l2t3_tag_index_c2 ; | |
| 717 | l2t3_tag_index_c4 <= l2t3_tag_index_c3 ; | |
| 718 | ||
| 719 | l2t3_wr_en_c1 <= l2t3_wr_en; | |
| 720 | l2t3_wr_en_c2 <= l2t3_wr_en_c1; | |
| 721 | l2t3_wr_en_c3 <= l2t3_wr_en_c2; | |
| 722 | l2t3_wr_en_c4 <= l2t3_wr_en_c3; | |
| 723 | ||
| 724 | l2t3_way_c1 <= l2t3_way; | |
| 725 | l2t3_way_c2 <= l2t3_way_c1; | |
| 726 | l2t3_way_c3 <= l2t3_way_c2; | |
| 727 | l2t3_way_c4 <= l2t3_way_c3; | |
| 728 | ||
| 729 | l2t3_tag_c1 <= l2t3_tag; | |
| 730 | l2t3_tag_c2 <= l2t3_tag_c1; | |
| 731 | l2t3_tag_c3 <= l2t3_tag_c2; | |
| 732 | l2t3_tag_c4 <= l2t3_tag_c3; | |
| 733 | ||
| 734 | l2t3_addr_c3 <= l2t3_addr; | |
| 735 | l2t3_addr_c4 <= l2t3_addr_c3; | |
| 736 | ||
| 737 | l2t3_inst_vld_c3 <= l2t3_inst_vld; | |
| 738 | l2t3_inst_vld_c4 <= l2t3_inst_vld_c3; | |
| 739 | ||
| 740 | l2t3_tagonly_hit_c3 <= l2t3_tagonly_hit; | |
| 741 | l2t3_tagonly_hit_c4 <= l2t3_tagonly_hit_c3; | |
| 742 | ||
| 743 | l2t3_vuad_wr_c4 <= l2t3_vuad_wr; | |
| 744 | ||
| 745 | case (l2t3_way_c4) | |
| 746 | 16'h1: way_3 = 4'b0; | |
| 747 | 16'h2: way_3 = 4'h1; | |
| 748 | 16'h4: way_3 = 4'h2; | |
| 749 | 16'h8: way_3 = 4'h3; | |
| 750 | 16'h10: way_3 = 4'h4; | |
| 751 | 16'h20: way_3 = 4'h5; | |
| 752 | 16'h40: way_3 = 4'h6; | |
| 753 | 16'h80: way_3 = 4'h7; | |
| 754 | 16'h100: way_3 = 4'h8; | |
| 755 | 16'h200: way_3 = 4'h9; | |
| 756 | 16'h400: way_3 = 4'ha; | |
| 757 | 16'h800: way_3 = 4'hb; | |
| 758 | 16'h1000: way_3 = 4'hc; | |
| 759 | 16'h2000: way_3 = 4'hd; | |
| 760 | 16'h4000: way_3 = 4'he; | |
| 761 | 16'h8000: way_3 = 4'hf; | |
| 762 | endcase | |
| 763 | ||
| 764 | ||
| 765 | // VUAD write Req | |
| 766 | if (l2t3_vuad_wr_c4 ) begin | |
| 767 | // VUAD & Tag Write | |
| 768 | if (l2t3_wr_en_c4 ) begin | |
| 769 | if (l2t3_tag_index_c4 != l2t3_vuad_index) begin | |
| 770 | ||
| 771 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,3, l2t3_tagonly_hit_c4, l2t3_addr_c4, l2t3_tag_c4, l2t3_tag_index_c4, 3, way_3, l2t3_valid, l2t3_used, l2t3_alloc, l2t3_dirty); | |
| 772 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,3, l2t3_tag_index_c4, l2t3_vuad_index); | |
| 773 | /* | |
| 774 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,3, l2t3_addr_c4, l2t3_tag_c4, l2t3_tag_index_c4, 3, way_3, l2t3_valid, l2t3_used, l2t3_alloc, l2t3_dirty); | |
| 775 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,3, l2t3_tag_index_c4, l2t3_vuad_index); | |
| 776 | */ | |
| 777 | end else begin | |
| 778 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,3,l2t3_tagonly_hit_c4, l2t3_addr_c4, l2t3_tag_c4, l2t3_tag_index_c4, 3, way_3, l2t3_valid, l2t3_used, l2t3_alloc, l2t3_dirty); | |
| 779 | /* | |
| 780 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,3, l2t3_addr_c4, l2t3_tag_c4, l2t3_tag_index_c4, 3, way_3, l2t3_valid, l2t3_used, l2t3_alloc, l2t3_dirty); | |
| 781 | */ | |
| 782 | end | |
| 783 | end else begin | |
| 784 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,3, l2t3_tagonly_hit_c4, l2t3_addr_c4, l2t3_vuad_index, 3, l2t3_valid, l2t3_used, l2t3_alloc, l2t3_dirty); | |
| 785 | /* | |
| 786 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,3, l2t3_addr_c4, l2t3_vuad_index, 3, l2t3_valid, l2t3_used, l2t3_alloc, l2t3_dirty); | |
| 787 | */ | |
| 788 | end | |
| 789 | end | |
| 790 | ||
| 791 | end else begin | |
| 792 | if (!l2t3_vuad_wr_c4 && l2t3_wr_en_c4) begin | |
| 793 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,3,l2t3_tagonly_hit_c4, l2t3_addr_c4, l2t3_tag_c4, l2t3_tag_index_c4, 3, way_3); | |
| 794 | /* | |
| 795 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,3, l2t3_addr_c4, l2t3_tag_c4, l2t3_tag_index_c4, 3, way_3); | |
| 796 | */ | |
| 797 | end | |
| 798 | end | |
| 799 | ||
| 800 | end | |
| 801 | ||
| 802 | ||
| 803 | ||
| 804 | ||
| 805 | reg [8:0] l2t4_tag_index_c1, l2t4_tag_index_c2, l2t4_tag_index_c3, l2t4_tag_index_c4; | |
| 806 | reg l2t4_wr_en_c1, l2t4_wr_en_c2, l2t4_wr_en_c3, l2t4_wr_en_c4; | |
| 807 | reg [15:0] l2t4_way_c1, l2t4_way_c2, l2t4_way_c3, l2t4_way_c4; | |
| 808 | reg [21:0] l2t4_tag_c1, l2t4_tag_c2, l2t4_tag_c3, l2t4_tag_c4; | |
| 809 | ||
| 810 | reg [39:0] l2t4_addr_c3, l2t4_addr_c4; | |
| 811 | reg l2t4_inst_vld_c3, l2t4_inst_vld_c4; | |
| 812 | reg l2t4_tagonly_hit_c3, l2t4_tagonly_hit_c4; | |
| 813 | ||
| 814 | reg l2t4_vuad_wr_c4; | |
| 815 | ||
| 816 | reg [3:0] way_4; | |
| 817 | ||
| 818 | initial | |
| 819 | begin | |
| 820 | l2t4_tag_index_c1 = 0; | |
| 821 | l2t4_wr_en_c1 = 0; | |
| 822 | l2t4_way_c1 = 0; | |
| 823 | l2t4_tag_c1 = 0; | |
| 824 | l2t4_tag_index_c2 = 0; | |
| 825 | l2t4_wr_en_c2 = 0; | |
| 826 | l2t4_way_c2 = 0; | |
| 827 | l2t4_tag_c2 = 0; | |
| 828 | l2t4_tag_index_c3 = 0; | |
| 829 | l2t4_wr_en_c3 = 0; | |
| 830 | l2t4_way_c3 = 0; | |
| 831 | l2t4_tag_c3 = 0; | |
| 832 | l2t4_tag_index_c4 = 0; | |
| 833 | l2t4_wr_en_c4 = 0; | |
| 834 | l2t4_way_c4 = 0; | |
| 835 | l2t4_tag_c4 = 0; | |
| 836 | l2t4_addr_c3 = 0; | |
| 837 | l2t4_inst_vld_c3 = 0; | |
| 838 | l2t4_addr_c4 = 0; | |
| 839 | l2t4_inst_vld_c4 = 0; | |
| 840 | l2t4_vuad_wr_c4 = 0; | |
| 841 | end | |
| 842 | ||
| 843 | always @ (posedge cmp_clk) | |
| 844 | begin | |
| 845 | if (cmp_rst_l) begin | |
| 846 | ||
| 847 | l2t4_tag_index_c1 <= l2t4_tag_index ; | |
| 848 | l2t4_tag_index_c2 <= l2t4_tag_index_c1 ; | |
| 849 | l2t4_tag_index_c3 <= l2t4_tag_index_c2 ; | |
| 850 | l2t4_tag_index_c4 <= l2t4_tag_index_c3 ; | |
| 851 | ||
| 852 | l2t4_wr_en_c1 <= l2t4_wr_en; | |
| 853 | l2t4_wr_en_c2 <= l2t4_wr_en_c1; | |
| 854 | l2t4_wr_en_c3 <= l2t4_wr_en_c2; | |
| 855 | l2t4_wr_en_c4 <= l2t4_wr_en_c3; | |
| 856 | ||
| 857 | l2t4_way_c1 <= l2t4_way; | |
| 858 | l2t4_way_c2 <= l2t4_way_c1; | |
| 859 | l2t4_way_c3 <= l2t4_way_c2; | |
| 860 | l2t4_way_c4 <= l2t4_way_c3; | |
| 861 | ||
| 862 | l2t4_tag_c1 <= l2t4_tag; | |
| 863 | l2t4_tag_c2 <= l2t4_tag_c1; | |
| 864 | l2t4_tag_c3 <= l2t4_tag_c2; | |
| 865 | l2t4_tag_c4 <= l2t4_tag_c3; | |
| 866 | ||
| 867 | l2t4_addr_c3 <= l2t4_addr; | |
| 868 | l2t4_addr_c4 <= l2t4_addr_c3; | |
| 869 | ||
| 870 | l2t4_inst_vld_c3 <= l2t4_inst_vld; | |
| 871 | l2t4_inst_vld_c4 <= l2t4_inst_vld_c3; | |
| 872 | ||
| 873 | l2t4_tagonly_hit_c3 <= l2t4_tagonly_hit; | |
| 874 | l2t4_tagonly_hit_c4 <= l2t4_tagonly_hit_c3; | |
| 875 | ||
| 876 | l2t4_vuad_wr_c4 <= l2t4_vuad_wr; | |
| 877 | ||
| 878 | case (l2t4_way_c4) | |
| 879 | 16'h1: way_4 = 4'b0; | |
| 880 | 16'h2: way_4 = 4'h1; | |
| 881 | 16'h4: way_4 = 4'h2; | |
| 882 | 16'h8: way_4 = 4'h3; | |
| 883 | 16'h10: way_4 = 4'h4; | |
| 884 | 16'h20: way_4 = 4'h5; | |
| 885 | 16'h40: way_4 = 4'h6; | |
| 886 | 16'h80: way_4 = 4'h7; | |
| 887 | 16'h100: way_4 = 4'h8; | |
| 888 | 16'h200: way_4 = 4'h9; | |
| 889 | 16'h400: way_4 = 4'ha; | |
| 890 | 16'h800: way_4 = 4'hb; | |
| 891 | 16'h1000: way_4 = 4'hc; | |
| 892 | 16'h2000: way_4 = 4'hd; | |
| 893 | 16'h4000: way_4 = 4'he; | |
| 894 | 16'h8000: way_4 = 4'hf; | |
| 895 | endcase | |
| 896 | ||
| 897 | ||
| 898 | // VUAD write Req | |
| 899 | if (l2t4_vuad_wr_c4 ) begin | |
| 900 | // VUAD & Tag Write | |
| 901 | if (l2t4_wr_en_c4 ) begin | |
| 902 | if (l2t4_tag_index_c4 != l2t4_vuad_index) begin | |
| 903 | ||
| 904 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,4, l2t4_tagonly_hit_c4, l2t4_addr_c4, l2t4_tag_c4, l2t4_tag_index_c4, 4, way_4, l2t4_valid, l2t4_used, l2t4_alloc, l2t4_dirty); | |
| 905 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,4, l2t4_tag_index_c4, l2t4_vuad_index); | |
| 906 | /* | |
| 907 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,4, l2t4_addr_c4, l2t4_tag_c4, l2t4_tag_index_c4, 4, way_4, l2t4_valid, l2t4_used, l2t4_alloc, l2t4_dirty); | |
| 908 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,4, l2t4_tag_index_c4, l2t4_vuad_index); | |
| 909 | */ | |
| 910 | end else begin | |
| 911 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,4,l2t4_tagonly_hit_c4, l2t4_addr_c4, l2t4_tag_c4, l2t4_tag_index_c4, 4, way_4, l2t4_valid, l2t4_used, l2t4_alloc, l2t4_dirty); | |
| 912 | /* | |
| 913 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,4, l2t4_addr_c4, l2t4_tag_c4, l2t4_tag_index_c4, 4, way_4, l2t4_valid, l2t4_used, l2t4_alloc, l2t4_dirty); | |
| 914 | */ | |
| 915 | end | |
| 916 | end else begin | |
| 917 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,4, l2t4_tagonly_hit_c4, l2t4_addr_c4, l2t4_vuad_index, 4, l2t4_valid, l2t4_used, l2t4_alloc, l2t4_dirty); | |
| 918 | /* | |
| 919 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,4, l2t4_addr_c4, l2t4_vuad_index, 4, l2t4_valid, l2t4_used, l2t4_alloc, l2t4_dirty); | |
| 920 | */ | |
| 921 | end | |
| 922 | end | |
| 923 | ||
| 924 | end else begin | |
| 925 | if (!l2t4_vuad_wr_c4 && l2t4_wr_en_c4) begin | |
| 926 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,4,l2t4_tagonly_hit_c4, l2t4_addr_c4, l2t4_tag_c4, l2t4_tag_index_c4, 4, way_4); | |
| 927 | /* | |
| 928 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,4, l2t4_addr_c4, l2t4_tag_c4, l2t4_tag_index_c4, 4, way_4); | |
| 929 | */ | |
| 930 | end | |
| 931 | end | |
| 932 | ||
| 933 | end | |
| 934 | ||
| 935 | ||
| 936 | ||
| 937 | ||
| 938 | reg [8:0] l2t5_tag_index_c1, l2t5_tag_index_c2, l2t5_tag_index_c3, l2t5_tag_index_c4; | |
| 939 | reg l2t5_wr_en_c1, l2t5_wr_en_c2, l2t5_wr_en_c3, l2t5_wr_en_c4; | |
| 940 | reg [15:0] l2t5_way_c1, l2t5_way_c2, l2t5_way_c3, l2t5_way_c4; | |
| 941 | reg [21:0] l2t5_tag_c1, l2t5_tag_c2, l2t5_tag_c3, l2t5_tag_c4; | |
| 942 | ||
| 943 | reg [39:0] l2t5_addr_c3, l2t5_addr_c4; | |
| 944 | reg l2t5_inst_vld_c3, l2t5_inst_vld_c4; | |
| 945 | reg l2t5_tagonly_hit_c3, l2t5_tagonly_hit_c4; | |
| 946 | ||
| 947 | reg l2t5_vuad_wr_c4; | |
| 948 | ||
| 949 | reg [3:0] way_5; | |
| 950 | ||
| 951 | initial | |
| 952 | begin | |
| 953 | l2t5_tag_index_c1 = 0; | |
| 954 | l2t5_wr_en_c1 = 0; | |
| 955 | l2t5_way_c1 = 0; | |
| 956 | l2t5_tag_c1 = 0; | |
| 957 | l2t5_tag_index_c2 = 0; | |
| 958 | l2t5_wr_en_c2 = 0; | |
| 959 | l2t5_way_c2 = 0; | |
| 960 | l2t5_tag_c2 = 0; | |
| 961 | l2t5_tag_index_c3 = 0; | |
| 962 | l2t5_wr_en_c3 = 0; | |
| 963 | l2t5_way_c3 = 0; | |
| 964 | l2t5_tag_c3 = 0; | |
| 965 | l2t5_tag_index_c4 = 0; | |
| 966 | l2t5_wr_en_c4 = 0; | |
| 967 | l2t5_way_c4 = 0; | |
| 968 | l2t5_tag_c4 = 0; | |
| 969 | l2t5_addr_c3 = 0; | |
| 970 | l2t5_inst_vld_c3 = 0; | |
| 971 | l2t5_addr_c4 = 0; | |
| 972 | l2t5_inst_vld_c4 = 0; | |
| 973 | l2t5_vuad_wr_c4 = 0; | |
| 974 | end | |
| 975 | ||
| 976 | always @ (posedge cmp_clk) | |
| 977 | begin | |
| 978 | if (cmp_rst_l) begin | |
| 979 | ||
| 980 | l2t5_tag_index_c1 <= l2t5_tag_index ; | |
| 981 | l2t5_tag_index_c2 <= l2t5_tag_index_c1 ; | |
| 982 | l2t5_tag_index_c3 <= l2t5_tag_index_c2 ; | |
| 983 | l2t5_tag_index_c4 <= l2t5_tag_index_c3 ; | |
| 984 | ||
| 985 | l2t5_wr_en_c1 <= l2t5_wr_en; | |
| 986 | l2t5_wr_en_c2 <= l2t5_wr_en_c1; | |
| 987 | l2t5_wr_en_c3 <= l2t5_wr_en_c2; | |
| 988 | l2t5_wr_en_c4 <= l2t5_wr_en_c3; | |
| 989 | ||
| 990 | l2t5_way_c1 <= l2t5_way; | |
| 991 | l2t5_way_c2 <= l2t5_way_c1; | |
| 992 | l2t5_way_c3 <= l2t5_way_c2; | |
| 993 | l2t5_way_c4 <= l2t5_way_c3; | |
| 994 | ||
| 995 | l2t5_tag_c1 <= l2t5_tag; | |
| 996 | l2t5_tag_c2 <= l2t5_tag_c1; | |
| 997 | l2t5_tag_c3 <= l2t5_tag_c2; | |
| 998 | l2t5_tag_c4 <= l2t5_tag_c3; | |
| 999 | ||
| 1000 | l2t5_addr_c3 <= l2t5_addr; | |
| 1001 | l2t5_addr_c4 <= l2t5_addr_c3; | |
| 1002 | ||
| 1003 | l2t5_inst_vld_c3 <= l2t5_inst_vld; | |
| 1004 | l2t5_inst_vld_c4 <= l2t5_inst_vld_c3; | |
| 1005 | ||
| 1006 | l2t5_tagonly_hit_c3 <= l2t5_tagonly_hit; | |
| 1007 | l2t5_tagonly_hit_c4 <= l2t5_tagonly_hit_c3; | |
| 1008 | ||
| 1009 | l2t5_vuad_wr_c4 <= l2t5_vuad_wr; | |
| 1010 | ||
| 1011 | case (l2t5_way_c4) | |
| 1012 | 16'h1: way_5 = 4'b0; | |
| 1013 | 16'h2: way_5 = 4'h1; | |
| 1014 | 16'h4: way_5 = 4'h2; | |
| 1015 | 16'h8: way_5 = 4'h3; | |
| 1016 | 16'h10: way_5 = 4'h4; | |
| 1017 | 16'h20: way_5 = 4'h5; | |
| 1018 | 16'h40: way_5 = 4'h6; | |
| 1019 | 16'h80: way_5 = 4'h7; | |
| 1020 | 16'h100: way_5 = 4'h8; | |
| 1021 | 16'h200: way_5 = 4'h9; | |
| 1022 | 16'h400: way_5 = 4'ha; | |
| 1023 | 16'h800: way_5 = 4'hb; | |
| 1024 | 16'h1000: way_5 = 4'hc; | |
| 1025 | 16'h2000: way_5 = 4'hd; | |
| 1026 | 16'h4000: way_5 = 4'he; | |
| 1027 | 16'h8000: way_5 = 4'hf; | |
| 1028 | endcase | |
| 1029 | ||
| 1030 | ||
| 1031 | // VUAD write Req | |
| 1032 | if (l2t5_vuad_wr_c4 ) begin | |
| 1033 | // VUAD & Tag Write | |
| 1034 | if (l2t5_wr_en_c4 ) begin | |
| 1035 | if (l2t5_tag_index_c4 != l2t5_vuad_index) begin | |
| 1036 | ||
| 1037 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,5, l2t5_tagonly_hit_c4, l2t5_addr_c4, l2t5_tag_c4, l2t5_tag_index_c4, 5, way_5, l2t5_valid, l2t5_used, l2t5_alloc, l2t5_dirty); | |
| 1038 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,5, l2t5_tag_index_c4, l2t5_vuad_index); | |
| 1039 | /* | |
| 1040 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,5, l2t5_addr_c4, l2t5_tag_c4, l2t5_tag_index_c4, 5, way_5, l2t5_valid, l2t5_used, l2t5_alloc, l2t5_dirty); | |
| 1041 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,5, l2t5_tag_index_c4, l2t5_vuad_index); | |
| 1042 | */ | |
| 1043 | end else begin | |
| 1044 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,5,l2t5_tagonly_hit_c4, l2t5_addr_c4, l2t5_tag_c4, l2t5_tag_index_c4, 5, way_5, l2t5_valid, l2t5_used, l2t5_alloc, l2t5_dirty); | |
| 1045 | /* | |
| 1046 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,5, l2t5_addr_c4, l2t5_tag_c4, l2t5_tag_index_c4, 5, way_5, l2t5_valid, l2t5_used, l2t5_alloc, l2t5_dirty); | |
| 1047 | */ | |
| 1048 | end | |
| 1049 | end else begin | |
| 1050 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,5, l2t5_tagonly_hit_c4, l2t5_addr_c4, l2t5_vuad_index, 5, l2t5_valid, l2t5_used, l2t5_alloc, l2t5_dirty); | |
| 1051 | /* | |
| 1052 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,5, l2t5_addr_c4, l2t5_vuad_index, 5, l2t5_valid, l2t5_used, l2t5_alloc, l2t5_dirty); | |
| 1053 | */ | |
| 1054 | end | |
| 1055 | end | |
| 1056 | ||
| 1057 | end else begin | |
| 1058 | if (!l2t5_vuad_wr_c4 && l2t5_wr_en_c4) begin | |
| 1059 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,5,l2t5_tagonly_hit_c4, l2t5_addr_c4, l2t5_tag_c4, l2t5_tag_index_c4, 5, way_5); | |
| 1060 | /* | |
| 1061 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,5, l2t5_addr_c4, l2t5_tag_c4, l2t5_tag_index_c4, 5, way_5); | |
| 1062 | */ | |
| 1063 | end | |
| 1064 | end | |
| 1065 | ||
| 1066 | end | |
| 1067 | ||
| 1068 | ||
| 1069 | ||
| 1070 | ||
| 1071 | reg [8:0] l2t6_tag_index_c1, l2t6_tag_index_c2, l2t6_tag_index_c3, l2t6_tag_index_c4; | |
| 1072 | reg l2t6_wr_en_c1, l2t6_wr_en_c2, l2t6_wr_en_c3, l2t6_wr_en_c4; | |
| 1073 | reg [15:0] l2t6_way_c1, l2t6_way_c2, l2t6_way_c3, l2t6_way_c4; | |
| 1074 | reg [21:0] l2t6_tag_c1, l2t6_tag_c2, l2t6_tag_c3, l2t6_tag_c4; | |
| 1075 | ||
| 1076 | reg [39:0] l2t6_addr_c3, l2t6_addr_c4; | |
| 1077 | reg l2t6_inst_vld_c3, l2t6_inst_vld_c4; | |
| 1078 | reg l2t6_tagonly_hit_c3, l2t6_tagonly_hit_c4; | |
| 1079 | ||
| 1080 | reg l2t6_vuad_wr_c4; | |
| 1081 | ||
| 1082 | reg [3:0] way_6; | |
| 1083 | ||
| 1084 | initial | |
| 1085 | begin | |
| 1086 | l2t6_tag_index_c1 = 0; | |
| 1087 | l2t6_wr_en_c1 = 0; | |
| 1088 | l2t6_way_c1 = 0; | |
| 1089 | l2t6_tag_c1 = 0; | |
| 1090 | l2t6_tag_index_c2 = 0; | |
| 1091 | l2t6_wr_en_c2 = 0; | |
| 1092 | l2t6_way_c2 = 0; | |
| 1093 | l2t6_tag_c2 = 0; | |
| 1094 | l2t6_tag_index_c3 = 0; | |
| 1095 | l2t6_wr_en_c3 = 0; | |
| 1096 | l2t6_way_c3 = 0; | |
| 1097 | l2t6_tag_c3 = 0; | |
| 1098 | l2t6_tag_index_c4 = 0; | |
| 1099 | l2t6_wr_en_c4 = 0; | |
| 1100 | l2t6_way_c4 = 0; | |
| 1101 | l2t6_tag_c4 = 0; | |
| 1102 | l2t6_addr_c3 = 0; | |
| 1103 | l2t6_inst_vld_c3 = 0; | |
| 1104 | l2t6_addr_c4 = 0; | |
| 1105 | l2t6_inst_vld_c4 = 0; | |
| 1106 | l2t6_vuad_wr_c4 = 0; | |
| 1107 | end | |
| 1108 | ||
| 1109 | always @ (posedge cmp_clk) | |
| 1110 | begin | |
| 1111 | if (cmp_rst_l) begin | |
| 1112 | ||
| 1113 | l2t6_tag_index_c1 <= l2t6_tag_index ; | |
| 1114 | l2t6_tag_index_c2 <= l2t6_tag_index_c1 ; | |
| 1115 | l2t6_tag_index_c3 <= l2t6_tag_index_c2 ; | |
| 1116 | l2t6_tag_index_c4 <= l2t6_tag_index_c3 ; | |
| 1117 | ||
| 1118 | l2t6_wr_en_c1 <= l2t6_wr_en; | |
| 1119 | l2t6_wr_en_c2 <= l2t6_wr_en_c1; | |
| 1120 | l2t6_wr_en_c3 <= l2t6_wr_en_c2; | |
| 1121 | l2t6_wr_en_c4 <= l2t6_wr_en_c3; | |
| 1122 | ||
| 1123 | l2t6_way_c1 <= l2t6_way; | |
| 1124 | l2t6_way_c2 <= l2t6_way_c1; | |
| 1125 | l2t6_way_c3 <= l2t6_way_c2; | |
| 1126 | l2t6_way_c4 <= l2t6_way_c3; | |
| 1127 | ||
| 1128 | l2t6_tag_c1 <= l2t6_tag; | |
| 1129 | l2t6_tag_c2 <= l2t6_tag_c1; | |
| 1130 | l2t6_tag_c3 <= l2t6_tag_c2; | |
| 1131 | l2t6_tag_c4 <= l2t6_tag_c3; | |
| 1132 | ||
| 1133 | l2t6_addr_c3 <= l2t6_addr; | |
| 1134 | l2t6_addr_c4 <= l2t6_addr_c3; | |
| 1135 | ||
| 1136 | l2t6_inst_vld_c3 <= l2t6_inst_vld; | |
| 1137 | l2t6_inst_vld_c4 <= l2t6_inst_vld_c3; | |
| 1138 | ||
| 1139 | l2t6_tagonly_hit_c3 <= l2t6_tagonly_hit; | |
| 1140 | l2t6_tagonly_hit_c4 <= l2t6_tagonly_hit_c3; | |
| 1141 | ||
| 1142 | l2t6_vuad_wr_c4 <= l2t6_vuad_wr; | |
| 1143 | ||
| 1144 | case (l2t6_way_c4) | |
| 1145 | 16'h1: way_6 = 4'b0; | |
| 1146 | 16'h2: way_6 = 4'h1; | |
| 1147 | 16'h4: way_6 = 4'h2; | |
| 1148 | 16'h8: way_6 = 4'h3; | |
| 1149 | 16'h10: way_6 = 4'h4; | |
| 1150 | 16'h20: way_6 = 4'h5; | |
| 1151 | 16'h40: way_6 = 4'h6; | |
| 1152 | 16'h80: way_6 = 4'h7; | |
| 1153 | 16'h100: way_6 = 4'h8; | |
| 1154 | 16'h200: way_6 = 4'h9; | |
| 1155 | 16'h400: way_6 = 4'ha; | |
| 1156 | 16'h800: way_6 = 4'hb; | |
| 1157 | 16'h1000: way_6 = 4'hc; | |
| 1158 | 16'h2000: way_6 = 4'hd; | |
| 1159 | 16'h4000: way_6 = 4'he; | |
| 1160 | 16'h8000: way_6 = 4'hf; | |
| 1161 | endcase | |
| 1162 | ||
| 1163 | ||
| 1164 | // VUAD write Req | |
| 1165 | if (l2t6_vuad_wr_c4 ) begin | |
| 1166 | // VUAD & Tag Write | |
| 1167 | if (l2t6_wr_en_c4 ) begin | |
| 1168 | if (l2t6_tag_index_c4 != l2t6_vuad_index) begin | |
| 1169 | ||
| 1170 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,6, l2t6_tagonly_hit_c4, l2t6_addr_c4, l2t6_tag_c4, l2t6_tag_index_c4, 6, way_6, l2t6_valid, l2t6_used, l2t6_alloc, l2t6_dirty); | |
| 1171 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,6, l2t6_tag_index_c4, l2t6_vuad_index); | |
| 1172 | /* | |
| 1173 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,6, l2t6_addr_c4, l2t6_tag_c4, l2t6_tag_index_c4, 6, way_6, l2t6_valid, l2t6_used, l2t6_alloc, l2t6_dirty); | |
| 1174 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,6, l2t6_tag_index_c4, l2t6_vuad_index); | |
| 1175 | */ | |
| 1176 | end else begin | |
| 1177 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,6,l2t6_tagonly_hit_c4, l2t6_addr_c4, l2t6_tag_c4, l2t6_tag_index_c4, 6, way_6, l2t6_valid, l2t6_used, l2t6_alloc, l2t6_dirty); | |
| 1178 | /* | |
| 1179 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,6, l2t6_addr_c4, l2t6_tag_c4, l2t6_tag_index_c4, 6, way_6, l2t6_valid, l2t6_used, l2t6_alloc, l2t6_dirty); | |
| 1180 | */ | |
| 1181 | end | |
| 1182 | end else begin | |
| 1183 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,6, l2t6_tagonly_hit_c4, l2t6_addr_c4, l2t6_vuad_index, 6, l2t6_valid, l2t6_used, l2t6_alloc, l2t6_dirty); | |
| 1184 | /* | |
| 1185 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,6, l2t6_addr_c4, l2t6_vuad_index, 6, l2t6_valid, l2t6_used, l2t6_alloc, l2t6_dirty); | |
| 1186 | */ | |
| 1187 | end | |
| 1188 | end | |
| 1189 | ||
| 1190 | end else begin | |
| 1191 | if (!l2t6_vuad_wr_c4 && l2t6_wr_en_c4) begin | |
| 1192 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,6,l2t6_tagonly_hit_c4, l2t6_addr_c4, l2t6_tag_c4, l2t6_tag_index_c4, 6, way_6); | |
| 1193 | /* | |
| 1194 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,6, l2t6_addr_c4, l2t6_tag_c4, l2t6_tag_index_c4, 6, way_6); | |
| 1195 | */ | |
| 1196 | end | |
| 1197 | end | |
| 1198 | ||
| 1199 | end | |
| 1200 | ||
| 1201 | ||
| 1202 | ||
| 1203 | ||
| 1204 | reg [8:0] l2t7_tag_index_c1, l2t7_tag_index_c2, l2t7_tag_index_c3, l2t7_tag_index_c4; | |
| 1205 | reg l2t7_wr_en_c1, l2t7_wr_en_c2, l2t7_wr_en_c3, l2t7_wr_en_c4; | |
| 1206 | reg [15:0] l2t7_way_c1, l2t7_way_c2, l2t7_way_c3, l2t7_way_c4; | |
| 1207 | reg [21:0] l2t7_tag_c1, l2t7_tag_c2, l2t7_tag_c3, l2t7_tag_c4; | |
| 1208 | ||
| 1209 | reg [39:0] l2t7_addr_c3, l2t7_addr_c4; | |
| 1210 | reg l2t7_inst_vld_c3, l2t7_inst_vld_c4; | |
| 1211 | reg l2t7_tagonly_hit_c3, l2t7_tagonly_hit_c4; | |
| 1212 | ||
| 1213 | reg l2t7_vuad_wr_c4; | |
| 1214 | ||
| 1215 | reg [3:0] way_7; | |
| 1216 | ||
| 1217 | initial | |
| 1218 | begin | |
| 1219 | l2t7_tag_index_c1 = 0; | |
| 1220 | l2t7_wr_en_c1 = 0; | |
| 1221 | l2t7_way_c1 = 0; | |
| 1222 | l2t7_tag_c1 = 0; | |
| 1223 | l2t7_tag_index_c2 = 0; | |
| 1224 | l2t7_wr_en_c2 = 0; | |
| 1225 | l2t7_way_c2 = 0; | |
| 1226 | l2t7_tag_c2 = 0; | |
| 1227 | l2t7_tag_index_c3 = 0; | |
| 1228 | l2t7_wr_en_c3 = 0; | |
| 1229 | l2t7_way_c3 = 0; | |
| 1230 | l2t7_tag_c3 = 0; | |
| 1231 | l2t7_tag_index_c4 = 0; | |
| 1232 | l2t7_wr_en_c4 = 0; | |
| 1233 | l2t7_way_c4 = 0; | |
| 1234 | l2t7_tag_c4 = 0; | |
| 1235 | l2t7_addr_c3 = 0; | |
| 1236 | l2t7_inst_vld_c3 = 0; | |
| 1237 | l2t7_addr_c4 = 0; | |
| 1238 | l2t7_inst_vld_c4 = 0; | |
| 1239 | l2t7_vuad_wr_c4 = 0; | |
| 1240 | end | |
| 1241 | ||
| 1242 | always @ (posedge cmp_clk) | |
| 1243 | begin | |
| 1244 | if (cmp_rst_l) begin | |
| 1245 | ||
| 1246 | l2t7_tag_index_c1 <= l2t7_tag_index ; | |
| 1247 | l2t7_tag_index_c2 <= l2t7_tag_index_c1 ; | |
| 1248 | l2t7_tag_index_c3 <= l2t7_tag_index_c2 ; | |
| 1249 | l2t7_tag_index_c4 <= l2t7_tag_index_c3 ; | |
| 1250 | ||
| 1251 | l2t7_wr_en_c1 <= l2t7_wr_en; | |
| 1252 | l2t7_wr_en_c2 <= l2t7_wr_en_c1; | |
| 1253 | l2t7_wr_en_c3 <= l2t7_wr_en_c2; | |
| 1254 | l2t7_wr_en_c4 <= l2t7_wr_en_c3; | |
| 1255 | ||
| 1256 | l2t7_way_c1 <= l2t7_way; | |
| 1257 | l2t7_way_c2 <= l2t7_way_c1; | |
| 1258 | l2t7_way_c3 <= l2t7_way_c2; | |
| 1259 | l2t7_way_c4 <= l2t7_way_c3; | |
| 1260 | ||
| 1261 | l2t7_tag_c1 <= l2t7_tag; | |
| 1262 | l2t7_tag_c2 <= l2t7_tag_c1; | |
| 1263 | l2t7_tag_c3 <= l2t7_tag_c2; | |
| 1264 | l2t7_tag_c4 <= l2t7_tag_c3; | |
| 1265 | ||
| 1266 | l2t7_addr_c3 <= l2t7_addr; | |
| 1267 | l2t7_addr_c4 <= l2t7_addr_c3; | |
| 1268 | ||
| 1269 | l2t7_inst_vld_c3 <= l2t7_inst_vld; | |
| 1270 | l2t7_inst_vld_c4 <= l2t7_inst_vld_c3; | |
| 1271 | ||
| 1272 | l2t7_tagonly_hit_c3 <= l2t7_tagonly_hit; | |
| 1273 | l2t7_tagonly_hit_c4 <= l2t7_tagonly_hit_c3; | |
| 1274 | ||
| 1275 | l2t7_vuad_wr_c4 <= l2t7_vuad_wr; | |
| 1276 | ||
| 1277 | case (l2t7_way_c4) | |
| 1278 | 16'h1: way_7 = 4'b0; | |
| 1279 | 16'h2: way_7 = 4'h1; | |
| 1280 | 16'h4: way_7 = 4'h2; | |
| 1281 | 16'h8: way_7 = 4'h3; | |
| 1282 | 16'h10: way_7 = 4'h4; | |
| 1283 | 16'h20: way_7 = 4'h5; | |
| 1284 | 16'h40: way_7 = 4'h6; | |
| 1285 | 16'h80: way_7 = 4'h7; | |
| 1286 | 16'h100: way_7 = 4'h8; | |
| 1287 | 16'h200: way_7 = 4'h9; | |
| 1288 | 16'h400: way_7 = 4'ha; | |
| 1289 | 16'h800: way_7 = 4'hb; | |
| 1290 | 16'h1000: way_7 = 4'hc; | |
| 1291 | 16'h2000: way_7 = 4'hd; | |
| 1292 | 16'h4000: way_7 = 4'he; | |
| 1293 | 16'h8000: way_7 = 4'hf; | |
| 1294 | endcase | |
| 1295 | ||
| 1296 | ||
| 1297 | // VUAD write Req | |
| 1298 | if (l2t7_vuad_wr_c4 ) begin | |
| 1299 | // VUAD & Tag Write | |
| 1300 | if (l2t7_wr_en_c4 ) begin | |
| 1301 | if (l2t7_tag_index_c4 != l2t7_vuad_index) begin | |
| 1302 | ||
| 1303 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x, Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,7, l2t7_tagonly_hit_c4, l2t7_addr_c4, l2t7_tag_c4, l2t7_tag_index_c4, 7, way_7, l2t7_valid, l2t7_used, l2t7_alloc, l2t7_dirty); | |
| 1304 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,7, l2t7_tag_index_c4, l2t7_vuad_index); | |
| 1305 | /* | |
| 1306 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,7, l2t7_addr_c4, l2t7_tag_c4, l2t7_tag_index_c4, 7, way_7, l2t7_valid, l2t7_used, l2t7_alloc, l2t7_dirty); | |
| 1307 | $display("%0d:L2_TAGSTATE_MON[%0d] -> ** L2 Tag Index in Tag Update differe from VUAD index update*** Tag Index = %0x, VUAD Index = %0x, , ", $time,7, l2t7_tag_index_c4, l2t7_vuad_index); | |
| 1308 | */ | |
| 1309 | end else begin | |
| 1310 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,7,l2t7_tagonly_hit_c4, l2t7_addr_c4, l2t7_tag_c4, l2t7_tag_index_c4, 7, way_7, l2t7_valid, l2t7_used, l2t7_alloc, l2t7_dirty); | |
| 1311 | /* | |
| 1312 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag and VUAD updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,7, l2t7_addr_c4, l2t7_tag_c4, l2t7_tag_index_c4, 7, way_7, l2t7_valid, l2t7_used, l2t7_alloc, l2t7_dirty); | |
| 1313 | */ | |
| 1314 | end | |
| 1315 | end else begin | |
| 1316 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,7, l2t7_tagonly_hit_c4, l2t7_addr_c4, l2t7_vuad_index, 7, l2t7_valid, l2t7_used, l2t7_alloc, l2t7_dirty); | |
| 1317 | /* | |
| 1318 | $display("%0d:L2_TAGSTATE_MON[%0d] -> VUAD updated :: Addr = %x, Index = %0x, Bank = %0x, Valid = %0x, Used = %0x, Allocate = %0x, Dirty = %0x ", $time,7, l2t7_addr_c4, l2t7_vuad_index, 7, l2t7_valid, l2t7_used, l2t7_alloc, l2t7_dirty); | |
| 1319 | */ | |
| 1320 | end | |
| 1321 | end | |
| 1322 | ||
| 1323 | end else begin | |
| 1324 | if (!l2t7_vuad_wr_c4 && l2t7_wr_en_c4) begin | |
| 1325 | `PR_INFO("l2_tagstate_mon",`INFO,"%0d:L2_TAGSTATE_MON[%0d] -> Tag Hit= %0x Only Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,7,l2t7_tagonly_hit_c4, l2t7_addr_c4, l2t7_tag_c4, l2t7_tag_index_c4, 7, way_7); | |
| 1326 | /* | |
| 1327 | $display("%0d:L2_TAGSTATE_MON[%0d] -> Tag updated :: Addr = %x, Tag = %0x, Index = %0x, Bank = %0x, Way = %0d", $time,7, l2t7_addr_c4, l2t7_tag_c4, l2t7_tag_index_c4, 7, way_7); | |
| 1328 | */ | |
| 1329 | end | |
| 1330 | end | |
| 1331 | ||
| 1332 | end | |
| 1333 | ||
| 1334 | ||
| 1335 | ||
| 1336 | //===================================================================== | |
| 1337 | // This task allows some more clocks and kills the test | |
| 1338 | //===================================================================== | |
| 1339 | task finish_test; | |
| 1340 | input [512:0] message; | |
| 1341 | input [2:0] id; | |
| 1342 | ||
| 1343 | begin | |
| 1344 | $display("%0d ERROR: L2 Bank %d %s", $time, id, message); | |
| 1345 | @(posedge cmp_clk); | |
| 1346 | @(posedge cmp_clk); | |
| 1347 | @(posedge cmp_clk); | |
| 1348 | $error ("l2_tagstate_mon", "L2_TAGSTATE monitor exited") ; | |
| 1349 | end | |
| 1350 | endtask | |
| 1351 | ||
| 1352 | ||
| 1353 | ||
| 1354 | ||
| 1355 | ||
| 1356 | ||
| 1357 | ||
| 1358 | endmodule |