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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / lru_mon.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: lru_mon.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef CORE_0
36
37
38module lru_mon_c0;
39
40// If vcs_build_args NO_MONITORS, then module will be empty
41`ifndef GATESIM
42`ifndef NO_MONITORS
43`ifdef SPC
44
45wire [7:0] core0_ld_rq_vld = `SPC0.lsu.lmc.ld_rq_vld[7:0];
46wire [7:0] core0_ld_asi_rq_sel = `SPC0.lsu.lmc.ld_asi_rq_sel[7:0];
47wire [7:0] core0_ld_pcx_rq_sel = `SPC0.lsu.lmc.ld_pcx_rq_sel[7:0];
48
49
50always @(posedge `SPC0.l2clk) begin
51
52 if (core0_ld_rq_vld[0] == 8'h0) begin
53 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
54 end
55 if (core0_ld_rq_vld[1] == 8'h1) begin
56 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
57 end
58 if (core0_ld_rq_vld[2] == 8'h2) begin
59 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
60 end
61 if (core0_ld_rq_vld[3] == 8'h3) begin
62 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
63 end
64 if (core0_ld_rq_vld[4] == 8'h4) begin
65 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
66 end
67 if (core0_ld_rq_vld[5] == 8'h5) begin
68 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
69 end
70 if (core0_ld_rq_vld[6] == 8'h6) begin
71 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
72 end
73 if (core0_ld_rq_vld[7] == 8'h7) begin
74 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
75 end
76
77 if ((core0_ld_asi_rq_sel[0] == 8'h0) | (core0_ld_pcx_rq_sel[0] == 8'h0)) begin
78 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
79 end
80 if ((core0_ld_asi_rq_sel[1] == 8'h1) | (core0_ld_pcx_rq_sel[1] == 8'h1)) begin
81 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
82 end
83 if ((core0_ld_asi_rq_sel[2] == 8'h2) | (core0_ld_pcx_rq_sel[2] == 8'h2)) begin
84 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
85 end
86 if ((core0_ld_asi_rq_sel[3] == 8'h3) | (core0_ld_pcx_rq_sel[3] == 8'h3)) begin
87 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
88 end
89 if ((core0_ld_asi_rq_sel[4] == 8'h4) | (core0_ld_pcx_rq_sel[4] == 8'h4)) begin
90 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
91 end
92 if ((core0_ld_asi_rq_sel[5] == 8'h5) | (core0_ld_pcx_rq_sel[5] == 8'h5)) begin
93 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
94 end
95 if ((core0_ld_asi_rq_sel[6] == 8'h6) | (core0_ld_pcx_rq_sel[6] == 8'h6)) begin
96 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
97 end
98 if ((core0_ld_asi_rq_sel[7] == 8'h7) | (core0_ld_pcx_rq_sel[7] == 8'h7)) begin
99 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
100 end
101
102end
103
104`endif
105`endif
106`endif
107
108endmodule
109
110`endif
111
112
113`ifdef CORE_1
114
115
116module lru_mon_c1;
117
118// If vcs_build_args NO_MONITORS, then module will be empty
119`ifndef GATESIM
120`ifndef NO_MONITORS
121`ifdef SPC
122
123wire [7:0] core1_ld_rq_vld = `SPC1.lsu.lmc.ld_rq_vld[7:0];
124wire [7:0] core1_ld_asi_rq_sel = `SPC1.lsu.lmc.ld_asi_rq_sel[7:0];
125wire [7:0] core1_ld_pcx_rq_sel = `SPC1.lsu.lmc.ld_pcx_rq_sel[7:0];
126
127
128always @(posedge `SPC1.l2clk) begin
129
130 if (core1_ld_rq_vld[0] == 8'h0) begin
131 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
132 end
133 if (core1_ld_rq_vld[1] == 8'h1) begin
134 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
135 end
136 if (core1_ld_rq_vld[2] == 8'h2) begin
137 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
138 end
139 if (core1_ld_rq_vld[3] == 8'h3) begin
140 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
141 end
142 if (core1_ld_rq_vld[4] == 8'h4) begin
143 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
144 end
145 if (core1_ld_rq_vld[5] == 8'h5) begin
146 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
147 end
148 if (core1_ld_rq_vld[6] == 8'h6) begin
149 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
150 end
151 if (core1_ld_rq_vld[7] == 8'h7) begin
152 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
153 end
154
155 if ((core1_ld_asi_rq_sel[0] == 8'h0) | (core1_ld_pcx_rq_sel[0] == 8'h0)) begin
156 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
157 end
158 if ((core1_ld_asi_rq_sel[1] == 8'h1) | (core1_ld_pcx_rq_sel[1] == 8'h1)) begin
159 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
160 end
161 if ((core1_ld_asi_rq_sel[2] == 8'h2) | (core1_ld_pcx_rq_sel[2] == 8'h2)) begin
162 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
163 end
164 if ((core1_ld_asi_rq_sel[3] == 8'h3) | (core1_ld_pcx_rq_sel[3] == 8'h3)) begin
165 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
166 end
167 if ((core1_ld_asi_rq_sel[4] == 8'h4) | (core1_ld_pcx_rq_sel[4] == 8'h4)) begin
168 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
169 end
170 if ((core1_ld_asi_rq_sel[5] == 8'h5) | (core1_ld_pcx_rq_sel[5] == 8'h5)) begin
171 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
172 end
173 if ((core1_ld_asi_rq_sel[6] == 8'h6) | (core1_ld_pcx_rq_sel[6] == 8'h6)) begin
174 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
175 end
176 if ((core1_ld_asi_rq_sel[7] == 8'h7) | (core1_ld_pcx_rq_sel[7] == 8'h7)) begin
177 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
178 end
179
180end
181
182`endif
183`endif
184`endif
185
186endmodule
187
188`endif
189
190
191`ifdef CORE_2
192
193
194module lru_mon_c2;
195
196// If vcs_build_args NO_MONITORS, then module will be empty
197`ifndef GATESIM
198`ifndef NO_MONITORS
199`ifdef SPC
200
201wire [7:0] core2_ld_rq_vld = `SPC2.lsu.lmc.ld_rq_vld[7:0];
202wire [7:0] core2_ld_asi_rq_sel = `SPC2.lsu.lmc.ld_asi_rq_sel[7:0];
203wire [7:0] core2_ld_pcx_rq_sel = `SPC2.lsu.lmc.ld_pcx_rq_sel[7:0];
204
205
206always @(posedge `SPC2.l2clk) begin
207
208 if (core2_ld_rq_vld[0] == 8'h0) begin
209 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
210 end
211 if (core2_ld_rq_vld[1] == 8'h1) begin
212 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
213 end
214 if (core2_ld_rq_vld[2] == 8'h2) begin
215 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
216 end
217 if (core2_ld_rq_vld[3] == 8'h3) begin
218 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
219 end
220 if (core2_ld_rq_vld[4] == 8'h4) begin
221 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
222 end
223 if (core2_ld_rq_vld[5] == 8'h5) begin
224 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
225 end
226 if (core2_ld_rq_vld[6] == 8'h6) begin
227 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
228 end
229 if (core2_ld_rq_vld[7] == 8'h7) begin
230 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
231 end
232
233 if ((core2_ld_asi_rq_sel[0] == 8'h0) | (core2_ld_pcx_rq_sel[0] == 8'h0)) begin
234 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
235 end
236 if ((core2_ld_asi_rq_sel[1] == 8'h1) | (core2_ld_pcx_rq_sel[1] == 8'h1)) begin
237 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
238 end
239 if ((core2_ld_asi_rq_sel[2] == 8'h2) | (core2_ld_pcx_rq_sel[2] == 8'h2)) begin
240 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
241 end
242 if ((core2_ld_asi_rq_sel[3] == 8'h3) | (core2_ld_pcx_rq_sel[3] == 8'h3)) begin
243 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
244 end
245 if ((core2_ld_asi_rq_sel[4] == 8'h4) | (core2_ld_pcx_rq_sel[4] == 8'h4)) begin
246 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
247 end
248 if ((core2_ld_asi_rq_sel[5] == 8'h5) | (core2_ld_pcx_rq_sel[5] == 8'h5)) begin
249 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
250 end
251 if ((core2_ld_asi_rq_sel[6] == 8'h6) | (core2_ld_pcx_rq_sel[6] == 8'h6)) begin
252 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
253 end
254 if ((core2_ld_asi_rq_sel[7] == 8'h7) | (core2_ld_pcx_rq_sel[7] == 8'h7)) begin
255 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
256 end
257
258end
259
260`endif
261`endif
262`endif
263
264endmodule
265
266`endif
267
268
269`ifdef CORE_3
270
271
272module lru_mon_c3;
273
274// If vcs_build_args NO_MONITORS, then module will be empty
275`ifndef GATESIM
276`ifndef NO_MONITORS
277`ifdef SPC
278
279wire [7:0] core3_ld_rq_vld = `SPC3.lsu.lmc.ld_rq_vld[7:0];
280wire [7:0] core3_ld_asi_rq_sel = `SPC3.lsu.lmc.ld_asi_rq_sel[7:0];
281wire [7:0] core3_ld_pcx_rq_sel = `SPC3.lsu.lmc.ld_pcx_rq_sel[7:0];
282
283
284always @(posedge `SPC3.l2clk) begin
285
286 if (core3_ld_rq_vld[0] == 8'h0) begin
287 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
288 end
289 if (core3_ld_rq_vld[1] == 8'h1) begin
290 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
291 end
292 if (core3_ld_rq_vld[2] == 8'h2) begin
293 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
294 end
295 if (core3_ld_rq_vld[3] == 8'h3) begin
296 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
297 end
298 if (core3_ld_rq_vld[4] == 8'h4) begin
299 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
300 end
301 if (core3_ld_rq_vld[5] == 8'h5) begin
302 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
303 end
304 if (core3_ld_rq_vld[6] == 8'h6) begin
305 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
306 end
307 if (core3_ld_rq_vld[7] == 8'h7) begin
308 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
309 end
310
311 if ((core3_ld_asi_rq_sel[0] == 8'h0) | (core3_ld_pcx_rq_sel[0] == 8'h0)) begin
312 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
313 end
314 if ((core3_ld_asi_rq_sel[1] == 8'h1) | (core3_ld_pcx_rq_sel[1] == 8'h1)) begin
315 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
316 end
317 if ((core3_ld_asi_rq_sel[2] == 8'h2) | (core3_ld_pcx_rq_sel[2] == 8'h2)) begin
318 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
319 end
320 if ((core3_ld_asi_rq_sel[3] == 8'h3) | (core3_ld_pcx_rq_sel[3] == 8'h3)) begin
321 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
322 end
323 if ((core3_ld_asi_rq_sel[4] == 8'h4) | (core3_ld_pcx_rq_sel[4] == 8'h4)) begin
324 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
325 end
326 if ((core3_ld_asi_rq_sel[5] == 8'h5) | (core3_ld_pcx_rq_sel[5] == 8'h5)) begin
327 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
328 end
329 if ((core3_ld_asi_rq_sel[6] == 8'h6) | (core3_ld_pcx_rq_sel[6] == 8'h6)) begin
330 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
331 end
332 if ((core3_ld_asi_rq_sel[7] == 8'h7) | (core3_ld_pcx_rq_sel[7] == 8'h7)) begin
333 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
334 end
335
336end
337
338`endif
339`endif
340`endif
341
342endmodule
343
344`endif
345
346
347`ifdef CORE_4
348
349
350module lru_mon_c4;
351
352// If vcs_build_args NO_MONITORS, then module will be empty
353`ifndef GATESIM
354`ifndef NO_MONITORS
355`ifdef SPC
356
357wire [7:0] core4_ld_rq_vld = `SPC4.lsu.lmc.ld_rq_vld[7:0];
358wire [7:0] core4_ld_asi_rq_sel = `SPC4.lsu.lmc.ld_asi_rq_sel[7:0];
359wire [7:0] core4_ld_pcx_rq_sel = `SPC4.lsu.lmc.ld_pcx_rq_sel[7:0];
360
361
362always @(posedge `SPC4.l2clk) begin
363
364 if (core4_ld_rq_vld[0] == 8'h0) begin
365 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
366 end
367 if (core4_ld_rq_vld[1] == 8'h1) begin
368 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
369 end
370 if (core4_ld_rq_vld[2] == 8'h2) begin
371 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
372 end
373 if (core4_ld_rq_vld[3] == 8'h3) begin
374 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
375 end
376 if (core4_ld_rq_vld[4] == 8'h4) begin
377 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
378 end
379 if (core4_ld_rq_vld[5] == 8'h5) begin
380 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
381 end
382 if (core4_ld_rq_vld[6] == 8'h6) begin
383 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
384 end
385 if (core4_ld_rq_vld[7] == 8'h7) begin
386 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
387 end
388
389 if ((core4_ld_asi_rq_sel[0] == 8'h0) | (core4_ld_pcx_rq_sel[0] == 8'h0)) begin
390 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
391 end
392 if ((core4_ld_asi_rq_sel[1] == 8'h1) | (core4_ld_pcx_rq_sel[1] == 8'h1)) begin
393 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
394 end
395 if ((core4_ld_asi_rq_sel[2] == 8'h2) | (core4_ld_pcx_rq_sel[2] == 8'h2)) begin
396 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
397 end
398 if ((core4_ld_asi_rq_sel[3] == 8'h3) | (core4_ld_pcx_rq_sel[3] == 8'h3)) begin
399 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
400 end
401 if ((core4_ld_asi_rq_sel[4] == 8'h4) | (core4_ld_pcx_rq_sel[4] == 8'h4)) begin
402 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
403 end
404 if ((core4_ld_asi_rq_sel[5] == 8'h5) | (core4_ld_pcx_rq_sel[5] == 8'h5)) begin
405 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
406 end
407 if ((core4_ld_asi_rq_sel[6] == 8'h6) | (core4_ld_pcx_rq_sel[6] == 8'h6)) begin
408 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
409 end
410 if ((core4_ld_asi_rq_sel[7] == 8'h7) | (core4_ld_pcx_rq_sel[7] == 8'h7)) begin
411 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
412 end
413
414end
415
416`endif
417`endif
418`endif
419
420endmodule
421
422`endif
423
424
425`ifdef CORE_5
426
427
428module lru_mon_c5;
429
430// If vcs_build_args NO_MONITORS, then module will be empty
431`ifndef GATESIM
432`ifndef NO_MONITORS
433`ifdef SPC
434
435wire [7:0] core5_ld_rq_vld = `SPC5.lsu.lmc.ld_rq_vld[7:0];
436wire [7:0] core5_ld_asi_rq_sel = `SPC5.lsu.lmc.ld_asi_rq_sel[7:0];
437wire [7:0] core5_ld_pcx_rq_sel = `SPC5.lsu.lmc.ld_pcx_rq_sel[7:0];
438
439
440always @(posedge `SPC5.l2clk) begin
441
442 if (core5_ld_rq_vld[0] == 8'h0) begin
443 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
444 end
445 if (core5_ld_rq_vld[1] == 8'h1) begin
446 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
447 end
448 if (core5_ld_rq_vld[2] == 8'h2) begin
449 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
450 end
451 if (core5_ld_rq_vld[3] == 8'h3) begin
452 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
453 end
454 if (core5_ld_rq_vld[4] == 8'h4) begin
455 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
456 end
457 if (core5_ld_rq_vld[5] == 8'h5) begin
458 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
459 end
460 if (core5_ld_rq_vld[6] == 8'h6) begin
461 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
462 end
463 if (core5_ld_rq_vld[7] == 8'h7) begin
464 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
465 end
466
467 if ((core5_ld_asi_rq_sel[0] == 8'h0) | (core5_ld_pcx_rq_sel[0] == 8'h0)) begin
468 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
469 end
470 if ((core5_ld_asi_rq_sel[1] == 8'h1) | (core5_ld_pcx_rq_sel[1] == 8'h1)) begin
471 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
472 end
473 if ((core5_ld_asi_rq_sel[2] == 8'h2) | (core5_ld_pcx_rq_sel[2] == 8'h2)) begin
474 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
475 end
476 if ((core5_ld_asi_rq_sel[3] == 8'h3) | (core5_ld_pcx_rq_sel[3] == 8'h3)) begin
477 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
478 end
479 if ((core5_ld_asi_rq_sel[4] == 8'h4) | (core5_ld_pcx_rq_sel[4] == 8'h4)) begin
480 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
481 end
482 if ((core5_ld_asi_rq_sel[5] == 8'h5) | (core5_ld_pcx_rq_sel[5] == 8'h5)) begin
483 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
484 end
485 if ((core5_ld_asi_rq_sel[6] == 8'h6) | (core5_ld_pcx_rq_sel[6] == 8'h6)) begin
486 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
487 end
488 if ((core5_ld_asi_rq_sel[7] == 8'h7) | (core5_ld_pcx_rq_sel[7] == 8'h7)) begin
489 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
490 end
491
492end
493
494`endif
495`endif
496`endif
497
498endmodule
499
500`endif
501
502
503`ifdef CORE_6
504
505
506module lru_mon_c6;
507
508// If vcs_build_args NO_MONITORS, then module will be empty
509`ifndef GATESIM
510`ifndef NO_MONITORS
511`ifdef SPC
512
513wire [7:0] core6_ld_rq_vld = `SPC6.lsu.lmc.ld_rq_vld[7:0];
514wire [7:0] core6_ld_asi_rq_sel = `SPC6.lsu.lmc.ld_asi_rq_sel[7:0];
515wire [7:0] core6_ld_pcx_rq_sel = `SPC6.lsu.lmc.ld_pcx_rq_sel[7:0];
516
517
518always @(posedge `SPC6.l2clk) begin
519
520 if (core6_ld_rq_vld[0] == 8'h0) begin
521 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
522 end
523 if (core6_ld_rq_vld[1] == 8'h1) begin
524 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
525 end
526 if (core6_ld_rq_vld[2] == 8'h2) begin
527 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
528 end
529 if (core6_ld_rq_vld[3] == 8'h3) begin
530 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
531 end
532 if (core6_ld_rq_vld[4] == 8'h4) begin
533 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
534 end
535 if (core6_ld_rq_vld[5] == 8'h5) begin
536 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
537 end
538 if (core6_ld_rq_vld[6] == 8'h6) begin
539 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
540 end
541 if (core6_ld_rq_vld[7] == 8'h7) begin
542 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
543 end
544
545 if ((core6_ld_asi_rq_sel[0] == 8'h0) | (core6_ld_pcx_rq_sel[0] == 8'h0)) begin
546 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
547 end
548 if ((core6_ld_asi_rq_sel[1] == 8'h1) | (core6_ld_pcx_rq_sel[1] == 8'h1)) begin
549 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
550 end
551 if ((core6_ld_asi_rq_sel[2] == 8'h2) | (core6_ld_pcx_rq_sel[2] == 8'h2)) begin
552 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
553 end
554 if ((core6_ld_asi_rq_sel[3] == 8'h3) | (core6_ld_pcx_rq_sel[3] == 8'h3)) begin
555 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
556 end
557 if ((core6_ld_asi_rq_sel[4] == 8'h4) | (core6_ld_pcx_rq_sel[4] == 8'h4)) begin
558 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
559 end
560 if ((core6_ld_asi_rq_sel[5] == 8'h5) | (core6_ld_pcx_rq_sel[5] == 8'h5)) begin
561 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
562 end
563 if ((core6_ld_asi_rq_sel[6] == 8'h6) | (core6_ld_pcx_rq_sel[6] == 8'h6)) begin
564 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
565 end
566 if ((core6_ld_asi_rq_sel[7] == 8'h7) | (core6_ld_pcx_rq_sel[7] == 8'h7)) begin
567 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
568 end
569
570end
571
572`endif
573`endif
574`endif
575
576endmodule
577
578`endif
579
580
581`ifdef CORE_7
582
583
584module lru_mon_c7;
585
586// If vcs_build_args NO_MONITORS, then module will be empty
587`ifndef GATESIM
588`ifndef NO_MONITORS
589`ifdef SPC
590
591wire [7:0] core7_ld_rq_vld = `SPC7.lsu.lmc.ld_rq_vld[7:0];
592wire [7:0] core7_ld_asi_rq_sel = `SPC7.lsu.lmc.ld_asi_rq_sel[7:0];
593wire [7:0] core7_ld_pcx_rq_sel = `SPC7.lsu.lmc.ld_pcx_rq_sel[7:0];
594
595
596always @(posedge `SPC7.l2clk) begin
597
598 if (core7_ld_rq_vld[0] == 8'h0) begin
599 `PR_INFO("lru_mon", `INFO, "THREAD0_START_REQ \n");
600 end
601 if (core7_ld_rq_vld[1] == 8'h1) begin
602 `PR_INFO("lru_mon", `INFO, "THREAD1_START_REQ \n");
603 end
604 if (core7_ld_rq_vld[2] == 8'h2) begin
605 `PR_INFO("lru_mon", `INFO, "THREAD2_START_REQ \n");
606 end
607 if (core7_ld_rq_vld[3] == 8'h3) begin
608 `PR_INFO("lru_mon", `INFO, "THREAD3_START_REQ \n");
609 end
610 if (core7_ld_rq_vld[4] == 8'h4) begin
611 `PR_INFO("lru_mon", `INFO, "THREAD4_START_REQ \n");
612 end
613 if (core7_ld_rq_vld[5] == 8'h5) begin
614 `PR_INFO("lru_mon", `INFO, "THREAD5_START_REQ \n");
615 end
616 if (core7_ld_rq_vld[6] == 8'h6) begin
617 `PR_INFO("lru_mon", `INFO, "THREAD6_START_REQ \n");
618 end
619 if (core7_ld_rq_vld[7] == 8'h7) begin
620 `PR_INFO("lru_mon", `INFO, "THREAD7_START_REQ \n");
621 end
622
623 if ((core7_ld_asi_rq_sel[0] == 8'h0) | (core7_ld_pcx_rq_sel[0] == 8'h0)) begin
624 `PR_INFO("lru_mon", `INFO, "THREAD0_END_SEL\n");
625 end
626 if ((core7_ld_asi_rq_sel[1] == 8'h1) | (core7_ld_pcx_rq_sel[1] == 8'h1)) begin
627 `PR_INFO("lru_mon", `INFO, "THREAD1_END_SEL\n");
628 end
629 if ((core7_ld_asi_rq_sel[2] == 8'h2) | (core7_ld_pcx_rq_sel[2] == 8'h2)) begin
630 `PR_INFO("lru_mon", `INFO, "THREAD2_END_SEL\n");
631 end
632 if ((core7_ld_asi_rq_sel[3] == 8'h3) | (core7_ld_pcx_rq_sel[3] == 8'h3)) begin
633 `PR_INFO("lru_mon", `INFO, "THREAD3_END_SEL\n");
634 end
635 if ((core7_ld_asi_rq_sel[4] == 8'h4) | (core7_ld_pcx_rq_sel[4] == 8'h4)) begin
636 `PR_INFO("lru_mon", `INFO, "THREAD4_END_SEL\n");
637 end
638 if ((core7_ld_asi_rq_sel[5] == 8'h5) | (core7_ld_pcx_rq_sel[5] == 8'h5)) begin
639 `PR_INFO("lru_mon", `INFO, "THREAD5_END_SEL\n");
640 end
641 if ((core7_ld_asi_rq_sel[6] == 8'h6) | (core7_ld_pcx_rq_sel[6] == 8'h6)) begin
642 `PR_INFO("lru_mon", `INFO, "THREAD6_END_SEL\n");
643 end
644 if ((core7_ld_asi_rq_sel[7] == 8'h7) | (core7_ld_pcx_rq_sel[7] == 8'h7)) begin
645 `PR_INFO("lru_mon", `INFO, "THREAD7_END_SEL\n");
646 end
647
648end
649
650`endif
651`endif
652`endif
653
654endmodule
655
656`endif
657
658
Full OpenSPARC design & verification tarball including full HDL.