Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / mcu / mcuesr_mon.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcuesr_mon.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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34// ========== Copyright Header End ============================================
35module mcuesr_mon();
36
37reg MCUesr_mon_debugon;
38
39initial
40begin
41MCUesr_mon_debugon = 1 ;//Enabled by default
42if($test$plusargs("mcuesr_mon_disable"))
43 MCUesr_mon_debugon = 0;
44end
45
46wire [25:0] esr_mcu0 = tb_top.cpu.mcu0.rdpctl.rdpctl_err_sts_reg[25:0];
47wire [25:0] esr_mcu1 = tb_top.cpu.mcu1.rdpctl.rdpctl_err_sts_reg[25:0];
48wire [25:0] esr_mcu2 = tb_top.cpu.mcu2.rdpctl.rdpctl_err_sts_reg[25:0];
49wire [25:0] esr_mcu3 = tb_top.cpu.mcu3.rdpctl.rdpctl_err_sts_reg[25:0];
50
51wire [30:0] mcu0_fbd_synd = tb_top.cpu.mcu0.fbdic.fbdic_mcu_syndrome[30:0];
52wire [30:0] mcu1_fbd_synd = tb_top.cpu.mcu1.fbdic.fbdic_mcu_syndrome[30:0];
53wire [30:0] mcu2_fbd_synd = tb_top.cpu.mcu2.fbdic.fbdic_mcu_syndrome[30:0];
54wire [30:0] mcu3_fbd_synd = tb_top.cpu.mcu3.fbdic.fbdic_mcu_syndrome[30:0];
55
56 /** Error Status Register***/
57
58always @(esr_mcu0 or MCUesr_mon_debugon)
59begin
60 if(MCUesr_mon_debugon && esr_mcu0)
61 begin
62 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tError Status Register; Detected");
63 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.MEU = %b,MCUESR.MEC = %b",esr_mcu0[25],esr_mcu0[24]);
64 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.DAC = %b,MCUESR.DAU = %b",esr_mcu0[23],esr_mcu0[22]);
65 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.DSC = %b,MCUESR.DSU = %b",esr_mcu0[21],esr_mcu0[20]);
66 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.DBU = %b,MCUESR.MEB = %b",esr_mcu0[19],esr_mcu0[18]);
67 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.FBU = %b,MCUESR.FBR = %b",esr_mcu0[17],esr_mcu0[16]);
68 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.ECC.SYND[15:0] = %h",esr_mcu0[15:0]);
69 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\tMCUESR.FBD.SYND[29:0] = %h", mcu0_fbd_synd[29:0]);
70 end
71end
72
73always @(esr_mcu1 or MCUesr_mon_debugon)
74begin
75 if(MCUesr_mon_debugon && esr_mcu1)
76 begin
77 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tError Status Register; Detected");
78 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.MEU = %b,MCUESR.MEC = %b",esr_mcu1[25],esr_mcu1[24]);
79 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.DAC = %b,MCUESR.DAU = %b",esr_mcu1[23],esr_mcu1[22]);
80 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.DSC = %b,MCUESR.DSU = %b",esr_mcu1[21],esr_mcu1[20]);
81 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.DBU = %b,MCUESR.MEB = %b",esr_mcu1[19],esr_mcu1[18]);
82 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.FBU = %b,MCUESR.FBR = %b",esr_mcu1[17],esr_mcu1[16]);
83 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.ECC.SYND[15:0] = %h",esr_mcu1[15:0]);
84 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\tMCUESR.FBD.SYND[29:0] = %h", mcu1_fbd_synd[29:0]);
85 end
86end
87
88always @(esr_mcu2 or MCUesr_mon_debugon)
89begin
90 if(MCUesr_mon_debugon && esr_mcu2)
91 begin
92 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tError Status Register; Detected");
93 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.MEU = %b,MCUESR.MEC = %b",esr_mcu2[25],esr_mcu2[24]);
94 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.DAC = %b,MCUESR.DAU = %b",esr_mcu2[23],esr_mcu2[22]);
95 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.DSC = %b,MCUESR.DSU = %b",esr_mcu2[21],esr_mcu2[20]);
96 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.DBU = %b,MCUESR.MEB = %b",esr_mcu2[19],esr_mcu2[18]);
97 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.FBU = %b,MCUESR.FBR = %b",esr_mcu2[17],esr_mcu2[16]);
98 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.ECC.SYND[15:0] = %h",esr_mcu2[15:0]);
99 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\tMCUESR.FBD.SYND[29:0] = %h", mcu2_fbd_synd[29:0]);
100 end
101end
102
103always @(esr_mcu3 or MCUesr_mon_debugon)
104begin
105 if(MCUesr_mon_debugon && esr_mcu3)
106 begin
107 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tError Status Register; Detected");
108 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.MEU = %b,MCUESR.MEC = %b",esr_mcu3[25],esr_mcu3[24]);
109 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.DAC = %b,MCUESR.DAU = %b",esr_mcu3[23],esr_mcu3[22]);
110 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.DSC = %b,MCUESR.DSU = %b",esr_mcu3[21],esr_mcu3[20]);
111 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.DBU = %b,MCUESR.MEB = %b",esr_mcu3[19],esr_mcu3[18]);
112 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.FBU = %b,MCUESR.FBR = %b",esr_mcu3[17],esr_mcu3[16]);
113 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.ECC.SYND[15:0] = %h",esr_mcu3[15:0]);
114 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\tMCUESR.FBD.SYND[29:0] = %h", mcu3_fbd_synd[29:0]);
115 end
116end
117
118 /** Error Address Register***/
119
120wire [39:0] mcu0_error_addr = { tb_top.cpu.mcu0.rdpctl_err_addr_reg[35:0], { 4{1'b0} } };
121wire [39:0] mcu1_error_addr = { tb_top.cpu.mcu1.rdpctl_err_addr_reg[35:0], { 4{1'b0} } };
122wire [39:0] mcu2_error_addr = { tb_top.cpu.mcu2.rdpctl_err_addr_reg[35:0], { 4{1'b0} } };
123wire [39:0] mcu3_error_addr = { tb_top.cpu.mcu3.rdpctl_err_addr_reg[35:0], { 4{1'b0} } };
124
125always @( mcu0_error_addr )
126begin
127 if (MCUesr_mon_debugon==1 && (|mcu0_error_addr) )
128 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU0)\t MCU Error Address Register[39:0] = 0x%h", mcu0_error_addr);
129end
130
131always @( mcu1_error_addr )
132begin
133 if (MCUesr_mon_debugon==1 && (|mcu1_error_addr) )
134 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU1)\t MCU Error Address Register[39:0] = 0x%h", mcu1_error_addr);
135end
136
137always @( mcu2_error_addr )
138begin
139 if (MCUesr_mon_debugon==1 && (|mcu2_error_addr) )
140 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU2)\t MCU Error Address Register[39:0] = 0x%h", mcu2_error_addr);
141end
142
143always @( mcu3_error_addr )
144begin
145 if (MCUesr_mon_debugon==1 && (|mcu3_error_addr) )
146 `PR_ALWAYS("MCUesr_mon",`ALWAYS," (MCU3)\t MCU Error Address Register[39:0] = 0x%h", mcu3_error_addr);
147end
148
149
150endmodule