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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_errmon.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1ps/1ps | |
36 | ||
37 | `ifdef MCUSAT | |
38 | `include "mcu_dispmonDefines.vh" | |
39 | `else | |
40 | `include "defines.vh" | |
41 | `include "dispmonDefines.vh" | |
42 | `endif | |
43 | ||
44 | module mcu_errmon( | |
45 | mcu_num, | |
46 | l2clk, | |
47 | drl2clk, | |
48 | rst_wmr_protect, | |
49 | l2t0_mcu_rd_req, | |
50 | l2t1_mcu_rd_req, | |
51 | l2t0_mcu_rd_dummy_req, | |
52 | l2t1_mcu_rd_dummy_req, | |
53 | mcu_l2t0_rd_ack, | |
54 | mcu_l2t1_rd_ack, | |
55 | l2t0_mcu_addr_39to7, | |
56 | l2t1_mcu_addr_39to7, | |
57 | drif_crc_rd_picked, | |
58 | drif_err_rd_picked, | |
59 | drif_rd_picked, | |
60 | drif_scrub_picked, | |
61 | drif0_rd_picked, | |
62 | drif0_raw_hazard, | |
63 | drif1_rd_picked, | |
64 | drif1_raw_hazard, | |
65 | drif_addr_err, | |
66 | fbdic_rddata_vld, | |
67 | fbdic_err_recov, | |
68 | fbdic_err_unrecov, | |
69 | readdp0_syndrome, | |
70 | readdp1_syndrome, | |
71 | ecc_multi_err0, | |
72 | ecc_multi_err1, | |
73 | ecc_single_err0, | |
74 | ecc_single_err1, | |
75 | ncu_mcu_ecci, | |
76 | ncu_mcu_fbri, | |
77 | ncu_mcu_fbui, | |
78 | fbdic_crc_error, | |
79 | rdpctl_crc_recov_err, | |
80 | rdpctl_crc_unrecov_err, | |
81 | drif_err_sts_reg_ld, | |
82 | drif_ucb_addr, | |
83 | drif_ucb_data, | |
84 | flush_reset_complete, | |
85 | rdpctl_err_retry_reg, | |
86 | rdpctl_err_sts_reg, | |
87 | rdpctl_fbr_error_in, | |
88 | rdpctl_fbu_error_in, | |
89 | rdpctl_dac_error_in, | |
90 | rdpctl_dau_error_in, | |
91 | rdpctl_dsc_error_in, | |
92 | rdpctl_dsu_error_in, | |
93 | rdpctl_dbu_error_in, | |
94 | rdpctl_meb_error_in, | |
95 | rdpctl_mec_error_in, | |
96 | rdpctl_meu_error_in | |
97 | ); | |
98 | ||
99 | // mcu variables {{{ | |
100 | // mcu module | |
101 | input [1:0] mcu_num; | |
102 | input l2clk; | |
103 | input drl2clk; | |
104 | input rst_wmr_protect; | |
105 | ||
106 | input l2t0_mcu_rd_req; | |
107 | input l2t1_mcu_rd_req; | |
108 | input l2t0_mcu_rd_dummy_req; | |
109 | input l2t1_mcu_rd_dummy_req; | |
110 | input mcu_l2t0_rd_ack; | |
111 | input mcu_l2t1_rd_ack; | |
112 | input [39:7] l2t0_mcu_addr_39to7; | |
113 | input [39:7] l2t1_mcu_addr_39to7; | |
114 | ||
115 | input drif_crc_rd_picked; | |
116 | input drif_err_rd_picked; | |
117 | input drif_rd_picked; | |
118 | input drif_scrub_picked; | |
119 | input drif0_rd_picked; | |
120 | input drif0_raw_hazard; | |
121 | input drif1_rd_picked; | |
122 | input drif1_raw_hazard; | |
123 | input drif_addr_err; | |
124 | ||
125 | input fbdic_rddata_vld; | |
126 | input fbdic_err_recov; | |
127 | input fbdic_err_unrecov; | |
128 | input [15:0] readdp0_syndrome; | |
129 | input [15:0] readdp1_syndrome; | |
130 | input ecc_multi_err0; | |
131 | input ecc_multi_err1; | |
132 | input ecc_single_err0; | |
133 | input ecc_single_err1; | |
134 | ||
135 | input ncu_mcu_ecci; | |
136 | input ncu_mcu_fbri; | |
137 | input ncu_mcu_fbui; | |
138 | input fbdic_crc_error; | |
139 | input rdpctl_crc_recov_err; | |
140 | input rdpctl_crc_unrecov_err; | |
141 | input drif_err_sts_reg_ld; | |
142 | input [12:0] drif_ucb_addr; | |
143 | input [63:0] drif_ucb_data; | |
144 | ||
145 | input flush_reset_complete; | |
146 | ||
147 | input [36:0] rdpctl_err_retry_reg; | |
148 | input [25:0] rdpctl_err_sts_reg; | |
149 | ||
150 | ||
151 | input rdpctl_fbr_error_in; | |
152 | input rdpctl_fbu_error_in; | |
153 | input rdpctl_dac_error_in; | |
154 | input rdpctl_dau_error_in; | |
155 | input rdpctl_dsc_error_in; | |
156 | input rdpctl_dsu_error_in; | |
157 | input rdpctl_dbu_error_in; | |
158 | input rdpctl_meb_error_in; | |
159 | input rdpctl_mec_error_in; | |
160 | input rdpctl_meu_error_in; | |
161 | ||
162 | ||
163 | // }}} | |
164 | ||
165 | ||
166 | // Local variables {{{ | |
167 | reg [63:0] mcu_err_status_reg; | |
168 | reg [63:0] mcu_err_retry_reg; | |
169 | reg [4:0] tmp_rd_picked; | |
170 | reg [4:0] rd_picked_fifo[7:0]; | |
171 | reg [2:0] rd_picked_fifo_enq; | |
172 | reg [2:0] rd_picked_fifo_deq; | |
173 | reg rd_pa_err_fifo[15:0]; | |
174 | reg [3:0] rd_pa_err_fifo_enq; | |
175 | reg [3:0] rd_pa_err_fifo_deq; | |
176 | reg [12:0] rd_err_fifo[15:0]; | |
177 | reg [3:0] rd_err_fifo_enq; | |
178 | reg [3:0] rd_err_fifo_deq; | |
179 | reg enabled; | |
180 | integer i; | |
181 | ||
182 | initial | |
183 | begin | |
184 | if ($test$plusargs("mcu_errmon_disable")) | |
185 | enabled = 1'b0; | |
186 | end | |
187 | ||
188 | initial begin | |
189 | mcu_err_status_reg = 64'b0; | |
190 | mcu_err_retry_reg = 64'b0; | |
191 | tmp_rd_picked = 4'b0; | |
192 | for(i = 0; i < 8; i = i + 1) | |
193 | rd_picked_fifo[i] = 5'b0; | |
194 | ||
195 | for(i = 0; i < 16; i = i + 1) | |
196 | rd_pa_err_fifo[i] = 1'b0; | |
197 | ||
198 | for(i = 0; i < 16; i = i + 1) | |
199 | rd_err_fifo[i] = 13'b0; | |
200 | ||
201 | rd_err_fifo_enq = 4'b0; | |
202 | rd_err_fifo_deq = 4'b0; | |
203 | rd_picked_fifo_enq = 3'b0; | |
204 | rd_picked_fifo_deq = 3'b0; | |
205 | rd_pa_err_fifo_enq = 4'b0; | |
206 | rd_pa_err_fifo_deq = 4'b0; | |
207 | end | |
208 | //}}} | |
209 | ||
210 | reg [39:0] pa_mask_l; | |
211 | reg [1:0] dimm_adjust; | |
212 | //reg rank_adjust; | |
213 | reg channel_adjust; | |
214 | reg side_adjust; | |
215 | reg [1:0] size_adjust; | |
216 | reg [4:0] dont_check_error_reg; | |
217 | reg halt_on_oob_error,halt_on_mcu_err; | |
218 | reg pb_mode; | |
219 | reg [1:0] pb_shift; | |
220 | reg [3:0] pb; | |
221 | ||
222 | initial | |
223 | begin | |
224 | dont_check_error_reg = 5'hf; | |
225 | ||
226 | if ($test$plusargs("2_FBDIMMS")) dimm_adjust = 2'h2; | |
227 | else if($test$plusargs("4_FBDIMMS")) dimm_adjust = 2'h1; | |
228 | else if($test$plusargs("8_FBDIMMS")) dimm_adjust = 2'h0; | |
229 | else dimm_adjust = 2'h3; // default 1_FBDIMM | |
230 | ||
231 | if($test$plusargs("SNG_CHANNEL")) channel_adjust = 1'h1; | |
232 | else channel_adjust = 1'h0; // default DUAL_CHANNEL | |
233 | ||
234 | if($test$plusargs("STACK_DIMM")) side_adjust = 1'h0; | |
235 | else side_adjust = 1'h1; // default RANK_DIMM | |
236 | ||
237 | if ($test$plusargs("DIMM_SIZE_256")) size_adjust = 2'h3; | |
238 | else if($test$plusargs("DIMM_SIZE_512")) size_adjust = 2'h2; | |
239 | else if($test$plusargs("DIMM_SIZE_1G")) size_adjust = 2'h1; | |
240 | else size_adjust = 2'h0; // default DIMM_SIZE_2G | |
241 | ||
242 | if($value$plusargs("bank_set_mask=%d", pb)) | |
243 | begin | |
244 | case(pb) | |
245 | 4'b0001, 4'b0010, 4'b0100, 4'b1000: begin | |
246 | pb_mode = 1'b1; | |
247 | pb_shift = 2'b10; | |
248 | end | |
249 | 4'b0011, 4'b0101, 4'b0110, 4'b1001, 4'b1010, 4'b1100: begin | |
250 | pb_mode = 1'b1; | |
251 | pb_shift = 2'b1; | |
252 | end | |
253 | default: pb_mode = 1'b0; | |
254 | endcase | |
255 | end | |
256 | else | |
257 | pb_mode = 1'b0; | |
258 | ||
259 | ||
260 | pa_mask_l = (40'hffffffffff >> (1 + channel_adjust + side_adjust + size_adjust + dimm_adjust)); | |
261 | ||
262 | if($test$plusargs("DISABLE_OOB_CHECK")) halt_on_oob_error = 1'b1; | |
263 | else halt_on_oob_error = 1'b0; | |
264 | if($test$plusargs("DISABLE_MCU_ESR_CHECK")) halt_on_mcu_err = 1'b1; | |
265 | else halt_on_mcu_err = 1'b0; | |
266 | ||
267 | ||
268 | end | |
269 | ||
270 | always @(negedge (l2clk && enabled)) | |
271 | begin | |
272 | if(l2t0_mcu_rd_req) | |
273 | begin | |
274 | if((|(l2t0_mcu_addr_39to7[39:7] & (~pa_mask_l[39:7]))) || (pb_mode && ((l2t0_mcu_addr_39to7 << pb_shift) & (~pa_mask_l[39:7])))) | |
275 | begin | |
276 | `ifdef MCUSAT | |
277 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Out-of-bound read address err detected on l2t0 MCU[%d] read. PA[39:7] = %x",mcu_num, l2t0_mcu_addr_39to7); | |
278 | `else | |
279 | if(~halt_on_oob_error) | |
280 | `PR_ERROR("mcu_errmon", `ERROR, "Out-of-bound read addr on l2t0 MCU[%d] Read: Address outside of Current Memory Configuration is being Accessed !!!, PA[39:7] = %x",mcu_num, l2t0_mcu_addr_39to7); | |
281 | `endif | |
282 | if(~l2t0_mcu_rd_dummy_req) | |
283 | begin | |
284 | rd_pa_err_fifo[rd_pa_err_fifo_enq] = 1'b1; | |
285 | rd_pa_err_fifo_enq = rd_pa_err_fifo_enq + 1'b1; | |
286 | end | |
287 | else | |
288 | begin | |
289 | @(posedge mcu_l2t0_rd_ack); | |
290 | if(dont_check_error_reg <= 5'h15) | |
291 | dont_check_error_reg = dont_check_error_reg + 3; | |
292 | if(mcu_err_status_reg[57] == 1'b0) | |
293 | mcu_err_status_reg[57] = 1'b1; | |
294 | else | |
295 | mcu_err_status_reg[56] = 1'b1; | |
296 | end | |
297 | end | |
298 | end | |
299 | end | |
300 | ||
301 | always @(negedge (l2clk && enabled)) | |
302 | begin | |
303 | if(l2t1_mcu_rd_req) | |
304 | begin | |
305 | if((|(l2t1_mcu_addr_39to7[39:7] & (~pa_mask_l[39:7]))) || (pb_mode && ((l2t1_mcu_addr_39to7 << pb_shift) & (~pa_mask_l[39:7])))) | |
306 | begin | |
307 | `ifdef MCUSAT | |
308 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Out-of-bound read address err detected on l2t1 MCU[%d] read, PA[39:7] = %x",mcu_num, l2t1_mcu_addr_39to7); | |
309 | `else | |
310 | if(~halt_on_oob_error) | |
311 | `PR_ERROR("mcu_errmon", `ERROR, "Out-of-bound read addr on l2t1 MCU[%d] Read: Address outside of Current Memory Configuration is being Accessed !!!, PA[39:7] = %x",mcu_num, l2t1_mcu_addr_39to7); | |
312 | `endif | |
313 | if(~l2t1_mcu_rd_dummy_req) | |
314 | begin | |
315 | rd_pa_err_fifo[rd_pa_err_fifo_enq] = 1'b1; | |
316 | rd_pa_err_fifo_enq = rd_pa_err_fifo_enq + 1'b1; | |
317 | end | |
318 | else | |
319 | begin | |
320 | @(posedge mcu_l2t1_rd_ack); | |
321 | if(dont_check_error_reg <= 5'h15) | |
322 | dont_check_error_reg = dont_check_error_reg + 3; | |
323 | if(mcu_err_status_reg[57] == 1'b0) | |
324 | mcu_err_status_reg[57] = 1'b1; | |
325 | else | |
326 | mcu_err_status_reg[56] = 1'b1; | |
327 | end | |
328 | end | |
329 | end | |
330 | end | |
331 | ||
332 | always @(posedge (drl2clk && enabled)) | |
333 | begin | |
334 | case({drif_addr_err, drif_crc_rd_picked, drif_err_rd_picked, drif_rd_picked, drif_scrub_picked}) | |
335 | 5'b00000: tmp_rd_picked = 5'b00000; | |
336 | 5'b00001: tmp_rd_picked = 5'b00001; | |
337 | 5'b00010: begin | |
338 | if((drif0_rd_picked && drif0_raw_hazard) || (drif1_rd_picked && drif1_raw_hazard)) | |
339 | tmp_rd_picked = 5'b00000; | |
340 | else | |
341 | tmp_rd_picked = 5'b00010; | |
342 | end | |
343 | 5'b00100: tmp_rd_picked = 5'b00100; | |
344 | 5'b01100: tmp_rd_picked = 5'b01100; | |
345 | 5'b10010: begin | |
346 | if((drif0_rd_picked && drif0_raw_hazard) || (drif1_rd_picked && drif1_raw_hazard)) | |
347 | begin | |
348 | tmp_rd_picked = 5'b00000; | |
349 | end | |
350 | else | |
351 | begin | |
352 | if(~rd_pa_err_fifo[rd_pa_err_fifo_deq]) | |
353 | `PR_ERROR("mcu_errmon", `ERROR, "Out-of-bound address err wrongly detected in mcu"); | |
354 | rd_pa_err_fifo[rd_pa_err_fifo_deq] = 1'b0; | |
355 | rd_pa_err_fifo_deq = rd_pa_err_fifo_deq + 1; | |
356 | tmp_rd_picked = 5'b10010; | |
357 | end | |
358 | end | |
359 | default: | |
360 | begin | |
361 | tmp_rd_picked = 5'b00000; | |
362 | `PR_DEBUG("mcu_errmon", `DEBUG, "Warning: Unrecognized read combination detected in MCU[%d].",mcu_num); | |
363 | end | |
364 | endcase | |
365 | ||
366 | if(tmp_rd_picked != 5'b0) | |
367 | begin | |
368 | rd_err_fifo[rd_err_fifo_enq] = {tmp_rd_picked, 8'h0}; | |
369 | rd_err_fifo_enq = rd_err_fifo_enq + 1; | |
370 | end | |
371 | end | |
372 | ||
373 | reg [15:0] tmp_err_detected_code; | |
374 | reg [31:0] err_detected_code; | |
375 | reg set_err_reg; | |
376 | reg [15:0] last_synd; | |
377 | reg [1:0] first_vld; | |
378 | reg skip_initial_clks; | |
379 | reg is_single_channel; | |
380 | reg mcu_ecc_multi_err0_d1; | |
381 | reg mcu_ecc_multi_err1_d1; | |
382 | reg mcu_ecc_single_err0_d1; | |
383 | reg mcu_ecc_single_err1_d1; | |
384 | reg mcu_ecc_multi_err0_d2; | |
385 | reg mcu_ecc_multi_err1_d2; | |
386 | reg mcu_ecc_single_err0_d2; | |
387 | reg mcu_ecc_single_err1_d2; | |
388 | reg mcu_fbdic_rddata_vld_d1; | |
389 | reg mcu_fbdic_crc_error_d1; | |
390 | ||
391 | initial begin | |
392 | tmp_err_detected_code = 16'b0; | |
393 | err_detected_code = 32'b0; | |
394 | last_synd = 16'b0; | |
395 | set_err_reg = 1'b0; | |
396 | first_vld = 2'b0; | |
397 | skip_initial_clks = 1'b1; | |
398 | if($test$plusargs("SNG_CHANNEL")) | |
399 | is_single_channel = 1'b1; | |
400 | else | |
401 | is_single_channel = 1'b0; | |
402 | end | |
403 | ||
404 | always @(posedge (set_err_reg && enabled)) | |
405 | begin | |
406 | @(posedge drl2clk); | |
407 | set_err_reg = 1'b0; | |
408 | end | |
409 | ||
410 | always @(posedge (drl2clk && enabled)) | |
411 | begin | |
412 | mcu_ecc_multi_err0_d1 <= ecc_multi_err0; | |
413 | mcu_ecc_multi_err1_d1 <= ecc_multi_err1; | |
414 | mcu_ecc_single_err0_d1 <= ecc_single_err0; | |
415 | mcu_ecc_single_err1_d1 <= ecc_single_err1; | |
416 | ||
417 | mcu_ecc_multi_err0_d2 <= mcu_ecc_multi_err0_d1; | |
418 | mcu_ecc_multi_err1_d2 <= mcu_ecc_multi_err1_d1; | |
419 | mcu_ecc_single_err0_d2 <= mcu_ecc_single_err0_d1; | |
420 | mcu_ecc_single_err1_d2 <= mcu_ecc_single_err1_d1; | |
421 | ||
422 | mcu_fbdic_rddata_vld_d1 <= fbdic_rddata_vld; | |
423 | mcu_fbdic_crc_error_d1 <= fbdic_crc_error; | |
424 | end | |
425 | ||
426 | always @(posedge (drl2clk && enabled)) | |
427 | begin | |
428 | if(dont_check_error_reg > 0) | |
429 | dont_check_error_reg = dont_check_error_reg - 1'b1; | |
430 | ||
431 | end | |
432 | ||
433 | always @(negedge (drl2clk && enabled)) | |
434 | begin | |
435 | `ifdef SNG_CHANNEL | |
436 | if(mcu_fbdic_rddata_vld_d1 == 1'b1 && first_vld == 2'b0) | |
437 | begin | |
438 | if(dont_check_error_reg <= 5'h15) | |
439 | dont_check_error_reg = dont_check_error_reg + 6; | |
440 | first_vld = first_vld + 1'b1; | |
441 | tmp_err_detected_code = 16'b0; | |
442 | last_synd = 16'b0; | |
443 | ||
444 | if(ecc_single_err0) | |
445 | begin | |
446 | last_synd = readdp0_syndrome; | |
447 | tmp_err_detected_code[3] = 1'b1; | |
448 | end | |
449 | else if(ecc_single_err1 && ~mcu_ecc_single_err1_d1) | |
450 | begin | |
451 | last_synd = readdp1_syndrome; | |
452 | tmp_err_detected_code[3] = 1'b1; | |
453 | end | |
454 | ||
455 | if(ecc_single_err0 && ecc_single_err1) | |
456 | tmp_err_detected_code[15] = 1'b1; | |
457 | ||
458 | if(ecc_multi_err0) | |
459 | begin | |
460 | last_synd = readdp0_syndrome; | |
461 | tmp_err_detected_code[2] = 1'b1; | |
462 | end | |
463 | else if(ecc_multi_err1 && ~mcu_ecc_multi_err1_d1) | |
464 | begin | |
465 | last_synd = readdp1_syndrome; | |
466 | tmp_err_detected_code[2] = 1'b1; | |
467 | end | |
468 | ||
469 | if(ecc_multi_err0 && ecc_multi_err1) | |
470 | tmp_err_detected_code[0] = 1'b1; | |
471 | ||
472 | if(mcu_fbdic_crc_error_d1) | |
473 | tmp_err_detected_code[5] = 1'b1; | |
474 | ||
475 | end | |
476 | else if(mcu_fbdic_rddata_vld_d1 == 1'b1 && first_vld == 2'b1) | |
477 | begin | |
478 | first_vld = first_vld + 1'b1; | |
479 | ||
480 | if(ecc_single_err0 && ~mcu_ecc_single_err0_d1) | |
481 | begin | |
482 | if(tmp_err_detected_code[3:2] == 2'b0) | |
483 | last_synd = readdp0_syndrome; | |
484 | tmp_err_detected_code[3] = 1'b1; | |
485 | end | |
486 | else if(ecc_single_err1 && ~mcu_ecc_single_err1_d1) | |
487 | begin | |
488 | if(tmp_err_detected_code[3:2] == 2'b0) | |
489 | last_synd = readdp1_syndrome; | |
490 | tmp_err_detected_code[3] = 1'b1; | |
491 | end | |
492 | ||
493 | if(ecc_single_err0 && ecc_single_err1) | |
494 | tmp_err_detected_code[15] = 1'b1; | |
495 | ||
496 | if(ecc_multi_err0 && ~mcu_ecc_multi_err0_d1) | |
497 | begin | |
498 | if(tmp_err_detected_code[2] == 1'b0) | |
499 | last_synd = readdp0_syndrome; | |
500 | tmp_err_detected_code[2] = 1'b1; | |
501 | end | |
502 | else if(ecc_multi_err1 && ~mcu_ecc_multi_err1_d1) | |
503 | begin | |
504 | if(tmp_err_detected_code[2] == 1'b0) | |
505 | last_synd = readdp1_syndrome; | |
506 | tmp_err_detected_code[2] = 1'b1; | |
507 | end | |
508 | ||
509 | if(ecc_multi_err0 && ecc_multi_err1) | |
510 | tmp_err_detected_code[14] = 1'b1; | |
511 | ||
512 | if(mcu_fbdic_crc_error_d1) | |
513 | tmp_err_detected_code[5] = 1'b1; | |
514 | ||
515 | if(rdpctl_crc_recov_err == 1'b1) | |
516 | tmp_err_detected_code[7] = 1'b1; | |
517 | ||
518 | if(rdpctl_crc_unrecov_err == 1'b1) | |
519 | tmp_err_detected_code[9] = 1'b1; | |
520 | ||
521 | end | |
522 | else if(mcu_fbdic_rddata_vld_d1 == 1'b1 && first_vld == 2'h2) | |
523 | begin | |
524 | first_vld = first_vld + 1'b1; | |
525 | ||
526 | if(ecc_single_err0) | |
527 | begin | |
528 | if(tmp_err_detected_code[3:2] == 2'b0) | |
529 | last_synd = readdp0_syndrome; | |
530 | tmp_err_detected_code[1] = 1'b1; | |
531 | end | |
532 | else if(ecc_single_err1 && ~mcu_ecc_single_err1_d1) | |
533 | begin | |
534 | if(tmp_err_detected_code[3:2] == 2'b0) | |
535 | last_synd = readdp1_syndrome; | |
536 | tmp_err_detected_code[1] = 1'b1; | |
537 | end | |
538 | ||
539 | if(ecc_single_err0 && ecc_single_err1) | |
540 | tmp_err_detected_code[13] = 1'b1; | |
541 | ||
542 | if(ecc_multi_err0) | |
543 | begin | |
544 | if(tmp_err_detected_code[2] == 1'b0) | |
545 | last_synd = readdp0_syndrome; | |
546 | tmp_err_detected_code[0] = 1'b1; | |
547 | end | |
548 | else if(ecc_multi_err1 && ~mcu_ecc_multi_err1_d1) | |
549 | begin | |
550 | if(tmp_err_detected_code[2] == 1'b0) | |
551 | last_synd = readdp1_syndrome; | |
552 | tmp_err_detected_code[0] = 1'b1; | |
553 | end | |
554 | ||
555 | if(ecc_multi_err0 && ecc_multi_err1) | |
556 | tmp_err_detected_code[12] = 1'b1; | |
557 | ||
558 | if(mcu_fbdic_crc_error_d1) | |
559 | tmp_err_detected_code[5] = 1'b1; | |
560 | ||
561 | if(rdpctl_crc_recov_err == 1'b1) | |
562 | tmp_err_detected_code[7] = 1'b1; | |
563 | ||
564 | if(rdpctl_crc_unrecov_err == 1'b1) | |
565 | tmp_err_detected_code[9] = 1'b1; | |
566 | ||
567 | end | |
568 | else if(mcu_fbdic_rddata_vld_d1 == 1'b1 && first_vld == 2'h3) | |
569 | begin | |
570 | ||
571 | if(ecc_single_err0 && ~mcu_ecc_single_err0_d1) | |
572 | begin | |
573 | if(tmp_err_detected_code[3:0] == 4'b0) | |
574 | last_synd = readdp0_syndrome; | |
575 | tmp_err_detected_code[1] = 1'b1; | |
576 | end | |
577 | else if(ecc_single_err1) | |
578 | begin | |
579 | if(tmp_err_detected_code[3:0] == 4'b0) | |
580 | last_synd = readdp1_syndrome; | |
581 | tmp_err_detected_code[1] = 1'b1; | |
582 | end | |
583 | ||
584 | if(ecc_single_err0 && ecc_single_err1) | |
585 | tmp_err_detected_code[13] = 1'b1; | |
586 | ||
587 | if(ecc_multi_err0 && ~mcu_ecc_multi_err0_d1) | |
588 | begin | |
589 | if({tmp_err_detected_code[2],tmp_err_detected_code[0]} == 2'b0) | |
590 | last_synd = readdp0_syndrome; | |
591 | tmp_err_detected_code[0] = 1'b1; | |
592 | end | |
593 | else if(ecc_multi_err1) | |
594 | begin | |
595 | if({tmp_err_detected_code[2],tmp_err_detected_code[0]} == 2'b0) | |
596 | last_synd = readdp1_syndrome; | |
597 | tmp_err_detected_code[0] = 1'b1; | |
598 | end | |
599 | ||
600 | if(ecc_multi_err0 && ecc_multi_err1) | |
601 | tmp_err_detected_code[12] = 1'b1; | |
602 | ||
603 | if(mcu_fbdic_crc_error_d1) | |
604 | tmp_err_detected_code[5] = 1'b1; | |
605 | ||
606 | if(rdpctl_crc_recov_err == 1'b1) | |
607 | tmp_err_detected_code[7] = 1'b1; | |
608 | ||
609 | if(rdpctl_crc_unrecov_err == 1'b1) | |
610 | tmp_err_detected_code[9] = 1'b1; | |
611 | ||
612 | err_detected_code = {last_synd, tmp_err_detected_code}; | |
613 | set_err_reg = 1'b1; | |
614 | first_vld = 2'b0; | |
615 | end | |
616 | ||
617 | `else | |
618 | ||
619 | if(mcu_fbdic_rddata_vld_d1 == 1'b1 && first_vld == 2'b0) | |
620 | begin | |
621 | if(dont_check_error_reg <= 5'h15) | |
622 | dont_check_error_reg = dont_check_error_reg + 6; | |
623 | first_vld = first_vld + 1'b1; | |
624 | tmp_err_detected_code = 16'b0; | |
625 | last_synd = 16'b0; | |
626 | ||
627 | if(ecc_single_err0) | |
628 | begin | |
629 | last_synd = readdp0_syndrome; | |
630 | tmp_err_detected_code[3] = 1'b1; | |
631 | end | |
632 | else if(ecc_single_err1) | |
633 | begin | |
634 | last_synd = readdp1_syndrome; | |
635 | tmp_err_detected_code[3] = 1'b1; | |
636 | end | |
637 | ||
638 | if(ecc_single_err0 && ecc_single_err1) | |
639 | tmp_err_detected_code[15] = 1'b1; | |
640 | ||
641 | if(ecc_multi_err0) | |
642 | begin | |
643 | last_synd = readdp0_syndrome; | |
644 | tmp_err_detected_code[2] = 1'b1; | |
645 | end | |
646 | else if(ecc_multi_err1) | |
647 | begin | |
648 | last_synd = readdp1_syndrome; | |
649 | tmp_err_detected_code[2] = 1'b1; | |
650 | end | |
651 | ||
652 | if(ecc_multi_err0 && ecc_multi_err1) | |
653 | tmp_err_detected_code[14] = 1'b1; | |
654 | ||
655 | if(mcu_fbdic_crc_error_d1) | |
656 | tmp_err_detected_code[5] = 1'b1; | |
657 | ||
658 | end | |
659 | else if(mcu_fbdic_rddata_vld_d1 == 1'b1 && first_vld == 2'b1) | |
660 | begin | |
661 | first_vld = first_vld + 1'b1; | |
662 | ||
663 | if(ecc_single_err0) | |
664 | begin | |
665 | if(tmp_err_detected_code[3:2] == 2'b0) | |
666 | last_synd = readdp0_syndrome; | |
667 | tmp_err_detected_code[1] = 1'b1; | |
668 | end | |
669 | else if(ecc_single_err1) | |
670 | begin | |
671 | if(tmp_err_detected_code[3:2] == 2'b0) | |
672 | last_synd = readdp1_syndrome; | |
673 | tmp_err_detected_code[1] = 1'b1; | |
674 | end | |
675 | ||
676 | if(ecc_single_err0 && ecc_single_err1) | |
677 | tmp_err_detected_code[13] = 1'b1; | |
678 | ||
679 | if(ecc_multi_err0) | |
680 | begin | |
681 | if(tmp_err_detected_code[2] == 1'b0) | |
682 | last_synd = readdp0_syndrome; | |
683 | tmp_err_detected_code[0] = 1'b1; | |
684 | end | |
685 | else if(ecc_multi_err1) | |
686 | begin | |
687 | if(tmp_err_detected_code[2] == 1'b0) | |
688 | last_synd = readdp1_syndrome; | |
689 | tmp_err_detected_code[0] = 1'b1; | |
690 | end | |
691 | ||
692 | if(ecc_multi_err0 && ecc_multi_err1) | |
693 | tmp_err_detected_code[12] = 1'b1; | |
694 | ||
695 | if(mcu_fbdic_crc_error_d1) | |
696 | tmp_err_detected_code[5] = 1'b1; | |
697 | ||
698 | if(rdpctl_crc_recov_err == 1'b1) | |
699 | tmp_err_detected_code[7] = 1'b1; | |
700 | ||
701 | if(rdpctl_crc_unrecov_err == 1'b1) | |
702 | tmp_err_detected_code[9] = 1'b1; | |
703 | ||
704 | err_detected_code = {last_synd, tmp_err_detected_code}; | |
705 | set_err_reg = 1'b1; | |
706 | first_vld = 2'b0; | |
707 | end | |
708 | `endif | |
709 | end | |
710 | ||
711 | ||
712 | //----------------------------------- | |
713 | // Check for FBU/FBR errors | |
714 | //----------------------------------- | |
715 | ||
716 | reg set_err_reg_fbur; | |
717 | initial set_err_reg_fbur = 1'b0; | |
718 | ||
719 | always @(posedge (drl2clk && enabled)) | |
720 | begin | |
721 | if(fbdic_err_recov && ~mcu_fbdic_rddata_vld_d1) | |
722 | begin | |
723 | if(dont_check_error_reg <= 5'h15) | |
724 | dont_check_error_reg <= dont_check_error_reg + 5; | |
725 | err_detected_code = {16'b0, 16'h80}; | |
726 | set_err_reg_fbur = 1'b1; | |
727 | end | |
728 | ||
729 | if(fbdic_err_unrecov && ~mcu_fbdic_rddata_vld_d1) | |
730 | begin | |
731 | if(dont_check_error_reg <= 5'h15) | |
732 | dont_check_error_reg <= dont_check_error_reg + 5; | |
733 | ||
734 | if(set_err_reg_fbur) | |
735 | err_detected_code[15:0] = err_detected_code[15:0] | 16'h200; | |
736 | else | |
737 | err_detected_code = {16'b0, 16'h200}; | |
738 | set_err_reg_fbur = 1'b1; | |
739 | end | |
740 | ||
741 | if(~fbdic_err_recov && ~fbdic_err_unrecov) | |
742 | set_err_reg_fbur <= 1'b0; | |
743 | end | |
744 | ||
745 | ||
746 | reg [31:0] err_code; | |
747 | reg [12:0] tmp_rd_err_fifo; | |
748 | integer tmp_cnt_s; | |
749 | integer tmp_cnt_m; | |
750 | ||
751 | initial begin | |
752 | err_code = 28'b0; | |
753 | tmp_rd_err_fifo = 13'b0; | |
754 | tmp_cnt_s = 0; | |
755 | tmp_cnt_m = 0; | |
756 | end | |
757 | ||
758 | always @(posedge (set_err_reg && enabled) or posedge (set_err_reg_fbur && enabled)) | |
759 | begin | |
760 | err_code = err_detected_code; | |
761 | tmp_rd_err_fifo = 13'b0; | |
762 | if(~set_err_reg_fbur) | |
763 | begin | |
764 | tmp_rd_err_fifo = rd_err_fifo[rd_err_fifo_deq]; | |
765 | rd_err_fifo_deq = rd_err_fifo_deq + 1'b1; | |
766 | end | |
767 | ||
768 | if(tmp_rd_err_fifo[12]) | |
769 | err_code[11] = 1'b1; | |
770 | ||
771 | // assign rdpctl_err_retry_reg[36:0] = {rdpctl_retry_reg_valid, rdpctl_err_retry2_reg[17:0],rdpctl_err_retry1_reg[17:0]}; | |
772 | ||
773 | if(tmp_rd_err_fifo[12:8] == 5'b00100) // retry rd | |
774 | begin | |
775 | if(mcu_err_retry_reg[63] != 1'b1) | |
776 | begin | |
777 | if(mcu_err_retry_reg[1:0] == 2'b0) | |
778 | begin | |
779 | if(err_code[2] || err_code[0] || err_code[14] || err_code[12]) | |
780 | begin | |
781 | mcu_err_retry_reg[1:0] = 2'b11; //ue | |
782 | mcu_err_retry_reg[17:2] = err_code[31:16]; | |
783 | mcu_err_retry_reg[63] = 1'b1; | |
784 | end | |
785 | else if(err_code[3] || err_code[1] || err_code[15] || err_code[13]) | |
786 | begin | |
787 | mcu_err_retry_reg[1:0] = 2'b10; //ce | |
788 | mcu_err_retry_reg[17:2] = err_code[31:16]; | |
789 | mcu_err_retry_reg[63] = 1'b1; | |
790 | end | |
791 | else | |
792 | mcu_err_retry_reg[1:0] = 2'b01; //no error | |
793 | end | |
794 | else if(mcu_err_retry_reg[33:32] == 2'b0) | |
795 | begin | |
796 | if(err_code[2] || err_code[0] || err_code[14] || err_code[12]) | |
797 | begin | |
798 | mcu_err_retry_reg[33:32] = 2'b11; //ue | |
799 | mcu_err_retry_reg[49:34] = err_code[31:16]; | |
800 | mcu_err_retry_reg[63] = 1'b1; | |
801 | end | |
802 | else if(err_code[3] || err_code[1] || err_code[15] || err_code[13]) | |
803 | begin | |
804 | mcu_err_retry_reg[33:32] = 2'b10; //ce | |
805 | mcu_err_retry_reg[49:34] = err_code[31:16]; | |
806 | mcu_err_retry_reg[63] = 1'b1; | |
807 | end | |
808 | else | |
809 | mcu_err_retry_reg[33:32] = 2'b01; //no error | |
810 | end | |
811 | end | |
812 | end // retry rd | |
813 | else | |
814 | begin // update ESR | |
815 | if(err_code[5] && ({err_code[9], err_code[7]} == 2'b0)) | |
816 | begin | |
817 | if(tmp_rd_err_fifo[12:8] == 5'b00001) // scrub rd | |
818 | begin | |
819 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU[%d] *** N2 T.O 1.0 BUG 113430 ***",mcu_num); | |
820 | end | |
821 | end | |
822 | if(~(err_code[5] && ({err_code[9], err_code[7]} == 2'b0))) | |
823 | begin | |
824 | if(mcu_err_status_reg[15:0] == 16'b0) | |
825 | begin | |
826 | if(err_code[11]) | |
827 | begin | |
828 | if(mcu_err_status_reg[57] == 1'b0) | |
829 | #0 mcu_err_status_reg[57] = 1'b1; | |
830 | else | |
831 | #0 mcu_err_status_reg[56] = 1'b1; | |
832 | end | |
833 | ||
834 | if(err_code[9]) begin | |
835 | if(mcu_err_status_reg[55] == 1'b1) | |
836 | #0 mcu_err_status_reg[63] = 1'b1; | |
837 | else | |
838 | #0 mcu_err_status_reg[55] = 1'b1; | |
839 | end | |
840 | ||
841 | if(err_code[7]) begin | |
842 | if(mcu_err_status_reg[54] == 1'b1) | |
843 | #0 mcu_err_status_reg[62] = 1'b1; | |
844 | else | |
845 | #0 mcu_err_status_reg[54] = 1'b1; | |
846 | end | |
847 | ||
848 | if(tmp_rd_err_fifo[12:8] == 5'b00001) // scrub rd | |
849 | begin | |
850 | if(err_code[3] || err_code[1] || err_code[15] || err_code[13]) | |
851 | #0 mcu_err_status_reg[59] = 1'b1; | |
852 | ||
853 | if(err_code[2] || err_code[0] || err_code[14] || err_code[12]) | |
854 | #0 mcu_err_status_reg[58] = 1'b1; | |
855 | ||
856 | if((err_code[3] || err_code[1] || err_code[15] || err_code[13]) && (err_code[2] || err_code[0] || err_code[14] || err_code[12])) | |
857 | begin | |
858 | // CE & UE in same cycle | |
859 | if((err_code[3] && err_code[2]) || (err_code[1] && err_code[0])) | |
860 | #0 mcu_err_status_reg[62] = 1'b1; | |
861 | ||
862 | // UE followed by CE | |
863 | if(err_code[2] && err_code[1]) | |
864 | #0 mcu_err_status_reg[62] = 1'b1; | |
865 | end | |
866 | ||
867 | tmp_cnt_s = 0; | |
868 | tmp_cnt_s = err_code[3] + err_code[1] + err_code[15] + err_code[13]; | |
869 | if(tmp_cnt_s > 1) | |
870 | #0 mcu_err_status_reg[62] = 1'b1; | |
871 | ||
872 | tmp_cnt_m = 0; | |
873 | tmp_cnt_m = err_code[2] + err_code[0] + err_code[14] + err_code[12]; | |
874 | if(tmp_cnt_m > 1) | |
875 | #0 mcu_err_status_reg[63] = 1'b1; | |
876 | ||
877 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
878 | end | |
879 | ||
880 | if(tmp_rd_err_fifo[12:8] == 5'b00010 || tmp_rd_err_fifo[12:8] == 5'b01100) // normal read | |
881 | begin | |
882 | if(err_code[3] || err_code[1] || err_code[15] || err_code[13]) | |
883 | #0 mcu_err_status_reg[61] = 1'b1; | |
884 | ||
885 | if(err_code[2] || err_code[0] || err_code[14] || err_code[12]) | |
886 | #0 mcu_err_status_reg[60] = 1'b1; | |
887 | ||
888 | if((err_code[3] || err_code[1] || err_code[15] || err_code[13]) && (err_code[2] || err_code[0] || err_code[14] || err_code[12])) | |
889 | begin | |
890 | // UE and CE in same cycle | |
891 | if((err_code[3] && err_code[2]) || (err_code[1] && err_code[0])) | |
892 | #0 mcu_err_status_reg[62] = 1'b1; | |
893 | ||
894 | // UE followed by CE | |
895 | if(err_code[2] && err_code[1]) | |
896 | #0 mcu_err_status_reg[62] = 1'b1; | |
897 | end | |
898 | ||
899 | tmp_cnt_s = 0; | |
900 | tmp_cnt_s = err_code[3] + err_code[1] + err_code[15] + err_code[13]; | |
901 | if(tmp_cnt_s > 1) | |
902 | #0 mcu_err_status_reg[62] = 1'b1; | |
903 | ||
904 | tmp_cnt_m = 0; | |
905 | tmp_cnt_m = err_code[2] + err_code[0] + err_code[14] + err_code[12]; | |
906 | if(tmp_cnt_m > 1) | |
907 | #0 mcu_err_status_reg[63] = 1'b1; | |
908 | ||
909 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
910 | end | |
911 | end | |
912 | else // if(status_reg[15:0] != 0) | |
913 | begin | |
914 | if(err_code[11]) | |
915 | begin | |
916 | if(mcu_err_status_reg[57] == 1'b1) | |
917 | #0 mcu_err_status_reg[56] = 1'b1; | |
918 | else | |
919 | #0 mcu_err_status_reg[57] = 1'b1; | |
920 | ||
921 | if(((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) && (mcu_err_status_reg[57] != 1'b1)) | |
922 | begin | |
923 | #0 mcu_err_status_reg[57] = 1'b1; | |
924 | //mcu_err_status_reg[15:0] = err_code[31:16]; syndrome not captured on oob errors | |
925 | end | |
926 | ||
927 | if(((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) && (mcu_err_status_reg[57] != 1'b1)) | |
928 | begin | |
929 | #0 mcu_err_status_reg[57] = 1'b1; | |
930 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
931 | end | |
932 | ||
933 | #0 mcu_err_status_reg[57] = 1'b1; | |
934 | end | |
935 | ||
936 | if(err_code[9]) | |
937 | begin | |
938 | if((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) | |
939 | #0 mcu_err_status_reg[63] = 1'b1; | |
940 | ||
941 | if(mcu_err_status_reg[57] && mcu_err_status_reg[55] != 1'b1) | |
942 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
943 | ||
944 | if(((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) && (mcu_err_status_reg[55] != 1'b1)) | |
945 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
946 | ||
947 | #0 mcu_err_status_reg[55] = 1'b1; | |
948 | end | |
949 | ||
950 | if(err_code[7]) | |
951 | begin | |
952 | if(((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) && (mcu_err_status_reg[54] != 1'b1)) | |
953 | #0 mcu_err_status_reg[62] = 1'b1; | |
954 | ||
955 | if(mcu_err_status_reg[57] == 1'b1 && mcu_err_status_reg[54] != 1'b0) | |
956 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
957 | ||
958 | if((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) | |
959 | #0 mcu_err_status_reg[62] = 1'b1; | |
960 | ||
961 | #0 mcu_err_status_reg[54] = 1'b1; | |
962 | end | |
963 | ||
964 | if(tmp_rd_err_fifo[12:8] == 5'b00001) // scrub read | |
965 | begin | |
966 | if(err_code[3] || err_code[1] || err_code[15] || err_code[13]) | |
967 | begin | |
968 | if(((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) && mcu_err_status_reg[59] != 1'b1) | |
969 | #0 mcu_err_status_reg[62] = 1'b1; | |
970 | ||
971 | if(mcu_err_status_reg[57] == 1'b1 && (|({mcu_err_status_reg[59],mcu_err_status_reg[60],mcu_err_status_reg[58]}) != 1'b1)) | |
972 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
973 | ||
974 | if((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) | |
975 | #0 mcu_err_status_reg[62] = 1'b1; | |
976 | ||
977 | #0 mcu_err_status_reg[59] = 1'b1; | |
978 | ||
979 | tmp_cnt_s = 0; | |
980 | tmp_cnt_s = err_code[3] + err_code[1] + err_code[15] + err_code[13]; | |
981 | if(tmp_cnt_s > 1) | |
982 | #0 mcu_err_status_reg[62] = 1'b1; | |
983 | ||
984 | end | |
985 | ||
986 | if(err_code[2] || err_code[0] || err_code[14] || err_code[12]) | |
987 | begin | |
988 | if((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) | |
989 | #0 mcu_err_status_reg[63] = 1'b1; | |
990 | ||
991 | if(mcu_err_status_reg[57] == 1'b1 && (mcu_err_status_reg[58] != 1'b1)) | |
992 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
993 | ||
994 | if(((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) && (|({mcu_err_status_reg[58],mcu_err_status_reg[60]}) != 1'b1)) | |
995 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
996 | ||
997 | #0 mcu_err_status_reg[58] = 1'b1; | |
998 | ||
999 | tmp_cnt_m = 0; | |
1000 | tmp_cnt_m = err_code[2] + err_code[0] + err_code[14] + err_code[12]; | |
1001 | if(tmp_cnt_m > 1) | |
1002 | #0 mcu_err_status_reg[63] = 1'b1; | |
1003 | ||
1004 | end | |
1005 | ||
1006 | if((err_code[3] || err_code[1] || err_code[15] || err_code[13]) && (err_code[2] || err_code[0] || err_code[14] || err_code[12])) | |
1007 | #0 mcu_err_status_reg[62] = 1'b1; | |
1008 | end | |
1009 | ||
1010 | if(tmp_rd_err_fifo[12:8] == 5'b00010 || tmp_rd_err_fifo[12:8] == 5'b01100) // normal read | |
1011 | begin | |
1012 | if(err_code[3] || err_code[1] || err_code[15] || err_code[13]) | |
1013 | begin | |
1014 | if(((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) && mcu_err_status_reg[61] != 1'b1) | |
1015 | #0 mcu_err_status_reg[62] = 1'b1; | |
1016 | ||
1017 | if(mcu_err_status_reg[57] == 1'b1 && (|({mcu_err_status_reg[61],mcu_err_status_reg[60],mcu_err_status_reg[58]}) != 1'b1)) | |
1018 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
1019 | ||
1020 | if((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) | |
1021 | #0 mcu_err_status_reg[62] = 1'b1; | |
1022 | ||
1023 | #0 mcu_err_status_reg[61] = 1'b1; | |
1024 | ||
1025 | tmp_cnt_s = 0; | |
1026 | tmp_cnt_s = err_code[3] + err_code[1] + err_code[15] + err_code[13]; | |
1027 | if(tmp_cnt_s > 1) | |
1028 | #0 mcu_err_status_reg[62] = 1'b1; | |
1029 | ||
1030 | end | |
1031 | ||
1032 | if(err_code[2] || err_code[0] || err_code[14] || err_code[12]) | |
1033 | begin | |
1034 | if((|({mcu_err_status_reg[58],mcu_err_status_reg[60],mcu_err_status_reg[55]})) == 1'b1) | |
1035 | #0 mcu_err_status_reg[63] = 1'b1; | |
1036 | ||
1037 | if(mcu_err_status_reg[57] == 1'b1 && (|({mcu_err_status_reg[60],mcu_err_status_reg[58]}) != 1'b1)) | |
1038 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
1039 | ||
1040 | if(((|({mcu_err_status_reg[59],mcu_err_status_reg[61],mcu_err_status_reg[54]})) == 1'b1) && (|({mcu_err_status_reg[60],mcu_err_status_reg[58]}) != 1'b1)) | |
1041 | #0 mcu_err_status_reg[15:0] = err_code[31:16]; | |
1042 | ||
1043 | #0 mcu_err_status_reg[60] = 1'b1; | |
1044 | ||
1045 | tmp_cnt_m = 0; | |
1046 | tmp_cnt_m = err_code[2] + err_code[0] + err_code[14] + err_code[12]; | |
1047 | if(tmp_cnt_m > 1) | |
1048 | #0 mcu_err_status_reg[63] = 1'b1; | |
1049 | ||
1050 | end | |
1051 | ||
1052 | if((err_code[3] || err_code[1] || err_code[15] || err_code[13]) && (err_code[2] || err_code[0] || err_code[14] || err_code[12])) | |
1053 | #0 mcu_err_status_reg[62] = 1'b1; | |
1054 | end | |
1055 | end | |
1056 | end | |
1057 | end | |
1058 | end | |
1059 | ||
1060 | //----------------------------------- | |
1061 | // Clear ESR on ucb_writes | |
1062 | //----------------------------------- | |
1063 | always @ (posedge (drl2clk && enabled)) | |
1064 | begin | |
1065 | ||
1066 | if ( ( rdpctl_fbr_error_in == 0 && rdpctl_fbu_error_in == 0 && rdpctl_dac_error_in == 0 && rdpctl_dau_error_in == 0 && | |
1067 | rdpctl_dsc_error_in == 0 && rdpctl_dsu_error_in == 0 && rdpctl_dbu_error_in == 0 && rdpctl_meb_error_in == 0 && | |
1068 | rdpctl_mec_error_in == 0 && rdpctl_meu_error_in == 0 ) && ( drif_err_sts_reg_ld == 1 && drif_ucb_addr[12:0] == 13'h280 ) ) | |
1069 | begin | |
1070 | if(dont_check_error_reg < 5'h15) | |
1071 | dont_check_error_reg = dont_check_error_reg + 2; | |
1072 | ||
1073 | mcu_err_status_reg[15:0] = drif_ucb_data[15:0]; | |
1074 | mcu_err_status_reg[63:54] = (mcu_err_status_reg[63:54] & (~drif_ucb_data[63:54])); | |
1075 | end | |
1076 | ||
1077 | end | |
1078 | ||
1079 | //------------------------------------------------------- | |
1080 | // Check ESR and ERR | |
1081 | //------------------------------------------------------- | |
1082 | always @ (posedge (drl2clk && enabled)) | |
1083 | begin | |
1084 | if(dont_check_error_reg == 5'b0) begin | |
1085 | if({mcu_err_status_reg[63:54], mcu_err_status_reg[15:0]} !== rdpctl_err_sts_reg) | |
1086 | `PR_WARN("mcu_errmon", `WARN, "Inconsistent state of MCU[%d] ESR\n\tExpected ESR data is %x, Actual ESR data received from drif is %x",mcu_num, {mcu_err_status_reg[63:54], mcu_err_status_reg[15:0]}, rdpctl_err_sts_reg); | |
1087 | end | |
1088 | end | |
1089 | ||
1090 | always @ (posedge (drl2clk && enabled)) | |
1091 | begin | |
1092 | if(dont_check_error_reg == 5'b0) begin | |
1093 | if({mcu_err_retry_reg[63], mcu_err_retry_reg[49:32], mcu_err_retry_reg[17:0]} !== rdpctl_err_retry_reg[36:0]) begin | |
1094 | `PR_WARN("mcu_errmon", `WARN, "MISMATCH: ERR not getting updated correctly in MCU[%d]\n\tExpected ERR data is %x, Actual ERR data received from drif is %x",mcu_num, {mcu_err_retry_reg[63],mcu_num, mcu_err_retry_reg[49:32], mcu_err_retry_reg[17:0]}, rdpctl_err_retry_reg); | |
1095 | end | |
1096 | end | |
1097 | end | |
1098 | ||
1099 | //------------------------------------------------------- | |
1100 | // Warning Messages | |
1101 | //------------------------------------------------------- | |
1102 | always @ (rdpctl_err_sts_reg) | |
1103 | if (enabled) | |
1104 | begin | |
1105 | `ifdef MCUSAT | |
1106 | if(rdpctl_err_sts_reg[25] == 1'b1) | |
1107 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Multiple Uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1108 | if(rdpctl_err_sts_reg[24] == 1'b1) | |
1109 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Multiple Correctable err detected in MCU[%d] ESR",mcu_num); | |
1110 | if(rdpctl_err_sts_reg[23] == 1'b1) | |
1111 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Correctable err detected in MCU[%d] ESR",mcu_num); | |
1112 | if(rdpctl_err_sts_reg[22] == 1'b1) | |
1113 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1114 | if(rdpctl_err_sts_reg[21] == 1'b1) | |
1115 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Scrub correctable err detected in MCU[%d] ESR",mcu_num); | |
1116 | if(rdpctl_err_sts_reg[20] == 1'b1) | |
1117 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Scrub uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1118 | if(rdpctl_err_sts_reg[19] == 1'b1) | |
1119 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Out-of-bound address err detected in MCU[%d] ESR",mcu_num); | |
1120 | if(rdpctl_err_sts_reg[18] == 1'b1) | |
1121 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Multiple Out-of-bound address err detected in MCU[%d] ESR",mcu_num); | |
1122 | if(rdpctl_err_sts_reg[17] == 1'b1) | |
1123 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: FBDIMM UnRecoverable err detected in MCU[%d] ESR",mcu_num); | |
1124 | if(rdpctl_err_sts_reg[16] == 1'b1) | |
1125 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: FBDIMM Recoverable err detected in MCU[%d] ESR",mcu_num); | |
1126 | `else | |
1127 | if(halt_on_mcu_err == 0) | |
1128 | begin | |
1129 | if(rdpctl_err_sts_reg[25] == 1'b1) | |
1130 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Multiple Uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1131 | if(rdpctl_err_sts_reg[24] == 1'b1) | |
1132 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Multiple Correctable err detected in MCU[%d] ESR",mcu_num); | |
1133 | if(rdpctl_err_sts_reg[23] == 1'b1) | |
1134 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Correctable err detected in MCU[%d] ESR",mcu_num); | |
1135 | if(rdpctl_err_sts_reg[22] == 1'b1) | |
1136 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1137 | if(rdpctl_err_sts_reg[21] == 1'b1) | |
1138 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Scrub correctable err detected in MCU[%d] ESR",mcu_num); | |
1139 | if(rdpctl_err_sts_reg[20] == 1'b1) | |
1140 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Scrub uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1141 | if(rdpctl_err_sts_reg[19] == 1'b1) | |
1142 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Out-of-bound address err detected in MCU[%d] ESR",mcu_num); | |
1143 | if(rdpctl_err_sts_reg[18] == 1'b1) | |
1144 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Multiple Out-of-bound address err detected in MCU[%d] ESR",mcu_num); | |
1145 | if(rdpctl_err_sts_reg[17] == 1'b1) | |
1146 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: FBDIMM UnRecoverable err detected in MCU[%d] ESR",mcu_num); | |
1147 | if(rdpctl_err_sts_reg[16] == 1'b1) | |
1148 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: FBDIMM Recoverable err detected in MCU[%d] ESR",mcu_num); | |
1149 | end | |
1150 | else | |
1151 | begin | |
1152 | if(rdpctl_err_sts_reg[25] == 1'b1) | |
1153 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Multiple Uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1154 | if(rdpctl_err_sts_reg[24] == 1'b1) | |
1155 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Multiple Correctable err detected in MCU[%d] ESR",mcu_num); | |
1156 | if(rdpctl_err_sts_reg[23] == 1'b1) | |
1157 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Correctable err detected in MCU[%d] ESR",mcu_num); | |
1158 | if(rdpctl_err_sts_reg[22] == 1'b1) | |
1159 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1160 | if(rdpctl_err_sts_reg[21] == 1'b1) | |
1161 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Scrub correctable err detected in MCU[%d] ESR",mcu_num); | |
1162 | if(rdpctl_err_sts_reg[20] == 1'b1) | |
1163 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Scrub uncorrectable err detected in MCU[%d] ESR",mcu_num); | |
1164 | if(rdpctl_err_sts_reg[19] == 1'b1) | |
1165 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Out-of-bound address err detected in MCU[%d] ESR",mcu_num); | |
1166 | if(rdpctl_err_sts_reg[18] == 1'b1) | |
1167 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: Multiple Out-of-bound address err detected in MCU[%d] ESR",mcu_num); | |
1168 | if(rdpctl_err_sts_reg[17] == 1'b1) | |
1169 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: FBDIMM UnRecoverable err detected in MCU[%d] ESR",mcu_num); | |
1170 | if(rdpctl_err_sts_reg[16] == 1'b1) | |
1171 | `PR_ERROR("mcu_errmon", `ERROR, "INFO: FBDIMM Recoverable err detected in MCU[%d] ESR",mcu_num); | |
1172 | end | |
1173 | `endif | |
1174 | ||
1175 | end | |
1176 | ||
1177 | always @ (rdpctl_err_retry_reg) | |
1178 | if (enabled) | |
1179 | begin | |
1180 | if(rdpctl_err_retry_reg[1:0] == 2'b01) | |
1181 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: No err detected on 1st retry read in MCU[%d].",mcu_num); | |
1182 | if(rdpctl_err_retry_reg[1:0] == 2'b10) | |
1183 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Correctable err detected on 1st retry read in MCU[%d].",mcu_num); | |
1184 | if(rdpctl_err_retry_reg[1:0] == 2'b11) | |
1185 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Un-Correctable err detected on 1st retry read in MCU[%d].",mcu_num); | |
1186 | if(rdpctl_err_retry_reg[33:32] == 2'b01) | |
1187 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: No err detected on 2st retry read in MCU[%d].",mcu_num); | |
1188 | if(rdpctl_err_retry_reg[33:32] == 2'b10) | |
1189 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Correctable err detected on 2st retry read in MCU[%d].",mcu_num); | |
1190 | if(rdpctl_err_retry_reg[33:32] == 2'b11) | |
1191 | `PR_DEBUG("mcu_errmon", `DEBUG, "INFO: Un-Correctable err detected on 2st retry read in MCU[%d].",mcu_num); | |
1192 | end | |
1193 | ||
1194 | ||
1195 | //----------------------------------- | |
1196 | // Disable mcu_errmon during Warm Reset | |
1197 | //----------------------------------- | |
1198 | `ifdef MCUSAT | |
1199 | always @ (posedge rst_wmr_protect) | |
1200 | begin | |
1201 | if (!($test$plusargs("mcu_errmon_disable"))) | |
1202 | enabled = 1'b0; | |
1203 | end | |
1204 | ||
1205 | always @ (negedge rst_wmr_protect) | |
1206 | begin | |
1207 | if (!($test$plusargs("mcu_errmon_disable"))) | |
1208 | enabled = 1'b1; | |
1209 | end | |
1210 | `else | |
1211 | always @ (flush_reset_complete) | |
1212 | begin | |
1213 | if (flush_reset_complete == 1'b0) begin | |
1214 | if (!($test$plusargs("mcu_errmon_disable"))) begin | |
1215 | enabled = 1'b0; | |
1216 | end | |
1217 | end | |
1218 | ||
1219 | mcu_err_status_reg = 64'h0; | |
1220 | mcu_err_retry_reg = 64'h0; | |
1221 | ||
1222 | if (flush_reset_complete == 1'b1) | |
1223 | if (!($test$plusargs("mcu_errmon_disable"))) | |
1224 | enabled = 1'b1; | |
1225 | end | |
1226 | `endif | |
1227 | ||
1228 | /* | |
1229 | ||
1230 | // BEGIN | |
1231 | ||
1232 | // quadword is an integer that tells simulator to insert error on one of the 4 quad words when in dual channel mode | |
1233 | // note: all 4 MCUs see the same quadword 'runtime argument' | |
1234 | ||
1235 | integer quadword; | |
1236 | always @(tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.amb_dram_err_inj.quadword) | |
1237 | quadword = tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.amb_dram_err_inj.quadword ; | |
1238 | ||
1239 | ||
1240 | // MCU0 | |
1241 | reg mcu0_sshot=0; | |
1242 | always @( posedge `MCU0.drif.drif_sshot_err_reg) mcu0_sshot=1; | |
1243 | // check DSC / DSU | |
1244 | always @( posedge `MCU0.rdpctl.rdpctl_dsc_error or posedge `MCU0.rdpctl.rdpctl_dsu_error ) | |
1245 | begin | |
1246 | if (!($test$plusargs("SNG_CHANNEL"))) | |
1247 | begin // in dual channel mode | |
1248 | if ( ( ( quadword==1 || mcu0_sshot ) && (`MCU0.rdpctl_err_addr_reg[1:0]==2'b01 ) ) || | |
1249 | ( ( quadword==2 ) && (`MCU0.rdpctl_err_addr_reg[1:0]==2'b00 ) ) || | |
1250 | ( ( quadword==3 ) && (`MCU0.rdpctl_err_addr_reg[1:0]==2'b11 ) ) || | |
1251 | ( ( quadword==4 ) && (`MCU0.rdpctl_err_addr_reg[1:0]==2'b10 ) ) ) | |
1252 | begin | |
1253 | `PR_DEBUG ("mcu_errmon", `DEBUG, "MCU0: err address register @ UCB 13\'h0288 incorrectly logs error address for scrub (quadword logging is reversed) *** N2 TO 2.0 BUG 120427 ***"); | |
1254 | mcu0_sshot=0; | |
1255 | end | |
1256 | else | |
1257 | `PR_ERROR ("mcu_errmon", `ERROR, "MCU0: err address register @ UCB 13\'h0288 did *NOT* log error address for scrub correctly!"); | |
1258 | end | |
1259 | end | |
1260 | ||
1261 | ||
1262 | // MCU1 | |
1263 | reg mcu1_sshot=0; | |
1264 | always @( posedge `MCU1.drif.drif_sshot_err_reg) mcu1_sshot=1; | |
1265 | // check DSC / DSU | |
1266 | always @( posedge `MCU1.rdpctl.rdpctl_dsc_error or posedge `MCU1.rdpctl.rdpctl_dsu_error ) | |
1267 | begin | |
1268 | if (!($test$plusargs("SNG_CHANNEL"))) | |
1269 | begin // in dual channel mode | |
1270 | if ( ( ( quadword==1 || mcu1_sshot ) && (`MCU1.rdpctl_err_addr_reg[1:0]==2'b01 ) ) || | |
1271 | ( ( quadword==2 ) && (`MCU1.rdpctl_err_addr_reg[1:0]==2'b00 ) ) || | |
1272 | ( ( quadword==3 ) && (`MCU1.rdpctl_err_addr_reg[1:0]==2'b11 ) ) || | |
1273 | ( ( quadword==4 ) && (`MCU1.rdpctl_err_addr_reg[1:0]==2'b10 ) ) ) | |
1274 | begin | |
1275 | `PR_DEBUG ("mcu_errmon", `DEBUG, "MCU1: err address register @ UCB 13\'h0288 incorrectly logs error address for scrub (quadword logging is reversed) *** N2 TO 2.0 BUG 120427 ***"); | |
1276 | mcu1_sshot=0; | |
1277 | end | |
1278 | else | |
1279 | `PR_ERROR ("mcu_errmon", `ERROR, "MCU1: err address register @ UCB 13\'h0288 did *NOT* log error address for scrub correctly!"); | |
1280 | end | |
1281 | end | |
1282 | ||
1283 | ||
1284 | // MCU2 | |
1285 | reg mcu2_sshot=0; | |
1286 | always @( posedge `MCU2.drif.drif_sshot_err_reg) mcu2_sshot=1; | |
1287 | // check DSC / DSU | |
1288 | always @( posedge `MCU2.rdpctl.rdpctl_dsc_error or posedge `MCU2.rdpctl.rdpctl_dsu_error ) | |
1289 | begin | |
1290 | if (!($test$plusargs("SNG_CHANNEL"))) | |
1291 | begin // in dual channel mode | |
1292 | if ( ( ( quadword==1 || mcu2_sshot ) && (`MCU2.rdpctl_err_addr_reg[1:0]==2'b01 ) ) || | |
1293 | ( ( quadword==2 ) && (`MCU2.rdpctl_err_addr_reg[1:0]==2'b00 ) ) || | |
1294 | ( ( quadword==3 ) && (`MCU2.rdpctl_err_addr_reg[1:0]==2'b11 ) ) || | |
1295 | ( ( quadword==4 ) && (`MCU2.rdpctl_err_addr_reg[1:0]==2'b10 ) ) ) | |
1296 | begin | |
1297 | `PR_DEBUG ("mcu_errmon", `DEBUG, "MCU2: err address register @ UCB 13\'h0288 incorrectly logs error address for scrub (quadword logging is reversed) *** N2 TO 2.0 BUG 120427 ***"); | |
1298 | mcu2_sshot=0; | |
1299 | end | |
1300 | else | |
1301 | `PR_ERROR ("mcu_errmon", `ERROR, "MCU2: err address register @ UCB 13\'h0288 did *NOT* log error address for scrub correctly!"); | |
1302 | end | |
1303 | end | |
1304 | ||
1305 | ||
1306 | // MCU3 | |
1307 | reg mcu3_sshot=0; | |
1308 | always @( posedge `MCU3.drif.drif_sshot_err_reg) mcu3_sshot=1; | |
1309 | // check DSC / DSU | |
1310 | always @( posedge `MCU3.rdpctl.rdpctl_dsc_error or posedge `MCU3.rdpctl.rdpctl_dsu_error ) | |
1311 | begin | |
1312 | if (!($test$plusargs("SNG_CHANNEL"))) | |
1313 | begin // in dual channel mode | |
1314 | if ( ( ( quadword==1 || mcu3_sshot ) && (`MCU3.rdpctl_err_addr_reg[1:0]==2'b01 ) ) || | |
1315 | ( ( quadword==2 ) && (`MCU3.rdpctl_err_addr_reg[1:0]==2'b00 ) ) || | |
1316 | ( ( quadword==3 ) && (`MCU3.rdpctl_err_addr_reg[1:0]==2'b11 ) ) || | |
1317 | ( ( quadword==4 ) && (`MCU3.rdpctl_err_addr_reg[1:0]==2'b10 ) ) ) | |
1318 | begin | |
1319 | `PR_DEBUG ("mcu_errmon", `DEBUG, "MCU3: err address register @ UCB 13\'h0288 incorrectly logs error address for scrub (quadword logging is reversed) *** N2 TO 2.0 BUG 120427 ***"); | |
1320 | mcu3_sshot=0; | |
1321 | end | |
1322 | else | |
1323 | `PR_ERROR ("mcu_errmon", `ERROR, "MCU3: err address register @ UCB 13\'h0288 did *NOT* log error address for scrub correctly!"); | |
1324 | end | |
1325 | end | |
1326 | ||
1327 | ||
1328 | ||
1329 | // END | |
1330 | ||
1331 | */ | |
1332 | ||
1333 | // added | |
1334 | ||
1335 | wire mcu0_esr_dac = `MCU0.rdpctl.rdpctl_dac_error_in & `MCU0.rdpctl.rdpctl_dac_error_en; | |
1336 | wire mcu1_esr_dac = `MCU1.rdpctl.rdpctl_dac_error_in & `MCU1.rdpctl.rdpctl_dac_error_en; | |
1337 | wire mcu2_esr_dac = `MCU2.rdpctl.rdpctl_dac_error_in & `MCU2.rdpctl.rdpctl_dac_error_en; | |
1338 | wire mcu3_esr_dac = `MCU3.rdpctl.rdpctl_dac_error_in & `MCU3.rdpctl.rdpctl_dac_error_en; | |
1339 | ||
1340 | wire mcu0_esr_dau = `MCU0.rdpctl.rdpctl_dau_error_in & `MCU0.rdpctl.rdpctl_dau_error_en; | |
1341 | wire mcu1_esr_dau = `MCU1.rdpctl.rdpctl_dau_error_in & `MCU1.rdpctl.rdpctl_dau_error_en; | |
1342 | wire mcu2_esr_dau = `MCU2.rdpctl.rdpctl_dau_error_in & `MCU2.rdpctl.rdpctl_dau_error_en; | |
1343 | wire mcu3_esr_dau = `MCU3.rdpctl.rdpctl_dau_error_in & `MCU3.rdpctl.rdpctl_dau_error_en; | |
1344 | ||
1345 | wire mcu0_esr_dsc = `MCU0.rdpctl.rdpctl_dsc_error_in & `MCU0.rdpctl.rdpctl_dsc_error_en; | |
1346 | wire mcu1_esr_dsc = `MCU1.rdpctl.rdpctl_dsc_error_in & `MCU1.rdpctl.rdpctl_dsc_error_en; | |
1347 | wire mcu2_esr_dsc = `MCU2.rdpctl.rdpctl_dsc_error_in & `MCU2.rdpctl.rdpctl_dsc_error_en; | |
1348 | wire mcu3_esr_dsc = `MCU3.rdpctl.rdpctl_dsc_error_in & `MCU3.rdpctl.rdpctl_dsc_error_en; | |
1349 | ||
1350 | wire mcu0_esr_dsu = `MCU0.rdpctl.rdpctl_dsu_error_in & `MCU0.rdpctl.rdpctl_dsu_error_en; | |
1351 | wire mcu1_esr_dsu = `MCU1.rdpctl.rdpctl_dsu_error_in & `MCU1.rdpctl.rdpctl_dsu_error_en; | |
1352 | wire mcu2_esr_dsu = `MCU2.rdpctl.rdpctl_dsu_error_in & `MCU2.rdpctl.rdpctl_dsu_error_en; | |
1353 | wire mcu3_esr_dsu = `MCU3.rdpctl.rdpctl_dsu_error_in & `MCU3.rdpctl.rdpctl_dsu_error_en; | |
1354 | ||
1355 | ||
1356 | reg mcu0_l2t0_data_vld_r0_delay; | |
1357 | reg mcu0_l2t1_data_vld_r0_delay; | |
1358 | reg mcu1_l2t0_data_vld_r0_delay; | |
1359 | reg mcu1_l2t1_data_vld_r0_delay; | |
1360 | reg mcu2_l2t0_data_vld_r0_delay; | |
1361 | reg mcu2_l2t1_data_vld_r0_delay; | |
1362 | reg mcu3_l2t0_data_vld_r0_delay; | |
1363 | reg mcu3_l2t1_data_vld_r0_delay; | |
1364 | ||
1365 | `define DELAY 3 | |
1366 | initial mcu0_l2t0_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU0.mcu_l2t0_data_vld_r0; | |
1367 | initial mcu0_l2t1_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU0.mcu_l2t1_data_vld_r0; | |
1368 | initial mcu1_l2t0_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU1.mcu_l2t0_data_vld_r0; | |
1369 | initial mcu1_l2t1_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU1.mcu_l2t1_data_vld_r0; | |
1370 | initial mcu2_l2t0_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU2.mcu_l2t0_data_vld_r0; | |
1371 | initial mcu2_l2t1_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU2.mcu_l2t1_data_vld_r0; | |
1372 | initial mcu3_l2t0_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU3.mcu_l2t0_data_vld_r0; | |
1373 | initial mcu3_l2t1_data_vld_r0_delay = repeat(`DELAY) @(posedge l2clk) `MCU3.mcu_l2t1_data_vld_r0; | |
1374 | ||
1375 | `define MAX_CYCLE_CNT 12 | |
1376 | reg mask_t0=0; | |
1377 | reg mask_t1=0; | |
1378 | ||
1379 | //###### # ##### | |
1380 | //# # # # # # | |
1381 | //# # # # # | |
1382 | //# # # # # | |
1383 | //# # ####### # | |
1384 | //# # # # # # | |
1385 | //###### # # ##### | |
1386 | ||
1387 | ||
1388 | always @(posedge mcu0_esr_dac) begin | |
1389 | if (enabled && mcu_num==2'b00) begin | |
1390 | ||
1391 | if (mcu0_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1392 | mask_t0=1; | |
1393 | ||
1394 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1395 | if (mask_t0) begin | |
1396 | @(negedge l2clk); | |
1397 | if (`MCU0.mcu_l2t0_secc_err_r3) | |
1398 | begin | |
1399 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t0_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1400 | mask_t0=0; | |
1401 | end | |
1402 | else if (i==`MAX_CYCLE_CNT) | |
1403 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t0_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1404 | end | |
1405 | end //for | |
1406 | ||
1407 | end | |
1408 | ||
1409 | if (mcu0_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1410 | mask_t1=1; | |
1411 | ||
1412 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1413 | if (mask_t1) begin | |
1414 | @(negedge l2clk); | |
1415 | if (`MCU0.mcu_l2t1_secc_err_r3) | |
1416 | begin | |
1417 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t1_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1418 | mask_t1=0; | |
1419 | end | |
1420 | else if (i==`MAX_CYCLE_CNT) | |
1421 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t1_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1422 | end | |
1423 | end //for | |
1424 | ||
1425 | end | |
1426 | ||
1427 | end | |
1428 | end //always | |
1429 | ||
1430 | ||
1431 | always @(posedge mcu1_esr_dac) begin | |
1432 | if (enabled && mcu_num==2'b01) begin | |
1433 | ||
1434 | if (mcu1_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1435 | mask_t0=1; | |
1436 | ||
1437 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1438 | if (mask_t0) begin | |
1439 | @(negedge l2clk); | |
1440 | if (`MCU1.mcu_l2t0_secc_err_r3) | |
1441 | begin | |
1442 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t0_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1443 | mask_t0=0; | |
1444 | end | |
1445 | else if (i==`MAX_CYCLE_CNT) | |
1446 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t0_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1447 | end | |
1448 | end //for | |
1449 | ||
1450 | end | |
1451 | ||
1452 | if (mcu1_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1453 | mask_t1=1; | |
1454 | ||
1455 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1456 | if (mask_t1) begin | |
1457 | @(negedge l2clk); | |
1458 | if (`MCU1.mcu_l2t1_secc_err_r3) | |
1459 | begin | |
1460 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t1_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1461 | mask_t1=0; | |
1462 | end | |
1463 | else if (i==`MAX_CYCLE_CNT) | |
1464 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t1_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1465 | end | |
1466 | end //for | |
1467 | ||
1468 | end | |
1469 | ||
1470 | end | |
1471 | end //always | |
1472 | ||
1473 | always @(posedge mcu2_esr_dac) begin | |
1474 | if (enabled && mcu_num==2'b10) begin | |
1475 | ||
1476 | if (mcu2_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1477 | mask_t0=1; | |
1478 | ||
1479 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1480 | if (mask_t0) begin | |
1481 | @(negedge l2clk); | |
1482 | if (`MCU2.mcu_l2t0_secc_err_r3) | |
1483 | begin | |
1484 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t0_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1485 | mask_t0=0; | |
1486 | end | |
1487 | else if (i==`MAX_CYCLE_CNT) | |
1488 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t0_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1489 | end | |
1490 | end //for | |
1491 | ||
1492 | end | |
1493 | ||
1494 | if (mcu2_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1495 | mask_t1=1; | |
1496 | ||
1497 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1498 | if (mask_t1) begin | |
1499 | @(negedge l2clk); | |
1500 | if (`MCU2.mcu_l2t1_secc_err_r3) | |
1501 | begin | |
1502 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t1_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1503 | mask_t1=0; | |
1504 | end | |
1505 | else if (i==`MAX_CYCLE_CNT) | |
1506 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t1_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1507 | end | |
1508 | end //for | |
1509 | ||
1510 | end | |
1511 | ||
1512 | end | |
1513 | end //always | |
1514 | ||
1515 | always @(posedge mcu3_esr_dac) begin | |
1516 | if (enabled && mcu_num==2'b11) begin | |
1517 | ||
1518 | if (mcu3_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1519 | mask_t0=1; | |
1520 | ||
1521 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1522 | if (mask_t0) begin | |
1523 | @(negedge l2clk); | |
1524 | if (`MCU3.mcu_l2t0_secc_err_r3) | |
1525 | begin | |
1526 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t0_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1527 | mask_t0=0; | |
1528 | end | |
1529 | else if (i==`MAX_CYCLE_CNT) | |
1530 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t0_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1531 | end | |
1532 | end //for | |
1533 | ||
1534 | end | |
1535 | ||
1536 | if (mcu3_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1537 | mask_t1=1; | |
1538 | ||
1539 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1540 | if (mask_t1) begin | |
1541 | @(negedge l2clk); | |
1542 | if (`MCU3.mcu_l2t1_secc_err_r3) | |
1543 | begin | |
1544 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t1_secc_err_r3 is asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1545 | mask_t1=0; | |
1546 | end | |
1547 | else if (i==`MAX_CYCLE_CNT) | |
1548 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t1_secc_err_r3 is NOT asserted when MCU esr DAC is logged (after %d cycles)",i); | |
1549 | end | |
1550 | end //for | |
1551 | ||
1552 | end | |
1553 | ||
1554 | end | |
1555 | end //always | |
1556 | ||
1557 | ||
1558 | //###### # # # | |
1559 | //# # # # # # | |
1560 | //# # # # # # | |
1561 | //# # # # # # | |
1562 | //# # ####### # # | |
1563 | //# # # # # # | |
1564 | //###### # # ##### | |
1565 | ||
1566 | ||
1567 | always @(posedge mcu0_esr_dau) begin | |
1568 | if (enabled && mcu_num==2'b00) begin | |
1569 | ||
1570 | if (mcu0_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1571 | mask_t0=1; | |
1572 | ||
1573 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1574 | if (mask_t0) begin | |
1575 | @(negedge l2clk); | |
1576 | if (`MCU0.mcu_l2t0_mecc_err_r3) | |
1577 | begin | |
1578 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t0_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1579 | mask_t0=0; | |
1580 | end | |
1581 | else if (i==`MAX_CYCLE_CNT) | |
1582 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t0_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1583 | end | |
1584 | end //for | |
1585 | ||
1586 | end | |
1587 | ||
1588 | if (mcu0_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1589 | mask_t1=1; | |
1590 | ||
1591 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1592 | if (mask_t1) begin | |
1593 | @(negedge l2clk); | |
1594 | if (`MCU0.mcu_l2t1_mecc_err_r3) | |
1595 | begin | |
1596 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t1_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1597 | mask_t1=0; | |
1598 | end | |
1599 | else if (i==`MAX_CYCLE_CNT) | |
1600 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t1_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1601 | end | |
1602 | end //for | |
1603 | ||
1604 | end | |
1605 | ||
1606 | end | |
1607 | end //always | |
1608 | ||
1609 | ||
1610 | always @(posedge mcu1_esr_dau) begin | |
1611 | if (enabled && mcu_num==2'b01) begin | |
1612 | ||
1613 | if (mcu1_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1614 | mask_t0=1; | |
1615 | ||
1616 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1617 | if (mask_t0) begin | |
1618 | @(negedge l2clk); | |
1619 | if (`MCU1.mcu_l2t0_mecc_err_r3) | |
1620 | begin | |
1621 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t0_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1622 | mask_t0=0; | |
1623 | end | |
1624 | else if (i==`MAX_CYCLE_CNT) | |
1625 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t0_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1626 | end | |
1627 | end //for | |
1628 | ||
1629 | end | |
1630 | ||
1631 | if (mcu1_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1632 | mask_t1=1; | |
1633 | ||
1634 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1635 | if (mask_t1) begin | |
1636 | @(negedge l2clk); | |
1637 | if (`MCU1.mcu_l2t1_mecc_err_r3) | |
1638 | begin | |
1639 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t1_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1640 | mask_t1=0; | |
1641 | end | |
1642 | else if (i==`MAX_CYCLE_CNT) | |
1643 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t1_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1644 | end | |
1645 | end //for | |
1646 | ||
1647 | end | |
1648 | ||
1649 | end | |
1650 | end //always | |
1651 | ||
1652 | always @(posedge mcu2_esr_dau) begin | |
1653 | if (enabled && mcu_num==2'b10) begin | |
1654 | ||
1655 | if (mcu2_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1656 | mask_t0=1; | |
1657 | ||
1658 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1659 | if (mask_t0) begin | |
1660 | @(negedge l2clk); | |
1661 | if (`MCU2.mcu_l2t0_mecc_err_r3) | |
1662 | begin | |
1663 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t0_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1664 | mask_t0=0; | |
1665 | end | |
1666 | else if (i==`MAX_CYCLE_CNT) | |
1667 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t0_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1668 | end | |
1669 | end //for | |
1670 | ||
1671 | end | |
1672 | ||
1673 | if (mcu2_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1674 | mask_t1=1; | |
1675 | ||
1676 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1677 | if (mask_t1) begin | |
1678 | @(negedge l2clk); | |
1679 | if (`MCU2.mcu_l2t1_mecc_err_r3) | |
1680 | begin | |
1681 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t1_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1682 | mask_t1=0; | |
1683 | end | |
1684 | else if (i==`MAX_CYCLE_CNT) | |
1685 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t1_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1686 | end | |
1687 | end //for | |
1688 | ||
1689 | end | |
1690 | ||
1691 | end | |
1692 | end //always | |
1693 | ||
1694 | always @(posedge mcu3_esr_dau) begin | |
1695 | if (enabled && mcu_num==2'b11) begin | |
1696 | ||
1697 | if (mcu3_l2t0_data_vld_r0_delay && !mask_t0) begin | |
1698 | mask_t0=1; | |
1699 | ||
1700 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1701 | if (mask_t0) begin | |
1702 | @(negedge l2clk); | |
1703 | if (`MCU3.mcu_l2t0_mecc_err_r3) | |
1704 | begin | |
1705 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t0_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1706 | mask_t0=0; | |
1707 | end | |
1708 | else if (i==`MAX_CYCLE_CNT) | |
1709 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t0_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1710 | end | |
1711 | end //for | |
1712 | ||
1713 | end | |
1714 | ||
1715 | if (mcu3_l2t1_data_vld_r0_delay && !mask_t1) begin | |
1716 | mask_t1=1; | |
1717 | ||
1718 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1719 | if (mask_t1) begin | |
1720 | @(negedge l2clk); | |
1721 | if (`MCU3.mcu_l2t1_mecc_err_r3) | |
1722 | begin | |
1723 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t1_mecc_err_r3 is asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1724 | mask_t1=0; | |
1725 | end | |
1726 | else if (i==`MAX_CYCLE_CNT) | |
1727 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t1_mecc_err_r3 is NOT asserted when MCU esr DAU is logged (after %d cycles)",i); | |
1728 | end | |
1729 | end //for | |
1730 | ||
1731 | end | |
1732 | ||
1733 | end | |
1734 | end //always | |
1735 | ||
1736 | ||
1737 | /*----------------------------------------------------------------------------*/ | |
1738 | ||
1739 | //MCU0 | |
1740 | ||
1741 | reg mcu0_rdata_scrb0_err_valid_d1, mcu0_rdata_scrb1_err_valid_d1; | |
1742 | ||
1743 | always @(posedge l2clk) begin | |
1744 | mcu0_rdata_scrb0_err_valid_d1 <= tb_top.cpu.mcu0.rdata.rdata_scrb0_err_valid; | |
1745 | mcu0_rdata_scrb1_err_valid_d1 <= tb_top.cpu.mcu0.rdata.rdata_scrb1_err_valid; | |
1746 | end | |
1747 | ||
1748 | wire mcu0_scrb0_secc_missed = tb_top.cpu.mcu0.rdata.readdp_l2_secc_err_dly1 & | |
1749 | mcu0_rdata_scrb0_err_valid_d1 & | |
1750 | tb_top.cpu.mcu0.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1751 | ~tb_top.cpu.mcu0.rdata.rdata_scrb0_err_valid; | |
1752 | ||
1753 | wire mcu0_scrb0_mecc_missed = tb_top.cpu.mcu0.rdata.readdp_l2_mecc_err_dly1 & | |
1754 | mcu0_rdata_scrb0_err_valid_d1 & | |
1755 | tb_top.cpu.mcu0.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1756 | ~tb_top.cpu.mcu0.rdata.rdata_scrb0_err_valid; | |
1757 | ||
1758 | wire mcu0_scrb1_secc_missed = tb_top.cpu.mcu0.rdata.readdp_l2_secc_err_dly1 & | |
1759 | mcu0_rdata_scrb1_err_valid_d1 & | |
1760 | tb_top.cpu.mcu0.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1761 | ~tb_top.cpu.mcu0.rdata.rdata_scrb1_err_valid; | |
1762 | ||
1763 | wire mcu0_scrb1_mecc_missed = tb_top.cpu.mcu0.rdata.readdp_l2_mecc_err_dly1 & | |
1764 | mcu0_rdata_scrb1_err_valid_d1 & | |
1765 | tb_top.cpu.mcu0.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1766 | ~tb_top.cpu.mcu0.rdata.rdata_scrb1_err_valid; | |
1767 | /*----------------------------------------------------------------------------*/ | |
1768 | ||
1769 | //MCU1 | |
1770 | ||
1771 | reg mcu1_rdata_scrb0_err_valid_d1, mcu1_rdata_scrb1_err_valid_d1; | |
1772 | ||
1773 | always @(posedge l2clk) begin | |
1774 | mcu1_rdata_scrb0_err_valid_d1 <= tb_top.cpu.mcu1.rdata.rdata_scrb0_err_valid; | |
1775 | mcu1_rdata_scrb1_err_valid_d1 <= tb_top.cpu.mcu1.rdata.rdata_scrb1_err_valid; | |
1776 | end | |
1777 | ||
1778 | wire mcu1_scrb0_secc_missed = tb_top.cpu.mcu1.rdata.readdp_l2_secc_err_dly1 & | |
1779 | mcu1_rdata_scrb0_err_valid_d1 & | |
1780 | tb_top.cpu.mcu1.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1781 | ~tb_top.cpu.mcu1.rdata.rdata_scrb0_err_valid; | |
1782 | ||
1783 | wire mcu1_scrb0_mecc_missed = tb_top.cpu.mcu1.rdata.readdp_l2_mecc_err_dly1 & | |
1784 | mcu1_rdata_scrb0_err_valid_d1 & | |
1785 | tb_top.cpu.mcu1.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1786 | ~tb_top.cpu.mcu1.rdata.rdata_scrb0_err_valid; | |
1787 | ||
1788 | wire mcu1_scrb1_secc_missed = tb_top.cpu.mcu1.rdata.readdp_l2_secc_err_dly1 & | |
1789 | mcu1_rdata_scrb1_err_valid_d1 & | |
1790 | tb_top.cpu.mcu1.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1791 | ~tb_top.cpu.mcu1.rdata.rdata_scrb1_err_valid; | |
1792 | ||
1793 | wire mcu1_scrb1_mecc_missed = tb_top.cpu.mcu1.rdata.readdp_l2_mecc_err_dly1 & | |
1794 | mcu1_rdata_scrb1_err_valid_d1 & | |
1795 | tb_top.cpu.mcu1.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1796 | ~tb_top.cpu.mcu1.rdata.rdata_scrb1_err_valid; | |
1797 | /*----------------------------------------------------------------------------*/ | |
1798 | ||
1799 | //MCU2 | |
1800 | ||
1801 | reg mcu2_rdata_scrb0_err_valid_d1, mcu2_rdata_scrb1_err_valid_d1; | |
1802 | ||
1803 | always @(posedge l2clk) begin | |
1804 | mcu2_rdata_scrb0_err_valid_d1 <= tb_top.cpu.mcu2.rdata.rdata_scrb0_err_valid; | |
1805 | mcu2_rdata_scrb1_err_valid_d1 <= tb_top.cpu.mcu2.rdata.rdata_scrb1_err_valid; | |
1806 | end | |
1807 | ||
1808 | wire mcu2_scrb0_secc_missed = tb_top.cpu.mcu2.rdata.readdp_l2_secc_err_dly1 & | |
1809 | mcu2_rdata_scrb0_err_valid_d1 & | |
1810 | tb_top.cpu.mcu2.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1811 | ~tb_top.cpu.mcu2.rdata.rdata_scrb0_err_valid; | |
1812 | ||
1813 | wire mcu2_scrb0_mecc_missed = tb_top.cpu.mcu2.rdata.readdp_l2_mecc_err_dly1 & | |
1814 | mcu2_rdata_scrb0_err_valid_d1 & | |
1815 | tb_top.cpu.mcu2.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1816 | ~tb_top.cpu.mcu2.rdata.rdata_scrb0_err_valid; | |
1817 | ||
1818 | wire mcu2_scrb1_secc_missed = tb_top.cpu.mcu2.rdata.readdp_l2_secc_err_dly1 & | |
1819 | mcu2_rdata_scrb1_err_valid_d1 & | |
1820 | tb_top.cpu.mcu2.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1821 | ~tb_top.cpu.mcu2.rdata.rdata_scrb1_err_valid; | |
1822 | ||
1823 | wire mcu2_scrb1_mecc_missed = tb_top.cpu.mcu2.rdata.readdp_l2_mecc_err_dly1 & | |
1824 | mcu2_rdata_scrb1_err_valid_d1 & | |
1825 | tb_top.cpu.mcu2.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1826 | ~tb_top.cpu.mcu2.rdata.rdata_scrb1_err_valid; | |
1827 | /*----------------------------------------------------------------------------*/ | |
1828 | ||
1829 | //MCU3 | |
1830 | ||
1831 | reg mcu3_rdata_scrb0_err_valid_d1, mcu3_rdata_scrb1_err_valid_d1; | |
1832 | ||
1833 | always @(posedge l2clk) begin | |
1834 | mcu3_rdata_scrb0_err_valid_d1 <= tb_top.cpu.mcu3.rdata.rdata_scrb0_err_valid; | |
1835 | mcu3_rdata_scrb1_err_valid_d1 <= tb_top.cpu.mcu3.rdata.rdata_scrb1_err_valid; | |
1836 | end | |
1837 | ||
1838 | wire mcu3_scrb0_secc_missed = tb_top.cpu.mcu3.rdata.readdp_l2_secc_err_dly1 & | |
1839 | mcu3_rdata_scrb0_err_valid_d1 & | |
1840 | tb_top.cpu.mcu3.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1841 | ~tb_top.cpu.mcu3.rdata.rdata_scrb0_err_valid; | |
1842 | ||
1843 | wire mcu3_scrb0_mecc_missed = tb_top.cpu.mcu3.rdata.readdp_l2_mecc_err_dly1 & | |
1844 | mcu3_rdata_scrb0_err_valid_d1 & | |
1845 | tb_top.cpu.mcu3.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1846 | ~tb_top.cpu.mcu3.rdata.rdata_scrb0_err_valid; | |
1847 | ||
1848 | wire mcu3_scrb1_secc_missed = tb_top.cpu.mcu3.rdata.readdp_l2_secc_err_dly1 & | |
1849 | mcu3_rdata_scrb1_err_valid_d1 & | |
1850 | tb_top.cpu.mcu3.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1851 | ~tb_top.cpu.mcu3.rdata.rdata_scrb1_err_valid; | |
1852 | ||
1853 | wire mcu3_scrb1_mecc_missed = tb_top.cpu.mcu3.rdata.readdp_l2_mecc_err_dly1 & | |
1854 | mcu3_rdata_scrb1_err_valid_d1 & | |
1855 | tb_top.cpu.mcu3.rdata.rdata_ddr_cmp_sync_en_d12 & | |
1856 | ~tb_top.cpu.mcu3.rdata.rdata_scrb1_err_valid; | |
1857 | /*----------------------------------------------------------------------------*/ | |
1858 | ||
1859 | ||
1860 | ||
1861 | //###### ##### ##### | |
1862 | //# # # # # # | |
1863 | //# # # # | |
1864 | //# # ##### # | |
1865 | //# # # # | |
1866 | //# # # # # # | |
1867 | //###### ##### ##### | |
1868 | ||
1869 | ||
1870 | always @(posedge mcu0_esr_dsc) begin | |
1871 | if (enabled && mcu_num==2'b00) begin | |
1872 | ||
1873 | if (!mask_t0 && `MCU0.drif.drif_scrub_bank_adr[0]==0) begin | |
1874 | mask_t0=1; | |
1875 | ||
1876 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1877 | if (mask_t0) begin | |
1878 | @(negedge l2clk); | |
1879 | if (`MCU0.mcu_l2t0_scb_secc_err) | |
1880 | begin | |
1881 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t0_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1882 | mask_t0=0; | |
1883 | end | |
1884 | else if (mcu0_scrb0_secc_missed==1) | |
1885 | begin | |
1886 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
1887 | mask_t0=0; | |
1888 | end | |
1889 | else if (i==`MAX_CYCLE_CNT) | |
1890 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1891 | end | |
1892 | end //for | |
1893 | ||
1894 | end | |
1895 | ||
1896 | if (!mask_t1 && `MCU0.drif.drif_scrub_bank_adr[0]==1) begin | |
1897 | mask_t1=1; | |
1898 | ||
1899 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1900 | if (mask_t1) begin | |
1901 | @(negedge l2clk); | |
1902 | if (`MCU0.mcu_l2t1_scb_secc_err) | |
1903 | begin | |
1904 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t1_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1905 | mask_t1=0; | |
1906 | end | |
1907 | else if (mcu0_scrb1_secc_missed==1) | |
1908 | begin | |
1909 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
1910 | mask_t1=0; | |
1911 | end | |
1912 | else if (i==`MAX_CYCLE_CNT) | |
1913 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1914 | end | |
1915 | end //for | |
1916 | ||
1917 | end | |
1918 | ||
1919 | end | |
1920 | end //always | |
1921 | ||
1922 | ||
1923 | always @(posedge mcu1_esr_dsc) begin | |
1924 | if (enabled && mcu_num==2'b01) begin | |
1925 | ||
1926 | if (!mask_t0 && `MCU1.drif.drif_scrub_bank_adr[0]==0) begin | |
1927 | mask_t0=1; | |
1928 | ||
1929 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1930 | if (mask_t0) begin | |
1931 | @(negedge l2clk); | |
1932 | if (`MCU1.mcu_l2t0_scb_secc_err) | |
1933 | begin | |
1934 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t0_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1935 | mask_t0=0; | |
1936 | end | |
1937 | else if (mcu1_scrb0_secc_missed==1) | |
1938 | begin | |
1939 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
1940 | mask_t0=0; | |
1941 | end | |
1942 | else if (i==`MAX_CYCLE_CNT) | |
1943 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1944 | end | |
1945 | end //for | |
1946 | ||
1947 | end | |
1948 | ||
1949 | if (!mask_t1 && `MCU1.drif.drif_scrub_bank_adr[0]==1) begin | |
1950 | mask_t1=1; | |
1951 | ||
1952 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1953 | if (mask_t1) begin | |
1954 | @(negedge l2clk); | |
1955 | if (`MCU1.mcu_l2t1_scb_secc_err) | |
1956 | begin | |
1957 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t1_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1958 | mask_t1=0; | |
1959 | end | |
1960 | else if (mcu1_scrb1_secc_missed==1) | |
1961 | begin | |
1962 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
1963 | mask_t1=0; | |
1964 | end | |
1965 | else if (i==`MAX_CYCLE_CNT) | |
1966 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1967 | end | |
1968 | end //for | |
1969 | ||
1970 | end | |
1971 | ||
1972 | end | |
1973 | end //always | |
1974 | ||
1975 | always @(posedge mcu2_esr_dsc) begin | |
1976 | if (enabled && mcu_num==2'b10) begin | |
1977 | ||
1978 | if (!mask_t0 && `MCU2.drif.drif_scrub_bank_adr[0]==0) begin | |
1979 | mask_t0=1; | |
1980 | ||
1981 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
1982 | if (mask_t0) begin | |
1983 | @(negedge l2clk); | |
1984 | if (`MCU2.mcu_l2t0_scb_secc_err) | |
1985 | begin | |
1986 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t0_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1987 | mask_t0=0; | |
1988 | end | |
1989 | else if (mcu2_scrb0_secc_missed==1) | |
1990 | begin | |
1991 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
1992 | mask_t0=0; | |
1993 | end | |
1994 | else if (i==`MAX_CYCLE_CNT) | |
1995 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
1996 | end | |
1997 | end //for | |
1998 | ||
1999 | end | |
2000 | ||
2001 | if (!mask_t1 && `MCU2.drif.drif_scrub_bank_adr[0]==1) begin | |
2002 | mask_t1=1; | |
2003 | ||
2004 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2005 | if (mask_t1) begin | |
2006 | @(negedge l2clk); | |
2007 | if (`MCU2.mcu_l2t1_scb_secc_err) | |
2008 | begin | |
2009 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t1_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
2010 | mask_t1=0; | |
2011 | end | |
2012 | else if (mcu2_scrb1_secc_missed==1) | |
2013 | begin | |
2014 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2015 | mask_t1=0; | |
2016 | end | |
2017 | else if (i==`MAX_CYCLE_CNT) | |
2018 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
2019 | end | |
2020 | end //for | |
2021 | ||
2022 | end | |
2023 | ||
2024 | end | |
2025 | end //always | |
2026 | ||
2027 | always @(posedge mcu3_esr_dsc) begin | |
2028 | if (enabled && mcu_num==2'b11) begin | |
2029 | ||
2030 | if (!mask_t0 && `MCU3.drif.drif_scrub_bank_adr[0]==0) begin | |
2031 | mask_t0=1; | |
2032 | ||
2033 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2034 | if (mask_t0) begin | |
2035 | @(negedge l2clk); | |
2036 | if (`MCU3.mcu_l2t0_scb_secc_err) | |
2037 | begin | |
2038 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t0_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
2039 | mask_t0=0; | |
2040 | end | |
2041 | else if (mcu3_scrb0_secc_missed==1) | |
2042 | begin | |
2043 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2044 | mask_t0=0; | |
2045 | end | |
2046 | else if (i==`MAX_CYCLE_CNT) | |
2047 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t0_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
2048 | end | |
2049 | end //for | |
2050 | ||
2051 | end | |
2052 | ||
2053 | if (!mask_t1 && `MCU3.drif.drif_scrub_bank_adr[0]==1) begin | |
2054 | mask_t1=1; | |
2055 | ||
2056 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2057 | if (mask_t1) begin | |
2058 | @(negedge l2clk); | |
2059 | if (`MCU3.mcu_l2t1_scb_secc_err) | |
2060 | begin | |
2061 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t1_scb_secc_err is asserted when MCU esr DSC is logged (after %d cycles)",i); | |
2062 | mask_t1=0; | |
2063 | end | |
2064 | else if (mcu3_scrb1_secc_missed==1) | |
2065 | begin | |
2066 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2067 | mask_t1=0; | |
2068 | end | |
2069 | else if (i==`MAX_CYCLE_CNT) | |
2070 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t1_scb_secc_err is NOT asserted when MCU esr DSC is logged (after %d cycles)",i); | |
2071 | end | |
2072 | end //for | |
2073 | ||
2074 | end | |
2075 | ||
2076 | end | |
2077 | end //always | |
2078 | ||
2079 | ||
2080 | ||
2081 | //###### ##### # # | |
2082 | //# # # # # # | |
2083 | //# # # # # | |
2084 | //# # ##### # # | |
2085 | //# # # # # | |
2086 | //# # # # # # | |
2087 | //###### ##### ##### | |
2088 | ||
2089 | ||
2090 | always @(posedge mcu0_esr_dsu) begin | |
2091 | if (enabled && mcu_num==2'b00) begin | |
2092 | ||
2093 | if (!mask_t0 && `MCU0.drif.drif_scrub_bank_adr[0]==0) begin | |
2094 | mask_t0=1; | |
2095 | ||
2096 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2097 | if (mask_t0) begin | |
2098 | @(negedge l2clk); | |
2099 | if (`MCU0.mcu_l2t0_scb_mecc_err) | |
2100 | begin | |
2101 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t0_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2102 | mask_t0=0; | |
2103 | end | |
2104 | else if (mcu0_scrb0_mecc_missed==1) | |
2105 | begin | |
2106 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2107 | mask_t0=0; | |
2108 | end | |
2109 | else if (i==`MAX_CYCLE_CNT) | |
2110 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2111 | end | |
2112 | end //for | |
2113 | ||
2114 | end | |
2115 | ||
2116 | if (!mask_t1 && `MCU0.drif.drif_scrub_bank_adr[0]==1) begin | |
2117 | mask_t1=1; | |
2118 | ||
2119 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2120 | if (mask_t1) begin | |
2121 | @(negedge l2clk); | |
2122 | if (`MCU0.mcu_l2t1_scb_mecc_err) | |
2123 | begin | |
2124 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t1_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2125 | mask_t1=0; | |
2126 | end | |
2127 | else if (mcu0_scrb1_mecc_missed==1) | |
2128 | begin | |
2129 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2130 | mask_t1=0; | |
2131 | end | |
2132 | else if (i==`MAX_CYCLE_CNT) | |
2133 | `PR_ERROR("mcu_errmon", `ERROR, "MCU0: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2134 | end | |
2135 | end //for | |
2136 | ||
2137 | end | |
2138 | ||
2139 | end | |
2140 | end //always | |
2141 | ||
2142 | ||
2143 | always @(posedge mcu1_esr_dsu) begin | |
2144 | if (enabled && mcu_num==2'b01) begin | |
2145 | ||
2146 | if (!mask_t0 && `MCU1.drif.drif_scrub_bank_adr[0]==0) begin | |
2147 | mask_t0=1; | |
2148 | ||
2149 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2150 | if (mask_t0) begin | |
2151 | @(negedge l2clk); | |
2152 | if (`MCU1.mcu_l2t0_scb_mecc_err) | |
2153 | begin | |
2154 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t0_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2155 | mask_t0=0; | |
2156 | end | |
2157 | else if (mcu1_scrb0_mecc_missed==1) | |
2158 | begin | |
2159 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2160 | mask_t0=0; | |
2161 | end | |
2162 | else if (i==`MAX_CYCLE_CNT) | |
2163 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2164 | end | |
2165 | end //for | |
2166 | ||
2167 | end | |
2168 | ||
2169 | if (!mask_t1 && `MCU1.drif.drif_scrub_bank_adr[0]==1) begin | |
2170 | mask_t1=1; | |
2171 | ||
2172 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2173 | if (mask_t1) begin | |
2174 | @(negedge l2clk); | |
2175 | if (`MCU1.mcu_l2t1_scb_mecc_err) | |
2176 | begin | |
2177 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t1_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2178 | mask_t1=0; | |
2179 | end | |
2180 | else if (mcu1_scrb1_mecc_missed==1) | |
2181 | begin | |
2182 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU1: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2183 | mask_t1=0; | |
2184 | end | |
2185 | else if (i==`MAX_CYCLE_CNT) | |
2186 | `PR_ERROR("mcu_errmon", `ERROR, "MCU1: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2187 | end | |
2188 | end //for | |
2189 | ||
2190 | end | |
2191 | ||
2192 | end | |
2193 | end //always | |
2194 | ||
2195 | always @(posedge mcu2_esr_dsu) begin | |
2196 | if (enabled && mcu_num==2'b10) begin | |
2197 | ||
2198 | if (!mask_t0 && `MCU2.drif.drif_scrub_bank_adr[0]==0) begin | |
2199 | mask_t0=1; | |
2200 | ||
2201 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2202 | if (mask_t0) begin | |
2203 | @(negedge l2clk); | |
2204 | if (`MCU2.mcu_l2t0_scb_mecc_err) | |
2205 | begin | |
2206 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t0_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2207 | mask_t0=0; | |
2208 | end | |
2209 | else if (mcu2_scrb0_mecc_missed==1) | |
2210 | begin | |
2211 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2212 | mask_t0=0; | |
2213 | end | |
2214 | else if (i==`MAX_CYCLE_CNT) | |
2215 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2216 | end | |
2217 | end //for | |
2218 | ||
2219 | end | |
2220 | ||
2221 | if (!mask_t1 && `MCU2.drif.drif_scrub_bank_adr[0]==1) begin | |
2222 | mask_t1=1; | |
2223 | ||
2224 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2225 | if (mask_t1) begin | |
2226 | @(negedge l2clk); | |
2227 | if (`MCU2.mcu_l2t1_scb_mecc_err) | |
2228 | begin | |
2229 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t1_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2230 | mask_t1=0; | |
2231 | end | |
2232 | else if (mcu2_scrb1_mecc_missed==1) | |
2233 | begin | |
2234 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU2: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2235 | mask_t1=0; | |
2236 | end | |
2237 | else if (i==`MAX_CYCLE_CNT) | |
2238 | `PR_ERROR("mcu_errmon", `ERROR, "MCU2: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2239 | end | |
2240 | end //for | |
2241 | ||
2242 | end | |
2243 | ||
2244 | end | |
2245 | end //always | |
2246 | ||
2247 | always @(posedge mcu3_esr_dsu) begin | |
2248 | if (enabled && mcu_num==2'b11) begin | |
2249 | ||
2250 | if (!mask_t0 && `MCU3.drif.drif_scrub_bank_adr[0]==0) begin | |
2251 | mask_t0=1; | |
2252 | ||
2253 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2254 | if (mask_t0) begin | |
2255 | @(negedge l2clk); | |
2256 | if (`MCU3.mcu_l2t0_scb_mecc_err) | |
2257 | begin | |
2258 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t0_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2259 | mask_t0=0; | |
2260 | end | |
2261 | else if (mcu3_scrb0_mecc_missed==1) | |
2262 | begin | |
2263 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2264 | mask_t0=0; | |
2265 | end | |
2266 | else if (i==`MAX_CYCLE_CNT) | |
2267 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t0_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2268 | end | |
2269 | end //for | |
2270 | ||
2271 | end | |
2272 | ||
2273 | if (!mask_t1 && `MCU3.drif.drif_scrub_bank_adr[0]==1) begin | |
2274 | mask_t1=1; | |
2275 | ||
2276 | for (i=1; i<=`MAX_CYCLE_CNT; i=i+1) begin | |
2277 | if (mask_t1) begin | |
2278 | @(negedge l2clk); | |
2279 | if (`MCU3.mcu_l2t1_scb_mecc_err) | |
2280 | begin | |
2281 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t1_scb_mecc_err is asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2282 | mask_t1=0; | |
2283 | end | |
2284 | else if (mcu3_scrb1_mecc_missed==1) | |
2285 | begin | |
2286 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU3: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles) *** N2 TO 2.0 BUG 120330 *** ",i); | |
2287 | mask_t1=0; | |
2288 | end | |
2289 | else if (i==`MAX_CYCLE_CNT) | |
2290 | `PR_ERROR("mcu_errmon", `ERROR, "MCU3: mcu_l2t1_scb_mecc_err is NOT asserted when MCU esr DSU is logged (after %d cycles)",i); | |
2291 | end | |
2292 | end //for | |
2293 | ||
2294 | end | |
2295 | ||
2296 | end | |
2297 | end //always | |
2298 | ||
2299 | ||
2300 | `ifndef MCUSAT | |
2301 | ||
2302 | // added this code for " -vcs_run_args=+MCU_BUG_111726 " | |
2303 | ||
2304 | `define CYCLE_CNT_111726 10 | |
2305 | ||
2306 | reg mask_t0_111726=0; | |
2307 | reg mask_t1_111726=0; | |
2308 | ||
2309 | // mcu0 | |
2310 | always @( tb_top.cpu.mcu0.rdpctl_err_sts_reg[25:16] ) begin | |
2311 | ||
2312 | if ( $test$plusargs("MCU_BUG_111726") && mcu_num==2'b00 ) begin | |
2313 | ||
2314 | if (!mask_t0_111726) | |
2315 | mask_t0_111726=1; | |
2316 | for (i=1; i<=`CYCLE_CNT_111726; i=i+1) begin | |
2317 | if (mask_t0_111726) | |
2318 | begin | |
2319 | @(negedge l2clk); | |
2320 | if ( tb_top.cpu.mcu0.mcu_l2t0_secc_err_r3==1 && tb_top.cpu.mcu0.mcu_l2t0_mecc_err_r3==1 ) begin | |
2321 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: *BOTH* mcu_l2t0_secc_err_r3 and mcu_l2t0_mecc_err_r3 are asserted at the same time !! (after %d cycles) *** N2 T.O.2.0 BUG 111726 *** ",i); | |
2322 | mask_t0_111726=0; | |
2323 | end | |
2324 | end | |
2325 | end | |
2326 | ||
2327 | if (!mask_t1_111726) | |
2328 | mask_t1_111726=1; | |
2329 | for (i=1; i<=`CYCLE_CNT_111726; i=i+1) begin | |
2330 | if (mask_t1_111726) | |
2331 | begin | |
2332 | @(negedge l2clk); | |
2333 | if ( tb_top.cpu.mcu0.mcu_l2t1_secc_err_r3==1 && tb_top.cpu.mcu0.mcu_l2t1_mecc_err_r3==1 ) begin | |
2334 | `PR_DEBUG("mcu_errmon", `DEBUG, "MCU0: *BOTH* mcu_l2t1_secc_err_r3 and mcu_l2t1_mecc_err_r3 are asserted at the same time !! (after %d cycles) *** N2 T.O.2.0 BUG 111726 *** ",i); | |
2335 | mask_t1_111726=0; | |
2336 | end | |
2337 | end | |
2338 | end | |
2339 | ||
2340 | ||
2341 | end | |
2342 | end | |
2343 | ||
2344 | `endif | |
2345 | ||
2346 | ||
2347 | endmodule |