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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / mcu_fmon.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcu_fmon.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`timescale 1ps/1ps
36`define SMPL 100
37
38
39`ifdef MCUSAT
40 `include "mcu_dispmonDefines.vh"
41`else
42 `include "defines.vh"
43 `include "dispmonDefines.vh"
44`endif
45module mcu_fmon();
46
47`define RD 3'h2
48`define WR 3'h3
49`define ACT 3'h4
50`define WRDATA 3'h5
51
52`define CMD_OTHER 3'h1
53`define CMD_OTHER_PDE 3'h2
54`define CMD_OTHER_SRPDX 3'h3
55`define CMD_OTHER_SRE 3'h4
56`define CMD_OTHER_REF 3'h5
57
58// FBDIMM header defines
59`define FBD_TS0_HDR 12'hbfe
60`define FBD_TS1_HDR 12'hffe
61`define FBD_TS2_HDR 12'h7fe
62`define FBD_TS3_HDR 12'h3fe
63
64reg enabled;
65reg mcu_bug_111483;
66reg mcu_bug_111547;
67reg mcu_bug_111811;
68reg ras_corner_case;
69reg first_time=1'b1;
70reg mcu0_fastreset;
71wire woq0_wrq_clr0;
72assign woq0_wrq_clr0 = `MCU0.drif.reqq.woq.woq0_wr_queue_clear[0];
73
74//---------------------------
75// Training Seq Err Inj Init Signals
76//---------------------------
77
78reg mcu0_training_err_enable,mcu1_training_err_enable,mcu2_training_err_enable,mcu3_training_err_enable;
79
80//----------------------------
81// L0s State Checker Signals
82//----------------------------
83
84wire l1clk = `MCU0.fbdic.l1clk;
85
86wire fbdic_l0s_enable_0 = `MCU0.fbdic.fbdic_l0s_enable;
87wire fbdic_l0s_enable_1 = `MCU1.fbdic.fbdic_l0s_enable;
88wire fbdic_l0s_enable_2 = `MCU2.fbdic.fbdic_l0s_enable;
89wire fbdic_l0s_enable_3 = `MCU3.fbdic.fbdic_l0s_enable;
90
91wire fbdic_l0s_stall_0 = `MCU0.fbdic.fbdic_l0s_stall_in;
92wire fbdic_l0s_stall_1 = `MCU1.fbdic.fbdic_l0s_stall_in;
93wire fbdic_l0s_stall_2 = `MCU2.fbdic.fbdic_l0s_stall_in;
94wire fbdic_l0s_stall_3 = `MCU3.fbdic.fbdic_l0s_stall_in;
95
96wire fbdic_sync_frame_req_0 = `MCU0.fbdic_sync_frame_req;
97wire fbdic_sync_frame_req_1 = `MCU1.fbdic_sync_frame_req;
98wire fbdic_sync_frame_req_2 = `MCU2.fbdic_sync_frame_req;
99wire fbdic_sync_frame_req_3 = `MCU3.fbdic_sync_frame_req;
100
101//----------------------------------
102// Power Down Mode Checker Signals
103//----------------------------------
104
105wire fbdic_mcu_idle_0 = `MCU0.fbdic.fbdic_mcu_idle;
106wire fbdic_mcu_idle_1 = `MCU1.fbdic.fbdic_mcu_idle;
107wire fbdic_mcu_idle_2 = `MCU2.fbdic.fbdic_mcu_idle;
108wire fbdic_mcu_idle_3 = `MCU3.fbdic.fbdic_mcu_idle;
109
110wire drif_pd_mode_enter_pending_0 = `MCU0.drif.drif_pd_mode_enter_pending;
111wire drif_pd_mode_enter_pending_1 = `MCU1.drif.drif_pd_mode_enter_pending;
112wire drif_pd_mode_enter_pending_2 = `MCU2.drif.drif_pd_mode_enter_pending;
113wire drif_pd_mode_enter_pending_3 = `MCU3.drif.drif_pd_mode_enter_pending;
114
115wire drif_pd_mode_exit_pending_0 = `MCU0.drif.drif_pd_mode_exit_pending;
116wire drif_pd_mode_exit_pending_1 = `MCU1.drif.drif_pd_mode_exit_pending;
117wire drif_pd_mode_exit_pending_2 = `MCU2.drif.drif_pd_mode_exit_pending;
118wire drif_pd_mode_exit_pending_3 = `MCU3.drif.drif_pd_mode_exit_pending;
119
120wire drif_pd_mode_enable_0 = `MCU0.drif.drif_pd_mode_enable;
121wire drif_pd_mode_enable_1 = `MCU1.drif.drif_pd_mode_enable;
122wire drif_pd_mode_enable_2 = `MCU2.drif.drif_pd_mode_enable;
123wire drif_pd_mode_enable_3 = `MCU3.drif.drif_pd_mode_enable;
124
125
126wire pdmc_pd_cnt_is_zero_00 = `MCU0.drif.pdmc0.pdmc_pd_cnt_is_zero;
127wire pdmc_pd_cnt_is_zero_01 = `MCU0.drif.pdmc1.pdmc_pd_cnt_is_zero;
128wire pdmc_pd_cnt_is_zero_02 = `MCU0.drif.pdmc2.pdmc_pd_cnt_is_zero;
129wire pdmc_pd_cnt_is_zero_03 = `MCU0.drif.pdmc3.pdmc_pd_cnt_is_zero;
130wire pdmc_pd_cnt_is_zero_04 = `MCU0.drif.pdmc4.pdmc_pd_cnt_is_zero;
131wire pdmc_pd_cnt_is_zero_05 = `MCU0.drif.pdmc5.pdmc_pd_cnt_is_zero;
132wire pdmc_pd_cnt_is_zero_06 = `MCU0.drif.pdmc6.pdmc_pd_cnt_is_zero;
133wire pdmc_pd_cnt_is_zero_07 = `MCU0.drif.pdmc7.pdmc_pd_cnt_is_zero;
134wire pdmc_pd_cnt_is_zero_08 = `MCU0.drif.pdmc8.pdmc_pd_cnt_is_zero;
135wire pdmc_pd_cnt_is_zero_09 = `MCU0.drif.pdmc9.pdmc_pd_cnt_is_zero;
136wire pdmc_pd_cnt_is_zero_0a = `MCU0.drif.pdmc10.pdmc_pd_cnt_is_zero;
137wire pdmc_pd_cnt_is_zero_0b = `MCU0.drif.pdmc11.pdmc_pd_cnt_is_zero;
138wire pdmc_pd_cnt_is_zero_0c = `MCU0.drif.pdmc12.pdmc_pd_cnt_is_zero;
139wire pdmc_pd_cnt_is_zero_0d = `MCU0.drif.pdmc13.pdmc_pd_cnt_is_zero;
140wire pdmc_pd_cnt_is_zero_0e = `MCU0.drif.pdmc14.pdmc_pd_cnt_is_zero;
141wire pdmc_pd_cnt_is_zero_0f = `MCU0.drif.pdmc15.pdmc_pd_cnt_is_zero;
142
143wire [3:0] pdmc_state_00 = `MCU0.drif.pdmc0.pdmc_state;
144wire [3:0] pdmc_state_01 = `MCU0.drif.pdmc1.pdmc_state;
145wire [3:0] pdmc_state_02 = `MCU0.drif.pdmc2.pdmc_state;
146wire [3:0] pdmc_state_03 = `MCU0.drif.pdmc3.pdmc_state;
147wire [3:0] pdmc_state_04 = `MCU0.drif.pdmc4.pdmc_state;
148wire [3:0] pdmc_state_05 = `MCU0.drif.pdmc5.pdmc_state;
149wire [3:0] pdmc_state_06 = `MCU0.drif.pdmc6.pdmc_state;
150wire [3:0] pdmc_state_07 = `MCU0.drif.pdmc7.pdmc_state;
151wire [3:0] pdmc_state_08 = `MCU0.drif.pdmc8.pdmc_state;
152wire [3:0] pdmc_state_09 = `MCU0.drif.pdmc9.pdmc_state;
153wire [3:0] pdmc_state_0a = `MCU0.drif.pdmc10.pdmc_state;
154wire [3:0] pdmc_state_0b = `MCU0.drif.pdmc11.pdmc_state;
155wire [3:0] pdmc_state_0c = `MCU0.drif.pdmc12.pdmc_state;
156wire [3:0] pdmc_state_0d = `MCU0.drif.pdmc13.pdmc_state;
157wire [3:0] pdmc_state_0e = `MCU0.drif.pdmc14.pdmc_state;
158wire [3:0] pdmc_state_0f = `MCU0.drif.pdmc15.pdmc_state;
159
160wire [15:0] mcu0_drif_pde_issued = `MCU0.drif.drif_pde_issued[15:0];
161wire [15:0] mcu0_drif_pdx_issued = `MCU0.drif.drif_pdx_issued[15:0];
162reg mcu0_start_pd_check_0 = 0;
163reg mcu0_start_pd_check_1 = 0;
164reg mcu0_start_pd_check_2 = 0;
165reg mcu0_start_pd_check_3 = 0;
166reg mcu0_start_pd_check_4 = 0;
167reg mcu0_start_pd_check_5 = 0;
168reg mcu0_start_pd_check_6 = 0;
169reg mcu0_start_pd_check_7 = 0;
170reg mcu0_start_pd_check_8 = 0;
171reg mcu0_start_pd_check_9 = 0;
172reg mcu0_start_pd_check_a = 0;
173reg mcu0_start_pd_check_b = 0;
174reg mcu0_start_pd_check_c = 0;
175reg mcu0_start_pd_check_d = 0;
176reg mcu0_start_pd_check_e = 0;
177reg mcu0_start_pd_check_f = 0;
178
179wire pdmc_pd_cnt_is_zero_10 = `MCU1.drif.pdmc0.pdmc_pd_cnt_is_zero;
180wire pdmc_pd_cnt_is_zero_11 = `MCU1.drif.pdmc1.pdmc_pd_cnt_is_zero;
181wire pdmc_pd_cnt_is_zero_12 = `MCU1.drif.pdmc2.pdmc_pd_cnt_is_zero;
182wire pdmc_pd_cnt_is_zero_13 = `MCU1.drif.pdmc3.pdmc_pd_cnt_is_zero;
183wire pdmc_pd_cnt_is_zero_14 = `MCU1.drif.pdmc4.pdmc_pd_cnt_is_zero;
184wire pdmc_pd_cnt_is_zero_15 = `MCU1.drif.pdmc5.pdmc_pd_cnt_is_zero;
185wire pdmc_pd_cnt_is_zero_16 = `MCU1.drif.pdmc6.pdmc_pd_cnt_is_zero;
186wire pdmc_pd_cnt_is_zero_17 = `MCU1.drif.pdmc7.pdmc_pd_cnt_is_zero;
187wire pdmc_pd_cnt_is_zero_18 = `MCU1.drif.pdmc8.pdmc_pd_cnt_is_zero;
188wire pdmc_pd_cnt_is_zero_19 = `MCU1.drif.pdmc9.pdmc_pd_cnt_is_zero;
189wire pdmc_pd_cnt_is_zero_1a = `MCU1.drif.pdmc10.pdmc_pd_cnt_is_zero;
190wire pdmc_pd_cnt_is_zero_1b = `MCU1.drif.pdmc11.pdmc_pd_cnt_is_zero;
191wire pdmc_pd_cnt_is_zero_1c = `MCU1.drif.pdmc12.pdmc_pd_cnt_is_zero;
192wire pdmc_pd_cnt_is_zero_1d = `MCU1.drif.pdmc13.pdmc_pd_cnt_is_zero;
193wire pdmc_pd_cnt_is_zero_1e = `MCU1.drif.pdmc14.pdmc_pd_cnt_is_zero;
194wire pdmc_pd_cnt_is_zero_1f = `MCU1.drif.pdmc15.pdmc_pd_cnt_is_zero;
195
196wire pdmc_pd_cnt_is_zero_20 = `MCU2.drif.pdmc0.pdmc_pd_cnt_is_zero;
197wire pdmc_pd_cnt_is_zero_21 = `MCU2.drif.pdmc1.pdmc_pd_cnt_is_zero;
198wire pdmc_pd_cnt_is_zero_22 = `MCU2.drif.pdmc2.pdmc_pd_cnt_is_zero;
199wire pdmc_pd_cnt_is_zero_23 = `MCU2.drif.pdmc3.pdmc_pd_cnt_is_zero;
200wire pdmc_pd_cnt_is_zero_24 = `MCU2.drif.pdmc4.pdmc_pd_cnt_is_zero;
201wire pdmc_pd_cnt_is_zero_25 = `MCU2.drif.pdmc5.pdmc_pd_cnt_is_zero;
202wire pdmc_pd_cnt_is_zero_26 = `MCU2.drif.pdmc6.pdmc_pd_cnt_is_zero;
203wire pdmc_pd_cnt_is_zero_27 = `MCU2.drif.pdmc7.pdmc_pd_cnt_is_zero;
204wire pdmc_pd_cnt_is_zero_28 = `MCU2.drif.pdmc8.pdmc_pd_cnt_is_zero;
205wire pdmc_pd_cnt_is_zero_29 = `MCU2.drif.pdmc9.pdmc_pd_cnt_is_zero;
206wire pdmc_pd_cnt_is_zero_2a = `MCU2.drif.pdmc10.pdmc_pd_cnt_is_zero;
207wire pdmc_pd_cnt_is_zero_2b = `MCU2.drif.pdmc11.pdmc_pd_cnt_is_zero;
208wire pdmc_pd_cnt_is_zero_2c = `MCU2.drif.pdmc12.pdmc_pd_cnt_is_zero;
209wire pdmc_pd_cnt_is_zero_2d = `MCU2.drif.pdmc13.pdmc_pd_cnt_is_zero;
210wire pdmc_pd_cnt_is_zero_2e = `MCU2.drif.pdmc14.pdmc_pd_cnt_is_zero;
211wire pdmc_pd_cnt_is_zero_2f = `MCU2.drif.pdmc15.pdmc_pd_cnt_is_zero;
212
213wire pdmc_pd_cnt_is_zero_30 = `MCU3.drif.pdmc0.pdmc_pd_cnt_is_zero;
214wire pdmc_pd_cnt_is_zero_31 = `MCU3.drif.pdmc1.pdmc_pd_cnt_is_zero;
215wire pdmc_pd_cnt_is_zero_32 = `MCU3.drif.pdmc2.pdmc_pd_cnt_is_zero;
216wire pdmc_pd_cnt_is_zero_33 = `MCU3.drif.pdmc3.pdmc_pd_cnt_is_zero;
217wire pdmc_pd_cnt_is_zero_34 = `MCU3.drif.pdmc4.pdmc_pd_cnt_is_zero;
218wire pdmc_pd_cnt_is_zero_35 = `MCU3.drif.pdmc5.pdmc_pd_cnt_is_zero;
219wire pdmc_pd_cnt_is_zero_36 = `MCU3.drif.pdmc6.pdmc_pd_cnt_is_zero;
220wire pdmc_pd_cnt_is_zero_37 = `MCU3.drif.pdmc7.pdmc_pd_cnt_is_zero;
221wire pdmc_pd_cnt_is_zero_38 = `MCU3.drif.pdmc8.pdmc_pd_cnt_is_zero;
222wire pdmc_pd_cnt_is_zero_39 = `MCU3.drif.pdmc9.pdmc_pd_cnt_is_zero;
223wire pdmc_pd_cnt_is_zero_3a = `MCU3.drif.pdmc10.pdmc_pd_cnt_is_zero;
224wire pdmc_pd_cnt_is_zero_3b = `MCU3.drif.pdmc11.pdmc_pd_cnt_is_zero;
225wire pdmc_pd_cnt_is_zero_3c = `MCU3.drif.pdmc12.pdmc_pd_cnt_is_zero;
226wire pdmc_pd_cnt_is_zero_3d = `MCU3.drif.pdmc13.pdmc_pd_cnt_is_zero;
227wire pdmc_pd_cnt_is_zero_3e = `MCU3.drif.pdmc14.pdmc_pd_cnt_is_zero;
228wire pdmc_pd_cnt_is_zero_3f = `MCU3.drif.pdmc15.pdmc_pd_cnt_is_zero;
229
230wire [15:0] pdmc_pd_cnt_is_zero_0 = {pdmc_pd_cnt_is_zero_0f,
231 pdmc_pd_cnt_is_zero_0e,
232 pdmc_pd_cnt_is_zero_0d,
233 pdmc_pd_cnt_is_zero_0c,
234 pdmc_pd_cnt_is_zero_0b,
235 pdmc_pd_cnt_is_zero_0a,
236 pdmc_pd_cnt_is_zero_09,
237 pdmc_pd_cnt_is_zero_08,
238 pdmc_pd_cnt_is_zero_07,
239 pdmc_pd_cnt_is_zero_06,
240 pdmc_pd_cnt_is_zero_05,
241 pdmc_pd_cnt_is_zero_04,
242 pdmc_pd_cnt_is_zero_03,
243 pdmc_pd_cnt_is_zero_02,
244 pdmc_pd_cnt_is_zero_01,
245 pdmc_pd_cnt_is_zero_00};
246reg [15:0] pdmc_pd_cnt_is_zero_0_d;
247
248wire [15:0] pdmc_pd_cnt_is_zero_1 = {pdmc_pd_cnt_is_zero_1f,
249 pdmc_pd_cnt_is_zero_1e,
250 pdmc_pd_cnt_is_zero_1d,
251 pdmc_pd_cnt_is_zero_1c,
252 pdmc_pd_cnt_is_zero_1b,
253 pdmc_pd_cnt_is_zero_1a,
254 pdmc_pd_cnt_is_zero_19,
255 pdmc_pd_cnt_is_zero_18,
256 pdmc_pd_cnt_is_zero_17,
257 pdmc_pd_cnt_is_zero_16,
258 pdmc_pd_cnt_is_zero_15,
259 pdmc_pd_cnt_is_zero_14,
260 pdmc_pd_cnt_is_zero_13,
261 pdmc_pd_cnt_is_zero_12,
262 pdmc_pd_cnt_is_zero_11,
263 pdmc_pd_cnt_is_zero_10};
264
265wire [15:0] pdmc_pd_cnt_is_zero_2 = {pdmc_pd_cnt_is_zero_2f,
266 pdmc_pd_cnt_is_zero_2e,
267 pdmc_pd_cnt_is_zero_2d,
268 pdmc_pd_cnt_is_zero_2c,
269 pdmc_pd_cnt_is_zero_2b,
270 pdmc_pd_cnt_is_zero_2a,
271 pdmc_pd_cnt_is_zero_29,
272 pdmc_pd_cnt_is_zero_28,
273 pdmc_pd_cnt_is_zero_27,
274 pdmc_pd_cnt_is_zero_26,
275 pdmc_pd_cnt_is_zero_25,
276 pdmc_pd_cnt_is_zero_24,
277 pdmc_pd_cnt_is_zero_23,
278 pdmc_pd_cnt_is_zero_22,
279 pdmc_pd_cnt_is_zero_21,
280 pdmc_pd_cnt_is_zero_20};
281
282wire [15:0] pdmc_pd_cnt_is_zero_3 = {pdmc_pd_cnt_is_zero_3f,
283 pdmc_pd_cnt_is_zero_3e,
284 pdmc_pd_cnt_is_zero_3d,
285 pdmc_pd_cnt_is_zero_3c,
286 pdmc_pd_cnt_is_zero_3b,
287 pdmc_pd_cnt_is_zero_3a,
288 pdmc_pd_cnt_is_zero_39,
289 pdmc_pd_cnt_is_zero_38,
290 pdmc_pd_cnt_is_zero_37,
291 pdmc_pd_cnt_is_zero_36,
292 pdmc_pd_cnt_is_zero_35,
293 pdmc_pd_cnt_is_zero_34,
294 pdmc_pd_cnt_is_zero_33,
295 pdmc_pd_cnt_is_zero_32,
296 pdmc_pd_cnt_is_zero_31,
297 pdmc_pd_cnt_is_zero_30};
298
299//-------------------------------------
300// Arbiter Checker Signals
301//-------------------------------------
302
303wire drif0_rd_picked_0 = `MCU0.drif.drif0_rd_picked;
304wire drif0_err_rd_picked_0 = `MCU0.drif.drif0_err_rd_picked;
305wire drif1_rd_picked_0 = `MCU0.drif.drif1_rd_picked;
306wire drif1_err_rd_picked_0 = `MCU0.drif.drif1_err_rd_picked;
307wire drif0_wr_picked_0 = `MCU0.drif.drif0_wr_picked;
308wire drif0_err_wr_picked_0 = `MCU0.drif.drif0_err_wr_picked;
309wire drif1_wr_picked_0 = `MCU0.drif.drif1_wr_picked;
310wire drif1_err_wr_picked_0 = `MCU0.drif.drif1_err_wr_picked;
311wire drif_scrub_picked_0 = `MCU0.drif.drif_scrub_picked;
312wire drif_refresh_req_picked_0 = `MCU0.drif.drif_refresh_req_picked;
313wire [9:0] drif_req_picked_0 = {drif_refresh_req_picked_0,
314 drif_scrub_picked_0,
315 drif1_err_wr_picked_0,
316 drif1_wr_picked_0,
317 drif0_err_wr_picked_0,
318 drif0_wr_picked_0,
319 drif1_err_rd_picked_0,
320 drif1_rd_picked_0,
321 drif0_err_rd_picked_0,
322 drif0_rd_picked_0};
323//-------------------------------------
324// IBIST Checker Signals
325//-------------------------------------
326wire [1:0] ibist_rx_errstat_0 = `MCU0.fbdic.fbdic_nbfibportctl[7:6];
327wire [1:0] ibist_rx_errstat_1 = `MCU1.fbdic.fbdic_nbfibportctl[7:6];
328wire [1:0] ibist_rx_errstat_2 = `MCU2.fbdic.fbdic_nbfibportctl[7:6];
329wire [1:0] ibist_rx_errstat_3 = `MCU3.fbdic.fbdic_nbfibportctl[7:6];
330
331//-------------------------------------
332// Link WMR protect Signals
333//-------------------------------------
334wire rst_wmr_protect = `CPU.rst_wmr_protect;
335
336wire [119:0] mcu_fsr0_data_0 = `MCU0.fdout.mcu_fsr0_data[119:0];
337wire [119:0] mcu_fsr1_data_0 = `MCU0.fdout.mcu_fsr1_data[119:0];
338wire [119:0] mcu_fsr0_data_1 = `MCU1.fdout.mcu_fsr0_data[119:0];
339wire [119:0] mcu_fsr1_data_1 = `MCU1.fdout.mcu_fsr1_data[119:0];
340wire [119:0] mcu_fsr0_data_2 = `MCU2.fdout.mcu_fsr0_data[119:0];
341wire [119:0] mcu_fsr1_data_2 = `MCU2.fdout.mcu_fsr1_data[119:0];
342wire [119:0] mcu_fsr0_data_3 = `MCU3.fdout.mcu_fsr0_data[119:0];
343wire [119:0] mcu_fsr1_data_3 = `MCU3.fdout.mcu_fsr1_data[119:0];
344
345//-------------------------------------
346// WOQ (Dq) Monitor Signals
347//-------------------------------------
348
349wire [1:0] drif_woq_free_0 = `MCU0.drif.reqq.woq.drif_woq_free;
350wire [1:0] drif_woq_free_1 = `MCU1.drif.reqq.woq.drif_woq_free;
351wire [1:0] drif_woq_free_2 = `MCU2.drif.reqq.woq.drif_woq_free;
352wire [1:0] drif_woq_free_3 = `MCU3.drif.reqq.woq.drif_woq_free;
353
354//-----------------------
355// FBDIC Checker Signals
356//-----------------------
357
358wire drl2clk = `MCU0.fbdic.drl2clk;
359wire l2clk = `MCU0.l2clk;
360wire sclk = tb_top.dram_12x_clk;
361
362wire [2:0] mcu0_drif_dram_cmd_a = `MCU0.fbdic.drif_dram_cmd_a;
363wire [2:0] mcu0_drif_dram_bank_a = `MCU0.fbdic.drif_dram_bank_a;
364wire [2:0] mcu0_drif_dram_dimm_a = `MCU0.fbdic.drif_dram_dimm_a;
365wire [15:0] mcu0_drif_dram_addr_a = `MCU0.fbdic.drif_dram_addr_a;
366wire mcu0_drif_dram_rank_a = `MCU0.fbdic.drif_dram_rank_a;
367
368wire [2:0] mcu0_drif_dram_cmd_b = `MCU0.fbdic.drif_dram_cmd_b;
369wire [2:0] mcu0_drif_dram_bank_b = `MCU0.fbdic.drif_dram_bank_b;
370wire [2:0] mcu0_drif_dram_dimm_b = `MCU0.fbdic.drif_dram_dimm_b;
371wire [15:0] mcu0_drif_dram_addr_b = `MCU0.fbdic.drif_dram_addr_b;
372wire mcu0_drif_dram_rank_b = `MCU0.fbdic.drif_dram_rank_b;
373
374wire [2:0] mcu0_drif_dram_cmd_c = `MCU0.fbdic.drif_dram_cmd_c;
375wire [2:0] mcu0_drif_dram_bank_c = `MCU0.fbdic.drif_dram_bank_c;
376wire [2:0] mcu0_drif_dram_dimm_c = `MCU0.fbdic.drif_dram_dimm_c;
377wire [15:0] mcu0_drif_dram_addr_c = `MCU0.fbdic.drif_dram_addr_c;
378wire mcu0_drif_dram_rank_c = `MCU0.fbdic.drif_dram_rank_c;
379
380wire [2:0] mcu1_drif_dram_cmd_a = `MCU1.fbdic.drif_dram_cmd_a;
381wire [2:0] mcu1_drif_dram_bank_a = `MCU1.fbdic.drif_dram_bank_a;
382wire [2:0] mcu1_drif_dram_dimm_a = `MCU1.fbdic.drif_dram_dimm_a;
383wire [15:0] mcu1_drif_dram_addr_a = `MCU1.fbdic.drif_dram_addr_a;
384wire mcu1_drif_dram_rank_a = `MCU1.fbdic.drif_dram_rank_a;
385
386wire [2:0] mcu1_drif_dram_cmd_b = `MCU1.fbdic.drif_dram_cmd_b;
387wire [2:0] mcu1_drif_dram_bank_b = `MCU1.fbdic.drif_dram_bank_b;
388wire [2:0] mcu1_drif_dram_dimm_b = `MCU1.fbdic.drif_dram_dimm_b;
389wire [15:0] mcu1_drif_dram_addr_b = `MCU1.fbdic.drif_dram_addr_b;
390wire mcu1_drif_dram_rank_b = `MCU1.fbdic.drif_dram_rank_b;
391
392wire [2:0] mcu1_drif_dram_cmd_c = `MCU1.fbdic.drif_dram_cmd_c;
393wire [2:0] mcu1_drif_dram_bank_c = `MCU1.fbdic.drif_dram_bank_c;
394wire [2:0] mcu1_drif_dram_dimm_c = `MCU1.fbdic.drif_dram_dimm_c;
395wire [15:0] mcu1_drif_dram_addr_c = `MCU1.fbdic.drif_dram_addr_c;
396wire mcu1_drif_dram_rank_c = `MCU1.fbdic.drif_dram_rank_c;
397
398wire [2:0] mcu2_drif_dram_cmd_a = `MCU2.fbdic.drif_dram_cmd_a;
399wire [2:0] mcu2_drif_dram_bank_a = `MCU2.fbdic.drif_dram_bank_a;
400wire [2:0] mcu2_drif_dram_dimm_a = `MCU2.fbdic.drif_dram_dimm_a;
401wire [15:0] mcu2_drif_dram_addr_a = `MCU2.fbdic.drif_dram_addr_a;
402wire mcu2_drif_dram_rank_a = `MCU2.fbdic.drif_dram_rank_a;
403
404wire [2:0] mcu2_drif_dram_cmd_b = `MCU2.fbdic.drif_dram_cmd_b;
405wire [2:0] mcu2_drif_dram_bank_b = `MCU2.fbdic.drif_dram_bank_b;
406wire [2:0] mcu2_drif_dram_dimm_b = `MCU2.fbdic.drif_dram_dimm_b;
407wire [15:0] mcu2_drif_dram_addr_b = `MCU2.fbdic.drif_dram_addr_b;
408wire mcu2_drif_dram_rank_b = `MCU2.fbdic.drif_dram_rank_b;
409
410wire [2:0] mcu2_drif_dram_cmd_c = `MCU2.fbdic.drif_dram_cmd_c;
411wire [2:0] mcu2_drif_dram_bank_c = `MCU2.fbdic.drif_dram_bank_c;
412wire [2:0] mcu2_drif_dram_dimm_c = `MCU2.fbdic.drif_dram_dimm_c;
413wire [15:0] mcu2_drif_dram_addr_c = `MCU2.fbdic.drif_dram_addr_c;
414wire mcu2_drif_dram_rank_c = `MCU2.fbdic.drif_dram_rank_c;
415
416wire [2:0] mcu3_drif_dram_cmd_a = `MCU3.fbdic.drif_dram_cmd_a;
417wire [2:0] mcu3_drif_dram_bank_a = `MCU3.fbdic.drif_dram_bank_a;
418wire [2:0] mcu3_drif_dram_dimm_a = `MCU3.fbdic.drif_dram_dimm_a;
419wire [15:0] mcu3_drif_dram_addr_a = `MCU3.fbdic.drif_dram_addr_a;
420wire mcu3_drif_dram_rank_a = `MCU3.fbdic.drif_dram_rank_a;
421
422wire [2:0] mcu3_drif_dram_cmd_b = `MCU3.fbdic.drif_dram_cmd_b;
423wire [2:0] mcu3_drif_dram_bank_b = `MCU3.fbdic.drif_dram_bank_b;
424wire [2:0] mcu3_drif_dram_dimm_b = `MCU3.fbdic.drif_dram_dimm_b;
425wire [15:0] mcu3_drif_dram_addr_b = `MCU3.fbdic.drif_dram_addr_b;
426wire mcu3_drif_dram_rank_b = `MCU3.fbdic.drif_dram_rank_b;
427
428wire [2:0] mcu3_drif_dram_cmd_c = `MCU3.fbdic.drif_dram_cmd_c;
429wire [2:0] mcu3_drif_dram_bank_c = `MCU3.fbdic.drif_dram_bank_c;
430wire [2:0] mcu3_drif_dram_dimm_c = `MCU3.fbdic.drif_dram_dimm_c;
431wire [15:0] mcu3_drif_dram_addr_c = `MCU3.fbdic.drif_dram_addr_c;
432wire mcu3_drif_dram_rank_c = `MCU3.fbdic.drif_dram_rank_c;
433
434reg [15:0] mcu0_drif_dram_ras_addr_a;
435reg [15:0] mcu0_drif_dram_ras_addr_b;
436reg [15:0] mcu0_drif_dram_ras_addr_c;
437
438reg [15:0] mcu1_drif_dram_ras_addr_a;
439reg [15:0] mcu1_drif_dram_ras_addr_b;
440reg [15:0] mcu1_drif_dram_ras_addr_c;
441
442reg [15:0] mcu2_drif_dram_ras_addr_a;
443reg [15:0] mcu2_drif_dram_ras_addr_b;
444reg [15:0] mcu2_drif_dram_ras_addr_c;
445
446reg [15:0] mcu3_drif_dram_ras_addr_a;
447reg [15:0] mcu3_drif_dram_ras_addr_b;
448reg [15:0] mcu3_drif_dram_ras_addr_c;
449
450reg [39:0] mcu0_physical_addr_a;
451reg [39:0] mcu0_physical_addr_b;
452reg [39:0] mcu0_physical_addr_c;
453
454reg [39:0] mcu1_physical_addr_a;
455reg [39:0] mcu1_physical_addr_b;
456reg [39:0] mcu1_physical_addr_c;
457
458reg [39:0] mcu2_physical_addr_a;
459reg [39:0] mcu2_physical_addr_b;
460reg [39:0] mcu2_physical_addr_c;
461
462reg [39:0] mcu3_physical_addr_a;
463reg [39:0] mcu3_physical_addr_b;
464reg [39:0] mcu3_physical_addr_c;
465
466wire [7:0] fbdic_fbd_state_0 = `MCU0.fbdic.fbdic_fbd_state;
467wire [7:0] fbdic_fbd_state_1 = `MCU1.fbdic.fbdic_fbd_state;
468wire [7:0] fbdic_fbd_state_2 = `MCU2.fbdic.fbdic_fbd_state;
469wire [7:0] fbdic_fbd_state_3 = `MCU3.fbdic.fbdic_fbd_state;
470
471wire [9:0] fbdimm0a_tx_p_top = tb_top.fbdimm0a_tx_p_top;
472wire [9:0] fbdimm0b_tx_p_top = tb_top.fbdimm0b_tx_p_top;
473wire [9:0] fbdimm1a_tx_p_top = tb_top.fbdimm1a_tx_p_top;
474wire [9:0] fbdimm1b_tx_p_top = tb_top.fbdimm1b_tx_p_top;
475wire [9:0] fbdimm2a_tx_p_top = tb_top.fbdimm2a_tx_p_top;
476wire [9:0] fbdimm2b_tx_p_top = tb_top.fbdimm2b_tx_p_top;
477wire [9:0] fbdimm3a_tx_p_top = tb_top.fbdimm3a_tx_p_top;
478wire [9:0] fbdimm3b_tx_p_top = tb_top.fbdimm3b_tx_p_top;
479
480wire [9:0] fbdimm0a_tx_n_top = tb_top.fbdimm0a_tx_n_top;
481wire [9:0] fbdimm0b_tx_n_top = tb_top.fbdimm0b_tx_n_top;
482wire [9:0] fbdimm1a_tx_n_top = tb_top.fbdimm1a_tx_n_top;
483wire [9:0] fbdimm1b_tx_n_top = tb_top.fbdimm1b_tx_n_top;
484wire [9:0] fbdimm2a_tx_n_top = tb_top.fbdimm2a_tx_n_top;
485wire [9:0] fbdimm2b_tx_n_top = tb_top.fbdimm2b_tx_n_top;
486wire [9:0] fbdimm3a_tx_n_top = tb_top.fbdimm3a_tx_n_top;
487wire [9:0] fbdimm3b_tx_n_top = tb_top.fbdimm3b_tx_n_top;
488
489wire [14:0] fbdimm0a_rx_p_top = tb_top.fbdimm0a_rx_p_top;
490wire [14:0] fbdimm0b_rx_p_top = tb_top.fbdimm0b_rx_p_top;
491wire [14:0] fbdimm1a_rx_p_top = tb_top.fbdimm1a_rx_p_top;
492wire [14:0] fbdimm1b_rx_p_top = tb_top.fbdimm1b_rx_p_top;
493wire [14:0] fbdimm2a_rx_p_top = tb_top.fbdimm2a_rx_p_top;
494wire [14:0] fbdimm2b_rx_p_top = tb_top.fbdimm2b_rx_p_top;
495wire [14:0] fbdimm3a_rx_p_top = tb_top.fbdimm3a_rx_p_top;
496wire [14:0] fbdimm3b_rx_p_top = tb_top.fbdimm3b_rx_p_top;
497
498wire [14:0] fbdimm0a_rx_n_top = tb_top.fbdimm0a_rx_n_top;
499wire [14:0] fbdimm0b_rx_n_top = tb_top.fbdimm0b_rx_n_top;
500wire [14:0] fbdimm1a_rx_n_top = tb_top.fbdimm1a_rx_n_top;
501wire [14:0] fbdimm1b_rx_n_top = tb_top.fbdimm1b_rx_n_top;
502wire [14:0] fbdimm2a_rx_n_top = tb_top.fbdimm2a_rx_n_top;
503wire [14:0] fbdimm2b_rx_n_top = tb_top.fbdimm2b_rx_n_top;
504wire [14:0] fbdimm3a_rx_n_top = tb_top.fbdimm3a_rx_n_top;
505wire [14:0] fbdimm3b_rx_n_top = tb_top.fbdimm3b_rx_n_top;
506
507reg [11:0] sync_frame_UI_err_0a;
508reg [11:0] sync_frame_UI_err_0b;
509reg [11:0] sync_frame_UI_err_1a;
510reg [11:0] sync_frame_UI_err_1b;
511reg [11:0] sync_frame_UI_err_2a;
512reg [11:0] sync_frame_UI_err_2b;
513reg [11:0] sync_frame_UI_err_3a;
514reg [11:0] sync_frame_UI_err_3b;
515
516reg chnl_type; // Dual Channel or Single Channel
517reg rank_addr; // RANK HI addr = 1, RANK LOW addr = 0
518reg [2:0] num_dimms; // DIMM NUMBERS: 1, 2, 4, 6, 8
519reg rank; // 1 RANK or 2 RANKS
520reg [1:0] dimm_size ;
521
522wire [15:0] fbdic_failover_config_0 = `MCU0.fbdic.fbdic_failover_config ;
523wire [15:0] fbdic_failover_config_1 = `MCU1.fbdic.fbdic_failover_config ;
524wire [15:0] fbdic_failover_config_2 = `MCU2.fbdic.fbdic_failover_config ;
525wire [15:0] fbdic_failover_config_3 = `MCU3.fbdic.fbdic_failover_config ;
526
527wire fbdic_l0_state_0 = `MCU0.fbdic.fbdic_l0_state ;
528wire fbdic_l0_state_1 = `MCU1.fbdic.fbdic_l0_state ;
529wire fbdic_l0_state_2 = `MCU2.fbdic.fbdic_l0_state ;
530wire fbdic_l0_state_3 = `MCU3.fbdic.fbdic_l0_state ;
531
532reg [9:0] mcu0_clk_train_pat0;
533reg [9:0] mcu0_clk_train_pat1;
534reg [9:0] mcu1_clk_train_pat0;
535reg [9:0] mcu1_clk_train_pat1;
536reg [9:0] mcu2_clk_train_pat0;
537reg [9:0] mcu2_clk_train_pat1;
538reg [9:0] mcu3_clk_train_pat0;
539reg [9:0] mcu3_clk_train_pat1;
540
541wire mcu0_fbdic_f_1_l = `MCU0.fbdiwr.fbdic_f_1_l ;
542wire mcu1_fbdic_f_1_l = `MCU1.fbdiwr.fbdic_f_1_l ;
543wire mcu2_fbdic_f_1_l = `MCU2.fbdiwr.fbdic_f_1_l ;
544wire mcu3_fbdic_f_1_l = `MCU3.fbdiwr.fbdic_f_1_l ;
545
546wire [1:0] mcu0_fbdic_f = `MCU0.fbdiwr.fbdic_f ;
547wire [1:0] mcu1_fbdic_f = `MCU1.fbdiwr.fbdic_f ;
548wire [1:0] mcu2_fbdic_f = `MCU2.fbdiwr.fbdic_f ;
549wire [1:0] mcu3_fbdic_f = `MCU3.fbdiwr.fbdic_f ;
550
551wire [71:0] mcu0_fbdiwr_bc_cmd_data0 = `MCU0.fbdiwr.fbdiwr_bc_cmd_data0 ;
552wire [71:0] mcu0_fbdiwr_bc_cmd_data1 = `MCU0.fbdiwr.fbdiwr_bc_cmd_data1 ;
553wire [71:0] mcu1_fbdiwr_bc_cmd_data0 = `MCU1.fbdiwr.fbdiwr_bc_cmd_data0 ;
554wire [71:0] mcu1_fbdiwr_bc_cmd_data1 = `MCU1.fbdiwr.fbdiwr_bc_cmd_data1 ;
555wire [71:0] mcu2_fbdiwr_bc_cmd_data0 = `MCU2.fbdiwr.fbdiwr_bc_cmd_data0 ;
556wire [71:0] mcu2_fbdiwr_bc_cmd_data1 = `MCU2.fbdiwr.fbdiwr_bc_cmd_data1 ;
557wire [71:0] mcu3_fbdiwr_bc_cmd_data0 = `MCU3.fbdiwr.fbdiwr_bc_cmd_data0 ;
558wire [71:0] mcu3_fbdiwr_bc_cmd_data1 = `MCU3.fbdiwr.fbdiwr_bc_cmd_data1 ;
559
560reg [1:0] mcu0_fbdic_f_1_cnt;
561reg [1:0] mcu1_fbdic_f_1_cnt;
562reg [1:0] mcu2_fbdic_f_1_cnt;
563reg [1:0] mcu3_fbdic_f_1_cnt;
564
565reg [2:0] mcu0_wdata_dimm;
566reg [2:0] mcu1_wdata_dimm;
567reg [2:0] mcu2_wdata_dimm;
568reg [2:0] mcu3_wdata_dimm;
569
570reg sync_collision_check_enable;
571
572reg mcu0_l2t_mecc_err_r3_detected;
573reg mcu0_l2t0_scb_mecc_err_detected;
574reg mcu1_l2t_mecc_err_r3_detected;
575reg mcu1_l2t0_scb_mecc_err_detected;
576reg mcu2_l2t_mecc_err_r3_detected;
577reg mcu2_l2t0_scb_mecc_err_detected;
578reg mcu3_l2t_mecc_err_r3_detected;
579reg mcu3_l2t0_scb_mecc_err_detected;
580
581//-------------------------------------------------
582// Warm Protect (mcu_fbd_protect) checker signals
583//-------------------------------------------------
584
585//wire mcu0_rst_mcu_fbd_protect = `MCU0.rst_mcu_fbd_protect ;
586//wire mcu1_rst_mcu_fbd_protect = `MCU1.rst_mcu_fbd_protect ;
587//wire mcu2_rst_mcu_fbd_protect = `MCU2.rst_mcu_fbd_protect ;
588//wire mcu3_rst_mcu_fbd_protect = `MCU3.rst_mcu_fbd_protect ;
589
590//--------------------------------------
591// Wr/Rd Cnfg CMDS : TID Checker signals
592//--------------------------------------
593
594reg fbdic0_last_tid_0;
595reg fbdic0_last_tid_1;
596reg fbdic0_last_tid_2;
597reg fbdic0_last_tid_3;
598
599reg fbdic1_last_tid_0;
600reg fbdic1_last_tid_1;
601reg fbdic1_last_tid_2;
602reg fbdic1_last_tid_3;
603
604wire fbdic_trans_id_0;
605wire fbdic_trans_id_1;
606wire fbdic_trans_id_2;
607wire fbdic_trans_id_3;
608
609reg chnl_0;
610reg chnl_1;
611reg chnl_2;
612reg chnl_3;
613
614wire [31:0] drif_ucb_addr_0 = `MCU0.fbdic.drif_ucb_addr;
615wire [31:0] drif_ucb_addr_1 = `MCU1.fbdic.drif_ucb_addr;
616wire [31:0] drif_ucb_addr_2 = `MCU2.fbdic.drif_ucb_addr;
617wire [31:0] drif_ucb_addr_3 = `MCU3.fbdic.drif_ucb_addr;
618
619wire [63:0] drif_ucb_data_0 = `MCU0.fbdic.drif_ucb_data;
620wire [63:0] drif_ucb_data_1 = `MCU1.fbdic.drif_ucb_data;
621wire [63:0] drif_ucb_data_2 = `MCU2.fbdic.drif_ucb_data;
622wire [63:0] drif_ucb_data_3 = `MCU3.fbdic.drif_ucb_data;
623
624wire fbdic_config_reg_write_0 = `MCU0.fbdic.fbdic_config_reg_write;
625wire fbdic_config_reg_write_1 = `MCU1.fbdic.fbdic_config_reg_write;
626wire fbdic_config_reg_write_2 = `MCU2.fbdic.fbdic_config_reg_write;
627wire fbdic_config_reg_write_3 = `MCU3.fbdic.fbdic_config_reg_write;
628
629wire drif_ucb_wr_req_vld_0 = `MCU0.fbdic.drif_ucb_wr_req_vld;
630wire drif_ucb_wr_req_vld_1 = `MCU1.fbdic.drif_ucb_wr_req_vld;
631wire drif_ucb_wr_req_vld_2 = `MCU2.fbdic.drif_ucb_wr_req_vld;
632wire drif_ucb_wr_req_vld_3 = `MCU3.fbdic.drif_ucb_wr_req_vld;
633
634//-----------------------------------
635// Readdp data X checkers/monitors
636//-----------------------------------
637
638wire mcu0_rdpctl_l2t0_data_valid = `MCU0.rdpctl.rdpctl_l2t0_data_valid;
639wire mcu0_rdpctl_l2t1_data_valid = `MCU0.rdpctl.rdpctl_l2t1_data_valid;
640wire mcu1_rdpctl_l2t0_data_valid = `MCU1.rdpctl.rdpctl_l2t0_data_valid;
641wire mcu1_rdpctl_l2t1_data_valid = `MCU1.rdpctl.rdpctl_l2t1_data_valid;
642wire mcu2_rdpctl_l2t0_data_valid = `MCU2.rdpctl.rdpctl_l2t0_data_valid;
643wire mcu2_rdpctl_l2t1_data_valid = `MCU2.rdpctl.rdpctl_l2t1_data_valid;
644wire mcu3_rdpctl_l2t0_data_valid = `MCU3.rdpctl.rdpctl_l2t0_data_valid;
645wire mcu3_rdpctl_l2t1_data_valid = `MCU3.rdpctl.rdpctl_l2t1_data_valid;
646
647wire [127:0] mcu0_rddata_0 = `MCU0.readdp0.rddata[127:0] ;
648wire [127:0] mcu0_rddata_1 = `MCU0.readdp1.rddata[127:0] ;
649wire [127:0] mcu1_rddata_0 = `MCU1.readdp0.rddata[127:0] ;
650wire [127:0] mcu1_rddata_1 = `MCU1.readdp1.rddata[127:0] ;
651wire [127:0] mcu2_rddata_0 = `MCU2.readdp0.rddata[127:0] ;
652wire [127:0] mcu2_rddata_1 = `MCU2.readdp1.rddata[127:0] ;
653wire [127:0] mcu3_rddata_0 = `MCU3.readdp0.rddata[127:0] ;
654wire [127:0] mcu3_rddata_1 = `MCU3.readdp1.rddata[127:0] ;
655
656//-----------------------------------------------
657// SYNC & STATUS Frames Checker Signals
658//-----------------------------------------------
659
660wire [5:0] mcu0_fbdic_sync_frm_period = `MCU0.fbdic.fbdic_sync_frm_period;
661wire [5:0] mcu1_fbdic_sync_frm_period = `MCU1.fbdic.fbdic_sync_frm_period;
662wire [5:0] mcu2_fbdic_sync_frm_period = `MCU2.fbdic.fbdic_sync_frm_period;
663wire [5:0] mcu3_fbdic_sync_frm_period = `MCU3.fbdic.fbdic_sync_frm_period;
664
665wire [15:0] mcu0_fbdic_chnl_read_lat = `MCU0.fbdic.fbdic_chnl_read_lat;
666wire [15:0] mcu1_fbdic_chnl_read_lat = `MCU1.fbdic.fbdic_chnl_read_lat;
667wire [15:0] mcu2_fbdic_chnl_read_lat = `MCU2.fbdic.fbdic_chnl_read_lat;
668wire [15:0] mcu3_fbdic_chnl_read_lat = `MCU3.fbdic.fbdic_chnl_read_lat;
669
670wire mcu0_fbdic_sync_frame_req = `MCU0.fbdic.fbdic_sync_frame_req;
671wire mcu1_fbdic_sync_frame_req = `MCU1.fbdic.fbdic_sync_frame_req;
672wire mcu2_fbdic_sync_frame_req = `MCU2.fbdic.fbdic_sync_frame_req;
673wire mcu3_fbdic_sync_frame_req = `MCU3.fbdic.fbdic_sync_frame_req;
674
675wire mcu0_fbdic_status_frame = `MCU0.fbdic.fbdic_status_frame;
676wire mcu1_fbdic_status_frame = `MCU1.fbdic.fbdic_status_frame;
677wire mcu2_fbdic_status_frame = `MCU2.fbdic.fbdic_status_frame;
678wire mcu3_fbdic_status_frame = `MCU3.fbdic.fbdic_status_frame;
679
680wire [1:0] mcu0_fbdic_sync_sd = `MCU0.fbdic.fbdic_sync_sd;
681wire [1:0] mcu1_fbdic_sync_sd = `MCU1.fbdic.fbdic_sync_sd;
682wire [1:0] mcu2_fbdic_sync_sd = `MCU2.fbdic.fbdic_sync_sd;
683wire [1:0] mcu3_fbdic_sync_sd = `MCU3.fbdic.fbdic_sync_sd;
684
685integer mcu0_chnl_lat,mcu0_chnl_lat_int;
686integer mcu1_chnl_lat,mcu1_chnl_lat_int;
687integer mcu2_chnl_lat,mcu2_chnl_lat_int;
688integer mcu3_chnl_lat,mcu3_chnl_lat_int;
689
690integer mcu0_sync_sd;
691integer mcu1_sync_sd;
692integer mcu2_sync_sd;
693integer mcu3_sync_sd;
694
695integer dummy;
696
697//-----------------------------------------------
698// SOFT CHANNEL RESET (SCR) Frame Checker Signals
699//-----------------------------------------------
700
701wire mcu0_fbdic_scr_frame_req = `MCU0.fbdic.fbdic_scr_frame_req;
702wire mcu1_fbdic_scr_frame_req = `MCU1.fbdic.fbdic_scr_frame_req;
703wire mcu2_fbdic_scr_frame_req = `MCU2.fbdic.fbdic_scr_frame_req;
704wire mcu3_fbdic_scr_frame_req = `MCU3.fbdic.fbdic_scr_frame_req;
705
706wire mcu0_fbdic_scr_response_frame = `MCU0.fbdic.fbdic_scr_response_frame;
707wire mcu1_fbdic_scr_response_frame = `MCU1.fbdic.fbdic_scr_response_frame;
708wire mcu2_fbdic_scr_response_frame = `MCU2.fbdic.fbdic_scr_response_frame;
709wire mcu3_fbdic_scr_response_frame = `MCU3.fbdic.fbdic_scr_response_frame;
710
711wire mcu0_fbdic_scr = `MCU0.fbdic.fbdic_scr;
712wire mcu1_fbdic_scr = `MCU1.fbdic.fbdic_scr;
713wire mcu2_fbdic_scr = `MCU2.fbdic.fbdic_scr;
714wire mcu3_fbdic_scr = `MCU3.fbdic.fbdic_scr;
715
716reg [2:0] mcu0_drif_dram_cmd_a_prev;
717reg [2:0] mcu0_drif_dram_cmd_b_prev;
718reg [2:0] mcu0_drif_dram_cmd_c_prev;
719
720reg [2:0] mcu1_drif_dram_cmd_a_prev;
721reg [2:0] mcu1_drif_dram_cmd_b_prev;
722reg [2:0] mcu1_drif_dram_cmd_c_prev;
723
724reg [2:0] mcu2_drif_dram_cmd_a_prev;
725reg [2:0] mcu2_drif_dram_cmd_b_prev;
726reg [2:0] mcu2_drif_dram_cmd_c_prev;
727
728reg [2:0] mcu3_drif_dram_cmd_a_prev;
729reg [2:0] mcu3_drif_dram_cmd_b_prev;
730reg [2:0] mcu3_drif_dram_cmd_c_prev;
731
732//--------------------------------------
733// Status Parity Error
734//--------------------------------------
735
736wire mcu0_fbdic_status_parity_error = `MCU0.fbdic.fbdic_status_parity_error;
737wire mcu1_fbdic_status_parity_error = `MCU1.fbdic.fbdic_status_parity_error;
738wire mcu2_fbdic_status_parity_error = `MCU2.fbdic.fbdic_status_parity_error;
739wire mcu3_fbdic_status_parity_error = `MCU3.fbdic.fbdic_status_parity_error;
740
741//--------------------------------------
742// Status Alert Bit Error
743//--------------------------------------
744
745wire mcu0_fbdic_status_alert_error = `MCU0.fbdic.fbdic_alert_asserted;
746wire mcu1_fbdic_status_alert_error = `MCU1.fbdic.fbdic_alert_asserted;
747wire mcu2_fbdic_status_alert_error = `MCU2.fbdic.fbdic_alert_asserted;
748wire mcu3_fbdic_status_alert_error = `MCU3.fbdic.fbdic_alert_asserted;
749
750//--------------------------------------
751// Status Alert Frame Error
752//--------------------------------------
753
754wire mcu0_fbdic_alert_frame = `MCU0.fbdic.fbdic_alert_frame;
755wire mcu1_fbdic_alert_frame = `MCU1.fbdic.fbdic_alert_frame;
756wire mcu2_fbdic_alert_frame = `MCU2.fbdic.fbdic_alert_frame;
757wire mcu3_fbdic_alert_frame = `MCU3.fbdic.fbdic_alert_frame;
758
759//----------------------------
760// FBD Init Signals
761//----------------------------
762
763wire mcu0_fbdic_fast_reset = `MCU0.fbdic.fbdic_fast_reset;
764wire mcu1_fbdic_fast_reset = `MCU1.fbdic.fbdic_fast_reset;
765wire mcu2_fbdic_fast_reset = `MCU2.fbdic.fbdic_fast_reset;
766wire mcu3_fbdic_fast_reset = `MCU3.fbdic.fbdic_fast_reset;
767
768wire [13:0] mcu0_fbd0_elect_idle = `MCU0.fbdic.fbd0_elect_idle;
769wire [13:0] mcu1_fbd0_elect_idle = `MCU1.fbdic.fbd0_elect_idle;
770wire [13:0] mcu2_fbd0_elect_idle = `MCU2.fbdic.fbd0_elect_idle;
771wire [13:0] mcu3_fbd0_elect_idle = `MCU3.fbdic.fbd0_elect_idle;
772
773wire [13:0] mcu0_fbd1_elect_idle = `MCU0.fbdic.fbd1_elect_idle;
774wire [13:0] mcu1_fbd1_elect_idle = `MCU1.fbdic.fbd1_elect_idle;
775wire [13:0] mcu2_fbd1_elect_idle = `MCU2.fbdic.fbd1_elect_idle;
776wire [13:0] mcu3_fbd1_elect_idle = `MCU3.fbdic.fbd1_elect_idle;
777
778wire mcu0_fbdic_tdisable_done = `MCU0.fbdic.fbdic_tdisable_done;
779wire mcu1_fbdic_tdisable_done = `MCU1.fbdic.fbdic_tdisable_done;
780wire mcu2_fbdic_tdisable_done = `MCU2.fbdic.fbdic_tdisable_done;
781wire mcu3_fbdic_tdisable_done = `MCU3.fbdic.fbdic_tdisable_done;
782
783wire mcu0_fbdic_tcalibrate_done = `MCU0.fbdic.fbdic_tcalibrate_done;
784wire mcu1_fbdic_tcalibrate_done = `MCU1.fbdic.fbdic_tcalibrate_done;
785wire mcu2_fbdic_tcalibrate_done = `MCU2.fbdic.fbdic_tcalibrate_done;
786wire mcu3_fbdic_tcalibrate_done = `MCU3.fbdic.fbdic_tcalibrate_done;
787
788wire [1:0] mcu0_fbdic_tclktrain_done = `MCU0.fbdic.fbdic_tclktrain_done;
789wire [1:0] mcu1_fbdic_tclktrain_done = `MCU1.fbdic.fbdic_tclktrain_done;
790wire [1:0] mcu2_fbdic_tclktrain_done = `MCU2.fbdic.fbdic_tclktrain_done;
791wire [1:0] mcu3_fbdic_tclktrain_done = `MCU3.fbdic.fbdic_tclktrain_done;
792
793wire [1:0] mcu0_fbdic_testing_done = `MCU0.fbdic.fbdic_testing_done;
794wire [1:0] mcu1_fbdic_testing_done = `MCU1.fbdic.fbdic_testing_done;
795wire [1:0] mcu2_fbdic_testing_done = `MCU2.fbdic.fbdic_testing_done;
796wire [1:0] mcu3_fbdic_testing_done = `MCU3.fbdic.fbdic_testing_done;
797
798wire [1:0] mcu0_fbdic_polling_done = `MCU0.fbdic.fbdic_polling_done;
799wire [1:0] mcu1_fbdic_polling_done = `MCU1.fbdic.fbdic_polling_done;
800wire [1:0] mcu2_fbdic_polling_done = `MCU2.fbdic.fbdic_polling_done;
801wire [1:0] mcu3_fbdic_polling_done = `MCU3.fbdic.fbdic_polling_done;
802
803wire [1:0] mcu0_fbdic_config_done = `MCU0.fbdic.fbdic_config_done;
804wire [1:0] mcu1_fbdic_config_done = `MCU1.fbdic.fbdic_config_done;
805wire [1:0] mcu2_fbdic_config_done = `MCU2.fbdic.fbdic_config_done;
806wire [1:0] mcu3_fbdic_config_done = `MCU3.fbdic.fbdic_config_done;
807
808reg enidl_chk_on;
809
810//--------------------------------------
811// CRC RETRY : BEFORE WRITE QUEUE EMPTY; WR SENT TO WRONG LOCATION
812//--------------------------------------
813
814wire mcu0_crc_retry_wr_q_not_empty = `MCU0.drif.drif_wr_picked & (|(`MCU0.drif.drif_err_state[4:1]));
815
816wire mcu1_crc_retry_wr_q_not_empty = `MCU1.drif.drif_wr_picked & (|(`MCU1.drif.drif_err_state[4:1]));
817
818wire mcu2_crc_retry_wr_q_not_empty = `MCU2.drif.drif_wr_picked & (|(`MCU2.drif.drif_err_state[4:1]));
819
820wire mcu3_crc_retry_wr_q_not_empty = `MCU3.drif.drif_wr_picked & (|(`MCU3.drif.drif_err_state[4:1]));
821
822//--------------------------------------
823// Collision : Alertframe and CRC Error assert at the same time
824//--------------------------------------
825
826wire mcu0_alertframe_crc_error = `MCU0.drif.drif_err_state[4] & `MCU0.fbdic.fbdic_err_state[5];
827wire mcu1_alertframe_crc_error = `MCU1.drif.drif_err_state[4] & `MCU1.fbdic.fbdic_err_state[5];
828wire mcu2_alertframe_crc_error = `MCU2.drif.drif_err_state[4] & `MCU2.fbdic.fbdic_err_state[5];
829wire mcu3_alertframe_crc_error = `MCU3.drif.drif_err_state[4] & `MCU3.fbdic.fbdic_err_state[5];
830
831//------------------------------------------------
832// Arbitration/Collision Signals
833//------------------------------------------------
834
835wire mcu0_drif_ucb_wr_req_vld = `MCU0.fbdic.drif_ucb_wr_req_vld;
836wire mcu1_drif_ucb_wr_req_vld = `MCU1.fbdic.drif_ucb_wr_req_vld;
837wire mcu2_drif_ucb_wr_req_vld = `MCU2.fbdic.drif_ucb_wr_req_vld;
838wire mcu3_drif_ucb_wr_req_vld = `MCU3.fbdic.drif_ucb_wr_req_vld;
839
840wire mcu0_drif_ucb_rd_req_vld = `MCU0.fbdic.drif_ucb_rd_req_vld;
841wire mcu1_drif_ucb_rd_req_vld = `MCU1.fbdic.drif_ucb_rd_req_vld;
842wire mcu2_drif_ucb_rd_req_vld = `MCU2.fbdic.drif_ucb_rd_req_vld;
843wire mcu3_drif_ucb_rd_req_vld = `MCU3.fbdic.drif_ucb_rd_req_vld;
844
845reg mcu0_drif_ucb_wr_req_vld_REG;
846reg mcu1_drif_ucb_wr_req_vld_REG;
847reg mcu2_drif_ucb_wr_req_vld_REG;
848reg mcu3_drif_ucb_wr_req_vld_REG;
849
850reg mcu0_drif_ucb_rd_req_vld_REG;
851reg mcu1_drif_ucb_rd_req_vld_REG;
852reg mcu2_drif_ucb_rd_req_vld_REG;
853reg mcu3_drif_ucb_rd_req_vld_REG;
854
855reg [2:0] mcu0_drif_dram_cmd_a_REG;
856reg [2:0] mcu0_drif_dram_cmd_b_REG;
857reg [2:0] mcu0_drif_dram_cmd_c_REG;
858
859reg [2:0] mcu1_drif_dram_cmd_a_REG;
860reg [2:0] mcu1_drif_dram_cmd_b_REG;
861reg [2:0] mcu1_drif_dram_cmd_c_REG;
862
863reg [2:0] mcu2_drif_dram_cmd_a_REG;
864reg [2:0] mcu2_drif_dram_cmd_b_REG;
865reg [2:0] mcu2_drif_dram_cmd_c_REG;
866
867reg [2:0] mcu3_drif_dram_cmd_a_REG;
868reg [2:0] mcu3_drif_dram_cmd_b_REG;
869reg [2:0] mcu3_drif_dram_cmd_c_REG;
870
871//---------------------------
872// Refresh Checker Signals
873//---------------------------
874
875wire [4:0] mcu0_drif_mcu_state_next = `MCU0.drif.drif_mcu_state_next;
876wire [4:0] mcu1_drif_mcu_state_next = `MCU1.drif.drif_mcu_state_next;
877wire [4:0] mcu2_drif_mcu_state_next = `MCU2.drif.drif_mcu_state_next;
878wire [4:0] mcu3_drif_mcu_state_next = `MCU3.drif.drif_mcu_state_next;
879
880integer ref_state5_cycle_0 = 0;
881integer ref_state5_cycle_1 = 0;
882integer ref_state5_cycle_2 = 0;
883integer ref_state5_cycle_3 = 0;
884
885integer ref_state6_cycle_0 = 0;
886integer ref_state6_cycle_1 = 0;
887integer ref_state6_cycle_2 = 0;
888integer ref_state6_cycle_3 = 0;
889
890//---------------------------------
891// FBD Channel Error & DTM Signals
892//---------------------------------
893
894reg dtm_enabled;
895reg fbd_init_check;
896
897reg [7:0] mcu0_nb_channel_error_cnt;
898reg [7:0] mcu1_nb_channel_error_cnt;
899reg [7:0] mcu2_nb_channel_error_cnt;
900reg [7:0] mcu3_nb_channel_error_cnt;
901
902reg [7:0] mcu0_sb_channel_error_cnt_tmp;
903reg [7:0] mcu1_sb_channel_error_cnt_tmp;
904reg [7:0] mcu2_sb_channel_error_cnt_tmp;
905reg [7:0] mcu3_sb_channel_error_cnt_tmp;
906
907reg [7:0] mcu0_sb_channel_error_cnt;
908reg [7:0] mcu1_sb_channel_error_cnt;
909reg [7:0] mcu2_sb_channel_error_cnt;
910reg [7:0] mcu3_sb_channel_error_cnt;
911
912
913reg mcu0_nb_err_enable;
914reg mcu1_nb_err_enable;
915reg mcu2_nb_err_enable;
916reg mcu3_nb_err_enable;
917
918reg mcu0_sb_err_enable;
919reg mcu1_sb_err_enable;
920reg mcu2_sb_err_enable;
921reg mcu3_sb_err_enable;
922
923reg mcu0_nb_err_random;
924reg mcu1_nb_err_random;
925reg mcu2_nb_err_random;
926reg mcu3_nb_err_random;
927
928reg mcu0_sb_err_random;
929reg mcu1_sb_err_random;
930reg mcu2_sb_err_random;
931reg mcu3_sb_err_random;
932
933integer mcu0_nb_random_val;
934integer mcu1_nb_random_val;
935integer mcu2_nb_random_val;
936integer mcu3_nb_random_val;
937
938integer mcu0_sb_random_val;
939integer mcu1_sb_random_val;
940integer mcu2_sb_random_val;
941integer mcu3_sb_random_val;
942
943integer mcu0_sb_random_cycle;
944integer mcu1_sb_random_cycle;
945integer mcu2_sb_random_cycle;
946integer mcu3_sb_random_cycle;
947
948integer mcu0_nb_random_cycle;
949integer mcu1_nb_random_cycle;
950integer mcu2_nb_random_cycle;
951integer mcu3_nb_random_cycle;
952
953integer mcu0_sb_random_lane=1;
954integer mcu1_sb_random_lane=1;
955integer mcu2_sb_random_lane=1;
956integer mcu3_sb_random_lane=1;
957
958integer mcu0_nb_random_lane=1;
959integer mcu1_nb_random_lane=1;
960integer mcu2_nb_random_lane=1;
961integer mcu3_nb_random_lane=1;
962
963integer mcu0_sb_random_bit_time=1;
964integer mcu1_sb_random_bit_time=1;
965integer mcu2_sb_random_bit_time=1;
966integer mcu3_sb_random_bit_time=1;
967
968integer mcu0_nb_random_bit_time=1;
969integer mcu1_nb_random_bit_time=1;
970integer mcu2_nb_random_bit_time=1;
971integer mcu3_nb_random_bit_time=1;
972
973reg [9:0] mcu0_sb_lane_mask;
974reg [9:0] mcu1_sb_lane_mask;
975reg [9:0] mcu2_sb_lane_mask;
976reg [9:0] mcu3_sb_lane_mask;
977
978reg [13:0] mcu0_nb_lane_mask;
979reg [13:0] mcu1_nb_lane_mask;
980reg [13:0] mcu2_nb_lane_mask;
981reg [13:0] mcu3_nb_lane_mask;
982
983reg mcu0_sb_crc_multiple_lanes;
984reg mcu1_sb_crc_multiple_lanes;
985reg mcu2_sb_crc_multiple_lanes;
986reg mcu3_sb_crc_multiple_lanes;
987
988reg mcu0_nb_crc_multiple_lanes;
989reg mcu1_nb_crc_multiple_lanes;
990reg mcu2_nb_crc_multiple_lanes;
991reg mcu3_nb_crc_multiple_lanes;
992
993reg [11:0] mcu0_sb_bit_time_mask;
994reg [11:0] mcu1_sb_bit_time_mask;
995reg [11:0] mcu2_sb_bit_time_mask;
996reg [11:0] mcu3_sb_bit_time_mask;
997
998reg [11:0] mcu0_nb_bit_time_mask;
999reg [11:0] mcu1_nb_bit_time_mask;
1000reg [11:0] mcu2_nb_bit_time_mask;
1001reg [11:0] mcu3_nb_bit_time_mask;
1002
1003reg mcu0_sb_crc_multiple_bit_times;
1004reg mcu1_sb_crc_multiple_bit_times;
1005reg mcu2_sb_crc_multiple_bit_times;
1006reg mcu3_sb_crc_multiple_bit_times;
1007
1008reg mcu0_nb_crc_multiple_bit_times;
1009reg mcu1_nb_crc_multiple_bit_times;
1010reg mcu2_nb_crc_multiple_bit_times;
1011reg mcu3_nb_crc_multiple_bit_times;
1012
1013integer MCU0_NB_RANDOM_WEIGHT;
1014integer MCU1_NB_RANDOM_WEIGHT;
1015integer MCU2_NB_RANDOM_WEIGHT;
1016integer MCU3_NB_RANDOM_WEIGHT;
1017
1018integer MCU0_SB_RANDOM_WEIGHT;
1019integer MCU1_SB_RANDOM_WEIGHT;
1020integer MCU2_SB_RANDOM_WEIGHT;
1021integer MCU3_SB_RANDOM_WEIGHT;
1022
1023integer mcu0_nb_cycle_cnt;
1024integer mcu1_nb_cycle_cnt;
1025integer mcu2_nb_cycle_cnt;
1026integer mcu3_nb_cycle_cnt;
1027
1028reg mcu0_inject_fbu_err;
1029reg mcu1_inject_fbu_err;
1030reg mcu2_inject_fbu_err;
1031reg mcu3_inject_fbu_err;
1032
1033reg mcu0_enable_ch0_err_inj;
1034reg mcu1_enable_ch0_err_inj;
1035reg mcu2_enable_ch0_err_inj;
1036reg mcu3_enable_ch0_err_inj;
1037
1038reg mcu0_enable_ch1_err_inj;
1039reg mcu1_enable_ch1_err_inj;
1040reg mcu2_enable_ch1_err_inj;
1041reg mcu3_enable_ch1_err_inj;
1042
1043wire mcu0_esr_fbr = `MCU0.drif.rdpctl_err_sts_reg[16];
1044wire mcu1_esr_fbr = `MCU1.drif.rdpctl_err_sts_reg[16];
1045wire mcu2_esr_fbr = `MCU2.drif.rdpctl_err_sts_reg[16];
1046wire mcu3_esr_fbr = `MCU3.drif.rdpctl_err_sts_reg[16];
1047
1048wire mcu0_esr_fbu = `MCU0.drif.rdpctl_err_sts_reg[17];
1049wire mcu1_esr_fbu = `MCU1.drif.rdpctl_err_sts_reg[17];
1050wire mcu2_esr_fbu = `MCU2.drif.rdpctl_err_sts_reg[17];
1051wire mcu3_esr_fbu = `MCU3.drif.rdpctl_err_sts_reg[17];
1052
1053// --- FBU ---
1054
1055wire mcu0_synd_SPE = `MCU0.fbdic.fbdic_mcu_syndrome[3];
1056wire mcu0_synd_AA = `MCU0.fbdic.fbdic_mcu_syndrome[2];
1057wire mcu0_synd_AF = `MCU0.fbdic.fbdic_mcu_syndrome[1];
1058wire mcu0_synd_C = `MCU0.fbdic.fbdic_mcu_syndrome[0];
1059
1060wire mcu1_synd_SPE = `MCU1.fbdic.fbdic_mcu_syndrome[3];
1061wire mcu1_synd_AA = `MCU1.fbdic.fbdic_mcu_syndrome[2];
1062wire mcu1_synd_AF = `MCU1.fbdic.fbdic_mcu_syndrome[1];
1063wire mcu1_synd_C = `MCU1.fbdic.fbdic_mcu_syndrome[0];
1064
1065wire mcu2_synd_SPE = `MCU2.fbdic.fbdic_mcu_syndrome[3];
1066wire mcu2_synd_AA = `MCU2.fbdic.fbdic_mcu_syndrome[2];
1067wire mcu2_synd_AF = `MCU2.fbdic.fbdic_mcu_syndrome[1];
1068wire mcu2_synd_C = `MCU2.fbdic.fbdic_mcu_syndrome[0];
1069
1070wire mcu3_synd_SPE = `MCU3.fbdic.fbdic_mcu_syndrome[3];
1071wire mcu3_synd_AA = `MCU3.fbdic.fbdic_mcu_syndrome[2];
1072wire mcu3_synd_AF = `MCU3.fbdic.fbdic_mcu_syndrome[1];
1073wire mcu3_synd_C = `MCU3.fbdic.fbdic_mcu_syndrome[0];
1074
1075// --- FBR ---
1076
1077wire mcu0_syndrome_SPE = `MCU0.fbdic.fbdic_mcu_syndrome_in[3] & `MCU0.fbdic.fbdic_mcu_syndrome_en;
1078wire mcu0_syndrome_AA = `MCU0.fbdic.fbdic_mcu_syndrome_in[2] & `MCU0.fbdic.fbdic_mcu_syndrome_en;
1079wire mcu0_syndrome_AF = `MCU0.fbdic.fbdic_mcu_syndrome_in[1] & `MCU0.fbdic.fbdic_mcu_syndrome_en;
1080wire mcu0_syndrome_C = `MCU0.fbdic.fbdic_mcu_syndrome_in[0] & `MCU0.fbdic.fbdic_mcu_syndrome_en;
1081
1082wire mcu1_syndrome_SPE = `MCU1.fbdic.fbdic_mcu_syndrome_in[3] & `MCU1.fbdic.fbdic_mcu_syndrome_en;
1083wire mcu1_syndrome_AA = `MCU1.fbdic.fbdic_mcu_syndrome_in[2] & `MCU1.fbdic.fbdic_mcu_syndrome_en;
1084wire mcu1_syndrome_AF = `MCU1.fbdic.fbdic_mcu_syndrome_in[1] & `MCU1.fbdic.fbdic_mcu_syndrome_en;
1085wire mcu1_syndrome_C = `MCU1.fbdic.fbdic_mcu_syndrome_in[0] & `MCU1.fbdic.fbdic_mcu_syndrome_en;
1086
1087wire mcu2_syndrome_SPE = `MCU2.fbdic.fbdic_mcu_syndrome_in[3] & `MCU2.fbdic.fbdic_mcu_syndrome_en;
1088wire mcu2_syndrome_AA = `MCU2.fbdic.fbdic_mcu_syndrome_in[2] & `MCU2.fbdic.fbdic_mcu_syndrome_en;
1089wire mcu2_syndrome_AF = `MCU2.fbdic.fbdic_mcu_syndrome_in[1] & `MCU2.fbdic.fbdic_mcu_syndrome_en;
1090wire mcu2_syndrome_C = `MCU2.fbdic.fbdic_mcu_syndrome_in[0] & `MCU2.fbdic.fbdic_mcu_syndrome_en;
1091
1092wire mcu3_syndrome_SPE = `MCU3.fbdic.fbdic_mcu_syndrome_in[3] & `MCU3.fbdic.fbdic_mcu_syndrome_en;
1093wire mcu3_syndrome_AA = `MCU3.fbdic.fbdic_mcu_syndrome_in[2] & `MCU3.fbdic.fbdic_mcu_syndrome_en;
1094wire mcu3_syndrome_AF = `MCU3.fbdic.fbdic_mcu_syndrome_in[1] & `MCU3.fbdic.fbdic_mcu_syndrome_en;
1095wire mcu3_syndrome_C = `MCU3.fbdic.fbdic_mcu_syndrome_in[0] & `MCU3.fbdic.fbdic_mcu_syndrome_en;
1096
1097wire mcu0_l2t0_scb_secc_err = `MCU0.mcu_l2t0_scb_secc_err;
1098wire mcu0_l2t0_scb_mecc_err = `MCU0.mcu_l2t0_scb_mecc_err;
1099wire mcu0_l2t0_mecc_err_r3 = `MCU0.mcu_l2t0_mecc_err_r3;
1100
1101wire mcu1_l2t0_scb_secc_err = `MCU1.mcu_l2t0_scb_secc_err;
1102wire mcu1_l2t0_scb_mecc_err = `MCU1.mcu_l2t0_scb_mecc_err;
1103wire mcu1_l2t0_mecc_err_r3 = `MCU1.mcu_l2t0_mecc_err_r3;
1104
1105wire mcu2_l2t0_scb_secc_err = `MCU2.mcu_l2t0_scb_secc_err;
1106wire mcu2_l2t0_scb_mecc_err = `MCU2.mcu_l2t0_scb_mecc_err;
1107wire mcu2_l2t0_mecc_err_r3 = `MCU2.mcu_l2t0_mecc_err_r3;
1108
1109wire mcu3_l2t0_scb_secc_err = `MCU3.mcu_l2t0_scb_secc_err;
1110wire mcu3_l2t0_scb_mecc_err = `MCU3.mcu_l2t0_scb_mecc_err;
1111wire mcu3_l2t0_mecc_err_r3 = `MCU3.mcu_l2t0_mecc_err_r3;
1112
1113wire mcu0_l2t1_scb_secc_err = `MCU0.mcu_l2t1_scb_secc_err;
1114wire mcu0_l2t1_scb_mecc_err = `MCU0.mcu_l2t1_scb_mecc_err;
1115wire mcu0_l2t1_mecc_err_r3 = `MCU0.mcu_l2t1_mecc_err_r3;
1116
1117wire mcu1_l2t1_scb_secc_err = `MCU1.mcu_l2t1_scb_secc_err;
1118wire mcu1_l2t1_scb_mecc_err = `MCU1.mcu_l2t1_scb_mecc_err;
1119wire mcu1_l2t1_mecc_err_r3 = `MCU1.mcu_l2t1_mecc_err_r3;
1120
1121wire mcu2_l2t1_scb_secc_err = `MCU2.mcu_l2t1_scb_secc_err;
1122wire mcu2_l2t1_scb_mecc_err = `MCU2.mcu_l2t1_scb_mecc_err;
1123wire mcu2_l2t1_mecc_err_r3 = `MCU2.mcu_l2t1_mecc_err_r3;
1124
1125wire mcu3_l2t1_scb_secc_err = `MCU3.mcu_l2t1_scb_secc_err;
1126wire mcu3_l2t1_scb_mecc_err = `MCU3.mcu_l2t1_scb_mecc_err;
1127wire mcu3_l2t1_mecc_err_r3 = `MCU3.mcu_l2t1_mecc_err_r3;
1128
1129// --- fbd errors during training
1130
1131wire mcu0_fbdic_chnl_reset_error = ~(`MCU0.fbdic.fbdic_chnl_reset_error_mode);
1132wire mcu1_fbdic_chnl_reset_error = ~(`MCU1.fbdic.fbdic_chnl_reset_error_mode);
1133wire mcu2_fbdic_chnl_reset_error = ~(`MCU2.fbdic.fbdic_chnl_reset_error_mode);
1134wire mcu3_fbdic_chnl_reset_error = ~(`MCU3.fbdic.fbdic_chnl_reset_error_mode);
1135
1136// --- refresh count
1137
1138wire mcu0_refresh_req = `MCU0.drif.drif_refresh_req_picked;
1139wire mcu1_refresh_req = `MCU1.drif.drif_refresh_req_picked;
1140wire mcu2_refresh_req = `MCU2.drif.drif_refresh_req_picked;
1141wire mcu3_refresh_req = `MCU3.drif.drif_refresh_req_picked;
1142
1143wire mcu0_refresh_go = `MCU0.drif.drif_ref_go;
1144wire mcu1_refresh_go = `MCU1.drif.drif_ref_go;
1145wire mcu2_refresh_go = `MCU2.drif.drif_ref_go;
1146wire mcu3_refresh_go = `MCU3.drif.drif_ref_go;
1147
1148wire mcu0_self_refresh = `MCU0.drif.drif_enter_self_refresh;
1149wire mcu1_self_refresh = `MCU1.drif.drif_enter_self_refresh;
1150wire mcu2_self_refresh = `MCU2.drif.drif_enter_self_refresh;
1151wire mcu3_self_refresh = `MCU3.drif.drif_enter_self_refresh;
1152
1153integer mcu0_refresh_counter;
1154integer mcu1_refresh_counter;
1155integer mcu2_refresh_counter;
1156integer mcu3_refresh_counter;
1157
1158integer mcu0_enter_refresh;
1159integer mcu1_enter_refresh;
1160integer mcu2_enter_refresh;
1161integer mcu3_enter_refresh;
1162
1163integer fbdimm0_refresh_counter;
1164integer fbdimm1_refresh_counter;
1165integer fbdimm2_refresh_counter;
1166integer fbdimm3_refresh_counter;
1167integer fbdimm4_refresh_counter;
1168integer fbdimm5_refresh_counter;
1169integer fbdimm6_refresh_counter;
1170integer fbdimm7_refresh_counter;
1171
1172reg enable_refresh_check;
1173reg enable_alert_crc_check;
1174reg enable_alert_crc_retry_wr_q_not_empty;
1175
1176`ifndef AXIS
1177 `ifdef X8
1178 //wire [14:0] fbdimm0_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx8.U00.refr_cnt;
1179 //wire [14:0] fbdimm2_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.fbdimm_DIMMx8.U00.refr_cnt;
1180 //wire [14:0] fbdimm4_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.fbdimm_DIMMx8.U00.refr_cnt;
1181 //wire [14:0] fbdimm6_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.fbdimm_DIMMx8.U00.refr_cnt;
1182 `else
1183 //wire [14:0] fbdimm0_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.refr_cnt;
1184 //wire [14:0] fbdimm2_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.fbdimm_DIMMx4.U00.refr_cnt;
1185 //wire [14:0] fbdimm4_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.fbdimm_DIMMx4.U00.refr_cnt;
1186 //wire [14:0] fbdimm6_refresh_cnt_sample = tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.fbdimm_DIMMx4.U00.refr_cnt;
1187 `endif
1188`endif
1189
1190// refresh define end
1191
1192//---------------------------------------------------------------
1193// CHECKERS
1194//---------------------------------------------------------------
1195
1196//-------------------
1197// mcu - check for 120049
1198//-------------------
1199
1200reg mcu0_l0state_cond1;
1201reg mcu0_l0state_cond2;
1202reg mcu1_l0state_cond1;
1203reg mcu1_l0state_cond2;
1204reg mcu2_l0state_cond1;
1205reg mcu2_l0state_cond2;
1206reg mcu3_l0state_cond1;
1207reg mcu3_l0state_cond2;
1208reg enable_mon_120049;
1209reg pipe_mcu0_fast_reset_err_on_first_sync;
1210reg pipe_mcu1_fast_reset_err_on_first_sync;
1211reg pipe_mcu2_fast_reset_err_on_first_sync;
1212reg pipe_mcu3_fast_reset_err_on_first_sync;
1213reg pipe_mcu0_fbdic_fbdic_error_mode;
1214reg pipe_mcu1_fbdic_fbdic_error_mode;
1215reg pipe_mcu2_fbdic_fbdic_error_mode;
1216reg pipe_mcu3_fbdic_fbdic_error_mode;
1217reg pipe_mcu0_drif_woq_wr_error_mode;
1218reg pipe_mcu1_drif_woq_wr_error_mode;
1219reg pipe_mcu2_drif_woq_wr_error_mode;
1220reg pipe_mcu3_drif_woq_wr_error_mode;
1221
1222initial
1223begin
1224 mcu0_l0state_cond1 = 1'b0;
1225 mcu0_l0state_cond2 = 1'b0;
1226 mcu1_l0state_cond1 = 1'b0;
1227 mcu1_l0state_cond2 = 1'b0;
1228 mcu2_l0state_cond1 = 1'b0;
1229 mcu2_l0state_cond2 = 1'b0;
1230 mcu3_l0state_cond1 = 1'b0;
1231 mcu3_l0state_cond2 = 1'b0;
1232 pipe_mcu0_fast_reset_err_on_first_sync = 1'b0;
1233 pipe_mcu1_fast_reset_err_on_first_sync = 1'b0;
1234 pipe_mcu2_fast_reset_err_on_first_sync = 1'b0;
1235 pipe_mcu3_fast_reset_err_on_first_sync = 1'b0;
1236 pipe_mcu0_fbdic_fbdic_error_mode = 1'b0;
1237 pipe_mcu1_fbdic_fbdic_error_mode = 1'b0;
1238 pipe_mcu2_fbdic_fbdic_error_mode = 1'b0;
1239 pipe_mcu3_fbdic_fbdic_error_mode = 1'b0;
1240 pipe_mcu0_drif_woq_wr_error_mode = 1'b0;
1241 pipe_mcu1_drif_woq_wr_error_mode = 1'b0;
1242 pipe_mcu2_drif_woq_wr_error_mode = 1'b0;
1243 pipe_mcu3_drif_woq_wr_error_mode = 1'b0;
1244 if ($test$plusargs("disable_mon_120049"))
1245 enable_mon_120049 = 0;
1246 else
1247 enable_mon_120049 = 1;
1248end
1249
1250// MCU0
1251always @ (posedge `MCU0.fbdic.l1clk && enable_mon_120049)
1252 begin
1253 pipe_mcu0_fast_reset_err_on_first_sync <= `MCU0.fbdic.fast_reset_err_on_first_sync;
1254 pipe_mcu0_fbdic_fbdic_error_mode <= `MCU0.fbdic.fbdic_error_mode;
1255 pipe_mcu0_drif_woq_wr_error_mode <= `MCU0.drif.woq_wr_error_mode;
1256 end
1257
1258always @ (posedge `MCU0.fbdic.l1clk && enable_mon_120049)
1259 if (((`MCU0.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU0.fbdic.fbdic_idle_frame == 1'b1)))
1260 mcu0_l0state_cond1 <= 1'b0;
1261 else
1262 mcu0_l0state_cond1 <= mcu0_l0state_cond1 | `MCU0.fbdic.fbdic_l0_state;
1263
1264always @ (posedge `MCU0.fbdic.l1clk && enable_mon_120049)
1265 if (((`MCU0.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU0.fbdic.fbdic_idle_frame == 1'b1)))
1266 mcu0_l0state_cond2 <= 1'b0;
1267 else
1268 mcu0_l0state_cond2 <= mcu0_l0state_cond2 | (`MCU0.drif.drif_dram_cmd_b[2:0] == 3'h5);
1269
1270wire mcu0_trigger = pipe_mcu0_fast_reset_err_on_first_sync & mcu0_l0state_cond1 & mcu0_l0state_cond2 & enable_mon_120049 & ~pipe_mcu0_fbdic_fbdic_error_mode & ~pipe_mcu0_drif_woq_wr_error_mode;
1271
1272always @ (posedge (mcu0_trigger === 1'b1))
1273 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: *** N2 TO 2.0 BUG 120049 ***");
1274
1275// MCU1
1276always @ (posedge `MCU1.fbdic.l1clk && enable_mon_120049)
1277 begin
1278 pipe_mcu1_fast_reset_err_on_first_sync <= `MCU1.fbdic.fast_reset_err_on_first_sync;
1279 pipe_mcu1_fbdic_fbdic_error_mode <= `MCU1.fbdic.fbdic_error_mode;
1280 pipe_mcu1_drif_woq_wr_error_mode <= `MCU1.drif.woq_wr_error_mode;
1281 end
1282
1283always @ (posedge `MCU1.fbdic.l1clk && enable_mon_120049)
1284 if (((`MCU1.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU1.fbdic.fbdic_idle_frame == 1'b1)))
1285 mcu1_l0state_cond1 <= 1'b0;
1286 else
1287 mcu1_l0state_cond1 <= mcu1_l0state_cond1 | `MCU1.fbdic.fbdic_l0_state;
1288
1289always @ (posedge `MCU1.fbdic.l1clk && enable_mon_120049)
1290 if (((`MCU1.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU1.fbdic.fbdic_idle_frame == 1'b1)))
1291 mcu1_l0state_cond2 <= 1'b0;
1292 else
1293 mcu1_l0state_cond2 <= mcu1_l0state_cond2 | (`MCU1.drif.drif_dram_cmd_b[2:0] == 3'h5);
1294
1295wire mcu1_trigger = pipe_mcu1_fast_reset_err_on_first_sync & mcu1_l0state_cond1 & mcu1_l0state_cond2 & enable_mon_120049 & ~pipe_mcu1_fbdic_fbdic_error_mode & ~pipe_mcu1_drif_woq_wr_error_mode;
1296
1297always @ (posedge (mcu1_trigger === 1'b1))
1298 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: *** N2 TO 2.0 BUG 120049 ***");
1299
1300// MCU2
1301always @ (posedge `MCU2.fbdic.l1clk && enable_mon_120049)
1302 begin
1303 pipe_mcu2_fast_reset_err_on_first_sync <= `MCU2.fbdic.fast_reset_err_on_first_sync;
1304 pipe_mcu2_fbdic_fbdic_error_mode <= `MCU2.fbdic.fbdic_error_mode;
1305 pipe_mcu2_drif_woq_wr_error_mode <= `MCU2.drif.woq_wr_error_mode;
1306 end
1307
1308always @ (posedge `MCU2.fbdic.l1clk && enable_mon_120049)
1309 if (((`MCU2.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU2.fbdic.fbdic_idle_frame == 1'b1)))
1310 mcu2_l0state_cond1 <= 1'b0;
1311 else
1312 mcu2_l0state_cond1 <= mcu2_l0state_cond1 | `MCU2.fbdic.fbdic_l0_state;
1313
1314always @ (posedge `MCU2.fbdic.l1clk && enable_mon_120049)
1315 if (((`MCU2.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU2.fbdic.fbdic_idle_frame == 1'b1)))
1316 mcu2_l0state_cond2 <= 1'b0;
1317 else
1318 mcu2_l0state_cond2 <= mcu2_l0state_cond2 | (`MCU2.drif.drif_dram_cmd_b[2:0] == 3'h5);
1319
1320wire mcu2_trigger = pipe_mcu2_fast_reset_err_on_first_sync & mcu2_l0state_cond1 & mcu2_l0state_cond2 & enable_mon_120049 & ~pipe_mcu2_fbdic_fbdic_error_mode & ~pipe_mcu2_drif_woq_wr_error_mode;
1321
1322always @ (posedge (mcu2_trigger === 1'b1))
1323 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: *** N2 TO 2.0 BUG 120049 ***");
1324
1325// MCU3
1326always @ (posedge `MCU3.fbdic.l1clk && enable_mon_120049)
1327 begin
1328 pipe_mcu3_fast_reset_err_on_first_sync <= `MCU3.fbdic.fast_reset_err_on_first_sync;
1329 pipe_mcu3_fbdic_fbdic_error_mode <= `MCU3.fbdic.fbdic_error_mode;
1330 pipe_mcu3_drif_woq_wr_error_mode <= `MCU3.drif.woq_wr_error_mode;
1331 end
1332always @ (posedge `MCU3.fbdic.l1clk && enable_mon_120049)
1333 if (((`MCU3.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU3.fbdic.fbdic_idle_frame == 1'b1)))
1334 mcu3_l0state_cond1 <= 1'b0;
1335 else
1336 mcu3_l0state_cond1 <= mcu3_l0state_cond1 | `MCU3.fbdic.fbdic_l0_state;
1337
1338always @ (posedge `MCU3.fbdic.l1clk && enable_mon_120049)
1339 if (((`MCU3.fbdic.fbdic_fbd_state[2:0] == 3'b0) | (`MCU3.fbdic.fbdic_idle_frame == 1'b1)))
1340 mcu3_l0state_cond2 <= 1'b0;
1341 else
1342 mcu3_l0state_cond2 <= mcu3_l0state_cond2 | (`MCU3.drif.drif_dram_cmd_b[2:0] == 3'h5);
1343
1344wire mcu3_trigger = pipe_mcu3_fast_reset_err_on_first_sync & mcu3_l0state_cond1 & mcu3_l0state_cond2 & enable_mon_120049 & ~pipe_mcu3_fbdic_fbdic_error_mode & ~pipe_mcu3_drif_woq_wr_error_mode;
1345
1346always @ (posedge (mcu3_trigger === 1'b1))
1347 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: *** N2 TO 2.0 BUG 120049 ***");
1348
1349//-------------------
1350// mcu - check for crc retry before wr error queue empty
1351//-------------------
1352
1353initial
1354 if ($test$plusargs("disable_alert_crc_retry_b4_wr_err_q_empty"))
1355 enable_alert_crc_retry_wr_q_not_empty = 0;
1356 else
1357 enable_alert_crc_retry_wr_q_not_empty = 1;
1358
1359
1360always @ (posedge `MCU0.drif.l1clk && enable_alert_crc_retry_wr_q_not_empty === 1'b1)
1361 if (mcu0_crc_retry_wr_q_not_empty === 1'b1)
1362 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: CRC RETRY WHILE WR ERR Q NOT EMPTY *** N2 TO 2.0 BUG 120114 ***");
1363
1364always @ (posedge `MCU1.drif.l1clk && enable_alert_crc_retry_wr_q_not_empty === 1'b1)
1365 if (mcu1_crc_retry_wr_q_not_empty === 1'b1)
1366 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: CRC RETRY WHILE WR ERR Q NOT EMPTY *** N2 TO 2.0 BUG 120114 ***");
1367
1368always @ (posedge `MCU2.drif.l1clk && enable_alert_crc_retry_wr_q_not_empty === 1'b1)
1369 if (mcu2_crc_retry_wr_q_not_empty === 1'b1)
1370 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: CRC RETRY WHILE WR ERR Q NOT EMPTY *** N2 TO 2.0 BUG 120114 ***");
1371
1372always @ (posedge `MCU3.drif.l1clk && enable_alert_crc_retry_wr_q_not_empty === 1'b1)
1373 if (mcu3_crc_retry_wr_q_not_empty === 1'b1)
1374 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: CRC RETRY WHILE WR ERR Q NOT EMPTY *** N2 TO 2.0 BUG 120114 ***");
1375
1376//-------------------
1377// mcu - check for collision : alertFrame and CRC error
1378//-------------------
1379
1380initial
1381 if ($test$plusargs("disable_alert_crc_checker"))
1382 enable_alert_crc_check = 0;
1383 else
1384 enable_alert_crc_check = 1;
1385
1386
1387always @ (posedge `MCU0.drif.l1clk && enable_alert_crc_check)
1388 if (mcu0_alertframe_crc_error === 1'b1)
1389 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: COLLISION : ALERT_FRAME and CRC RETRY *** N2 TO 2.0 BUG 118987 ***");
1390
1391always @ (posedge `MCU1.drif.l1clk && enable_alert_crc_check)
1392 if (mcu1_alertframe_crc_error === 1'b1)
1393 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: COLLISION : ALERT_FRAME and CRC RETRY *** N2 TO 2.0 BUG 118987 ***");
1394
1395always @ (posedge `MCU2.drif.l1clk && enable_alert_crc_check)
1396 if (mcu2_alertframe_crc_error === 1'b1)
1397 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: COLLISION : ALERT_FRAME and CRC RETRY *** N2 TO 2.0 BUG 118987 ***");
1398
1399always @ (posedge `MCU3.drif.l1clk && enable_alert_crc_check)
1400 if (mcu3_alertframe_crc_error === 1'b1)
1401 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: COLLISION : ALERT_FRAME and CRC RETRY *** N2 TO 2.0 BUG 118987 ***");
1402
1403//-------------------
1404// mcu - dimm refresh check
1405//-------------------
1406
1407initial
1408begin
1409mcu0_refresh_counter = 0;
1410mcu1_refresh_counter = 0;
1411mcu2_refresh_counter = 0;
1412mcu3_refresh_counter = 0;
1413
1414mcu0_enter_refresh = 0;
1415mcu1_enter_refresh = 0;
1416mcu2_enter_refresh = 0;
1417mcu3_enter_refresh = 0;
1418
1419fbdimm0_refresh_counter = 0;
1420fbdimm1_refresh_counter = 0;
1421fbdimm2_refresh_counter = 0;
1422fbdimm3_refresh_counter = 0;
1423fbdimm4_refresh_counter = 0;
1424fbdimm5_refresh_counter = 0;
1425fbdimm6_refresh_counter = 0;
1426fbdimm7_refresh_counter = 0;
1427
1428if ($test$plusargs("disable_refresh_checker"))
1429 enable_refresh_check = 0;
1430else
1431 enable_refresh_check = 1;
1432
1433end
1434
1435`ifndef AXIS
1436always @ (posedge fbdic_l0_state_0)
1437begin
1438 mcu0_refresh_counter = 0;
1439 fbdimm0_refresh_counter = 1;
1440end
1441
1442always @ (posedge fbdic_l0_state_1)
1443begin
1444 mcu1_refresh_counter = 0;
1445 fbdimm2_refresh_counter = 1;
1446end
1447
1448// --- MCU0 refresh count check
1449always @ (posedge mcu0_self_refresh)
1450 mcu0_refresh_counter = mcu0_refresh_counter + 1;
1451
1452always @ (posedge mcu0_refresh_go && (mcu0_enter_refresh == 0))
1453begin
1454 mcu0_enter_refresh = 1;
1455 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: MCU0 enter refresh state %d",mcu0_enter_refresh);
1456end
1457
1458always @ (posedge mcu0_refresh_req)
1459 if (mcu0_enter_refresh && (mcu0_drif_dram_rank_b === 1'b1) || (mcu0_drif_dram_dimm_b !== 3'b0))
1460 begin
1461 mcu0_enter_refresh = 0;
1462 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: MCU0 refresh other dimms, out of refresh state %d",mcu0_enter_refresh);
1463 end
1464
1465always @ (posedge drl2clk && enable_refresh_check)
1466begin
1467 if (mcu0_refresh_req && (mcu0_enter_refresh != 0)
1468 && (mcu0_drif_dram_rank_b !== 1'b1) && (mcu0_drif_dram_dimm_b === 3'b0))
1469 begin
1470// if (mcu0_enter_refresh >= `MCU0.drif.drif_dimms_present)
1471// begin
1472 mcu0_refresh_counter = mcu0_refresh_counter + 1;
1473 mcu0_enter_refresh = 0;
1474
1475 repeat(10) @ (posedge drl2clk);
1476
1477 // if (mcu0_refresh_counter > fbdimm0_refresh_counter)
1478 // `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu0 refresh lost mcu cnt = %d dimm cnt = %d", mcu0_refresh_counter, fbdimm0_refresh_counter);
1479// else
1480 // `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: MCU0 refresh complete mcu_cnt=%d dimm_cnt=%d",mcu0_refresh_counter, fbdimm0_refresh_counter);
1481// end
1482// else
1483// mcu0_enter_refresh = mcu0_enter_refresh + 1;
1484 end
1485end
1486
1487/*always @ (fbdimm0_refresh_cnt_sample)
1488begin
1489 if (enable_refresh_check)
1490 begin
1491 fbdimm0_refresh_counter = fbdimm0_refresh_counter + 1;
1492 if (mcu0_refresh_counter > fbdimm0_refresh_counter)
1493 `PR_ERROR("mcu_fmon", `ERROR, "FBDIMM0: MCU0 refresh lost mcu_cnt=%d dimm_cnt=%d", mcu0_refresh_counter, fbdimm0_refresh_counter);
1494 else
1495 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: FBDIMM0 refresh mcu_cnt=%d dimm_cnt=%d",mcu0_refresh_counter, fbdimm0_refresh_counter);
1496 end
1497end
1498*/
1499// --- MCU0 refresh count check end
1500
1501// --- MCU1 refresh count check
1502
1503// --- MCU1 refresh count check end
1504
1505`endif
1506
1507//-------------------
1508
1509// L0s State Checker
1510//-------------------
1511
1512always @ (negedge (fbdic_l0s_stall_0 && enabled))
1513begin
1514 if (fbdic_l0s_enable_0) begin
1515 if (fbdic_sync_frame_req_0 !== 1)
1516 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: The first frame after L0s duration is not a sync frame");
1517 end
1518end
1519
1520always @ (negedge (fbdic_l0s_stall_1 && enabled))
1521begin
1522 if (fbdic_l0s_enable_1) begin
1523 if (fbdic_sync_frame_req_1 !== 1)
1524 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: The first frame after L0s duration is not a sync frame");
1525 end
1526end
1527
1528always @ (negedge (fbdic_l0s_stall_2 && enabled))
1529begin
1530 if (fbdic_l0s_enable_2) begin
1531 if (fbdic_sync_frame_req_2 !== 1)
1532 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: The first frame after L0s duration is not a sync frame");
1533 end
1534end
1535
1536always @ (negedge (fbdic_l0s_stall_3 && enabled))
1537begin
1538 if (fbdic_l0s_enable_3) begin
1539 if (fbdic_sync_frame_req_3 !== 1)
1540 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: The first frame after L0s duration is not a sync frame");
1541 end
1542end
1543
1544//--------------------------
1545// Power Down Mode Checkers
1546//--------------------------
1547always @ (posedge drl2clk && enabled)
1548begin
1549 pdmc_pd_cnt_is_zero_0_d <= pdmc_pd_cnt_is_zero_0;
1550end
1551
1552//***pdmc0***
1553always @ (posedge drl2clk && enabled)
1554begin
1555 if (mcu0_drif_pdx_issued[0] || pdmc_state_00[0])
1556 mcu0_start_pd_check_0 = 0;
1557 else if (mcu0_drif_pde_issued[0]) begin
1558 mcu0_start_pd_check_0 = 1;
1559 if ((mcu0_start_pd_check_0 == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[0] !== 1'b1))
1560 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1561 end
1562end
1563
1564always @ (posedge drl2clk && enabled)
1565begin
1566 if (mcu0_start_pd_check_0) begin
1567 if ((mcu0_drif_dram_dimm_a == 3'd0) && (mcu0_drif_dram_rank_a == 1'b0) &&
1568 ((mcu0_drif_dram_cmd_a == `RD) ||
1569 (mcu0_drif_dram_cmd_a == `WR) ||
1570 (mcu0_drif_dram_cmd_a == `ACT)))
1571 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1572 if ((mcu0_drif_dram_dimm_b == 3'd0) && (mcu0_drif_dram_rank_b == 1'b0) &&
1573 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1574 (mcu0_drif_dram_cmd_b == `WR) ||
1575 (mcu0_drif_dram_cmd_b == `ACT)))
1576 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1577 if ((mcu0_drif_dram_dimm_c == 3'd0) && (mcu0_drif_dram_rank_c == 1'b0) &&
1578 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1579 (mcu0_drif_dram_cmd_c == `WR) ||
1580 (mcu0_drif_dram_cmd_c == `ACT)))
1581 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1582 end
1583end
1584
1585//***pdmc8***
1586always @ (posedge drl2clk && enabled)
1587begin
1588 if (mcu0_drif_pdx_issued[8] || pdmc_state_08[0])
1589 mcu0_start_pd_check_8 = 0;
1590 else if (mcu0_drif_pde_issued[8]) begin
1591 mcu0_start_pd_check_8 = 1;
1592 if ((mcu0_start_pd_check_8 == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[8] !== 1'b1))
1593 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1594 end
1595end
1596
1597always @ (posedge drl2clk && enabled)
1598begin
1599 if (mcu0_start_pd_check_8) begin
1600 if ((mcu0_drif_dram_dimm_a == 3'd0) && (mcu0_drif_dram_rank_a == 1'b1) &&
1601 ((mcu0_drif_dram_cmd_a == `RD) ||
1602 (mcu0_drif_dram_cmd_a == `WR) ||
1603 (mcu0_drif_dram_cmd_a == `ACT)))
1604 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1605 if ((mcu0_drif_dram_dimm_b == 3'd0) && (mcu0_drif_dram_rank_b == 1'b1) &&
1606 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1607 (mcu0_drif_dram_cmd_b == `WR) ||
1608 (mcu0_drif_dram_cmd_b == `ACT)))
1609 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1610 if ((mcu0_drif_dram_dimm_c == 3'd0) && (mcu0_drif_dram_rank_c == 1'b1) &&
1611 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1612 (mcu0_drif_dram_cmd_c == `WR) ||
1613 (mcu0_drif_dram_cmd_c == `ACT)))
1614 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1615 end
1616end
1617
1618//***pdmc1***
1619always @ (posedge drl2clk && enabled)
1620begin
1621 if (mcu0_drif_pdx_issued[1] || pdmc_state_01[0])
1622 mcu0_start_pd_check_1 = 0;
1623 else if (mcu0_drif_pde_issued[1]) begin
1624 mcu0_start_pd_check_1 = 1;
1625 if ((mcu0_start_pd_check_1 == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[1] !== 1'b1))
1626 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1627 end
1628end
1629
1630always @ (posedge drl2clk && enabled)
1631begin
1632 if (mcu0_start_pd_check_1) begin
1633 if ((mcu0_drif_dram_dimm_a == 3'd1) && (mcu0_drif_dram_rank_a == 1'b0) &&
1634 ((mcu0_drif_dram_cmd_a == `RD) ||
1635 (mcu0_drif_dram_cmd_a == `WR) ||
1636 (mcu0_drif_dram_cmd_a == `ACT)))
1637 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1638 if ((mcu0_drif_dram_dimm_b == 3'd1) && (mcu0_drif_dram_rank_b == 1'b0) &&
1639 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1640 (mcu0_drif_dram_cmd_b == `WR) ||
1641 (mcu0_drif_dram_cmd_b == `ACT)))
1642 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1643 if ((mcu0_drif_dram_dimm_c == 3'd1) && (mcu0_drif_dram_rank_c == 1'b0) &&
1644 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1645 (mcu0_drif_dram_cmd_c == `WR) ||
1646 (mcu0_drif_dram_cmd_c == `ACT)))
1647 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1648 end
1649end
1650
1651//***pdmc9***
1652always @ (posedge drl2clk && enabled)
1653begin
1654 if (mcu0_drif_pdx_issued[9] || pdmc_state_09[0])
1655 mcu0_start_pd_check_9 = 0;
1656 else if (mcu0_drif_pde_issued[9]) begin
1657 mcu0_start_pd_check_9 = 1;
1658 if ((mcu0_start_pd_check_9 == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[9] !== 1'b1))
1659 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1660 end
1661end
1662
1663always @ (posedge drl2clk && enabled)
1664begin
1665 if (mcu0_start_pd_check_9) begin
1666 if ((mcu0_drif_dram_dimm_a == 3'd1) && (mcu0_drif_dram_rank_a == 1'b1) &&
1667 ((mcu0_drif_dram_cmd_a == `RD) ||
1668 (mcu0_drif_dram_cmd_a == `WR) ||
1669 (mcu0_drif_dram_cmd_a == `ACT)))
1670 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1671 if ((mcu0_drif_dram_dimm_b == 3'd1) && (mcu0_drif_dram_rank_b == 1'b1) &&
1672 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1673 (mcu0_drif_dram_cmd_b == `WR) ||
1674 (mcu0_drif_dram_cmd_b == `ACT)))
1675 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1676 if ((mcu0_drif_dram_dimm_c == 3'd1) && (mcu0_drif_dram_rank_c == 1'b1) &&
1677 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1678 (mcu0_drif_dram_cmd_c == `WR) ||
1679 (mcu0_drif_dram_cmd_c == `ACT)))
1680 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1681 end
1682end
1683
1684//***pdmc2***
1685always @ (posedge drl2clk && enabled)
1686begin
1687 if (mcu0_drif_pdx_issued[2] || pdmc_state_02[0])
1688 mcu0_start_pd_check_2 = 0;
1689 else if (mcu0_drif_pde_issued[2]) begin
1690 mcu0_start_pd_check_2 = 1;
1691 if ((mcu0_start_pd_check_2 == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[2] !== 1'b1))
1692 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1693 end
1694end
1695
1696always @ (posedge drl2clk && enabled)
1697begin
1698 if (mcu0_start_pd_check_2) begin
1699 if ((mcu0_drif_dram_dimm_a == 3'd2) && (mcu0_drif_dram_rank_a == 1'b0) &&
1700 ((mcu0_drif_dram_cmd_a == `RD) ||
1701 (mcu0_drif_dram_cmd_a == `WR) ||
1702 (mcu0_drif_dram_cmd_a == `ACT)))
1703 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1704 if ((mcu0_drif_dram_dimm_b == 3'd2) && (mcu0_drif_dram_rank_b == 1'b0) &&
1705 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1706 (mcu0_drif_dram_cmd_b == `WR) ||
1707 (mcu0_drif_dram_cmd_b == `ACT)))
1708 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1709 if ((mcu0_drif_dram_dimm_c == 3'd2) && (mcu0_drif_dram_rank_c == 1'b0) &&
1710 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1711 (mcu0_drif_dram_cmd_c == `WR) ||
1712 (mcu0_drif_dram_cmd_c == `ACT)))
1713 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1714 end
1715end
1716
1717//***pdmc10***
1718always @ (posedge drl2clk && enabled)
1719begin
1720 if (mcu0_drif_pdx_issued[10] || pdmc_state_0a[0])
1721 mcu0_start_pd_check_a = 0;
1722 else if (mcu0_drif_pde_issued[10]) begin
1723 mcu0_start_pd_check_a = 1;
1724 if ((mcu0_start_pd_check_a == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[10] !== 1'b1))
1725 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1726 end
1727end
1728
1729always @ (posedge drl2clk && enabled)
1730begin
1731 if (mcu0_start_pd_check_a) begin
1732 if ((mcu0_drif_dram_dimm_a == 3'd2) && (mcu0_drif_dram_rank_a == 1'b1) &&
1733 ((mcu0_drif_dram_cmd_a == `RD) ||
1734 (mcu0_drif_dram_cmd_a == `WR) ||
1735 (mcu0_drif_dram_cmd_a == `ACT)))
1736 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1737 if ((mcu0_drif_dram_dimm_b == 3'd2) && (mcu0_drif_dram_rank_b == 1'b1) &&
1738 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1739 (mcu0_drif_dram_cmd_b == `WR) ||
1740 (mcu0_drif_dram_cmd_b == `ACT)))
1741 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1742 if ((mcu0_drif_dram_dimm_c == 3'd2) && (mcu0_drif_dram_rank_c == 1'b1) &&
1743 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1744 (mcu0_drif_dram_cmd_c == `WR) ||
1745 (mcu0_drif_dram_cmd_c == `ACT)))
1746 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1747 end
1748end
1749
1750//***pdmc3***
1751always @ (posedge drl2clk && enabled)
1752begin
1753 if (mcu0_drif_pdx_issued[3] || pdmc_state_03[0])
1754 mcu0_start_pd_check_3 = 0;
1755 else if (mcu0_drif_pde_issued[3]) begin
1756 mcu0_start_pd_check_3 = 1;
1757 if ((mcu0_start_pd_check_3 == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[3] !== 1'b1))
1758 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1759 end
1760end
1761
1762always @ (posedge drl2clk && enabled)
1763begin
1764 if (mcu0_start_pd_check_3) begin
1765 if ((mcu0_drif_dram_dimm_a == 3'd3) && (mcu0_drif_dram_rank_a == 1'b0) &&
1766 ((mcu0_drif_dram_cmd_a == `RD) ||
1767 (mcu0_drif_dram_cmd_a == `WR) ||
1768 (mcu0_drif_dram_cmd_a == `ACT)))
1769 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1770 if ((mcu0_drif_dram_dimm_b == 3'd3) && (mcu0_drif_dram_rank_b == 1'b0) &&
1771 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1772 (mcu0_drif_dram_cmd_b == `WR) ||
1773 (mcu0_drif_dram_cmd_b == `ACT)))
1774 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1775 if ((mcu0_drif_dram_dimm_c == 3'd3) && (mcu0_drif_dram_rank_c == 1'b0) &&
1776 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1777 (mcu0_drif_dram_cmd_c == `WR) ||
1778 (mcu0_drif_dram_cmd_c == `ACT)))
1779 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1780 end
1781end
1782
1783//***pdmc11***
1784always @ (posedge drl2clk && enabled)
1785begin
1786 if (mcu0_drif_pdx_issued[11] || pdmc_state_0b[0])
1787 mcu0_start_pd_check_b = 0;
1788 else if (mcu0_drif_pde_issued[11]) begin
1789 mcu0_start_pd_check_b = 1;
1790 if ((mcu0_start_pd_check_b == 1'b1) && (pdmc_pd_cnt_is_zero_0_d[11] !== 1'b1))
1791 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Power down is issued but cnt is not zero");
1792 end
1793end
1794
1795always @ (posedge drl2clk && enabled)
1796begin
1797 if (mcu0_start_pd_check_b) begin
1798 if ((mcu0_drif_dram_dimm_a == 3'd3) && (mcu0_drif_dram_rank_a == 1'b1) &&
1799 ((mcu0_drif_dram_cmd_a == `RD) ||
1800 (mcu0_drif_dram_cmd_a == `WR) ||
1801 (mcu0_drif_dram_cmd_a == `ACT)))
1802 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1803 if ((mcu0_drif_dram_dimm_b == 3'd3) && (mcu0_drif_dram_rank_b == 1'b1) &&
1804 (((mcu0_drif_dram_cmd_b == `CMD_OTHER) && (mcu0_drif_dram_addr_b[2:0] == `CMD_OTHER_REF)) ||
1805 (mcu0_drif_dram_cmd_b == `WR) ||
1806 (mcu0_drif_dram_cmd_b == `ACT)))
1807 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1808 if ((mcu0_drif_dram_dimm_c == 3'd3) && (mcu0_drif_dram_rank_c == 1'b1) &&
1809 (((mcu0_drif_dram_cmd_c == `CMD_OTHER) && (mcu0_drif_dram_addr_c[2:0] == `CMD_OTHER_SRE)) ||
1810 (mcu0_drif_dram_cmd_c == `WR) ||
1811 (mcu0_drif_dram_cmd_c == `ACT)))
1812 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Non power_down_exit command is sent while in power down");
1813 end
1814end
1815
1816
1817//`endif
1818
1819//---------------------
1820// Arbiter Checkers
1821//---------------------
1822
1823always @ (negedge (drl2clk && enabled))
1824begin
1825 if (|(drif_req_picked_0[9:0]))
1826 begin
1827 if ((drif_req_picked_0 != 10'h001) &&
1828 (drif_req_picked_0 != 10'h002) &&
1829 (drif_req_picked_0 != 10'h004) &&
1830 (drif_req_picked_0 != 10'h008) &&
1831 (drif_req_picked_0 != 10'h010) &&
1832 (drif_req_picked_0 != 10'h020) &&
1833 (drif_req_picked_0 != 10'h040) &&
1834 (drif_req_picked_0 != 10'h080) &&
1835 (drif_req_picked_0 != 10'h100) &&
1836 (drif_req_picked_0 != 10'h200))
1837 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: %h More than 1 request present", drif_req_picked_0);
1838 end
1839end
1840
1841//---------------------
1842// IBIST Checkers
1843//---------------------
1844always @ (ibist_rx_errstat_0)
1845if (enabled && (!mcu0_training_err_enable))
1846begin
1847 if (ibist_rx_errstat_0 == 2'b10)
1848 `PR_ERROR("mcu_fmon", `ERROR, "MCU0:IBIST transmission error %d",ibist_rx_errstat_0);
1849end
1850
1851always @ (ibist_rx_errstat_1)
1852if (enabled && (!mcu1_training_err_enable))
1853begin
1854 if (ibist_rx_errstat_1 == 2'b10)
1855 `PR_ERROR("mcu_fmon", `ERROR, "MCU1:IBIST transmission error %d",ibist_rx_errstat_1);
1856end
1857
1858always @ (ibist_rx_errstat_2)
1859if (enabled && (!mcu2_training_err_enable))
1860begin
1861 if (ibist_rx_errstat_2 == 2'b10)
1862 `PR_ERROR("mcu_fmon", `ERROR, "MCU2:IBIST transmission error %d",ibist_rx_errstat_2);
1863end
1864
1865always @ (ibist_rx_errstat_3)
1866if (enabled && (!mcu3_training_err_enable))
1867begin
1868 if (ibist_rx_errstat_3 == 2'b10)
1869 `PR_ERROR("mcu_fmon", `ERROR, "MCU3:IBIST transmission error %d",ibist_rx_errstat_3);
1870end
1871
1872//--------------------------
1873// WOQ (Wr Dq) Monitors
1874//--------------------------
1875
1876always @ (drif_woq_free_0)
1877if (enabled)
1878begin
1879 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Number of Writes dequeued from WOQ = %x", drif_woq_free_0);
1880end
1881
1882always @ (drif_woq_free_1)
1883if (enabled)
1884begin
1885 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Number of Writes dequeued from WOQ = %x", drif_woq_free_1);
1886end
1887
1888always @ (drif_woq_free_2)
1889if (enabled)
1890begin
1891 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Number of Writes dequeued from WOQ = %x", drif_woq_free_2);
1892end
1893
1894always @ (drif_woq_free_3)
1895if (enabled)
1896begin
1897 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Number of Writes dequeued from WOQ = %x", drif_woq_free_3);
1898end
1899
1900//-----------------------------
1901// FBDIC Checkers
1902//-----------------------------
1903
1904initial
1905begin
1906
1907// Training Seq Err Inj Init Signals
1908
1909 mcu0_training_err_enable = 1'b0;
1910 mcu1_training_err_enable = 1'b0;
1911 mcu2_training_err_enable = 1'b0;
1912 mcu3_training_err_enable = 1'b0;
1913
1914// - End
1915
1916 mcu0_fbdic_f_1_cnt = 2'b0;
1917 mcu1_fbdic_f_1_cnt = 2'b0;
1918 mcu2_fbdic_f_1_cnt = 2'b0;
1919 mcu3_fbdic_f_1_cnt = 2'b0;
1920
1921 mcu0_wdata_dimm = 3'b0;
1922 mcu1_wdata_dimm = 3'b0;
1923 mcu2_wdata_dimm = 3'b0;
1924 mcu3_wdata_dimm = 3'b0;
1925
1926 enabled = 1'b1;
1927
1928 if ($test$plusargs("mcu_fmon_disable"))
1929 enabled = 1'b0;
1930
1931 if ($test$plusargs("disable_sync_check"))
1932 sync_collision_check_enable = 1'b0;
1933 else
1934 sync_collision_check_enable = 1'b1;
1935
1936end
1937
1938always @ (posedge (drl2clk && enabled))
1939begin
1940
1941 // ----- Arbitration/Collision Checks ------
1942
1943 if ((mcu0_drif_dram_cmd_a==`WR && mcu0_drif_dram_cmd_b==`WR) && (mcu0_drif_dram_dimm_a==mcu0_drif_dram_dimm_b))
1944 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue writes to same dimms in Slot A and B");
1945
1946 if ((mcu0_drif_dram_cmd_a==`WR && mcu0_drif_dram_cmd_c==`WR) && (mcu0_drif_dram_dimm_a==mcu0_drif_dram_dimm_c))
1947 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue writes to same dimms in Slot A and C");
1948
1949 if ((mcu0_drif_dram_cmd_b==`WR && mcu0_drif_dram_cmd_c==`WR) && (mcu0_drif_dram_dimm_b==mcu0_drif_dram_dimm_c))
1950 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue writes to same dimms in Slot B and C");
1951
1952 // MCU1 DIMM Collision Checks
1953
1954 if ((mcu1_drif_dram_cmd_a==`WR && mcu1_drif_dram_cmd_b==`WR) && (mcu1_drif_dram_dimm_a==mcu1_drif_dram_dimm_b))
1955 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue writes to same dimms in Slot A and B");
1956
1957 if ((mcu1_drif_dram_cmd_a==`WR && mcu1_drif_dram_cmd_c==`WR) && (mcu1_drif_dram_dimm_a==mcu1_drif_dram_dimm_c))
1958 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue writes to same dimms in Slot A and C");
1959
1960 if ((mcu1_drif_dram_cmd_b==`WR && mcu1_drif_dram_cmd_c==`WR) && (mcu1_drif_dram_dimm_b==mcu1_drif_dram_dimm_c))
1961 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue writes to same dimms in Slot B and C");
1962
1963 // MCU2 DIMM Collision Checks
1964
1965 if ((mcu2_drif_dram_cmd_a==`WR && mcu2_drif_dram_cmd_b==`WR) && (mcu2_drif_dram_dimm_a==mcu2_drif_dram_dimm_b))
1966 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue writes to same dimms in Slot A and B");
1967
1968 if ((mcu2_drif_dram_cmd_a==`WR && mcu2_drif_dram_cmd_c==`WR) && (mcu2_drif_dram_dimm_a==mcu2_drif_dram_dimm_c))
1969 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue writes to same dimms in Slot A and C");
1970
1971 if ((mcu2_drif_dram_cmd_b==`WR && mcu2_drif_dram_cmd_c==`WR) && (mcu2_drif_dram_dimm_b==mcu2_drif_dram_dimm_c))
1972 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue writes to same dimms in Slot B and C");
1973
1974 // MCU3 DIMM Collision Checks
1975
1976 if ((mcu3_drif_dram_cmd_a==`WR && mcu3_drif_dram_cmd_b==`WR) && (mcu3_drif_dram_dimm_a==mcu3_drif_dram_dimm_b))
1977 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue writes to same dimms in Slot A and B");
1978
1979 if ((mcu3_drif_dram_cmd_a==`WR && mcu3_drif_dram_cmd_c==`WR) && (mcu3_drif_dram_dimm_a==mcu3_drif_dram_dimm_c))
1980 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue writes to same dimms in Slot A and C");
1981
1982 if ((mcu3_drif_dram_cmd_b==`WR && mcu3_drif_dram_cmd_c==`WR) && (mcu3_drif_dram_dimm_b==mcu3_drif_dram_dimm_c))
1983 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue writes to same dimms in Slot B and C");
1984
1985 // ---- Read Slot A Checkers -----
1986
1987 // MCU0 1 RD/Frame Check
1988 if((mcu0_drif_dram_cmd_a==`RD && mcu0_drif_dram_cmd_b==`RD) ||
1989 (mcu0_drif_dram_cmd_b==`RD && mcu0_drif_dram_cmd_c==`RD) ||
1990 (mcu0_drif_dram_cmd_a==`RD && mcu0_drif_dram_cmd_c==`RD) ||
1991 (mcu0_drif_dram_cmd_a==`RD && mcu0_drif_dram_cmd_b==`RD && mcu0_drif_dram_cmd_c==`RD))
1992 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue more than 1 RD command per frame");
1993
1994 // MCU1 1 RD/Frame Check
1995 if((mcu1_drif_dram_cmd_a==`RD && mcu1_drif_dram_cmd_b==`RD) ||
1996 (mcu1_drif_dram_cmd_b==`RD && mcu1_drif_dram_cmd_c==`RD) ||
1997 (mcu1_drif_dram_cmd_a==`RD && mcu1_drif_dram_cmd_c==`RD) ||
1998 (mcu1_drif_dram_cmd_a==`RD && mcu1_drif_dram_cmd_b==`RD && mcu1_drif_dram_cmd_c==`RD))
1999 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue more than 1 RD command per frame");
2000
2001 // MCU2 1 RD/Frame Check
2002 if((mcu2_drif_dram_cmd_a==`RD && mcu2_drif_dram_cmd_b==`RD) ||
2003 (mcu2_drif_dram_cmd_b==`RD && mcu2_drif_dram_cmd_c==`RD) ||
2004 (mcu2_drif_dram_cmd_a==`RD && mcu2_drif_dram_cmd_c==`RD) ||
2005 (mcu2_drif_dram_cmd_a==`RD && mcu2_drif_dram_cmd_b==`RD && mcu2_drif_dram_cmd_c==`RD))
2006 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue more than 1 RD command per frame");
2007
2008 // MCU3 1 RD/Frame Check
2009 if((mcu3_drif_dram_cmd_a==`RD && mcu3_drif_dram_cmd_b==`RD) ||
2010 (mcu3_drif_dram_cmd_b==`RD && mcu3_drif_dram_cmd_c==`RD) ||
2011 (mcu3_drif_dram_cmd_a==`RD && mcu3_drif_dram_cmd_c==`RD) ||
2012 (mcu3_drif_dram_cmd_a==`RD && mcu3_drif_dram_cmd_b==`RD && mcu3_drif_dram_cmd_c==`RD))
2013 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue more than 1 RD command per frame");
2014
2015 // MCU0 1 RD(Slot A) Check
2016 if (mcu0_drif_dram_cmd_b==`RD || mcu0_drif_dram_cmd_c==`RD)
2017 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue RD CMD in Slots B or C");
2018
2019 // MCU1 1 RD(Slot A) Check
2020 if (mcu1_drif_dram_cmd_b==`RD || mcu1_drif_dram_cmd_c==`RD)
2021 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue RD CMD in Slots B or C");
2022
2023 // MCU2 1 RD(Slot A) Check
2024 if (mcu2_drif_dram_cmd_b==`RD || mcu2_drif_dram_cmd_c==`RD)
2025 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue RD CMD in Slots B or C");
2026
2027 // MCU3 1 RD(Slot A) Check
2028 if (mcu3_drif_dram_cmd_b==`RD || mcu3_drif_dram_cmd_c==`RD)
2029 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue RD CMD in Slots B or C");
2030
2031 // ---- Read (Slot A) & Auto Ref Collision Checks ----
2032
2033 // MCU0 RD(A) & Auto Ref(B) Check
2034 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_a==`RD) && (mcu0_drif_dram_dimm_a == mcu0_drif_dram_dimm_b))
2035 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue RD CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2036
2037 // MCU1 RD(A) & Auto Ref(B) Check
2038 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_a==`RD) && (mcu1_drif_dram_dimm_a == mcu1_drif_dram_dimm_b))
2039 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue RD CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2040
2041 // MCU2 RD(A) & Auto Ref(B) Check
2042 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_a==`RD) && (mcu2_drif_dram_dimm_a == mcu2_drif_dram_dimm_b))
2043 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue RD CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2044
2045 // MCU3 RD(A) & Auto Ref(B) Check
2046 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_a==`RD) && (mcu3_drif_dram_dimm_a == mcu3_drif_dram_dimm_b))
2047 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue RD CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2048
2049 // ---- Write (Slot A) & Auto Ref Collision Checks ----
2050
2051 // MCU0 WR(A) & Auto Ref(B) Check
2052 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_a==`WR) && (mcu0_drif_dram_dimm_a == mcu0_drif_dram_dimm_b))
2053 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue WR CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2054
2055 // MCU1 WR(A) & Auto Ref(B) Check
2056 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_a==`WR) && (mcu1_drif_dram_dimm_a == mcu1_drif_dram_dimm_b))
2057 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue WR CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2058
2059 // MCU2 WR(A) & Auto Ref(B) Check
2060 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_a==`WR) && (mcu2_drif_dram_dimm_a == mcu2_drif_dram_dimm_b))
2061 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue WR CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2062
2063 // MCU3 WR(A) & Auto Ref(B) Check
2064 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_a==`WR) && (mcu3_drif_dram_dimm_a == mcu3_drif_dram_dimm_b))
2065 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue WR CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2066
2067 // ---- Write (Slot C) & Auto Ref Collision Checks ----
2068
2069 // MCU0 WR(C) & Auto Ref(B) Check
2070 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_c==`WR) && (mcu0_drif_dram_dimm_c == mcu0_drif_dram_dimm_b))
2071 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue WR CMD (C) and Auto Ref (B) addressed to same DIMM in same cycle");
2072
2073 // MCU1 WR(C) & Auto Ref(B) Check
2074 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_c==`WR) && (mcu1_drif_dram_dimm_c == mcu1_drif_dram_dimm_b))
2075 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue WR CMD (C) and Auto Ref (B) addressed to same DIMM in same cycle");
2076
2077 // MCU2 WR(C) & Auto Ref(B) Check
2078 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_c==`WR) && (mcu2_drif_dram_dimm_c == mcu2_drif_dram_dimm_b))
2079 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue WR CMD (C) and Auto Ref (B) addressed to same DIMM in same cycle");
2080
2081 // MCU3 WR(C) & Auto Ref(B) Check
2082 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_c==`WR) && (mcu3_drif_dram_dimm_c == mcu3_drif_dram_dimm_b))
2083 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue WR CMD (C) and Auto Ref (B) addressed to same DIMM in same cycle");
2084
2085 // ---- Activate (Slot A) & Auto Ref Collision Checks ----
2086
2087 // MCU0 ACT(A) & Auto Ref(B) Check
2088 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_a==`ACT) && (mcu0_drif_dram_dimm_a == mcu0_drif_dram_dimm_b))
2089 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2090
2091 // MCU1 ACT(A) & Auto Ref(B) Check
2092 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_a==`ACT) && (mcu1_drif_dram_dimm_a == mcu1_drif_dram_dimm_b))
2093 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2094
2095 // MCU2 ACT(A) & Auto Ref(B) Check
2096 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_a==`ACT) && (mcu2_drif_dram_dimm_a == mcu2_drif_dram_dimm_b))
2097 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2098
2099 // MCU3 ACT(A) & Auto Ref(B) Check
2100 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_a==`ACT) && (mcu3_drif_dram_dimm_a == mcu3_drif_dram_dimm_b))
2101 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2102
2103 // ---- Activate (Slot C) & Auto Ref Collision Checks ----
2104
2105 // MCU0 ACT(C) & Auto Ref(B) Check
2106 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_c==`ACT) && (mcu0_drif_dram_dimm_c == mcu0_drif_dram_dimm_b))
2107 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2108
2109 // MCU1 ACT(C) & Auto Ref(B) Check
2110 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_c==`ACT) && (mcu1_drif_dram_dimm_c == mcu1_drif_dram_dimm_b))
2111 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2112
2113 // MCU2 ACT(C) & Auto Ref(B) Check
2114 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_c==`ACT) && (mcu2_drif_dram_dimm_c == mcu2_drif_dram_dimm_b))
2115 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2116
2117 // MCU3 ACT(C) & Auto Ref(B) Check
2118 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_c==`ACT) && (mcu3_drif_dram_dimm_c == mcu3_drif_dram_dimm_b))
2119 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue ACT CMD (A) and Auto Ref (B) addressed to same DIMM in same cycle");
2120
2121 // ---- Auto Ref(B) & Power Down(C) Collision Checks ----
2122
2123 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_c==`CMD_OTHER && mcu0_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu0_drif_dram_dimm_b == mcu0_drif_dram_dimm_c))
2124 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue Auto Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2125
2126 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu1_drif_dram_dimm_b == mcu1_drif_dram_dimm_c))
2127 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue Auto Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2128
2129 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu2_drif_dram_dimm_b == mcu2_drif_dram_dimm_c))
2130 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue Auto Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2131
2132 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu3_drif_dram_dimm_b == mcu3_drif_dram_dimm_c))
2133 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue Auto Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2134
2135 // ---- Auto Ref(B) & Power Enter(C) Collision Checks ----
2136
2137 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF && mcu0_drif_dram_cmd_c==`CMD_OTHER && mcu0_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu0_drif_dram_dimm_b == mcu0_drif_dram_dimm_c))
2138 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue Auto Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2139
2140 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF && mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu1_drif_dram_dimm_b == mcu1_drif_dram_dimm_c))
2141 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue Auto Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2142
2143 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF && mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu2_drif_dram_dimm_b == mcu2_drif_dram_dimm_c))
2144 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue Auto Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2145
2146 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF && mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu3_drif_dram_dimm_b == mcu3_drif_dram_dimm_c))
2147 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue Auto Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2148
2149 // ---- Self Ref(B) & Power Down(C) Collision Checks ----
2150
2151 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRE && mcu0_drif_dram_cmd_c==`CMD_OTHER && mcu0_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu0_drif_dram_dimm_b == mcu0_drif_dram_dimm_c))
2152 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue Self Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2153
2154 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_SRE && mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu1_drif_dram_dimm_b == mcu1_drif_dram_dimm_c))
2155 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue Self Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2156
2157 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_SRE && mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu2_drif_dram_dimm_b == mcu2_drif_dram_dimm_c))
2158 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue Self Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2159
2160 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_SRE && mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_SRPDX) && (mcu3_drif_dram_dimm_b == mcu3_drif_dram_dimm_c))
2161 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue Self Ref (B) and Power Down (C) addressed to same DIMM in same cycle");
2162
2163 // ---- Self Ref(B) & Power Enter(C) Collision Checks ----
2164
2165 if ((mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRE && mcu0_drif_dram_cmd_c==`CMD_OTHER && mcu0_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu0_drif_dram_dimm_b == mcu0_drif_dram_dimm_c))
2166 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: FBDIC cannot issue Self Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2167
2168 if ((mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_SRE && mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu1_drif_dram_dimm_b == mcu1_drif_dram_dimm_c))
2169 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: FBDIC cannot issue Self Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2170
2171 if ((mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_SRE && mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu2_drif_dram_dimm_b == mcu2_drif_dram_dimm_c))
2172 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: FBDIC cannot issue Self Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2173
2174 if ((mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_SRE && mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_PDE) && (mcu3_drif_dram_dimm_b == mcu3_drif_dram_dimm_c))
2175 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: FBDIC cannot issue Self Ref (B) and Power Enter (C) addressed to same DIMM in same cycle");
2176
2177 // ---- Tick Monitor : Sync Frame Req ----
2178
2179 if (fbdic_sync_frame_req_0)
2180 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: SYNC Frame request issued");
2181 if (fbdic_sync_frame_req_1)
2182 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: SYNC Frame request issued");
2183 if (fbdic_sync_frame_req_2)
2184 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: SYNC Frame request issued");
2185 if (fbdic_sync_frame_req_3)
2186 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: SYNC Frame request issued");
2187
2188 //----------------------------------------------------------------------------------------------
2189 // M C U 0 - phys addr gen
2190 //----------------------------------------------------------------------------------------------
2191
2192 mcu0_physical_addr_a = 40'b0;
2193 mcu0_physical_addr_b = 40'b0;
2194 mcu0_physical_addr_c = 40'b0;
2195
2196/*
2197reg chnl_type; // Dual Channel (1) or Single Channel (0)
2198reg rank_addr; // RANK HIGH (1), RANK LOW (0)
2199reg rank; // 1S (no stack dimm,0) or 2S (yes stack dimm,1)
2200reg [1:0] dimm_size ; // 256M=00, 512M=01, 1G=10, 2G=11
2201reg [2:0] num_dimms; // DIMM NUMBERS: 1D=1, 2D=2, ... , 7D=7, 8D=0
2202*/
2203
2204 case({chnl_type, rank_addr, rank, dimm_size, num_dimms})
2205
2206 //-------------------------------
2207 // DUAL CHANNEL, RANK HIGH
2208 //-------------------------------
2209
2210 8'b1_1_0_00_001,
2211 8'b1_1_0_00_010,
2212 8'b1_1_0_00_100,
2213 8'b1_1_0_00_000: begin
2214 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[12:0],
2215 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2],
2216 mcu0_drif_dram_bank_a[1], 2'b00, mcu0_drif_dram_bank_a[0],
2217 mcu0_drif_dram_addr_a[1], 5'b00000};
2218 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[12:0],
2219 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2],
2220 mcu0_drif_dram_bank_b[1], 2'b00, mcu0_drif_dram_bank_b[0],
2221 mcu0_drif_dram_addr_b[1], 5'b00000};
2222 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[12:0],
2223 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2],
2224 mcu0_drif_dram_bank_c[1], 2'b00, mcu0_drif_dram_bank_c[0],
2225 mcu0_drif_dram_addr_c[1], 5'b00000};
2226 end
2227 8'b1_1_1_00_001,
2228 8'b1_1_1_00_010,
2229 8'b1_1_1_00_100,
2230 8'b1_1_1_00_000: begin
2231 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[12:0],
2232 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2],
2233 mcu0_drif_dram_bank_a[1], 2'b00, mcu0_drif_dram_bank_a[0],
2234 mcu0_drif_dram_addr_a[1], 5'b00000};
2235 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[12:0],
2236 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2],
2237 mcu0_drif_dram_bank_b[1], 2'b00, mcu0_drif_dram_bank_b[0],
2238 mcu0_drif_dram_addr_b[1], 5'b00000};
2239 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[12:0],
2240 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2],
2241 mcu0_drif_dram_bank_c[1], 2'b00, mcu0_drif_dram_bank_c[0],
2242 mcu0_drif_dram_addr_c[1], 5'b00000};
2243 case(num_dimms)
2244 001: begin
2245 mcu0_physical_addr_a[32] = mcu0_drif_dram_rank_a;
2246 mcu0_physical_addr_b[32] = mcu0_drif_dram_rank_b;
2247 mcu0_physical_addr_c[32] = mcu0_drif_dram_rank_c;
2248 end
2249 010: begin
2250 mcu0_physical_addr_a[33] = mcu0_drif_dram_rank_a;
2251 mcu0_physical_addr_b[33] = mcu0_drif_dram_rank_b;
2252 mcu0_physical_addr_c[33] = mcu0_drif_dram_rank_c;
2253 end
2254 100: begin
2255 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2256 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2257 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2258 end
2259 000: begin
2260 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2261 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2262 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2263 end
2264 endcase
2265 end
2266 8'b1_1_0_01_001,
2267 8'b1_1_0_01_010,
2268 8'b1_1_0_01_100,
2269 8'b1_1_0_01_000: begin
2270 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[13:0],
2271 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2],
2272 mcu0_drif_dram_bank_a[1], 2'b00, mcu0_drif_dram_bank_a[0],
2273 mcu0_drif_dram_addr_a[1], 5'b00000};
2274 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[13:0],
2275 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2],
2276 mcu0_drif_dram_bank_b[1], 2'b00, mcu0_drif_dram_bank_b[0],
2277 mcu0_drif_dram_addr_b[1], 5'b00000};
2278 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[13:0],
2279 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2],
2280 mcu0_drif_dram_bank_c[1], 2'b00, mcu0_drif_dram_bank_c[0],
2281 mcu0_drif_dram_addr_c[1], 5'b00000};
2282 end
2283 8'b1_1_1_01_001,
2284 8'b1_1_1_01_010,
2285 8'b1_1_1_01_100,
2286 8'b1_1_1_01_000: begin
2287 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[13:0],
2288 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2],
2289 mcu0_drif_dram_bank_a[1], 2'b00, mcu0_drif_dram_bank_a[0],
2290 mcu0_drif_dram_addr_a[1], 5'b00000};
2291 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[13:0],
2292 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2],
2293 mcu0_drif_dram_bank_b[1], 2'b00, mcu0_drif_dram_bank_b[0],
2294 mcu0_drif_dram_addr_b[1], 5'b00000};
2295 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[13:0],
2296 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2],
2297 mcu0_drif_dram_bank_c[1], 2'b00, mcu0_drif_dram_bank_c[0],
2298 mcu0_drif_dram_addr_c[1], 5'b00000};
2299 case(num_dimms)
2300 001: begin
2301 mcu0_physical_addr_a[33] = mcu0_drif_dram_rank_a;
2302 mcu0_physical_addr_b[33] = mcu0_drif_dram_rank_b;
2303 mcu0_physical_addr_c[33] = mcu0_drif_dram_rank_c;
2304 end
2305 010: begin
2306 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2307 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2308 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2309 end
2310 100: begin
2311 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2312 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2313 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2314 end
2315 000: begin
2316 mcu0_physical_addr_a[36] = mcu0_drif_dram_rank_a;
2317 mcu0_physical_addr_b[36] = mcu0_drif_dram_rank_b;
2318 mcu0_physical_addr_c[36] = mcu0_drif_dram_rank_c;
2319 end
2320 endcase
2321 end
2322 8'b1_1_0_10_001,
2323 8'b1_1_0_10_010,
2324 8'b1_1_0_10_100,
2325 8'b1_1_0_10_000: begin
2326 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[2],
2327 mcu0_drif_dram_ras_addr_a[13:0], mcu0_drif_dram_addr_a[11],
2328 mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[2:1],
2329 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1], 5'b00000};
2330 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[2],
2331 mcu0_drif_dram_ras_addr_b[13:0], mcu0_drif_dram_addr_b[11],
2332 mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[2:1],
2333 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1], 5'b00000};
2334 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[2],
2335 mcu0_drif_dram_ras_addr_c[13:0], mcu0_drif_dram_addr_c[11],
2336 mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[2:1],
2337 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1], 5'b00000};
2338 end
2339 8'b1_1_1_10_001,
2340 8'b1_1_1_10_010,
2341 8'b1_1_1_10_100,
2342 8'b1_1_1_10_000: begin
2343 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[2],
2344 mcu0_drif_dram_ras_addr_a[13:0], mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3],
2345 mcu0_drif_dram_bank_a[2:1], 2'b00, mcu0_drif_dram_bank_a[0],
2346 mcu0_drif_dram_addr_a[1], 5'b00000};
2347 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[2],
2348 mcu0_drif_dram_ras_addr_b[13:0], mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3],
2349 mcu0_drif_dram_bank_b[2:1], 2'b00, mcu0_drif_dram_bank_b[0],
2350 mcu0_drif_dram_addr_b[1], 5'b00000};
2351 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[2],
2352 mcu0_drif_dram_ras_addr_c[13:0], mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3],
2353 mcu0_drif_dram_bank_c[2:1], 2'b00, mcu0_drif_dram_bank_c[0],
2354 mcu0_drif_dram_addr_c[1], 5'b00000};
2355 case(num_dimms)
2356 001: begin
2357 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2358 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2359 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2360 end
2361 010: begin
2362 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2363 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2364 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2365 end
2366 100: begin
2367 mcu0_physical_addr_a[36] = mcu0_drif_dram_rank_a;
2368 mcu0_physical_addr_b[36] = mcu0_drif_dram_rank_b;
2369 mcu0_physical_addr_c[36] = mcu0_drif_dram_rank_c;
2370 end
2371 000: begin
2372 mcu0_physical_addr_a[37] = mcu0_drif_dram_rank_a;
2373 mcu0_physical_addr_b[37] = mcu0_drif_dram_rank_b;
2374 mcu0_physical_addr_c[37] = mcu0_drif_dram_rank_c;
2375 end
2376 endcase
2377 end
2378 8'b1_1_0_11_001,
2379 8'b1_1_0_11_010,
2380 8'b1_1_0_11_100,
2381 8'b1_1_0_11_000: begin
2382 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[2],
2383 mcu0_drif_dram_ras_addr_a[14:0], mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3],
2384 mcu0_drif_dram_bank_a[2:1], 2'b00, mcu0_drif_dram_bank_a[0],
2385 mcu0_drif_dram_addr_a[1], 5'b00000};
2386 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[2],
2387 mcu0_drif_dram_ras_addr_b[14:0], mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3],
2388 mcu0_drif_dram_bank_b[2:1], 2'b00, mcu0_drif_dram_bank_b[0],
2389 mcu0_drif_dram_addr_b[1], 5'b00000};
2390 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[2],
2391 mcu0_drif_dram_ras_addr_c[14:0], mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3],
2392 mcu0_drif_dram_bank_c[2:1], 2'b00, mcu0_drif_dram_bank_c[0],
2393 mcu0_drif_dram_addr_c[1], 5'b00000};
2394 end
2395 8'b1_1_1_11_001,
2396 8'b1_1_1_11_010,
2397 8'b1_1_1_11_100,
2398 8'b1_1_1_11_000: begin
2399 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[2],
2400 mcu0_drif_dram_ras_addr_a[14:0], mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3],
2401 mcu0_drif_dram_bank_a[2:1], 2'b00, mcu0_drif_dram_bank_a[0],
2402 mcu0_drif_dram_addr_a[1], 5'b00000};
2403 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[2],
2404 mcu0_drif_dram_ras_addr_b[14:0], mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3],
2405 mcu0_drif_dram_bank_b[2:1], 2'b00, mcu0_drif_dram_bank_b[0],
2406 mcu0_drif_dram_addr_b[1], 5'b00000};
2407 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[2],
2408 mcu0_drif_dram_ras_addr_c[14:0], mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3],
2409 mcu0_drif_dram_bank_c[2:1], 2'b00, mcu0_drif_dram_bank_c[0],
2410 mcu0_drif_dram_addr_c[1], 5'b00000};
2411 case(num_dimms)
2412 001: begin
2413 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2414 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2415 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2416 end
2417 010: begin
2418 mcu0_physical_addr_a[36] = mcu0_drif_dram_rank_a;
2419 mcu0_physical_addr_b[36] = mcu0_drif_dram_rank_b;
2420 mcu0_physical_addr_c[36] = mcu0_drif_dram_rank_c;
2421 end
2422 100: begin
2423 mcu0_physical_addr_a[37] = mcu0_drif_dram_rank_a;
2424 mcu0_physical_addr_b[37] = mcu0_drif_dram_rank_b;
2425 mcu0_physical_addr_c[37] = mcu0_drif_dram_rank_c;
2426 end
2427 000: begin
2428 mcu0_physical_addr_a[38] = mcu0_drif_dram_rank_a;
2429 mcu0_physical_addr_b[38] = mcu0_drif_dram_rank_b;
2430 mcu0_physical_addr_c[38] = mcu0_drif_dram_rank_c;
2431 end
2432 endcase
2433 end
2434
2435 //---------------------------
2436 // SINGLE CHANNEL, RANK HIGH
2437 //---------------------------
2438
2439 8'b0_1_0_00_001,
2440 8'b0_1_0_00_010,
2441 8'b0_1_0_00_100,
2442 8'b0_1_0_00_000: begin
2443 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[12:0],
2444 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
2445 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2446 5'b00000};
2447 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[12:0],
2448 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
2449 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2450 5'b00000};
2451 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[12:0],
2452 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
2453 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2454 5'b00000};
2455 end
2456 8'b0_1_1_00_001,
2457 8'b0_1_1_00_010,
2458 8'b0_1_1_00_100,
2459 8'b0_1_1_00_000: begin
2460 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[12:0],
2461 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
2462 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2463 5'b00000};
2464 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[12:0],
2465 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
2466 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2467 5'b00000};
2468 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[12:0],
2469 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
2470 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2471 5'b00000};
2472 case(num_dimms)
2473 001: begin
2474 mcu0_physical_addr_a[31] = mcu0_drif_dram_rank_a;
2475 mcu0_physical_addr_b[31] = mcu0_drif_dram_rank_b;
2476 mcu0_physical_addr_c[31] = mcu0_drif_dram_rank_c;
2477 end
2478 010: begin
2479 mcu0_physical_addr_a[32] = mcu0_drif_dram_rank_a;
2480 mcu0_physical_addr_b[32] = mcu0_drif_dram_rank_b;
2481 mcu0_physical_addr_c[32] = mcu0_drif_dram_rank_c;
2482 end
2483 100: begin
2484 mcu0_physical_addr_a[33] = mcu0_drif_dram_rank_a;
2485 mcu0_physical_addr_b[33] = mcu0_drif_dram_rank_b;
2486 mcu0_physical_addr_c[33] = mcu0_drif_dram_rank_c;
2487 end
2488 000: begin
2489 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2490 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2491 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2492 end
2493 endcase
2494 end
2495 8'b0_1_0_01_001,
2496 8'b0_1_0_01_010,
2497 8'b0_1_0_01_100,
2498 8'b0_1_0_01_000: begin
2499 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[13:0],
2500 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
2501 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2502 5'b00000};
2503 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[13:0],
2504 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
2505 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2506 5'b00000};
2507 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[13:0],
2508 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
2509 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2510 5'b00000};
2511 end
2512 8'b0_1_1_01_001,
2513 8'b0_1_1_01_010,
2514 8'b0_1_1_01_100,
2515 8'b0_1_1_01_000: begin
2516 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_ras_addr_a[13:0],
2517 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
2518 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2519 5'b00000};
2520 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_ras_addr_b[13:0],
2521 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
2522 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2523 5'b00000};
2524 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_ras_addr_c[13:0],
2525 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
2526 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2527 5'b00000};
2528 case(num_dimms)
2529 001: begin
2530 mcu0_physical_addr_a[32] = mcu0_drif_dram_rank_a;
2531 mcu0_physical_addr_b[32] = mcu0_drif_dram_rank_b;
2532 mcu0_physical_addr_c[32] = mcu0_drif_dram_rank_c;
2533 end
2534 010: begin
2535 mcu0_physical_addr_a[33] = mcu0_drif_dram_rank_a;
2536 mcu0_physical_addr_b[33] = mcu0_drif_dram_rank_b;
2537 mcu0_physical_addr_c[33] = mcu0_drif_dram_rank_c;
2538 end
2539 100: begin
2540 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2541 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2542 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2543 end
2544 000: begin
2545 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2546 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2547 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2548 end
2549 endcase
2550 end
2551 8'b0_1_0_10_001,
2552 8'b0_1_0_10_010,
2553 8'b0_1_0_10_100,
2554 8'b0_1_0_10_000: begin
2555 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[3],
2556 mcu0_drif_dram_ras_addr_a[13:0],
2557 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
2558 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2559 5'b00000};
2560 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[3],
2561 mcu0_drif_dram_ras_addr_b[13:0],
2562 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
2563 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2564 5'b00000};
2565 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[3],
2566 mcu0_drif_dram_ras_addr_c[13:0],
2567 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
2568 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2569 5'b00000};
2570 end
2571 8'b0_1_1_10_001,
2572 8'b0_1_1_10_010,
2573 8'b0_1_1_10_100,
2574 8'b0_1_1_10_000: begin
2575 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[3],
2576 mcu0_drif_dram_ras_addr_a[13:0],
2577 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
2578 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2579 5'b00000};
2580 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[3],
2581 mcu0_drif_dram_ras_addr_b[13:0],
2582 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
2583 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2584 5'b00000};
2585 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[3],
2586 mcu0_drif_dram_ras_addr_c[13:0],
2587 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
2588 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2589 5'b00000};
2590 case(num_dimms)
2591 001: begin
2592 mcu0_physical_addr_a[33] = mcu0_drif_dram_rank_a;
2593 mcu0_physical_addr_b[33] = mcu0_drif_dram_rank_b;
2594 mcu0_physical_addr_c[33] = mcu0_drif_dram_rank_c;
2595 end
2596 010: begin
2597 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2598 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2599 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2600 end
2601 100: begin
2602 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2603 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2604 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2605 end
2606 000: begin
2607 mcu0_physical_addr_a[36] = mcu0_drif_dram_rank_a;
2608 mcu0_physical_addr_b[36] = mcu0_drif_dram_rank_b;
2609 mcu0_physical_addr_c[36] = mcu0_drif_dram_rank_c;
2610 end
2611 endcase
2612 end
2613 8'b0_1_0_11_001,
2614 8'b0_1_0_11_010,
2615 8'b0_1_0_11_100,
2616 8'b0_1_0_11_000: begin
2617 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[3],
2618 mcu0_drif_dram_ras_addr_a[14:0],
2619 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
2620 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2621 5'b00000};
2622 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[3],
2623 mcu0_drif_dram_ras_addr_b[14:0],
2624 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
2625 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2626 5'b00000};
2627 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[3],
2628 mcu0_drif_dram_ras_addr_c[14:0],
2629 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
2630 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2631 5'b00000};
2632 end
2633 8'b0_1_1_11_001,
2634 8'b0_1_1_11_010,
2635 8'b0_1_1_11_100,
2636 8'b0_1_1_11_000: begin
2637 mcu0_physical_addr_a = {mcu0_drif_dram_dimm_a, mcu0_drif_dram_addr_a[3],
2638 mcu0_drif_dram_ras_addr_a[14:0],
2639 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
2640 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
2641 5'b00000};
2642 mcu0_physical_addr_b = {mcu0_drif_dram_dimm_b, mcu0_drif_dram_addr_b[3],
2643 mcu0_drif_dram_ras_addr_b[14:0],
2644 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
2645 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
2646 5'b00000};
2647 mcu0_physical_addr_c = {mcu0_drif_dram_dimm_c, mcu0_drif_dram_addr_c[3],
2648 mcu0_drif_dram_ras_addr_c[14:0],
2649 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
2650 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
2651 5'b00000};
2652 case(num_dimms)
2653 001: begin
2654 mcu0_physical_addr_a[34] = mcu0_drif_dram_rank_a;
2655 mcu0_physical_addr_b[34] = mcu0_drif_dram_rank_b;
2656 mcu0_physical_addr_c[34] = mcu0_drif_dram_rank_c;
2657 end
2658 010: begin
2659 mcu0_physical_addr_a[35] = mcu0_drif_dram_rank_a;
2660 mcu0_physical_addr_b[35] = mcu0_drif_dram_rank_b;
2661 mcu0_physical_addr_c[35] = mcu0_drif_dram_rank_c;
2662 end
2663 100: begin
2664 mcu0_physical_addr_a[36] = mcu0_drif_dram_rank_a;
2665 mcu0_physical_addr_b[36] = mcu0_drif_dram_rank_b;
2666 mcu0_physical_addr_c[36] = mcu0_drif_dram_rank_c;
2667 end
2668 000: begin
2669 mcu0_physical_addr_a[37] = mcu0_drif_dram_rank_a;
2670 mcu0_physical_addr_b[37] = mcu0_drif_dram_rank_b;
2671 mcu0_physical_addr_c[37] = mcu0_drif_dram_rank_c;
2672 end
2673 endcase
2674 end
2675
2676 //---------------------------
2677 // DUAL CHANNEL, RANK LOW
2678 //---------------------------
2679
2680 8'b1_0_0_00_001,
2681 8'b1_0_0_00_010,
2682 8'b1_0_0_00_100,
2683 8'b1_0_0_00_000: begin
2684 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[12:0],
2685 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2], mcu0_drif_dram_bank_a[1],
2686 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
2687 5'b00000};
2688 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[12:0],
2689 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2], mcu0_drif_dram_bank_b[1],
2690 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
2691 5'b00000};
2692 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[12:0],
2693 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2], mcu0_drif_dram_bank_c[1],
2694 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
2695 5'b00000};
2696 case(num_dimms)
2697 001: begin
2698 end
2699 010: begin
2700 mcu0_physical_addr_a[32] = mcu0_drif_dram_addr_a[2];
2701 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
2702 mcu0_physical_addr_b[32] = mcu0_drif_dram_addr_b[2];
2703 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
2704 mcu0_physical_addr_c[32] = mcu0_drif_dram_addr_c[2];
2705 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
2706 end
2707 100: begin
2708 mcu0_physical_addr_a[33:32] = mcu0_drif_dram_addr_a[3:2];
2709 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
2710 mcu0_physical_addr_b[33:32] = mcu0_drif_dram_addr_b[3:2];
2711 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
2712 mcu0_physical_addr_c[33:32] = mcu0_drif_dram_addr_c[3:2];
2713 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
2714 end
2715 000: begin
2716 mcu0_physical_addr_a[34:32] = mcu0_drif_dram_addr_a[4:2];
2717 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
2718 mcu0_physical_addr_b[34:32] = mcu0_drif_dram_addr_b[4:2];
2719 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
2720 mcu0_physical_addr_c[34:32] = mcu0_drif_dram_addr_c[4:2];
2721 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
2722 end
2723 endcase
2724 end
2725 8'b1_0_1_00_001,
2726 8'b1_0_1_00_010,
2727 8'b1_0_1_00_100,
2728 8'b1_0_1_00_000: begin
2729 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[12:0],
2730 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2], mcu0_drif_dram_bank_a[1],
2731 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
2732 5'b00000};
2733 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[12:0],
2734 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2], mcu0_drif_dram_bank_b[1],
2735 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
2736 5'b00000};
2737 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[12:0],
2738 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2], mcu0_drif_dram_bank_c[1],
2739 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
2740 5'b00000};
2741 case(num_dimms)
2742 001: begin
2743 mcu0_physical_addr_a[32] = mcu0_drif_dram_addr_a[2];
2744 mcu0_physical_addr_a[10] = mcu0_drif_dram_rank_a;
2745 mcu0_physical_addr_b[32] = mcu0_drif_dram_addr_b[2];
2746 mcu0_physical_addr_b[10] = mcu0_drif_dram_rank_b;
2747 mcu0_physical_addr_c[32] = mcu0_drif_dram_addr_c[2];
2748 mcu0_physical_addr_c[10] = mcu0_drif_dram_rank_c;
2749 end
2750 010: begin
2751 mcu0_physical_addr_a[33:32] = mcu0_drif_dram_addr_a[3:2];
2752 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
2753 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
2754 mcu0_physical_addr_b[33:32] = mcu0_drif_dram_addr_b[3:2];
2755 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
2756 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
2757 mcu0_physical_addr_c[33:32] = mcu0_drif_dram_addr_c[3:2];
2758 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
2759 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
2760 end
2761 100: begin
2762 mcu0_physical_addr_a[34:32] = mcu0_drif_dram_addr_a[4:2];
2763 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
2764 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
2765 mcu0_physical_addr_b[34:32] = mcu0_drif_dram_addr_b[4:2];
2766 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
2767 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
2768 mcu0_physical_addr_c[34:32] = mcu0_drif_dram_addr_c[4:2];
2769 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
2770 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
2771 end
2772 000: begin
2773 mcu0_physical_addr_a[35:32] = mcu0_drif_dram_addr_a[5:2];
2774 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
2775 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
2776 mcu0_physical_addr_b[35:32] = mcu0_drif_dram_addr_b[5:2];
2777 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
2778 mcu0_physical_addr_b[13] = mcu0_drif_dram_rank_b;
2779 mcu0_physical_addr_c[35:32] = mcu0_drif_dram_addr_c[5:2];
2780 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
2781 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
2782 end
2783 endcase
2784 end
2785 8'b1_0_0_01_001,
2786 8'b1_0_0_01_010,
2787 8'b1_0_0_01_100,
2788 8'b1_0_0_01_000: begin
2789 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
2790 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2], mcu0_drif_dram_bank_a[1],
2791 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
2792 5'b00000};
2793 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
2794 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2], mcu0_drif_dram_bank_b[1],
2795 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
2796 5'b00000};
2797 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
2798 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2], mcu0_drif_dram_bank_c[1],
2799 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
2800 5'b00000};
2801 case(num_dimms)
2802 001: begin
2803 end
2804 010: begin
2805 mcu0_physical_addr_a[33] = mcu0_drif_dram_addr_a[2];
2806 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
2807 mcu0_physical_addr_b[33] = mcu0_drif_dram_addr_b[2];
2808 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
2809 mcu0_physical_addr_c[33] = mcu0_drif_dram_addr_c[2];
2810 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
2811 end
2812 100: begin
2813 mcu0_physical_addr_a[34:33] = mcu0_drif_dram_addr_a[3:2];
2814 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
2815 mcu0_physical_addr_b[34:33] = mcu0_drif_dram_addr_b[3:2];
2816 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
2817 mcu0_physical_addr_c[34:33] = mcu0_drif_dram_addr_c[3:2];
2818 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
2819 end
2820 000: begin
2821 mcu0_physical_addr_a[35:33] = mcu0_drif_dram_addr_a[4:2];
2822 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
2823 mcu0_physical_addr_b[35:33] = mcu0_drif_dram_addr_b[4:2];
2824 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
2825 mcu0_physical_addr_c[35:33] = mcu0_drif_dram_addr_c[4:2];
2826 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
2827 end
2828 endcase
2829 end
2830 8'b1_0_1_01_001,
2831 8'b1_0_1_01_010,
2832 8'b1_0_1_01_100,
2833 8'b1_0_1_01_000: begin
2834 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
2835 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2], mcu0_drif_dram_bank_a[1],
2836 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
2837 5'b00000};
2838 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
2839 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2], mcu0_drif_dram_bank_b[1],
2840 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
2841 5'b00000};
2842 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
2843 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2], mcu0_drif_dram_bank_c[1],
2844 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
2845 5'b00000};
2846 case(num_dimms)
2847 001: begin
2848 mcu0_physical_addr_a[33] = mcu0_drif_dram_addr_a[2];
2849 mcu0_physical_addr_a[10] = mcu0_drif_dram_rank_a;
2850 mcu0_physical_addr_b[33] = mcu0_drif_dram_addr_b[2];
2851 mcu0_physical_addr_b[10] = mcu0_drif_dram_rank_b;
2852 mcu0_physical_addr_c[33] = mcu0_drif_dram_addr_c[2];
2853 mcu0_physical_addr_c[10] = mcu0_drif_dram_rank_c;
2854 end
2855 010: begin
2856 mcu0_physical_addr_a[34:33] = mcu0_drif_dram_addr_a[3:2];
2857 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
2858 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
2859 mcu0_physical_addr_b[34:33] = mcu0_drif_dram_addr_b[3:2];
2860 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
2861 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
2862 mcu0_physical_addr_c[34:33] = mcu0_drif_dram_addr_c[3:2];
2863 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
2864 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
2865 end
2866 100: begin
2867 mcu0_physical_addr_a[35:33] = mcu0_drif_dram_addr_a[4:2];
2868 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
2869 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
2870 mcu0_physical_addr_b[35:33] = mcu0_drif_dram_addr_b[4:2];
2871 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
2872 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
2873 mcu0_physical_addr_c[35:33] = mcu0_drif_dram_addr_c[4:2];
2874 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
2875 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
2876 end
2877 000: begin
2878 mcu0_physical_addr_a[36:33] = mcu0_drif_dram_addr_a[5:2];
2879 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
2880 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
2881 mcu0_physical_addr_b[36:33] = mcu0_drif_dram_addr_b[5:2];
2882 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
2883 mcu0_physical_addr_b[13] = mcu0_drif_dram_rank_b;
2884 mcu0_physical_addr_c[36:33] = mcu0_drif_dram_addr_c[5:2];
2885 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
2886 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
2887 end
2888 endcase
2889 end
2890 8'b1_0_0_10_001,
2891 8'b1_0_0_10_010,
2892 8'b1_0_0_10_100,
2893 8'b1_0_0_10_000: begin
2894 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
2895 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[2:1],
2896 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
2897 5'b00000};
2898 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
2899 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[2:1],
2900 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
2901 5'b00000};
2902 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
2903 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[2:1],
2904 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
2905 5'b00000};
2906 case(num_dimms)
2907 001: begin
2908 mcu0_physical_addr_a[33] = mcu0_drif_dram_addr_a[2];
2909 mcu0_physical_addr_b[33] = mcu0_drif_dram_addr_b[2];
2910 mcu0_physical_addr_c[33] = mcu0_drif_dram_addr_c[2];
2911 end
2912 010: begin
2913 mcu0_physical_addr_a[34:33] = mcu0_drif_dram_addr_a[3:2];
2914 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
2915 mcu0_physical_addr_b[34:33] = mcu0_drif_dram_addr_b[3:2];
2916 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
2917 mcu0_physical_addr_c[34:33] = mcu0_drif_dram_addr_c[3:2];
2918 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
2919 end
2920 100: begin
2921 mcu0_physical_addr_a[35:33] = mcu0_drif_dram_addr_a[4:2];
2922 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
2923 mcu0_physical_addr_b[35:33] = mcu0_drif_dram_addr_b[4:2];
2924 mcu0_physical_addr_b[12:11] = mcu0_drif_dram_dimm_b[1:0];
2925 mcu0_physical_addr_c[35:33] = mcu0_drif_dram_addr_c[4:2];
2926 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
2927 end
2928 000: begin
2929 mcu0_physical_addr_a[36:33] = mcu0_drif_dram_addr_a[5:2];
2930 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
2931 mcu0_physical_addr_b[36:33] = mcu0_drif_dram_addr_b[5:2];
2932 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
2933 mcu0_physical_addr_c[36:33] = mcu0_drif_dram_addr_c[5:2];
2934 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
2935 end
2936 endcase
2937 end
2938 8'b1_0_1_10_001,
2939 8'b1_0_1_10_010,
2940 8'b1_0_1_10_100,
2941 8'b1_0_1_10_000: begin
2942 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
2943 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2], mcu0_drif_dram_bank_a[1],
2944 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
2945 5'b00000};
2946 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
2947 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2], mcu0_drif_dram_bank_b[1],
2948 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
2949 5'b00000};
2950 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
2951 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2], mcu0_drif_dram_bank_c[1],
2952 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
2953 5'b00000};
2954 case(num_dimms)
2955 001: begin
2956 mcu0_physical_addr_a[34:33] = mcu0_drif_dram_addr_a[3:2];
2957 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
2958 mcu0_physical_addr_b[34:33] = mcu0_drif_dram_addr_b[3:2];
2959 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
2960 mcu0_physical_addr_c[34:33] = mcu0_drif_dram_addr_c[3:2];
2961 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
2962 end
2963 010: begin
2964 mcu0_physical_addr_a[35:33] = mcu0_drif_dram_addr_a[4:2];
2965 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
2966 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
2967 mcu0_physical_addr_b[35:33] = mcu0_drif_dram_addr_b[4:2];
2968 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
2969 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
2970 mcu0_physical_addr_c[35:33] = mcu0_drif_dram_addr_c[4:2];
2971 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
2972 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
2973 end
2974 100: begin
2975 mcu0_physical_addr_a[36:33] = mcu0_drif_dram_addr_a[5:2];
2976 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
2977 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
2978 mcu0_physical_addr_b[36:33] = mcu0_drif_dram_addr_b[5:2];
2979 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[1:0];
2980 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
2981 mcu0_physical_addr_c[36:33] = mcu0_drif_dram_addr_c[5:2];
2982 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
2983 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
2984 end
2985 000: begin
2986 mcu0_physical_addr_a[37:33] = mcu0_drif_dram_addr_a[5:2];
2987 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
2988 mcu0_physical_addr_a[14] = mcu0_drif_dram_rank_a;
2989 mcu0_physical_addr_b[37:33] = mcu0_drif_dram_addr_b[5:2];
2990 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
2991 mcu0_physical_addr_b[14] = mcu0_drif_dram_rank_b;
2992 mcu0_physical_addr_c[37:33] = mcu0_drif_dram_addr_c[5:2];
2993 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
2994 mcu0_physical_addr_c[14] = mcu0_drif_dram_rank_c;
2995 end
2996 endcase
2997 end
2998 8'b1_0_0_11_001,
2999 8'b1_0_0_11_010,
3000 8'b1_0_0_11_100,
3001 8'b1_0_0_11_000: begin
3002 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[14:0],
3003 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[2:1],
3004 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
3005 5'b00000};
3006 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[14:0],
3007 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[2:1],
3008 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
3009 5'b00000};
3010 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[14:0],
3011 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[2:1],
3012 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
3013 5'b00000};
3014 case(num_dimms)
3015 001: begin
3016 mcu0_physical_addr_a[34] = mcu0_drif_dram_addr_a[2];
3017 mcu0_physical_addr_b[34] = mcu0_drif_dram_addr_b[2];
3018 mcu0_physical_addr_c[34] = mcu0_drif_dram_addr_c[2];
3019 end
3020 010: begin
3021 mcu0_physical_addr_a[35:34] = mcu0_drif_dram_addr_a[3:2];
3022 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
3023 mcu0_physical_addr_b[35:34] = mcu0_drif_dram_addr_b[3:2];
3024 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
3025 mcu0_physical_addr_c[35:34] = mcu0_drif_dram_addr_c[3:2];
3026 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
3027 end
3028 100: begin
3029 mcu0_physical_addr_a[36:34] = mcu0_drif_dram_addr_a[4:2];
3030 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
3031 mcu0_physical_addr_b[36:34] = mcu0_drif_dram_addr_b[4:2];
3032 mcu0_physical_addr_b[12:11] = mcu0_drif_dram_dimm_b[1:0];
3033 mcu0_physical_addr_c[36:34] = mcu0_drif_dram_addr_c[4:2];
3034 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
3035 end
3036 000: begin
3037 mcu0_physical_addr_a[37:34] = mcu0_drif_dram_addr_a[5:2];
3038 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
3039 mcu0_physical_addr_b[37:34] = mcu0_drif_dram_addr_b[5:2];
3040 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
3041 mcu0_physical_addr_c[37:34] = mcu0_drif_dram_addr_c[5:2];
3042 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
3043 end
3044 endcase
3045 end
3046 8'b1_0_1_11_001,
3047 8'b1_0_1_11_010,
3048 8'b1_0_1_11_100,
3049 8'b1_0_1_11_000: begin
3050 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[14:0],
3051 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:2], mcu0_drif_dram_bank_a[1],
3052 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[1],
3053 5'b00000};
3054 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[14:0],
3055 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:2], mcu0_drif_dram_bank_b[1],
3056 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[1],
3057 5'b00000};
3058 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[14:0],
3059 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:2], mcu0_drif_dram_bank_c[1],
3060 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[1],
3061 5'b00000};
3062 case(num_dimms)
3063 001: begin
3064 mcu0_physical_addr_a[35:34] = mcu0_drif_dram_addr_a[3:2];
3065 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
3066 mcu0_physical_addr_b[35:34] = mcu0_drif_dram_addr_b[3:2];
3067 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
3068 mcu0_physical_addr_c[35:34] = mcu0_drif_dram_addr_c[3:2];
3069 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
3070 end
3071 010: begin
3072 mcu0_physical_addr_a[36:34] = mcu0_drif_dram_addr_a[4:2];
3073 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
3074 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
3075 mcu0_physical_addr_b[36:34] = mcu0_drif_dram_addr_b[4:2];
3076 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
3077 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
3078 mcu0_physical_addr_c[36:34] = mcu0_drif_dram_addr_c[4:2];
3079 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
3080 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
3081 end
3082 100: begin
3083 mcu0_physical_addr_a[37:34] = mcu0_drif_dram_addr_a[5:2];
3084 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
3085 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
3086 mcu0_physical_addr_b[37:34] = mcu0_drif_dram_addr_b[5:2];
3087 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[1:0];
3088 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
3089 mcu0_physical_addr_c[37:34] = mcu0_drif_dram_addr_c[5:2];
3090 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
3091 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
3092 end
3093 000: begin
3094 mcu0_physical_addr_a[38:34] = mcu0_drif_dram_addr_a[5:2];
3095 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
3096 mcu0_physical_addr_a[14] = mcu0_drif_dram_rank_a;
3097 mcu0_physical_addr_b[38:34] = mcu0_drif_dram_addr_b[5:2];
3098 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
3099 mcu0_physical_addr_b[14] = mcu0_drif_dram_rank_b;
3100 mcu0_physical_addr_c[38:34] = mcu0_drif_dram_addr_c[5:2];
3101 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
3102 mcu0_physical_addr_c[14] = mcu0_drif_dram_rank_c;
3103 end
3104 endcase
3105 end
3106
3107 //---------------------------
3108 // SINGLE CHANNEL, RANK LOW
3109 //---------------------------
3110
3111 8'b0_0_0_00_001,
3112 8'b0_0_0_00_010,
3113 8'b0_0_0_00_100,
3114 8'b0_0_0_00_000: begin
3115 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[12:0],
3116 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
3117 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3118 5'b00000};
3119 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[12:0],
3120 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
3121 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3122 5'b00000};
3123 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[12:0],
3124 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
3125 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3126 5'b00000};
3127 case(num_dimms)
3128 001: begin
3129 end
3130 010: begin
3131 mcu0_physical_addr_a[31] = mcu0_drif_dram_addr_a[3];
3132 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
3133 mcu0_physical_addr_b[31] = mcu0_drif_dram_addr_b[3];
3134 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
3135 mcu0_physical_addr_c[31] = mcu0_drif_dram_addr_c[3];
3136 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
3137 end
3138 100: begin
3139 mcu0_physical_addr_a[32:31] = mcu0_drif_dram_addr_a[4:3];
3140 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
3141 mcu0_physical_addr_b[32:31] = mcu0_drif_dram_addr_b[4:3];
3142 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
3143 mcu0_physical_addr_c[32:31] = mcu0_drif_dram_addr_c[4:3];
3144 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
3145 end
3146 000: begin
3147 mcu0_physical_addr_a[33:31] = mcu0_drif_dram_addr_a[5:3];
3148 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
3149 mcu0_physical_addr_b[33:31] = mcu0_drif_dram_addr_b[5:3];
3150 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
3151 mcu0_physical_addr_c[33:31] = mcu0_drif_dram_addr_c[5:3];
3152 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
3153 end
3154 endcase
3155 end
3156 8'b0_0_1_00_001,
3157 8'b0_0_1_00_010,
3158 8'b0_0_1_00_100,
3159 8'b0_0_1_00_000: begin
3160 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[12:0],
3161 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
3162 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3163 5'b00000};
3164 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[12:0],
3165 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
3166 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3167 5'b00000};
3168 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[12:0],
3169 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
3170 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3171 5'b00000};
3172 case(num_dimms)
3173 001: begin
3174 mcu0_physical_addr_a[31] = mcu0_drif_dram_addr_a[3];
3175 mcu0_physical_addr_a[10] = mcu0_drif_dram_rank_a;
3176 mcu0_physical_addr_b[31] = mcu0_drif_dram_addr_b[3];
3177 mcu0_physical_addr_b[10] = mcu0_drif_dram_rank_b;
3178 mcu0_physical_addr_c[31] = mcu0_drif_dram_addr_c[3];
3179 mcu0_physical_addr_c[10] = mcu0_drif_dram_rank_c;
3180 end
3181 010: begin
3182 mcu0_physical_addr_a[32:31] = mcu0_drif_dram_addr_a[4:3];
3183 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
3184 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
3185 mcu0_physical_addr_b[32:31] = mcu0_drif_dram_addr_b[4:3];
3186 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
3187 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
3188 mcu0_physical_addr_c[32:31] = mcu0_drif_dram_addr_c[4:3];
3189 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
3190 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
3191 end
3192 100: begin
3193 mcu0_physical_addr_a[33:31] = mcu0_drif_dram_addr_a[5:3];
3194 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
3195 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
3196 mcu0_physical_addr_b[33:31] = mcu0_drif_dram_addr_b[5:3];
3197 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
3198 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
3199 mcu0_physical_addr_c[33:31] = mcu0_drif_dram_addr_c[5:3];
3200 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
3201 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
3202 end
3203 000: begin
3204 mcu0_physical_addr_a[34:31] = mcu0_drif_dram_addr_a[6:3];
3205 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
3206 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
3207 mcu0_physical_addr_b[34:31] = mcu0_drif_dram_addr_b[6:3];
3208 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
3209 mcu0_physical_addr_b[13] = mcu0_drif_dram_rank_b;
3210 mcu0_physical_addr_c[34:31] = mcu0_drif_dram_addr_c[6:3];
3211 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
3212 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
3213 end
3214 endcase
3215 end
3216 8'b0_0_0_01_001,
3217 8'b0_0_0_01_010,
3218 8'b0_0_0_01_100,
3219 8'b0_0_0_01_000: begin
3220 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
3221 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
3222 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3223 5'b00000};
3224 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
3225 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
3226 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3227 5'b00000};
3228 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
3229 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
3230 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3231 5'b00000};
3232 case(num_dimms)
3233 001: begin
3234 end
3235 010: begin
3236 mcu0_physical_addr_a[32] = mcu0_drif_dram_addr_a[3];
3237 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
3238 mcu0_physical_addr_b[32] = mcu0_drif_dram_addr_b[3];
3239 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
3240 mcu0_physical_addr_c[32] = mcu0_drif_dram_addr_c[3];
3241 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
3242 end
3243 100: begin
3244 mcu0_physical_addr_a[33:32] = mcu0_drif_dram_addr_a[4:3];
3245 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
3246 mcu0_physical_addr_b[33:32] = mcu0_drif_dram_addr_b[4:3];
3247 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
3248 mcu0_physical_addr_c[33:32] = mcu0_drif_dram_addr_c[4:3];
3249 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
3250 end
3251 000: begin
3252 mcu0_physical_addr_a[34:32] = mcu0_drif_dram_addr_a[5:3];
3253 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
3254 mcu0_physical_addr_b[34:32] = mcu0_drif_dram_addr_b[5:3];
3255 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
3256 mcu0_physical_addr_c[34:32] = mcu0_drif_dram_addr_c[5:3];
3257 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
3258 end
3259 endcase
3260 end
3261 8'b0_0_1_01_001,
3262 8'b0_0_1_01_010,
3263 8'b0_0_1_01_100,
3264 8'b0_0_1_01_000: begin
3265 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
3266 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:3], mcu0_drif_dram_bank_a[1],
3267 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3268 5'b00000};
3269 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
3270 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:3], mcu0_drif_dram_bank_b[1],
3271 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3272 5'b00000};
3273 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
3274 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:3], mcu0_drif_dram_bank_c[1],
3275 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3276 5'b00000};
3277 case(num_dimms)
3278 001: begin
3279 mcu0_physical_addr_a[32] = mcu0_drif_dram_addr_a[3];
3280 mcu0_physical_addr_a[10] = mcu0_drif_dram_rank_a;
3281 mcu0_physical_addr_b[32] = mcu0_drif_dram_addr_b[3];
3282 mcu0_physical_addr_b[10] = mcu0_drif_dram_rank_b;
3283 mcu0_physical_addr_c[32] = mcu0_drif_dram_addr_c[3];
3284 mcu0_physical_addr_c[10] = mcu0_drif_dram_rank_c;
3285 end
3286 010: begin
3287 mcu0_physical_addr_a[33:32] = mcu0_drif_dram_addr_a[4:3];
3288 mcu0_physical_addr_a[10] = mcu0_drif_dram_dimm_a[0];
3289 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
3290 mcu0_physical_addr_b[33:32] = mcu0_drif_dram_addr_b[4:3];
3291 mcu0_physical_addr_b[10] = mcu0_drif_dram_dimm_b[0];
3292 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
3293 mcu0_physical_addr_c[33:32] = mcu0_drif_dram_addr_c[4:3];
3294 mcu0_physical_addr_c[10] = mcu0_drif_dram_dimm_c[0];
3295 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
3296 end
3297 100: begin
3298 mcu0_physical_addr_a[34:32] = mcu0_drif_dram_addr_a[5:3];
3299 mcu0_physical_addr_a[11:10] = mcu0_drif_dram_dimm_a[1:0];
3300 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
3301 mcu0_physical_addr_b[34:32] = mcu0_drif_dram_addr_b[5:3];
3302 mcu0_physical_addr_b[11:10] = mcu0_drif_dram_dimm_b[1:0];
3303 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
3304 mcu0_physical_addr_c[34:32] = mcu0_drif_dram_addr_c[5:3];
3305 mcu0_physical_addr_c[11:10] = mcu0_drif_dram_dimm_c[1:0];
3306 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
3307 end
3308 000: begin
3309 mcu0_physical_addr_a[35:32] = mcu0_drif_dram_addr_a[6:3];
3310 mcu0_physical_addr_a[12:10] = mcu0_drif_dram_dimm_a[2:0];
3311 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
3312 mcu0_physical_addr_b[35:32] = mcu0_drif_dram_addr_b[6:3];
3313 mcu0_physical_addr_b[12:10] = mcu0_drif_dram_dimm_b[2:0];
3314 mcu0_physical_addr_b[13] = mcu0_drif_dram_rank_b;
3315 mcu0_physical_addr_c[35:32] = mcu0_drif_dram_addr_c[6:3];
3316 mcu0_physical_addr_c[12:10] = mcu0_drif_dram_dimm_c[2:0];
3317 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
3318 end
3319 endcase
3320 end
3321 8'b0_0_0_10_001,
3322 8'b0_0_0_10_010,
3323 8'b0_0_0_10_100,
3324 8'b0_0_0_10_000: begin
3325 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
3326 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
3327 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3328 5'b00000};
3329 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
3330 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
3331 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3332 5'b00000};
3333 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
3334 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
3335 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3336 5'b00000};
3337 case(num_dimms)
3338 001: begin
3339 mcu0_physical_addr_a[32] = mcu0_drif_dram_addr_a[3];
3340 mcu0_physical_addr_b[32] = mcu0_drif_dram_addr_b[3];
3341 mcu0_physical_addr_c[32] = mcu0_drif_dram_addr_c[3];
3342 end
3343 010: begin
3344 mcu0_physical_addr_a[33:32] = mcu0_drif_dram_addr_a[4:3];
3345 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
3346 mcu0_physical_addr_b[33:32] = mcu0_drif_dram_addr_b[4:3];
3347 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
3348 mcu0_physical_addr_c[33:32] = mcu0_drif_dram_addr_c[4:3];
3349 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
3350 end
3351 100: begin
3352 mcu0_physical_addr_a[34:32] = mcu0_drif_dram_addr_a[5:3];
3353 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
3354 mcu0_physical_addr_b[34:32] = mcu0_drif_dram_addr_b[5:3];
3355 mcu0_physical_addr_b[12:11] = mcu0_drif_dram_dimm_b[1:0];
3356 mcu0_physical_addr_c[34:32] = mcu0_drif_dram_addr_c[5:3];
3357 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
3358 end
3359 000: begin
3360 mcu0_physical_addr_a[35:32] = mcu0_drif_dram_addr_a[6:3];
3361 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
3362 mcu0_physical_addr_b[35:32] = mcu0_drif_dram_addr_b[6:3];
3363 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
3364 mcu0_physical_addr_c[35:32] = mcu0_drif_dram_addr_c[6:3];
3365 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
3366 end
3367 endcase
3368 end
3369 8'b0_0_1_10_001,
3370 8'b0_0_1_10_010,
3371 8'b0_0_1_10_100,
3372 8'b0_0_1_10_000: begin
3373 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[13:0],
3374 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
3375 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3376 5'b00000};
3377 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[13:0],
3378 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
3379 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3380 5'b00000};
3381 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[13:0],
3382 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
3383 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3384 5'b00000};
3385 case(num_dimms)
3386 001: begin
3387 mcu0_physical_addr_a[33:32] = mcu0_drif_dram_addr_a[4:3];
3388 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
3389 mcu0_physical_addr_b[33:32] = mcu0_drif_dram_addr_b[4:3];
3390 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
3391 mcu0_physical_addr_c[33:32] = mcu0_drif_dram_addr_c[4:3];
3392 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
3393 end
3394 010: begin
3395 mcu0_physical_addr_a[34:32] = mcu0_drif_dram_addr_a[5:3];
3396 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
3397 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
3398 mcu0_physical_addr_b[34:32] = mcu0_drif_dram_addr_b[5:3];
3399 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
3400 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
3401 mcu0_physical_addr_c[34:32] = mcu0_drif_dram_addr_c[5:3];
3402 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
3403 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
3404 end
3405 100: begin
3406 mcu0_physical_addr_a[35:32] = mcu0_drif_dram_addr_a[6:3];
3407 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
3408 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
3409 mcu0_physical_addr_b[35:32] = mcu0_drif_dram_addr_b[6:3];
3410 mcu0_physical_addr_b[12:11] = mcu0_drif_dram_dimm_b[1:0];
3411 mcu0_physical_addr_b[13] = mcu0_drif_dram_rank_b;
3412 mcu0_physical_addr_c[35:32] = mcu0_drif_dram_addr_c[6:3];
3413 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
3414 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
3415 end
3416 000: begin
3417 mcu0_physical_addr_a[36:32] = mcu0_drif_dram_addr_a[7:3];
3418 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
3419 mcu0_physical_addr_a[14] = mcu0_drif_dram_rank_a;
3420 mcu0_physical_addr_b[36:32] = mcu0_drif_dram_addr_b[7:3];
3421 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
3422 mcu0_physical_addr_b[14] = mcu0_drif_dram_rank_b;
3423 mcu0_physical_addr_c[36:32] = mcu0_drif_dram_addr_c[7:3];
3424 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
3425 mcu0_physical_addr_c[14] = mcu0_drif_dram_rank_c;
3426 end
3427 endcase
3428 end
3429 8'b0_0_0_11_001,
3430 8'b0_0_0_11_010,
3431 8'b0_0_0_11_100,
3432 8'b0_0_0_11_000: begin
3433 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[14:0],
3434 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
3435 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3436 5'b00000};
3437 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[14:0],
3438 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
3439 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3440 5'b00000};
3441 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[14:0],
3442 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
3443 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3444 5'b00000};
3445 case(num_dimms)
3446 001: begin
3447 mcu0_physical_addr_a[33] = mcu0_drif_dram_addr_a[3];
3448 mcu0_physical_addr_b[33] = mcu0_drif_dram_addr_b[3];
3449 mcu0_physical_addr_c[33] = mcu0_drif_dram_addr_c[3];
3450 end
3451 010: begin
3452 mcu0_physical_addr_a[34:33] = mcu0_drif_dram_addr_a[4:3];
3453 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
3454 mcu0_physical_addr_b[34:33] = mcu0_drif_dram_addr_b[4:3];
3455 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
3456 mcu0_physical_addr_c[34:33] = mcu0_drif_dram_addr_c[4:3];
3457 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
3458 end
3459 100: begin
3460 mcu0_physical_addr_a[35:33] = mcu0_drif_dram_addr_a[5:3];
3461 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
3462 mcu0_physical_addr_b[35:33] = mcu0_drif_dram_addr_b[5:3];
3463 mcu0_physical_addr_b[12:11] = mcu0_drif_dram_dimm_b[1:0];
3464 mcu0_physical_addr_c[35:33] = mcu0_drif_dram_addr_c[5:3];
3465 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
3466 end
3467 000: begin
3468 mcu0_physical_addr_a[36:33] = mcu0_drif_dram_addr_a[6:3];
3469 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
3470 mcu0_physical_addr_b[36:33] = mcu0_drif_dram_addr_b[6:3];
3471 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
3472 mcu0_physical_addr_c[36:33] = mcu0_drif_dram_addr_c[6:3];
3473 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
3474 end
3475 endcase
3476 end
3477 8'b0_0_1_11_001,
3478 8'b0_0_1_11_010,
3479 8'b0_0_1_11_100,
3480 8'b0_0_1_11_000: begin
3481 mcu0_physical_addr_a = {mcu0_drif_dram_ras_addr_a[14:0],
3482 mcu0_drif_dram_addr_a[11],mcu0_drif_dram_addr_a[9:4], mcu0_drif_dram_bank_a[2:1],
3483 2'b00, mcu0_drif_dram_bank_a[0], mcu0_drif_dram_addr_a[2],
3484 5'b00000};
3485 mcu0_physical_addr_b = {mcu0_drif_dram_ras_addr_b[14:0],
3486 mcu0_drif_dram_addr_b[11],mcu0_drif_dram_addr_b[9:4], mcu0_drif_dram_bank_b[2:1],
3487 2'b00, mcu0_drif_dram_bank_b[0], mcu0_drif_dram_addr_b[2],
3488 5'b00000};
3489 mcu0_physical_addr_c = {mcu0_drif_dram_ras_addr_c[14:0],
3490 mcu0_drif_dram_addr_c[11],mcu0_drif_dram_addr_c[9:4], mcu0_drif_dram_bank_c[2:1],
3491 2'b00, mcu0_drif_dram_bank_c[0], mcu0_drif_dram_addr_c[2],
3492 5'b00000};
3493 case(num_dimms)
3494 001: begin
3495 mcu0_physical_addr_a[34:33] = mcu0_drif_dram_addr_a[4:3];
3496 mcu0_physical_addr_a[11] = mcu0_drif_dram_rank_a;
3497 mcu0_physical_addr_b[34:33] = mcu0_drif_dram_addr_b[4:3];
3498 mcu0_physical_addr_b[11] = mcu0_drif_dram_rank_b;
3499 mcu0_physical_addr_c[34:33] = mcu0_drif_dram_addr_c[4:3];
3500 mcu0_physical_addr_c[11] = mcu0_drif_dram_rank_c;
3501 end
3502 010: begin
3503 mcu0_physical_addr_a[35:33] = mcu0_drif_dram_addr_a[5:3];
3504 mcu0_physical_addr_a[11] = mcu0_drif_dram_dimm_a[0];
3505 mcu0_physical_addr_a[12] = mcu0_drif_dram_rank_a;
3506 mcu0_physical_addr_b[35:33] = mcu0_drif_dram_addr_b[5:3];
3507 mcu0_physical_addr_b[11] = mcu0_drif_dram_dimm_b[0];
3508 mcu0_physical_addr_b[12] = mcu0_drif_dram_rank_b;
3509 mcu0_physical_addr_c[35:33] = mcu0_drif_dram_addr_c[5:3];
3510 mcu0_physical_addr_c[11] = mcu0_drif_dram_dimm_c[0];
3511 mcu0_physical_addr_c[12] = mcu0_drif_dram_rank_c;
3512 end
3513 100: begin
3514 mcu0_physical_addr_a[36:33] = mcu0_drif_dram_addr_a[6:3];
3515 mcu0_physical_addr_a[12:11] = mcu0_drif_dram_dimm_a[1:0];
3516 mcu0_physical_addr_a[13] = mcu0_drif_dram_rank_a;
3517 mcu0_physical_addr_b[36:33] = mcu0_drif_dram_addr_b[6:3];
3518 mcu0_physical_addr_b[12:11] = mcu0_drif_dram_dimm_b[1:0];
3519 mcu0_physical_addr_b[13] = mcu0_drif_dram_rank_b;
3520 mcu0_physical_addr_c[36:33] = mcu0_drif_dram_addr_c[6:3];
3521 mcu0_physical_addr_c[12:11] = mcu0_drif_dram_dimm_c[1:0];
3522 mcu0_physical_addr_c[13] = mcu0_drif_dram_rank_c;
3523 end
3524 000: begin
3525 mcu0_physical_addr_a[37:33] = mcu0_drif_dram_addr_a[7:3];
3526 mcu0_physical_addr_a[13:11] = mcu0_drif_dram_dimm_a[2:0];
3527 mcu0_physical_addr_a[14] = mcu0_drif_dram_rank_a;
3528 mcu0_physical_addr_b[37:33] = mcu0_drif_dram_addr_b[7:3];
3529 mcu0_physical_addr_b[13:11] = mcu0_drif_dram_dimm_b[2:0];
3530 mcu0_physical_addr_b[14] = mcu0_drif_dram_rank_b;
3531 mcu0_physical_addr_c[37:33] = mcu0_drif_dram_addr_c[7:3];
3532 mcu0_physical_addr_c[13:11] = mcu0_drif_dram_dimm_c[2:0];
3533 mcu0_physical_addr_c[14] = mcu0_drif_dram_rank_c;
3534 end
3535 endcase
3536 end
3537 endcase
3538
3539 //----------------------------------------------------------------------------------------------
3540 // M C U 1 - phys addr gen
3541 //----------------------------------------------------------------------------------------------
3542
3543
3544 mcu1_physical_addr_a = 40'b0;
3545 mcu1_physical_addr_b = 40'b0;
3546 mcu1_physical_addr_c = 40'b0;
3547
3548 case({chnl_type, rank_addr, rank, dimm_size, num_dimms})
3549
3550 //-------------------------------
3551 // DUAL CHANNEL, RANK HIGH
3552 //-------------------------------
3553
3554 8'b1_1_0_00_001,
3555 8'b1_1_0_00_010,
3556 8'b1_1_0_00_100,
3557 8'b1_1_0_00_000: begin
3558 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[12:0],
3559 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2],
3560 mcu1_drif_dram_bank_a[1], 2'b01, mcu1_drif_dram_bank_a[0],
3561 mcu1_drif_dram_addr_a[1], 5'b00000};
3562 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[12:0],
3563 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2],
3564 mcu1_drif_dram_bank_b[1], 2'b01, mcu1_drif_dram_bank_b[0],
3565 mcu1_drif_dram_addr_b[1], 5'b00000};
3566 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[12:0],
3567 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2],
3568 mcu1_drif_dram_bank_c[1], 2'b01, mcu1_drif_dram_bank_c[0],
3569 mcu1_drif_dram_addr_c[1], 5'b00000};
3570 end
3571 8'b1_1_1_00_001,
3572 8'b1_1_1_00_010,
3573 8'b1_1_1_00_100,
3574 8'b1_1_1_00_000: begin
3575 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[12:0],
3576 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2],
3577 mcu1_drif_dram_bank_a[1], 2'b01, mcu1_drif_dram_bank_a[0],
3578 mcu1_drif_dram_addr_a[1], 5'b00000};
3579 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[12:0],
3580 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2],
3581 mcu1_drif_dram_bank_b[1], 2'b01, mcu1_drif_dram_bank_b[0],
3582 mcu1_drif_dram_addr_b[1], 5'b00000};
3583 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[12:0],
3584 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2],
3585 mcu1_drif_dram_bank_c[1], 2'b01, mcu1_drif_dram_bank_c[0],
3586 mcu1_drif_dram_addr_c[1], 5'b00000};
3587 case(num_dimms)
3588 001: begin
3589 mcu1_physical_addr_a[32] = mcu1_drif_dram_rank_a;
3590 mcu1_physical_addr_b[32] = mcu1_drif_dram_rank_b;
3591 mcu1_physical_addr_c[32] = mcu1_drif_dram_rank_c;
3592 end
3593 010: begin
3594 mcu1_physical_addr_a[33] = mcu1_drif_dram_rank_a;
3595 mcu1_physical_addr_b[33] = mcu1_drif_dram_rank_b;
3596 mcu1_physical_addr_c[33] = mcu1_drif_dram_rank_c;
3597 end
3598 100: begin
3599 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3600 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
3601 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
3602 end
3603 000: begin
3604 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
3605 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
3606 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
3607 end
3608 endcase
3609 end
3610 8'b1_1_0_01_001,
3611 8'b1_1_0_01_010,
3612 8'b1_1_0_01_100,
3613 8'b1_1_0_01_000: begin
3614 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[13:0],
3615 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2],
3616 mcu1_drif_dram_bank_a[1], 2'b01, mcu1_drif_dram_bank_a[0],
3617 mcu1_drif_dram_addr_a[1], 5'b00000};
3618 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[13:0],
3619 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2],
3620 mcu1_drif_dram_bank_b[1], 2'b01, mcu1_drif_dram_bank_b[0],
3621 mcu1_drif_dram_addr_b[1], 5'b00000};
3622 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[13:0],
3623 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2],
3624 mcu1_drif_dram_bank_c[1], 2'b01, mcu1_drif_dram_bank_c[0],
3625 mcu1_drif_dram_addr_c[1], 5'b00000};
3626 end
3627 8'b1_1_1_01_001,
3628 8'b1_1_1_01_010,
3629 8'b1_1_1_01_100,
3630 8'b1_1_1_01_000: begin
3631 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[13:0],
3632 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2],
3633 mcu1_drif_dram_bank_a[1], 2'b01, mcu1_drif_dram_bank_a[0],
3634 mcu1_drif_dram_addr_a[1], 5'b00000};
3635 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[13:0],
3636 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2],
3637 mcu1_drif_dram_bank_b[1], 2'b01, mcu1_drif_dram_bank_b[0],
3638 mcu1_drif_dram_addr_b[1], 5'b00000};
3639 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[13:0],
3640 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2],
3641 mcu1_drif_dram_bank_c[1], 2'b01, mcu1_drif_dram_bank_c[0],
3642 mcu1_drif_dram_addr_c[1], 5'b00000};
3643 case(num_dimms)
3644 001: begin
3645 mcu1_physical_addr_a[33] = mcu1_drif_dram_rank_a;
3646 mcu1_physical_addr_b[33] = mcu1_drif_dram_rank_b;
3647 mcu1_physical_addr_c[33] = mcu1_drif_dram_rank_c;
3648 end
3649 010: begin
3650 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3651 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
3652 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
3653 end
3654 100: begin
3655 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
3656 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
3657 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
3658 end
3659 000: begin
3660 mcu1_physical_addr_a[36] = mcu1_drif_dram_rank_a;
3661 mcu1_physical_addr_b[36] = mcu1_drif_dram_rank_b;
3662 mcu1_physical_addr_c[36] = mcu1_drif_dram_rank_c;
3663 end
3664 endcase
3665 end
3666 8'b1_1_0_10_001,
3667 8'b1_1_0_10_010,
3668 8'b1_1_0_10_100,
3669 8'b1_1_0_10_000: begin
3670 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[2],
3671 mcu1_drif_dram_ras_addr_a[13:0], mcu1_drif_dram_addr_a[11],
3672 mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[2:1],
3673 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1], 5'b00000};
3674 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[2],
3675 mcu1_drif_dram_ras_addr_b[13:0], mcu1_drif_dram_addr_b[11],
3676 mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[2:1],
3677 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1], 5'b00000};
3678 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[2],
3679 mcu1_drif_dram_ras_addr_c[13:0], mcu1_drif_dram_addr_c[11],
3680 mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[2:1],
3681 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1], 5'b00000};
3682 end
3683 8'b1_1_1_10_001,
3684 8'b1_1_1_10_010,
3685 8'b1_1_1_10_100,
3686 8'b1_1_1_10_000: begin
3687 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[2],
3688 mcu1_drif_dram_ras_addr_a[13:0], mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3],
3689 mcu1_drif_dram_bank_a[2:1], 2'b01, mcu1_drif_dram_bank_a[0],
3690 mcu1_drif_dram_addr_a[1], 5'b00000};
3691 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[2],
3692 mcu1_drif_dram_ras_addr_b[13:0], mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3],
3693 mcu1_drif_dram_bank_b[2:1], 2'b01, mcu1_drif_dram_bank_b[0],
3694 mcu1_drif_dram_addr_b[1], 5'b00000};
3695 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[2],
3696 mcu1_drif_dram_ras_addr_c[13:0], mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3],
3697 mcu1_drif_dram_bank_c[2:1], 2'b01, mcu1_drif_dram_bank_c[0],
3698 mcu1_drif_dram_addr_c[1], 5'b00000};
3699 case(num_dimms)
3700 001: begin
3701 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3702 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
3703 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
3704 end
3705 010: begin
3706 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
3707 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
3708 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
3709 end
3710 100: begin
3711 mcu1_physical_addr_a[36] = mcu1_drif_dram_rank_a;
3712 mcu1_physical_addr_b[36] = mcu1_drif_dram_rank_b;
3713 mcu1_physical_addr_c[36] = mcu1_drif_dram_rank_c;
3714 end
3715 000: begin
3716 mcu1_physical_addr_a[37] = mcu1_drif_dram_rank_a;
3717 mcu1_physical_addr_b[37] = mcu1_drif_dram_rank_b;
3718 mcu1_physical_addr_c[37] = mcu1_drif_dram_rank_c;
3719 end
3720 endcase
3721 end
3722 8'b1_1_0_11_001,
3723 8'b1_1_0_11_010,
3724 8'b1_1_0_11_100,
3725 8'b1_1_0_11_000: begin
3726 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[2],
3727 mcu1_drif_dram_ras_addr_a[14:0], mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3],
3728 mcu1_drif_dram_bank_a[2:1], 2'b01, mcu1_drif_dram_bank_a[0],
3729 mcu1_drif_dram_addr_a[1], 5'b00000};
3730 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[2],
3731 mcu1_drif_dram_ras_addr_b[14:0], mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3],
3732 mcu1_drif_dram_bank_b[2:1], 2'b01, mcu1_drif_dram_bank_b[0],
3733 mcu1_drif_dram_addr_b[1], 5'b00000};
3734 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[2],
3735 mcu1_drif_dram_ras_addr_c[14:0], mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3],
3736 mcu1_drif_dram_bank_c[2:1], 2'b01, mcu1_drif_dram_bank_c[0],
3737 mcu1_drif_dram_addr_c[1], 5'b00000};
3738 end
3739 8'b1_1_1_11_001,
3740 8'b1_1_1_11_010,
3741 8'b1_1_1_11_100,
3742 8'b1_1_1_11_000: begin
3743 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[2],
3744 mcu1_drif_dram_ras_addr_a[14:0], mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3],
3745 mcu1_drif_dram_bank_a[2:1], 2'b01, mcu1_drif_dram_bank_a[0],
3746 mcu1_drif_dram_addr_a[1], 5'b00000};
3747 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[2],
3748 mcu1_drif_dram_ras_addr_b[14:0], mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3],
3749 mcu1_drif_dram_bank_b[2:1], 2'b01, mcu1_drif_dram_bank_b[0],
3750 mcu1_drif_dram_addr_b[1], 5'b00000};
3751 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[2],
3752 mcu1_drif_dram_ras_addr_c[14:0], mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3],
3753 mcu1_drif_dram_bank_c[2:1], 2'b01, mcu1_drif_dram_bank_c[0],
3754 mcu1_drif_dram_addr_c[1], 5'b00000};
3755 case(num_dimms)
3756 001: begin
3757 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
3758 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
3759 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
3760 end
3761 010: begin
3762 mcu1_physical_addr_a[36] = mcu1_drif_dram_rank_a;
3763 mcu1_physical_addr_b[36] = mcu1_drif_dram_rank_b;
3764 mcu1_physical_addr_c[36] = mcu1_drif_dram_rank_c;
3765 end
3766 100: begin
3767 mcu1_physical_addr_a[37] = mcu1_drif_dram_rank_a;
3768 mcu1_physical_addr_b[37] = mcu1_drif_dram_rank_b;
3769 mcu1_physical_addr_c[37] = mcu1_drif_dram_rank_c;
3770 end
3771 000: begin
3772 mcu1_physical_addr_a[38] = mcu1_drif_dram_rank_a;
3773 mcu1_physical_addr_b[38] = mcu1_drif_dram_rank_b;
3774 mcu1_physical_addr_c[38] = mcu1_drif_dram_rank_c;
3775 end
3776 endcase
3777 end
3778
3779 //---------------------------
3780 // SINGLE CHANNEL, RANK HIGH
3781 //---------------------------
3782
3783 8'b0_1_0_00_001,
3784 8'b0_1_0_00_010,
3785 8'b0_1_0_00_100,
3786 8'b0_1_0_00_000: begin
3787 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[12:0],
3788 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
3789 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3790 5'b00000};
3791 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[12:0],
3792 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
3793 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3794 5'b00000};
3795 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[12:0],
3796 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
3797 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3798 5'b00000};
3799 end
3800 8'b0_1_1_00_001,
3801 8'b0_1_1_00_010,
3802 8'b0_1_1_00_100,
3803 8'b0_1_1_00_000: begin
3804 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[12:0],
3805 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
3806 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3807 5'b00000};
3808 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[12:0],
3809 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
3810 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3811 5'b00000};
3812 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[12:0],
3813 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
3814 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3815 5'b00000};
3816 case(num_dimms)
3817 001: begin
3818 mcu1_physical_addr_a[31] = mcu1_drif_dram_rank_a;
3819 mcu1_physical_addr_b[31] = mcu1_drif_dram_rank_b;
3820 mcu1_physical_addr_c[31] = mcu1_drif_dram_rank_c;
3821 end
3822 010: begin
3823 mcu1_physical_addr_a[32] = mcu1_drif_dram_rank_a;
3824 mcu1_physical_addr_b[32] = mcu1_drif_dram_rank_b;
3825 mcu1_physical_addr_c[32] = mcu1_drif_dram_rank_c;
3826 end
3827 100: begin
3828 mcu1_physical_addr_a[33] = mcu1_drif_dram_rank_a;
3829 mcu1_physical_addr_b[33] = mcu1_drif_dram_rank_b;
3830 mcu1_physical_addr_c[33] = mcu1_drif_dram_rank_c;
3831 end
3832 000: begin
3833 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3834 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
3835 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
3836 end
3837 endcase
3838 end
3839 8'b0_1_0_01_001,
3840 8'b0_1_0_01_010,
3841 8'b0_1_0_01_100,
3842 8'b0_1_0_01_000: begin
3843 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[13:0],
3844 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
3845 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3846 5'b00000};
3847 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[13:0],
3848 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
3849 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3850 5'b00000};
3851 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[13:0],
3852 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
3853 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3854 5'b00000};
3855 end
3856 8'b0_1_1_01_001,
3857 8'b0_1_1_01_010,
3858 8'b0_1_1_01_100,
3859 8'b0_1_1_01_000: begin
3860 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_ras_addr_a[13:0],
3861 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
3862 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3863 5'b00000};
3864 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_ras_addr_b[13:0],
3865 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
3866 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3867 5'b00000};
3868 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_ras_addr_c[13:0],
3869 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
3870 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3871 5'b00000};
3872 case(num_dimms)
3873 001: begin
3874 mcu1_physical_addr_a[32] = mcu1_drif_dram_rank_a;
3875 mcu1_physical_addr_b[32] = mcu1_drif_dram_rank_b;
3876 mcu1_physical_addr_c[32] = mcu1_drif_dram_rank_c;
3877 end
3878 010: begin
3879 mcu1_physical_addr_a[33] = mcu1_drif_dram_rank_a;
3880 mcu1_physical_addr_b[33] = mcu1_drif_dram_rank_b;
3881 mcu1_physical_addr_c[33] = mcu1_drif_dram_rank_c;
3882 end
3883 100: begin
3884 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3885 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
3886 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
3887 end
3888 000: begin
3889 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
3890 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
3891 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
3892 end
3893 endcase
3894 end
3895 8'b0_1_0_10_001,
3896 8'b0_1_0_10_010,
3897 8'b0_1_0_10_100,
3898 8'b0_1_0_10_000: begin
3899 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[3],
3900 mcu1_drif_dram_ras_addr_a[13:0],
3901 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
3902 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3903 5'b00000};
3904 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[3],
3905 mcu1_drif_dram_ras_addr_b[13:0],
3906 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
3907 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3908 5'b00000};
3909 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[3],
3910 mcu1_drif_dram_ras_addr_c[13:0],
3911 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
3912 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3913 5'b00000};
3914 end
3915 8'b0_1_1_10_001,
3916 8'b0_1_1_10_010,
3917 8'b0_1_1_10_100,
3918 8'b0_1_1_10_000: begin
3919 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[3],
3920 mcu1_drif_dram_ras_addr_a[13:0],
3921 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
3922 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3923 5'b00000};
3924 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[3],
3925 mcu1_drif_dram_ras_addr_b[13:0],
3926 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
3927 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3928 5'b00000};
3929 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[3],
3930 mcu1_drif_dram_ras_addr_c[13:0],
3931 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
3932 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3933 5'b00000};
3934 case(num_dimms)
3935 001: begin
3936 mcu1_physical_addr_a[33] = mcu1_drif_dram_rank_a;
3937 mcu1_physical_addr_b[33] = mcu1_drif_dram_rank_b;
3938 mcu1_physical_addr_c[33] = mcu1_drif_dram_rank_c;
3939 end
3940 010: begin
3941 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3942 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
3943 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
3944 end
3945 100: begin
3946 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
3947 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
3948 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
3949 end
3950 000: begin
3951 mcu1_physical_addr_a[36] = mcu1_drif_dram_rank_a;
3952 mcu1_physical_addr_b[36] = mcu1_drif_dram_rank_b;
3953 mcu1_physical_addr_c[36] = mcu1_drif_dram_rank_c;
3954 end
3955 endcase
3956 end
3957 8'b0_1_0_11_001,
3958 8'b0_1_0_11_010,
3959 8'b0_1_0_11_100,
3960 8'b0_1_0_11_000: begin
3961 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[3],
3962 mcu1_drif_dram_ras_addr_a[14:0],
3963 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
3964 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3965 5'b00000};
3966 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[3],
3967 mcu1_drif_dram_ras_addr_b[14:0],
3968 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
3969 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3970 5'b00000};
3971 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[3],
3972 mcu1_drif_dram_ras_addr_c[14:0],
3973 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
3974 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3975 5'b00000};
3976 end
3977 8'b0_1_1_11_001,
3978 8'b0_1_1_11_010,
3979 8'b0_1_1_11_100,
3980 8'b0_1_1_11_000: begin
3981 mcu1_physical_addr_a = {mcu1_drif_dram_dimm_a, mcu1_drif_dram_addr_a[3],
3982 mcu1_drif_dram_ras_addr_a[14:0],
3983 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
3984 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
3985 5'b00000};
3986 mcu1_physical_addr_b = {mcu1_drif_dram_dimm_b, mcu1_drif_dram_addr_b[3],
3987 mcu1_drif_dram_ras_addr_b[14:0],
3988 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
3989 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
3990 5'b00000};
3991 mcu1_physical_addr_c = {mcu1_drif_dram_dimm_c, mcu1_drif_dram_addr_c[3],
3992 mcu1_drif_dram_ras_addr_c[14:0],
3993 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
3994 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
3995 5'b00000};
3996 case(num_dimms)
3997 001: begin
3998 mcu1_physical_addr_a[34] = mcu1_drif_dram_rank_a;
3999 mcu1_physical_addr_b[34] = mcu1_drif_dram_rank_b;
4000 mcu1_physical_addr_c[34] = mcu1_drif_dram_rank_c;
4001 end
4002 010: begin
4003 mcu1_physical_addr_a[35] = mcu1_drif_dram_rank_a;
4004 mcu1_physical_addr_b[35] = mcu1_drif_dram_rank_b;
4005 mcu1_physical_addr_c[35] = mcu1_drif_dram_rank_c;
4006 end
4007 100: begin
4008 mcu1_physical_addr_a[36] = mcu1_drif_dram_rank_a;
4009 mcu1_physical_addr_b[36] = mcu1_drif_dram_rank_b;
4010 mcu1_physical_addr_c[36] = mcu1_drif_dram_rank_c;
4011 end
4012 000: begin
4013 mcu1_physical_addr_a[37] = mcu1_drif_dram_rank_a;
4014 mcu1_physical_addr_b[37] = mcu1_drif_dram_rank_b;
4015 mcu1_physical_addr_c[37] = mcu1_drif_dram_rank_c;
4016 end
4017 endcase
4018 end
4019
4020 //---------------------------
4021 // DUAL CHANNEL, RANK LOW
4022 //---------------------------
4023
4024 8'b1_0_0_00_001,
4025 8'b1_0_0_00_010,
4026 8'b1_0_0_00_100,
4027 8'b1_0_0_00_000: begin
4028 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[12:0],
4029 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2], mcu1_drif_dram_bank_a[1],
4030 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4031 5'b00000};
4032 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[12:0],
4033 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2], mcu1_drif_dram_bank_b[1],
4034 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4035 5'b00000};
4036 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[12:0],
4037 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2], mcu1_drif_dram_bank_c[1],
4038 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4039 5'b00000};
4040 case(num_dimms)
4041 001: begin
4042 end
4043 010: begin
4044 mcu1_physical_addr_a[32] = mcu1_drif_dram_addr_a[2];
4045 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4046 mcu1_physical_addr_b[32] = mcu1_drif_dram_addr_b[2];
4047 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4048 mcu1_physical_addr_c[32] = mcu1_drif_dram_addr_c[2];
4049 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4050 end
4051 100: begin
4052 mcu1_physical_addr_a[33:32] = mcu1_drif_dram_addr_a[3:2];
4053 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4054 mcu1_physical_addr_b[33:32] = mcu1_drif_dram_addr_b[3:2];
4055 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4056 mcu1_physical_addr_c[33:32] = mcu1_drif_dram_addr_c[3:2];
4057 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4058 end
4059 000: begin
4060 mcu1_physical_addr_a[34:32] = mcu1_drif_dram_addr_a[4:2];
4061 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4062 mcu1_physical_addr_b[34:32] = mcu1_drif_dram_addr_b[4:2];
4063 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4064 mcu1_physical_addr_c[34:32] = mcu1_drif_dram_addr_c[4:2];
4065 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4066 end
4067 endcase
4068 end
4069 8'b1_0_1_00_001,
4070 8'b1_0_1_00_010,
4071 8'b1_0_1_00_100,
4072 8'b1_0_1_00_000: begin
4073 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[12:0],
4074 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2], mcu1_drif_dram_bank_a[1],
4075 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4076 5'b00000};
4077 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[12:0],
4078 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2], mcu1_drif_dram_bank_b[1],
4079 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4080 5'b00000};
4081 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[12:0],
4082 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2], mcu1_drif_dram_bank_c[1],
4083 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4084 5'b00000};
4085 case(num_dimms)
4086 001: begin
4087 mcu1_physical_addr_a[32] = mcu1_drif_dram_addr_a[2];
4088 mcu1_physical_addr_a[10] = mcu1_drif_dram_rank_a;
4089 mcu1_physical_addr_b[32] = mcu1_drif_dram_addr_b[2];
4090 mcu1_physical_addr_b[10] = mcu1_drif_dram_rank_b;
4091 mcu1_physical_addr_c[32] = mcu1_drif_dram_addr_c[2];
4092 mcu1_physical_addr_c[10] = mcu1_drif_dram_rank_c;
4093 end
4094 010: begin
4095 mcu1_physical_addr_a[33:32] = mcu1_drif_dram_addr_a[3:2];
4096 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4097 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4098 mcu1_physical_addr_b[33:32] = mcu1_drif_dram_addr_b[3:2];
4099 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4100 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4101 mcu1_physical_addr_c[33:32] = mcu1_drif_dram_addr_c[3:2];
4102 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4103 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4104 end
4105 100: begin
4106 mcu1_physical_addr_a[34:32] = mcu1_drif_dram_addr_a[4:2];
4107 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4108 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4109 mcu1_physical_addr_b[34:32] = mcu1_drif_dram_addr_b[4:2];
4110 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4111 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4112 mcu1_physical_addr_c[34:32] = mcu1_drif_dram_addr_c[4:2];
4113 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4114 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4115 end
4116 000: begin
4117 mcu1_physical_addr_a[35:32] = mcu1_drif_dram_addr_a[5:2];
4118 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4119 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4120 mcu1_physical_addr_b[35:32] = mcu1_drif_dram_addr_b[5:2];
4121 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4122 mcu1_physical_addr_b[13] = mcu1_drif_dram_rank_b;
4123 mcu1_physical_addr_c[35:32] = mcu1_drif_dram_addr_c[5:2];
4124 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4125 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4126 end
4127 endcase
4128 end
4129 8'b1_0_0_01_001,
4130 8'b1_0_0_01_010,
4131 8'b1_0_0_01_100,
4132 8'b1_0_0_01_000: begin
4133 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4134 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2], mcu1_drif_dram_bank_a[1],
4135 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4136 5'b00000};
4137 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4138 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2], mcu1_drif_dram_bank_b[1],
4139 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4140 5'b00000};
4141 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4142 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2], mcu1_drif_dram_bank_c[1],
4143 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4144 5'b00000};
4145 case(num_dimms)
4146 001: begin
4147 end
4148 010: begin
4149 mcu1_physical_addr_a[33] = mcu1_drif_dram_addr_a[2];
4150 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4151 mcu1_physical_addr_b[33] = mcu1_drif_dram_addr_b[2];
4152 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4153 mcu1_physical_addr_c[33] = mcu1_drif_dram_addr_c[2];
4154 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4155 end
4156 100: begin
4157 mcu1_physical_addr_a[34:33] = mcu1_drif_dram_addr_a[3:2];
4158 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4159 mcu1_physical_addr_b[34:33] = mcu1_drif_dram_addr_b[3:2];
4160 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4161 mcu1_physical_addr_c[34:33] = mcu1_drif_dram_addr_c[3:2];
4162 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4163 end
4164 000: begin
4165 mcu1_physical_addr_a[35:33] = mcu1_drif_dram_addr_a[4:2];
4166 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4167 mcu1_physical_addr_b[35:33] = mcu1_drif_dram_addr_b[4:2];
4168 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4169 mcu1_physical_addr_c[35:33] = mcu1_drif_dram_addr_c[4:2];
4170 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4171 end
4172 endcase
4173 end
4174 8'b1_0_1_01_001,
4175 8'b1_0_1_01_010,
4176 8'b1_0_1_01_100,
4177 8'b1_0_1_01_000: begin
4178 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4179 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2], mcu1_drif_dram_bank_a[1],
4180 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4181 5'b00000};
4182 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4183 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2], mcu1_drif_dram_bank_b[1],
4184 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4185 5'b00000};
4186 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4187 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2], mcu1_drif_dram_bank_c[1],
4188 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4189 5'b00000};
4190 case(num_dimms)
4191 001: begin
4192 mcu1_physical_addr_a[33] = mcu1_drif_dram_addr_a[2];
4193 mcu1_physical_addr_a[10] = mcu1_drif_dram_rank_a;
4194 mcu1_physical_addr_b[33] = mcu1_drif_dram_addr_b[2];
4195 mcu1_physical_addr_b[10] = mcu1_drif_dram_rank_b;
4196 mcu1_physical_addr_c[33] = mcu1_drif_dram_addr_c[2];
4197 mcu1_physical_addr_c[10] = mcu1_drif_dram_rank_c;
4198 end
4199 010: begin
4200 mcu1_physical_addr_a[34:33] = mcu1_drif_dram_addr_a[3:2];
4201 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4202 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4203 mcu1_physical_addr_b[34:33] = mcu1_drif_dram_addr_b[3:2];
4204 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4205 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4206 mcu1_physical_addr_c[34:33] = mcu1_drif_dram_addr_c[3:2];
4207 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4208 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4209 end
4210 100: begin
4211 mcu1_physical_addr_a[35:33] = mcu1_drif_dram_addr_a[4:2];
4212 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4213 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4214 mcu1_physical_addr_b[35:33] = mcu1_drif_dram_addr_b[4:2];
4215 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4216 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4217 mcu1_physical_addr_c[35:33] = mcu1_drif_dram_addr_c[4:2];
4218 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4219 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4220 end
4221 000: begin
4222 mcu1_physical_addr_a[36:33] = mcu1_drif_dram_addr_a[5:2];
4223 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4224 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4225 mcu1_physical_addr_b[36:33] = mcu1_drif_dram_addr_b[5:2];
4226 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4227 mcu1_physical_addr_b[13] = mcu1_drif_dram_rank_b;
4228 mcu1_physical_addr_c[36:33] = mcu1_drif_dram_addr_c[5:2];
4229 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4230 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4231 end
4232 endcase
4233 end
4234 8'b1_0_0_10_001,
4235 8'b1_0_0_10_010,
4236 8'b1_0_0_10_100,
4237 8'b1_0_0_10_000: begin
4238 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4239 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[2:1],
4240 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4241 5'b00000};
4242 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4243 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[2:1],
4244 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4245 5'b00000};
4246 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4247 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[2:1],
4248 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4249 5'b00000};
4250 case(num_dimms)
4251 001: begin
4252 mcu1_physical_addr_a[33] = mcu1_drif_dram_addr_a[2];
4253 mcu1_physical_addr_b[33] = mcu1_drif_dram_addr_b[2];
4254 mcu1_physical_addr_c[33] = mcu1_drif_dram_addr_c[2];
4255 end
4256 010: begin
4257 mcu1_physical_addr_a[34:33] = mcu1_drif_dram_addr_a[3:2];
4258 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4259 mcu1_physical_addr_b[34:33] = mcu1_drif_dram_addr_b[3:2];
4260 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4261 mcu1_physical_addr_c[34:33] = mcu1_drif_dram_addr_c[3:2];
4262 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4263 end
4264 100: begin
4265 mcu1_physical_addr_a[35:33] = mcu1_drif_dram_addr_a[4:2];
4266 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4267 mcu1_physical_addr_b[35:33] = mcu1_drif_dram_addr_b[4:2];
4268 mcu1_physical_addr_b[12:11] = mcu1_drif_dram_dimm_b[1:0];
4269 mcu1_physical_addr_c[35:33] = mcu1_drif_dram_addr_c[4:2];
4270 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4271 end
4272 000: begin
4273 mcu1_physical_addr_a[36:33] = mcu1_drif_dram_addr_a[5:2];
4274 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4275 mcu1_physical_addr_b[36:33] = mcu1_drif_dram_addr_b[5:2];
4276 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4277 mcu1_physical_addr_c[36:33] = mcu1_drif_dram_addr_c[5:2];
4278 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4279 end
4280 endcase
4281 end
4282 8'b1_0_1_10_001,
4283 8'b1_0_1_10_010,
4284 8'b1_0_1_10_100,
4285 8'b1_0_1_10_000: begin
4286 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4287 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2], mcu1_drif_dram_bank_a[1],
4288 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4289 5'b00000};
4290 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4291 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2], mcu1_drif_dram_bank_b[1],
4292 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4293 5'b00000};
4294 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4295 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2], mcu1_drif_dram_bank_c[1],
4296 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4297 5'b00000};
4298 case(num_dimms)
4299 001: begin
4300 mcu1_physical_addr_a[34:33] = mcu1_drif_dram_addr_a[3:2];
4301 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4302 mcu1_physical_addr_b[34:33] = mcu1_drif_dram_addr_b[3:2];
4303 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4304 mcu1_physical_addr_c[34:33] = mcu1_drif_dram_addr_c[3:2];
4305 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4306 end
4307 010: begin
4308 mcu1_physical_addr_a[35:33] = mcu1_drif_dram_addr_a[4:2];
4309 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4310 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4311 mcu1_physical_addr_b[35:33] = mcu1_drif_dram_addr_b[4:2];
4312 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4313 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4314 mcu1_physical_addr_c[35:33] = mcu1_drif_dram_addr_c[4:2];
4315 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4316 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4317 end
4318 100: begin
4319 mcu1_physical_addr_a[36:33] = mcu1_drif_dram_addr_a[5:2];
4320 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4321 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4322 mcu1_physical_addr_b[36:33] = mcu1_drif_dram_addr_b[5:2];
4323 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[1:0];
4324 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4325 mcu1_physical_addr_c[36:33] = mcu1_drif_dram_addr_c[5:2];
4326 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4327 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4328 end
4329 000: begin
4330 mcu1_physical_addr_a[37:33] = mcu1_drif_dram_addr_a[5:2];
4331 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4332 mcu1_physical_addr_a[14] = mcu1_drif_dram_rank_a;
4333 mcu1_physical_addr_b[37:33] = mcu1_drif_dram_addr_b[5:2];
4334 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4335 mcu1_physical_addr_b[14] = mcu1_drif_dram_rank_b;
4336 mcu1_physical_addr_c[37:33] = mcu1_drif_dram_addr_c[5:2];
4337 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4338 mcu1_physical_addr_c[14] = mcu1_drif_dram_rank_c;
4339 end
4340 endcase
4341 end
4342 8'b1_0_0_11_001,
4343 8'b1_0_0_11_010,
4344 8'b1_0_0_11_100,
4345 8'b1_0_0_11_000: begin
4346 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[14:0],
4347 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[2:1],
4348 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4349 5'b00000};
4350 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[14:0],
4351 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[2:1],
4352 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4353 5'b00000};
4354 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[14:0],
4355 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[2:1],
4356 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4357 5'b00000};
4358 case(num_dimms)
4359 001: begin
4360 mcu1_physical_addr_a[34] = mcu1_drif_dram_addr_a[2];
4361 mcu1_physical_addr_b[34] = mcu1_drif_dram_addr_b[2];
4362 mcu1_physical_addr_c[34] = mcu1_drif_dram_addr_c[2];
4363 end
4364 010: begin
4365 mcu1_physical_addr_a[35:34] = mcu1_drif_dram_addr_a[3:2];
4366 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4367 mcu1_physical_addr_b[35:34] = mcu1_drif_dram_addr_b[3:2];
4368 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4369 mcu1_physical_addr_c[35:34] = mcu1_drif_dram_addr_c[3:2];
4370 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4371 end
4372 100: begin
4373 mcu1_physical_addr_a[36:34] = mcu1_drif_dram_addr_a[4:2];
4374 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4375 mcu1_physical_addr_b[36:34] = mcu1_drif_dram_addr_b[4:2];
4376 mcu1_physical_addr_b[12:11] = mcu1_drif_dram_dimm_b[1:0];
4377 mcu1_physical_addr_c[36:34] = mcu1_drif_dram_addr_c[4:2];
4378 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4379 end
4380 000: begin
4381 mcu1_physical_addr_a[37:34] = mcu1_drif_dram_addr_a[5:2];
4382 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4383 mcu1_physical_addr_b[37:34] = mcu1_drif_dram_addr_b[5:2];
4384 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4385 mcu1_physical_addr_c[37:34] = mcu1_drif_dram_addr_c[5:2];
4386 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4387 end
4388 endcase
4389 end
4390 8'b1_0_1_11_001,
4391 8'b1_0_1_11_010,
4392 8'b1_0_1_11_100,
4393 8'b1_0_1_11_000: begin
4394 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[14:0],
4395 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:2], mcu1_drif_dram_bank_a[1],
4396 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[1],
4397 5'b00000};
4398 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[14:0],
4399 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:2], mcu1_drif_dram_bank_b[1],
4400 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[1],
4401 5'b00000};
4402 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[14:0],
4403 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:2], mcu1_drif_dram_bank_c[1],
4404 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[1],
4405 5'b00000};
4406 case(num_dimms)
4407 001: begin
4408 mcu1_physical_addr_a[35:34] = mcu1_drif_dram_addr_a[3:2];
4409 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4410 mcu1_physical_addr_b[35:34] = mcu1_drif_dram_addr_b[3:2];
4411 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4412 mcu1_physical_addr_c[35:34] = mcu1_drif_dram_addr_c[3:2];
4413 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4414 end
4415 010: begin
4416 mcu1_physical_addr_a[36:34] = mcu1_drif_dram_addr_a[4:2];
4417 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4418 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4419 mcu1_physical_addr_b[36:34] = mcu1_drif_dram_addr_b[4:2];
4420 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4421 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4422 mcu1_physical_addr_c[36:34] = mcu1_drif_dram_addr_c[4:2];
4423 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4424 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4425 end
4426 100: begin
4427 mcu1_physical_addr_a[37:34] = mcu1_drif_dram_addr_a[5:2];
4428 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4429 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4430 mcu1_physical_addr_b[37:34] = mcu1_drif_dram_addr_b[5:2];
4431 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[1:0];
4432 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4433 mcu1_physical_addr_c[37:34] = mcu1_drif_dram_addr_c[5:2];
4434 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4435 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4436 end
4437 000: begin
4438 mcu1_physical_addr_a[38:34] = mcu1_drif_dram_addr_a[5:2];
4439 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4440 mcu1_physical_addr_a[14] = mcu1_drif_dram_rank_a;
4441 mcu1_physical_addr_b[38:34] = mcu1_drif_dram_addr_b[5:2];
4442 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4443 mcu1_physical_addr_b[14] = mcu1_drif_dram_rank_b;
4444 mcu1_physical_addr_c[38:34] = mcu1_drif_dram_addr_c[5:2];
4445 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4446 mcu1_physical_addr_c[14] = mcu1_drif_dram_rank_c;
4447 end
4448 endcase
4449 end
4450
4451 //---------------------------
4452 // SINGLE CHANNEL, RANK LOW
4453 //---------------------------
4454
4455 8'b0_0_0_00_001,
4456 8'b0_0_0_00_010,
4457 8'b0_0_0_00_100,
4458 8'b0_0_0_00_000: begin
4459 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[12:0],
4460 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
4461 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4462 5'b00000};
4463 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[12:0],
4464 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
4465 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4466 5'b00000};
4467 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[12:0],
4468 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
4469 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4470 5'b00000};
4471 case(num_dimms)
4472 001: begin
4473 end
4474 010: begin
4475 mcu1_physical_addr_a[31] = mcu1_drif_dram_addr_a[3];
4476 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4477 mcu1_physical_addr_b[31] = mcu1_drif_dram_addr_b[3];
4478 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4479 mcu1_physical_addr_c[31] = mcu1_drif_dram_addr_c[3];
4480 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4481 end
4482 100: begin
4483 mcu1_physical_addr_a[32:31] = mcu1_drif_dram_addr_a[4:3];
4484 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4485 mcu1_physical_addr_b[32:31] = mcu1_drif_dram_addr_b[4:3];
4486 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4487 mcu1_physical_addr_c[32:31] = mcu1_drif_dram_addr_c[4:3];
4488 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4489 end
4490 000: begin
4491 mcu1_physical_addr_a[33:31] = mcu1_drif_dram_addr_a[5:3];
4492 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4493 mcu1_physical_addr_b[33:31] = mcu1_drif_dram_addr_b[5:3];
4494 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4495 mcu1_physical_addr_c[33:31] = mcu1_drif_dram_addr_c[5:3];
4496 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4497 end
4498 endcase
4499 end
4500 8'b0_0_1_00_001,
4501 8'b0_0_1_00_010,
4502 8'b0_0_1_00_100,
4503 8'b0_0_1_00_000: begin
4504 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[12:0],
4505 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
4506 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4507 5'b00000};
4508 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[12:0],
4509 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
4510 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4511 5'b00000};
4512 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[12:0],
4513 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
4514 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4515 5'b00000};
4516 case(num_dimms)
4517 001: begin
4518 mcu1_physical_addr_a[31] = mcu1_drif_dram_addr_a[3];
4519 mcu1_physical_addr_a[10] = mcu1_drif_dram_rank_a;
4520 mcu1_physical_addr_b[31] = mcu1_drif_dram_addr_b[3];
4521 mcu1_physical_addr_b[10] = mcu1_drif_dram_rank_b;
4522 mcu1_physical_addr_c[31] = mcu1_drif_dram_addr_c[3];
4523 mcu1_physical_addr_c[10] = mcu1_drif_dram_rank_c;
4524 end
4525 010: begin
4526 mcu1_physical_addr_a[32:31] = mcu1_drif_dram_addr_a[4:3];
4527 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4528 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4529 mcu1_physical_addr_b[32:31] = mcu1_drif_dram_addr_b[4:3];
4530 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4531 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4532 mcu1_physical_addr_c[32:31] = mcu1_drif_dram_addr_c[4:3];
4533 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4534 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4535 end
4536 100: begin
4537 mcu1_physical_addr_a[33:31] = mcu1_drif_dram_addr_a[5:3];
4538 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4539 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4540 mcu1_physical_addr_b[33:31] = mcu1_drif_dram_addr_b[5:3];
4541 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4542 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4543 mcu1_physical_addr_c[33:31] = mcu1_drif_dram_addr_c[5:3];
4544 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4545 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4546 end
4547 000: begin
4548 mcu1_physical_addr_a[34:31] = mcu1_drif_dram_addr_a[6:3];
4549 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4550 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4551 mcu1_physical_addr_b[34:31] = mcu1_drif_dram_addr_b[6:3];
4552 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4553 mcu1_physical_addr_b[13] = mcu1_drif_dram_rank_b;
4554 mcu1_physical_addr_c[34:31] = mcu1_drif_dram_addr_c[6:3];
4555 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4556 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4557 end
4558 endcase
4559 end
4560 8'b0_0_0_01_001,
4561 8'b0_0_0_01_010,
4562 8'b0_0_0_01_100,
4563 8'b0_0_0_01_000: begin
4564 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4565 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
4566 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4567 5'b00000};
4568 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4569 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
4570 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4571 5'b00000};
4572 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4573 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
4574 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4575 5'b00000};
4576 case(num_dimms)
4577 001: begin
4578 end
4579 010: begin
4580 mcu1_physical_addr_a[32] = mcu1_drif_dram_addr_a[3];
4581 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4582 mcu1_physical_addr_b[32] = mcu1_drif_dram_addr_b[3];
4583 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4584 mcu1_physical_addr_c[32] = mcu1_drif_dram_addr_c[3];
4585 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4586 end
4587 100: begin
4588 mcu1_physical_addr_a[33:32] = mcu1_drif_dram_addr_a[4:3];
4589 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4590 mcu1_physical_addr_b[33:32] = mcu1_drif_dram_addr_b[4:3];
4591 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4592 mcu1_physical_addr_c[33:32] = mcu1_drif_dram_addr_c[4:3];
4593 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4594 end
4595 000: begin
4596 mcu1_physical_addr_a[34:32] = mcu1_drif_dram_addr_a[5:3];
4597 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4598 mcu1_physical_addr_b[34:32] = mcu1_drif_dram_addr_b[5:3];
4599 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4600 mcu1_physical_addr_c[34:32] = mcu1_drif_dram_addr_c[5:3];
4601 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4602 end
4603 endcase
4604 end
4605 8'b0_0_1_01_001,
4606 8'b0_0_1_01_010,
4607 8'b0_0_1_01_100,
4608 8'b0_0_1_01_000: begin
4609 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4610 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:3], mcu1_drif_dram_bank_a[1],
4611 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4612 5'b00000};
4613 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4614 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:3], mcu1_drif_dram_bank_b[1],
4615 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4616 5'b00000};
4617 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4618 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:3], mcu1_drif_dram_bank_c[1],
4619 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4620 5'b00000};
4621 case(num_dimms)
4622 001: begin
4623 mcu1_physical_addr_a[32] = mcu1_drif_dram_addr_a[3];
4624 mcu1_physical_addr_a[10] = mcu1_drif_dram_rank_a;
4625 mcu1_physical_addr_b[32] = mcu1_drif_dram_addr_b[3];
4626 mcu1_physical_addr_b[10] = mcu1_drif_dram_rank_b;
4627 mcu1_physical_addr_c[32] = mcu1_drif_dram_addr_c[3];
4628 mcu1_physical_addr_c[10] = mcu1_drif_dram_rank_c;
4629 end
4630 010: begin
4631 mcu1_physical_addr_a[33:32] = mcu1_drif_dram_addr_a[4:3];
4632 mcu1_physical_addr_a[10] = mcu1_drif_dram_dimm_a[0];
4633 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4634 mcu1_physical_addr_b[33:32] = mcu1_drif_dram_addr_b[4:3];
4635 mcu1_physical_addr_b[10] = mcu1_drif_dram_dimm_b[0];
4636 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4637 mcu1_physical_addr_c[33:32] = mcu1_drif_dram_addr_c[4:3];
4638 mcu1_physical_addr_c[10] = mcu1_drif_dram_dimm_c[0];
4639 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4640 end
4641 100: begin
4642 mcu1_physical_addr_a[34:32] = mcu1_drif_dram_addr_a[5:3];
4643 mcu1_physical_addr_a[11:10] = mcu1_drif_dram_dimm_a[1:0];
4644 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4645 mcu1_physical_addr_b[34:32] = mcu1_drif_dram_addr_b[5:3];
4646 mcu1_physical_addr_b[11:10] = mcu1_drif_dram_dimm_b[1:0];
4647 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4648 mcu1_physical_addr_c[34:32] = mcu1_drif_dram_addr_c[5:3];
4649 mcu1_physical_addr_c[11:10] = mcu1_drif_dram_dimm_c[1:0];
4650 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4651 end
4652 000: begin
4653 mcu1_physical_addr_a[35:32] = mcu1_drif_dram_addr_a[6:3];
4654 mcu1_physical_addr_a[12:10] = mcu1_drif_dram_dimm_a[2:0];
4655 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4656 mcu1_physical_addr_b[35:32] = mcu1_drif_dram_addr_b[6:3];
4657 mcu1_physical_addr_b[12:10] = mcu1_drif_dram_dimm_b[2:0];
4658 mcu1_physical_addr_b[13] = mcu1_drif_dram_rank_b;
4659 mcu1_physical_addr_c[35:32] = mcu1_drif_dram_addr_c[6:3];
4660 mcu1_physical_addr_c[12:10] = mcu1_drif_dram_dimm_c[2:0];
4661 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4662 end
4663 endcase
4664 end
4665 8'b0_0_0_10_001,
4666 8'b0_0_0_10_010,
4667 8'b0_0_0_10_100,
4668 8'b0_0_0_10_000: begin
4669 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4670 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
4671 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4672 5'b00000};
4673 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4674 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
4675 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4676 5'b00000};
4677 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4678 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
4679 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4680 5'b00000};
4681 case(num_dimms)
4682 001: begin
4683 mcu1_physical_addr_a[32] = mcu1_drif_dram_addr_a[3];
4684 mcu1_physical_addr_b[32] = mcu1_drif_dram_addr_b[3];
4685 mcu1_physical_addr_c[32] = mcu1_drif_dram_addr_c[3];
4686 end
4687 010: begin
4688 mcu1_physical_addr_a[33:32] = mcu1_drif_dram_addr_a[4:3];
4689 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4690 mcu1_physical_addr_b[33:32] = mcu1_drif_dram_addr_b[4:3];
4691 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4692 mcu1_physical_addr_c[33:32] = mcu1_drif_dram_addr_c[4:3];
4693 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4694 end
4695 100: begin
4696 mcu1_physical_addr_a[34:32] = mcu1_drif_dram_addr_a[5:3];
4697 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4698 mcu1_physical_addr_b[34:32] = mcu1_drif_dram_addr_b[5:3];
4699 mcu1_physical_addr_b[12:11] = mcu1_drif_dram_dimm_b[1:0];
4700 mcu1_physical_addr_c[34:32] = mcu1_drif_dram_addr_c[5:3];
4701 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4702 end
4703 000: begin
4704 mcu1_physical_addr_a[35:32] = mcu1_drif_dram_addr_a[6:3];
4705 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4706 mcu1_physical_addr_b[35:32] = mcu1_drif_dram_addr_b[6:3];
4707 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4708 mcu1_physical_addr_c[35:32] = mcu1_drif_dram_addr_c[6:3];
4709 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4710 end
4711 endcase
4712 end
4713 8'b0_0_1_10_001,
4714 8'b0_0_1_10_010,
4715 8'b0_0_1_10_100,
4716 8'b0_0_1_10_000: begin
4717 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[13:0],
4718 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
4719 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4720 5'b00000};
4721 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[13:0],
4722 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
4723 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4724 5'b00000};
4725 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[13:0],
4726 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
4727 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4728 5'b00000};
4729 case(num_dimms)
4730 001: begin
4731 mcu1_physical_addr_a[33:32] = mcu1_drif_dram_addr_a[4:3];
4732 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4733 mcu1_physical_addr_b[33:32] = mcu1_drif_dram_addr_b[4:3];
4734 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4735 mcu1_physical_addr_c[33:32] = mcu1_drif_dram_addr_c[4:3];
4736 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4737 end
4738 010: begin
4739 mcu1_physical_addr_a[34:32] = mcu1_drif_dram_addr_a[5:3];
4740 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4741 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4742 mcu1_physical_addr_b[34:32] = mcu1_drif_dram_addr_b[5:3];
4743 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4744 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4745 mcu1_physical_addr_c[34:32] = mcu1_drif_dram_addr_c[5:3];
4746 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4747 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4748 end
4749 100: begin
4750 mcu1_physical_addr_a[35:32] = mcu1_drif_dram_addr_a[6:3];
4751 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4752 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4753 mcu1_physical_addr_b[35:32] = mcu1_drif_dram_addr_b[6:3];
4754 mcu1_physical_addr_b[12:11] = mcu1_drif_dram_dimm_b[1:0];
4755 mcu1_physical_addr_b[13] = mcu1_drif_dram_rank_b;
4756 mcu1_physical_addr_c[35:32] = mcu1_drif_dram_addr_c[6:3];
4757 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4758 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4759 end
4760 000: begin
4761 mcu1_physical_addr_a[36:32] = mcu1_drif_dram_addr_a[7:3];
4762 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4763 mcu1_physical_addr_a[14] = mcu1_drif_dram_rank_a;
4764 mcu1_physical_addr_b[36:32] = mcu1_drif_dram_addr_b[7:3];
4765 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4766 mcu1_physical_addr_b[14] = mcu1_drif_dram_rank_b;
4767 mcu1_physical_addr_c[36:32] = mcu1_drif_dram_addr_c[7:3];
4768 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4769 mcu1_physical_addr_c[14] = mcu1_drif_dram_rank_c;
4770 end
4771 endcase
4772 end
4773 8'b0_0_0_11_001,
4774 8'b0_0_0_11_010,
4775 8'b0_0_0_11_100,
4776 8'b0_0_0_11_000: begin
4777 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[14:0],
4778 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
4779 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4780 5'b00000};
4781 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[14:0],
4782 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
4783 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4784 5'b00000};
4785 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[14:0],
4786 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
4787 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4788 5'b00000};
4789 case(num_dimms)
4790 001: begin
4791 mcu1_physical_addr_a[33] = mcu1_drif_dram_addr_a[3];
4792 mcu1_physical_addr_b[33] = mcu1_drif_dram_addr_b[3];
4793 mcu1_physical_addr_c[33] = mcu1_drif_dram_addr_c[3];
4794 end
4795 010: begin
4796 mcu1_physical_addr_a[34:33] = mcu1_drif_dram_addr_a[4:3];
4797 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4798 mcu1_physical_addr_b[34:33] = mcu1_drif_dram_addr_b[4:3];
4799 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4800 mcu1_physical_addr_c[34:33] = mcu1_drif_dram_addr_c[4:3];
4801 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4802 end
4803 100: begin
4804 mcu1_physical_addr_a[35:33] = mcu1_drif_dram_addr_a[5:3];
4805 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4806 mcu1_physical_addr_b[35:33] = mcu1_drif_dram_addr_b[5:3];
4807 mcu1_physical_addr_b[12:11] = mcu1_drif_dram_dimm_b[1:0];
4808 mcu1_physical_addr_c[35:33] = mcu1_drif_dram_addr_c[5:3];
4809 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4810 end
4811 000: begin
4812 mcu1_physical_addr_a[36:33] = mcu1_drif_dram_addr_a[6:3];
4813 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4814 mcu1_physical_addr_b[36:33] = mcu1_drif_dram_addr_b[6:3];
4815 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4816 mcu1_physical_addr_c[36:33] = mcu1_drif_dram_addr_c[6:3];
4817 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4818 end
4819 endcase
4820 end
4821 8'b0_0_1_11_001,
4822 8'b0_0_1_11_010,
4823 8'b0_0_1_11_100,
4824 8'b0_0_1_11_000: begin
4825 mcu1_physical_addr_a = {mcu1_drif_dram_ras_addr_a[14:0],
4826 mcu1_drif_dram_addr_a[11],mcu1_drif_dram_addr_a[9:4], mcu1_drif_dram_bank_a[2:1],
4827 2'b01, mcu1_drif_dram_bank_a[0], mcu1_drif_dram_addr_a[2],
4828 5'b00000};
4829 mcu1_physical_addr_b = {mcu1_drif_dram_ras_addr_b[14:0],
4830 mcu1_drif_dram_addr_b[11],mcu1_drif_dram_addr_b[9:4], mcu1_drif_dram_bank_b[2:1],
4831 2'b01, mcu1_drif_dram_bank_b[0], mcu1_drif_dram_addr_b[2],
4832 5'b00000};
4833 mcu1_physical_addr_c = {mcu1_drif_dram_ras_addr_c[14:0],
4834 mcu1_drif_dram_addr_c[11],mcu1_drif_dram_addr_c[9:4], mcu1_drif_dram_bank_c[2:1],
4835 2'b01, mcu1_drif_dram_bank_c[0], mcu1_drif_dram_addr_c[2],
4836 5'b00000};
4837 case(num_dimms)
4838 001: begin
4839 mcu1_physical_addr_a[34:33] = mcu1_drif_dram_addr_a[4:3];
4840 mcu1_physical_addr_a[11] = mcu1_drif_dram_rank_a;
4841 mcu1_physical_addr_b[34:33] = mcu1_drif_dram_addr_b[4:3];
4842 mcu1_physical_addr_b[11] = mcu1_drif_dram_rank_b;
4843 mcu1_physical_addr_c[34:33] = mcu1_drif_dram_addr_c[4:3];
4844 mcu1_physical_addr_c[11] = mcu1_drif_dram_rank_c;
4845 end
4846 010: begin
4847 mcu1_physical_addr_a[35:33] = mcu1_drif_dram_addr_a[5:3];
4848 mcu1_physical_addr_a[11] = mcu1_drif_dram_dimm_a[0];
4849 mcu1_physical_addr_a[12] = mcu1_drif_dram_rank_a;
4850 mcu1_physical_addr_b[35:33] = mcu1_drif_dram_addr_b[5:3];
4851 mcu1_physical_addr_b[11] = mcu1_drif_dram_dimm_b[0];
4852 mcu1_physical_addr_b[12] = mcu1_drif_dram_rank_b;
4853 mcu1_physical_addr_c[35:33] = mcu1_drif_dram_addr_c[5:3];
4854 mcu1_physical_addr_c[11] = mcu1_drif_dram_dimm_c[0];
4855 mcu1_physical_addr_c[12] = mcu1_drif_dram_rank_c;
4856 end
4857 100: begin
4858 mcu1_physical_addr_a[36:33] = mcu1_drif_dram_addr_a[6:3];
4859 mcu1_physical_addr_a[12:11] = mcu1_drif_dram_dimm_a[1:0];
4860 mcu1_physical_addr_a[13] = mcu1_drif_dram_rank_a;
4861 mcu1_physical_addr_b[36:33] = mcu1_drif_dram_addr_b[6:3];
4862 mcu1_physical_addr_b[12:11] = mcu1_drif_dram_dimm_b[1:0];
4863 mcu1_physical_addr_b[13] = mcu1_drif_dram_rank_b;
4864 mcu1_physical_addr_c[36:33] = mcu1_drif_dram_addr_c[6:3];
4865 mcu1_physical_addr_c[12:11] = mcu1_drif_dram_dimm_c[1:0];
4866 mcu1_physical_addr_c[13] = mcu1_drif_dram_rank_c;
4867 end
4868 000: begin
4869 mcu1_physical_addr_a[37:33] = mcu1_drif_dram_addr_a[7:3];
4870 mcu1_physical_addr_a[13:11] = mcu1_drif_dram_dimm_a[2:0];
4871 mcu1_physical_addr_a[14] = mcu1_drif_dram_rank_a;
4872 mcu1_physical_addr_b[37:33] = mcu1_drif_dram_addr_b[7:3];
4873 mcu1_physical_addr_b[13:11] = mcu1_drif_dram_dimm_b[2:0];
4874 mcu1_physical_addr_b[14] = mcu1_drif_dram_rank_b;
4875 mcu1_physical_addr_c[37:33] = mcu1_drif_dram_addr_c[7:3];
4876 mcu1_physical_addr_c[13:11] = mcu1_drif_dram_dimm_c[2:0];
4877 mcu1_physical_addr_c[14] = mcu1_drif_dram_rank_c;
4878 end
4879 endcase
4880 end
4881 endcase
4882
4883 //----------------------------------------------------------------------------------------------
4884 // M C U 2 - phys addr gen
4885 //----------------------------------------------------------------------------------------------
4886
4887
4888 mcu2_physical_addr_a = 40'b0;
4889 mcu2_physical_addr_b = 40'b0;
4890 mcu2_physical_addr_c = 40'b0;
4891
4892 case({chnl_type, rank_addr, rank, dimm_size, num_dimms})
4893
4894 //-------------------------------
4895 // DUAL CHANNEL, RANK HIGH
4896 //-------------------------------
4897
4898 8'b1_1_0_00_001,
4899 8'b1_1_0_00_010,
4900 8'b1_1_0_00_100,
4901 8'b1_1_0_00_000: begin
4902 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[12:0],
4903 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2],
4904 mcu2_drif_dram_bank_a[1], 2'b10, mcu2_drif_dram_bank_a[0],
4905 mcu2_drif_dram_addr_a[1], 5'b00000};
4906 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[12:0],
4907 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2],
4908 mcu2_drif_dram_bank_b[1], 2'b10, mcu2_drif_dram_bank_b[0],
4909 mcu2_drif_dram_addr_b[1], 5'b00000};
4910 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[12:0],
4911 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2],
4912 mcu2_drif_dram_bank_c[1], 2'b10, mcu2_drif_dram_bank_c[0],
4913 mcu2_drif_dram_addr_c[1], 5'b00000};
4914 end
4915 8'b1_1_1_00_001,
4916 8'b1_1_1_00_010,
4917 8'b1_1_1_00_100,
4918 8'b1_1_1_00_000: begin
4919 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[12:0],
4920 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2],
4921 mcu2_drif_dram_bank_a[1], 2'b10, mcu2_drif_dram_bank_a[0],
4922 mcu2_drif_dram_addr_a[1], 5'b00000};
4923 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[12:0],
4924 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2],
4925 mcu2_drif_dram_bank_b[1], 2'b10, mcu2_drif_dram_bank_b[0],
4926 mcu2_drif_dram_addr_b[1], 5'b00000};
4927 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[12:0],
4928 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2],
4929 mcu2_drif_dram_bank_c[1], 2'b10, mcu2_drif_dram_bank_c[0],
4930 mcu2_drif_dram_addr_c[1], 5'b00000};
4931 case(num_dimms)
4932 001: begin
4933 mcu2_physical_addr_a[32] = mcu2_drif_dram_rank_a;
4934 mcu2_physical_addr_b[32] = mcu2_drif_dram_rank_b;
4935 mcu2_physical_addr_c[32] = mcu2_drif_dram_rank_c;
4936 end
4937 010: begin
4938 mcu2_physical_addr_a[33] = mcu2_drif_dram_rank_a;
4939 mcu2_physical_addr_b[33] = mcu2_drif_dram_rank_b;
4940 mcu2_physical_addr_c[33] = mcu2_drif_dram_rank_c;
4941 end
4942 100: begin
4943 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
4944 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
4945 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
4946 end
4947 000: begin
4948 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
4949 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
4950 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
4951 end
4952 endcase
4953 end
4954 8'b1_1_0_01_001,
4955 8'b1_1_0_01_010,
4956 8'b1_1_0_01_100,
4957 8'b1_1_0_01_000: begin
4958 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[13:0],
4959 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2],
4960 mcu2_drif_dram_bank_a[1], 2'b10, mcu2_drif_dram_bank_a[0],
4961 mcu2_drif_dram_addr_a[1], 5'b00000};
4962 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[13:0],
4963 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2],
4964 mcu2_drif_dram_bank_b[1], 2'b10, mcu2_drif_dram_bank_b[0],
4965 mcu2_drif_dram_addr_b[1], 5'b00000};
4966 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[13:0],
4967 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2],
4968 mcu2_drif_dram_bank_c[1], 2'b10, mcu2_drif_dram_bank_c[0],
4969 mcu2_drif_dram_addr_c[1], 5'b00000};
4970 end
4971 8'b1_1_1_01_001,
4972 8'b1_1_1_01_010,
4973 8'b1_1_1_01_100,
4974 8'b1_1_1_01_000: begin
4975 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[13:0],
4976 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2],
4977 mcu2_drif_dram_bank_a[1], 2'b10, mcu2_drif_dram_bank_a[0],
4978 mcu2_drif_dram_addr_a[1], 5'b00000};
4979 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[13:0],
4980 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2],
4981 mcu2_drif_dram_bank_b[1], 2'b10, mcu2_drif_dram_bank_b[0],
4982 mcu2_drif_dram_addr_b[1], 5'b00000};
4983 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[13:0],
4984 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2],
4985 mcu2_drif_dram_bank_c[1], 2'b10, mcu2_drif_dram_bank_c[0],
4986 mcu2_drif_dram_addr_c[1], 5'b00000};
4987 case(num_dimms)
4988 001: begin
4989 mcu2_physical_addr_a[33] = mcu2_drif_dram_rank_a;
4990 mcu2_physical_addr_b[33] = mcu2_drif_dram_rank_b;
4991 mcu2_physical_addr_c[33] = mcu2_drif_dram_rank_c;
4992 end
4993 010: begin
4994 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
4995 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
4996 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
4997 end
4998 100: begin
4999 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
5000 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
5001 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
5002 end
5003 000: begin
5004 mcu2_physical_addr_a[36] = mcu2_drif_dram_rank_a;
5005 mcu2_physical_addr_b[36] = mcu2_drif_dram_rank_b;
5006 mcu2_physical_addr_c[36] = mcu2_drif_dram_rank_c;
5007 end
5008 endcase
5009 end
5010 8'b1_1_0_10_001,
5011 8'b1_1_0_10_010,
5012 8'b1_1_0_10_100,
5013 8'b1_1_0_10_000: begin
5014 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[2],
5015 mcu2_drif_dram_ras_addr_a[13:0], mcu2_drif_dram_addr_a[11],
5016 mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[2:1],
5017 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1], 5'b00000};
5018 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[2],
5019 mcu2_drif_dram_ras_addr_b[13:0], mcu2_drif_dram_addr_b[11],
5020 mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[2:1],
5021 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1], 5'b00000};
5022 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[2],
5023 mcu2_drif_dram_ras_addr_c[13:0], mcu2_drif_dram_addr_c[11],
5024 mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[2:1],
5025 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1], 5'b00000};
5026 end
5027 8'b1_1_1_10_001,
5028 8'b1_1_1_10_010,
5029 8'b1_1_1_10_100,
5030 8'b1_1_1_10_000: begin
5031 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[2],
5032 mcu2_drif_dram_ras_addr_a[13:0], mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3],
5033 mcu2_drif_dram_bank_a[2:1], 2'b10, mcu2_drif_dram_bank_a[0],
5034 mcu2_drif_dram_addr_a[1], 5'b00000};
5035 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[2],
5036 mcu2_drif_dram_ras_addr_b[13:0], mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3],
5037 mcu2_drif_dram_bank_b[2:1], 2'b10, mcu2_drif_dram_bank_b[0],
5038 mcu2_drif_dram_addr_b[1], 5'b00000};
5039 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[2],
5040 mcu2_drif_dram_ras_addr_c[13:0], mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3],
5041 mcu2_drif_dram_bank_c[2:1], 2'b10, mcu2_drif_dram_bank_c[0],
5042 mcu2_drif_dram_addr_c[1], 5'b00000};
5043 case(num_dimms)
5044 001: begin
5045 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
5046 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
5047 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
5048 end
5049 010: begin
5050 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
5051 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
5052 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
5053 end
5054 100: begin
5055 mcu2_physical_addr_a[36] = mcu2_drif_dram_rank_a;
5056 mcu2_physical_addr_b[36] = mcu2_drif_dram_rank_b;
5057 mcu2_physical_addr_c[36] = mcu2_drif_dram_rank_c;
5058 end
5059 000: begin
5060 mcu2_physical_addr_a[37] = mcu2_drif_dram_rank_a;
5061 mcu2_physical_addr_b[37] = mcu2_drif_dram_rank_b;
5062 mcu2_physical_addr_c[37] = mcu2_drif_dram_rank_c;
5063 end
5064 endcase
5065 end
5066 8'b1_1_0_11_001,
5067 8'b1_1_0_11_010,
5068 8'b1_1_0_11_100,
5069 8'b1_1_0_11_000: begin
5070 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[2],
5071 mcu2_drif_dram_ras_addr_a[14:0], mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3],
5072 mcu2_drif_dram_bank_a[2:1], 2'b10, mcu2_drif_dram_bank_a[0],
5073 mcu2_drif_dram_addr_a[1], 5'b00000};
5074 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[2],
5075 mcu2_drif_dram_ras_addr_b[14:0], mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3],
5076 mcu2_drif_dram_bank_b[2:1], 2'b10, mcu2_drif_dram_bank_b[0],
5077 mcu2_drif_dram_addr_b[1], 5'b00000};
5078 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[2],
5079 mcu2_drif_dram_ras_addr_c[14:0], mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3],
5080 mcu2_drif_dram_bank_c[2:1], 2'b10, mcu2_drif_dram_bank_c[0],
5081 mcu2_drif_dram_addr_c[1], 5'b00000};
5082 end
5083 8'b1_1_1_11_001,
5084 8'b1_1_1_11_010,
5085 8'b1_1_1_11_100,
5086 8'b1_1_1_11_000: begin
5087 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[2],
5088 mcu2_drif_dram_ras_addr_a[14:0], mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3],
5089 mcu2_drif_dram_bank_a[2:1], 2'b10, mcu2_drif_dram_bank_a[0],
5090 mcu2_drif_dram_addr_a[1], 5'b00000};
5091 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[2],
5092 mcu2_drif_dram_ras_addr_b[14:0], mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3],
5093 mcu2_drif_dram_bank_b[2:1], 2'b10, mcu2_drif_dram_bank_b[0],
5094 mcu2_drif_dram_addr_b[1], 5'b00000};
5095 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[2],
5096 mcu2_drif_dram_ras_addr_c[14:0], mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3],
5097 mcu2_drif_dram_bank_c[2:1], 2'b10, mcu2_drif_dram_bank_c[0],
5098 mcu2_drif_dram_addr_c[1], 5'b00000};
5099 case(num_dimms)
5100 001: begin
5101 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
5102 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
5103 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
5104 end
5105 010: begin
5106 mcu2_physical_addr_a[36] = mcu2_drif_dram_rank_a;
5107 mcu2_physical_addr_b[36] = mcu2_drif_dram_rank_b;
5108 mcu2_physical_addr_c[36] = mcu2_drif_dram_rank_c;
5109 end
5110 100: begin
5111 mcu2_physical_addr_a[37] = mcu2_drif_dram_rank_a;
5112 mcu2_physical_addr_b[37] = mcu2_drif_dram_rank_b;
5113 mcu2_physical_addr_c[37] = mcu2_drif_dram_rank_c;
5114 end
5115 000: begin
5116 mcu2_physical_addr_a[38] = mcu2_drif_dram_rank_a;
5117 mcu2_physical_addr_b[38] = mcu2_drif_dram_rank_b;
5118 mcu2_physical_addr_c[38] = mcu2_drif_dram_rank_c;
5119 end
5120 endcase
5121 end
5122
5123 //---------------------------
5124 // SINGLE CHANNEL, RANK HIGH
5125 //---------------------------
5126
5127 8'b0_1_0_00_001,
5128 8'b0_1_0_00_010,
5129 8'b0_1_0_00_100,
5130 8'b0_1_0_00_000: begin
5131 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[12:0],
5132 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5133 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5134 5'b00000};
5135 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[12:0],
5136 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5137 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5138 5'b00000};
5139 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[12:0],
5140 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5141 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5142 5'b00000};
5143 end
5144 8'b0_1_1_00_001,
5145 8'b0_1_1_00_010,
5146 8'b0_1_1_00_100,
5147 8'b0_1_1_00_000: begin
5148 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[12:0],
5149 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5150 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5151 5'b00000};
5152 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[12:0],
5153 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5154 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5155 5'b00000};
5156 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[12:0],
5157 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5158 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5159 5'b00000};
5160 case(num_dimms)
5161 001: begin
5162 mcu2_physical_addr_a[31] = mcu2_drif_dram_rank_a;
5163 mcu2_physical_addr_b[31] = mcu2_drif_dram_rank_b;
5164 mcu2_physical_addr_c[31] = mcu2_drif_dram_rank_c;
5165 end
5166 010: begin
5167 mcu2_physical_addr_a[32] = mcu2_drif_dram_rank_a;
5168 mcu2_physical_addr_b[32] = mcu2_drif_dram_rank_b;
5169 mcu2_physical_addr_c[32] = mcu2_drif_dram_rank_c;
5170 end
5171 100: begin
5172 mcu2_physical_addr_a[33] = mcu2_drif_dram_rank_a;
5173 mcu2_physical_addr_b[33] = mcu2_drif_dram_rank_b;
5174 mcu2_physical_addr_c[33] = mcu2_drif_dram_rank_c;
5175 end
5176 000: begin
5177 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
5178 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
5179 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
5180 end
5181 endcase
5182 end
5183 8'b0_1_0_01_001,
5184 8'b0_1_0_01_010,
5185 8'b0_1_0_01_100,
5186 8'b0_1_0_01_000: begin
5187 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[13:0],
5188 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5189 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5190 5'b00000};
5191 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[13:0],
5192 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5193 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5194 5'b00000};
5195 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[13:0],
5196 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5197 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5198 5'b00000};
5199 end
5200 8'b0_1_1_01_001,
5201 8'b0_1_1_01_010,
5202 8'b0_1_1_01_100,
5203 8'b0_1_1_01_000: begin
5204 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_ras_addr_a[13:0],
5205 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5206 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5207 5'b00000};
5208 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_ras_addr_b[13:0],
5209 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5210 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5211 5'b00000};
5212 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_ras_addr_c[13:0],
5213 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5214 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5215 5'b00000};
5216 case(num_dimms)
5217 001: begin
5218 mcu2_physical_addr_a[32] = mcu2_drif_dram_rank_a;
5219 mcu2_physical_addr_b[32] = mcu2_drif_dram_rank_b;
5220 mcu2_physical_addr_c[32] = mcu2_drif_dram_rank_c;
5221 end
5222 010: begin
5223 mcu2_physical_addr_a[33] = mcu2_drif_dram_rank_a;
5224 mcu2_physical_addr_b[33] = mcu2_drif_dram_rank_b;
5225 mcu2_physical_addr_c[33] = mcu2_drif_dram_rank_c;
5226 end
5227 100: begin
5228 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
5229 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
5230 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
5231 end
5232 000: begin
5233 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
5234 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
5235 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
5236 end
5237 endcase
5238 end
5239 8'b0_1_0_10_001,
5240 8'b0_1_0_10_010,
5241 8'b0_1_0_10_100,
5242 8'b0_1_0_10_000: begin
5243 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[3],
5244 mcu2_drif_dram_ras_addr_a[13:0],
5245 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
5246 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5247 5'b00000};
5248 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[3],
5249 mcu2_drif_dram_ras_addr_b[13:0],
5250 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
5251 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5252 5'b00000};
5253 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[3],
5254 mcu2_drif_dram_ras_addr_c[13:0],
5255 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
5256 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5257 5'b00000};
5258 end
5259 8'b0_1_1_10_001,
5260 8'b0_1_1_10_010,
5261 8'b0_1_1_10_100,
5262 8'b0_1_1_10_000: begin
5263 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[3],
5264 mcu2_drif_dram_ras_addr_a[13:0],
5265 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
5266 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5267 5'b00000};
5268 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[3],
5269 mcu2_drif_dram_ras_addr_b[13:0],
5270 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
5271 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5272 5'b00000};
5273 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[3],
5274 mcu2_drif_dram_ras_addr_c[13:0],
5275 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
5276 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5277 5'b00000};
5278 case(num_dimms)
5279 001: begin
5280 mcu2_physical_addr_a[33] = mcu2_drif_dram_rank_a;
5281 mcu2_physical_addr_b[33] = mcu2_drif_dram_rank_b;
5282 mcu2_physical_addr_c[33] = mcu2_drif_dram_rank_c;
5283 end
5284 010: begin
5285 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
5286 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
5287 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
5288 end
5289 100: begin
5290 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
5291 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
5292 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
5293 end
5294 000: begin
5295 mcu2_physical_addr_a[36] = mcu2_drif_dram_rank_a;
5296 mcu2_physical_addr_b[36] = mcu2_drif_dram_rank_b;
5297 mcu2_physical_addr_c[36] = mcu2_drif_dram_rank_c;
5298 end
5299 endcase
5300 end
5301 8'b0_1_0_11_001,
5302 8'b0_1_0_11_010,
5303 8'b0_1_0_11_100,
5304 8'b0_1_0_11_000: begin
5305 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[3],
5306 mcu2_drif_dram_ras_addr_a[14:0],
5307 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
5308 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5309 5'b00000};
5310 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[3],
5311 mcu2_drif_dram_ras_addr_b[14:0],
5312 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
5313 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5314 5'b00000};
5315 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[3],
5316 mcu2_drif_dram_ras_addr_c[14:0],
5317 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
5318 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5319 5'b00000};
5320 end
5321 8'b0_1_1_11_001,
5322 8'b0_1_1_11_010,
5323 8'b0_1_1_11_100,
5324 8'b0_1_1_11_000: begin
5325 mcu2_physical_addr_a = {mcu2_drif_dram_dimm_a, mcu2_drif_dram_addr_a[3],
5326 mcu2_drif_dram_ras_addr_a[14:0],
5327 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
5328 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5329 5'b00000};
5330 mcu2_physical_addr_b = {mcu2_drif_dram_dimm_b, mcu2_drif_dram_addr_b[3],
5331 mcu2_drif_dram_ras_addr_b[14:0],
5332 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
5333 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5334 5'b00000};
5335 mcu2_physical_addr_c = {mcu2_drif_dram_dimm_c, mcu2_drif_dram_addr_c[3],
5336 mcu2_drif_dram_ras_addr_c[14:0],
5337 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
5338 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5339 5'b00000};
5340 case(num_dimms)
5341 001: begin
5342 mcu2_physical_addr_a[34] = mcu2_drif_dram_rank_a;
5343 mcu2_physical_addr_b[34] = mcu2_drif_dram_rank_b;
5344 mcu2_physical_addr_c[34] = mcu2_drif_dram_rank_c;
5345 end
5346 010: begin
5347 mcu2_physical_addr_a[35] = mcu2_drif_dram_rank_a;
5348 mcu2_physical_addr_b[35] = mcu2_drif_dram_rank_b;
5349 mcu2_physical_addr_c[35] = mcu2_drif_dram_rank_c;
5350 end
5351 100: begin
5352 mcu2_physical_addr_a[36] = mcu2_drif_dram_rank_a;
5353 mcu2_physical_addr_b[36] = mcu2_drif_dram_rank_b;
5354 mcu2_physical_addr_c[36] = mcu2_drif_dram_rank_c;
5355 end
5356 000: begin
5357 mcu2_physical_addr_a[37] = mcu2_drif_dram_rank_a;
5358 mcu2_physical_addr_b[37] = mcu2_drif_dram_rank_b;
5359 mcu2_physical_addr_c[37] = mcu2_drif_dram_rank_c;
5360 end
5361 endcase
5362 end
5363
5364 //---------------------------
5365 // DUAL CHANNEL, RANK LOW
5366 //---------------------------
5367
5368 8'b1_0_0_00_001,
5369 8'b1_0_0_00_010,
5370 8'b1_0_0_00_100,
5371 8'b1_0_0_00_000: begin
5372 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[12:0],
5373 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2], mcu2_drif_dram_bank_a[1],
5374 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5375 5'b00000};
5376 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[12:0],
5377 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2], mcu2_drif_dram_bank_b[1],
5378 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5379 5'b00000};
5380 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[12:0],
5381 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2], mcu2_drif_dram_bank_c[1],
5382 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5383 5'b00000};
5384 case(num_dimms)
5385 001: begin
5386 end
5387 010: begin
5388 mcu2_physical_addr_a[32] = mcu2_drif_dram_addr_a[2];
5389 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5390 mcu2_physical_addr_b[32] = mcu2_drif_dram_addr_b[2];
5391 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5392 mcu2_physical_addr_c[32] = mcu2_drif_dram_addr_c[2];
5393 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5394 end
5395 100: begin
5396 mcu2_physical_addr_a[33:32] = mcu2_drif_dram_addr_a[3:2];
5397 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5398 mcu2_physical_addr_b[33:32] = mcu2_drif_dram_addr_b[3:2];
5399 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5400 mcu2_physical_addr_c[33:32] = mcu2_drif_dram_addr_c[3:2];
5401 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5402 end
5403 000: begin
5404 mcu2_physical_addr_a[34:32] = mcu2_drif_dram_addr_a[4:2];
5405 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5406 mcu2_physical_addr_b[34:32] = mcu2_drif_dram_addr_b[4:2];
5407 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5408 mcu2_physical_addr_c[34:32] = mcu2_drif_dram_addr_c[4:2];
5409 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5410 end
5411 endcase
5412 end
5413 8'b1_0_1_00_001,
5414 8'b1_0_1_00_010,
5415 8'b1_0_1_00_100,
5416 8'b1_0_1_00_000: begin
5417 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[12:0],
5418 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2], mcu2_drif_dram_bank_a[1],
5419 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5420 5'b00000};
5421 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[12:0],
5422 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2], mcu2_drif_dram_bank_b[1],
5423 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5424 5'b00000};
5425 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[12:0],
5426 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2], mcu2_drif_dram_bank_c[1],
5427 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5428 5'b00000};
5429 case(num_dimms)
5430 001: begin
5431 mcu2_physical_addr_a[32] = mcu2_drif_dram_addr_a[2];
5432 mcu2_physical_addr_a[10] = mcu2_drif_dram_rank_a;
5433 mcu2_physical_addr_b[32] = mcu2_drif_dram_addr_b[2];
5434 mcu2_physical_addr_b[10] = mcu2_drif_dram_rank_b;
5435 mcu2_physical_addr_c[32] = mcu2_drif_dram_addr_c[2];
5436 mcu2_physical_addr_c[10] = mcu2_drif_dram_rank_c;
5437 end
5438 010: begin
5439 mcu2_physical_addr_a[33:32] = mcu2_drif_dram_addr_a[3:2];
5440 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5441 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
5442 mcu2_physical_addr_b[33:32] = mcu2_drif_dram_addr_b[3:2];
5443 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5444 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
5445 mcu2_physical_addr_c[33:32] = mcu2_drif_dram_addr_c[3:2];
5446 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5447 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
5448 end
5449 100: begin
5450 mcu2_physical_addr_a[34:32] = mcu2_drif_dram_addr_a[4:2];
5451 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5452 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
5453 mcu2_physical_addr_b[34:32] = mcu2_drif_dram_addr_b[4:2];
5454 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5455 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5456 mcu2_physical_addr_c[34:32] = mcu2_drif_dram_addr_c[4:2];
5457 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5458 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
5459 end
5460 000: begin
5461 mcu2_physical_addr_a[35:32] = mcu2_drif_dram_addr_a[5:2];
5462 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5463 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
5464 mcu2_physical_addr_b[35:32] = mcu2_drif_dram_addr_b[5:2];
5465 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5466 mcu2_physical_addr_b[13] = mcu2_drif_dram_rank_b;
5467 mcu2_physical_addr_c[35:32] = mcu2_drif_dram_addr_c[5:2];
5468 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5469 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
5470 end
5471 endcase
5472 end
5473 8'b1_0_0_01_001,
5474 8'b1_0_0_01_010,
5475 8'b1_0_0_01_100,
5476 8'b1_0_0_01_000: begin
5477 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
5478 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2], mcu2_drif_dram_bank_a[1],
5479 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5480 5'b00000};
5481 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
5482 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2], mcu2_drif_dram_bank_b[1],
5483 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5484 5'b00000};
5485 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
5486 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2], mcu2_drif_dram_bank_c[1],
5487 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5488 5'b00000};
5489 case(num_dimms)
5490 001: begin
5491 end
5492 010: begin
5493 mcu2_physical_addr_a[33] = mcu2_drif_dram_addr_a[2];
5494 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5495 mcu2_physical_addr_b[33] = mcu2_drif_dram_addr_b[2];
5496 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5497 mcu2_physical_addr_c[33] = mcu2_drif_dram_addr_c[2];
5498 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5499 end
5500 100: begin
5501 mcu2_physical_addr_a[34:33] = mcu2_drif_dram_addr_a[3:2];
5502 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5503 mcu2_physical_addr_b[34:33] = mcu2_drif_dram_addr_b[3:2];
5504 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5505 mcu2_physical_addr_c[34:33] = mcu2_drif_dram_addr_c[3:2];
5506 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5507 end
5508 000: begin
5509 mcu2_physical_addr_a[35:33] = mcu2_drif_dram_addr_a[4:2];
5510 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5511 mcu2_physical_addr_b[35:33] = mcu2_drif_dram_addr_b[4:2];
5512 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5513 mcu2_physical_addr_c[35:33] = mcu2_drif_dram_addr_c[4:2];
5514 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5515 end
5516 endcase
5517 end
5518 8'b1_0_1_01_001,
5519 8'b1_0_1_01_010,
5520 8'b1_0_1_01_100,
5521 8'b1_0_1_01_000: begin
5522 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
5523 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2], mcu2_drif_dram_bank_a[1],
5524 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5525 5'b00000};
5526 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
5527 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2], mcu2_drif_dram_bank_b[1],
5528 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5529 5'b00000};
5530 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
5531 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2], mcu2_drif_dram_bank_c[1],
5532 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5533 5'b00000};
5534 case(num_dimms)
5535 001: begin
5536 mcu2_physical_addr_a[33] = mcu2_drif_dram_addr_a[2];
5537 mcu2_physical_addr_a[10] = mcu2_drif_dram_rank_a;
5538 mcu2_physical_addr_b[33] = mcu2_drif_dram_addr_b[2];
5539 mcu2_physical_addr_b[10] = mcu2_drif_dram_rank_b;
5540 mcu2_physical_addr_c[33] = mcu2_drif_dram_addr_c[2];
5541 mcu2_physical_addr_c[10] = mcu2_drif_dram_rank_c;
5542 end
5543 010: begin
5544 mcu2_physical_addr_a[34:33] = mcu2_drif_dram_addr_a[3:2];
5545 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5546 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
5547 mcu2_physical_addr_b[34:33] = mcu2_drif_dram_addr_b[3:2];
5548 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5549 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
5550 mcu2_physical_addr_c[34:33] = mcu2_drif_dram_addr_c[3:2];
5551 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5552 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
5553 end
5554 100: begin
5555 mcu2_physical_addr_a[35:33] = mcu2_drif_dram_addr_a[4:2];
5556 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5557 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
5558 mcu2_physical_addr_b[35:33] = mcu2_drif_dram_addr_b[4:2];
5559 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5560 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5561 mcu2_physical_addr_c[35:33] = mcu2_drif_dram_addr_c[4:2];
5562 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5563 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
5564 end
5565 000: begin
5566 mcu2_physical_addr_a[36:33] = mcu2_drif_dram_addr_a[5:2];
5567 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5568 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
5569 mcu2_physical_addr_b[36:33] = mcu2_drif_dram_addr_b[5:2];
5570 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5571 mcu2_physical_addr_b[13] = mcu2_drif_dram_rank_b;
5572 mcu2_physical_addr_c[36:33] = mcu2_drif_dram_addr_c[5:2];
5573 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5574 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
5575 end
5576 endcase
5577 end
5578 8'b1_0_0_10_001,
5579 8'b1_0_0_10_010,
5580 8'b1_0_0_10_100,
5581 8'b1_0_0_10_000: begin
5582 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
5583 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[2:1],
5584 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5585 5'b00000};
5586 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
5587 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[2:1],
5588 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5589 5'b00000};
5590 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
5591 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[2:1],
5592 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5593 5'b00000};
5594 case(num_dimms)
5595 001: begin
5596 mcu2_physical_addr_a[33] = mcu2_drif_dram_addr_a[2];
5597 mcu2_physical_addr_b[33] = mcu2_drif_dram_addr_b[2];
5598 mcu2_physical_addr_c[33] = mcu2_drif_dram_addr_c[2];
5599 end
5600 010: begin
5601 mcu2_physical_addr_a[34:33] = mcu2_drif_dram_addr_a[3:2];
5602 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
5603 mcu2_physical_addr_b[34:33] = mcu2_drif_dram_addr_b[3:2];
5604 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
5605 mcu2_physical_addr_c[34:33] = mcu2_drif_dram_addr_c[3:2];
5606 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
5607 end
5608 100: begin
5609 mcu2_physical_addr_a[35:33] = mcu2_drif_dram_addr_a[4:2];
5610 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
5611 mcu2_physical_addr_b[35:33] = mcu2_drif_dram_addr_b[4:2];
5612 mcu2_physical_addr_b[12:11] = mcu2_drif_dram_dimm_b[1:0];
5613 mcu2_physical_addr_c[35:33] = mcu2_drif_dram_addr_c[4:2];
5614 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
5615 end
5616 000: begin
5617 mcu2_physical_addr_a[36:33] = mcu2_drif_dram_addr_a[5:2];
5618 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
5619 mcu2_physical_addr_b[36:33] = mcu2_drif_dram_addr_b[5:2];
5620 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
5621 mcu2_physical_addr_c[36:33] = mcu2_drif_dram_addr_c[5:2];
5622 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
5623 end
5624 endcase
5625 end
5626 8'b1_0_1_10_001,
5627 8'b1_0_1_10_010,
5628 8'b1_0_1_10_100,
5629 8'b1_0_1_10_000: begin
5630 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
5631 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2], mcu2_drif_dram_bank_a[1],
5632 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5633 5'b00000};
5634 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
5635 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2], mcu2_drif_dram_bank_b[1],
5636 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5637 5'b00000};
5638 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
5639 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2], mcu2_drif_dram_bank_c[1],
5640 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5641 5'b00000};
5642 case(num_dimms)
5643 001: begin
5644 mcu2_physical_addr_a[34:33] = mcu2_drif_dram_addr_a[3:2];
5645 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
5646 mcu2_physical_addr_b[34:33] = mcu2_drif_dram_addr_b[3:2];
5647 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
5648 mcu2_physical_addr_c[34:33] = mcu2_drif_dram_addr_c[3:2];
5649 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
5650 end
5651 010: begin
5652 mcu2_physical_addr_a[35:33] = mcu2_drif_dram_addr_a[4:2];
5653 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
5654 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
5655 mcu2_physical_addr_b[35:33] = mcu2_drif_dram_addr_b[4:2];
5656 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
5657 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5658 mcu2_physical_addr_c[35:33] = mcu2_drif_dram_addr_c[4:2];
5659 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
5660 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
5661 end
5662 100: begin
5663 mcu2_physical_addr_a[36:33] = mcu2_drif_dram_addr_a[5:2];
5664 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
5665 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
5666 mcu2_physical_addr_b[36:33] = mcu2_drif_dram_addr_b[5:2];
5667 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[1:0];
5668 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5669 mcu2_physical_addr_c[36:33] = mcu2_drif_dram_addr_c[5:2];
5670 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
5671 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
5672 end
5673 000: begin
5674 mcu2_physical_addr_a[37:33] = mcu2_drif_dram_addr_a[5:2];
5675 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
5676 mcu2_physical_addr_a[14] = mcu2_drif_dram_rank_a;
5677 mcu2_physical_addr_b[37:33] = mcu2_drif_dram_addr_b[5:2];
5678 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
5679 mcu2_physical_addr_b[14] = mcu2_drif_dram_rank_b;
5680 mcu2_physical_addr_c[37:33] = mcu2_drif_dram_addr_c[5:2];
5681 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
5682 mcu2_physical_addr_c[14] = mcu2_drif_dram_rank_c;
5683 end
5684 endcase
5685 end
5686 8'b1_0_0_11_001,
5687 8'b1_0_0_11_010,
5688 8'b1_0_0_11_100,
5689 8'b1_0_0_11_000: begin
5690 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[14:0],
5691 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[2:1],
5692 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5693 5'b00000};
5694 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[14:0],
5695 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[2:1],
5696 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5697 5'b00000};
5698 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[14:0],
5699 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[2:1],
5700 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5701 5'b00000};
5702 case(num_dimms)
5703 001: begin
5704 mcu2_physical_addr_a[34] = mcu2_drif_dram_addr_a[2];
5705 mcu2_physical_addr_b[34] = mcu2_drif_dram_addr_b[2];
5706 mcu2_physical_addr_c[34] = mcu2_drif_dram_addr_c[2];
5707 end
5708 010: begin
5709 mcu2_physical_addr_a[35:34] = mcu2_drif_dram_addr_a[3:2];
5710 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
5711 mcu2_physical_addr_b[35:34] = mcu2_drif_dram_addr_b[3:2];
5712 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
5713 mcu2_physical_addr_c[35:34] = mcu2_drif_dram_addr_c[3:2];
5714 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
5715 end
5716 100: begin
5717 mcu2_physical_addr_a[36:34] = mcu2_drif_dram_addr_a[4:2];
5718 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
5719 mcu2_physical_addr_b[36:34] = mcu2_drif_dram_addr_b[4:2];
5720 mcu2_physical_addr_b[12:11] = mcu2_drif_dram_dimm_b[1:0];
5721 mcu2_physical_addr_c[36:34] = mcu2_drif_dram_addr_c[4:2];
5722 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
5723 end
5724 000: begin
5725 mcu2_physical_addr_a[37:34] = mcu2_drif_dram_addr_a[5:2];
5726 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
5727 mcu2_physical_addr_b[37:34] = mcu2_drif_dram_addr_b[5:2];
5728 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
5729 mcu2_physical_addr_c[37:34] = mcu2_drif_dram_addr_c[5:2];
5730 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
5731 end
5732 endcase
5733 end
5734 8'b1_0_1_11_001,
5735 8'b1_0_1_11_010,
5736 8'b1_0_1_11_100,
5737 8'b1_0_1_11_000: begin
5738 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[14:0],
5739 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:2], mcu2_drif_dram_bank_a[1],
5740 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[1],
5741 5'b00000};
5742 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[14:0],
5743 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:2], mcu2_drif_dram_bank_b[1],
5744 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[1],
5745 5'b00000};
5746 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[14:0],
5747 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:2], mcu2_drif_dram_bank_c[1],
5748 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[1],
5749 5'b00000};
5750 case(num_dimms)
5751 001: begin
5752 mcu2_physical_addr_a[35:34] = mcu2_drif_dram_addr_a[3:2];
5753 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
5754 mcu2_physical_addr_b[35:34] = mcu2_drif_dram_addr_b[3:2];
5755 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
5756 mcu2_physical_addr_c[35:34] = mcu2_drif_dram_addr_c[3:2];
5757 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
5758 end
5759 010: begin
5760 mcu2_physical_addr_a[36:34] = mcu2_drif_dram_addr_a[4:2];
5761 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
5762 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
5763 mcu2_physical_addr_b[36:34] = mcu2_drif_dram_addr_b[4:2];
5764 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
5765 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5766 mcu2_physical_addr_c[36:34] = mcu2_drif_dram_addr_c[4:2];
5767 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
5768 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
5769 end
5770 100: begin
5771 mcu2_physical_addr_a[37:34] = mcu2_drif_dram_addr_a[5:2];
5772 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
5773 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
5774 mcu2_physical_addr_b[37:34] = mcu2_drif_dram_addr_b[5:2];
5775 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[1:0];
5776 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5777 mcu2_physical_addr_c[37:34] = mcu2_drif_dram_addr_c[5:2];
5778 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
5779 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
5780 end
5781 000: begin
5782 mcu2_physical_addr_a[38:34] = mcu2_drif_dram_addr_a[5:2];
5783 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
5784 mcu2_physical_addr_a[14] = mcu2_drif_dram_rank_a;
5785 mcu2_physical_addr_b[38:34] = mcu2_drif_dram_addr_b[5:2];
5786 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
5787 mcu2_physical_addr_b[14] = mcu2_drif_dram_rank_b;
5788 mcu2_physical_addr_c[38:34] = mcu2_drif_dram_addr_c[5:2];
5789 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
5790 mcu2_physical_addr_c[14] = mcu2_drif_dram_rank_c;
5791 end
5792 endcase
5793 end
5794
5795 //---------------------------
5796 // SINGLE CHANNEL, RANK LOW
5797 //---------------------------
5798
5799 8'b0_0_0_00_001,
5800 8'b0_0_0_00_010,
5801 8'b0_0_0_00_100,
5802 8'b0_0_0_00_000: begin
5803 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[12:0],
5804 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5805 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5806 5'b00000};
5807 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[12:0],
5808 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5809 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5810 5'b00000};
5811 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[12:0],
5812 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5813 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5814 5'b00000};
5815 case(num_dimms)
5816 001: begin
5817 end
5818 010: begin
5819 mcu2_physical_addr_a[31] = mcu2_drif_dram_addr_a[3];
5820 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5821 mcu2_physical_addr_b[31] = mcu2_drif_dram_addr_b[3];
5822 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5823 mcu2_physical_addr_c[31] = mcu2_drif_dram_addr_c[3];
5824 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5825 end
5826 100: begin
5827 mcu2_physical_addr_a[32:31] = mcu2_drif_dram_addr_a[4:3];
5828 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5829 mcu2_physical_addr_b[32:31] = mcu2_drif_dram_addr_b[4:3];
5830 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5831 mcu2_physical_addr_c[32:31] = mcu2_drif_dram_addr_c[4:3];
5832 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5833 end
5834 000: begin
5835 mcu2_physical_addr_a[33:31] = mcu2_drif_dram_addr_a[5:3];
5836 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5837 mcu2_physical_addr_b[33:31] = mcu2_drif_dram_addr_b[5:3];
5838 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5839 mcu2_physical_addr_c[33:31] = mcu2_drif_dram_addr_c[5:3];
5840 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5841 end
5842 endcase
5843 end
5844 8'b0_0_1_00_001,
5845 8'b0_0_1_00_010,
5846 8'b0_0_1_00_100,
5847 8'b0_0_1_00_000: begin
5848 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[12:0],
5849 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5850 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5851 5'b00000};
5852 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[12:0],
5853 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5854 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5855 5'b00000};
5856 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[12:0],
5857 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5858 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5859 5'b00000};
5860 case(num_dimms)
5861 001: begin
5862 mcu2_physical_addr_a[31] = mcu2_drif_dram_addr_a[3];
5863 mcu2_physical_addr_a[10] = mcu2_drif_dram_rank_a;
5864 mcu2_physical_addr_b[31] = mcu2_drif_dram_addr_b[3];
5865 mcu2_physical_addr_b[10] = mcu2_drif_dram_rank_b;
5866 mcu2_physical_addr_c[31] = mcu2_drif_dram_addr_c[3];
5867 mcu2_physical_addr_c[10] = mcu2_drif_dram_rank_c;
5868 end
5869 010: begin
5870 mcu2_physical_addr_a[32:31] = mcu2_drif_dram_addr_a[4:3];
5871 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5872 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
5873 mcu2_physical_addr_b[32:31] = mcu2_drif_dram_addr_b[4:3];
5874 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5875 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
5876 mcu2_physical_addr_c[32:31] = mcu2_drif_dram_addr_c[4:3];
5877 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5878 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
5879 end
5880 100: begin
5881 mcu2_physical_addr_a[33:31] = mcu2_drif_dram_addr_a[5:3];
5882 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5883 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
5884 mcu2_physical_addr_b[33:31] = mcu2_drif_dram_addr_b[5:3];
5885 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5886 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5887 mcu2_physical_addr_c[33:31] = mcu2_drif_dram_addr_c[5:3];
5888 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5889 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
5890 end
5891 000: begin
5892 mcu2_physical_addr_a[34:31] = mcu2_drif_dram_addr_a[6:3];
5893 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5894 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
5895 mcu2_physical_addr_b[34:31] = mcu2_drif_dram_addr_b[6:3];
5896 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5897 mcu2_physical_addr_b[13] = mcu2_drif_dram_rank_b;
5898 mcu2_physical_addr_c[34:31] = mcu2_drif_dram_addr_c[6:3];
5899 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5900 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
5901 end
5902 endcase
5903 end
5904 8'b0_0_0_01_001,
5905 8'b0_0_0_01_010,
5906 8'b0_0_0_01_100,
5907 8'b0_0_0_01_000: begin
5908 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
5909 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5910 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5911 5'b00000};
5912 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
5913 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5914 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5915 5'b00000};
5916 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
5917 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5918 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5919 5'b00000};
5920 case(num_dimms)
5921 001: begin
5922 end
5923 010: begin
5924 mcu2_physical_addr_a[32] = mcu2_drif_dram_addr_a[3];
5925 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5926 mcu2_physical_addr_b[32] = mcu2_drif_dram_addr_b[3];
5927 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5928 mcu2_physical_addr_c[32] = mcu2_drif_dram_addr_c[3];
5929 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5930 end
5931 100: begin
5932 mcu2_physical_addr_a[33:32] = mcu2_drif_dram_addr_a[4:3];
5933 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5934 mcu2_physical_addr_b[33:32] = mcu2_drif_dram_addr_b[4:3];
5935 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5936 mcu2_physical_addr_c[33:32] = mcu2_drif_dram_addr_c[4:3];
5937 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5938 end
5939 000: begin
5940 mcu2_physical_addr_a[34:32] = mcu2_drif_dram_addr_a[5:3];
5941 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5942 mcu2_physical_addr_b[34:32] = mcu2_drif_dram_addr_b[5:3];
5943 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
5944 mcu2_physical_addr_c[34:32] = mcu2_drif_dram_addr_c[5:3];
5945 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
5946 end
5947 endcase
5948 end
5949 8'b0_0_1_01_001,
5950 8'b0_0_1_01_010,
5951 8'b0_0_1_01_100,
5952 8'b0_0_1_01_000: begin
5953 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
5954 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:3], mcu2_drif_dram_bank_a[1],
5955 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
5956 5'b00000};
5957 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
5958 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:3], mcu2_drif_dram_bank_b[1],
5959 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
5960 5'b00000};
5961 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
5962 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:3], mcu2_drif_dram_bank_c[1],
5963 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
5964 5'b00000};
5965 case(num_dimms)
5966 001: begin
5967 mcu2_physical_addr_a[32] = mcu2_drif_dram_addr_a[3];
5968 mcu2_physical_addr_a[10] = mcu2_drif_dram_rank_a;
5969 mcu2_physical_addr_b[32] = mcu2_drif_dram_addr_b[3];
5970 mcu2_physical_addr_b[10] = mcu2_drif_dram_rank_b;
5971 mcu2_physical_addr_c[32] = mcu2_drif_dram_addr_c[3];
5972 mcu2_physical_addr_c[10] = mcu2_drif_dram_rank_c;
5973 end
5974 010: begin
5975 mcu2_physical_addr_a[33:32] = mcu2_drif_dram_addr_a[4:3];
5976 mcu2_physical_addr_a[10] = mcu2_drif_dram_dimm_a[0];
5977 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
5978 mcu2_physical_addr_b[33:32] = mcu2_drif_dram_addr_b[4:3];
5979 mcu2_physical_addr_b[10] = mcu2_drif_dram_dimm_b[0];
5980 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
5981 mcu2_physical_addr_c[33:32] = mcu2_drif_dram_addr_c[4:3];
5982 mcu2_physical_addr_c[10] = mcu2_drif_dram_dimm_c[0];
5983 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
5984 end
5985 100: begin
5986 mcu2_physical_addr_a[34:32] = mcu2_drif_dram_addr_a[5:3];
5987 mcu2_physical_addr_a[11:10] = mcu2_drif_dram_dimm_a[1:0];
5988 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
5989 mcu2_physical_addr_b[34:32] = mcu2_drif_dram_addr_b[5:3];
5990 mcu2_physical_addr_b[11:10] = mcu2_drif_dram_dimm_b[1:0];
5991 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
5992 mcu2_physical_addr_c[34:32] = mcu2_drif_dram_addr_c[5:3];
5993 mcu2_physical_addr_c[11:10] = mcu2_drif_dram_dimm_c[1:0];
5994 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
5995 end
5996 000: begin
5997 mcu2_physical_addr_a[35:32] = mcu2_drif_dram_addr_a[6:3];
5998 mcu2_physical_addr_a[12:10] = mcu2_drif_dram_dimm_a[2:0];
5999 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
6000 mcu2_physical_addr_b[35:32] = mcu2_drif_dram_addr_b[6:3];
6001 mcu2_physical_addr_b[12:10] = mcu2_drif_dram_dimm_b[2:0];
6002 mcu2_physical_addr_b[13] = mcu2_drif_dram_rank_b;
6003 mcu2_physical_addr_c[35:32] = mcu2_drif_dram_addr_c[6:3];
6004 mcu2_physical_addr_c[12:10] = mcu2_drif_dram_dimm_c[2:0];
6005 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
6006 end
6007 endcase
6008 end
6009 8'b0_0_0_10_001,
6010 8'b0_0_0_10_010,
6011 8'b0_0_0_10_100,
6012 8'b0_0_0_10_000: begin
6013 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
6014 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
6015 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
6016 5'b00000};
6017 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
6018 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
6019 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
6020 5'b00000};
6021 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
6022 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
6023 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
6024 5'b00000};
6025 case(num_dimms)
6026 001: begin
6027 mcu2_physical_addr_a[32] = mcu2_drif_dram_addr_a[3];
6028 mcu2_physical_addr_b[32] = mcu2_drif_dram_addr_b[3];
6029 mcu2_physical_addr_c[32] = mcu2_drif_dram_addr_c[3];
6030 end
6031 010: begin
6032 mcu2_physical_addr_a[33:32] = mcu2_drif_dram_addr_a[4:3];
6033 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
6034 mcu2_physical_addr_b[33:32] = mcu2_drif_dram_addr_b[4:3];
6035 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
6036 mcu2_physical_addr_c[33:32] = mcu2_drif_dram_addr_c[4:3];
6037 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
6038 end
6039 100: begin
6040 mcu2_physical_addr_a[34:32] = mcu2_drif_dram_addr_a[5:3];
6041 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
6042 mcu2_physical_addr_b[34:32] = mcu2_drif_dram_addr_b[5:3];
6043 mcu2_physical_addr_b[12:11] = mcu2_drif_dram_dimm_b[1:0];
6044 mcu2_physical_addr_c[34:32] = mcu2_drif_dram_addr_c[5:3];
6045 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
6046 end
6047 000: begin
6048 mcu2_physical_addr_a[35:32] = mcu2_drif_dram_addr_a[6:3];
6049 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
6050 mcu2_physical_addr_b[35:32] = mcu2_drif_dram_addr_b[6:3];
6051 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
6052 mcu2_physical_addr_c[35:32] = mcu2_drif_dram_addr_c[6:3];
6053 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
6054 end
6055 endcase
6056 end
6057 8'b0_0_1_10_001,
6058 8'b0_0_1_10_010,
6059 8'b0_0_1_10_100,
6060 8'b0_0_1_10_000: begin
6061 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[13:0],
6062 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
6063 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
6064 5'b00000};
6065 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[13:0],
6066 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
6067 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
6068 5'b00000};
6069 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[13:0],
6070 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
6071 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
6072 5'b00000};
6073 case(num_dimms)
6074 001: begin
6075 mcu2_physical_addr_a[33:32] = mcu2_drif_dram_addr_a[4:3];
6076 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
6077 mcu2_physical_addr_b[33:32] = mcu2_drif_dram_addr_b[4:3];
6078 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
6079 mcu2_physical_addr_c[33:32] = mcu2_drif_dram_addr_c[4:3];
6080 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
6081 end
6082 010: begin
6083 mcu2_physical_addr_a[34:32] = mcu2_drif_dram_addr_a[5:3];
6084 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
6085 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
6086 mcu2_physical_addr_b[34:32] = mcu2_drif_dram_addr_b[5:3];
6087 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
6088 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
6089 mcu2_physical_addr_c[34:32] = mcu2_drif_dram_addr_c[5:3];
6090 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
6091 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
6092 end
6093 100: begin
6094 mcu2_physical_addr_a[35:32] = mcu2_drif_dram_addr_a[6:3];
6095 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
6096 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
6097 mcu2_physical_addr_b[35:32] = mcu2_drif_dram_addr_b[6:3];
6098 mcu2_physical_addr_b[12:11] = mcu2_drif_dram_dimm_b[1:0];
6099 mcu2_physical_addr_b[13] = mcu2_drif_dram_rank_b;
6100 mcu2_physical_addr_c[35:32] = mcu2_drif_dram_addr_c[6:3];
6101 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
6102 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
6103 end
6104 000: begin
6105 mcu2_physical_addr_a[36:32] = mcu2_drif_dram_addr_a[7:3];
6106 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
6107 mcu2_physical_addr_a[14] = mcu2_drif_dram_rank_a;
6108 mcu2_physical_addr_b[36:32] = mcu2_drif_dram_addr_b[7:3];
6109 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
6110 mcu2_physical_addr_b[14] = mcu2_drif_dram_rank_b;
6111 mcu2_physical_addr_c[36:32] = mcu2_drif_dram_addr_c[7:3];
6112 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
6113 mcu2_physical_addr_c[14] = mcu2_drif_dram_rank_c;
6114 end
6115 endcase
6116 end
6117 8'b0_0_0_11_001,
6118 8'b0_0_0_11_010,
6119 8'b0_0_0_11_100,
6120 8'b0_0_0_11_000: begin
6121 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[14:0],
6122 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
6123 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
6124 5'b00000};
6125 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[14:0],
6126 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
6127 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
6128 5'b00000};
6129 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[14:0],
6130 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
6131 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
6132 5'b00000};
6133 case(num_dimms)
6134 001: begin
6135 mcu2_physical_addr_a[33] = mcu2_drif_dram_addr_a[3];
6136 mcu2_physical_addr_b[33] = mcu2_drif_dram_addr_b[3];
6137 mcu2_physical_addr_c[33] = mcu2_drif_dram_addr_c[3];
6138 end
6139 010: begin
6140 mcu2_physical_addr_a[34:33] = mcu2_drif_dram_addr_a[4:3];
6141 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
6142 mcu2_physical_addr_b[34:33] = mcu2_drif_dram_addr_b[4:3];
6143 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
6144 mcu2_physical_addr_c[34:33] = mcu2_drif_dram_addr_c[4:3];
6145 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
6146 end
6147 100: begin
6148 mcu2_physical_addr_a[35:33] = mcu2_drif_dram_addr_a[5:3];
6149 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
6150 mcu2_physical_addr_b[35:33] = mcu2_drif_dram_addr_b[5:3];
6151 mcu2_physical_addr_b[12:11] = mcu2_drif_dram_dimm_b[1:0];
6152 mcu2_physical_addr_c[35:33] = mcu2_drif_dram_addr_c[5:3];
6153 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
6154 end
6155 000: begin
6156 mcu2_physical_addr_a[36:33] = mcu2_drif_dram_addr_a[6:3];
6157 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
6158 mcu2_physical_addr_b[36:33] = mcu2_drif_dram_addr_b[6:3];
6159 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
6160 mcu2_physical_addr_c[36:33] = mcu2_drif_dram_addr_c[6:3];
6161 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
6162 end
6163 endcase
6164 end
6165 8'b0_0_1_11_001,
6166 8'b0_0_1_11_010,
6167 8'b0_0_1_11_100,
6168 8'b0_0_1_11_000: begin
6169 mcu2_physical_addr_a = {mcu2_drif_dram_ras_addr_a[14:0],
6170 mcu2_drif_dram_addr_a[11],mcu2_drif_dram_addr_a[9:4], mcu2_drif_dram_bank_a[2:1],
6171 2'b10, mcu2_drif_dram_bank_a[0], mcu2_drif_dram_addr_a[2],
6172 5'b00000};
6173 mcu2_physical_addr_b = {mcu2_drif_dram_ras_addr_b[14:0],
6174 mcu2_drif_dram_addr_b[11],mcu2_drif_dram_addr_b[9:4], mcu2_drif_dram_bank_b[2:1],
6175 2'b10, mcu2_drif_dram_bank_b[0], mcu2_drif_dram_addr_b[2],
6176 5'b00000};
6177 mcu2_physical_addr_c = {mcu2_drif_dram_ras_addr_c[14:0],
6178 mcu2_drif_dram_addr_c[11],mcu2_drif_dram_addr_c[9:4], mcu2_drif_dram_bank_c[2:1],
6179 2'b10, mcu2_drif_dram_bank_c[0], mcu2_drif_dram_addr_c[2],
6180 5'b00000};
6181 case(num_dimms)
6182 001: begin
6183 mcu2_physical_addr_a[34:33] = mcu2_drif_dram_addr_a[4:3];
6184 mcu2_physical_addr_a[11] = mcu2_drif_dram_rank_a;
6185 mcu2_physical_addr_b[34:33] = mcu2_drif_dram_addr_b[4:3];
6186 mcu2_physical_addr_b[11] = mcu2_drif_dram_rank_b;
6187 mcu2_physical_addr_c[34:33] = mcu2_drif_dram_addr_c[4:3];
6188 mcu2_physical_addr_c[11] = mcu2_drif_dram_rank_c;
6189 end
6190 010: begin
6191 mcu2_physical_addr_a[35:33] = mcu2_drif_dram_addr_a[5:3];
6192 mcu2_physical_addr_a[11] = mcu2_drif_dram_dimm_a[0];
6193 mcu2_physical_addr_a[12] = mcu2_drif_dram_rank_a;
6194 mcu2_physical_addr_b[35:33] = mcu2_drif_dram_addr_b[5:3];
6195 mcu2_physical_addr_b[11] = mcu2_drif_dram_dimm_b[0];
6196 mcu2_physical_addr_b[12] = mcu2_drif_dram_rank_b;
6197 mcu2_physical_addr_c[35:33] = mcu2_drif_dram_addr_c[5:3];
6198 mcu2_physical_addr_c[11] = mcu2_drif_dram_dimm_c[0];
6199 mcu2_physical_addr_c[12] = mcu2_drif_dram_rank_c;
6200 end
6201 100: begin
6202 mcu2_physical_addr_a[36:33] = mcu2_drif_dram_addr_a[6:3];
6203 mcu2_physical_addr_a[12:11] = mcu2_drif_dram_dimm_a[1:0];
6204 mcu2_physical_addr_a[13] = mcu2_drif_dram_rank_a;
6205 mcu2_physical_addr_b[36:33] = mcu2_drif_dram_addr_b[6:3];
6206 mcu2_physical_addr_b[12:11] = mcu2_drif_dram_dimm_b[1:0];
6207 mcu2_physical_addr_b[13] = mcu2_drif_dram_rank_b;
6208 mcu2_physical_addr_c[36:33] = mcu2_drif_dram_addr_c[6:3];
6209 mcu2_physical_addr_c[12:11] = mcu2_drif_dram_dimm_c[1:0];
6210 mcu2_physical_addr_c[13] = mcu2_drif_dram_rank_c;
6211 end
6212 000: begin
6213 mcu2_physical_addr_a[37:33] = mcu2_drif_dram_addr_a[7:3];
6214 mcu2_physical_addr_a[13:11] = mcu2_drif_dram_dimm_a[2:0];
6215 mcu2_physical_addr_a[14] = mcu2_drif_dram_rank_a;
6216 mcu2_physical_addr_b[37:33] = mcu2_drif_dram_addr_b[7:3];
6217 mcu2_physical_addr_b[13:11] = mcu2_drif_dram_dimm_b[2:0];
6218 mcu2_physical_addr_b[14] = mcu2_drif_dram_rank_b;
6219 mcu2_physical_addr_c[37:33] = mcu2_drif_dram_addr_c[7:3];
6220 mcu2_physical_addr_c[13:11] = mcu2_drif_dram_dimm_c[2:0];
6221 mcu2_physical_addr_c[14] = mcu2_drif_dram_rank_c;
6222 end
6223 endcase
6224 end
6225 endcase
6226
6227 //----------------------------------------------------------------------------------------------
6228 // M C U 3 - phys addr gen
6229 //----------------------------------------------------------------------------------------------
6230
6231
6232 mcu3_physical_addr_a = 40'b0;
6233 mcu3_physical_addr_b = 40'b0;
6234 mcu3_physical_addr_c = 40'b0;
6235
6236 case({chnl_type, rank_addr, rank, dimm_size, num_dimms})
6237
6238 //-------------------------------
6239 // DUAL CHANNEL, RANK HIGH
6240 //-------------------------------
6241
6242 8'b1_1_0_00_001,
6243 8'b1_1_0_00_010,
6244 8'b1_1_0_00_100,
6245 8'b1_1_0_00_000: begin
6246 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[12:0],
6247 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2],
6248 mcu3_drif_dram_bank_a[1], 2'b11, mcu3_drif_dram_bank_a[0],
6249 mcu3_drif_dram_addr_a[1], 5'b00000};
6250 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[12:0],
6251 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2],
6252 mcu3_drif_dram_bank_b[1], 2'b11, mcu3_drif_dram_bank_b[0],
6253 mcu3_drif_dram_addr_b[1], 5'b00000};
6254 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[12:0],
6255 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2],
6256 mcu3_drif_dram_bank_c[1], 2'b11, mcu3_drif_dram_bank_c[0],
6257 mcu3_drif_dram_addr_c[1], 5'b00000};
6258 end
6259 8'b1_1_1_00_001,
6260 8'b1_1_1_00_010,
6261 8'b1_1_1_00_100,
6262 8'b1_1_1_00_000: begin
6263 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[12:0],
6264 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2],
6265 mcu3_drif_dram_bank_a[1], 2'b11, mcu3_drif_dram_bank_a[0],
6266 mcu3_drif_dram_addr_a[1], 5'b00000};
6267 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[12:0],
6268 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2],
6269 mcu3_drif_dram_bank_b[1], 2'b11, mcu3_drif_dram_bank_b[0],
6270 mcu3_drif_dram_addr_b[1], 5'b00000};
6271 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[12:0],
6272 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2],
6273 mcu3_drif_dram_bank_c[1], 2'b11, mcu3_drif_dram_bank_c[0],
6274 mcu3_drif_dram_addr_c[1], 5'b00000};
6275 case(num_dimms)
6276 001: begin
6277 mcu3_physical_addr_a[32] = mcu3_drif_dram_rank_a;
6278 mcu3_physical_addr_b[32] = mcu3_drif_dram_rank_b;
6279 mcu3_physical_addr_c[32] = mcu3_drif_dram_rank_c;
6280 end
6281 010: begin
6282 mcu3_physical_addr_a[33] = mcu3_drif_dram_rank_a;
6283 mcu3_physical_addr_b[33] = mcu3_drif_dram_rank_b;
6284 mcu3_physical_addr_c[33] = mcu3_drif_dram_rank_c;
6285 end
6286 100: begin
6287 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6288 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6289 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6290 end
6291 000: begin
6292 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6293 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6294 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6295 end
6296 endcase
6297 end
6298 8'b1_1_0_01_001,
6299 8'b1_1_0_01_010,
6300 8'b1_1_0_01_100,
6301 8'b1_1_0_01_000: begin
6302 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[13:0],
6303 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2],
6304 mcu3_drif_dram_bank_a[1], 2'b11, mcu3_drif_dram_bank_a[0],
6305 mcu3_drif_dram_addr_a[1], 5'b00000};
6306 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[13:0],
6307 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2],
6308 mcu3_drif_dram_bank_b[1], 2'b11, mcu3_drif_dram_bank_b[0],
6309 mcu3_drif_dram_addr_b[1], 5'b00000};
6310 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[13:0],
6311 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2],
6312 mcu3_drif_dram_bank_c[1], 2'b11, mcu3_drif_dram_bank_c[0],
6313 mcu3_drif_dram_addr_c[1], 5'b00000};
6314 end
6315 8'b1_1_1_01_001,
6316 8'b1_1_1_01_010,
6317 8'b1_1_1_01_100,
6318 8'b1_1_1_01_000: begin
6319 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[13:0],
6320 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2],
6321 mcu3_drif_dram_bank_a[1], 2'b11, mcu3_drif_dram_bank_a[0],
6322 mcu3_drif_dram_addr_a[1], 5'b00000};
6323 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[13:0],
6324 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2],
6325 mcu3_drif_dram_bank_b[1], 2'b11, mcu3_drif_dram_bank_b[0],
6326 mcu3_drif_dram_addr_b[1], 5'b00000};
6327 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[13:0],
6328 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2],
6329 mcu3_drif_dram_bank_c[1], 2'b11, mcu3_drif_dram_bank_c[0],
6330 mcu3_drif_dram_addr_c[1], 5'b00000};
6331 case(num_dimms)
6332 001: begin
6333 mcu3_physical_addr_a[33] = mcu3_drif_dram_rank_a;
6334 mcu3_physical_addr_b[33] = mcu3_drif_dram_rank_b;
6335 mcu3_physical_addr_c[33] = mcu3_drif_dram_rank_c;
6336 end
6337 010: begin
6338 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6339 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6340 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6341 end
6342 100: begin
6343 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6344 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6345 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6346 end
6347 000: begin
6348 mcu3_physical_addr_a[36] = mcu3_drif_dram_rank_a;
6349 mcu3_physical_addr_b[36] = mcu3_drif_dram_rank_b;
6350 mcu3_physical_addr_c[36] = mcu3_drif_dram_rank_c;
6351 end
6352 endcase
6353 end
6354 8'b1_1_0_10_001,
6355 8'b1_1_0_10_010,
6356 8'b1_1_0_10_100,
6357 8'b1_1_0_10_000: begin
6358 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[2],
6359 mcu3_drif_dram_ras_addr_a[13:0], mcu3_drif_dram_addr_a[11],
6360 mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[2:1],
6361 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1], 5'b00000};
6362 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[2],
6363 mcu3_drif_dram_ras_addr_b[13:0], mcu3_drif_dram_addr_b[11],
6364 mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[2:1],
6365 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1], 5'b00000};
6366 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[2],
6367 mcu3_drif_dram_ras_addr_c[13:0], mcu3_drif_dram_addr_c[11],
6368 mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[2:1],
6369 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1], 5'b00000};
6370 end
6371 8'b1_1_1_10_001,
6372 8'b1_1_1_10_010,
6373 8'b1_1_1_10_100,
6374 8'b1_1_1_10_000: begin
6375 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[2],
6376 mcu3_drif_dram_ras_addr_a[13:0], mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3],
6377 mcu3_drif_dram_bank_a[2:1], 2'b11, mcu3_drif_dram_bank_a[0],
6378 mcu3_drif_dram_addr_a[1], 5'b00000};
6379 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[2],
6380 mcu3_drif_dram_ras_addr_b[13:0], mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3],
6381 mcu3_drif_dram_bank_b[2:1], 2'b11, mcu3_drif_dram_bank_b[0],
6382 mcu3_drif_dram_addr_b[1], 5'b00000};
6383 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[2],
6384 mcu3_drif_dram_ras_addr_c[13:0], mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3],
6385 mcu3_drif_dram_bank_c[2:1], 2'b11, mcu3_drif_dram_bank_c[0],
6386 mcu3_drif_dram_addr_c[1], 5'b00000};
6387 case(num_dimms)
6388 001: begin
6389 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6390 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6391 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6392 end
6393 010: begin
6394 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6395 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6396 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6397 end
6398 100: begin
6399 mcu3_physical_addr_a[36] = mcu3_drif_dram_rank_a;
6400 mcu3_physical_addr_b[36] = mcu3_drif_dram_rank_b;
6401 mcu3_physical_addr_c[36] = mcu3_drif_dram_rank_c;
6402 end
6403 000: begin
6404 mcu3_physical_addr_a[37] = mcu3_drif_dram_rank_a;
6405 mcu3_physical_addr_b[37] = mcu3_drif_dram_rank_b;
6406 mcu3_physical_addr_c[37] = mcu3_drif_dram_rank_c;
6407 end
6408 endcase
6409 end
6410 8'b1_1_0_11_001,
6411 8'b1_1_0_11_010,
6412 8'b1_1_0_11_100,
6413 8'b1_1_0_11_000: begin
6414 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[2],
6415 mcu3_drif_dram_ras_addr_a[14:0], mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3],
6416 mcu3_drif_dram_bank_a[2:1], 2'b11, mcu3_drif_dram_bank_a[0],
6417 mcu3_drif_dram_addr_a[1], 5'b00000};
6418 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[2],
6419 mcu3_drif_dram_ras_addr_b[14:0], mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3],
6420 mcu3_drif_dram_bank_b[2:1], 2'b11, mcu3_drif_dram_bank_b[0],
6421 mcu3_drif_dram_addr_b[1], 5'b00000};
6422 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[2],
6423 mcu3_drif_dram_ras_addr_c[14:0], mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3],
6424 mcu3_drif_dram_bank_c[2:1], 2'b11, mcu3_drif_dram_bank_c[0],
6425 mcu3_drif_dram_addr_c[1], 5'b00000};
6426 end
6427 8'b1_1_1_11_001,
6428 8'b1_1_1_11_010,
6429 8'b1_1_1_11_100,
6430 8'b1_1_1_11_000: begin
6431 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[2],
6432 mcu3_drif_dram_ras_addr_a[14:0], mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3],
6433 mcu3_drif_dram_bank_a[2:1], 2'b11, mcu3_drif_dram_bank_a[0],
6434 mcu3_drif_dram_addr_a[1], 5'b00000};
6435 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[2],
6436 mcu3_drif_dram_ras_addr_b[14:0], mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3],
6437 mcu3_drif_dram_bank_b[2:1], 2'b11, mcu3_drif_dram_bank_b[0],
6438 mcu3_drif_dram_addr_b[1], 5'b00000};
6439 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[2],
6440 mcu3_drif_dram_ras_addr_c[14:0], mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3],
6441 mcu3_drif_dram_bank_c[2:1], 2'b11, mcu3_drif_dram_bank_c[0],
6442 mcu3_drif_dram_addr_c[1], 5'b00000};
6443 case(num_dimms)
6444 001: begin
6445 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6446 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6447 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6448 end
6449 010: begin
6450 mcu3_physical_addr_a[36] = mcu3_drif_dram_rank_a;
6451 mcu3_physical_addr_b[36] = mcu3_drif_dram_rank_b;
6452 mcu3_physical_addr_c[36] = mcu3_drif_dram_rank_c;
6453 end
6454 100: begin
6455 mcu3_physical_addr_a[37] = mcu3_drif_dram_rank_a;
6456 mcu3_physical_addr_b[37] = mcu3_drif_dram_rank_b;
6457 mcu3_physical_addr_c[37] = mcu3_drif_dram_rank_c;
6458 end
6459 000: begin
6460 mcu3_physical_addr_a[38] = mcu3_drif_dram_rank_a;
6461 mcu3_physical_addr_b[38] = mcu3_drif_dram_rank_b;
6462 mcu3_physical_addr_c[38] = mcu3_drif_dram_rank_c;
6463 end
6464 endcase
6465 end
6466
6467 //---------------------------
6468 // SINGLE CHANNEL, RANK HIGH
6469 //---------------------------
6470
6471 8'b0_1_0_00_001,
6472 8'b0_1_0_00_010,
6473 8'b0_1_0_00_100,
6474 8'b0_1_0_00_000: begin
6475 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[12:0],
6476 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
6477 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6478 5'b00000};
6479 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[12:0],
6480 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
6481 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6482 5'b00000};
6483 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[12:0],
6484 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
6485 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6486 5'b00000};
6487 end
6488 8'b0_1_1_00_001,
6489 8'b0_1_1_00_010,
6490 8'b0_1_1_00_100,
6491 8'b0_1_1_00_000: begin
6492 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[12:0],
6493 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
6494 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6495 5'b00000};
6496 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[12:0],
6497 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
6498 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6499 5'b00000};
6500 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[12:0],
6501 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
6502 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6503 5'b00000};
6504 case(num_dimms)
6505 001: begin
6506 mcu3_physical_addr_a[31] = mcu3_drif_dram_rank_a;
6507 mcu3_physical_addr_b[31] = mcu3_drif_dram_rank_b;
6508 mcu3_physical_addr_c[31] = mcu3_drif_dram_rank_c;
6509 end
6510 010: begin
6511 mcu3_physical_addr_a[32] = mcu3_drif_dram_rank_a;
6512 mcu3_physical_addr_b[32] = mcu3_drif_dram_rank_b;
6513 mcu3_physical_addr_c[32] = mcu3_drif_dram_rank_c;
6514 end
6515 100: begin
6516 mcu3_physical_addr_a[33] = mcu3_drif_dram_rank_a;
6517 mcu3_physical_addr_b[33] = mcu3_drif_dram_rank_b;
6518 mcu3_physical_addr_c[33] = mcu3_drif_dram_rank_c;
6519 end
6520 000: begin
6521 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6522 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6523 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6524 end
6525 endcase
6526 end
6527 8'b0_1_0_01_001,
6528 8'b0_1_0_01_010,
6529 8'b0_1_0_01_100,
6530 8'b0_1_0_01_000: begin
6531 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[13:0],
6532 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
6533 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6534 5'b00000};
6535 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[13:0],
6536 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
6537 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6538 5'b00000};
6539 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[13:0],
6540 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
6541 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6542 5'b00000};
6543 end
6544 8'b0_1_1_01_001,
6545 8'b0_1_1_01_010,
6546 8'b0_1_1_01_100,
6547 8'b0_1_1_01_000: begin
6548 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_ras_addr_a[13:0],
6549 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
6550 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6551 5'b00000};
6552 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_ras_addr_b[13:0],
6553 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
6554 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6555 5'b00000};
6556 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_ras_addr_c[13:0],
6557 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
6558 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6559 5'b00000};
6560 case(num_dimms)
6561 001: begin
6562 mcu3_physical_addr_a[32] = mcu3_drif_dram_rank_a;
6563 mcu3_physical_addr_b[32] = mcu3_drif_dram_rank_b;
6564 mcu3_physical_addr_c[32] = mcu3_drif_dram_rank_c;
6565 end
6566 010: begin
6567 mcu3_physical_addr_a[33] = mcu3_drif_dram_rank_a;
6568 mcu3_physical_addr_b[33] = mcu3_drif_dram_rank_b;
6569 mcu3_physical_addr_c[33] = mcu3_drif_dram_rank_c;
6570 end
6571 100: begin
6572 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6573 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6574 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6575 end
6576 000: begin
6577 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6578 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6579 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6580 end
6581 endcase
6582 end
6583 8'b0_1_0_10_001,
6584 8'b0_1_0_10_010,
6585 8'b0_1_0_10_100,
6586 8'b0_1_0_10_000: begin
6587 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[3],
6588 mcu3_drif_dram_ras_addr_a[13:0],
6589 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
6590 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6591 5'b00000};
6592 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[3],
6593 mcu3_drif_dram_ras_addr_b[13:0],
6594 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
6595 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6596 5'b00000};
6597 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[3],
6598 mcu3_drif_dram_ras_addr_c[13:0],
6599 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
6600 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6601 5'b00000};
6602 end
6603 8'b0_1_1_10_001,
6604 8'b0_1_1_10_010,
6605 8'b0_1_1_10_100,
6606 8'b0_1_1_10_000: begin
6607 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[3],
6608 mcu3_drif_dram_ras_addr_a[13:0],
6609 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
6610 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6611 5'b00000};
6612 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[3],
6613 mcu3_drif_dram_ras_addr_b[13:0],
6614 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
6615 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6616 5'b00000};
6617 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[3],
6618 mcu3_drif_dram_ras_addr_c[13:0],
6619 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
6620 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6621 5'b00000};
6622 case(num_dimms)
6623 001: begin
6624 mcu3_physical_addr_a[33] = mcu3_drif_dram_rank_a;
6625 mcu3_physical_addr_b[33] = mcu3_drif_dram_rank_b;
6626 mcu3_physical_addr_c[33] = mcu3_drif_dram_rank_c;
6627 end
6628 010: begin
6629 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6630 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6631 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6632 end
6633 100: begin
6634 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6635 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6636 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6637 end
6638 000: begin
6639 mcu3_physical_addr_a[36] = mcu3_drif_dram_rank_a;
6640 mcu3_physical_addr_b[36] = mcu3_drif_dram_rank_b;
6641 mcu3_physical_addr_c[36] = mcu3_drif_dram_rank_c;
6642 end
6643 endcase
6644 end
6645 8'b0_1_0_11_001,
6646 8'b0_1_0_11_010,
6647 8'b0_1_0_11_100,
6648 8'b0_1_0_11_000: begin
6649 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[3],
6650 mcu3_drif_dram_ras_addr_a[14:0],
6651 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
6652 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6653 5'b00000};
6654 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[3],
6655 mcu3_drif_dram_ras_addr_b[14:0],
6656 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
6657 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6658 5'b00000};
6659 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[3],
6660 mcu3_drif_dram_ras_addr_c[14:0],
6661 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
6662 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6663 5'b00000};
6664 end
6665 8'b0_1_1_11_001,
6666 8'b0_1_1_11_010,
6667 8'b0_1_1_11_100,
6668 8'b0_1_1_11_000: begin
6669 mcu3_physical_addr_a = {mcu3_drif_dram_dimm_a, mcu3_drif_dram_addr_a[3],
6670 mcu3_drif_dram_ras_addr_a[14:0],
6671 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
6672 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
6673 5'b00000};
6674 mcu3_physical_addr_b = {mcu3_drif_dram_dimm_b, mcu3_drif_dram_addr_b[3],
6675 mcu3_drif_dram_ras_addr_b[14:0],
6676 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
6677 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
6678 5'b00000};
6679 mcu3_physical_addr_c = {mcu3_drif_dram_dimm_c, mcu3_drif_dram_addr_c[3],
6680 mcu3_drif_dram_ras_addr_c[14:0],
6681 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
6682 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
6683 5'b00000};
6684 case(num_dimms)
6685 001: begin
6686 mcu3_physical_addr_a[34] = mcu3_drif_dram_rank_a;
6687 mcu3_physical_addr_b[34] = mcu3_drif_dram_rank_b;
6688 mcu3_physical_addr_c[34] = mcu3_drif_dram_rank_c;
6689 end
6690 010: begin
6691 mcu3_physical_addr_a[35] = mcu3_drif_dram_rank_a;
6692 mcu3_physical_addr_b[35] = mcu3_drif_dram_rank_b;
6693 mcu3_physical_addr_c[35] = mcu3_drif_dram_rank_c;
6694 end
6695 100: begin
6696 mcu3_physical_addr_a[36] = mcu3_drif_dram_rank_a;
6697 mcu3_physical_addr_b[36] = mcu3_drif_dram_rank_b;
6698 mcu3_physical_addr_c[36] = mcu3_drif_dram_rank_c;
6699 end
6700 000: begin
6701 mcu3_physical_addr_a[37] = mcu3_drif_dram_rank_a;
6702 mcu3_physical_addr_b[37] = mcu3_drif_dram_rank_b;
6703 mcu3_physical_addr_c[37] = mcu3_drif_dram_rank_c;
6704 end
6705 endcase
6706 end
6707
6708 //---------------------------
6709 // DUAL CHANNEL, RANK LOW
6710 //---------------------------
6711
6712 8'b1_0_0_00_001,
6713 8'b1_0_0_00_010,
6714 8'b1_0_0_00_100,
6715 8'b1_0_0_00_000: begin
6716 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[12:0],
6717 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2], mcu3_drif_dram_bank_a[1],
6718 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
6719 5'b00000};
6720 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[12:0],
6721 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2], mcu3_drif_dram_bank_b[1],
6722 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
6723 5'b00000};
6724 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[12:0],
6725 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2], mcu3_drif_dram_bank_c[1],
6726 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
6727 5'b00000};
6728 case(num_dimms)
6729 001: begin
6730 end
6731 010: begin
6732 mcu3_physical_addr_a[32] = mcu3_drif_dram_addr_a[2];
6733 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
6734 mcu3_physical_addr_b[32] = mcu3_drif_dram_addr_b[2];
6735 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
6736 mcu3_physical_addr_c[32] = mcu3_drif_dram_addr_c[2];
6737 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
6738 end
6739 100: begin
6740 mcu3_physical_addr_a[33:32] = mcu3_drif_dram_addr_a[3:2];
6741 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
6742 mcu3_physical_addr_b[33:32] = mcu3_drif_dram_addr_b[3:2];
6743 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
6744 mcu3_physical_addr_c[33:32] = mcu3_drif_dram_addr_c[3:2];
6745 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
6746 end
6747 000: begin
6748 mcu3_physical_addr_a[34:32] = mcu3_drif_dram_addr_a[4:2];
6749 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
6750 mcu3_physical_addr_b[34:32] = mcu3_drif_dram_addr_b[4:2];
6751 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
6752 mcu3_physical_addr_c[34:32] = mcu3_drif_dram_addr_c[4:2];
6753 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
6754 end
6755 endcase
6756 end
6757 8'b1_0_1_00_001,
6758 8'b1_0_1_00_010,
6759 8'b1_0_1_00_100,
6760 8'b1_0_1_00_000: begin
6761 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[12:0],
6762 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2], mcu3_drif_dram_bank_a[1],
6763 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
6764 5'b00000};
6765 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[12:0],
6766 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2], mcu3_drif_dram_bank_b[1],
6767 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
6768 5'b00000};
6769 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[12:0],
6770 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2], mcu3_drif_dram_bank_c[1],
6771 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
6772 5'b00000};
6773 case(num_dimms)
6774 001: begin
6775 mcu3_physical_addr_a[32] = mcu3_drif_dram_addr_a[2];
6776 mcu3_physical_addr_a[10] = mcu3_drif_dram_rank_a;
6777 mcu3_physical_addr_b[32] = mcu3_drif_dram_addr_b[2];
6778 mcu3_physical_addr_b[10] = mcu3_drif_dram_rank_b;
6779 mcu3_physical_addr_c[32] = mcu3_drif_dram_addr_c[2];
6780 mcu3_physical_addr_c[10] = mcu3_drif_dram_rank_c;
6781 end
6782 010: begin
6783 mcu3_physical_addr_a[33:32] = mcu3_drif_dram_addr_a[3:2];
6784 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
6785 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
6786 mcu3_physical_addr_b[33:32] = mcu3_drif_dram_addr_b[3:2];
6787 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
6788 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
6789 mcu3_physical_addr_c[33:32] = mcu3_drif_dram_addr_c[3:2];
6790 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
6791 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
6792 end
6793 100: begin
6794 mcu3_physical_addr_a[34:32] = mcu3_drif_dram_addr_a[4:2];
6795 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
6796 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
6797 mcu3_physical_addr_b[34:32] = mcu3_drif_dram_addr_b[4:2];
6798 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
6799 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
6800 mcu3_physical_addr_c[34:32] = mcu3_drif_dram_addr_c[4:2];
6801 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
6802 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
6803 end
6804 000: begin
6805 mcu3_physical_addr_a[35:32] = mcu3_drif_dram_addr_a[5:2];
6806 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
6807 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
6808 mcu3_physical_addr_b[35:32] = mcu3_drif_dram_addr_b[5:2];
6809 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
6810 mcu3_physical_addr_b[13] = mcu3_drif_dram_rank_b;
6811 mcu3_physical_addr_c[35:32] = mcu3_drif_dram_addr_c[5:2];
6812 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
6813 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
6814 end
6815 endcase
6816 end
6817 8'b1_0_0_01_001,
6818 8'b1_0_0_01_010,
6819 8'b1_0_0_01_100,
6820 8'b1_0_0_01_000: begin
6821 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
6822 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2], mcu3_drif_dram_bank_a[1],
6823 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
6824 5'b00000};
6825 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
6826 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2], mcu3_drif_dram_bank_b[1],
6827 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
6828 5'b00000};
6829 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
6830 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2], mcu3_drif_dram_bank_c[1],
6831 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
6832 5'b00000};
6833 case(num_dimms)
6834 001: begin
6835 end
6836 010: begin
6837 mcu3_physical_addr_a[33] = mcu3_drif_dram_addr_a[2];
6838 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
6839 mcu3_physical_addr_b[33] = mcu3_drif_dram_addr_b[2];
6840 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
6841 mcu3_physical_addr_c[33] = mcu3_drif_dram_addr_c[2];
6842 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
6843 end
6844 100: begin
6845 mcu3_physical_addr_a[34:33] = mcu3_drif_dram_addr_a[3:2];
6846 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
6847 mcu3_physical_addr_b[34:33] = mcu3_drif_dram_addr_b[3:2];
6848 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
6849 mcu3_physical_addr_c[34:33] = mcu3_drif_dram_addr_c[3:2];
6850 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
6851 end
6852 000: begin
6853 mcu3_physical_addr_a[35:33] = mcu3_drif_dram_addr_a[4:2];
6854 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
6855 mcu3_physical_addr_b[35:33] = mcu3_drif_dram_addr_b[4:2];
6856 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
6857 mcu3_physical_addr_c[35:33] = mcu3_drif_dram_addr_c[4:2];
6858 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
6859 end
6860 endcase
6861 end
6862 8'b1_0_1_01_001,
6863 8'b1_0_1_01_010,
6864 8'b1_0_1_01_100,
6865 8'b1_0_1_01_000: begin
6866 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
6867 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2], mcu3_drif_dram_bank_a[1],
6868 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
6869 5'b00000};
6870 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
6871 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2], mcu3_drif_dram_bank_b[1],
6872 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
6873 5'b00000};
6874 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
6875 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2], mcu3_drif_dram_bank_c[1],
6876 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
6877 5'b00000};
6878 case(num_dimms)
6879 001: begin
6880 mcu3_physical_addr_a[33] = mcu3_drif_dram_addr_a[2];
6881 mcu3_physical_addr_a[10] = mcu3_drif_dram_rank_a;
6882 mcu3_physical_addr_b[33] = mcu3_drif_dram_addr_b[2];
6883 mcu3_physical_addr_b[10] = mcu3_drif_dram_rank_b;
6884 mcu3_physical_addr_c[33] = mcu3_drif_dram_addr_c[2];
6885 mcu3_physical_addr_c[10] = mcu3_drif_dram_rank_c;
6886 end
6887 010: begin
6888 mcu3_physical_addr_a[34:33] = mcu3_drif_dram_addr_a[3:2];
6889 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
6890 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
6891 mcu3_physical_addr_b[34:33] = mcu3_drif_dram_addr_b[3:2];
6892 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
6893 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
6894 mcu3_physical_addr_c[34:33] = mcu3_drif_dram_addr_c[3:2];
6895 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
6896 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
6897 end
6898 100: begin
6899 mcu3_physical_addr_a[35:33] = mcu3_drif_dram_addr_a[4:2];
6900 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
6901 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
6902 mcu3_physical_addr_b[35:33] = mcu3_drif_dram_addr_b[4:2];
6903 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
6904 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
6905 mcu3_physical_addr_c[35:33] = mcu3_drif_dram_addr_c[4:2];
6906 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
6907 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
6908 end
6909 000: begin
6910 mcu3_physical_addr_a[36:33] = mcu3_drif_dram_addr_a[5:2];
6911 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
6912 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
6913 mcu3_physical_addr_b[36:33] = mcu3_drif_dram_addr_b[5:2];
6914 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
6915 mcu3_physical_addr_b[13] = mcu3_drif_dram_rank_b;
6916 mcu3_physical_addr_c[36:33] = mcu3_drif_dram_addr_c[5:2];
6917 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
6918 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
6919 end
6920 endcase
6921 end
6922 8'b1_0_0_10_001,
6923 8'b1_0_0_10_010,
6924 8'b1_0_0_10_100,
6925 8'b1_0_0_10_000: begin
6926 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
6927 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[2:1],
6928 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
6929 5'b00000};
6930 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
6931 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[2:1],
6932 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
6933 5'b00000};
6934 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
6935 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[2:1],
6936 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
6937 5'b00000};
6938 case(num_dimms)
6939 001: begin
6940 mcu3_physical_addr_a[33] = mcu3_drif_dram_addr_a[2];
6941 mcu3_physical_addr_b[33] = mcu3_drif_dram_addr_b[2];
6942 mcu3_physical_addr_c[33] = mcu3_drif_dram_addr_c[2];
6943 end
6944 010: begin
6945 mcu3_physical_addr_a[34:33] = mcu3_drif_dram_addr_a[3:2];
6946 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
6947 mcu3_physical_addr_b[34:33] = mcu3_drif_dram_addr_b[3:2];
6948 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
6949 mcu3_physical_addr_c[34:33] = mcu3_drif_dram_addr_c[3:2];
6950 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
6951 end
6952 100: begin
6953 mcu3_physical_addr_a[35:33] = mcu3_drif_dram_addr_a[4:2];
6954 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
6955 mcu3_physical_addr_b[35:33] = mcu3_drif_dram_addr_b[4:2];
6956 mcu3_physical_addr_b[12:11] = mcu3_drif_dram_dimm_b[1:0];
6957 mcu3_physical_addr_c[35:33] = mcu3_drif_dram_addr_c[4:2];
6958 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
6959 end
6960 000: begin
6961 mcu3_physical_addr_a[36:33] = mcu3_drif_dram_addr_a[5:2];
6962 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
6963 mcu3_physical_addr_b[36:33] = mcu3_drif_dram_addr_b[5:2];
6964 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
6965 mcu3_physical_addr_c[36:33] = mcu3_drif_dram_addr_c[5:2];
6966 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
6967 end
6968 endcase
6969 end
6970 8'b1_0_1_10_001,
6971 8'b1_0_1_10_010,
6972 8'b1_0_1_10_100,
6973 8'b1_0_1_10_000: begin
6974 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
6975 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2], mcu3_drif_dram_bank_a[1],
6976 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
6977 5'b00000};
6978 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
6979 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2], mcu3_drif_dram_bank_b[1],
6980 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
6981 5'b00000};
6982 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
6983 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2], mcu3_drif_dram_bank_c[1],
6984 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
6985 5'b00000};
6986 case(num_dimms)
6987 001: begin
6988 mcu3_physical_addr_a[34:33] = mcu3_drif_dram_addr_a[3:2];
6989 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
6990 mcu3_physical_addr_b[34:33] = mcu3_drif_dram_addr_b[3:2];
6991 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
6992 mcu3_physical_addr_c[34:33] = mcu3_drif_dram_addr_c[3:2];
6993 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
6994 end
6995 010: begin
6996 mcu3_physical_addr_a[35:33] = mcu3_drif_dram_addr_a[4:2];
6997 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
6998 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
6999 mcu3_physical_addr_b[35:33] = mcu3_drif_dram_addr_b[4:2];
7000 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7001 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7002 mcu3_physical_addr_c[35:33] = mcu3_drif_dram_addr_c[4:2];
7003 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7004 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
7005 end
7006 100: begin
7007 mcu3_physical_addr_a[36:33] = mcu3_drif_dram_addr_a[5:2];
7008 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7009 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
7010 mcu3_physical_addr_b[36:33] = mcu3_drif_dram_addr_b[5:2];
7011 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[1:0];
7012 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7013 mcu3_physical_addr_c[36:33] = mcu3_drif_dram_addr_c[5:2];
7014 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7015 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
7016 end
7017 000: begin
7018 mcu3_physical_addr_a[37:33] = mcu3_drif_dram_addr_a[5:2];
7019 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7020 mcu3_physical_addr_a[14] = mcu3_drif_dram_rank_a;
7021 mcu3_physical_addr_b[37:33] = mcu3_drif_dram_addr_b[5:2];
7022 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7023 mcu3_physical_addr_b[14] = mcu3_drif_dram_rank_b;
7024 mcu3_physical_addr_c[37:33] = mcu3_drif_dram_addr_c[5:2];
7025 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7026 mcu3_physical_addr_c[14] = mcu3_drif_dram_rank_c;
7027 end
7028 endcase
7029 end
7030 8'b1_0_0_11_001,
7031 8'b1_0_0_11_010,
7032 8'b1_0_0_11_100,
7033 8'b1_0_0_11_000: begin
7034 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[14:0],
7035 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[2:1],
7036 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
7037 5'b00000};
7038 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[14:0],
7039 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[2:1],
7040 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
7041 5'b00000};
7042 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[14:0],
7043 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[2:1],
7044 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
7045 5'b00000};
7046 case(num_dimms)
7047 001: begin
7048 mcu3_physical_addr_a[34] = mcu3_drif_dram_addr_a[2];
7049 mcu3_physical_addr_b[34] = mcu3_drif_dram_addr_b[2];
7050 mcu3_physical_addr_c[34] = mcu3_drif_dram_addr_c[2];
7051 end
7052 010: begin
7053 mcu3_physical_addr_a[35:34] = mcu3_drif_dram_addr_a[3:2];
7054 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
7055 mcu3_physical_addr_b[35:34] = mcu3_drif_dram_addr_b[3:2];
7056 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7057 mcu3_physical_addr_c[35:34] = mcu3_drif_dram_addr_c[3:2];
7058 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7059 end
7060 100: begin
7061 mcu3_physical_addr_a[36:34] = mcu3_drif_dram_addr_a[4:2];
7062 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7063 mcu3_physical_addr_b[36:34] = mcu3_drif_dram_addr_b[4:2];
7064 mcu3_physical_addr_b[12:11] = mcu3_drif_dram_dimm_b[1:0];
7065 mcu3_physical_addr_c[36:34] = mcu3_drif_dram_addr_c[4:2];
7066 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7067 end
7068 000: begin
7069 mcu3_physical_addr_a[37:34] = mcu3_drif_dram_addr_a[5:2];
7070 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7071 mcu3_physical_addr_b[37:34] = mcu3_drif_dram_addr_b[5:2];
7072 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7073 mcu3_physical_addr_c[37:34] = mcu3_drif_dram_addr_c[5:2];
7074 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7075 end
7076 endcase
7077 end
7078 8'b1_0_1_11_001,
7079 8'b1_0_1_11_010,
7080 8'b1_0_1_11_100,
7081 8'b1_0_1_11_000: begin
7082 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[14:0],
7083 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:2], mcu3_drif_dram_bank_a[1],
7084 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[1],
7085 5'b00000};
7086 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[14:0],
7087 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:2], mcu3_drif_dram_bank_b[1],
7088 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[1],
7089 5'b00000};
7090 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[14:0],
7091 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:2], mcu3_drif_dram_bank_c[1],
7092 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[1],
7093 5'b00000};
7094 case(num_dimms)
7095 001: begin
7096 mcu3_physical_addr_a[35:34] = mcu3_drif_dram_addr_a[3:2];
7097 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
7098 mcu3_physical_addr_b[35:34] = mcu3_drif_dram_addr_b[3:2];
7099 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
7100 mcu3_physical_addr_c[35:34] = mcu3_drif_dram_addr_c[3:2];
7101 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
7102 end
7103 010: begin
7104 mcu3_physical_addr_a[36:34] = mcu3_drif_dram_addr_a[4:2];
7105 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
7106 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
7107 mcu3_physical_addr_b[36:34] = mcu3_drif_dram_addr_b[4:2];
7108 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7109 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7110 mcu3_physical_addr_c[36:34] = mcu3_drif_dram_addr_c[4:2];
7111 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7112 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
7113 end
7114 100: begin
7115 mcu3_physical_addr_a[37:34] = mcu3_drif_dram_addr_a[5:2];
7116 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7117 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
7118 mcu3_physical_addr_b[37:34] = mcu3_drif_dram_addr_b[5:2];
7119 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[1:0];
7120 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7121 mcu3_physical_addr_c[37:34] = mcu3_drif_dram_addr_c[5:2];
7122 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7123 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
7124 end
7125 000: begin
7126 mcu3_physical_addr_a[38:34] = mcu3_drif_dram_addr_a[5:2];
7127 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7128 mcu3_physical_addr_a[14] = mcu3_drif_dram_rank_a;
7129 mcu3_physical_addr_b[38:34] = mcu3_drif_dram_addr_b[5:2];
7130 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7131 mcu3_physical_addr_b[14] = mcu3_drif_dram_rank_b;
7132 mcu3_physical_addr_c[38:34] = mcu3_drif_dram_addr_c[5:2];
7133 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7134 mcu3_physical_addr_c[14] = mcu3_drif_dram_rank_c;
7135 end
7136 endcase
7137 end
7138
7139 //---------------------------
7140 // SINGLE CHANNEL, RANK LOW
7141 //---------------------------
7142
7143 8'b0_0_0_00_001,
7144 8'b0_0_0_00_010,
7145 8'b0_0_0_00_100,
7146 8'b0_0_0_00_000: begin
7147 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[12:0],
7148 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
7149 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7150 5'b00000};
7151 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[12:0],
7152 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
7153 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7154 5'b00000};
7155 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[12:0],
7156 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
7157 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7158 5'b00000};
7159 case(num_dimms)
7160 001: begin
7161 end
7162 010: begin
7163 mcu3_physical_addr_a[31] = mcu3_drif_dram_addr_a[3];
7164 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
7165 mcu3_physical_addr_b[31] = mcu3_drif_dram_addr_b[3];
7166 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
7167 mcu3_physical_addr_c[31] = mcu3_drif_dram_addr_c[3];
7168 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
7169 end
7170 100: begin
7171 mcu3_physical_addr_a[32:31] = mcu3_drif_dram_addr_a[4:3];
7172 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
7173 mcu3_physical_addr_b[32:31] = mcu3_drif_dram_addr_b[4:3];
7174 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
7175 mcu3_physical_addr_c[32:31] = mcu3_drif_dram_addr_c[4:3];
7176 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
7177 end
7178 000: begin
7179 mcu3_physical_addr_a[33:31] = mcu3_drif_dram_addr_a[5:3];
7180 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
7181 mcu3_physical_addr_b[33:31] = mcu3_drif_dram_addr_b[5:3];
7182 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
7183 mcu3_physical_addr_c[33:31] = mcu3_drif_dram_addr_c[5:3];
7184 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
7185 end
7186 endcase
7187 end
7188 8'b0_0_1_00_001,
7189 8'b0_0_1_00_010,
7190 8'b0_0_1_00_100,
7191 8'b0_0_1_00_000: begin
7192 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[12:0],
7193 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
7194 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7195 5'b00000};
7196 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[12:0],
7197 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
7198 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7199 5'b00000};
7200 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[12:0],
7201 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
7202 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7203 5'b00000};
7204 case(num_dimms)
7205 001: begin
7206 mcu3_physical_addr_a[31] = mcu3_drif_dram_addr_a[3];
7207 mcu3_physical_addr_a[10] = mcu3_drif_dram_rank_a;
7208 mcu3_physical_addr_b[31] = mcu3_drif_dram_addr_b[3];
7209 mcu3_physical_addr_b[10] = mcu3_drif_dram_rank_b;
7210 mcu3_physical_addr_c[31] = mcu3_drif_dram_addr_c[3];
7211 mcu3_physical_addr_c[10] = mcu3_drif_dram_rank_c;
7212 end
7213 010: begin
7214 mcu3_physical_addr_a[32:31] = mcu3_drif_dram_addr_a[4:3];
7215 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
7216 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
7217 mcu3_physical_addr_b[32:31] = mcu3_drif_dram_addr_b[4:3];
7218 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
7219 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
7220 mcu3_physical_addr_c[32:31] = mcu3_drif_dram_addr_c[4:3];
7221 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
7222 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
7223 end
7224 100: begin
7225 mcu3_physical_addr_a[33:31] = mcu3_drif_dram_addr_a[5:3];
7226 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
7227 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
7228 mcu3_physical_addr_b[33:31] = mcu3_drif_dram_addr_b[5:3];
7229 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
7230 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7231 mcu3_physical_addr_c[33:31] = mcu3_drif_dram_addr_c[5:3];
7232 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
7233 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
7234 end
7235 000: begin
7236 mcu3_physical_addr_a[34:31] = mcu3_drif_dram_addr_a[6:3];
7237 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
7238 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
7239 mcu3_physical_addr_b[34:31] = mcu3_drif_dram_addr_b[6:3];
7240 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
7241 mcu3_physical_addr_b[13] = mcu3_drif_dram_rank_b;
7242 mcu3_physical_addr_c[34:31] = mcu3_drif_dram_addr_c[6:3];
7243 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
7244 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
7245 end
7246 endcase
7247 end
7248 8'b0_0_0_01_001,
7249 8'b0_0_0_01_010,
7250 8'b0_0_0_01_100,
7251 8'b0_0_0_01_000: begin
7252 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
7253 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
7254 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7255 5'b00000};
7256 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
7257 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
7258 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7259 5'b00000};
7260 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
7261 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
7262 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7263 5'b00000};
7264 case(num_dimms)
7265 001: begin
7266 end
7267 010: begin
7268 mcu3_physical_addr_a[32] = mcu3_drif_dram_addr_a[3];
7269 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
7270 mcu3_physical_addr_b[32] = mcu3_drif_dram_addr_b[3];
7271 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
7272 mcu3_physical_addr_c[32] = mcu3_drif_dram_addr_c[3];
7273 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
7274 end
7275 100: begin
7276 mcu3_physical_addr_a[33:32] = mcu3_drif_dram_addr_a[4:3];
7277 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
7278 mcu3_physical_addr_b[33:32] = mcu3_drif_dram_addr_b[4:3];
7279 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
7280 mcu3_physical_addr_c[33:32] = mcu3_drif_dram_addr_c[4:3];
7281 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
7282 end
7283 000: begin
7284 mcu3_physical_addr_a[34:32] = mcu3_drif_dram_addr_a[5:3];
7285 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
7286 mcu3_physical_addr_b[34:32] = mcu3_drif_dram_addr_b[5:3];
7287 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
7288 mcu3_physical_addr_c[34:32] = mcu3_drif_dram_addr_c[5:3];
7289 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
7290 end
7291 endcase
7292 end
7293 8'b0_0_1_01_001,
7294 8'b0_0_1_01_010,
7295 8'b0_0_1_01_100,
7296 8'b0_0_1_01_000: begin
7297 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
7298 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:3], mcu3_drif_dram_bank_a[1],
7299 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7300 5'b00000};
7301 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
7302 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:3], mcu3_drif_dram_bank_b[1],
7303 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7304 5'b00000};
7305 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
7306 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:3], mcu3_drif_dram_bank_c[1],
7307 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7308 5'b00000};
7309 case(num_dimms)
7310 001: begin
7311 mcu3_physical_addr_a[32] = mcu3_drif_dram_addr_a[3];
7312 mcu3_physical_addr_a[10] = mcu3_drif_dram_rank_a;
7313 mcu3_physical_addr_b[32] = mcu3_drif_dram_addr_b[3];
7314 mcu3_physical_addr_b[10] = mcu3_drif_dram_rank_b;
7315 mcu3_physical_addr_c[32] = mcu3_drif_dram_addr_c[3];
7316 mcu3_physical_addr_c[10] = mcu3_drif_dram_rank_c;
7317 end
7318 010: begin
7319 mcu3_physical_addr_a[33:32] = mcu3_drif_dram_addr_a[4:3];
7320 mcu3_physical_addr_a[10] = mcu3_drif_dram_dimm_a[0];
7321 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
7322 mcu3_physical_addr_b[33:32] = mcu3_drif_dram_addr_b[4:3];
7323 mcu3_physical_addr_b[10] = mcu3_drif_dram_dimm_b[0];
7324 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
7325 mcu3_physical_addr_c[33:32] = mcu3_drif_dram_addr_c[4:3];
7326 mcu3_physical_addr_c[10] = mcu3_drif_dram_dimm_c[0];
7327 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
7328 end
7329 100: begin
7330 mcu3_physical_addr_a[34:32] = mcu3_drif_dram_addr_a[5:3];
7331 mcu3_physical_addr_a[11:10] = mcu3_drif_dram_dimm_a[1:0];
7332 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
7333 mcu3_physical_addr_b[34:32] = mcu3_drif_dram_addr_b[5:3];
7334 mcu3_physical_addr_b[11:10] = mcu3_drif_dram_dimm_b[1:0];
7335 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7336 mcu3_physical_addr_c[34:32] = mcu3_drif_dram_addr_c[5:3];
7337 mcu3_physical_addr_c[11:10] = mcu3_drif_dram_dimm_c[1:0];
7338 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
7339 end
7340 000: begin
7341 mcu3_physical_addr_a[35:32] = mcu3_drif_dram_addr_a[6:3];
7342 mcu3_physical_addr_a[12:10] = mcu3_drif_dram_dimm_a[2:0];
7343 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
7344 mcu3_physical_addr_b[35:32] = mcu3_drif_dram_addr_b[6:3];
7345 mcu3_physical_addr_b[12:10] = mcu3_drif_dram_dimm_b[2:0];
7346 mcu3_physical_addr_b[13] = mcu3_drif_dram_rank_b;
7347 mcu3_physical_addr_c[35:32] = mcu3_drif_dram_addr_c[6:3];
7348 mcu3_physical_addr_c[12:10] = mcu3_drif_dram_dimm_c[2:0];
7349 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
7350 end
7351 endcase
7352 end
7353 8'b0_0_0_10_001,
7354 8'b0_0_0_10_010,
7355 8'b0_0_0_10_100,
7356 8'b0_0_0_10_000: begin
7357 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
7358 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
7359 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7360 5'b00000};
7361 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
7362 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
7363 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7364 5'b00000};
7365 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
7366 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
7367 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7368 5'b00000};
7369 case(num_dimms)
7370 001: begin
7371 mcu3_physical_addr_a[32] = mcu3_drif_dram_addr_a[3];
7372 mcu3_physical_addr_b[32] = mcu3_drif_dram_addr_b[3];
7373 mcu3_physical_addr_c[32] = mcu3_drif_dram_addr_c[3];
7374 end
7375 010: begin
7376 mcu3_physical_addr_a[33:32] = mcu3_drif_dram_addr_a[4:3];
7377 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
7378 mcu3_physical_addr_b[33:32] = mcu3_drif_dram_addr_b[4:3];
7379 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7380 mcu3_physical_addr_c[33:32] = mcu3_drif_dram_addr_c[4:3];
7381 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7382 end
7383 100: begin
7384 mcu3_physical_addr_a[34:32] = mcu3_drif_dram_addr_a[5:3];
7385 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7386 mcu3_physical_addr_b[34:32] = mcu3_drif_dram_addr_b[5:3];
7387 mcu3_physical_addr_b[12:11] = mcu3_drif_dram_dimm_b[1:0];
7388 mcu3_physical_addr_c[34:32] = mcu3_drif_dram_addr_c[5:3];
7389 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7390 end
7391 000: begin
7392 mcu3_physical_addr_a[35:32] = mcu3_drif_dram_addr_a[6:3];
7393 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7394 mcu3_physical_addr_b[35:32] = mcu3_drif_dram_addr_b[6:3];
7395 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7396 mcu3_physical_addr_c[35:32] = mcu3_drif_dram_addr_c[6:3];
7397 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7398 end
7399 endcase
7400 end
7401 8'b0_0_1_10_001,
7402 8'b0_0_1_10_010,
7403 8'b0_0_1_10_100,
7404 8'b0_0_1_10_000: begin
7405 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[13:0],
7406 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
7407 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7408 5'b00000};
7409 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[13:0],
7410 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
7411 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7412 5'b00000};
7413 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[13:0],
7414 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
7415 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7416 5'b00000};
7417 case(num_dimms)
7418 001: begin
7419 mcu3_physical_addr_a[33:32] = mcu3_drif_dram_addr_a[4:3];
7420 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
7421 mcu3_physical_addr_b[33:32] = mcu3_drif_dram_addr_b[4:3];
7422 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
7423 mcu3_physical_addr_c[33:32] = mcu3_drif_dram_addr_c[4:3];
7424 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
7425 end
7426 010: begin
7427 mcu3_physical_addr_a[34:32] = mcu3_drif_dram_addr_a[5:3];
7428 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
7429 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
7430 mcu3_physical_addr_b[34:32] = mcu3_drif_dram_addr_b[5:3];
7431 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7432 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7433 mcu3_physical_addr_c[34:32] = mcu3_drif_dram_addr_c[5:3];
7434 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7435 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
7436 end
7437 100: begin
7438 mcu3_physical_addr_a[35:32] = mcu3_drif_dram_addr_a[6:3];
7439 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7440 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
7441 mcu3_physical_addr_b[35:32] = mcu3_drif_dram_addr_b[6:3];
7442 mcu3_physical_addr_b[12:11] = mcu3_drif_dram_dimm_b[1:0];
7443 mcu3_physical_addr_b[13] = mcu3_drif_dram_rank_b;
7444 mcu3_physical_addr_c[35:32] = mcu3_drif_dram_addr_c[6:3];
7445 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7446 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
7447 end
7448 000: begin
7449 mcu3_physical_addr_a[36:32] = mcu3_drif_dram_addr_a[7:3];
7450 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7451 mcu3_physical_addr_a[14] = mcu3_drif_dram_rank_a;
7452 mcu3_physical_addr_b[36:32] = mcu3_drif_dram_addr_b[7:3];
7453 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7454 mcu3_physical_addr_b[14] = mcu3_drif_dram_rank_b;
7455 mcu3_physical_addr_c[36:32] = mcu3_drif_dram_addr_c[7:3];
7456 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7457 mcu3_physical_addr_c[14] = mcu3_drif_dram_rank_c;
7458 end
7459 endcase
7460 end
7461 8'b0_0_0_11_001,
7462 8'b0_0_0_11_010,
7463 8'b0_0_0_11_100,
7464 8'b0_0_0_11_000: begin
7465 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[14:0],
7466 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
7467 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7468 5'b00000};
7469 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[14:0],
7470 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
7471 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7472 5'b00000};
7473 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[14:0],
7474 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
7475 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7476 5'b00000};
7477 case(num_dimms)
7478 001: begin
7479 mcu3_physical_addr_a[33] = mcu3_drif_dram_addr_a[3];
7480 mcu3_physical_addr_b[33] = mcu3_drif_dram_addr_b[3];
7481 mcu3_physical_addr_c[33] = mcu3_drif_dram_addr_c[3];
7482 end
7483 010: begin
7484 mcu3_physical_addr_a[34:33] = mcu3_drif_dram_addr_a[4:3];
7485 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
7486 mcu3_physical_addr_b[34:33] = mcu3_drif_dram_addr_b[4:3];
7487 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7488 mcu3_physical_addr_c[34:33] = mcu3_drif_dram_addr_c[4:3];
7489 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7490 end
7491 100: begin
7492 mcu3_physical_addr_a[35:33] = mcu3_drif_dram_addr_a[5:3];
7493 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7494 mcu3_physical_addr_b[35:33] = mcu3_drif_dram_addr_b[5:3];
7495 mcu3_physical_addr_b[12:11] = mcu3_drif_dram_dimm_b[1:0];
7496 mcu3_physical_addr_c[35:33] = mcu3_drif_dram_addr_c[5:3];
7497 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7498 end
7499 000: begin
7500 mcu3_physical_addr_a[36:33] = mcu3_drif_dram_addr_a[6:3];
7501 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7502 mcu3_physical_addr_b[36:33] = mcu3_drif_dram_addr_b[6:3];
7503 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7504 mcu3_physical_addr_c[36:33] = mcu3_drif_dram_addr_c[6:3];
7505 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7506 end
7507 endcase
7508 end
7509 8'b0_0_1_11_001,
7510 8'b0_0_1_11_010,
7511 8'b0_0_1_11_100,
7512 8'b0_0_1_11_000: begin
7513 mcu3_physical_addr_a = {mcu3_drif_dram_ras_addr_a[14:0],
7514 mcu3_drif_dram_addr_a[11],mcu3_drif_dram_addr_a[9:4], mcu3_drif_dram_bank_a[2:1],
7515 2'b11, mcu3_drif_dram_bank_a[0], mcu3_drif_dram_addr_a[2],
7516 5'b00000};
7517 mcu3_physical_addr_b = {mcu3_drif_dram_ras_addr_b[14:0],
7518 mcu3_drif_dram_addr_b[11],mcu3_drif_dram_addr_b[9:4], mcu3_drif_dram_bank_b[2:1],
7519 2'b11, mcu3_drif_dram_bank_b[0], mcu3_drif_dram_addr_b[2],
7520 5'b00000};
7521 mcu3_physical_addr_c = {mcu3_drif_dram_ras_addr_c[14:0],
7522 mcu3_drif_dram_addr_c[11],mcu3_drif_dram_addr_c[9:4], mcu3_drif_dram_bank_c[2:1],
7523 2'b11, mcu3_drif_dram_bank_c[0], mcu3_drif_dram_addr_c[2],
7524 5'b00000};
7525 case(num_dimms)
7526 001: begin
7527 mcu3_physical_addr_a[34:33] = mcu3_drif_dram_addr_a[4:3];
7528 mcu3_physical_addr_a[11] = mcu3_drif_dram_rank_a;
7529 mcu3_physical_addr_b[34:33] = mcu3_drif_dram_addr_b[4:3];
7530 mcu3_physical_addr_b[11] = mcu3_drif_dram_rank_b;
7531 mcu3_physical_addr_c[34:33] = mcu3_drif_dram_addr_c[4:3];
7532 mcu3_physical_addr_c[11] = mcu3_drif_dram_rank_c;
7533 end
7534 010: begin
7535 mcu3_physical_addr_a[35:33] = mcu3_drif_dram_addr_a[5:3];
7536 mcu3_physical_addr_a[11] = mcu3_drif_dram_dimm_a[0];
7537 mcu3_physical_addr_a[12] = mcu3_drif_dram_rank_a;
7538 mcu3_physical_addr_b[35:33] = mcu3_drif_dram_addr_b[5:3];
7539 mcu3_physical_addr_b[11] = mcu3_drif_dram_dimm_b[0];
7540 mcu3_physical_addr_b[12] = mcu3_drif_dram_rank_b;
7541 mcu3_physical_addr_c[35:33] = mcu3_drif_dram_addr_c[5:3];
7542 mcu3_physical_addr_c[11] = mcu3_drif_dram_dimm_c[0];
7543 mcu3_physical_addr_c[12] = mcu3_drif_dram_rank_c;
7544 end
7545 100: begin
7546 mcu3_physical_addr_a[36:33] = mcu3_drif_dram_addr_a[6:3];
7547 mcu3_physical_addr_a[12:11] = mcu3_drif_dram_dimm_a[1:0];
7548 mcu3_physical_addr_a[13] = mcu3_drif_dram_rank_a;
7549 mcu3_physical_addr_b[36:33] = mcu3_drif_dram_addr_b[6:3];
7550 mcu3_physical_addr_b[12:11] = mcu3_drif_dram_dimm_b[1:0];
7551 mcu3_physical_addr_b[13] = mcu3_drif_dram_rank_b;
7552 mcu3_physical_addr_c[36:33] = mcu3_drif_dram_addr_c[6:3];
7553 mcu3_physical_addr_c[12:11] = mcu3_drif_dram_dimm_c[1:0];
7554 mcu3_physical_addr_c[13] = mcu3_drif_dram_rank_c;
7555 end
7556 000: begin
7557 mcu3_physical_addr_a[37:33] = mcu3_drif_dram_addr_a[7:3];
7558 mcu3_physical_addr_a[13:11] = mcu3_drif_dram_dimm_a[2:0];
7559 mcu3_physical_addr_a[14] = mcu3_drif_dram_rank_a;
7560 mcu3_physical_addr_b[37:33] = mcu3_drif_dram_addr_b[7:3];
7561 mcu3_physical_addr_b[13:11] = mcu3_drif_dram_dimm_b[2:0];
7562 mcu3_physical_addr_b[14] = mcu3_drif_dram_rank_b;
7563 mcu3_physical_addr_c[37:33] = mcu3_drif_dram_addr_c[7:3];
7564 mcu3_physical_addr_c[13:11] = mcu3_drif_dram_dimm_c[2:0];
7565 mcu3_physical_addr_c[14] = mcu3_drif_dram_rank_c;
7566 end
7567 endcase
7568 end
7569 endcase
7570
7571
7572 //--------------------------------------------------------------
7573 // MCU0 Print Read/Write Commands being sent out to FBD Branch 0
7574 //--------------------------------------------------------------
7575
7576 if (mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF) begin
7577 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (Slot B) Auto Refresh Request issued");
7578 end
7579
7580 if (mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRPDX) begin
7581 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (Slot B) Power Down Request issued");
7582 end
7583
7584 if (mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_PDE) begin
7585 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (Slot B) Power Enter Request issued");
7586 end
7587
7588 if (mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRE) begin
7589 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (Slot B) Self Refresh Request issued");
7590 end
7591
7592 if (mcu0_drif_dram_cmd_a==`ACT) begin
7593 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: ACTIVATE CMD \(Slot A\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x", mcu0_drif_dram_dimm_a, mcu0_drif_dram_bank_a, mcu0_drif_dram_rank_a, mcu0_drif_dram_addr_a);
7594 mcu0_drif_dram_ras_addr_a = mcu0_drif_dram_addr_a;
7595 end
7596
7597 if (mcu0_drif_dram_cmd_b==`ACT) begin
7598 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: ACTIVATE CMD\ (Slot B\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu0_drif_dram_dimm_b, mcu0_drif_dram_bank_b, mcu0_drif_dram_rank_b, mcu0_drif_dram_addr_b);
7599 mcu0_drif_dram_ras_addr_b = mcu0_drif_dram_addr_b;
7600 end
7601
7602 if (mcu0_drif_dram_cmd_c==`ACT) begin
7603 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: ACTIVATE CMD\ (Slot C\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu0_drif_dram_dimm_c, mcu0_drif_dram_bank_c, mcu0_drif_dram_rank_c, mcu0_drif_dram_addr_c);
7604 mcu0_drif_dram_ras_addr_c = mcu0_drif_dram_addr_c;
7605 end
7606
7607 if (mcu0_drif_dram_cmd_a==`WR)
7608 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: WRITE CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu0_physical_addr_a, mcu0_drif_dram_dimm_a, mcu0_drif_dram_bank_a, mcu0_drif_dram_rank_a, mcu0_drif_dram_addr_a, mcu0_drif_dram_ras_addr_a);
7609
7610 if (mcu0_drif_dram_cmd_b==`WR)
7611 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: WRITE CMD\ (Slot B\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu0_physical_addr_b, mcu0_drif_dram_dimm_b, mcu0_drif_dram_bank_b, mcu0_drif_dram_rank_b, mcu0_drif_dram_addr_b, mcu0_drif_dram_ras_addr_b);
7612
7613 if (mcu0_drif_dram_cmd_c==`WR)
7614 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: WRITE CMD\ (Slot C\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu0_physical_addr_c, mcu0_drif_dram_dimm_c, mcu0_drif_dram_bank_c, mcu0_drif_dram_rank_c, mcu0_drif_dram_addr_c, mcu0_drif_dram_ras_addr_c);
7615
7616 if (mcu0_drif_dram_cmd_a==`RD)
7617 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: READ CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu0_physical_addr_a, mcu0_drif_dram_dimm_a, mcu0_drif_dram_bank_a, mcu0_drif_dram_rank_a, mcu0_drif_dram_addr_a, mcu0_drif_dram_ras_addr_a);
7618
7619 if (mcu0_fbdic_f_1_l == 1'b0) begin
7620 case (mcu0_fbdic_f_1_cnt)
7621 2'b00: mcu0_wdata_dimm[0] = mcu0_fbdic_f[0] ;
7622 2'b01: mcu0_wdata_dimm[1] = mcu0_fbdic_f[0] ;
7623 2'b10: mcu0_wdata_dimm[2] = mcu0_fbdic_f[0] ;
7624 default: ;
7625 endcase
7626
7627 if (mcu0_fbdic_f_1_cnt < 3'b11) begin
7628 if (chnl_type==1'b1)
7629 begin
7630 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x WSn=%b", mcu0_fbdiwr_bc_cmd_data0, mcu0_fbdiwr_bc_cmd_data1, mcu0_fbdic_f[0]);
7631 end
7632 else begin
7633 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (CH0) WDATA[71:0]=%x WSn=%b", mcu0_fbdiwr_bc_cmd_data0, mcu0_fbdic_f[0]);
7634 end
7635 mcu0_fbdic_f_1_cnt = mcu0_fbdic_f_1_cnt + 1'b1;
7636 end
7637 else begin
7638 if (chnl_type==1'b1)
7639 begin
7640 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x DIMM[2:0]=%x", mcu0_fbdiwr_bc_cmd_data0, mcu0_fbdiwr_bc_cmd_data1, mcu0_wdata_dimm);
7641 end
7642 else begin
7643 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: (CH0) WDATA[71:0]=%x DIMM[2:0]=%x", mcu0_fbdiwr_bc_cmd_data0, mcu0_wdata_dimm);
7644 end
7645 mcu0_fbdic_f_1_cnt = 2'b0;
7646 end
7647 end
7648
7649 //--------------------------------------------------------------
7650 // MCU1 Print Read/Write Commands being sent out to FBD Branch 1
7651 //--------------------------------------------------------------
7652
7653 if (mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF) begin
7654 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (Slot B) Auto Refresh Request issued");
7655 end
7656
7657 if (mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_SRPDX) begin
7658 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (Slot B) Power Down Request issued");
7659 end
7660
7661 if (mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_PDE) begin
7662 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (Slot B) Power Enter Request issued");
7663 end
7664
7665 if (mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_SRE) begin
7666 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (Slot B) Self Refresh Request issued");
7667 end
7668
7669 if (mcu1_drif_dram_cmd_a==`ACT) begin
7670 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: ACTIVATE CMD \(Slot A\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu1_drif_dram_dimm_a, mcu1_drif_dram_bank_a, mcu1_drif_dram_rank_a, mcu1_drif_dram_addr_a);
7671 mcu1_drif_dram_ras_addr_a = mcu1_drif_dram_addr_a;
7672 end
7673
7674 if (mcu1_drif_dram_cmd_b==`ACT) begin
7675 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: ACTIVATE CMD\ (Slot B\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu1_drif_dram_dimm_b, mcu1_drif_dram_bank_b, mcu1_drif_dram_rank_b, mcu1_drif_dram_addr_b);
7676 mcu1_drif_dram_ras_addr_b = mcu1_drif_dram_addr_b;
7677 end
7678
7679 if (mcu1_drif_dram_cmd_c==`ACT) begin
7680 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: ACTIVATE CMD\ (Slot C\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu1_drif_dram_dimm_c, mcu1_drif_dram_bank_c, mcu1_drif_dram_rank_c, mcu1_drif_dram_addr_c);
7681 mcu1_drif_dram_ras_addr_c = mcu1_drif_dram_addr_c;
7682 end
7683
7684
7685 if (mcu1_drif_dram_cmd_a==`WR)
7686 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: WRITE CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu1_physical_addr_a, mcu1_drif_dram_dimm_a, mcu1_drif_dram_bank_a, mcu1_drif_dram_rank_a, mcu1_drif_dram_addr_a, mcu1_drif_dram_ras_addr_a);
7687
7688 if (mcu1_drif_dram_cmd_b==`WR)
7689 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: WRITE CMD\ (Slot B\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu1_physical_addr_b, mcu1_drif_dram_dimm_b, mcu1_drif_dram_bank_b, mcu1_drif_dram_rank_b, mcu1_drif_dram_addr_b, mcu1_drif_dram_ras_addr_b);
7690
7691 if (mcu1_drif_dram_cmd_c==`WR)
7692 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: WRITE CMD\ (Slot C\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu1_physical_addr_c, mcu1_drif_dram_dimm_c, mcu1_drif_dram_bank_c, mcu1_drif_dram_rank_c, mcu1_drif_dram_addr_c, mcu1_drif_dram_ras_addr_c);
7693
7694 if (mcu1_drif_dram_cmd_a==`RD)
7695 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: READ CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu1_physical_addr_a, mcu1_drif_dram_dimm_a, mcu1_drif_dram_bank_a, mcu1_drif_dram_rank_a, mcu1_drif_dram_addr_a, mcu1_drif_dram_ras_addr_a);
7696
7697 if (mcu1_fbdic_f_1_l == 1'b0) begin
7698 case (mcu1_fbdic_f_1_cnt)
7699 2'b00: mcu1_wdata_dimm[0] = mcu1_fbdic_f[0] ;
7700 2'b01: mcu1_wdata_dimm[1] = mcu1_fbdic_f[0] ;
7701 2'b10: mcu1_wdata_dimm[2] = mcu1_fbdic_f[0] ;
7702 default: ;
7703 endcase
7704
7705 if (mcu1_fbdic_f_1_cnt < 3'b11) begin
7706 if (chnl_type==1'b1)
7707 begin
7708 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x WSn=%b", mcu1_fbdiwr_bc_cmd_data0, mcu1_fbdiwr_bc_cmd_data1, mcu1_fbdic_f[0]);
7709 end
7710 else
7711 begin
7712 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (CH0) WDATA[71:0]=%x WSn=%b", mcu1_fbdiwr_bc_cmd_data0, mcu1_fbdic_f[0]);
7713 end
7714 mcu1_fbdic_f_1_cnt = mcu1_fbdic_f_1_cnt + 1'b1;
7715 end
7716 else begin
7717 if (chnl_type==1'b1)
7718 begin
7719 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x DIMM[2:0]=%x", mcu1_fbdiwr_bc_cmd_data0, mcu1_fbdiwr_bc_cmd_data1, mcu1_wdata_dimm);
7720 end
7721 else
7722 begin
7723 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: (CH0) WDATA[71:0]=%x DIMM[2:0]=%x", mcu1_fbdiwr_bc_cmd_data0, mcu1_wdata_dimm);
7724 end
7725 mcu1_fbdic_f_1_cnt = 2'b0;
7726 end
7727 end
7728
7729 //--------------------------------------------------------------
7730 // MCU2 Print Read/Write Commands being sent out to FBD Branch 2
7731 //--------------------------------------------------------------
7732
7733 if (mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF) begin
7734 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (Slot B) Auto Refresh Request issued");
7735 end
7736
7737 if (mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRPDX) begin
7738 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (Slot B) Power Down Request issued");
7739 end
7740
7741 if (mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_PDE) begin
7742 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (Slot B) Power Enter Request issued");
7743 end
7744
7745 if (mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRE) begin
7746 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (Slot B) Self Refresh Request issued");
7747 end
7748
7749 if (mcu2_drif_dram_cmd_a==`ACT) begin
7750 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: ACTIVATE CMD \(Slot A\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu2_drif_dram_dimm_a, mcu2_drif_dram_bank_a, mcu2_drif_dram_rank_a, mcu2_drif_dram_addr_a);
7751 mcu2_drif_dram_ras_addr_a = mcu2_drif_dram_addr_a;
7752 end
7753
7754 if (mcu2_drif_dram_cmd_b==`ACT) begin
7755 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: ACTIVATE CMD\ (Slot B\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu2_drif_dram_dimm_b, mcu2_drif_dram_bank_b, mcu2_drif_dram_rank_b, mcu2_drif_dram_addr_b);
7756 mcu2_drif_dram_ras_addr_b = mcu2_drif_dram_addr_b;
7757 end
7758
7759 if (mcu2_drif_dram_cmd_c==`ACT) begin
7760 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: ACTIVATE CMD\ (Slot C\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu2_drif_dram_dimm_c, mcu2_drif_dram_bank_c, mcu2_drif_dram_rank_c, mcu2_drif_dram_addr_c);
7761 mcu2_drif_dram_ras_addr_c = mcu2_drif_dram_addr_c;
7762 end
7763
7764
7765 if (mcu2_drif_dram_cmd_a==`WR)
7766 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: WRITE CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu2_physical_addr_a, mcu2_drif_dram_dimm_a, mcu2_drif_dram_bank_a, mcu2_drif_dram_rank_a, mcu2_drif_dram_addr_a, mcu2_drif_dram_ras_addr_a);
7767
7768 if (mcu2_drif_dram_cmd_b==`WR)
7769 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: WRITE CMD\ (Slot B\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu2_physical_addr_b, mcu2_drif_dram_dimm_b, mcu2_drif_dram_bank_b, mcu2_drif_dram_rank_b, mcu2_drif_dram_addr_b, mcu2_drif_dram_ras_addr_b);
7770
7771 if (mcu2_drif_dram_cmd_c==`WR)
7772 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: WRITE CMD\ (Slot C\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu2_physical_addr_c, mcu2_drif_dram_dimm_c, mcu2_drif_dram_bank_c, mcu2_drif_dram_rank_c, mcu2_drif_dram_addr_c, mcu2_drif_dram_ras_addr_c);
7773
7774 if (mcu2_drif_dram_cmd_a==`RD)
7775 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: READ CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu2_physical_addr_a, mcu2_drif_dram_dimm_a, mcu2_drif_dram_bank_a, mcu2_drif_dram_rank_a, mcu2_drif_dram_addr_a, mcu2_drif_dram_ras_addr_a);
7776
7777 if (mcu2_fbdic_f_1_l == 1'b0) begin
7778 case (mcu2_fbdic_f_1_cnt)
7779 2'b00: mcu2_wdata_dimm[0] = mcu2_fbdic_f[0] ;
7780 2'b01: mcu2_wdata_dimm[1] = mcu2_fbdic_f[0] ;
7781 2'b10: mcu2_wdata_dimm[2] = mcu2_fbdic_f[0] ;
7782 default: ;
7783 endcase
7784
7785 if (mcu2_fbdic_f_1_cnt < 3'b11) begin
7786 if(chnl_type==1'b1)
7787 begin
7788 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x WSn=%b", mcu2_fbdiwr_bc_cmd_data0, mcu2_fbdiwr_bc_cmd_data1, mcu2_fbdic_f[0]);
7789 end
7790 else
7791 begin
7792 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (CH0) WDATA[71:0]=%x WSn=%b", mcu2_fbdiwr_bc_cmd_data0, mcu2_fbdic_f[0]);
7793 end
7794 mcu2_fbdic_f_1_cnt = mcu2_fbdic_f_1_cnt + 1'b1;
7795 end
7796 else begin
7797 if (chnl_type==1'b1)
7798 begin
7799 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x DIMM[2:0]=%x", mcu2_fbdiwr_bc_cmd_data0, mcu2_fbdiwr_bc_cmd_data1, mcu2_wdata_dimm);
7800 end
7801 else
7802 begin
7803 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: (CH0) WDATA[71:0]=%x DIMM[2:0]=%x", mcu2_fbdiwr_bc_cmd_data0, mcu2_wdata_dimm);
7804 end
7805 mcu2_fbdic_f_1_cnt = 2'b0;
7806 end
7807 end
7808
7809 //--------------------------------------------------------------
7810 // MCU3 Print Read/Write Commands being sent out to FBD Branch 3
7811 //--------------------------------------------------------------
7812
7813 if (mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF) begin
7814 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (slot B) Auto Refresh Request issued");
7815 end
7816
7817 if (mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRPDX) begin
7818 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (slot B) Power Down Request issued");
7819 end
7820
7821 if (mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_PDE) begin
7822 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (slot B) Power Enter Request issued");
7823 end
7824
7825 if (mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_SRE) begin
7826 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (slot B) Self Refresh Request issued");
7827 end
7828
7829 if (mcu3_drif_dram_cmd_a==`ACT) begin
7830 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: ACTIVATE CMD \(Slot A\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu3_drif_dram_dimm_a, mcu3_drif_dram_bank_a, mcu3_drif_dram_rank_a, mcu3_drif_dram_addr_a);
7831 mcu3_drif_dram_ras_addr_a = mcu3_drif_dram_addr_a;
7832 end
7833
7834 if (mcu3_drif_dram_cmd_b==`ACT) begin
7835 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: ACTIVATE CMD\ (Slot B\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu3_drif_dram_dimm_b, mcu3_drif_dram_bank_b, mcu3_drif_dram_rank_b, mcu3_drif_dram_addr_b);
7836 mcu3_drif_dram_ras_addr_b = mcu3_drif_dram_addr_b;
7837 end
7838
7839 if (mcu3_drif_dram_cmd_c==`ACT) begin
7840 //`PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: ACTIVATE CMD\ (Slot C\) sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, ADDR=%x",mcu3_drif_dram_dimm_c, mcu3_drif_dram_bank_c, mcu3_drif_dram_rank_c, mcu3_drif_dram_addr_c);
7841 mcu3_drif_dram_ras_addr_c = mcu3_drif_dram_addr_c;
7842 end
7843
7844
7845 if (mcu3_drif_dram_cmd_a==`WR)
7846 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: WRITE CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu3_physical_addr_a, mcu3_drif_dram_dimm_a, mcu3_drif_dram_bank_a, mcu3_drif_dram_rank_a, mcu3_drif_dram_addr_a, mcu3_drif_dram_ras_addr_a);
7847
7848 if (mcu3_drif_dram_cmd_b==`WR)
7849 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: WRITE CMD\ (Slot B\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu3_physical_addr_b, mcu3_drif_dram_dimm_b, mcu3_drif_dram_bank_b, mcu3_drif_dram_rank_b, mcu3_drif_dram_addr_b, mcu3_drif_dram_ras_addr_b);
7850
7851 if (mcu3_drif_dram_cmd_c==`WR)
7852 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: WRITE CMD\ (Slot C\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu3_physical_addr_c, mcu3_drif_dram_dimm_c, mcu3_drif_dram_bank_c, mcu3_drif_dram_rank_c, mcu3_drif_dram_addr_c, mcu3_drif_dram_ras_addr_c);
7853
7854 if (mcu3_drif_dram_cmd_a==`RD)
7855 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: READ CMD\ (Slot A\) PA[39:0]=%x sent to DIMM[2:0]=%x, BANK[2:0]=%x, RANK=%x, CAS ADDR[10:0]=%x, RAS ADDR[14:0]=%x",mcu3_physical_addr_a, mcu3_drif_dram_dimm_a, mcu3_drif_dram_bank_a, mcu3_drif_dram_rank_a, mcu3_drif_dram_addr_a, mcu3_drif_dram_ras_addr_a);
7856
7857 if (mcu3_fbdic_f_1_l == 1'b0) begin
7858 case (mcu3_fbdic_f_1_cnt)
7859 2'b00: mcu3_wdata_dimm[0] = mcu3_fbdic_f[0] ;
7860 2'b01: mcu3_wdata_dimm[1] = mcu3_fbdic_f[0] ;
7861 2'b10: mcu3_wdata_dimm[2] = mcu3_fbdic_f[0] ;
7862 default: ;
7863 endcase
7864
7865 if (mcu3_fbdic_f_1_cnt < 3'b11) begin
7866 if (chnl_type==1'b1)
7867 begin
7868 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x WSn=%b", mcu3_fbdiwr_bc_cmd_data0, mcu3_fbdiwr_bc_cmd_data1, mcu3_fbdic_f[0]);
7869 end
7870 else
7871 begin
7872 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (CH0) WDATA[71:0]=%x WSn=%b", mcu3_fbdiwr_bc_cmd_data0, mcu3_fbdic_f[0]);
7873 end
7874 mcu3_fbdic_f_1_cnt = mcu3_fbdic_f_1_cnt + 1'b1;
7875 end
7876 else begin
7877 if(chnl_type==1'b1)
7878 begin
7879 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (CH0) WDATA[71:0]=%x (CH1) WDATA[71:0]=%x DIMM[2:0]=%x", mcu3_fbdiwr_bc_cmd_data0, mcu3_fbdiwr_bc_cmd_data1, mcu3_wdata_dimm);
7880 end
7881 else
7882 begin
7883 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: (CH0) WDATA[71:0]=%x DIMM[2:0]=%x", mcu3_fbdiwr_bc_cmd_data0, mcu3_wdata_dimm);
7884 end
7885 mcu3_fbdic_f_1_cnt = 2'b0;
7886 end
7887 end
7888
7889end
7890
7891//----------------------------------------
7892// Print MCU FBDIC States (tick Monitor)
7893//----------------------------------------
7894
7895always @ (fbdic_fbd_state_0)
7896if (enabled)
7897begin
7898 case(fbdic_fbd_state_0)
7899 8'h0: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered DISABLE STATE of Link Training Seq");
7900 8'h1: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered CALIBRATE STATE of Link Training Seq");
7901 8'h2: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered TRAINING STATE of Link Training Seq");
7902 8'h3: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered TESTING STATE of Link Training Seq");
7903 8'h4: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered POLLING STATE of Link Training Seq");
7904 8'h5: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered CONFIG STATE of Link Training Seq");
7905 8'h6: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Entered L0 STATE");
7906 endcase
7907end
7908
7909always @ (fbdic_fbd_state_1)
7910if (enabled)
7911begin
7912 case(fbdic_fbd_state_1)
7913 8'h0: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered DISABLE STATE of Link Training Seq");
7914 8'h1: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered CALIBRATE STATE of Link Training Seq");
7915 8'h2: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered TRAINING STATE of Link Training Seq");
7916 8'h3: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered TESTING STATE of Link Training Seq");
7917 8'h4: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered POLLING STATE of Link Training Seq");
7918 8'h5: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered CONFIG STATE of Link Training Seq");
7919 8'h6: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: Entered L0 STATE");
7920 endcase
7921end
7922
7923always @ (fbdic_fbd_state_2)
7924if (enabled)
7925begin
7926 case(fbdic_fbd_state_2)
7927 8'h0: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered DISABLE STATE of Link Training Seq");
7928 8'h1: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered CALIBRATE STATE of Link Training Seq");
7929 8'h2: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered TRAINING STATE of Link Training Seq");
7930 8'h3: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered TESTING STATE of Link Training Seq");
7931 8'h4: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered POLLING STATE of Link Training Seq");
7932 8'h5: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered CONFIG STATE of Link Training Seq");
7933 8'h6: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: Entered L0 STATE");
7934 endcase
7935end
7936
7937always @ (fbdic_fbd_state_3)
7938if (enabled)
7939begin
7940 case(fbdic_fbd_state_3)
7941 8'h0: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered DISABLE STATE of Link Training Seq");
7942 8'h1: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered CALIBRATE STATE of Link Training Seq");
7943 8'h2: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered TRAINING STATE of Link Training Seq");
7944 8'h3: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered TESTING STATE of Link Training Seq");
7945 8'h4: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered POLLING STATE of Link Training Seq");
7946 8'h5: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered CONFIG STATE of Link Training Seq");
7947 8'h6: `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: Entered L0 STATE");
7948 endcase
7949end
7950
7951//----------------------------------------
7952// Sync Frame Collision & failover
7953//----------------------------------------
7954
7955initial
7956begin
7957 sync_frame_UI_err_0a = 12'h0;
7958 sync_frame_UI_err_0b = 12'h0;
7959 sync_frame_UI_err_1a = 12'h0;
7960 sync_frame_UI_err_1b = 12'h0;
7961 sync_frame_UI_err_2a = 12'h0;
7962 sync_frame_UI_err_2b = 12'h0;
7963 sync_frame_UI_err_3a = 12'h0;
7964 sync_frame_UI_err_3b = 12'h0;
7965
7966 #100;
7967
7968 if ($test$plusargs("DUAL_CHANNEL"))
7969 chnl_type = 1'b1; // DUAL CHANNELS PER BRANCH
7970 else if ($test$plusargs("SNG_CHANNEL"))
7971 chnl_type = 1'b0; // SINGLE CHANNEL PER BRANCH
7972 else
7973 chnl_type = 1'b1; // DUAL CHANNELS PER BRANCH (Default)
7974
7975 if ($test$plusargs("RANK_LOW"))
7976 rank_addr = 1'b0; // RANK LOW Address Select
7977 else if ($test$plusargs("RANK_HIGH"))
7978 rank_addr = 1'b1; // RANK HIGH Address Select
7979 else
7980 rank_addr = 1'b1; // RANK HIGH Address Select (Default)
7981
7982 if ($test$plusargs("STACK_DIMM"))
7983 rank = 1'b1; // 2 RANKS
7984 else
7985 rank = 1'b0; // 1 RANK (Default)
7986
7987 if ($test$plusargs("DIMM_SIZE_1G"))
7988 dimm_size = 2'b10;
7989 else if ($test$plusargs("DIMM_SIZE_512"))
7990 dimm_size = 2'b01;
7991 else if ($test$plusargs("DIMM_SIZE_256"))
7992 dimm_size = 2'b00;
7993 else
7994 dimm_size = 2'b11;
7995
7996 if ($test$plusargs("1_FBDIMM")) // Number of DIMMS
7997 num_dimms = 3'h1;
7998 else if ($test$plusargs("2_FBDIMMS"))
7999 num_dimms = 3'h2;
8000 else if ($test$plusargs("3_FBDIMMS"))
8001 num_dimms = 3'h3;
8002 else if ($test$plusargs("4_FBDIMMS"))
8003 num_dimms = 3'h4;
8004 else if ($test$plusargs("5_FBDIMMS"))
8005 num_dimms = 3'h5;
8006 else if ($test$plusargs("6_FBDIMMS"))
8007 num_dimms = 3'h6;
8008 else if ($test$plusargs("7_FBDIMMS"))
8009 num_dimms = 3'h7;
8010 else if ($test$plusargs("8_FBDIMMS"))
8011 num_dimms = 3'h0;
8012 else
8013 num_dimms = 3'h1; // Default 1 FBDIMM
8014
8015 if ($test$plusargs("DTM_ENABLED"))
8016 dtm_enabled = 1;
8017 else
8018 dtm_enabled = 0;
8019
8020 if ($test$plusargs("disable_fbdinit_chk"))
8021 fbd_init_check = 0;
8022 else
8023 fbd_init_check = 1;
8024
8025end
8026
8027always @ (posedge (fbdic_l0_state_0 && enabled))
8028begin
8029 // SB failover lanes
8030 if (fbdic_failover_config_0[7:4] != 4'hf)
8031 begin
8032 mcu0_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_0[7:4]);
8033 mcu0_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_0[7:4]);
8034 end
8035
8036 if (fbdic_failover_config_0[15:12] != 4'hf)
8037 begin
8038 mcu0_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_0[15:12]);
8039 mcu0_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_0[15:12]);
8040 end
8041end
8042
8043always @ (posedge (fbdic_l0_state_1 && enabled))
8044begin
8045 // SB failover lanes
8046 if (fbdic_failover_config_1[7:4] != 4'hf)
8047 begin
8048 mcu1_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_1[7:4]);
8049 mcu1_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_1[7:4]);
8050 end
8051
8052 if (fbdic_failover_config_1[15:12] != 4'hf)
8053 begin
8054 mcu1_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_1[15:12]);
8055 mcu1_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_1[15:12]);
8056 end
8057end
8058
8059always @ (posedge (fbdic_l0_state_2 && enabled))
8060begin
8061 // SB failover lanes
8062 if (fbdic_failover_config_2[7:4] != 4'hf)
8063 begin
8064 mcu2_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_2[7:4]);
8065 mcu2_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_2[7:4]);
8066 end
8067
8068 if (fbdic_failover_config_2[15:12] != 4'hf)
8069 begin
8070 mcu2_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_2[15:12]);
8071 mcu2_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_2[15:12]);
8072 end
8073end
8074
8075always @ (posedge (fbdic_l0_state_3 && enabled))
8076begin
8077 // SB failover lanes
8078 if (fbdic_failover_config_3[7:4] != 4'hf)
8079 begin
8080 mcu3_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_3[7:4]);
8081 mcu3_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_3[7:4]);
8082 end
8083
8084 if (fbdic_failover_config_3[15:12] != 4'hf)
8085 begin
8086 mcu3_clk_train_pat0 = bit_failover_lane_shift(10'h2aa, fbdic_failover_config_3[15:12]);
8087 mcu3_clk_train_pat1 = bit_failover_lane_shift(10'h155, fbdic_failover_config_3[15:12]);
8088 end
8089end
8090
8091always @ (posedge (fbdic_sync_frame_req_0 && enabled))
8092begin
8093 repeat(4) @(posedge drl2clk);
8094 repeat(4) @(negedge sclk);
8095
8096 @(negedge sclk);
8097 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat0)
8098 sync_frame_UI_err_0a[4] = 1'b1;
8099 if (chnl_type) begin
8100 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat0)
8101 sync_frame_UI_err_0b[4] = 1'b1;
8102 end
8103 @(negedge sclk);
8104 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat1)
8105 sync_frame_UI_err_0a[5] = 1'b1;
8106 if (chnl_type) begin
8107 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat1)
8108 sync_frame_UI_err_0b[5] = 1'b1;
8109 end
8110 @(negedge sclk);
8111 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat0)
8112 sync_frame_UI_err_0a[6] = 1'b1;
8113 if (chnl_type) begin
8114 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat0)
8115 sync_frame_UI_err_0b[6] = 1'b1;
8116 end
8117 @(negedge sclk);
8118 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat1)
8119 sync_frame_UI_err_0a[7] = 1'b1;
8120 if (chnl_type) begin
8121 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat1)
8122 sync_frame_UI_err_0b[7] = 1'b1;
8123 end
8124 @(negedge sclk);
8125 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat0)
8126 sync_frame_UI_err_0a[8] = 1'b1;
8127 if (chnl_type) begin
8128 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat0)
8129 sync_frame_UI_err_0b[8] = 1'b1;
8130 end
8131 @(negedge sclk);
8132 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat1)
8133 sync_frame_UI_err_0a[9] = 1'b1;
8134 if (chnl_type) begin
8135 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat1)
8136 sync_frame_UI_err_0b[9] = 1'b1;
8137 end
8138 @(negedge sclk);
8139 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat0)
8140 sync_frame_UI_err_0a[10] = 1'b1;
8141 if (chnl_type) begin
8142 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat0)
8143 sync_frame_UI_err_0b[10] = 1'b1;
8144 end
8145 @(negedge sclk);
8146 if (fbdimm0a_tx_p_top != mcu0_clk_train_pat1)
8147 sync_frame_UI_err_0a[11] = 1'b1;
8148 if (chnl_type) begin
8149 if (fbdimm0b_tx_p_top != mcu0_clk_train_pat1)
8150 sync_frame_UI_err_0b[11] = 1'b1;
8151 end
8152
8153`ifdef MCUSAT
8154 if (((|sync_frame_UI_err_0a[11:0] == 1'b1) || (|sync_frame_UI_err_0b[11:0] == 1'b1)) && sync_collision_check_enable)
8155 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: SYNC Frame is corrupted due to possible collision Ch a=%x Ch b=%x",sync_frame_UI_err_0a, sync_frame_UI_err_0b);
8156`endif
8157end
8158
8159always @ (posedge (fbdic_sync_frame_req_1 && enabled))
8160begin
8161 repeat(4) @(posedge drl2clk);
8162 repeat(4) @(negedge sclk);
8163
8164 @(negedge sclk);
8165 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat0)
8166 sync_frame_UI_err_1a[4] = 1'b1;
8167 if (chnl_type) begin
8168 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat0)
8169 sync_frame_UI_err_1b[4] = 1'b1;
8170 end
8171 @(negedge sclk);
8172 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat1)
8173 sync_frame_UI_err_1a[5] = 1'b1;
8174 if (chnl_type) begin
8175 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat1)
8176 sync_frame_UI_err_1b[5] = 1'b1;
8177 end
8178 @(negedge sclk);
8179 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat0)
8180 sync_frame_UI_err_1a[6] = 1'b1;
8181 if (chnl_type) begin
8182 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat0)
8183 sync_frame_UI_err_1b[6] = 1'b1;
8184 end
8185 @(negedge sclk);
8186 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat1)
8187 sync_frame_UI_err_1a[7] = 1'b1;
8188 if (chnl_type) begin
8189 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat1)
8190 sync_frame_UI_err_1b[7] = 1'b1;
8191 end
8192 @(negedge sclk);
8193 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat0)
8194 sync_frame_UI_err_1a[8] = 1'b1;
8195 if (chnl_type) begin
8196 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat0)
8197 sync_frame_UI_err_1b[8] = 1'b1;
8198 end
8199 @(negedge sclk);
8200 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat1)
8201 sync_frame_UI_err_1a[9] = 1'b1;
8202 if (chnl_type) begin
8203 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat1)
8204 sync_frame_UI_err_1b[9] = 1'b1;
8205 end
8206 @(negedge sclk);
8207 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat0)
8208 sync_frame_UI_err_1a[10] = 1'b1;
8209 if (chnl_type) begin
8210 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat0)
8211 sync_frame_UI_err_1b[10] = 1'b1;
8212 end
8213 @(negedge sclk);
8214 if (fbdimm1a_tx_p_top != mcu1_clk_train_pat1)
8215 sync_frame_UI_err_1a[11] = 1'b1;
8216 if (chnl_type) begin
8217 if (fbdimm1b_tx_p_top != mcu1_clk_train_pat1)
8218 sync_frame_UI_err_1b[11] = 1'b1;
8219 end
8220
8221`ifdef MCUSAT
8222 if (((|sync_frame_UI_err_1a[11:0] == 1'b1) || (|sync_frame_UI_err_1b[11:0] == 1'b1)) && sync_collision_check_enable)
8223 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: SYNC Frame is corrupted due to possible collision Ch a=%x Ch b=%x",sync_frame_UI_err_1a, sync_frame_UI_err_1b);
8224`endif
8225end
8226
8227always @ (posedge (fbdic_sync_frame_req_2 && enabled))
8228begin
8229 repeat(4) @(posedge drl2clk);
8230 repeat(4) @(negedge sclk);
8231
8232 @(negedge sclk);
8233 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat0)
8234 sync_frame_UI_err_2a[4] = 1'b1;
8235 if (chnl_type) begin
8236 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat0)
8237 sync_frame_UI_err_2b[4] = 1'b1;
8238 end
8239 @(negedge sclk);
8240 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat1)
8241 sync_frame_UI_err_2a[5] = 1'b1;
8242 if (chnl_type) begin
8243 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat1)
8244 sync_frame_UI_err_2b[5] = 1'b1;
8245 end
8246 @(negedge sclk);
8247 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat0)
8248 sync_frame_UI_err_2a[6] = 1'b1;
8249 if (chnl_type) begin
8250 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat0)
8251 sync_frame_UI_err_2b[6] = 1'b1;
8252 end
8253 @(negedge sclk);
8254 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat1)
8255 sync_frame_UI_err_2a[7] = 1'b1;
8256 if (chnl_type) begin
8257 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat1)
8258 sync_frame_UI_err_2b[7] = 1'b1;
8259 end
8260 @(negedge sclk);
8261 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat0)
8262 sync_frame_UI_err_2a[8] = 1'b1;
8263 if (chnl_type) begin
8264 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat0)
8265 sync_frame_UI_err_2b[8] = 1'b1;
8266 end
8267 @(negedge sclk);
8268 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat1)
8269 sync_frame_UI_err_2a[9] = 1'b1;
8270 if (chnl_type) begin
8271 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat1)
8272 sync_frame_UI_err_2b[9] = 1'b1;
8273 end
8274 @(negedge sclk);
8275 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat0)
8276 sync_frame_UI_err_2a[10] = 1'b1;
8277 if (chnl_type) begin
8278 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat0)
8279 sync_frame_UI_err_2b[10] = 1'b1;
8280 end
8281 @(negedge sclk);
8282 if (fbdimm2a_tx_p_top != mcu2_clk_train_pat1)
8283 sync_frame_UI_err_2a[11] = 1'b1;
8284 if (chnl_type) begin
8285 if (fbdimm2b_tx_p_top != mcu2_clk_train_pat1)
8286 sync_frame_UI_err_2b[11] = 1'b1;
8287 end
8288
8289`ifdef MCUSAT
8290 if (((|sync_frame_UI_err_2a[11:0] == 1'b1) || (|sync_frame_UI_err_2b[11:0] == 1'b1)) && sync_collision_check_enable)
8291 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: SYNC Frame is corrupted due to possible collision Ch a=%x Ch b=%x",sync_frame_UI_err_2a, sync_frame_UI_err_2b);
8292`endif
8293end
8294
8295always @ (posedge (fbdic_sync_frame_req_3 && enabled))
8296begin
8297 repeat(4) @(posedge drl2clk);
8298 repeat(4) @(negedge sclk);
8299
8300 @(negedge sclk);
8301 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat0)
8302 sync_frame_UI_err_3a[4] = 1'b1;
8303 if (chnl_type) begin
8304 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat0)
8305 sync_frame_UI_err_3b[4] = 1'b1;
8306 end
8307 @(negedge sclk);
8308 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat1)
8309 sync_frame_UI_err_3a[5] = 1'b1;
8310 if (chnl_type) begin
8311 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat1)
8312 sync_frame_UI_err_3b[5] = 1'b1;
8313 end
8314 @(negedge sclk);
8315 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat0)
8316 sync_frame_UI_err_3a[6] = 1'b1;
8317 if (chnl_type) begin
8318 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat0)
8319 sync_frame_UI_err_3b[6] = 1'b1;
8320 end
8321 @(negedge sclk);
8322 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat1)
8323 sync_frame_UI_err_3a[7] = 1'b1;
8324 if (chnl_type) begin
8325 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat1)
8326 sync_frame_UI_err_3b[7] = 1'b1;
8327 end
8328 @(negedge sclk);
8329 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat0)
8330 sync_frame_UI_err_3a[8] = 1'b1;
8331 if (chnl_type) begin
8332 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat0)
8333 sync_frame_UI_err_3b[8] = 1'b1;
8334 end
8335 @(negedge sclk);
8336 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat1)
8337 sync_frame_UI_err_3a[9] = 1'b1;
8338 if (chnl_type) begin
8339 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat1)
8340 sync_frame_UI_err_3b[9] = 1'b1;
8341 end
8342 @(negedge sclk);
8343 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat0)
8344 sync_frame_UI_err_3a[10] = 1'b1;
8345 if (chnl_type) begin
8346 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat0)
8347 sync_frame_UI_err_3b[10] = 1'b1;
8348 end
8349 @(negedge sclk);
8350 if (fbdimm3a_tx_p_top != mcu3_clk_train_pat1)
8351 sync_frame_UI_err_3a[11] = 1'b1;
8352 if (chnl_type) begin
8353 if (fbdimm3b_tx_p_top != mcu3_clk_train_pat1)
8354 sync_frame_UI_err_3b[11] = 1'b1;
8355 end
8356
8357`ifdef MCUSAT
8358 if (((|sync_frame_UI_err_3a[11:0] == 1'b1) || (|sync_frame_UI_err_3b[11:0] == 1'b1)) && sync_collision_check_enable)
8359 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: SYNC Frame is corrupted due to possible collision Ch a=%x Ch b=%x",sync_frame_UI_err_3a, sync_frame_UI_err_3b);
8360`endif
8361end
8362
8363function [9:0] bit_failover_lane_shift;
8364input [9:0] mcu_clk_train_pat;
8365input [3:0] bad_bit_lane_ch;
8366
8367reg [9:0] MCU_CLK_TRAIN_PAT;
8368
8369begin
8370 MCU_CLK_TRAIN_PAT = mcu_clk_train_pat;
8371 mcu_clk_train_pat = mcu_clk_train_pat << 1;
8372
8373 case(bad_bit_lane_ch)
8374 0000: mcu_clk_train_pat[0] = MCU_CLK_TRAIN_PAT[0] ;
8375 0001: mcu_clk_train_pat[1:0] = MCU_CLK_TRAIN_PAT[1:0] ;
8376 0010: mcu_clk_train_pat[2:0] = MCU_CLK_TRAIN_PAT[2:0] ;
8377 0011: mcu_clk_train_pat[3:0] = MCU_CLK_TRAIN_PAT[3:0] ;
8378 0100: mcu_clk_train_pat[4:0] = MCU_CLK_TRAIN_PAT[4:0] ;
8379 0101: mcu_clk_train_pat[5:0] = MCU_CLK_TRAIN_PAT[5:0] ;
8380 0110: mcu_clk_train_pat[6:0] = MCU_CLK_TRAIN_PAT[6:0] ;
8381 0111: mcu_clk_train_pat[7:0] = MCU_CLK_TRAIN_PAT[7:0] ;
8382 1000: mcu_clk_train_pat[8:0] = MCU_CLK_TRAIN_PAT[8:0] ;
8383 1001: mcu_clk_train_pat[9:0] = MCU_CLK_TRAIN_PAT[9:0] ;
8384 endcase
8385
8386 bit_failover_lane_shift = mcu_clk_train_pat ;
8387
8388end
8389endfunction
8390
8391//----------------------------
8392// Wr/Rd Config (TID) checkers
8393//----------------------------
8394
8395initial
8396begin
8397 chnl_0 = 1'b0;
8398 chnl_1 = 1'b0;
8399 chnl_2 = 1'b0;
8400 chnl_3 = 1'b0;
8401
8402 fbdic0_last_tid_0 = 1'b0;
8403 fbdic0_last_tid_1 = 1'b0;
8404 fbdic0_last_tid_2 = 1'b0;
8405 fbdic0_last_tid_3 = 1'b0;
8406
8407 fbdic1_last_tid_0 = 1'b0;
8408 fbdic1_last_tid_1 = 1'b0;
8409 fbdic1_last_tid_2 = 1'b0;
8410 fbdic1_last_tid_3 = 1'b0;
8411end
8412
8413always @(posedge (drl2clk && enabled))
8414begin
8415 // MCU 0
8416 if (drif_ucb_addr_0[31:0] == 32'h900)
8417 if (drif_ucb_data_0[15] == 1'b0)
8418 chnl_0 <= 1'b0;
8419 else
8420 chnl_0 <= 1'b1;
8421
8422 if (drif_ucb_addr_0==32'h908 && drif_ucb_wr_req_vld_0==1'b1 && chnl_0==1'b0)
8423 fbdic0_last_tid_0 <= ~fbdic0_last_tid_0;
8424
8425 if (drif_ucb_addr_0==32'h908 && drif_ucb_wr_req_vld_0==1'b1 && chnl_0==1'b1)
8426 fbdic1_last_tid_0 <= ~fbdic1_last_tid_0;
8427
8428 // MCU 1
8429 if (drif_ucb_addr_1[31:0] == 32'h900)
8430 if (drif_ucb_data_1[15] == 1'b0)
8431 chnl_1 <= 1'b0;
8432 else
8433 chnl_1 <= 1'b1;
8434
8435 if (drif_ucb_addr_1==32'h908 && drif_ucb_wr_req_vld_1==1'b1 && chnl_1==1'b0)
8436 fbdic0_last_tid_1 <= ~fbdic0_last_tid_1;
8437
8438 if (drif_ucb_addr_1==32'h908 && drif_ucb_wr_req_vld_1==1'b1 && chnl_1==1'b1)
8439 fbdic1_last_tid_1 <= ~fbdic1_last_tid_1;
8440
8441 // MCU 2
8442 if (drif_ucb_addr_2[31:0] == 32'h900)
8443 if (drif_ucb_data_2[15] == 1'b0)
8444 chnl_2 <= 1'b0;
8445 else
8446 chnl_2 <= 1'b1;
8447
8448 if (drif_ucb_addr_2==32'h908 && drif_ucb_wr_req_vld_2==1'b1 && chnl_2==1'b0)
8449 fbdic0_last_tid_2 <= ~fbdic0_last_tid_2;
8450
8451 if (drif_ucb_addr_2==32'h908 && drif_ucb_wr_req_vld_2==1'b1 && chnl_2==1'b1)
8452 fbdic1_last_tid_2 <= ~fbdic1_last_tid_2;
8453
8454 // MCU 3
8455 if (drif_ucb_addr_3[31:0] == 32'h900)
8456 if (drif_ucb_data_3[15] == 1'b0)
8457 chnl_3 <= 1'b0;
8458 else
8459 chnl_3 <= 1'b1;
8460
8461 if (drif_ucb_addr_3==32'h908 && drif_ucb_wr_req_vld_3==1'b1 && chnl_3==1'b0)
8462 fbdic0_last_tid_3 <= ~fbdic0_last_tid_3;
8463
8464 if (drif_ucb_addr_3==32'h908 && drif_ucb_wr_req_vld_3==1'b1 && chnl_3==1'b1)
8465 fbdic1_last_tid_3 <= ~fbdic1_last_tid_3;
8466
8467end
8468
8469assign fbdic_trans_id_0 = chnl_0 ? fbdic1_last_tid_0 : fbdic0_last_tid_0 ;
8470assign fbdic_trans_id_1 = chnl_1 ? fbdic1_last_tid_1 : fbdic0_last_tid_1 ;
8471assign fbdic_trans_id_2 = chnl_2 ? fbdic1_last_tid_2 : fbdic0_last_tid_2 ;
8472assign fbdic_trans_id_3 = chnl_3 ? fbdic1_last_tid_3 : fbdic0_last_tid_3 ;
8473
8474`ifndef DISABLE_TID_CHKR
8475
8476always @(posedge (fbdic_config_reg_write_0 && enabled))
8477begin
8478 if (fbdic_sync_frame_req_0)
8479 repeat(5) @(posedge drl2clk);
8480 else
8481 repeat(4) @(posedge drl2clk);
8482
8483 repeat(5) @(negedge sclk);
8484
8485 if ((fbdimm0a_tx_p_top[3] != fbdic_trans_id_0) && (chnl_0 == 1'b0))
8486 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm0a_tx_p_top[3], fbdic_trans_id_0);
8487
8488 if ((fbdimm0a_tx_p_top[3] == fbdic_trans_id_0) && (chnl_0 == 1'b0))
8489 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm0a_tx_p_top[3], fbdic_trans_id_0);
8490
8491 if ((fbdimm0b_tx_p_top[3] != fbdic_trans_id_0) && (chnl_0 == 1'b1))
8492 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm0b_tx_p_top[3], fbdic_trans_id_0);
8493
8494 if ((fbdimm0b_tx_p_top[3] == fbdic_trans_id_0) && (chnl_0 == 1'b1))
8495 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm0b_tx_p_top[3], fbdic_trans_id_0);
8496end
8497
8498always @(posedge (fbdic_config_reg_write_1 && enabled))
8499begin
8500 if (fbdic_sync_frame_req_1)
8501 repeat(5) @(posedge drl2clk);
8502 else
8503 repeat(4) @(posedge drl2clk);
8504
8505 repeat(5) @(negedge sclk);
8506
8507 if ((fbdimm1a_tx_p_top[3] != fbdic_trans_id_1) && (chnl_1 == 1'b0))
8508 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm1a_tx_p_top[3], fbdic_trans_id_1);
8509
8510 if ((fbdimm1a_tx_p_top[3] == fbdic_trans_id_1) && (chnl_1 == 1'b0))
8511 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm1a_tx_p_top[3], fbdic_trans_id_1);
8512
8513 if ((fbdimm1b_tx_p_top[3] != fbdic_trans_id_1) && (chnl_1 == 1'b1)) ;
8514 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm1b_tx_p_top[3], fbdic_trans_id_1);
8515
8516 if ((fbdimm1b_tx_p_top[3] == fbdic_trans_id_1) && (chnl_1 == 1'b1))
8517 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm1b_tx_p_top[3], fbdic_trans_id_1);
8518end
8519
8520always @(posedge (fbdic_config_reg_write_2 && enabled))
8521begin
8522 if (fbdic_sync_frame_req_2)
8523 repeat(5) @(posedge drl2clk);
8524 else
8525 repeat(4) @(posedge drl2clk);
8526
8527 repeat(5) @(negedge sclk);
8528
8529 if ((fbdimm2a_tx_p_top[3] != fbdic_trans_id_2) && (chnl_2 == 1'b0))
8530 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm2a_tx_p_top[3], fbdic_trans_id_2);
8531
8532 if ((fbdimm2a_tx_p_top[3] == fbdic_trans_id_2) && (chnl_2 == 1'b0))
8533 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm2a_tx_p_top[3], fbdic_trans_id_2);
8534
8535 if ((fbdimm2b_tx_p_top[3] != fbdic_trans_id_2) && (chnl_2 == 1'b1))
8536 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm2b_tx_p_top[3], fbdic_trans_id_2);
8537
8538 if ((fbdimm2b_tx_p_top[3] == fbdic_trans_id_2) && (chnl_2 == 1'b1))
8539 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm2b_tx_p_top[3], fbdic_trans_id_2);
8540end
8541
8542always @(posedge (fbdic_config_reg_write_3 && enabled))
8543begin
8544 if (fbdic_sync_frame_req_3)
8545 repeat(5) @(posedge drl2clk);
8546 else
8547 repeat(4) @(posedge drl2clk);
8548
8549 repeat(5) @(negedge sclk);
8550
8551 if ((fbdimm3a_tx_p_top[3] != fbdic_trans_id_3) && (chnl_3 == 1'b0))
8552 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm3a_tx_p_top[3], fbdic_trans_id_3);
8553
8554 if ((fbdimm3a_tx_p_top[3] == fbdic_trans_id_3) && (chnl_3 == 1'b0))
8555 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm3a_tx_p_top[3], fbdic_trans_id_3);
8556
8557 if ((fbdimm3b_tx_p_top[3] != fbdic_trans_id_3) && (chnl_3 == 1'b1))
8558 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: BAD TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm3b_tx_p_top[3], fbdic_trans_id_3);
8559
8560 if ((fbdimm3b_tx_p_top[3] == fbdic_trans_id_3) && (chnl_3 == 1'b1))
8561 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: MATCHED TID ACTUAL TID=%b EXPECTED TID=%b", fbdimm3b_tx_p_top[3], fbdic_trans_id_3);
8562end
8563
8564`endif
8565
8566//---------------------------------------------------------------
8567// Added Read Data return print statements in fbdic and X checker
8568//---------------------------------------------------------------
8569
8570always @(posedge (mcu0_rdpctl_l2t0_data_valid && enabled) or posedge (mcu0_rdpctl_l2t1_data_valid && enabled))
8571begin
8572 if (chnl_type == 1'b1) // DUAL Channel Mode for now
8573 begin
8574 @(negedge drl2clk);
8575 if (|mcu0_rddata_0 === 1'bX)
8576 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: (Chnla) Read Data = %x has X", mcu0_rddata_0);
8577 //else
8578 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: (Chnla) Read Data = %x", mcu0_rddata_0);
8579
8580 if (|mcu0_rddata_1 === 1'bX)
8581 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: (Chnlb) Read Data = %x has X", mcu0_rddata_1);
8582 //else
8583 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: (Chnlb) Read Data = %x", mcu0_rddata_1);
8584
8585 @(negedge drl2clk);
8586 if (|mcu0_rddata_0 === 1'bX)
8587 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: (Chnla) Read Data = %x has X", mcu0_rddata_0);
8588 //else
8589 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: (Chnla) Read Data = %x", mcu0_rddata_0);
8590
8591 if (|mcu0_rddata_1 === 1'bX)
8592 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: (Chnlb) Read Data = %x has X", mcu0_rddata_1);
8593 //else
8594 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: (Chnlb) Read Data = %x", mcu0_rddata_1);
8595 end
8596end
8597
8598always @(posedge (mcu1_rdpctl_l2t0_data_valid && enabled) or posedge (mcu1_rdpctl_l2t1_data_valid && enabled))
8599begin
8600 if (chnl_type == 1'b1) // DUAL Channel Mode for now
8601 begin
8602 @(negedge drl2clk);
8603 if (|mcu1_rddata_0 === 1'bX)
8604 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: (Chnla) Read Data = %x has X", mcu1_rddata_0);
8605 //else
8606 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: (Chnla) Read Data = %x", mcu1_rddata_0);
8607
8608 if (|mcu1_rddata_1 === 1'bX)
8609 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: (Chnlb) Read Data = %x has X", mcu1_rddata_1);
8610 //else
8611 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: (Chnlb) Read Data = %x", mcu1_rddata_1);
8612
8613 @(negedge drl2clk);
8614 if (|mcu1_rddata_0 === 1'bX)
8615 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: (Chnla) Read Data = %x has X", mcu1_rddata_0);
8616 //else
8617 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: (Chnla) Read Data = %x", mcu1_rddata_0);
8618
8619 if (|mcu1_rddata_1 === 1'bX)
8620 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: (Chnlb) Read Data = %x has X", mcu1_rddata_1);
8621 //else
8622 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: (Chnlb) Read Data = %x", mcu1_rddata_1);
8623 end
8624end
8625
8626always @(posedge (mcu2_rdpctl_l2t0_data_valid && enabled) or posedge (mcu2_rdpctl_l2t1_data_valid && enabled))
8627begin
8628 if (chnl_type == 1'b1) // DUAL Channel Mode for now
8629 begin
8630 @(negedge drl2clk);
8631 if (|mcu2_rddata_0 === 1'bX)
8632 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: (Chnla) Read Data = %x has X", mcu2_rddata_0);
8633 //else
8634 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: (Chnla) Read Data = %x", mcu2_rddata_0);
8635
8636 if (|mcu2_rddata_1 === 1'bX)
8637 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: (Chnlb) Read Data = %x has X", mcu2_rddata_1);
8638 //else
8639 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: (Chnlb) Read Data = %x", mcu2_rddata_1);
8640
8641 @(negedge drl2clk);
8642 if (|mcu2_rddata_0 === 1'bX)
8643 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: (Chnla) Read Data = %x has X", mcu2_rddata_0);
8644 //else
8645 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: (Chnla) Read Data = %x", mcu2_rddata_0);
8646
8647 if (|mcu2_rddata_1 === 1'bX)
8648 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: (Chnlb) Read Data = %x has X", mcu2_rddata_1);
8649 //else
8650 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: (Chnlb) Read Data = %x", mcu2_rddata_1);
8651 end
8652end
8653
8654always @(posedge (mcu3_rdpctl_l2t0_data_valid && enabled) or posedge (mcu3_rdpctl_l2t1_data_valid && enabled))
8655begin
8656 if (chnl_type == 1'b1) // DUAL Channel Mode for now
8657 begin
8658 @(negedge drl2clk);
8659 if (|mcu3_rddata_0 === 1'bX)
8660 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: (Chnla) Read Data = %x has X", mcu3_rddata_0);
8661 //else
8662 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: (Chnla) Read Data = %x", mcu3_rddata_0);
8663
8664 if (|mcu3_rddata_1 === 1'bX)
8665 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: (Chnlb) Read Data = %x has X", mcu3_rddata_1);
8666 //else
8667 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: (Chnlb) Read Data = %x", mcu3_rddata_1);
8668
8669 @(negedge drl2clk);
8670 if (|mcu3_rddata_0 === 1'bX)
8671 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: (Chnla) Read Data = %x has X", mcu3_rddata_0);
8672 //else
8673 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: (Chnla) Read Data = %x", mcu3_rddata_0);
8674
8675 if (|mcu3_rddata_1 === 1'bX)
8676 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: (Chnlb) Read Data = %x has X", mcu3_rddata_1);
8677 //else
8678 // `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: (Chnlb) Read Data = %x", mcu3_rddata_1);
8679 end
8680end
8681
8682
8683
8684// added for including code common to both MCUSAT and fullchip
8685`ifdef MCUSAT
8686 `define MCUSAT_AND_FC
8687`endif
8688`ifdef FC_CRC_INJECT
8689 `define MCUSAT_AND_FC
8690`endif
8691
8692
8693//----------------------------
8694// SYNC & Status Frame Checker
8695//----------------------------
8696`ifdef MCUSAT_AND_FC
8697initial
8698begin
8699 mcu0_chnl_lat = 0;
8700 mcu1_chnl_lat = 0;
8701 mcu2_chnl_lat = 0;
8702 mcu3_chnl_lat = 0;
8703end
8704
8705always @(posedge (fbdic_l0_state_0 && enabled))
8706begin
8707 for (mcu0_chnl_lat=0; mcu0_chnl_lat < mcu0_fbdic_chnl_read_lat[7:0]; mcu0_chnl_lat=mcu0_chnl_lat + 1) dummy=1;
8708end
8709
8710always @(posedge (fbdic_l0_state_1 && enabled))
8711begin
8712 for (mcu1_chnl_lat=0; mcu1_chnl_lat < mcu1_fbdic_chnl_read_lat[7:0]; mcu1_chnl_lat=mcu1_chnl_lat + 1) dummy=1;
8713end
8714
8715always @(posedge (fbdic_l0_state_2 && enabled))
8716begin
8717 for (mcu2_chnl_lat=0; mcu2_chnl_lat < mcu2_fbdic_chnl_read_lat[7:0]; mcu2_chnl_lat=mcu2_chnl_lat + 1) dummy=1;
8718end
8719
8720always @(posedge (fbdic_l0_state_3 && enabled))
8721begin
8722 for (mcu3_chnl_lat=0; mcu3_chnl_lat < mcu3_fbdic_chnl_read_lat[7:0]; mcu3_chnl_lat=mcu3_chnl_lat + 1) dummy=1;
8723end
8724
8725/////////////////////////////////////
8726/////////////////////////////////////
8727always @(posedge (fbdic_l0_state_0 && enabled && mcu0_fbdic_chnl_read_lat))
8728begin
8729 for (mcu0_chnl_lat_int=0; mcu0_chnl_lat_int < mcu0_fbdic_chnl_read_lat[7:0]; mcu0_chnl_lat_int=mcu0_chnl_lat_int + 1) dummy=1;
8730end
8731
8732always @(posedge (fbdic_l0_state_1 && enabled && mcu1_fbdic_chnl_read_lat))
8733begin
8734 for (mcu1_chnl_lat_int=0; mcu1_chnl_lat_int < mcu1_fbdic_chnl_read_lat[7:0]; mcu1_chnl_lat_int=mcu1_chnl_lat_int + 1) dummy=1;
8735end
8736
8737always @(posedge (fbdic_l0_state_2 && enabled && mcu2_fbdic_chnl_read_lat))
8738begin
8739 for (mcu2_chnl_lat_int=0; mcu2_chnl_lat_int < mcu2_fbdic_chnl_read_lat[7:0]; mcu2_chnl_lat_int=mcu2_chnl_lat_int + 1) dummy=1;
8740end
8741
8742always @(posedge (fbdic_l0_state_3 && enabled && mcu3_fbdic_chnl_read_lat))
8743begin
8744 for (mcu3_chnl_lat_int=0; mcu3_chnl_lat_int < mcu3_fbdic_chnl_read_lat[7:0]; mcu3_chnl_lat_int=mcu3_chnl_lat_int + 1) dummy=1;
8745end
8746
8747always @(posedge (mcu0_fbdic_sync_frame_req && enabled))
8748begin
8749 @(negedge drl2clk);
8750 case (mcu0_fbdic_sync_sd)
8751 2'b00: mcu0_sync_sd = 0;
8752 2'b01: mcu0_sync_sd = 1;
8753 2'b10: mcu0_sync_sd = 2;
8754 2'b11: mcu0_sync_sd = 3;
8755 endcase
8756
8757 repeat (mcu0_chnl_lat+mcu0_sync_sd+1) @(posedge drl2clk);
8758
8759 @(negedge drl2clk);
8760 if (mcu0_fbdic_status_frame != 1'b1 && fbdic_l0_state_0)
8761 begin
8762 if(mcu0_chnl_lat != mcu0_chnl_lat_int)
8763 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: STATUS Frame not received after %x dram cycles after SYNC Frame *** N2 T.O. BUG 121080 ***", mcu0_fbdic_chnl_read_lat[7:0]);
8764 else
8765 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: STATUS Frame not received after %x dram cycles after SYNC Frame", mcu0_fbdic_chnl_read_lat[7:0]);
8766 end
8767end
8768
8769always @(posedge (mcu1_fbdic_sync_frame_req && enabled))
8770begin
8771 @(negedge drl2clk);
8772 case (mcu1_fbdic_sync_sd)
8773 2'b00: mcu1_sync_sd = 0;
8774 2'b01: mcu1_sync_sd = 1;
8775 2'b10: mcu1_sync_sd = 2;
8776 2'b11: mcu1_sync_sd = 3;
8777 endcase
8778
8779 repeat (mcu1_chnl_lat+mcu1_sync_sd+1) @(posedge drl2clk);
8780
8781 @(negedge drl2clk);
8782 if (mcu1_fbdic_status_frame != 1'b1 && fbdic_l0_state_1)
8783 begin
8784 if(mcu1_chnl_lat != mcu1_chnl_lat_int)
8785 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: STATUS Frame not received after %x dram cycles after SYNC Frame *** N2 T.O. BUG 121080 ***", mcu1_fbdic_chnl_read_lat[7:0]);
8786 else
8787 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: STATUS Frame not received after %x dram cycles after SYNC Frame", mcu1_fbdic_chnl_read_lat[7:0]);
8788 end
8789end
8790
8791always @(posedge (mcu2_fbdic_sync_frame_req && enabled))
8792begin
8793 @(negedge drl2clk);
8794 case (mcu2_fbdic_sync_sd)
8795 2'b00: mcu2_sync_sd = 0;
8796 2'b01: mcu2_sync_sd = 1;
8797 2'b10: mcu2_sync_sd = 2;
8798 2'b11: mcu2_sync_sd = 3;
8799 endcase
8800
8801 repeat (mcu2_chnl_lat+mcu2_sync_sd+1) @(posedge drl2clk);
8802
8803 @(negedge drl2clk);
8804 if (mcu2_fbdic_status_frame != 1'b1 && fbdic_l0_state_2)
8805 begin
8806 if(mcu2_chnl_lat != mcu2_chnl_lat_int)
8807 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: STATUS Frame not received after %x dram cycles after SYNC Frame *** N2 T.O. BUG 121080 ***", mcu2_fbdic_chnl_read_lat[7:0]);
8808 else
8809 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: STATUS Frame not received after %x dram cycles after SYNC Frame", mcu2_fbdic_chnl_read_lat[7:0]);
8810 end
8811end
8812
8813always @(posedge (mcu3_fbdic_sync_frame_req && enabled))
8814begin
8815 @(negedge drl2clk);
8816 case (mcu3_fbdic_sync_sd)
8817 2'b00: mcu3_sync_sd = 0;
8818 2'b01: mcu3_sync_sd = 1;
8819 2'b10: mcu3_sync_sd = 2;
8820 2'b11: mcu3_sync_sd = 3;
8821 endcase
8822
8823 repeat (mcu3_chnl_lat+mcu3_sync_sd+1) @(posedge drl2clk);
8824
8825 @(negedge drl2clk);
8826 if (mcu3_fbdic_status_frame != 1'b1 && fbdic_l0_state_3)
8827 begin
8828 if(mcu3_chnl_lat != mcu3_chnl_lat_int)
8829 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: STATUS Frame not received after %x dram cycles after SYNC Frame *** N2 T.O. BUG 121080 ***", mcu3_fbdic_chnl_read_lat[7:0]);
8830 else
8831 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: STATUS Frame not received after %x dram cycles after SYNC Frame", mcu3_fbdic_chnl_read_lat[7:0]);
8832 end
8833end
8834`endif
8835
8836always @(posedge (mcu0_fbdic_status_frame && enabled)) begin
8837 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Frame received");
8838end
8839
8840always @(posedge (mcu1_fbdic_status_frame && enabled)) begin
8841 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Frame received");
8842end
8843
8844always @(posedge (mcu2_fbdic_status_frame && enabled)) begin
8845 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Frame received");
8846end
8847
8848always @(posedge (mcu3_fbdic_status_frame && enabled)) begin
8849 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Frame received");
8850end
8851
8852//-------------------------------
8853// SCR Frame Checkers & Monitors
8854//-------------------------------
8855
8856initial
8857begin
8858 mcu0_drif_dram_cmd_a_prev = 3'b0;
8859 mcu0_drif_dram_cmd_b_prev = 3'b0;
8860 mcu0_drif_dram_cmd_c_prev = 3'b0;
8861
8862 mcu1_drif_dram_cmd_a_prev = 3'b0;
8863 mcu1_drif_dram_cmd_b_prev = 3'b0;
8864 mcu1_drif_dram_cmd_c_prev = 3'b0;
8865
8866 mcu2_drif_dram_cmd_a_prev = 3'b0;
8867 mcu2_drif_dram_cmd_b_prev = 3'b0;
8868 mcu2_drif_dram_cmd_c_prev = 3'b0;
8869
8870 mcu3_drif_dram_cmd_a_prev = 3'b0;
8871 mcu3_drif_dram_cmd_b_prev = 3'b0;
8872 mcu3_drif_dram_cmd_c_prev = 3'b0;
8873end
8874
8875//------------------------------------------------------
8876// SCR Checker for NO CMD other than NOP/REF/DATA(Slotb)
8877//------------------------------------------------------
8878
8879always @(posedge (drl2clk && enabled))
8880begin
8881
8882 mcu0_drif_dram_cmd_a_prev <= mcu0_drif_dram_cmd_a;
8883 mcu0_drif_dram_cmd_b_prev <= mcu0_drif_dram_cmd_b;
8884 mcu0_drif_dram_cmd_c_prev <= mcu0_drif_dram_cmd_c;
8885
8886 mcu1_drif_dram_cmd_a_prev <= mcu1_drif_dram_cmd_a;
8887 mcu1_drif_dram_cmd_b_prev <= mcu1_drif_dram_cmd_b;
8888 mcu1_drif_dram_cmd_c_prev <= mcu1_drif_dram_cmd_c;
8889
8890 mcu2_drif_dram_cmd_a_prev <= mcu2_drif_dram_cmd_a;
8891 mcu2_drif_dram_cmd_b_prev <= mcu2_drif_dram_cmd_b;
8892 mcu2_drif_dram_cmd_c_prev <= mcu2_drif_dram_cmd_c;
8893
8894 mcu3_drif_dram_cmd_a_prev <= mcu3_drif_dram_cmd_a;
8895 mcu3_drif_dram_cmd_b_prev <= mcu3_drif_dram_cmd_b;
8896 mcu3_drif_dram_cmd_c_prev <= mcu3_drif_dram_cmd_c;
8897
8898end
8899
8900//-------------------------
8901// SCR NOP Checker
8902//-------------------------
8903
8904always @(posedge (mcu0_fbdic_scr_frame_req && enabled)) begin
8905 if (mcu0_drif_dram_cmd_a_prev || mcu0_drif_dram_cmd_b_prev || mcu0_drif_dram_cmd_c_prev)
8906 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: should not issue a CMD a cycle earlier than SCR frame req");
8907
8908 if (mcu0_drif_dram_cmd_a || mcu0_drif_dram_cmd_b || mcu0_drif_dram_cmd_c)
8909 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: should not issue a CMD when SCR frame req is issued");
8910
8911 @(posedge drl2clk);
8912 if (mcu0_drif_dram_cmd_a || mcu0_drif_dram_cmd_b || mcu0_drif_dram_cmd_c)
8913 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: should not issue a CMD 1 cycle after SCR frame req is issued");
8914
8915 @(posedge drl2clk);
8916 if (mcu0_drif_dram_cmd_a || mcu0_drif_dram_cmd_b || mcu0_drif_dram_cmd_c)
8917 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: should not issue a CMD 2 cycles after SCR frame req is issued");
8918
8919 @(posedge drl2clk);
8920 if (mcu0_drif_dram_cmd_a || mcu0_drif_dram_cmd_b || mcu0_drif_dram_cmd_c)
8921 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: should not issue a CMD 3 cycles after SCR frame req is issued");
8922
8923 @(posedge drl2clk);
8924 if (mcu0_drif_dram_cmd_a || mcu0_drif_dram_cmd_b || mcu0_drif_dram_cmd_c)
8925 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: should not issue a CMD 4 cycles after SCR frame req is issued");
8926
8927end
8928
8929always @(posedge (mcu1_fbdic_scr_frame_req && enabled)) begin
8930 if (mcu1_drif_dram_cmd_a_prev || mcu1_drif_dram_cmd_b_prev || mcu1_drif_dram_cmd_c_prev)
8931 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: should not issue a CMD a cycle earlier than SCR frame req");
8932
8933 if (mcu1_drif_dram_cmd_a || mcu1_drif_dram_cmd_b || mcu1_drif_dram_cmd_c)
8934 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: should not issue a CMD when SCR frame req is issued");
8935
8936 @(posedge drl2clk);
8937 if (mcu1_drif_dram_cmd_a || mcu1_drif_dram_cmd_b || mcu1_drif_dram_cmd_c)
8938 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: should not issue a CMD 1 cycle after SCR frame req is issued");
8939
8940 @(posedge drl2clk);
8941 if (mcu1_drif_dram_cmd_a || mcu1_drif_dram_cmd_b || mcu1_drif_dram_cmd_c)
8942 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: should not issue a CMD 2 cycles after SCR frame req is issued");
8943
8944 @(posedge drl2clk);
8945 if (mcu1_drif_dram_cmd_a || mcu1_drif_dram_cmd_b || mcu1_drif_dram_cmd_c)
8946 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: should not issue a CMD 3 cycles after SCR frame req is issued");
8947
8948 @(posedge drl2clk);
8949 if (mcu1_drif_dram_cmd_a || mcu1_drif_dram_cmd_b || mcu1_drif_dram_cmd_c)
8950 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: should not issue a CMD 4 cycles after SCR frame req is issued");
8951
8952end
8953
8954always @(posedge (mcu2_fbdic_scr_frame_req && enabled)) begin
8955 if (mcu2_drif_dram_cmd_a_prev || mcu2_drif_dram_cmd_b_prev || mcu2_drif_dram_cmd_c_prev)
8956 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: should not issue a CMD a cycle earlier than SCR frame req");
8957
8958 if (mcu2_drif_dram_cmd_a || mcu2_drif_dram_cmd_b || mcu2_drif_dram_cmd_c)
8959 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: should not issue a CMD when SCR frame req is issued");
8960
8961 @(posedge drl2clk);
8962 if (mcu2_drif_dram_cmd_a || mcu2_drif_dram_cmd_b || mcu2_drif_dram_cmd_c)
8963 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: should not issue a CMD 1 cycle after SCR frame req is issued");
8964
8965 @(posedge drl2clk);
8966 if (mcu2_drif_dram_cmd_a || mcu2_drif_dram_cmd_b || mcu2_drif_dram_cmd_c)
8967 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: should not issue a CMD 2 cycles after SCR frame req is issued");
8968
8969 @(posedge drl2clk);
8970 if (mcu2_drif_dram_cmd_a || mcu2_drif_dram_cmd_b || mcu2_drif_dram_cmd_c)
8971 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: should not issue a CMD 3 cycles after SCR frame req is issued");
8972
8973 @(posedge drl2clk);
8974 if (mcu2_drif_dram_cmd_a || mcu2_drif_dram_cmd_b || mcu2_drif_dram_cmd_c)
8975 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: should not issue a CMD 4 cycles after SCR frame req is issued");
8976
8977end
8978
8979always @(posedge (mcu3_fbdic_scr_frame_req && enabled)) begin
8980 if (mcu3_drif_dram_cmd_a_prev || mcu3_drif_dram_cmd_b_prev || mcu3_drif_dram_cmd_c_prev)
8981 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: should not issue a CMD a cycle earlier than SCR frame req");
8982
8983 if (mcu3_drif_dram_cmd_a || mcu3_drif_dram_cmd_b || mcu3_drif_dram_cmd_c)
8984 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: should not issue a CMD when SCR frame req is issued");
8985
8986 @(posedge drl2clk);
8987 if (mcu3_drif_dram_cmd_a || mcu3_drif_dram_cmd_b || mcu3_drif_dram_cmd_c)
8988 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: should not issue a CMD 1 cycle after SCR frame req is issued");
8989
8990 @(posedge drl2clk);
8991 if (mcu3_drif_dram_cmd_a || mcu3_drif_dram_cmd_b || mcu3_drif_dram_cmd_c)
8992 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: should not issue a CMD 2 cycles after SCR frame req is issued");
8993
8994 @(posedge drl2clk);
8995 if (mcu3_drif_dram_cmd_a || mcu3_drif_dram_cmd_b || mcu3_drif_dram_cmd_c)
8996 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: should not issue a CMD 3 cycles after SCR frame req is issued");
8997
8998 @(posedge drl2clk);
8999 if (mcu3_drif_dram_cmd_a || mcu3_drif_dram_cmd_b || mcu3_drif_dram_cmd_c)
9000 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: should not issue a CMD 4 cycles after SCR frame req is issued");
9001
9002end
9003
9004//-----------------------------
9005// SCR Frame request Monitor
9006//-----------------------------
9007
9008always @(posedge (mcu0_fbdic_scr_frame_req && enabled)) begin
9009 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: SCR (Soft Channel Reset) Frame issued");
9010end
9011
9012always @(posedge (mcu1_fbdic_scr_frame_req && enabled)) begin
9013 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: SCR (Soft Channel Reset) Frame issued");
9014end
9015
9016always @(posedge (mcu2_fbdic_scr_frame_req && enabled)) begin
9017 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: SCR (Soft Channel Reset) Frame issued");
9018end
9019
9020always @(posedge (mcu3_fbdic_scr_frame_req && enabled)) begin
9021 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: SCR (Soft Channel Reset) Frame issued");
9022end
9023
9024//-----------------------------
9025// SCR Status Response Monitor
9026//-----------------------------
9027
9028always @(posedge (mcu0_fbdic_scr_response_frame && enabled)) begin
9029 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: SCR (Soft Channel Reset) Frame Response received");
9030end
9031
9032always @(posedge (mcu1_fbdic_scr_response_frame && enabled)) begin
9033 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: SCR (Soft Channel Reset) Frame Response received");
9034end
9035
9036always @(posedge (mcu2_fbdic_scr_response_frame && enabled)) begin
9037 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: SCR (Soft Channel Reset) Frame Response received");
9038end
9039
9040always @(posedge (mcu3_fbdic_scr_response_frame && enabled)) begin
9041 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: SCR (Soft Channel Reset) Frame Response received");
9042end
9043
9044//-----------------------------
9045// Status Parity Detect Monitor
9046//-----------------------------
9047
9048always @ (posedge (mcu0_fbdic_status_parity_error && enabled))
9049 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Parity err asserted");
9050
9051always @ (posedge (mcu1_fbdic_status_parity_error && enabled))
9052 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Parity err asserted");
9053
9054always @ (posedge (mcu2_fbdic_status_parity_error && enabled))
9055 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Parity err asserted");
9056
9057always @ (posedge (mcu3_fbdic_status_parity_error && enabled))
9058 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Parity err asserted");
9059
9060always @ (negedge (mcu0_fbdic_status_parity_error && enabled))
9061 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Parity err de-asserted");
9062
9063always @ (negedge (mcu1_fbdic_status_parity_error && enabled))
9064 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Parity err de-asserted");
9065
9066always @ (negedge (mcu2_fbdic_status_parity_error && enabled))
9067 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Parity err de-asserted");
9068
9069always @ (negedge (mcu3_fbdic_status_parity_error && enabled))
9070 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Parity err de-asserted");
9071
9072//-----------------------------
9073// Status Alert Detect Monitor
9074//-----------------------------
9075
9076always @ (posedge (mcu0_fbdic_status_alert_error && enabled))
9077 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Alert bit err asserted");
9078
9079always @ (posedge (mcu1_fbdic_status_alert_error && enabled))
9080 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Alert bit err asserted");
9081
9082always @ (posedge (mcu2_fbdic_status_alert_error && enabled))
9083 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Alert bit err asserted");
9084
9085always @ (posedge (mcu3_fbdic_status_alert_error && enabled))
9086 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Alert bit err asserted");
9087
9088always @ (negedge (mcu0_fbdic_status_alert_error && enabled))
9089 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Alert bit err de-asserted");
9090
9091always @ (negedge (mcu1_fbdic_status_alert_error && enabled))
9092 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Alert bit err de-asserted");
9093
9094always @ (negedge (mcu2_fbdic_status_alert_error && enabled))
9095 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Alert bit err de-asserted");
9096
9097always @ (negedge (mcu3_fbdic_status_alert_error && enabled))
9098 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Alert bit err de-asserted");
9099
9100
9101//-----------------------------
9102// Status Alert Detect Monitor
9103//-----------------------------
9104
9105always @ (posedge (mcu0_fbdic_alert_frame && enabled))
9106 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Alert Frame err asserted");
9107
9108always @ (posedge (mcu1_fbdic_alert_frame && enabled))
9109 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Alert Frame err asserted");
9110
9111always @ (posedge (mcu2_fbdic_alert_frame && enabled))
9112 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Alert Frame err asserted");
9113
9114always @ (posedge (mcu3_fbdic_alert_frame && enabled))
9115 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Alert Frame err asserted");
9116
9117always @ (negedge (mcu0_fbdic_alert_frame && enabled)) begin
9118 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU0: STATUS Alert Frame err de-asserted");
9119end
9120
9121always @ (negedge (mcu1_fbdic_alert_frame && enabled))
9122 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU1: STATUS Alert Frame err de-asserted");
9123
9124always @ (negedge (mcu2_fbdic_alert_frame && enabled))
9125 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU2: STATUS Alert Frame err de-asserted");
9126
9127always @ (negedge (mcu3_fbdic_alert_frame && enabled))
9128 `PR_DEBUG ("mcu_fmon", `DEBUG, "MCU3: STATUS Alert Frame err de-asserted");
9129
9130//---------------------------------------------------
9131// Electrical Idle Checker
9132//---------------------------------------------------
9133
9134reg [3:0] EI_CNT, EI_CNT_CYCLE;
9135reg EI_checker;
9136
9137initial
9138begin
9139 EI_CNT = 3'h0;
9140 if ($test$plusargs("EI_checker_disable"))
9141 EI_checker = 1'b0;
9142 else
9143 EI_checker = 1'b1;
9144
9145 if ($test$plusargs("RANDOM_PARAM"))
9146 EI_CNT_CYCLE = 4'hA;
9147 else
9148`ifdef NEC_FBDIMM
9149 EI_CNT_CYCLE = 4'hA;
9150`else
9151 EI_CNT_CYCLE = 4'h5;
9152`endif
9153end
9154
9155always @ (posedge (drl2clk && EI_checker && enabled))
9156begin
9157
9158 if ((fbdimm0a_rx_p_top == fbdimm0a_rx_n_top) && (fbdimm0b_rx_p_top == fbdimm0b_rx_n_top))
9159 EI_CNT = EI_CNT + 1'b1;
9160 else
9161 EI_CNT = 1'b0;
9162
9163 if (EI_CNT == EI_CNT_CYCLE) begin
9164 if (mcu0_fbd0_elect_idle != 14'h3fff)
9165 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: FBD0 Electrical Idle bits not set %x", mcu0_fbd0_elect_idle);
9166 if (mcu0_fbd1_elect_idle != 14'h3fff && chnl_type == 1'b1)
9167 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: FBD1 Electrical Idle bits not set %x", mcu0_fbd1_elect_idle);
9168 end
9169end
9170
9171//----------------------------------------------------
9172// SERDES Checkers (ENIDL)
9173//----------------------------------------------------
9174
9175`ifdef MCUSAT
9176always @ (posedge (`MCU0.mcu_fsr0_cfgtx_enidl && enabled))
9177begin
9178 if (fbdic_fbd_state_0 != 8'h0)
9179 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: ENIDL to SERDES should be asserted during DISABLE STATE");
9180end
9181
9182always @ (negedge (`MCU0.mcu_fsr0_cfgtx_enidl && enabled))
9183begin
9184 if (fbdic_fbd_state_0 == 8'h0)
9185 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: ENIDL to SERDES should not be de-asserted during DISABLE STATE");
9186end
9187
9188`ifndef SNG_CHANNEL
9189always @ (posedge (`MCU0.mcu_fsr1_cfgtx_enidl && enabled))
9190if (chnl_type)
9191begin
9192 if (fbdic_fbd_state_0 != 8'h0)
9193 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: ENIDL to SERDES should be asserted during DISABLE STATE");
9194end
9195
9196always @ (negedge (`MCU0.mcu_fsr1_cfgtx_enidl && enabled))
9197if (chnl_type)
9198begin
9199 if (fbdic_fbd_state_0 == 8'h0)
9200 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: ENIDL to SERDES should not be de-asserted during DISABLE STATE");
9201end
9202`endif
9203
9204`endif
9205
9206//---------------------------------------------------
9207// FBD Init Checkers
9208//---------------------------------------------------
9209
9210reg [7:0] prev_fbdic_fbd_state_0;
9211
9212initial prev_fbdic_fbd_state_0 = 8'h0;
9213
9214always @ (fbdic_fbd_state_0)
9215if (enabled && ~dtm_enabled)
9216begin
9217 if (fbdic_fbd_state_0 == 8'h0)
9218 begin
9219 repeat (25) @ (posedge drl2clk);
9220 if (`MCU0.fbdic.fbdic_tdisable_done != 1'b0)
9221 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: fbdic_tdisable_done bit should be reset during initial part of DISABLE STATE");
9222 if ((`MCU0.fbdic.fbdic_tcalibrate_done != 1'b0) && (prev_fbdic_fbd_state_0 != 8'h1))
9223 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: fbdic_tcalibrate_done bit should be reset during DISABLE STATE");
9224 if (`MCU0.fbdic.fbdic_tclktrain_done[0] != 1'b0)
9225 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: fbdic_tclktrain_done bit should be reset during DISABLE STATE");
9226 if (`MCU0.fbdic.fbdic_testing_done[0] != 1'b0)
9227 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: fbdic_testing_done bit should be reset during DISABLE STATE");
9228 if (`MCU0.fbdic.fbdic_polling_done[0] != 1'b0)
9229 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: fbdic_polling_done bit should be reset during DISABLE STATE");
9230 if (`MCU0.fbdic.fbdic_config_done[0] != 1'b0)
9231 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: fbdic_config_done bit should be reset during DISABLE STATE");
9232 end
9233 prev_fbdic_fbd_state_0 = fbdic_fbd_state_0;
9234end
9235
9236
9237always @(posedge (drl2clk && enabled))
9238begin
9239
9240 if (~dtm_enabled && fbd_init_check)
9241 begin
9242 case (fbdic_fbd_state_0)
9243 8'h3: begin
9244 if (mcu0_fbdic_tclktrain_done[0] != 1'b1)
9245 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Training Done Bit should be asserted after TRAINING STATE");
9246 end
9247 8'h4: begin
9248 if (mcu0_fbdic_testing_done[0] != 1'b1)
9249 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Testing Done Bit should be asserted after TESTING STATE");
9250 end
9251 8'h5: begin
9252 if (mcu0_fbdic_polling_done[0] != 1'b1)
9253 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Polling Done Bit should be asserted after POLLING STATE");
9254 end
9255 8'h6: begin
9256 if (mcu0_fbdic_config_done[0] != 1'b1)
9257 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Config Done Bit should be asserted after CONFIG STATE");
9258 end
9259 default: begin
9260 end
9261 endcase
9262
9263 case (fbdic_fbd_state_1)
9264 8'h3: begin
9265 if (mcu1_fbdic_tclktrain_done[0] != 1'b1)
9266 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Training Done Bit should be asserted after TRAINING STATE");
9267 end
9268 8'h4: begin
9269 if (mcu1_fbdic_testing_done[0] != 1'b1)
9270 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Testing Done Bit should be asserted after TESTING STATE");
9271 end
9272 8'h5: begin
9273 if (mcu1_fbdic_polling_done[0] != 1'b1)
9274 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Polling Done Bit should be asserted after POLLING STATE");
9275 end
9276 8'h6: begin
9277 if (mcu1_fbdic_config_done[0] != 1'b1)
9278 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Config Done Bit should be asserted after CONFIG STATE");
9279 end
9280 default: begin
9281 end
9282 endcase
9283
9284 case (fbdic_fbd_state_2)
9285 8'h3: begin
9286 if (mcu2_fbdic_tclktrain_done[0] != 1'b1)
9287 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Training Done Bit should be asserted after TRAINING STATE");
9288 end
9289 8'h4: begin
9290 if (mcu2_fbdic_testing_done[0] != 1'b1)
9291 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Testing Done Bit should be asserted after TESTING STATE");
9292 end
9293 8'h5: begin
9294 if (mcu2_fbdic_polling_done[0] != 1'b1)
9295 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Polling Done Bit should be asserted after POLLING STATE");
9296 end
9297 8'h6: begin
9298 if (mcu2_fbdic_config_done[0] != 1'b1)
9299 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Config Done Bit should be asserted after CONFIG STATE");
9300 end
9301 default: begin
9302 end
9303 endcase
9304
9305 case (fbdic_fbd_state_3)
9306 8'h3: begin
9307 if (mcu3_fbdic_tclktrain_done[0] != 1'b1)
9308 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Training Done Bit should be asserted after TRAINING STATE");
9309 end
9310 8'h4: begin
9311 if (mcu3_fbdic_testing_done[0] != 1'b1)
9312 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Testing Done Bit should be asserted after TESTING STATE");
9313 end
9314 8'h5: begin
9315 if (mcu3_fbdic_polling_done[0] != 1'b1)
9316 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Polling Done Bit should be asserted after POLLING STATE");
9317 end
9318 8'h6: begin
9319 if (mcu3_fbdic_config_done[0] != 1'b1)
9320 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Config Done Bit should be asserted after CONFIG STATE");
9321 end
9322 default: begin
9323 end
9324 endcase
9325 end
9326
9327end
9328
9329always @(posedge (drl2clk && enabled))
9330begin
9331
9332if(!mcu0_training_err_enable)
9333begin
9334#(`SMPL);
9335 if (mcu0_fbdic_tclktrain_done[1] == 1'b1)
9336 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Training Error Bit asserted");
9337
9338 if (mcu0_fbdic_testing_done[1] == 1'b1)
9339 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Testing Error Bit asserted");
9340
9341 if (mcu0_fbdic_polling_done[1] == 1'b1)
9342 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Polling Error Bit asserted");
9343
9344 if (mcu0_fbdic_config_done[1] == 1'b1)
9345 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Config Error Bit asserted");
9346end
9347
9348if(!mcu1_training_err_enable)
9349begin
9350#(`SMPL);
9351 if (mcu1_fbdic_tclktrain_done[1] == 1'b1)
9352 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Training Error Bit asserted");
9353
9354 if (mcu1_fbdic_testing_done[1] == 1'b1)
9355 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Testing Error Bit asserted");
9356
9357 if (mcu1_fbdic_polling_done[1] == 1'b1)
9358 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Polling Error Bit asserted");
9359
9360 if (mcu1_fbdic_config_done[1] == 1'b1)
9361 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Config Error Bit asserted");
9362
9363end
9364
9365if(!mcu2_training_err_enable)
9366begin
9367#(`SMPL);
9368 if (mcu2_fbdic_tclktrain_done[1] == 1'b1)
9369 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Training Error Bit asserted");
9370
9371 if (mcu2_fbdic_testing_done[1] == 1'b1)
9372 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Testing Error Bit asserted");
9373
9374 if (mcu2_fbdic_polling_done[1] == 1'b1)
9375 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Polling Error Bit asserted");
9376
9377 if (mcu2_fbdic_config_done[1] == 1'b1)
9378 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Config Error Bit asserted");
9379
9380end
9381
9382if(!mcu3_training_err_enable)
9383begin
9384#(`SMPL);
9385 if (mcu3_fbdic_tclktrain_done[1] == 1'b1)
9386 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Training Error Bit asserted");
9387
9388 if (mcu3_fbdic_testing_done[1] == 1'b1)
9389 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Testing Error Bit asserted");
9390
9391 if (mcu3_fbdic_polling_done[1] == 1'b1)
9392 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Polling Error Bit asserted");
9393
9394 if (mcu3_fbdic_config_done[1] == 1'b1)
9395 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Config Error Bit asserted");
9396end
9397
9398end
9399
9400//----------------------------------------------------------
9401// Arbritration/Collision Checkers
9402//----------------------------------------------------------
9403
9404// Make sure CMDs sent from DRIF -> FBDIC are asserted for
9405// 2 cycles if sync_frame req are asserted at same time
9406
9407//-----
9408// MCU0
9409
9410always @ (posedge (mcu0_drif_ucb_wr_req_vld && fbdic_sync_frame_req_0 && enabled))
9411begin
9412 mcu0_drif_ucb_wr_req_vld_REG = mcu0_drif_ucb_wr_req_vld;
9413 @ (posedge drl2clk);
9414 if (mcu0_drif_ucb_wr_req_vld != mcu0_drif_ucb_wr_req_vld_REG)
9415 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: DRIF needs to assert drif_ucb_wr_req_vld for 1 more cycle");
9416end
9417
9418always @ (posedge (mcu0_drif_ucb_rd_req_vld && fbdic_sync_frame_req_0 && enabled))
9419begin
9420 mcu0_drif_ucb_rd_req_vld_REG = mcu0_drif_ucb_rd_req_vld;
9421 @ (posedge drl2clk);
9422 if (mcu0_drif_ucb_rd_req_vld != mcu0_drif_ucb_rd_req_vld_REG)
9423 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: DRIF needs to assert drif_ucb_rd_req_vld for 1 more cycle");
9424end
9425
9426always @ (mcu0_drif_dram_cmd_a)
9427if (enabled && fbdic_sync_frame_req_0 && (mcu0_drif_dram_cmd_a==`ACT || mcu0_drif_dram_cmd_a==`WR || mcu0_drif_dram_cmd_a==`RD))
9428begin
9429 mcu0_drif_dram_cmd_a_REG = mcu0_drif_dram_cmd_a;
9430 @ (posedge drl2clk);
9431 if (mcu0_drif_dram_cmd_a != mcu0_drif_dram_cmd_a_REG)
9432 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: DRIF needs to assert mcu0_drif_dram_cmd_a for 1 more cycle");
9433end
9434
9435always @ (mcu0_drif_dram_cmd_b)
9436if (enabled && fbdic_sync_frame_req_0 && (mcu0_drif_dram_cmd_b==`ACT || mcu0_drif_dram_cmd_b==`WR))
9437begin
9438 mcu0_drif_dram_cmd_b_REG = mcu0_drif_dram_cmd_b;
9439 @ (posedge drl2clk);
9440 if (mcu0_drif_dram_cmd_b != mcu0_drif_dram_cmd_b_REG)
9441 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: DRIF needs to assert mcu0_drif_dram_cmd_b for 1 more cycle");
9442end
9443
9444always @ (mcu0_drif_dram_cmd_c)
9445if (enabled && fbdic_sync_frame_req_0 && (mcu0_drif_dram_cmd_c==`ACT || mcu0_drif_dram_cmd_c==`WR))
9446begin
9447 mcu0_drif_dram_cmd_c_REG = mcu0_drif_dram_cmd_c;
9448 @ (posedge drl2clk);
9449 if (mcu0_drif_dram_cmd_c != mcu0_drif_dram_cmd_c_REG)
9450 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: DRIF needs to assert mcu0_drif_dram_cmd_c for 1 more cycle");
9451end
9452
9453//-----
9454// MCU1
9455
9456always @ (posedge (mcu1_drif_ucb_wr_req_vld && fbdic_sync_frame_req_1 && enabled))
9457begin
9458 mcu1_drif_ucb_wr_req_vld_REG = mcu1_drif_ucb_wr_req_vld;
9459 @ (posedge drl2clk);
9460 if (mcu1_drif_ucb_wr_req_vld != mcu1_drif_ucb_wr_req_vld_REG)
9461 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: DRIF needs to assert drif_ucb_wr_req_vld for 1 more cycle");
9462end
9463
9464always @ (posedge (mcu1_drif_ucb_rd_req_vld && fbdic_sync_frame_req_1 && enabled))
9465begin
9466 mcu1_drif_ucb_rd_req_vld_REG = mcu1_drif_ucb_rd_req_vld;
9467 @ (posedge drl2clk);
9468 if (mcu1_drif_ucb_rd_req_vld != mcu1_drif_ucb_rd_req_vld_REG)
9469 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: DRIF needs to assert drif_ucb_rd_req_vld for 1 more cycle");
9470end
9471
9472always @ (mcu1_drif_dram_cmd_a)
9473if (enabled && fbdic_sync_frame_req_1 && (mcu1_drif_dram_cmd_a==`ACT || mcu1_drif_dram_cmd_a==`WR || mcu1_drif_dram_cmd_a==`RD))
9474begin
9475 mcu1_drif_dram_cmd_a_REG = mcu1_drif_dram_cmd_a;
9476 @ (posedge drl2clk);
9477 if (mcu1_drif_dram_cmd_a != mcu1_drif_dram_cmd_a_REG)
9478 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: DRIF needs to assert mcu1_drif_dram_cmd_a for 1 more cycle");
9479end
9480
9481always @ (mcu1_drif_dram_cmd_b)
9482if (enabled && fbdic_sync_frame_req_1 && (mcu1_drif_dram_cmd_b==`ACT || mcu1_drif_dram_cmd_b==`WR))
9483begin
9484 mcu1_drif_dram_cmd_b_REG = mcu1_drif_dram_cmd_b;
9485 @ (posedge drl2clk);
9486 if (mcu1_drif_dram_cmd_b != mcu1_drif_dram_cmd_b_REG)
9487 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: DRIF needs to assert mcu1_drif_dram_cmd_b for 1 more cycle");
9488end
9489
9490always @ (mcu1_drif_dram_cmd_c)
9491if (enabled && fbdic_sync_frame_req_1 && (mcu1_drif_dram_cmd_c==`ACT || mcu1_drif_dram_cmd_c==`WR))
9492begin
9493 mcu1_drif_dram_cmd_c_REG = mcu1_drif_dram_cmd_c;
9494 @ (posedge drl2clk);
9495 if (mcu1_drif_dram_cmd_c != mcu1_drif_dram_cmd_c_REG)
9496 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: DRIF needs to assert mcu1_drif_dram_cmd_c for 1 more cycle");
9497end
9498
9499//-----
9500// MCU2
9501
9502always @ (posedge (mcu2_drif_ucb_wr_req_vld && fbdic_sync_frame_req_2 && enabled))
9503begin
9504 mcu2_drif_ucb_wr_req_vld_REG = mcu2_drif_ucb_wr_req_vld;
9505 @ (posedge drl2clk);
9506 if (mcu2_drif_ucb_wr_req_vld != mcu2_drif_ucb_wr_req_vld_REG)
9507 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: DRIF needs to assert drif_ucb_wr_req_vld for 1 more cycle");
9508end
9509
9510always @ (posedge (mcu2_drif_ucb_rd_req_vld && fbdic_sync_frame_req_2 && enabled))
9511begin
9512 mcu2_drif_ucb_rd_req_vld_REG = mcu2_drif_ucb_rd_req_vld;
9513 @ (posedge drl2clk);
9514 if (mcu2_drif_ucb_rd_req_vld != mcu2_drif_ucb_rd_req_vld_REG)
9515 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: DRIF needs to assert drif_ucb_rd_req_vld for 1 more cycle");
9516end
9517
9518always @ (mcu2_drif_dram_cmd_a)
9519if (enabled && fbdic_sync_frame_req_2 && (mcu2_drif_dram_cmd_a==`ACT || mcu2_drif_dram_cmd_a==`WR || mcu2_drif_dram_cmd_a==`RD))
9520begin
9521 mcu2_drif_dram_cmd_a_REG = mcu2_drif_dram_cmd_a;
9522 @ (posedge drl2clk);
9523 if (mcu2_drif_dram_cmd_a != mcu2_drif_dram_cmd_a_REG)
9524 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: DRIF needs to assert mcu2_drif_dram_cmd_a for 1 more cycle");
9525end
9526
9527always @ (mcu2_drif_dram_cmd_b)
9528if (enabled && fbdic_sync_frame_req_2 && (mcu2_drif_dram_cmd_b==`ACT || mcu2_drif_dram_cmd_b==`WR))
9529begin
9530 mcu2_drif_dram_cmd_b_REG = mcu2_drif_dram_cmd_b;
9531 @ (posedge drl2clk);
9532 if (mcu2_drif_dram_cmd_b != mcu2_drif_dram_cmd_b_REG)
9533 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: DRIF needs to assert mcu2_drif_dram_cmd_b for 1 more cycle");
9534end
9535
9536always @ (mcu2_drif_dram_cmd_c)
9537if (enabled && fbdic_sync_frame_req_2 && (mcu2_drif_dram_cmd_c==`ACT || mcu2_drif_dram_cmd_c==`WR))
9538begin
9539 mcu2_drif_dram_cmd_c_REG = mcu2_drif_dram_cmd_c;
9540 @ (posedge drl2clk);
9541 if (mcu2_drif_dram_cmd_c != mcu2_drif_dram_cmd_c_REG)
9542 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: DRIF needs to assert mcu2_drif_dram_cmd_c for 1 more cycle");
9543end
9544
9545//-----
9546// MCU3
9547
9548always @ (posedge (mcu3_drif_ucb_wr_req_vld && fbdic_sync_frame_req_3 && enabled))
9549begin
9550 mcu3_drif_ucb_wr_req_vld_REG = mcu3_drif_ucb_wr_req_vld;
9551 @ (posedge drl2clk);
9552 if (mcu3_drif_ucb_wr_req_vld != mcu3_drif_ucb_wr_req_vld_REG)
9553 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: DRIF needs to assert drif_ucb_wr_req_vld for 1 more cycle");
9554end
9555
9556always @ (posedge (mcu3_drif_ucb_rd_req_vld && fbdic_sync_frame_req_3 && enabled))
9557begin
9558 mcu3_drif_ucb_rd_req_vld_REG = mcu3_drif_ucb_rd_req_vld;
9559 @ (posedge drl2clk);
9560 if (mcu3_drif_ucb_rd_req_vld != mcu3_drif_ucb_rd_req_vld_REG)
9561 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: DRIF needs to assert drif_ucb_rd_req_vld for 1 more cycle");
9562end
9563
9564always @ (mcu3_drif_dram_cmd_a)
9565if (enabled && fbdic_sync_frame_req_3 && (mcu3_drif_dram_cmd_a==`ACT || mcu3_drif_dram_cmd_a==`WR || mcu3_drif_dram_cmd_a==`RD))
9566begin
9567 mcu3_drif_dram_cmd_a_REG = mcu3_drif_dram_cmd_a;
9568 @ (posedge drl2clk);
9569 if (mcu3_drif_dram_cmd_a != mcu3_drif_dram_cmd_a_REG)
9570 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: DRIF needs to assert mcu3_drif_dram_cmd_a for 1 more cycle");
9571end
9572
9573always @ (mcu3_drif_dram_cmd_b)
9574if (enabled && fbdic_sync_frame_req_3 && (mcu3_drif_dram_cmd_b==`ACT || mcu3_drif_dram_cmd_b==`WR))
9575begin
9576 mcu3_drif_dram_cmd_b_REG = mcu3_drif_dram_cmd_b;
9577 @ (posedge drl2clk);
9578 if (mcu3_drif_dram_cmd_b != mcu3_drif_dram_cmd_b_REG)
9579 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: DRIF needs to assert mcu3_drif_dram_cmd_b for 1 more cycle");
9580end
9581
9582always @ (mcu3_drif_dram_cmd_c)
9583if (enabled && fbdic_sync_frame_req_3 && (mcu3_drif_dram_cmd_c==`ACT || mcu3_drif_dram_cmd_c==`WR))
9584begin
9585 mcu3_drif_dram_cmd_c_REG = mcu3_drif_dram_cmd_c;
9586 @ (posedge drl2clk);
9587 if (mcu3_drif_dram_cmd_c != mcu3_drif_dram_cmd_c_REG)
9588 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: DRIF needs to assert mcu3_drif_dram_cmd_c for 1 more cycle");
9589end
9590
9591//-------------------------
9592// Refresh Checker Signals
9593//-------------------------
9594
9595always @(posedge (drl2clk && enabled))
9596begin
9597 if (mcu0_drif_mcu_state_next == 5'h5)
9598 begin
9599 if (ref_state5_cycle_0 < 4) // wait for 4 cycles as auto ref is issued
9600 ref_state5_cycle_0 = ref_state5_cycle_0 + 1;
9601 else
9602 begin
9603 if ((mcu0_drif_dram_cmd_a != 3'b0) || (mcu0_drif_dram_cmd_b != 3'b0 && mcu0_drif_dram_cmd_b != 3'h5) || (mcu0_drif_dram_cmd_c != 3'b0))
9604 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Issued CMD other than NOP during Self Refresh STATE");
9605 end
9606 end
9607 else
9608 ref_state5_cycle_0 = 0;
9609
9610 if (mcu0_drif_mcu_state_next == 5'h6)
9611 begin
9612 if (ref_state6_cycle_0 < 4) // wait for 4 cycles as auto ref is issued
9613 ref_state6_cycle_0 = ref_state6_cycle_0 + 1;
9614 else
9615 begin
9616 if ((mcu0_drif_dram_cmd_a != 3'b0) || (mcu0_drif_dram_cmd_b != 3'b0 && mcu0_drif_dram_cmd_b != 3'h5) || (mcu0_drif_dram_cmd_c != 3'b0))
9617 `PR_ERROR ("mcu_fmon", `ERROR, "MCU0: Issued CMD other than NOP during Power Down STATE");
9618 end
9619 end
9620 else
9621 ref_state6_cycle_0 = 0;
9622
9623 if (mcu1_drif_mcu_state_next == 5'h5)
9624 begin
9625 if (ref_state5_cycle_1 < 4) // wait for 4 cycles as auto ref is issued
9626 ref_state5_cycle_1 = ref_state5_cycle_1 + 1;
9627 else
9628 begin
9629 if ((mcu1_drif_dram_cmd_a != 3'b0) || (mcu1_drif_dram_cmd_b != 3'b0 && mcu1_drif_dram_cmd_b != 3'h5) || (mcu1_drif_dram_cmd_c != 3'b0))
9630 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Issued CMD other than NOP during Self Refresh STATE");
9631 end
9632 end
9633 else
9634 ref_state5_cycle_1 = 0;
9635
9636 if (mcu1_drif_mcu_state_next == 5'h6)
9637 begin
9638 if (ref_state6_cycle_1 < 4) // wait for 4 cycles as auto ref is issued
9639 ref_state6_cycle_1 = ref_state6_cycle_1 + 1;
9640 else
9641 begin
9642 if ((mcu1_drif_dram_cmd_a != 3'b0) || (mcu1_drif_dram_cmd_b != 3'b0 && mcu1_drif_dram_cmd_b != 3'h5) || (mcu1_drif_dram_cmd_c != 3'b0))
9643 `PR_ERROR ("mcu_fmon", `ERROR, "MCU1: Issued CMD other than NOP during Power Down STATE");
9644 end
9645 end
9646 else
9647 ref_state6_cycle_1 = 0;
9648
9649 if (mcu2_drif_mcu_state_next == 5'h5)
9650 begin
9651 if (ref_state5_cycle_2 < 4) // wait for 4 cycles as auto ref is issued
9652 ref_state5_cycle_2 = ref_state5_cycle_2 + 1;
9653 else
9654 begin
9655 if ((mcu2_drif_dram_cmd_a != 3'b0) || (mcu2_drif_dram_cmd_b != 3'b0 && mcu2_drif_dram_cmd_b != 3'h5) || (mcu2_drif_dram_cmd_c != 3'b0))
9656 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Issued CMD other than NOP during Self Refresh STATE");
9657 end
9658 end
9659 else
9660 ref_state5_cycle_2 = 0;
9661
9662 if (mcu2_drif_mcu_state_next == 5'h6)
9663 begin
9664 if (ref_state6_cycle_2 < 4) // wait for 4 cycles as auto ref is issued
9665 ref_state6_cycle_2 = ref_state6_cycle_2 + 1;
9666 else
9667 begin
9668 if ((mcu2_drif_dram_cmd_a != 3'b0) || (mcu2_drif_dram_cmd_b != 3'b0 && mcu2_drif_dram_cmd_b != 3'h5) || (mcu2_drif_dram_cmd_c != 3'b0))
9669 `PR_ERROR ("mcu_fmon", `ERROR, "MCU2: Issued CMD other than NOP during Power Down STATE");
9670 end
9671 end
9672 else
9673 ref_state6_cycle_2 = 0;
9674
9675 if (mcu3_drif_mcu_state_next == 5'h5)
9676 begin
9677 if (ref_state5_cycle_3 < 4) // wait for 4 cycles as auto ref is issued
9678 ref_state5_cycle_3 = ref_state5_cycle_3 + 1;
9679 else
9680 begin
9681 if ((mcu3_drif_dram_cmd_a != 3'b0) || (mcu3_drif_dram_cmd_b != 3'b0 && mcu3_drif_dram_cmd_b != 3'h5) || (mcu3_drif_dram_cmd_c != 3'b0))
9682 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Issued CMD other than NOP during Self Refresh STATE");
9683 end
9684 end
9685 else
9686 ref_state5_cycle_3 = 0;
9687
9688 if (mcu3_drif_mcu_state_next == 5'h6)
9689 begin
9690 if (ref_state6_cycle_3 < 4) // wait for 4 cycles as auto ref is issued
9691 ref_state6_cycle_3 = ref_state6_cycle_3 + 1;
9692 else
9693 begin
9694 if ((mcu3_drif_dram_cmd_a != 3'b0) || (mcu3_drif_dram_cmd_b != 3'b0 && mcu3_drif_dram_cmd_b != 3'h5) || (mcu3_drif_dram_cmd_c != 3'b0))
9695 `PR_ERROR ("mcu_fmon", `ERROR, "MCU3: Issued CMD other than NOP during Power Down STATE");
9696 end
9697 end
9698 else
9699 ref_state6_cycle_3 = 0;
9700
9701end
9702
9703//-------------------------------------------------
9704// FBD Channel Error Injection Scheme
9705//-------------------------------------------------
9706
9707integer status1,status2,status3,status4,status5,status6,status7,status8,status9,status10,status11,status12,status13,status14,status15,status16,status17,status18,status19,status20;
9708
9709initial
9710begin
9711 mcu0_sb_bit_time_mask = 12'h1;
9712 mcu1_sb_bit_time_mask = 12'h1;
9713 mcu2_sb_bit_time_mask = 12'h1;
9714 mcu3_sb_bit_time_mask = 12'h1;
9715
9716 mcu0_nb_bit_time_mask = 12'h1;
9717 mcu1_nb_bit_time_mask = 12'h1;
9718 mcu2_nb_bit_time_mask = 12'h1;
9719 mcu3_nb_bit_time_mask = 12'h1;
9720
9721 mcu0_sb_lane_mask = 10'h1;
9722 mcu1_sb_lane_mask = 10'h1;
9723 mcu2_sb_lane_mask = 10'h1;
9724 mcu3_sb_lane_mask = 10'h1;
9725
9726 mcu0_nb_lane_mask = 14'h1;
9727 mcu1_nb_lane_mask = 14'h1;
9728 mcu2_nb_lane_mask = 14'h1;
9729 mcu3_nb_lane_mask = 14'h1;
9730
9731 mcu0_l2t_mecc_err_r3_detected = 1'b0;
9732 mcu0_l2t0_scb_mecc_err_detected = 1'b0;
9733 mcu1_l2t_mecc_err_r3_detected = 1'b0;
9734 mcu1_l2t0_scb_mecc_err_detected = 1'b0;
9735 mcu2_l2t_mecc_err_r3_detected = 1'b0;
9736 mcu2_l2t0_scb_mecc_err_detected = 1'b0;
9737 mcu3_l2t_mecc_err_r3_detected = 1'b0;
9738 mcu3_l2t0_scb_mecc_err_detected = 1'b0;
9739
9740`ifdef FC_CRC_INJECT
9741 mcu0_nb_channel_error_cnt=8'h0;
9742 mcu1_nb_channel_error_cnt=8'h0;
9743 mcu2_nb_channel_error_cnt=8'h0;
9744 mcu3_nb_channel_error_cnt=8'h0;
9745
9746 mcu0_sb_channel_error_cnt=8'h0;
9747 mcu1_sb_channel_error_cnt=8'h0;
9748 mcu2_sb_channel_error_cnt=8'h0;
9749 mcu3_sb_channel_error_cnt=8'h0;
9750`else
9751 mcu0_nb_channel_error_cnt=8'h1;
9752 mcu1_nb_channel_error_cnt=8'h1;
9753 mcu2_nb_channel_error_cnt=8'h1;
9754 mcu3_nb_channel_error_cnt=8'h1;
9755
9756 mcu0_sb_channel_error_cnt=8'h1;
9757 mcu1_sb_channel_error_cnt=8'h1;
9758 mcu2_sb_channel_error_cnt=8'h1;
9759 mcu3_sb_channel_error_cnt=8'h1;
9760`endif
9761
9762 MCU0_NB_RANDOM_WEIGHT = 10; // Default Random Weigthage 10%
9763 MCU1_NB_RANDOM_WEIGHT = 10; // Default Random Weigthage 10%
9764 MCU2_NB_RANDOM_WEIGHT = 10; // Default Random Weigthage 10%
9765 MCU3_NB_RANDOM_WEIGHT = 10; // Default Random Weigthage 10%
9766
9767 MCU0_SB_RANDOM_WEIGHT = 10; // Default Random Weightage 10%
9768 MCU1_SB_RANDOM_WEIGHT = 10; // Default Random Weightage 10%
9769 MCU2_SB_RANDOM_WEIGHT = 10; // Default Random Weightage 10%
9770 MCU3_SB_RANDOM_WEIGHT = 10; // Default Random Weightage 10%
9771
9772 #5;
9773
9774`ifndef AXIS
9775 status1 = $value$plusargs("mcu0_nb_channel_error_cnt=%h",mcu0_nb_channel_error_cnt);
9776 status2 = $value$plusargs("mcu1_nb_channel_error_cnt=%h",mcu1_nb_channel_error_cnt);
9777 status3 = $value$plusargs("mcu2_nb_channel_error_cnt=%h",mcu2_nb_channel_error_cnt);
9778 status4 = $value$plusargs("mcu3_nb_channel_error_cnt=%h",mcu3_nb_channel_error_cnt);
9779
9780 status5 = $value$plusargs("mcu0_sb_channel_error_cnt=%h",mcu0_sb_channel_error_cnt);
9781 status6 = $value$plusargs("mcu1_sb_channel_error_cnt=%h",mcu1_sb_channel_error_cnt);
9782 status7 = $value$plusargs("mcu2_sb_channel_error_cnt=%h",mcu2_sb_channel_error_cnt);
9783 status8 = $value$plusargs("mcu3_sb_channel_error_cnt=%h",mcu3_sb_channel_error_cnt);
9784
9785 status9 = $value$plusargs("mcu0_nb_random_weight=%d",MCU0_NB_RANDOM_WEIGHT);
9786 status10 = $value$plusargs("mcu1_nb_random_weight=%d",MCU1_NB_RANDOM_WEIGHT);
9787 status11 = $value$plusargs("mcu2_nb_random_weight=%d",MCU2_NB_RANDOM_WEIGHT);
9788 status12 = $value$plusargs("mcu3_nb_random_weight=%d",MCU3_NB_RANDOM_WEIGHT);
9789
9790 status13 = $value$plusargs("mcu0_sb_random_weight=%d",MCU0_SB_RANDOM_WEIGHT);
9791 status14 = $value$plusargs("mcu1_sb_random_weight=%d",MCU1_SB_RANDOM_WEIGHT);
9792 status15 = $value$plusargs("mcu2_sb_random_weight=%d",MCU2_SB_RANDOM_WEIGHT);
9793 status16 = $value$plusargs("mcu3_sb_random_weight=%d",MCU3_SB_RANDOM_WEIGHT);
9794`endif
9795
9796 mcu0_sb_random_val = MCU0_SB_RANDOM_WEIGHT;
9797 mcu1_sb_random_val = MCU1_SB_RANDOM_WEIGHT;
9798 mcu2_sb_random_val = MCU2_SB_RANDOM_WEIGHT;
9799 mcu3_sb_random_val = MCU3_SB_RANDOM_WEIGHT;
9800
9801 mcu0_nb_random_val = MCU0_NB_RANDOM_WEIGHT;
9802 mcu1_nb_random_val = MCU1_NB_RANDOM_WEIGHT;
9803 mcu2_nb_random_val = MCU2_NB_RANDOM_WEIGHT;
9804 mcu3_nb_random_val = MCU3_NB_RANDOM_WEIGHT;
9805
9806 if ($test$plusargs("MCU0_NB_ERR_ENABLE"))
9807 mcu0_nb_err_enable = 1;
9808 else
9809 mcu0_nb_err_enable = 0;
9810
9811 if ($test$plusargs("MCU1_NB_ERR_ENABLE"))
9812 mcu1_nb_err_enable = 1;
9813 else
9814 mcu1_nb_err_enable = 0;
9815
9816 if ($test$plusargs("MCU2_NB_ERR_ENABLE"))
9817 mcu2_nb_err_enable = 1;
9818 else
9819 mcu2_nb_err_enable = 0;
9820
9821 if ($test$plusargs("MCU3_NB_ERR_ENABLE"))
9822 mcu3_nb_err_enable = 1;
9823 else
9824 mcu3_nb_err_enable = 0;
9825
9826 if ($test$plusargs("MCU0_SB_ERR_ENABLE"))
9827 mcu0_sb_err_enable = 1;
9828 else
9829 mcu0_sb_err_enable = 0;
9830
9831 if ($test$plusargs("MCU1_SB_ERR_ENABLE"))
9832 mcu1_sb_err_enable = 1;
9833 else
9834 mcu1_sb_err_enable = 0;
9835
9836 if ($test$plusargs("MCU2_SB_ERR_ENABLE"))
9837 mcu2_sb_err_enable = 1;
9838 else
9839 mcu2_sb_err_enable = 0;
9840
9841 if ($test$plusargs("MCU3_SB_ERR_ENABLE"))
9842 mcu3_sb_err_enable = 1;
9843 else
9844 mcu3_sb_err_enable = 0;
9845
9846 if ($test$plusargs("MCU0_NB_ERR_RANDOM")) begin
9847 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU0: *** NB RANDOM ERR WEIGHT = %d ***", MCU0_NB_RANDOM_WEIGHT);
9848 mcu0_nb_err_random = 1;
9849 end
9850 else
9851 mcu0_nb_err_random = 0;
9852
9853 if ($test$plusargs("MCU1_NB_ERR_RANDOM")) begin
9854 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU1: *** NB RANDOM ERR WEIGHT = %d ***", MCU1_NB_RANDOM_WEIGHT);
9855 mcu1_nb_err_random = 1;
9856 end
9857 else
9858 mcu1_nb_err_random = 0;
9859
9860 if ($test$plusargs("MCU2_NB_ERR_RANDOM")) begin
9861 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU2: *** NB RANDOM ERR WEIGHT = %d ***", MCU2_NB_RANDOM_WEIGHT);
9862 mcu2_nb_err_random = 1;
9863 end
9864 else
9865 mcu2_nb_err_random = 0;
9866
9867 if ($test$plusargs("MCU3_NB_ERR_RANDOM")) begin
9868 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU3: *** NB RANDOM ERR WEIGHT = %d ***", MCU3_NB_RANDOM_WEIGHT);
9869 mcu3_nb_err_random = 1;
9870 end
9871 else
9872 mcu3_nb_err_random = 0;
9873
9874 if ($test$plusargs("MCU0_SB_ERR_RANDOM")) begin
9875 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU0: *** SB RANDOM ERR WEIGHT = %d ***", MCU0_SB_RANDOM_WEIGHT);
9876 mcu0_sb_err_random = 1;
9877 end
9878 else
9879 mcu0_sb_err_random = 0;
9880
9881 if ($test$plusargs("MCU1_SB_ERR_RANDOM")) begin
9882 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU1: *** SB RANDOM ERR WEIGHT = %d ***", MCU1_SB_RANDOM_WEIGHT);
9883 mcu1_sb_err_random = 1;
9884 end
9885 else
9886 mcu1_sb_err_random = 0;
9887
9888 if ($test$plusargs("MCU2_SB_ERR_RANDOM")) begin
9889 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU2: *** SB RANDOM ERR WEIGHT = %d ***", MCU2_SB_RANDOM_WEIGHT);
9890 mcu2_sb_err_random = 1;
9891 end
9892 else
9893 mcu2_sb_err_random = 0;
9894
9895 if ($test$plusargs("MCU3_SB_ERR_RANDOM")) begin
9896 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU3: *** SB RANDOM ERR WEIGHT = %d ***", MCU3_SB_RANDOM_WEIGHT);
9897 mcu3_sb_err_random = 1;
9898 end
9899 else
9900 mcu3_sb_err_random = 0;
9901
9902 if ($test$plusargs("MCU0_INJECT_FBU_ERR"))
9903 mcu0_inject_fbu_err = 1;
9904 else
9905 mcu0_inject_fbu_err = 0;
9906
9907 if ($test$plusargs("MCU1_INJECT_FBU_ERR"))
9908 mcu1_inject_fbu_err = 1;
9909 else
9910 mcu1_inject_fbu_err = 0;
9911
9912 if ($test$plusargs("MCU2_INJECT_FBU_ERR"))
9913 mcu2_inject_fbu_err = 1;
9914 else
9915 mcu2_inject_fbu_err = 0;
9916
9917 if ($test$plusargs("MCU3_INJECT_FBU_ERR"))
9918 mcu3_inject_fbu_err = 1;
9919 else
9920 mcu3_inject_fbu_err = 0;
9921
9922 if($test$plusargs("ALL_MCU_TRAINING_SEQ_ERR"))
9923 begin
9924 mcu0_training_err_enable = 1;
9925 mcu1_training_err_enable = 1;
9926 mcu2_training_err_enable = 1;
9927 mcu3_training_err_enable = 1;
9928 end
9929 else
9930 begin
9931 mcu0_training_err_enable = 0;
9932 mcu1_training_err_enable = 0;
9933 mcu2_training_err_enable = 0;
9934 mcu3_training_err_enable = 0;
9935 end
9936
9937 if($test$plusargs("MCU0_TRAINING_SEQ_ERR"))
9938 mcu0_training_err_enable = 1;
9939 else
9940 mcu0_training_err_enable = 0;
9941
9942 if($test$plusargs("MCU1_TRAINING_SEQ_ERR"))
9943 mcu1_training_err_enable = 1;
9944 else
9945 mcu1_training_err_enable = 0;
9946
9947 if($test$plusargs("MCU2_TRAINING_SEQ_ERR"))
9948 mcu2_training_err_enable = 1;
9949 else
9950 mcu2_training_err_enable = 0;
9951
9952 if($test$plusargs("MCU3_TRAINING_SEQ_ERR"))
9953 mcu3_training_err_enable = 1;
9954 else
9955 mcu3_training_err_enable = 0;
9956
9957 if ($test$plusargs("MCU0_DISABLE_CH0_FBD_ERRINJ"))
9958 mcu0_enable_ch0_err_inj = 0;
9959 else
9960 mcu0_enable_ch0_err_inj = 1;
9961
9962 if ($test$plusargs("MCU1_DISABLE_CH0_FBD_ERRINJ"))
9963 mcu1_enable_ch0_err_inj = 0;
9964 else
9965 mcu1_enable_ch0_err_inj = 1;
9966
9967 if ($test$plusargs("MCU2_DISABLE_CH0_FBD_ERRINJ"))
9968 mcu2_enable_ch0_err_inj = 0;
9969 else
9970 mcu2_enable_ch0_err_inj = 1;
9971
9972 if ($test$plusargs("MCU3_DISABLE_CH0_FBD_ERRINJ"))
9973 mcu3_enable_ch0_err_inj = 0;
9974 else
9975 mcu3_enable_ch0_err_inj = 1;
9976
9977 if ($test$plusargs("MCU0_DISABLE_CH1_FBD_ERRINJ"))
9978 mcu0_enable_ch1_err_inj = 0;
9979 else
9980 mcu0_enable_ch1_err_inj = 1;
9981
9982 if ($test$plusargs("MCU1_DISABLE_CH1_FBD_ERRINJ"))
9983 mcu1_enable_ch1_err_inj = 0;
9984 else
9985 mcu1_enable_ch1_err_inj = 1;
9986
9987 if ($test$plusargs("MCU2_DISABLE_CH1_FBD_ERRINJ"))
9988 mcu2_enable_ch1_err_inj = 0;
9989 else
9990 mcu2_enable_ch1_err_inj = 1;
9991
9992 if ($test$plusargs("MCU3_DISABLE_CH1_FBD_ERRINJ"))
9993 mcu3_enable_ch1_err_inj = 0;
9994 else
9995 mcu3_enable_ch1_err_inj = 1;
9996
9997 if ($test$plusargs("MCU0_SB_CRC_MULTIPLE_LANES"))
9998 mcu0_sb_crc_multiple_lanes = 1;
9999 else
10000 mcu0_sb_crc_multiple_lanes = 0;
10001
10002 if ($test$plusargs("MCU1_SB_CRC_MULTIPLE_LANES"))
10003 mcu1_sb_crc_multiple_lanes = 1;
10004 else
10005 mcu1_sb_crc_multiple_lanes = 0;
10006
10007 if ($test$plusargs("MCU2_SB_CRC_MULTIPLE_LANES"))
10008 mcu2_sb_crc_multiple_lanes = 1;
10009 else
10010 mcu2_sb_crc_multiple_lanes = 0;
10011
10012 if ($test$plusargs("MCU3_SB_CRC_MULTIPLE_LANES"))
10013 mcu3_sb_crc_multiple_lanes = 1;
10014 else
10015 mcu3_sb_crc_multiple_lanes = 0;
10016
10017 if ($test$plusargs("MCU0_SB_CRC_MULTIPLE_BIT_TIMES"))
10018 mcu0_sb_crc_multiple_bit_times = 1;
10019 else
10020 mcu0_sb_crc_multiple_bit_times = 0;
10021
10022 if ($test$plusargs("MCU1_SB_CRC_MULTIPLE_BIT_TIMES"))
10023 mcu1_sb_crc_multiple_bit_times = 1;
10024 else
10025 mcu1_sb_crc_multiple_bit_times = 0;
10026
10027 if ($test$plusargs("MCU2_SB_CRC_MULTIPLE_BIT_TIMES"))
10028 mcu2_sb_crc_multiple_bit_times = 1;
10029 else
10030 mcu2_sb_crc_multiple_bit_times = 0;
10031
10032 if ($test$plusargs("MCU3_SB_CRC_MULTIPLE_BIT_TIMES"))
10033 mcu3_sb_crc_multiple_bit_times = 1;
10034 else
10035 mcu3_sb_crc_multiple_bit_times = 0;
10036
10037 if ($test$plusargs("MCU0_NB_CRC_MULTIPLE_LANES"))
10038 mcu0_nb_crc_multiple_lanes = 1;
10039 else
10040 mcu0_nb_crc_multiple_lanes = 0;
10041
10042 if ($test$plusargs("MCU1_NB_CRC_MULTIPLE_LANES"))
10043 mcu1_nb_crc_multiple_lanes = 1;
10044 else
10045 mcu1_nb_crc_multiple_lanes = 0;
10046
10047 if ($test$plusargs("MCU2_NB_CRC_MULTIPLE_LANES"))
10048 mcu2_nb_crc_multiple_lanes = 1;
10049 else
10050 mcu2_nb_crc_multiple_lanes = 0;
10051
10052 if ($test$plusargs("MCU3_NB_CRC_MULTIPLE_LANES"))
10053 mcu3_nb_crc_multiple_lanes = 1;
10054 else
10055 mcu3_nb_crc_multiple_lanes = 0;
10056
10057 if ($test$plusargs("MCU0_NB_CRC_MULTIPLE_BIT_TIMES"))
10058 mcu0_nb_crc_multiple_bit_times = 1;
10059 else
10060 mcu0_nb_crc_multiple_bit_times = 0;
10061
10062 if ($test$plusargs("MCU1_NB_CRC_MULTIPLE_BIT_TIMES"))
10063 mcu1_nb_crc_multiple_bit_times = 1;
10064 else
10065 mcu1_nb_crc_multiple_bit_times = 0;
10066
10067 if ($test$plusargs("MCU2_NB_CRC_MULTIPLE_BIT_TIMES"))
10068 mcu2_nb_crc_multiple_bit_times = 1;
10069 else
10070 mcu2_nb_crc_multiple_bit_times = 0;
10071
10072 if ($test$plusargs("MCU3_NB_CRC_MULTIPLE_BIT_TIMES"))
10073 mcu3_nb_crc_multiple_bit_times = 1;
10074 else
10075 mcu3_nb_crc_multiple_bit_times = 0;
10076
10077 if ($test$plusargs("MCU_BUG_111483"))
10078 mcu_bug_111483 = 1;
10079 else
10080 mcu_bug_111483 = 0;
10081
10082 if ($test$plusargs("MCU_BUG_111547"))
10083 mcu_bug_111547 = 1;
10084 else
10085 mcu_bug_111547 = 0;
10086
10087 if ($test$plusargs("MCU_BUG_111811"))
10088 mcu_bug_111811 = 1;
10089 else
10090 mcu_bug_111811 = 0;
10091
10092 if ($test$plusargs("RAS_CORNER_CASE"))
10093 ras_corner_case = 1;
10094 else
10095 ras_corner_case = 0;
10096
10097 mcu0_nb_cycle_cnt = 0;
10098 mcu1_nb_cycle_cnt = 0;
10099 mcu2_nb_cycle_cnt = 0;
10100 mcu3_nb_cycle_cnt = 0;
10101
10102`ifndef AXIS
10103 status17 = $value$plusargs("mcu0_nb_cycle_cnt=%d",mcu0_nb_cycle_cnt);
10104 status18 = $value$plusargs("mcu1_nb_cycle_cnt=%d",mcu1_nb_cycle_cnt);
10105 status19 = $value$plusargs("mcu2_nb_cycle_cnt=%d",mcu2_nb_cycle_cnt);
10106 status20 = $value$plusargs("mcu3_nb_cycle_cnt=%d",mcu3_nb_cycle_cnt);
10107`endif
10108
10109end
10110
10111`ifdef MCUSAT_AND_FC
10112`ifdef FC_CRC_INJECT
10113 reg passed_bootEnd_mask=0;
10114 always @( `TOP.gOutOfBoot[63:0] ) begin
10115 if (!passed_bootEnd_mask && (`TOP.gOutOfBoot[63:0] === `TOP.verif_args.finish_mask[63:0]) ) begin
10116 repeat (1000) @ (posedge drl2clk); // wait until 1000 cycles after bootEnd, then start injecting
10117 passed_bootEnd_mask=1;
10118 end
10119 end
10120`endif
10121
10122// added the following to stop, re-start and re-stop CRC error injections
10123//NB
10124time stop_mcu0_nb_crc_inj_time=0, stop_mcu1_nb_crc_inj_time=0, stop_mcu2_nb_crc_inj_time=0, stop_mcu3_nb_crc_inj_time=0;
10125time restart_mcu0_nb_crc_inj_time=0, restart_mcu1_nb_crc_inj_time=0, restart_mcu2_nb_crc_inj_time=0, restart_mcu3_nb_crc_inj_time=0;
10126time restart_stop_mcu0_nb_crc_inj_time=0, restart_stop_mcu1_nb_crc_inj_time=0, restart_stop_mcu2_nb_crc_inj_time=0, restart_stop_mcu3_nb_crc_inj_time=0;
10127reg stop_mcu0_nb_mask=0, stop_mcu1_nb_mask=0, stop_mcu2_nb_mask=0, stop_mcu3_nb_mask=0;
10128reg restart_mcu0_nb_mask=0, restart_mcu1_nb_mask=0, restart_mcu2_nb_mask=0, restart_mcu3_nb_mask=0;
10129reg restart_stop_mcu0_nb_mask=0, restart_stop_mcu1_nb_mask=0, restart_stop_mcu2_nb_mask=0, restart_stop_mcu3_nb_mask=0;
10130
10131//mcu0
10132initial
10133begin
10134if($value$plusargs("STOP_MCU0_NB_CRC_INJ_TIME=%d",stop_mcu0_nb_crc_inj_time))
10135 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU0_NB_CRC_INJ_TIME\" has been set to %d",stop_mcu0_nb_crc_inj_time);
10136end
10137initial
10138begin
10139if($value$plusargs("RESTART_MCU0_NB_CRC_INJ_TIME=%d",restart_mcu0_nb_crc_inj_time))
10140 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU0_NB_CRC_INJ_TIME\" has been set to %d",restart_mcu0_nb_crc_inj_time);
10141end
10142initial
10143begin
10144if($value$plusargs("RESTART_STOP_MCU0_NB_CRC_INJ_TIME=%d",restart_stop_mcu0_nb_crc_inj_time))
10145 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU0_NB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu0_nb_crc_inj_time);
10146end
10147
10148//mcu1
10149initial
10150begin
10151if($value$plusargs("STOP_MCU1_NB_CRC_INJ_TIME=%d",stop_mcu1_nb_crc_inj_time))
10152 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU1_NB_CRC_INJ_TIME\" has been set to %d",stop_mcu1_nb_crc_inj_time);
10153end
10154initial
10155begin
10156if($value$plusargs("RESTART_MCU1_NB_CRC_INJ_TIME=%d",restart_mcu1_nb_crc_inj_time))
10157 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU1_NB_CRC_INJ_TIME\" has been set to %d",restart_mcu1_nb_crc_inj_time);
10158end
10159initial
10160begin
10161if($value$plusargs("RESTART_STOP_MCU1_NB_CRC_INJ_TIME=%d",restart_stop_mcu1_nb_crc_inj_time))
10162 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU1_NB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu1_nb_crc_inj_time);
10163end
10164
10165//mcu2
10166initial
10167begin
10168if($value$plusargs("STOP_MCU2_NB_CRC_INJ_TIME=%d",stop_mcu2_nb_crc_inj_time))
10169 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU2_NB_CRC_INJ_TIME\" has been set to %d",stop_mcu2_nb_crc_inj_time);
10170end
10171initial
10172begin
10173if($value$plusargs("RESTART_MCU2_NB_CRC_INJ_TIME=%d",restart_mcu2_nb_crc_inj_time))
10174 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU2_NB_CRC_INJ_TIME\" has been set to %d",restart_mcu2_nb_crc_inj_time);
10175end
10176initial
10177begin
10178if($value$plusargs("RESTART_STOP_MCU2_NB_CRC_INJ_TIME=%d",restart_stop_mcu2_nb_crc_inj_time))
10179 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU2_NB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu2_nb_crc_inj_time);
10180end
10181
10182//mcu3
10183initial
10184begin
10185if($value$plusargs("STOP_MCU3_NB_CRC_INJ_TIME=%d",stop_mcu3_nb_crc_inj_time))
10186 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU3_NB_CRC_INJ_TIME\" has been set to %d",stop_mcu3_nb_crc_inj_time);
10187end
10188initial
10189begin
10190if($value$plusargs("RESTART_MCU3_NB_CRC_INJ_TIME=%d",restart_mcu3_nb_crc_inj_time))
10191 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU3_NB_CRC_INJ_TIME\" has been set to %d",restart_mcu3_nb_crc_inj_time);
10192end
10193initial
10194begin
10195if($value$plusargs("RESTART_STOP_MCU3_NB_CRC_INJ_TIME=%d",restart_stop_mcu3_nb_crc_inj_time))
10196 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU3_NB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu3_nb_crc_inj_time);
10197end
10198
10199//SB
10200time stop_mcu0_sb_crc_inj_time=0, stop_mcu1_sb_crc_inj_time=0, stop_mcu2_sb_crc_inj_time=0, stop_mcu3_sb_crc_inj_time=0;
10201time restart_mcu0_sb_crc_inj_time=0, restart_mcu1_sb_crc_inj_time=0, restart_mcu2_sb_crc_inj_time=0, restart_mcu3_sb_crc_inj_time=0;
10202time restart_stop_mcu0_sb_crc_inj_time=0, restart_stop_mcu1_sb_crc_inj_time=0, restart_stop_mcu2_sb_crc_inj_time=0, restart_stop_mcu3_sb_crc_inj_time=0;
10203reg stop_mcu0_sb_mask=0, stop_mcu1_sb_mask=0, stop_mcu2_sb_mask=0, stop_mcu3_sb_mask=0;
10204reg restart_mcu0_sb_mask=0, restart_mcu1_sb_mask=0, restart_mcu2_sb_mask=0, restart_mcu3_sb_mask=0;
10205reg restart_stop_mcu0_sb_mask=0, restart_stop_mcu1_sb_mask=0, restart_stop_mcu2_sb_mask=0, restart_stop_mcu3_sb_mask=0;
10206
10207//mcu0
10208initial
10209begin
10210if($value$plusargs("STOP_MCU0_SB_CRC_INJ_TIME=%d",stop_mcu0_sb_crc_inj_time))
10211 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU0_SB_CRC_INJ_TIME\" has been set to %d",stop_mcu0_sb_crc_inj_time);
10212end
10213initial
10214begin
10215if($value$plusargs("RESTART_MCU0_SB_CRC_INJ_TIME=%d",restart_mcu0_sb_crc_inj_time))
10216 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU0_SB_CRC_INJ_TIME\" has been set to %d",restart_mcu0_sb_crc_inj_time);
10217end
10218initial
10219begin
10220if($value$plusargs("RESTART_STOP_MCU0_SB_CRC_INJ_TIME=%d",restart_stop_mcu0_sb_crc_inj_time))
10221 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU0_SB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu0_sb_crc_inj_time);
10222end
10223
10224//mcu1
10225initial
10226begin
10227if($value$plusargs("STOP_MCU1_SB_CRC_INJ_TIME=%d",stop_mcu1_sb_crc_inj_time))
10228 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU1_SB_CRC_INJ_TIME\" has been set to %d",stop_mcu1_sb_crc_inj_time);
10229end
10230initial
10231begin
10232if($value$plusargs("RESTART_MCU1_SB_CRC_INJ_TIME=%d",restart_mcu1_sb_crc_inj_time))
10233 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU1_SB_CRC_INJ_TIME\" has been set to %d",restart_mcu1_sb_crc_inj_time);
10234end
10235initial
10236begin
10237if($value$plusargs("RESTART_STOP_MCU1_SB_CRC_INJ_TIME=%d",restart_stop_mcu1_sb_crc_inj_time))
10238 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU1_SB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu1_sb_crc_inj_time);
10239end
10240
10241//mcu2
10242initial
10243begin
10244if($value$plusargs("STOP_MCU2_SB_CRC_INJ_TIME=%d",stop_mcu2_sb_crc_inj_time))
10245 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU2_SB_CRC_INJ_TIME\" has been set to %d",stop_mcu2_sb_crc_inj_time);
10246end
10247initial
10248begin
10249if($value$plusargs("RESTART_MCU2_SB_CRC_INJ_TIME=%d",restart_mcu2_sb_crc_inj_time))
10250 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU2_SB_CRC_INJ_TIME\" has been set to %d",restart_mcu2_sb_crc_inj_time);
10251end
10252initial
10253begin
10254if($value$plusargs("RESTART_STOP_MCU2_SB_CRC_INJ_TIME=%d",restart_stop_mcu2_sb_crc_inj_time))
10255 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU2_SB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu2_sb_crc_inj_time);
10256end
10257
10258//mcu3
10259initial
10260begin
10261if($value$plusargs("STOP_MCU3_SB_CRC_INJ_TIME=%d",stop_mcu3_sb_crc_inj_time))
10262 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"STOP_MCU3_SB_CRC_INJ_TIME\" has been set to %d",stop_mcu3_sb_crc_inj_time);
10263end
10264initial
10265begin
10266if($value$plusargs("RESTART_MCU3_SB_CRC_INJ_TIME=%d",restart_mcu3_sb_crc_inj_time))
10267 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_MCU3_SB_CRC_INJ_TIME\" has been set to %d",restart_mcu3_sb_crc_inj_time);
10268end
10269initial
10270begin
10271if($value$plusargs("RESTART_STOP_MCU3_SB_CRC_INJ_TIME=%d",restart_stop_mcu3_sb_crc_inj_time))
10272 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Parameter \"RESTART_STOP_MCU3_SB_CRC_INJ_TIME\" has been set to %d",restart_stop_mcu3_sb_crc_inj_time);
10273end
10274
10275
10276integer mcu0_nb_err=0, mcu1_nb_err=0, mcu2_nb_err=0, mcu3_nb_err=0;
10277integer mcu0_sb_err=0, mcu1_sb_err=0, mcu2_sb_err=0, mcu3_sb_err=0;
10278reg inject_crc_mcu0_nb_mask=0, inject_crc_mcu1_nb_mask=0, inject_crc_mcu2_nb_mask=0, inject_crc_mcu3_nb_mask=0;
10279reg inject_crc_mcu0_sb_mask=0, inject_crc_mcu1_sb_mask=0, inject_crc_mcu2_sb_mask=0, inject_crc_mcu3_sb_mask=0;
10280
10281
10282reg inject_crc_mcu0_nb_errq_mask=0, inject_crc_mcu1_nb_errq_mask=0, inject_crc_mcu2_nb_errq_mask=0, inject_crc_mcu3_nb_errq_mask=0;
10283reg inject_crc_mcu0_sb_errq_mask=0, inject_crc_mcu1_sb_errq_mask=0, inject_crc_mcu2_sb_errq_mask=0, inject_crc_mcu3_sb_errq_mask=0;
10284
10285/*
10286always @( posedge `MCU0.drif.reqq.drq0.drq_rdq_full or posedge `MCU0.drif.reqq.drq0.drq_wrq_full or
10287 posedge `MCU0.drif.reqq.drq1.drq_rdq_full or posedge `MCU0.drif.reqq.drq1.drq_wrq_full
10288 ) begin
10289 if ( `MCU0.drif.reqq.drq0.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU0 drq0 RD queue is full !!");
10290 if ( `MCU0.drif.reqq.drq1.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU0 drq1 RD queue is full !!");
10291 if ( `MCU0.drif.reqq.drq0.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU0 drq0 WR queue is full !!");
10292 if ( `MCU0.drif.reqq.drq1.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU0 drq1 WR queue is full !!");
10293 if ($test$plusargs("INJECT_CRC_MCU0_NB_ERRQ")) begin
10294 inject_crc_mcu0_nb_errq_mask=0;
10295 end
10296 if ($test$plusargs("INJECT_CRC_MCU0_SB_ERRQ")) begin
10297 inject_crc_mcu0_sb_errq_mask=0;
10298 end
10299 end
10300
10301
10302always @( posedge `MCU1.drif.reqq.drq0.drq_rdq_full or posedge `MCU1.drif.reqq.drq0.drq_wrq_full or
10303 posedge `MCU1.drif.reqq.drq1.drq_rdq_full or posedge `MCU1.drif.reqq.drq1.drq_wrq_full
10304 ) begin
10305 if ( `MCU1.drif.reqq.drq0.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU1 drq0 RD queue is full !!");
10306 if ( `MCU1.drif.reqq.drq1.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU1 drq1 RD queue is full !!");
10307 if ( `MCU1.drif.reqq.drq0.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU1 drq0 WR queue is full !!");
10308 if ( `MCU1.drif.reqq.drq1.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU1 drq1 WR queue is full !!");
10309 if ($test$plusargs("INJECT_CRC_MCU1_NB_ERRQ")) begin
10310 inject_crc_mcu1_nb_errq_mask=0;
10311 end
10312 if ($test$plusargs("INJECT_CRC_MCU1_SB_ERRQ")) begin
10313 inject_crc_mcu1_sb_errq_mask=0;
10314 end
10315 end
10316
10317
10318always @( posedge `MCU2.drif.reqq.drq0.drq_rdq_full or posedge `MCU2.drif.reqq.drq0.drq_wrq_full or
10319 posedge `MCU2.drif.reqq.drq1.drq_rdq_full or posedge `MCU2.drif.reqq.drq1.drq_wrq_full
10320 ) begin
10321 if ( `MCU2.drif.reqq.drq0.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU2 drq0 RD queue is full !!");
10322 if ( `MCU2.drif.reqq.drq1.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU2 drq1 RD queue is full !!");
10323 if ( `MCU2.drif.reqq.drq0.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU2 drq0 WR queue is full !!");
10324 if ( `MCU2.drif.reqq.drq1.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU2 drq1 WR queue is full !!");
10325 if ($test$plusargs("INJECT_CRC_MCU2_NB_ERRQ")) begin
10326 inject_crc_mcu2_nb_errq_mask=0;
10327 end
10328 if ($test$plusargs("INJECT_CRC_MCU2_SB_ERRQ")) begin
10329 inject_crc_mcu2_sb_errq_mask=0;
10330 end
10331 end
10332
10333
10334always @( posedge `MCU3.drif.reqq.drq0.drq_rdq_full or posedge `MCU3.drif.reqq.drq0.drq_wrq_full or
10335 posedge `MCU3.drif.reqq.drq1.drq_rdq_full or posedge `MCU3.drif.reqq.drq1.drq_wrq_full
10336 ) begin
10337 if ( `MCU3.drif.reqq.drq0.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU3 drq0 RD queue is full !!");
10338 if ( `MCU3.drif.reqq.drq1.drq_rdq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU3 drq1 RD queue is full !!");
10339 if ( `MCU3.drif.reqq.drq0.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU3 drq0 WR queue is full !!");
10340 if ( `MCU3.drif.reqq.drq1.drq_wrq_full ) `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** MCU3 drq1 WR queue is full !!");
10341 if ($test$plusargs("INJECT_CRC_MCU3_NB_ERRQ")) begin
10342 inject_crc_mcu3_nb_errq_mask=0;
10343 end
10344 if ($test$plusargs("INJECT_CRC_MCU3_SB_ERRQ")) begin
10345 inject_crc_mcu3_sb_errq_mask=0;
10346 end
10347 end
10348*/
10349
10350
10351//---------------------------------------------------------------
10352// NB CRC - Corrupt Read Data or Read Config Data Frame Mechanism
10353//---------------------------------------------------------------
10354parameter BIT_TIMES =12;
10355parameter NB_LANES =14;
10356parameter SB_LANES =10;
10357
10358// --- MCU0 ---
10359
10360`ifdef FC_CRC_INJECT
10361reg [167:0] corrupted_mcu0_nb_lndskw0_data;
10362reg [167:0] corrupted_mcu0_nb_lndskw1_data;
10363integer mcu0_nb_quadword=1; //default is always the 1st quadword
10364initial begin
10365if ($value$plusargs("MCU0_NB_QUADWORD=%d",mcu0_nb_quadword)) begin
10366 if ( (mcu0_nb_quadword<1) || (mcu0_nb_quadword>4) ) `PR_ERROR ("mcu_fmon", `ERROR, "can only specify 1,2,3 or 4!");
10367 else `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: will inject CRC error on MCU0 NB quadword %d",mcu0_nb_quadword);
10368 end
10369end
10370`endif
10371
10372reg NBQW1=0; reg NBQW2=0; reg NBQW3=0; reg NBQW4=0;
10373reg SBQW1=0; reg SBQW2=0; reg SBQW3=0; reg SBQW4=0;
10374
10375function [167:0] return_168_bits_nb_mask;
10376input[11:0] mcu0_nb_bit_time_mask;
10377input[13:0] mcu0_nb_lane_mask;
10378begin
10379 return_168_bits_nb_mask=168'b0;
10380 if (mcu0_nb_bit_time_mask[0] ==1) return_168_bits_nb_mask[13:0] = mcu0_nb_lane_mask[13:0];
10381 if (mcu0_nb_bit_time_mask[1] ==1) return_168_bits_nb_mask[27:14] = mcu0_nb_lane_mask[13:0];
10382 if (mcu0_nb_bit_time_mask[2] ==1) return_168_bits_nb_mask[41:28] = mcu0_nb_lane_mask[13:0];
10383 if (mcu0_nb_bit_time_mask[3] ==1) return_168_bits_nb_mask[55:42] = mcu0_nb_lane_mask[13:0];
10384 if (mcu0_nb_bit_time_mask[4] ==1) return_168_bits_nb_mask[69:56] = mcu0_nb_lane_mask[13:0];
10385 if (mcu0_nb_bit_time_mask[5] ==1) return_168_bits_nb_mask[83:70] = mcu0_nb_lane_mask[13:0];
10386 if (mcu0_nb_bit_time_mask[6] ==1) return_168_bits_nb_mask[97:84] = mcu0_nb_lane_mask[13:0];
10387 if (mcu0_nb_bit_time_mask[7] ==1) return_168_bits_nb_mask[111:98] = mcu0_nb_lane_mask[13:0];
10388 if (mcu0_nb_bit_time_mask[8] ==1) return_168_bits_nb_mask[125:112] = mcu0_nb_lane_mask[13:0];
10389 if (mcu0_nb_bit_time_mask[9] ==1) return_168_bits_nb_mask[139:126] = mcu0_nb_lane_mask[13:0];
10390 if (mcu0_nb_bit_time_mask[10]==1) return_168_bits_nb_mask[153:140] = mcu0_nb_lane_mask[13:0];
10391 if (mcu0_nb_bit_time_mask[11]==1) return_168_bits_nb_mask[167:154] = mcu0_nb_lane_mask[13:0];
10392end
10393endfunction
10394
10395`define MAX_CRC_ERRORS 16
10396reg [167:0] mcu0_nb_data_array_QW1 [0:`MAX_CRC_ERRORS-1];
10397reg [167:0] mcu0_nb_data_array_QW2 [0:`MAX_CRC_ERRORS-1];
10398reg [167:0] mcu0_nb_data_array_QW3 [0:`MAX_CRC_ERRORS-1];
10399reg [167:0] mcu0_nb_data_array_QW4 [0:`MAX_CRC_ERRORS-1];
10400integer mcu0_nb_data_array_QW1_cnt [0:`MAX_CRC_ERRORS-1];
10401integer mcu0_nb_data_array_QW2_cnt [0:`MAX_CRC_ERRORS-1];
10402integer mcu0_nb_data_array_QW3_cnt [0:`MAX_CRC_ERRORS-1];
10403integer mcu0_nb_data_array_QW4_cnt [0:`MAX_CRC_ERRORS-1];
10404
10405integer i=0; integer j=-1;
10406reg found=0;
10407integer N=0;
10408reg trigger_NB=0;
10409
10410integer delay_crc;
10411initial
10412 if (!$value$plusargs("DELAY_CRC=%d",delay_crc)) delay_crc=6;
10413
10414always @ (
10415`ifdef FC_CRC_INJECT //for fullchip
10416 posedge `MCU0.fbdic.fbdic_rddata_vld // for fullchip, check for all reads
10417`else //for MCUSAT
10418 mcu0_drif_dram_cmd_a or
10419 `MCU0.fbdic.fbdic_config_reg_read or
10420 `MCU0.fbdic.fbdic_config_reg_write or
10421 `MCU0.fbdic.fbdic_sync_frame_req or
10422 `MCU0.fbdic.fbdic_scr_frame_req
10423`endif
10424)
10425begin
10426if (enabled && ~ras_corner_case)
10427begin
10428`ifdef FC_CRC_INJECT
10429if ( passed_bootEnd_mask==1 && !mcu0_esr_fbr && !mcu0_esr_fbu)
10430begin
10431N=N+1;
10432`endif
10433
10434 // --------- Random NB CRC Err Injection --------
10435 if (mcu0_nb_err_random) begin
10436
10437 if (mcu0_nb_crc_multiple_bit_times) begin
10438 mcu0_nb_bit_time_mask = ({$random} % 4095); // pick multiple bit times
10439 while (mcu0_nb_bit_time_mask==0) mcu0_nb_bit_time_mask = ({$random} % 4095);
10440 end
10441 else begin // pick any 1 random bit time
10442 mcu0_nb_bit_time_mask=1;
10443 mcu0_nb_random_bit_time = ({$random} % BIT_TIMES);
10444 while (mcu0_nb_random_bit_time==0) mcu0_nb_random_bit_time = ({$random} % BIT_TIMES);
10445 mcu0_nb_bit_time_mask = mcu0_nb_bit_time_mask << mcu0_nb_random_bit_time;
10446 end
10447
10448 if (mcu0_nb_crc_multiple_lanes) begin
10449 mcu0_nb_lane_mask = ({$random} % 16383); // pick multiple lanes
10450 while (mcu0_nb_lane_mask==0) mcu0_nb_lane_mask = ({$random} % 16383);
10451`ifdef FC_CRC_INJECT
10452 mcu0_nb_lane_mask = mcu0_nb_lane_mask & 14'h3000; // for FC, pick only 13 and 14th lanes as they carry CRC bits on NB
10453`endif
10454 end
10455 else begin // pick any 1 random lane
10456 mcu0_nb_lane_mask=1;
10457`ifdef MCUSAT
10458 mcu0_nb_random_lane = ({$random} % NB_LANES);
10459 while (mcu0_nb_random_lane==0) mcu0_nb_random_lane = ({$random} % NB_LANES);
10460 mcu0_nb_lane_mask = mcu0_nb_lane_mask << mcu0_nb_random_lane;
10461`else
10462 mcu0_nb_random_lane = ({$random} % 2); // for now inside FC, pick one of 13th/14th lane
10463 mcu0_nb_lane_mask = mcu0_nb_lane_mask << (mcu0_nb_random_lane+12);
10464`endif
10465 end
10466`ifdef MCUSAT
10467 mcu0_nb_random_cycle = ({$random} % 3);
10468 mcu0_nb_random_val = ({$random} % 100);
10469 if (!(mcu0_nb_random_val > MCU0_NB_RANDOM_WEIGHT)) mcu0_nb_err_enable=1;
10470`else
10471 mcu0_nb_err_enable=1;
10472`endif
10473 end //if (mcu0_nb_err_random)
10474
10475`ifdef FC_CRC_INJECT
10476 else if (mcu0_nb_err_enable) begin
10477 mcu0_nb_bit_time_mask=12'h1;
10478 mcu0_nb_lane_mask=14'h1000; // for FC, pick only the 13th lane
10479 end
10480`endif
10481
10482
10483//times to stop and restart
10484 if ( !stop_mcu0_nb_mask && !($time < stop_mcu0_nb_crc_inj_time) && !(stop_mcu0_nb_crc_inj_time == 0) )
10485 begin
10486 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on NB channel for MCU0, time now is %d",$time);
10487 force mcu0_nb_err_enable=0;
10488 stop_mcu0_nb_mask = 1;
10489 end
10490 else if ( !restart_mcu0_nb_mask && !($time < restart_mcu0_nb_crc_inj_time) && !(restart_mcu0_nb_crc_inj_time == 0) && (restart_mcu0_nb_crc_inj_time > stop_mcu0_nb_crc_inj_time) )
10491 begin
10492 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on NB channel for MCU0, time now is %d",$time);
10493 release mcu0_nb_err_enable;
10494 restart_mcu0_nb_mask=1;
10495 end
10496 else if ( !restart_stop_mcu0_nb_mask && !($time < restart_stop_mcu0_nb_crc_inj_time) && !(restart_stop_mcu0_nb_crc_inj_time == 0) && (restart_stop_mcu0_nb_crc_inj_time > restart_mcu0_nb_crc_inj_time) )
10497 begin
10498 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on NB channel for MCU0, time now is %d",$time);
10499 force mcu0_nb_err_enable=0;
10500 restart_stop_mcu0_nb_mask=1;
10501 end
10502
10503// code for fullchip crc injection on both NB and SB has been completely changed
10504// 11/02/2006
10505`ifdef FC_CRC_INJECT
10506 if (mcu0_nb_err_enable==1) begin
10507 trigger_NB=1;
10508 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: CRC NB masks : mcu0_nb_bit_time_mask[11:0] is %b, mcu0_nb_lane_mask[13:0] is %b",mcu0_nb_bit_time_mask,mcu0_nb_lane_mask);
10509
10510 found=0; i=0; j=-1;
10511 for (i=0; i<`MAX_CRC_ERRORS; i=i+1)
10512 begin
10513 if ( (mcu0_nb_data_array_QW1[i][167:0]==`MCU0.lndskw0_data[167:0] && found==0 && mcu0_nb_quadword==1) ||
10514 (mcu0_nb_data_array_QW2[i][167:0]==`MCU0.lndskw1_data[167:0] && found==0 && mcu0_nb_quadword==2) )
10515 //see if data already exists in array
10516 begin found=1; j=i; end
10517 if (found==0 && ( !(mcu0_nb_data_array_QW1[i][167:0]===168'bx) && mcu0_nb_quadword==1) ||
10518 ( !(mcu0_nb_data_array_QW2[i][167:0]===168'bx) && mcu0_nb_quadword==2) )
10519 //find the array index to put "new" data
10520 j=i;
10521 end
10522 if (found==0 && (N%delay_crc==1))
10523 begin
10524 if (mcu0_nb_quadword==1) begin
10525 mcu0_nb_data_array_QW1[j+1][167:0]=`MCU0.lndskw0_data[167:0];
10526 if (mcu0_inject_fbu_err==1)
10527 mcu0_nb_data_array_QW1_cnt[j+1]=3;
10528 else
10529 mcu0_nb_data_array_QW1_cnt[j+1]=1;
10530 end
10531 if (mcu0_nb_quadword==2) begin
10532 mcu0_nb_data_array_QW2[j+1][167:0]=`MCU0.lndskw1_data[167:0];
10533 if (mcu0_inject_fbu_err==1)
10534 mcu0_nb_data_array_QW2_cnt[j+1]=3;
10535 else
10536 mcu0_nb_data_array_QW2_cnt[j+1]=1;
10537 end
10538 end
10539
10540 if ( (mcu0_inject_fbu_err==1 && found==1 && ( (mcu0_nb_quadword==1 && mcu0_nb_data_array_QW1_cnt[j]>0)
10541 || (mcu0_nb_quadword==2 && mcu0_nb_data_array_QW2_cnt[j]>0) ) ) ||
10542 (found==0 && ( (mcu0_nb_quadword==1 && mcu0_nb_data_array_QW1_cnt[j+1]>0)
10543 || (mcu0_nb_quadword==2 && mcu0_nb_data_array_QW2_cnt[j+1]>0) ) ) ) begin
10544
10545 if (mcu0_nb_quadword==1) begin
10546 NBQW1=1;
10547 corrupted_mcu0_nb_lndskw0_data[167:0] = `MCU0.lndskw0_data[167:0] ^ ( return_168_bits_nb_mask ( mcu0_nb_bit_time_mask, mcu0_nb_lane_mask ) ) ;
10548 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 NB QW1: orig. data [167:0] was %x, modif. data [167:0] is %x",`MCU0.lndskw0_data[167:0],corrupted_mcu0_nb_lndskw0_data[167:0]);
10549 force `MCU0.lndskw0_data[167:0] = corrupted_mcu0_nb_lndskw0_data[167:0];
10550 @(posedge drl2clk);
10551 release `MCU0.lndskw0_data[167:0];
10552 end
10553 else if (mcu0_nb_quadword==2) begin
10554 NBQW2=1;
10555 corrupted_mcu0_nb_lndskw1_data[167:0] = `MCU0.lndskw1_data[167:0] ^ ( return_168_bits_nb_mask ( mcu0_nb_bit_time_mask, mcu0_nb_lane_mask ) ) ;
10556 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 NB QW2: orig. data [167:0] was %x, modif. data [167:0] is %x",`MCU0.lndskw1_data[167:0],corrupted_mcu0_nb_lndskw1_data[167:0]);
10557 force `MCU0.lndskw1_data[167:0] = corrupted_mcu0_nb_lndskw1_data[167:0];
10558 @(posedge drl2clk);
10559 release `MCU0.lndskw1_data[167:0];
10560 end
10561 end
10562
10563 @(posedge drl2clk);
10564
10565 found=0; i=0; j=-1;
10566 for (i=0; i<`MAX_CRC_ERRORS; i=i+1)
10567 begin
10568 if ( (mcu0_nb_data_array_QW3[i][167:0]==`MCU0.lndskw0_data[167:0] && found==0 && mcu0_nb_quadword==3) ||
10569 (mcu0_nb_data_array_QW4[i][167:0]==`MCU0.lndskw1_data[167:0] && found==0 && mcu0_nb_quadword==4) )
10570 begin found=1; j=i; end
10571 if (found==0 && ( !(mcu0_nb_data_array_QW3[i][167:0]===168'bx) && mcu0_nb_quadword==3) ||
10572 ( !(mcu0_nb_data_array_QW4[i][167:0]===168'bx) && mcu0_nb_quadword==4) )
10573 j=i;
10574 end
10575 if (found==0 && (N%delay_crc==1))
10576 begin
10577 if (mcu0_nb_quadword==3) begin
10578 mcu0_nb_data_array_QW3[j+1][167:0]=`MCU0.lndskw0_data[167:0];
10579 if (mcu0_inject_fbu_err==1)
10580 mcu0_nb_data_array_QW3_cnt[j+1]=3;
10581 else
10582 mcu0_nb_data_array_QW3_cnt[j+1]=1;
10583 end
10584 if (mcu0_nb_quadword==4) begin
10585 mcu0_nb_data_array_QW4[j+1][167:0]=`MCU0.lndskw1_data[167:0];
10586 if (mcu0_inject_fbu_err==1)
10587 mcu0_nb_data_array_QW4_cnt[j+1]=3;
10588 else
10589 mcu0_nb_data_array_QW4_cnt[j+1]=1;
10590 end
10591 end
10592
10593 if ( (mcu0_inject_fbu_err==1 && found==1 && ( (mcu0_nb_quadword==3 && mcu0_nb_data_array_QW3_cnt[j]>0)
10594 || (mcu0_nb_quadword==4 && mcu0_nb_data_array_QW4_cnt[j]>0) ) ) ||
10595 (found==0 && ( (mcu0_nb_quadword==3 && mcu0_nb_data_array_QW3_cnt[j+1]>0)
10596 || (mcu0_nb_quadword==4 && mcu0_nb_data_array_QW4_cnt[j+1]>0) ) ) ) begin
10597
10598 if (mcu0_nb_quadword==3) begin
10599 NBQW3=1;
10600 corrupted_mcu0_nb_lndskw0_data[167:0] = `MCU0.lndskw0_data[167:0] ^ ( return_168_bits_nb_mask ( mcu0_nb_bit_time_mask, mcu0_nb_lane_mask ) ) ;
10601 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 NB QW3: orig. data [167:0] was %x, modif. data [167:0] is %x",`MCU0.lndskw0_data[167:0],corrupted_mcu0_nb_lndskw0_data[167:0]);
10602 force `MCU0.lndskw0_data[167:0] = corrupted_mcu0_nb_lndskw0_data[167:0];
10603 @(posedge drl2clk);
10604 release `MCU0.lndskw0_data[167:0];
10605 end
10606 else if (mcu0_nb_quadword==4) begin
10607 NBQW4=1;
10608 corrupted_mcu0_nb_lndskw1_data[167:0] = `MCU0.lndskw1_data[167:0] ^ ( return_168_bits_nb_mask ( mcu0_nb_bit_time_mask, mcu0_nb_lane_mask ) ) ;
10609 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 NB QW4: orig. data [167:0] was %x, modif. data [167:0] is %x",`MCU0.lndskw1_data[167:0],corrupted_mcu0_nb_lndskw1_data[167:0]);
10610 force `MCU0.lndskw1_data[167:0] = corrupted_mcu0_nb_lndskw1_data[167:0];
10611 @(posedge drl2clk);
10612 release `MCU0.lndskw1_data[167:0];
10613 end
10614 end
10615
10616 if (found==0) begin
10617 if (mcu0_nb_quadword==1 && mcu0_nb_data_array_QW1_cnt[j+1]>0) mcu0_nb_data_array_QW1_cnt[j+1]=mcu0_nb_data_array_QW1_cnt[j+1]-1;
10618 if (mcu0_nb_quadword==2 && mcu0_nb_data_array_QW2_cnt[j+1]>0) mcu0_nb_data_array_QW2_cnt[j+1]=mcu0_nb_data_array_QW2_cnt[j+1]-1;
10619 if (mcu0_nb_quadword==3 && mcu0_nb_data_array_QW3_cnt[j+1]>0) mcu0_nb_data_array_QW3_cnt[j+1]=mcu0_nb_data_array_QW3_cnt[j+1]-1;
10620 if (mcu0_nb_quadword==4 && mcu0_nb_data_array_QW4_cnt[j+1]>0) mcu0_nb_data_array_QW4_cnt[j+1]=mcu0_nb_data_array_QW4_cnt[j+1]-1;
10621 end
10622 else begin
10623 if (mcu0_nb_quadword==1 && mcu0_nb_data_array_QW1_cnt[j]>0) mcu0_nb_data_array_QW1_cnt[j]=mcu0_nb_data_array_QW1_cnt[j]-1;
10624 if (mcu0_nb_quadword==2 && mcu0_nb_data_array_QW2_cnt[j]>0) mcu0_nb_data_array_QW2_cnt[j]=mcu0_nb_data_array_QW2_cnt[j]-1;
10625 if (mcu0_nb_quadword==3 && mcu0_nb_data_array_QW3_cnt[j]>0) mcu0_nb_data_array_QW3_cnt[j]=mcu0_nb_data_array_QW3_cnt[j]-1;
10626 if (mcu0_nb_quadword==4 && mcu0_nb_data_array_QW4_cnt[j]>0) mcu0_nb_data_array_QW4_cnt[j]=mcu0_nb_data_array_QW4_cnt[j]-1;
10627 end
10628 end
10629 NBQW1=0; NBQW2=0; NBQW3=0; NBQW4=0;
10630 trigger_NB=0;
10631
10632`ifdef FC_CRC_INJECT
10633end
10634`endif
10635
10636`else //mcusat
10637 if ( (mcu0_nb_err_enable==1) && mcu0_drif_dram_cmd_a==`RD ||
10638 (`MCU0.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
10639 (`MCU0.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
10640 (`MCU0.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
10641 (`MCU0.fbdic.fbdic_scr_frame_req==1'b1 ) &&
10642 (mcu0_nb_channel_error_cnt>0) &&
10643 (!mcu0_esr_fbr && !mcu0_esr_fbu) && (~mcu0_esr_fbu || mcu0_inject_fbu_err) &&
10644 (`MCU0.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
10645 (`MCU0.drif.drif_err_state == 5'h1 || mcu0_inject_fbu_err))
10646 begin
10647
10648
10649 if (mcu0_nb_err_random)
10650 repeat ((mcu0_chnl_lat-4)+mcu0_nb_random_cycle) @ (posedge drl2clk);
10651 else
10652 repeat ((mcu0_chnl_lat-4)+mcu0_nb_cycle_cnt) @ (posedge drl2clk);
10653
10654
10655`ifdef NEC_FBDIMM
10656 repeat (6) @ (posedge sclk);
10657`else
10658 repeat (11) @ (posedge sclk);
10659`endif
10660
10661 if (mcu0_enable_ch0_err_inj) begin
10662 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_freq = 12'h1;
10663 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_period = 12'h1;
10664 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_frame_num = 12'h1;
10665
10666 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_freq = 12'h1;
10667 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_period = 12'h1;
10668 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_frame_num = 12'h1;
10669
10670 if (mcu0_nb_err_random) begin
10671 if (mcu0_nb_bit_time_mask[0]) begin
10672 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn0_crc_mask = mcu0_nb_lane_mask;
10673 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn0_crc_mask = mcu0_nb_lane_mask;
10674 end
10675 if (mcu0_nb_bit_time_mask[1]) begin
10676 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn1_crc_mask = mcu0_nb_lane_mask;
10677 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn1_crc_mask = mcu0_nb_lane_mask;
10678 end
10679 if (mcu0_nb_bit_time_mask[2]) begin
10680 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn2_crc_mask = mcu0_nb_lane_mask;
10681 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn2_crc_mask = mcu0_nb_lane_mask;
10682 end
10683 if (mcu0_nb_bit_time_mask[3]) begin
10684 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn3_crc_mask = mcu0_nb_lane_mask;
10685 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn3_crc_mask = mcu0_nb_lane_mask;
10686 end
10687 if (mcu0_nb_bit_time_mask[4]) begin
10688 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn4_crc_mask = mcu0_nb_lane_mask;
10689 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn4_crc_mask = mcu0_nb_lane_mask;
10690 end
10691 if (mcu0_nb_bit_time_mask[5]) begin
10692 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn5_crc_mask = mcu0_nb_lane_mask;
10693 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn5_crc_mask = mcu0_nb_lane_mask;
10694 end
10695 if (mcu0_nb_bit_time_mask[6]) begin
10696 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn6_crc_mask = mcu0_nb_lane_mask;
10697 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn6_crc_mask = mcu0_nb_lane_mask;
10698 end
10699 if (mcu0_nb_bit_time_mask[7]) begin
10700 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn7_crc_mask = mcu0_nb_lane_mask;
10701 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn7_crc_mask = mcu0_nb_lane_mask;
10702 end
10703 if (mcu0_nb_bit_time_mask[8]) begin
10704 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn8_crc_mask = mcu0_nb_lane_mask;
10705 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn8_crc_mask = mcu0_nb_lane_mask;
10706 end
10707 if (mcu0_nb_bit_time_mask[9]) begin
10708 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn9_crc_mask = mcu0_nb_lane_mask;
10709 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn9_crc_mask = mcu0_nb_lane_mask;
10710 end
10711 if (mcu0_nb_bit_time_mask[10]) begin
10712 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn10_crc_mask = mcu0_nb_lane_mask;
10713 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn10_crc_mask = mcu0_nb_lane_mask;
10714 end
10715 if (mcu0_nb_bit_time_mask[11]) begin
10716 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn11_crc_mask = mcu0_nb_lane_mask;
10717 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn11_crc_mask = mcu0_nb_lane_mask;
10718 end
10719 end
10720
10721 if (mcu0_inject_fbu_err && !mcu0_esr_fbu)
10722 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 NB - MCU0 (mcu0_nb_bit_time_mask[11:0] is %b, mcu0_nb_lane_mask[13:0] is %b)",mcu0_nb_bit_time_mask,mcu0_nb_lane_mask);
10723 else if (!mcu0_esr_fbr)
10724 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 NB - MCU0 (mcu0_nb_bit_time_mask[11:0] is %b, mcu0_nb_lane_mask[13:0] is %b)",mcu0_nb_bit_time_mask,mcu0_nb_lane_mask);
10725
10726 end
10727
10728 if (mcu0_enable_ch1_err_inj) begin
10729 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_freq = 12'h1;
10730 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_period = 12'h1;
10731 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_frame_num = 12'h1;
10732
10733 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_freq = 12'h1;
10734 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_period = 12'h1;
10735 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_frame_num = 12'h1;
10736
10737 if (mcu0_nb_err_random) begin
10738 if (mcu0_nb_bit_time_mask[0]) begin
10739 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn0_crc_mask = mcu0_nb_lane_mask;
10740 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn0_crc_mask = mcu0_nb_lane_mask;
10741 end
10742 if (mcu0_nb_bit_time_mask[1]) begin
10743 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn1_crc_mask = mcu0_nb_lane_mask;
10744 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn1_crc_mask = mcu0_nb_lane_mask;
10745 end
10746 if (mcu0_nb_bit_time_mask[2]) begin
10747 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn2_crc_mask = mcu0_nb_lane_mask;
10748 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn2_crc_mask = mcu0_nb_lane_mask;
10749 end
10750 if (mcu0_nb_bit_time_mask[3]) begin
10751 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn3_crc_mask = mcu0_nb_lane_mask;
10752 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn3_crc_mask = mcu0_nb_lane_mask;
10753 end
10754 if (mcu0_nb_bit_time_mask[4]) begin
10755 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn4_crc_mask = mcu0_nb_lane_mask;
10756 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn4_crc_mask = mcu0_nb_lane_mask;
10757 end
10758 if (mcu0_nb_bit_time_mask[5]) begin
10759 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn5_crc_mask = mcu0_nb_lane_mask;
10760 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn5_crc_mask = mcu0_nb_lane_mask;
10761 end
10762 if (mcu0_nb_bit_time_mask[6]) begin
10763 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn6_crc_mask = mcu0_nb_lane_mask;
10764 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn6_crc_mask = mcu0_nb_lane_mask;
10765 end
10766 if (mcu0_nb_bit_time_mask[7]) begin
10767 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn7_crc_mask = mcu0_nb_lane_mask;
10768 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn7_crc_mask = mcu0_nb_lane_mask;
10769 end
10770 if (mcu0_nb_bit_time_mask[8]) begin
10771 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn8_crc_mask = mcu0_nb_lane_mask;
10772 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn8_crc_mask = mcu0_nb_lane_mask;
10773 end
10774 if (mcu0_nb_bit_time_mask[9]) begin
10775 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn9_crc_mask = mcu0_nb_lane_mask;
10776 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn9_crc_mask = mcu0_nb_lane_mask;
10777 end
10778 if (mcu0_nb_bit_time_mask[10]) begin
10779 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn10_crc_mask = mcu0_nb_lane_mask;
10780 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn10_crc_mask = mcu0_nb_lane_mask;
10781 end
10782 if (mcu0_nb_bit_time_mask[11]) begin
10783 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn11_crc_mask = mcu0_nb_lane_mask;
10784 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn11_crc_mask = mcu0_nb_lane_mask;
10785 end
10786 end
10787
10788 if (mcu0_inject_fbu_err && !mcu0_esr_fbu)
10789 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 NB - MCU0 (mcu0_nb_bit_time_mask[11:0] is %b, mcu0_nb_lane_mask[13:0] is %b)",mcu0_nb_bit_time_mask,mcu0_nb_lane_mask);
10790 else if (!mcu0_esr_fbr)
10791 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 NB - MCU0 (mcu0_nb_bit_time_mask[11:0] is %b, mcu0_nb_lane_mask[13:0] is %b)",mcu0_nb_bit_time_mask,mcu0_nb_lane_mask);
10792
10793 end
10794
10795 repeat (1) @ (posedge sclk);
10796
10797 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_freq;
10798 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_period;
10799 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_frame_num;
10800
10801 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_freq;
10802 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_period;
10803 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_frame_num;
10804
10805 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_freq;
10806 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_period;
10807 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_frame_num;
10808
10809 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_freq;
10810 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_period;
10811 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_frame_num;
10812
10813 if (mcu0_nb_err_random==0)
10814 mcu0_nb_channel_error_cnt=mcu0_nb_channel_error_cnt - 1;
10815 else begin
10816 mcu0_nb_err_enable = 0;
10817 mcu0_nb_lane_mask = 14'h1;
10818 mcu0_nb_bit_time_mask = 12'h1;
10819 end
10820 end
10821`endif
10822end
10823end
10824
10825// --- MCU1 ---
10826
10827
10828always @ ( mcu1_drif_dram_cmd_a or
10829 `MCU1.fbdic.fbdic_config_reg_read or
10830 `MCU1.fbdic.fbdic_config_reg_write or
10831 `MCU1.fbdic.fbdic_sync_frame_req or
10832 `MCU1.fbdic.fbdic_scr_frame_req
10833 )
10834begin
10835if (enabled && ~ras_corner_case)
10836begin
10837
10838 // --------- Random NB CRC Err Injection --------
10839 if (mcu1_nb_err_random) begin
10840 mcu1_nb_random_cycle = ({$random} % 3);
10841 if (mcu1_nb_crc_multiple_bit_times)
10842 mcu1_nb_bit_time_mask = $random;
10843 else begin
10844 mcu1_nb_random_bit_time = ({$random} % BIT_TIMES);
10845 mcu1_nb_bit_time_mask = mcu1_nb_bit_time_mask << mcu1_nb_random_bit_time;
10846 end
10847 if (mcu1_nb_crc_multiple_lanes)
10848 mcu1_nb_lane_mask = $random;
10849 else begin
10850 mcu1_nb_random_lane = ({$random} % NB_LANES);
10851 mcu1_nb_lane_mask = mcu1_nb_lane_mask << mcu1_nb_random_lane;
10852 end
10853 mcu1_nb_random_val = ({$random} % 100);
10854 if (!(mcu1_nb_random_val > MCU1_NB_RANDOM_WEIGHT)) mcu1_nb_err_enable=1;
10855 end
10856
10857
10858
10859 if ( !stop_mcu1_nb_mask && !($time < stop_mcu1_nb_crc_inj_time) && !(stop_mcu1_nb_crc_inj_time == 0) )
10860 begin
10861 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on NB channel for MCU1, time now is %d",$time);
10862 force mcu1_nb_err_enable=0;
10863 stop_mcu1_nb_mask = 1;
10864 end
10865 else if ( !restart_mcu1_nb_mask && !($time < restart_mcu1_nb_crc_inj_time) && !(restart_mcu1_nb_crc_inj_time == 0) && (restart_mcu1_nb_crc_inj_time > stop_mcu1_nb_crc_inj_time) )
10866 begin
10867 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on NB channel for MCU1, time now is %d",$time);
10868 release mcu1_nb_err_enable;
10869 restart_mcu1_nb_mask=1;
10870 end
10871 else if ( !restart_stop_mcu1_nb_mask && !($time < restart_stop_mcu1_nb_crc_inj_time) && !(restart_stop_mcu1_nb_crc_inj_time == 0) && (restart_stop_mcu1_nb_crc_inj_time > restart_mcu1_nb_crc_inj_time) )
10872 begin
10873 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on NB channel for MCU1, time now is %d",$time);
10874 force mcu1_nb_err_enable=0;
10875 restart_stop_mcu1_nb_mask=1;
10876 end
10877
10878
10879
10880 if ( ( $test$plusargs("INJECT_CRC_MCU1_NB_ERRQ") && (mcu1_nb_err < 8) && mcu1_nb_err_random ) &&
10881 ( `MCU1.drif.reqq.drq0.drq_rdq_full == 0 && `MCU1.drif.reqq.drq0.drq_wrq_full == 0 ) && // check both rd and wr queues on both channels are empty
10882 ( `MCU1.drif.reqq.drq1.drq_rdq_full == 0 && `MCU1.drif.reqq.drq1.drq_wrq_full == 0 ) &&
10883 ( `MCU1.drif.reqq.drq0.drq_empty == 1 && `MCU1.drif.reqq.drq1.drq_empty == 1 ) && // check channel 0/1 dram rd/wr queues
10884 ( `MCU1.drif.errq.errq_empty == 1 && `MCU1.drif.reqq.woq_err_fifo_empty == 1 ) && // check also dram rd/wr ecc/crc error fifo
10885`ifdef FC_CRC_INJECT
10886 passed_bootEnd_mask==1 &&
10887`endif
10888 ( mcu1_drif_dram_cmd_a==`RD ||
10889 (`MCU1.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
10890 (`MCU1.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
10891 (`MCU1.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
10892 `MCU1.fbdic.fbdic_scr_frame_req==1'b1) )
10893 begin
10894 force mcu1_nb_err_enable=0;
10895 inject_crc_mcu1_nb_errq_mask=1;
10896 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Injecting CRC errors on NB channel in MCU1 via RD/WR queue tracking, errq loop count is %d (max. allowed is 8)",mcu1_nb_err);
10897 end
10898
10899 else if ( mcu1_nb_err_enable==1 && (mcu1_drif_dram_cmd_a==`RD ||
10900 (`MCU1.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
10901 (`MCU1.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
10902 (`MCU1.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
10903 (`MCU1.fbdic.fbdic_scr_frame_req==1'b1 )) &&
10904 (mcu1_nb_channel_error_cnt>0) &&
10905 (~mcu1_esr_fbu || mcu1_inject_fbu_err) &&
10906 (`MCU1.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
10907`ifdef FC_CRC_INJECT
10908 passed_bootEnd_mask==1 &&
10909 (!mcu1_esr_fbr && !mcu1_esr_fbu) &&
10910`endif
10911 (`MCU1.drif.drif_err_state == 5'h1 || mcu1_inject_fbu_err) )
10912 inject_crc_mcu1_nb_mask=1;
10913
10914
10915 if ( inject_crc_mcu1_nb_errq_mask==1 || (inject_crc_mcu1_nb_errq_mask==0 && inject_crc_mcu1_nb_mask==1 ) )
10916 begin
10917
10918
10919 if (mcu1_nb_err_random)
10920 repeat ((mcu1_chnl_lat-4)+mcu1_nb_random_cycle) @ (posedge drl2clk);
10921 else
10922 repeat ((mcu1_chnl_lat-4)+mcu1_nb_cycle_cnt) @ (posedge drl2clk);
10923`ifdef NEC_FBDIMM
10924 repeat (6) @ (posedge sclk);
10925`else
10926 repeat (11) @ (posedge sclk);
10927`endif
10928
10929
10930
10931 mcu1_nb_err = mcu1_nb_err + 1;
10932 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU1: NB --- injecting CRC error no. %d", mcu1_nb_err);
10933
10934 if (mcu1_enable_ch0_err_inj) begin
10935 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_crc_freq = 12'h1;
10936 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_crc_period = 12'h1;
10937 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_frame_num = 12'h1;
10938
10939 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_crc_freq = 12'h1;
10940 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_crc_period = 12'h1;
10941 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_frame_num = 12'h1;
10942
10943 if (mcu1_nb_err_random) begin
10944 if (mcu1_nb_bit_time_mask[0]) begin
10945 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn0_crc_mask = mcu1_nb_lane_mask;
10946 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn0_crc_mask = mcu1_nb_lane_mask;
10947 end
10948 if (mcu1_nb_bit_time_mask[1]) begin
10949 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn1_crc_mask = mcu1_nb_lane_mask;
10950 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn1_crc_mask = mcu1_nb_lane_mask;
10951 end
10952 if (mcu1_nb_bit_time_mask[2]) begin
10953 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn2_crc_mask = mcu1_nb_lane_mask;
10954 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn2_crc_mask = mcu1_nb_lane_mask;
10955 end
10956 if (mcu1_nb_bit_time_mask[3]) begin
10957 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn3_crc_mask = mcu1_nb_lane_mask;
10958 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn3_crc_mask = mcu1_nb_lane_mask;
10959 end
10960 if (mcu1_nb_bit_time_mask[4]) begin
10961 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn4_crc_mask = mcu1_nb_lane_mask;
10962 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn4_crc_mask = mcu1_nb_lane_mask;
10963 end
10964 if (mcu1_nb_bit_time_mask[5]) begin
10965 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn5_crc_mask = mcu1_nb_lane_mask;
10966 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn5_crc_mask = mcu1_nb_lane_mask;
10967 end
10968 if (mcu1_nb_bit_time_mask[6]) begin
10969 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn6_crc_mask = mcu1_nb_lane_mask;
10970 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn6_crc_mask = mcu1_nb_lane_mask;
10971 end
10972 if (mcu1_nb_bit_time_mask[7]) begin
10973 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn7_crc_mask = mcu1_nb_lane_mask;
10974 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn7_crc_mask = mcu1_nb_lane_mask;
10975 end
10976 if (mcu1_nb_bit_time_mask[8]) begin
10977 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn8_crc_mask = mcu1_nb_lane_mask;
10978 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn8_crc_mask = mcu1_nb_lane_mask;
10979 end
10980 if (mcu1_nb_bit_time_mask[9]) begin
10981 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn9_crc_mask = mcu1_nb_lane_mask;
10982 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn9_crc_mask = mcu1_nb_lane_mask;
10983 end
10984 if (mcu1_nb_bit_time_mask[10]) begin
10985 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn10_crc_mask = mcu1_nb_lane_mask;
10986 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn10_crc_mask = mcu1_nb_lane_mask;
10987 end
10988 if (mcu1_nb_bit_time_mask[11]) begin
10989 force tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn11_crc_mask = mcu1_nb_lane_mask;
10990 force tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn11_crc_mask = mcu1_nb_lane_mask;
10991 end
10992 end
10993
10994 if (mcu1_inject_fbu_err && !mcu1_esr_fbu)
10995 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 NB - MCU1 (mcu1_nb_bit_time_mask[11:0] is %b, mcu1_nb_lane_mask[13:0] is %b)",mcu1_nb_bit_time_mask,mcu1_nb_lane_mask);
10996 else if (!mcu1_esr_fbr)
10997 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 NB - MCU1 (mcu1_nb_bit_time_mask[11:0] is %b, mcu1_nb_lane_mask[13:0] is %b)",mcu1_nb_bit_time_mask,mcu1_nb_lane_mask);
10998
10999 end
11000
11001 if (mcu1_enable_ch1_err_inj) begin
11002 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_crc_freq = 12'h1;
11003 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_crc_period = 12'h1;
11004 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_frame_num = 12'h1;
11005
11006 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_crc_freq = 12'h1;
11007 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_crc_period = 12'h1;
11008 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_frame_num = 12'h1;
11009
11010 if (mcu1_nb_err_random) begin
11011 if (mcu1_nb_bit_time_mask[0]) begin
11012 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn0_crc_mask = mcu1_nb_lane_mask;
11013 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn0_crc_mask = mcu1_nb_lane_mask;
11014 end
11015 if (mcu1_nb_bit_time_mask[1]) begin
11016 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn1_crc_mask = mcu1_nb_lane_mask;
11017 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn1_crc_mask = mcu1_nb_lane_mask;
11018 end
11019 if (mcu1_nb_bit_time_mask[2]) begin
11020 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn2_crc_mask = mcu1_nb_lane_mask;
11021 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn2_crc_mask = mcu1_nb_lane_mask;
11022 end
11023 if (mcu1_nb_bit_time_mask[3]) begin
11024 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn3_crc_mask = mcu1_nb_lane_mask;
11025 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn3_crc_mask = mcu1_nb_lane_mask;
11026 end
11027 if (mcu1_nb_bit_time_mask[4]) begin
11028 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn4_crc_mask = mcu1_nb_lane_mask;
11029 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn4_crc_mask = mcu1_nb_lane_mask;
11030 end
11031 if (mcu1_nb_bit_time_mask[5]) begin
11032 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn5_crc_mask = mcu1_nb_lane_mask;
11033 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn5_crc_mask = mcu1_nb_lane_mask;
11034 end
11035 if (mcu1_nb_bit_time_mask[6]) begin
11036 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn6_crc_mask = mcu1_nb_lane_mask;
11037 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn6_crc_mask = mcu1_nb_lane_mask;
11038 end
11039 if (mcu1_nb_bit_time_mask[7]) begin
11040 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn7_crc_mask = mcu1_nb_lane_mask;
11041 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn7_crc_mask = mcu1_nb_lane_mask;
11042 end
11043 if (mcu1_nb_bit_time_mask[8]) begin
11044 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn8_crc_mask = mcu1_nb_lane_mask;
11045 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn8_crc_mask = mcu1_nb_lane_mask;
11046 end
11047 if (mcu1_nb_bit_time_mask[9]) begin
11048 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn9_crc_mask = mcu1_nb_lane_mask;
11049 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn9_crc_mask = mcu1_nb_lane_mask;
11050 end
11051 if (mcu1_nb_bit_time_mask[10]) begin
11052 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn10_crc_mask = mcu1_nb_lane_mask;
11053 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn10_crc_mask = mcu1_nb_lane_mask;
11054 end
11055 if (mcu1_nb_bit_time_mask[11]) begin
11056 force tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn11_crc_mask = mcu1_nb_lane_mask;
11057 force tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn11_crc_mask = mcu1_nb_lane_mask;
11058 end
11059 end
11060
11061 if (mcu1_inject_fbu_err && !mcu1_esr_fbu)
11062 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 NB - MCU1 (mcu1_nb_bit_time_mask[11:0] is %b, mcu1_nb_lane_mask[13:0] is %b)",mcu1_nb_bit_time_mask,mcu1_nb_lane_mask);
11063 else if (!mcu1_esr_fbr)
11064 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 NB - MCU1 (mcu1_nb_bit_time_mask[11:0] is %b, mcu1_nb_lane_mask[13:0] is %b)",mcu1_nb_bit_time_mask,mcu1_nb_lane_mask);
11065
11066 end
11067
11068 repeat (1) @ (posedge sclk);
11069
11070 release tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_crc_freq;
11071 release tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_crc_period;
11072 release tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_frame_num;
11073
11074 release tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_crc_freq;
11075 release tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_crc_period;
11076 release tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_frame_num;
11077
11078 release tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_crc_freq;
11079 release tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_crc_period;
11080 release tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_frame_num;
11081
11082 release tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_crc_freq;
11083 release tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_crc_period;
11084 release tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_frame_num;
11085
11086 inject_crc_mcu1_nb_mask=0;
11087 if (mcu1_nb_err_random==0)
11088 mcu1_nb_channel_error_cnt=mcu1_nb_channel_error_cnt - 1;
11089 else begin
11090 mcu1_nb_err_enable = 0;
11091 mcu1_nb_lane_mask = 14'h1;
11092 mcu1_nb_bit_time_mask = 12'h1;
11093 end
11094 end
11095end
11096end
11097
11098// --- MCU2 ---
11099
11100
11101always @ ( mcu2_drif_dram_cmd_a or
11102 `MCU2.fbdic.fbdic_config_reg_read or
11103 `MCU2.fbdic.fbdic_config_reg_write or
11104 `MCU2.fbdic.fbdic_sync_frame_req or
11105 `MCU2.fbdic.fbdic_scr_frame_req
11106 )
11107begin
11108if (enabled && ~ras_corner_case)
11109begin
11110
11111 // --------- Random NB CRC Err Injection --------
11112 if (mcu2_nb_err_random) begin
11113 mcu2_nb_random_cycle = ({$random} % 3);
11114 if (mcu2_nb_crc_multiple_bit_times)
11115 mcu2_nb_bit_time_mask = $random;
11116 else begin
11117 mcu2_nb_random_bit_time = ({$random} % BIT_TIMES);
11118 mcu2_nb_bit_time_mask = mcu2_nb_bit_time_mask << mcu2_nb_random_bit_time;
11119 end
11120 if (mcu2_nb_crc_multiple_lanes)
11121 mcu2_nb_lane_mask = $random;
11122 else begin
11123 mcu2_nb_random_lane = ({$random} % NB_LANES);
11124 mcu2_nb_lane_mask = mcu2_nb_lane_mask << mcu2_nb_random_lane;
11125 end
11126 mcu2_nb_random_val = ({$random} % 100);
11127 if (!(mcu2_nb_random_val > MCU2_NB_RANDOM_WEIGHT)) mcu2_nb_err_enable=1;
11128 end
11129
11130
11131
11132 if ( !stop_mcu2_nb_mask && !($time < stop_mcu2_nb_crc_inj_time) && !(stop_mcu2_nb_crc_inj_time == 0) )
11133 begin
11134 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on NB channel for MCU2, time now is %d",$time);
11135 force mcu2_nb_err_enable=0;
11136 stop_mcu2_nb_mask = 1;
11137 end
11138 else if ( !restart_mcu2_nb_mask && !($time < restart_mcu2_nb_crc_inj_time) && !(restart_mcu2_nb_crc_inj_time == 0) && (restart_mcu2_nb_crc_inj_time > stop_mcu2_nb_crc_inj_time) )
11139 begin
11140 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on NB channel for MCU2, time now is %d",$time);
11141 release mcu2_nb_err_enable;
11142 restart_mcu2_nb_mask=1;
11143 end
11144 else if ( !restart_stop_mcu2_nb_mask && !($time < restart_stop_mcu2_nb_crc_inj_time) && !(restart_stop_mcu2_nb_crc_inj_time == 0) && (restart_stop_mcu2_nb_crc_inj_time > restart_mcu2_nb_crc_inj_time) )
11145 begin
11146 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on NB channel for MCU2, time now is %d",$time);
11147 force mcu2_nb_err_enable=0;
11148 restart_stop_mcu2_nb_mask=1;
11149 end
11150
11151
11152
11153 if ( ( $test$plusargs("INJECT_CRC_MCU2_NB_ERRQ") && (mcu2_nb_err < 8) && mcu2_nb_err_random ) &&
11154 ( `MCU2.drif.reqq.drq0.drq_rdq_full == 0 && `MCU2.drif.reqq.drq0.drq_wrq_full == 0 ) && // check both rd and wr queues on both channels are empty
11155 ( `MCU2.drif.reqq.drq1.drq_rdq_full == 0 && `MCU2.drif.reqq.drq1.drq_wrq_full == 0 ) &&
11156 ( `MCU2.drif.reqq.drq0.drq_empty == 1 && `MCU2.drif.reqq.drq1.drq_empty == 1 ) && // check channel 0/1 dram rd/wr queues
11157 ( `MCU2.drif.errq.errq_empty == 1 && `MCU2.drif.reqq.woq_err_fifo_empty == 1 ) && // check also dram rd/wr ecc/crc error fifo
11158`ifdef FC_CRC_INJECT
11159 passed_bootEnd_mask==1 &&
11160`endif
11161 ( mcu2_drif_dram_cmd_a==`RD ||
11162 (`MCU2.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
11163 (`MCU2.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
11164 (`MCU2.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
11165 `MCU2.fbdic.fbdic_scr_frame_req==1'b1) )
11166 begin
11167 force mcu2_nb_err_enable=0;
11168 inject_crc_mcu2_nb_errq_mask=1;
11169 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Injecting CRC errors on NB channel in MCU2 via RD/WR queue tracking, errq loop count is %d (max. allowed is 8)",mcu2_nb_err);
11170 end
11171
11172
11173 else if ( mcu2_nb_err_enable==1 && (mcu2_drif_dram_cmd_a==`RD ||
11174 (`MCU2.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
11175 (`MCU2.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
11176 (`MCU2.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
11177 (`MCU2.fbdic.fbdic_scr_frame_req==1'b1 )) &&
11178 (mcu2_nb_channel_error_cnt>0) &&
11179 (~mcu2_esr_fbu || mcu2_inject_fbu_err) &&
11180 (`MCU2.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
11181`ifdef FC_CRC_INJECT
11182 passed_bootEnd_mask==1 &&
11183 (!mcu2_esr_fbr && !mcu2_esr_fbu) &&
11184`endif
11185 (`MCU2.drif.drif_err_state == 5'h1 || mcu2_inject_fbu_err) )
11186 inject_crc_mcu2_nb_mask=1;
11187
11188
11189 if ( inject_crc_mcu2_nb_errq_mask==1 || (inject_crc_mcu2_nb_errq_mask==0 && inject_crc_mcu2_nb_mask==1 ) )
11190 begin
11191
11192
11193 if (mcu2_nb_err_random)
11194 repeat ((mcu2_chnl_lat-4)+mcu2_nb_random_cycle) @ (posedge drl2clk);
11195 else
11196 repeat ((mcu2_chnl_lat-4)+mcu2_nb_cycle_cnt) @ (posedge drl2clk);
11197
11198
11199`ifdef NEC_FBDIMM
11200 repeat (6) @ (posedge sclk);
11201`else
11202 repeat (11) @ (posedge sclk);
11203`endif
11204
11205
11206
11207 mcu2_nb_err = mcu2_nb_err + 1;
11208 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU2: NB --- injecting CRC error no. %d", mcu2_nb_err);
11209
11210 if (mcu2_enable_ch0_err_inj) begin
11211 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_crc_freq = 12'h1;
11212 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_crc_period = 12'h1;
11213 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_frame_num = 12'h1;
11214
11215 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_crc_freq = 12'h1;
11216 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_crc_period = 12'h1;
11217 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_frame_num = 12'h1;
11218
11219 if (mcu2_nb_err_random) begin
11220 if (mcu2_nb_bit_time_mask[0]) begin
11221 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn0_crc_mask = mcu2_nb_lane_mask;
11222 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn0_crc_mask = mcu2_nb_lane_mask;
11223 end
11224 if (mcu2_nb_bit_time_mask[1]) begin
11225 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn1_crc_mask = mcu2_nb_lane_mask;
11226 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn1_crc_mask = mcu2_nb_lane_mask;
11227 end
11228 if (mcu2_nb_bit_time_mask[2]) begin
11229 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn2_crc_mask = mcu2_nb_lane_mask;
11230 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn2_crc_mask = mcu2_nb_lane_mask;
11231 end
11232 if (mcu2_nb_bit_time_mask[3]) begin
11233 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn3_crc_mask = mcu2_nb_lane_mask;
11234 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn3_crc_mask = mcu2_nb_lane_mask;
11235 end
11236 if (mcu2_nb_bit_time_mask[4]) begin
11237 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn4_crc_mask = mcu2_nb_lane_mask;
11238 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn4_crc_mask = mcu2_nb_lane_mask;
11239 end
11240 if (mcu2_nb_bit_time_mask[5]) begin
11241 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn5_crc_mask = mcu2_nb_lane_mask;
11242 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn5_crc_mask = mcu2_nb_lane_mask;
11243 end
11244 if (mcu2_nb_bit_time_mask[6]) begin
11245 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn6_crc_mask = mcu2_nb_lane_mask;
11246 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn6_crc_mask = mcu2_nb_lane_mask;
11247 end
11248 if (mcu2_nb_bit_time_mask[7]) begin
11249 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn7_crc_mask = mcu2_nb_lane_mask;
11250 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn7_crc_mask = mcu2_nb_lane_mask;
11251 end
11252 if (mcu2_nb_bit_time_mask[8]) begin
11253 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn8_crc_mask = mcu2_nb_lane_mask;
11254 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn8_crc_mask = mcu2_nb_lane_mask;
11255 end
11256 if (mcu2_nb_bit_time_mask[9]) begin
11257 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn9_crc_mask = mcu2_nb_lane_mask;
11258 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn9_crc_mask = mcu2_nb_lane_mask;
11259 end
11260 if (mcu2_nb_bit_time_mask[10]) begin
11261 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn10_crc_mask = mcu2_nb_lane_mask;
11262 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn10_crc_mask = mcu2_nb_lane_mask;
11263 end
11264 if (mcu2_nb_bit_time_mask[11]) begin
11265 force tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn11_crc_mask = mcu2_nb_lane_mask;
11266 force tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn11_crc_mask = mcu2_nb_lane_mask;
11267 end
11268 end
11269
11270 if (mcu2_inject_fbu_err && !mcu2_esr_fbu)
11271 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 NB - MCU2 (mcu2_nb_bit_time_mask[11:0] is %b, mcu2_nb_lane_mask[13:0] is %b)",mcu2_nb_bit_time_mask,mcu2_nb_lane_mask);
11272 else if (!mcu2_esr_fbr)
11273 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 NB - MCU2 (mcu2_nb_bit_time_mask[11:0] is %b, mcu2_nb_lane_mask[13:0] is %b)",mcu2_nb_bit_time_mask,mcu2_nb_lane_mask);
11274
11275 end
11276
11277 if (mcu2_enable_ch1_err_inj) begin
11278 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_crc_freq = 12'h1;
11279 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_crc_period = 12'h1;
11280 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_frame_num = 12'h1;
11281
11282 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_crc_freq = 12'h1;
11283 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_crc_period = 12'h1;
11284 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_frame_num = 12'h1;
11285
11286 if (mcu2_nb_err_random) begin
11287 if (mcu2_nb_bit_time_mask[0]) begin
11288 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn0_crc_mask = mcu2_nb_lane_mask;
11289 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn0_crc_mask = mcu2_nb_lane_mask;
11290 end
11291 if (mcu2_nb_bit_time_mask[1]) begin
11292 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn1_crc_mask = mcu2_nb_lane_mask;
11293 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn1_crc_mask = mcu2_nb_lane_mask;
11294 end
11295 if (mcu2_nb_bit_time_mask[2]) begin
11296 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn2_crc_mask = mcu2_nb_lane_mask;
11297 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn2_crc_mask = mcu2_nb_lane_mask;
11298 end
11299 if (mcu2_nb_bit_time_mask[3]) begin
11300 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn3_crc_mask = mcu2_nb_lane_mask;
11301 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn3_crc_mask = mcu2_nb_lane_mask;
11302 end
11303 if (mcu2_nb_bit_time_mask[4]) begin
11304 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn4_crc_mask = mcu2_nb_lane_mask;
11305 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn4_crc_mask = mcu2_nb_lane_mask;
11306 end
11307 if (mcu2_nb_bit_time_mask[5]) begin
11308 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn5_crc_mask = mcu2_nb_lane_mask;
11309 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn5_crc_mask = mcu2_nb_lane_mask;
11310 end
11311 if (mcu2_nb_bit_time_mask[6]) begin
11312 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn6_crc_mask = mcu2_nb_lane_mask;
11313 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn6_crc_mask = mcu2_nb_lane_mask;
11314 end
11315 if (mcu2_nb_bit_time_mask[7]) begin
11316 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn7_crc_mask = mcu2_nb_lane_mask;
11317 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn7_crc_mask = mcu2_nb_lane_mask;
11318 end
11319 if (mcu2_nb_bit_time_mask[8]) begin
11320 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn8_crc_mask = mcu2_nb_lane_mask;
11321 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn8_crc_mask = mcu2_nb_lane_mask;
11322 end
11323 if (mcu2_nb_bit_time_mask[9]) begin
11324 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn9_crc_mask = mcu2_nb_lane_mask;
11325 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn9_crc_mask = mcu2_nb_lane_mask;
11326 end
11327 if (mcu2_nb_bit_time_mask[10]) begin
11328 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn10_crc_mask = mcu2_nb_lane_mask;
11329 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn10_crc_mask = mcu2_nb_lane_mask;
11330 end
11331 if (mcu2_nb_bit_time_mask[11]) begin
11332 force tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn11_crc_mask = mcu2_nb_lane_mask;
11333 force tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn11_crc_mask = mcu2_nb_lane_mask;
11334 end
11335 end
11336
11337 if (mcu2_inject_fbu_err && !mcu2_esr_fbu)
11338 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 NB - MCU2 (mcu2_nb_bit_time_mask[11:0] is %b, mcu2_nb_lane_mask[13:0] is %b)",mcu2_nb_bit_time_mask,mcu2_nb_lane_mask);
11339 else if (!mcu2_esr_fbr)
11340 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 NB - MCU2 (mcu2_nb_bit_time_mask[11:0] is %b, mcu2_nb_lane_mask[13:0] is %b)",mcu2_nb_bit_time_mask,mcu2_nb_lane_mask);
11341
11342 end
11343
11344 repeat (1) @ (posedge sclk);
11345
11346 release tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_crc_freq;
11347 release tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_crc_period;
11348 release tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_frame_num;
11349
11350 release tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_crc_freq;
11351 release tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_crc_period;
11352 release tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_frame_num;
11353
11354 release tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_crc_freq;
11355 release tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_crc_period;
11356 release tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_frame_num;
11357
11358 release tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_crc_freq;
11359 release tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_crc_period;
11360 release tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_frame_num;
11361
11362 inject_crc_mcu2_nb_mask=0;
11363 if (mcu2_nb_err_random==0)
11364 mcu2_nb_channel_error_cnt=mcu2_nb_channel_error_cnt - 1;
11365 else begin
11366 mcu2_nb_err_enable = 0;
11367 mcu2_nb_lane_mask = 14'h1;
11368 mcu2_nb_bit_time_mask = 12'h1;
11369 end
11370 end
11371end
11372end
11373
11374// --- MCU3 ---
11375
11376
11377always @ ( mcu3_drif_dram_cmd_a or
11378 `MCU3.fbdic.fbdic_config_reg_read or
11379 `MCU3.fbdic.fbdic_config_reg_write or
11380 `MCU3.fbdic.fbdic_sync_frame_req or
11381 `MCU3.fbdic.fbdic_scr_frame_req
11382 )
11383begin
11384if (enabled && ~ras_corner_case)
11385begin
11386
11387 // --------- Random NB CRC Err Injection --------
11388 if (mcu3_nb_err_random) begin
11389 mcu3_nb_random_cycle = ({$random} % 3);
11390 if (mcu3_nb_crc_multiple_bit_times)
11391 mcu3_nb_bit_time_mask = $random;
11392 else begin
11393 mcu3_nb_random_bit_time = ({$random} % BIT_TIMES);
11394 mcu3_nb_bit_time_mask = mcu3_nb_bit_time_mask << mcu3_nb_random_bit_time;
11395 end
11396 if (mcu3_nb_crc_multiple_lanes)
11397 mcu3_nb_lane_mask = $random;
11398 else begin
11399 mcu3_nb_random_lane = ({$random} % NB_LANES);
11400 mcu3_nb_lane_mask = mcu3_nb_lane_mask << mcu3_nb_random_lane;
11401 end
11402 mcu3_nb_random_val = ({$random} % 100);
11403 if (!(mcu3_nb_random_val > MCU3_NB_RANDOM_WEIGHT)) mcu3_nb_err_enable=1;
11404 end
11405
11406
11407
11408 if ( !stop_mcu3_nb_mask && !($time < stop_mcu3_nb_crc_inj_time) && !(stop_mcu3_nb_crc_inj_time == 0) )
11409 begin
11410 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on NB channel for MCU3, time now is %d",$time);
11411 force mcu3_nb_err_enable=0;
11412 stop_mcu3_nb_mask = 1;
11413 end
11414 else if ( !restart_mcu3_nb_mask && !($time < restart_mcu3_nb_crc_inj_time) && !(restart_mcu3_nb_crc_inj_time == 0) && (restart_mcu3_nb_crc_inj_time > stop_mcu3_nb_crc_inj_time) )
11415 begin
11416 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on NB channel for MCU3, time now is %d",$time);
11417 release mcu3_nb_err_enable;
11418 restart_mcu3_nb_mask=1;
11419 end
11420 else if ( !restart_stop_mcu3_nb_mask && !($time < restart_stop_mcu3_nb_crc_inj_time) && !(restart_stop_mcu3_nb_crc_inj_time == 0) && (restart_stop_mcu3_nb_crc_inj_time > restart_mcu3_nb_crc_inj_time) )
11421 begin
11422 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on NB channel for MCU3, time now is %d",$time);
11423 force mcu3_nb_err_enable=0;
11424 restart_stop_mcu3_nb_mask=1;
11425 end
11426
11427
11428
11429 if ( ( $test$plusargs("INJECT_CRC_MCU3_NB_ERRQ") && (mcu3_nb_err < 8) && mcu3_nb_err_random ) &&
11430 ( `MCU3.drif.reqq.drq0.drq_rdq_full == 0 && `MCU3.drif.reqq.drq0.drq_wrq_full == 0 ) && // check both rd and wr queues on both channels are empty
11431 ( `MCU3.drif.reqq.drq1.drq_rdq_full == 0 && `MCU3.drif.reqq.drq1.drq_wrq_full == 0 ) &&
11432 ( `MCU3.drif.reqq.drq0.drq_empty == 1 && `MCU3.drif.reqq.drq1.drq_empty == 1 ) && // check channel 0/1 dram rd/wr queues
11433 ( `MCU3.drif.errq.errq_empty == 1 && `MCU3.drif.reqq.woq_err_fifo_empty == 1 ) && // check also dram rd/wr ecc/crc error fifo
11434`ifdef FC_CRC_INJECT
11435 passed_bootEnd_mask==1 &&
11436`endif
11437 ( mcu3_drif_dram_cmd_a==`RD ||
11438 (`MCU3.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
11439 (`MCU3.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
11440 (`MCU3.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
11441 `MCU3.fbdic.fbdic_scr_frame_req==1'b1) )
11442 begin
11443 force mcu3_nb_err_enable=0;
11444 inject_crc_mcu3_nb_errq_mask=1;
11445 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Injecting CRC errors on NB channel in MCU3 via RD/WR queue tracking, errq loop count is %d (max. allowed is 8)",mcu3_nb_err);
11446 end
11447
11448
11449 else if ( mcu3_nb_err_enable==1 && (mcu3_drif_dram_cmd_a==`RD ||
11450 (`MCU3.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
11451 (`MCU3.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
11452 (`MCU3.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
11453 (`MCU3.fbdic.fbdic_scr_frame_req==1'b1 )) &&
11454 (mcu3_nb_channel_error_cnt>0) &&
11455 (~mcu3_esr_fbu || mcu3_inject_fbu_err) &&
11456 (`MCU3.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
11457`ifdef FC_CRC_INJECT
11458 passed_bootEnd_mask==1 &&
11459 (!mcu3_esr_fbr && !mcu3_esr_fbu) &&
11460`endif
11461 (`MCU3.drif.drif_err_state == 5'h1 || mcu3_inject_fbu_err) )
11462 inject_crc_mcu3_nb_mask=1;
11463
11464
11465 if ( inject_crc_mcu3_nb_errq_mask==1 || (inject_crc_mcu3_nb_errq_mask==0 && inject_crc_mcu3_nb_mask==1 ) )
11466 begin
11467
11468
11469 if (mcu3_nb_err_random)
11470 repeat ((mcu3_chnl_lat-4)+mcu3_nb_random_cycle) @ (posedge drl2clk);
11471 else
11472 repeat ((mcu3_chnl_lat-4)+mcu3_nb_cycle_cnt) @ (posedge drl2clk);
11473
11474`ifdef NEC_FBDIMM
11475 repeat (6) @ (posedge sclk);
11476`else
11477 repeat (11) @ (posedge sclk);
11478`endif
11479
11480
11481
11482 mcu3_nb_err = mcu3_nb_err + 1;
11483 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU3: NB --- injecting CRC error no. %d", mcu3_nb_err);
11484
11485 if (mcu3_enable_ch0_err_inj) begin
11486 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_crc_freq = 12'h1;
11487 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_crc_period = 12'h1;
11488 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_frame_num = 12'h1;
11489
11490 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_crc_freq = 12'h1;
11491 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_crc_period = 12'h1;
11492 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_frame_num = 12'h1;
11493
11494 if (mcu3_nb_err_random) begin
11495 if (mcu3_nb_bit_time_mask[0]) begin
11496 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn0_crc_mask = mcu3_nb_lane_mask;
11497 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn0_crc_mask = mcu3_nb_lane_mask;
11498 end
11499 if (mcu3_nb_bit_time_mask[1]) begin
11500 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn1_crc_mask = mcu3_nb_lane_mask;
11501 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn1_crc_mask = mcu3_nb_lane_mask;
11502 end
11503 if (mcu3_nb_bit_time_mask[2]) begin
11504 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn2_crc_mask = mcu3_nb_lane_mask;
11505 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn2_crc_mask = mcu3_nb_lane_mask;
11506 end
11507 if (mcu3_nb_bit_time_mask[3]) begin
11508 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn3_crc_mask = mcu3_nb_lane_mask;
11509 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn3_crc_mask = mcu3_nb_lane_mask;
11510 end
11511 if (mcu3_nb_bit_time_mask[4]) begin
11512 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn4_crc_mask = mcu3_nb_lane_mask;
11513 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn4_crc_mask = mcu3_nb_lane_mask;
11514 end
11515 if (mcu3_nb_bit_time_mask[5]) begin
11516 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn5_crc_mask = mcu3_nb_lane_mask;
11517 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn5_crc_mask = mcu3_nb_lane_mask;
11518 end
11519 if (mcu3_nb_bit_time_mask[6]) begin
11520 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn6_crc_mask = mcu3_nb_lane_mask;
11521 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn6_crc_mask = mcu3_nb_lane_mask;
11522 end
11523 if (mcu3_nb_bit_time_mask[7]) begin
11524 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn7_crc_mask = mcu3_nb_lane_mask;
11525 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn7_crc_mask = mcu3_nb_lane_mask;
11526 end
11527 if (mcu3_nb_bit_time_mask[8]) begin
11528 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn8_crc_mask = mcu3_nb_lane_mask;
11529 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn8_crc_mask = mcu3_nb_lane_mask;
11530 end
11531 if (mcu3_nb_bit_time_mask[9]) begin
11532 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn9_crc_mask = mcu3_nb_lane_mask;
11533 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn9_crc_mask = mcu3_nb_lane_mask;
11534 end
11535 if (mcu3_nb_bit_time_mask[10]) begin
11536 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn10_crc_mask = mcu3_nb_lane_mask;
11537 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn10_crc_mask = mcu3_nb_lane_mask;
11538 end
11539 if (mcu3_nb_bit_time_mask[11]) begin
11540 force tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn11_crc_mask = mcu3_nb_lane_mask;
11541 force tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn11_crc_mask = mcu3_nb_lane_mask;
11542 end
11543 end
11544
11545 if (mcu3_inject_fbu_err && !mcu3_esr_fbu)
11546 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 NB - MCU3 (mcu3_nb_bit_time_mask[11:0] is %b, mcu3_nb_lane_mask[13:0] is %b)",mcu3_nb_bit_time_mask,mcu3_nb_lane_mask);
11547 else if (!mcu3_esr_fbr)
11548 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 NB - MCU3 (mcu3_nb_bit_time_mask[11:0] is %b, mcu3_nb_lane_mask[13:0] is %b)",mcu3_nb_bit_time_mask,mcu3_nb_lane_mask);
11549
11550 end
11551
11552 if (mcu3_enable_ch1_err_inj) begin
11553 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_crc_freq = 12'h1;
11554 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_crc_period = 12'h1;
11555 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_frame_num = 12'h1;
11556
11557 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_crc_freq = 12'h1;
11558 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_crc_period = 12'h1;
11559 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_frame_num = 12'h1;
11560
11561 if (mcu3_nb_err_random) begin
11562 if (mcu3_nb_bit_time_mask[0]) begin
11563 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn0_crc_mask = mcu3_nb_lane_mask;
11564 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn0_crc_mask = mcu3_nb_lane_mask;
11565 end
11566 if (mcu3_nb_bit_time_mask[1]) begin
11567 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn1_crc_mask = mcu3_nb_lane_mask;
11568 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn1_crc_mask = mcu3_nb_lane_mask;
11569 end
11570 if (mcu3_nb_bit_time_mask[2]) begin
11571 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn2_crc_mask = mcu3_nb_lane_mask;
11572 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn2_crc_mask = mcu3_nb_lane_mask;
11573 end
11574 if (mcu3_nb_bit_time_mask[3]) begin
11575 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn3_crc_mask = mcu3_nb_lane_mask;
11576 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn3_crc_mask = mcu3_nb_lane_mask;
11577 end
11578 if (mcu3_nb_bit_time_mask[4]) begin
11579 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn4_crc_mask = mcu3_nb_lane_mask;
11580 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn4_crc_mask = mcu3_nb_lane_mask;
11581 end
11582 if (mcu3_nb_bit_time_mask[5]) begin
11583 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn5_crc_mask = mcu3_nb_lane_mask;
11584 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn5_crc_mask = mcu3_nb_lane_mask;
11585 end
11586 if (mcu3_nb_bit_time_mask[6]) begin
11587 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn6_crc_mask = mcu3_nb_lane_mask;
11588 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn6_crc_mask = mcu3_nb_lane_mask;
11589 end
11590 if (mcu3_nb_bit_time_mask[7]) begin
11591 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn7_crc_mask = mcu3_nb_lane_mask;
11592 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn7_crc_mask = mcu3_nb_lane_mask;
11593 end
11594 if (mcu3_nb_bit_time_mask[8]) begin
11595 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn8_crc_mask = mcu3_nb_lane_mask;
11596 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn8_crc_mask = mcu3_nb_lane_mask;
11597 end
11598 if (mcu3_nb_bit_time_mask[9]) begin
11599 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn9_crc_mask = mcu3_nb_lane_mask;
11600 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn9_crc_mask = mcu3_nb_lane_mask;
11601 end
11602 if (mcu3_nb_bit_time_mask[10]) begin
11603 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn10_crc_mask = mcu3_nb_lane_mask;
11604 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn10_crc_mask = mcu3_nb_lane_mask;
11605 end
11606 if (mcu3_nb_bit_time_mask[11]) begin
11607 force tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn11_crc_mask = mcu3_nb_lane_mask;
11608 force tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn11_crc_mask = mcu3_nb_lane_mask;
11609 end
11610 end
11611
11612 if (mcu3_inject_fbu_err && !mcu3_esr_fbu)
11613 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 NB - MCU3 (mcu3_nb_bit_time_mask[11:0] is %b, mcu3_nb_lane_mask[13:0] is %b)",mcu3_nb_bit_time_mask,mcu3_nb_lane_mask);
11614 else if (!mcu3_esr_fbr)
11615 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 NB - MCU3 (mcu3_nb_bit_time_mask[11:0] is %b, mcu3_nb_lane_mask[13:0] is %b)",mcu3_nb_bit_time_mask,mcu3_nb_lane_mask);
11616
11617 end
11618
11619 repeat (1) @ (posedge sclk);
11620
11621 release tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_crc_freq;
11622 release tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_crc_period;
11623 release tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_frame_num;
11624
11625 release tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_crc_freq;
11626 release tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_crc_period;
11627 release tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_frame_num;
11628
11629 release tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_crc_freq;
11630 release tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_crc_period;
11631 release tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_frame_num;
11632
11633 release tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_crc_freq;
11634 release tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_crc_period;
11635 release tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_frame_num;
11636
11637 inject_crc_mcu3_nb_mask=0;
11638 if (mcu3_nb_err_random==0)
11639 mcu3_nb_channel_error_cnt=mcu3_nb_channel_error_cnt - 1;
11640 else begin
11641 mcu3_nb_err_enable = 0;
11642 mcu3_nb_lane_mask = 14'h1;
11643 mcu3_nb_bit_time_mask = 12'h1;
11644 end
11645 end
11646end
11647end
11648
11649
11650//Error Injection in Training Seq
11651
11652// --- MCU0 ---
11653
11654
11655always @(fbdic_fbd_state_0)
11656begin
11657mcu0_sb_channel_error_cnt_tmp = mcu0_sb_channel_error_cnt;
11658end
11659
11660// If an error is detected and MCU went to disable state, stop the error
11661// injection
11662always @(posedge drl2clk)
11663begin
11664
11665 if ((mcu0_fbdic_tclktrain_done[1] == 1'b1)||
11666 (mcu0_fbdic_testing_done[1] == 1'b1) ||
11667 (mcu0_fbdic_polling_done[1] == 1'b1))
11668 begin
11669 repeat (50) @(posedge drl2clk);
11670 if(fbdic_fbd_state_0 == 0)
11671 begin
11672 mcu0_training_err_enable = 0;
11673 `PR_DEBUG("mcu_fmon",`DEBUG," DISABLED Err INJECTION IN TRAINING SEQUENCE");
11674 end
11675 end
11676
11677
11678end
11679
11680
11681always @(posedge drl2clk)
11682begin
11683
11684@(posedge drl2clk);
11685
11686 if ((mcu0_training_err_enable == 1) &&
11687 (fbdic_fbd_state_0 == 2 || fbdic_fbd_state_0 == 3 ||
11688 fbdic_fbd_state_0 == 4 || fbdic_fbd_state_0 == 5) &&
11689 ( mcu0_sb_channel_error_cnt_tmp>0 ) )
11690 begin
11691
11692 if( fbdic_fbd_state_0 == 2 )
11693 begin
11694 repeat (100) @(posedge drl2clk);
11695 end
11696 else
11697 begin
11698 repeat (30) @(posedge drl2clk);
11699 end
11700
11701 `PR_DEBUG("mcu_fmon",`DEBUG," Entered Err Injection in TRAINING SEQUENCE SB Channel");
11702
11703 if (mcu0_enable_ch0_err_inj)
11704 begin
11705 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq = 12'h1;
11706 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period = 12'h1;
11707 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num = 12'h1;
11708
11709 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq = 12'h1;
11710 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period = 12'h1;
11711 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num = 12'h1;
11712 end
11713
11714 if (mcu0_enable_ch1_err_inj)
11715 begin
11716 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq = 12'h1;
11717 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period = 12'h1;
11718 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num = 12'h1;
11719
11720 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq = 12'h1;
11721 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period = 12'h1;
11722 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num = 12'h1;
11723 end
11724
11725 repeat (1) @ (posedge sclk);
11726
11727 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq;
11728 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period;
11729 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num;
11730
11731 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq;
11732 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period;
11733 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num;
11734
11735 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq;
11736 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period;
11737 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num;
11738
11739 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq;
11740 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period;
11741 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num;
11742
11743 mcu0_sb_channel_error_cnt_tmp = mcu0_sb_channel_error_cnt_tmp - 1;
11744
11745 repeat (3) @ (posedge sclk);
11746 end // if (mcu0_training_err_enable ..
11747end
11748
11749
11750//------------------------------------------------
11751// SB CRC - Corrupt SB CMD/Data Frame Mechanism
11752//------------------------------------------------
11753
11754
11755`ifdef FC_CRC_INJECT
11756reg [119:0] corrupted_mcu0_sb_mcu0_fsr0_data;
11757integer mcu0_sb_quadword=1;
11758initial begin
11759if ($value$plusargs("MCU0_SB_QUADWORD=%d",mcu0_sb_quadword)) begin
11760 if ( (mcu0_sb_quadword<1) || (mcu0_sb_quadword>4) ) `PR_ERROR ("mcu_fmon", `ERROR, "can only specify 1,2,3 or 4!");
11761 else `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: will inject CRC error on MCU0 SB quadword %d",mcu0_sb_quadword);
11762 end
11763end
11764`endif
11765
11766function [119:0] return_120_bits_sb_mask;
11767input[11:0] mcu0_sb_bit_time_mask;
11768input[9:0] mcu0_sb_lane_mask;
11769begin
11770 return_120_bits_sb_mask=120'b0;
11771 if (mcu0_sb_bit_time_mask[0] ==1) return_120_bits_sb_mask[9:0] = mcu0_sb_lane_mask[9:0];
11772 if (mcu0_sb_bit_time_mask[1] ==1) return_120_bits_sb_mask[19:10] = mcu0_sb_lane_mask[9:0];
11773 if (mcu0_sb_bit_time_mask[2] ==1) return_120_bits_sb_mask[29:20] = mcu0_sb_lane_mask[9:0];
11774 if (mcu0_sb_bit_time_mask[3] ==1) return_120_bits_sb_mask[39:30] = mcu0_sb_lane_mask[9:0];
11775 if (mcu0_sb_bit_time_mask[4] ==1) return_120_bits_sb_mask[49:40] = mcu0_sb_lane_mask[9:0];
11776 if (mcu0_sb_bit_time_mask[5] ==1) return_120_bits_sb_mask[59:50] = mcu0_sb_lane_mask[9:0];
11777 if (mcu0_sb_bit_time_mask[6] ==1) return_120_bits_sb_mask[69:60] = mcu0_sb_lane_mask[9:0];
11778 if (mcu0_sb_bit_time_mask[7] ==1) return_120_bits_sb_mask[79:70] = mcu0_sb_lane_mask[9:0];
11779 if (mcu0_sb_bit_time_mask[8] ==1) return_120_bits_sb_mask[89:80] = mcu0_sb_lane_mask[9:0];
11780 if (mcu0_sb_bit_time_mask[9] ==1) return_120_bits_sb_mask[99:90] = mcu0_sb_lane_mask[9:0];
11781 if (mcu0_sb_bit_time_mask[10]==1) return_120_bits_sb_mask[109:100] = mcu0_sb_lane_mask[9:0];
11782 if (mcu0_sb_bit_time_mask[11]==1) return_120_bits_sb_mask[119:110] = mcu0_sb_lane_mask[9:0];
11783end
11784endfunction
11785
11786reg [119:0] mcu0_sb_data_array_QW1 [0:`MAX_CRC_ERRORS-1];
11787reg [119:0] mcu0_sb_data_array_QW2 [0:`MAX_CRC_ERRORS-1];
11788reg [119:0] mcu0_sb_data_array_QW3 [0:`MAX_CRC_ERRORS-1];
11789reg [119:0] mcu0_sb_data_array_QW4 [0:`MAX_CRC_ERRORS-1];
11790integer mcu0_sb_data_array_QW1_cnt [0:`MAX_CRC_ERRORS-1];
11791integer mcu0_sb_data_array_QW2_cnt [0:`MAX_CRC_ERRORS-1];
11792integer mcu0_sb_data_array_QW3_cnt [0:`MAX_CRC_ERRORS-1];
11793integer mcu0_sb_data_array_QW4_cnt [0:`MAX_CRC_ERRORS-1];
11794
11795integer S=0;
11796reg trigger_SB=0;
11797
11798always @ (
11799`ifdef FC_CRC_INJECT // for fullchip, pick only valid write packets
11800 `MCU0.drif.drif_dram_cmd_b[2:0]
11801`else //for MCUSAT
11802 mcu0_drif_dram_cmd_a or
11803 mcu0_drif_dram_cmd_b or
11804 mcu0_drif_dram_cmd_c or
11805 `MCU0.fbdic.fbdic_config_reg_write or
11806 `MCU0.fbdic.fbdic_config_reg_read or
11807 `MCU0.fbdic.fbdic_scr_frame_req or
11808 `MCU0.fbdic.fbdic_sync_frame_req or
11809 `MCU0.fbdic.fbdic_issue_pre_all_cmd or
11810 `MCU0.fbdic.fbdic_issue_cke_cmd
11811`endif
11812)
11813begin
11814if (enabled && ~ras_corner_case)
11815begin
11816`ifdef FC_CRC_INJECT
11817if ( passed_bootEnd_mask==1 && `MCU0.drif.drif_dram_cmd_b[2:0]==3'h5 // currently injecting only on writes only
11818 && !mcu0_esr_fbr && !mcu0_esr_fbu)
11819begin
11820S=S+1;
11821`endif
11822
11823 // --------- Random SB CRC Err Injection --------
11824 if (mcu0_sb_err_random) begin
11825
11826 if (mcu0_sb_crc_multiple_bit_times) begin
11827 mcu0_sb_bit_time_mask = ({$random} % 4095); // pick multiple bit times
11828 while (mcu0_sb_bit_time_mask==0) mcu0_sb_bit_time_mask = ({$random} % 4095);
11829`ifdef FC_CRC_INJECT
11830 mcu0_sb_bit_time_mask = mcu0_sb_bit_time_mask & 12'hFF0; //pick bit times 5 thru 12
11831`endif
11832 end
11833 else begin // pick any 1 random bit time
11834 mcu0_sb_bit_time_mask=1;
11835`ifdef MCUSAT
11836 mcu0_sb_random_bit_time = ({$random} % BIT_TIMES);
11837 while (mcu0_sb_random_bit_time==0) mcu0_sb_random_bit_time = ({$random} % BIT_TIMES);
11838 mcu0_sb_bit_time_mask = mcu0_sb_bit_time_mask << mcu0_sb_random_bit_time;
11839`else
11840 mcu0_sb_random_bit_time = ({$random} % 8); // for now within FC, pick one of bit times 5 thru 12
11841 mcu0_sb_bit_time_mask = mcu0_sb_bit_time_mask << (mcu0_sb_random_bit_time+4);
11842`endif
11843 end
11844
11845 if (mcu0_sb_crc_multiple_lanes) begin
11846 mcu0_sb_lane_mask = ({$random} % 1023); // pick multiple lanes
11847 while (mcu0_sb_lane_mask==0) mcu0_sb_lane_mask = ({$random} % 1023);
11848 end
11849 else begin // pick any 1 random lane
11850 mcu0_sb_lane_mask=1;
11851 mcu0_sb_random_lane = ({$random} % SB_LANES);
11852 while (mcu0_sb_random_lane==0) mcu0_sb_random_lane = ({$random} % SB_LANES);
11853 mcu0_sb_lane_mask = mcu0_sb_lane_mask << mcu0_sb_random_lane;
11854 end
11855`ifdef MCUSAT
11856 mcu0_sb_random_cycle = ({$random} % 3);
11857 mcu0_sb_random_val = ({$random} % 100);
11858 if (!(mcu0_sb_random_val > MCU0_SB_RANDOM_WEIGHT)) mcu0_sb_err_enable=1;
11859`else
11860 mcu0_sb_err_enable=1;
11861`endif
11862 end //if (mcu0_sb_err_random)
11863
11864`ifdef FC_CRC_INJECT
11865 else if (mcu0_sb_err_enable) begin
11866 mcu0_sb_bit_time_mask=12'h010; // for FC, pick only the 5th bit time
11867 mcu0_sb_lane_mask=10'h200;
11868 end
11869`endif
11870
11871
11872 if ( !stop_mcu0_sb_mask && !($time < stop_mcu0_sb_crc_inj_time) && !(stop_mcu0_sb_crc_inj_time == 0) )
11873 begin
11874 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on SB channel for MCU0, time now is %d",$time);
11875 force mcu0_sb_err_enable=0;
11876 stop_mcu0_sb_mask = 1;
11877 end
11878 else if ( !restart_mcu0_sb_mask && !($time < restart_mcu0_sb_crc_inj_time) && !(restart_mcu0_sb_crc_inj_time == 0) && (restart_mcu0_sb_crc_inj_time > stop_mcu0_sb_crc_inj_time) )
11879 begin
11880 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on SB channel for MCU0, time now is %d",$time);
11881 release mcu0_sb_err_enable;
11882 restart_mcu0_sb_mask=1;
11883 end
11884 else if ( !restart_stop_mcu0_sb_mask && !($time < restart_stop_mcu0_sb_crc_inj_time) && !(restart_stop_mcu0_sb_crc_inj_time == 0) && (restart_stop_mcu0_sb_crc_inj_time > restart_mcu0_sb_crc_inj_time) )
11885 begin
11886 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on SB channel for MCU0, time now is %d",$time);
11887 force mcu0_sb_err_enable=0;
11888 restart_stop_mcu0_sb_mask=1;
11889 end
11890
11891// code for fullchip crc injection on both NB and SB has been completely changed
11892// 11/02/2006
11893`ifdef FC_CRC_INJECT
11894 if (mcu0_sb_err_enable==1) begin
11895 trigger_SB=1;
11896 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: CRC SB masks : mcu0_sb_bit_time_mask[11:0] is %b, mcu0_sb_lane_mask[9:0] is %b",mcu0_sb_bit_time_mask,mcu0_sb_lane_mask);
11897
11898 repeat (2) @(posedge drl2clk); // always has a delay of 2 cycles
11899
11900 found=0; i=0; j=-1;
11901 for (i=0; i<`MAX_CRC_ERRORS; i=i+1)
11902 begin
11903 if (mcu0_sb_data_array_QW1[i][119:0]==`MCU0.mcu_fsr0_data[119:0] && found==0 && mcu0_sb_quadword==1)
11904 begin found=1; j=i; end
11905 if ( found==0 && !(mcu0_sb_data_array_QW1[i][119:0]===120'bx) && mcu0_sb_quadword==1)
11906 j=i;
11907 end
11908 if (found==0 && (S%delay_crc==1))
11909 begin
11910 if (mcu0_sb_quadword==1) begin
11911 mcu0_sb_data_array_QW1[j+1][119:0]=`MCU0.mcu_fsr0_data[119:0];
11912 if (mcu0_inject_fbu_err==1)
11913 mcu0_sb_data_array_QW1_cnt[j+1]=3;
11914 else
11915 mcu0_sb_data_array_QW1_cnt[j+1]=1;
11916 end
11917 end
11918
11919 if ( (mcu0_inject_fbu_err==1 && found==1 && mcu0_sb_quadword==1 && mcu0_sb_data_array_QW1_cnt[j]>0) ||
11920 (found==0 && mcu0_sb_quadword==1 && mcu0_sb_data_array_QW1_cnt[j+1]>0) ) begin
11921 SBQW1=1;
11922
11923 if (mcu0_sb_quadword==1) begin
11924 corrupted_mcu0_sb_mcu0_fsr0_data[119:0] = `MCU0.mcu_fsr0_data[119:0] ^ ( return_120_bits_sb_mask ( mcu0_sb_bit_time_mask, mcu0_sb_lane_mask ) ) ;
11925 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 SB QW1: orig. fsr0 data [119:0] was %x, modif. fsr0 data [119:0] is %x",`MCU0.mcu_fsr0_data[119:0], corrupted_mcu0_sb_mcu0_fsr0_data[119:0]);
11926 force `MCU0.mcu_fsr0_data[119:0] = corrupted_mcu0_sb_mcu0_fsr0_data[119:0];
11927 @(posedge drl2clk);
11928 release `MCU0.mcu_fsr0_data[119:0];
11929 end
11930 end
11931
11932 @(posedge drl2clk);
11933
11934 found=0; i=0; j=-1;
11935 for (i=0; i<`MAX_CRC_ERRORS; i=i+1)
11936 begin
11937 if (mcu0_sb_data_array_QW2[i][119:0]==`MCU0.mcu_fsr0_data[119:0] && found==0 && mcu0_sb_quadword==2)
11938 begin found=1; j=i; end
11939 if ( found==0 && !(mcu0_sb_data_array_QW2[i][119:0]===120'bx) && mcu0_sb_quadword==2)
11940 j=i;
11941 end
11942 if (found==0 && (S%delay_crc==1))
11943 begin
11944 if (mcu0_sb_quadword==2) begin
11945 mcu0_sb_data_array_QW2[j+1][119:0]=`MCU0.mcu_fsr0_data[119:0];
11946 if (mcu0_inject_fbu_err==1)
11947 mcu0_sb_data_array_QW2_cnt[j+1]=3;
11948 else
11949 mcu0_sb_data_array_QW2_cnt[j+1]=1;
11950 end
11951 end
11952
11953 if ( (mcu0_inject_fbu_err==1 && found==1 && mcu0_sb_quadword==2 && mcu0_sb_data_array_QW2_cnt[j]>0) ||
11954 (found==0 && mcu0_sb_quadword==2 && mcu0_sb_data_array_QW2_cnt[j+1]>0) ) begin
11955 SBQW2=1;
11956
11957 if (mcu0_sb_quadword==2) begin
11958 corrupted_mcu0_sb_mcu0_fsr0_data[119:0] = `MCU0.mcu_fsr0_data[119:0] ^ ( return_120_bits_sb_mask ( mcu0_sb_bit_time_mask, mcu0_sb_lane_mask ) ) ;
11959 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 SB QW2: orig. fsr0 data [119:0] was %x, modif. fsr0 data [119:0] is %x",`MCU0.mcu_fsr0_data[119:0], corrupted_mcu0_sb_mcu0_fsr0_data[119:0]);
11960 force `MCU0.mcu_fsr0_data[119:0] = corrupted_mcu0_sb_mcu0_fsr0_data[119:0];
11961 @(posedge drl2clk);
11962 release `MCU0.mcu_fsr0_data[119:0];
11963 end
11964 end
11965
11966 @(posedge drl2clk);
11967
11968 found=0; i=0; j=-1;
11969 for (i=0; i<`MAX_CRC_ERRORS; i=i+1)
11970 begin
11971 if (mcu0_sb_data_array_QW3[i][119:0]==`MCU0.mcu_fsr0_data[119:0] && found==0 && mcu0_sb_quadword==3)
11972 begin found=1; j=i; end
11973 if ( found==0 && !(mcu0_sb_data_array_QW3[i][119:0]===120'bx) && mcu0_sb_quadword==3)
11974 j=i;
11975 end
11976 if (found==0 && (S%delay_crc==1))
11977 begin
11978 if (mcu0_sb_quadword==3) begin
11979 mcu0_sb_data_array_QW3[j+1][119:0]=`MCU0.mcu_fsr0_data[119:0];
11980 if (mcu0_inject_fbu_err==1)
11981 mcu0_sb_data_array_QW3_cnt[j+1]=3;
11982 else
11983 mcu0_sb_data_array_QW3_cnt[j+1]=1;
11984 end
11985 end
11986
11987 if ( (mcu0_inject_fbu_err==1 && found==1 && mcu0_sb_quadword==3 && mcu0_sb_data_array_QW3_cnt[j]>0) ||
11988 (found==0 && mcu0_sb_quadword==3 && mcu0_sb_data_array_QW3_cnt[j+1]>0) ) begin
11989 SBQW3=1;
11990
11991 if (mcu0_sb_quadword==3) begin
11992 corrupted_mcu0_sb_mcu0_fsr0_data[119:0] = `MCU0.mcu_fsr0_data[119:0] ^ ( return_120_bits_sb_mask ( mcu0_sb_bit_time_mask, mcu0_sb_lane_mask ) ) ;
11993 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 SB QW3: orig. fsr0 data [119:0] was %x, modif. fsr0 data [119:0] is %x",`MCU0.mcu_fsr0_data[119:0], corrupted_mcu0_sb_mcu0_fsr0_data[119:0]);
11994 force `MCU0.mcu_fsr0_data[119:0] = corrupted_mcu0_sb_mcu0_fsr0_data[119:0];
11995 @(posedge drl2clk);
11996 release `MCU0.mcu_fsr0_data[119:0];
11997 end
11998 end
11999
12000 @(posedge drl2clk);
12001
12002 found=0; i=0; j=-1;
12003 for (i=0; i<`MAX_CRC_ERRORS; i=i+1)
12004 begin
12005 if (mcu0_sb_data_array_QW4[i][119:0]==`MCU0.mcu_fsr0_data[119:0] && found==0 && mcu0_sb_quadword==4)
12006 begin found=1; j=i; end
12007 if ( found==0 && !(mcu0_sb_data_array_QW4[i][119:0]===120'bx) && mcu0_sb_quadword==4)
12008 j=i;
12009 end
12010 if (found==0 && (S%delay_crc==1))
12011 begin
12012 if (mcu0_sb_quadword==4) begin
12013 mcu0_sb_data_array_QW4[j+1][119:0]=`MCU0.mcu_fsr0_data[119:0];
12014 if (mcu0_inject_fbu_err==1)
12015 mcu0_sb_data_array_QW4_cnt[j+1]=3;
12016 else
12017 mcu0_sb_data_array_QW4_cnt[j+1]=1;
12018 end
12019 end
12020
12021 if ( (mcu0_inject_fbu_err==1 && found==1 && mcu0_sb_quadword==4 && mcu0_sb_data_array_QW4_cnt[j]>0) ||
12022 (found==0 && mcu0_sb_quadword==4 && mcu0_sb_data_array_QW4_cnt[j+1]>0) ) begin
12023 SBQW4=1;
12024
12025 if (mcu0_sb_quadword==4) begin
12026 corrupted_mcu0_sb_mcu0_fsr0_data[119:0] = `MCU0.mcu_fsr0_data[119:0] ^ ( return_120_bits_sb_mask ( mcu0_sb_bit_time_mask, mcu0_sb_lane_mask ) ) ;
12027 `PR_ALWAYS ("mcu_fmon", `ALWAYS, "INFO: MCU0 SB QW4: orig. fsr0 data [119:0] was %x, modif. fsr0 data [119:0] is %x",`MCU0.mcu_fsr0_data[119:0], corrupted_mcu0_sb_mcu0_fsr0_data[119:0]);
12028 force `MCU0.mcu_fsr0_data[119:0] = corrupted_mcu0_sb_mcu0_fsr0_data[119:0];
12029 @(posedge drl2clk);
12030 release `MCU0.mcu_fsr0_data[119:0];
12031 end
12032 end
12033
12034 if (found==0) begin
12035 if (mcu0_sb_quadword==1 && mcu0_sb_data_array_QW1_cnt[j+1]>0) mcu0_sb_data_array_QW1_cnt[j+1]=mcu0_sb_data_array_QW1_cnt[j+1]-1;
12036 if (mcu0_sb_quadword==2 && mcu0_sb_data_array_QW2_cnt[j+1]>0) mcu0_sb_data_array_QW2_cnt[j+1]=mcu0_sb_data_array_QW2_cnt[j+1]-1;
12037 if (mcu0_sb_quadword==3 && mcu0_sb_data_array_QW3_cnt[j+1]>0) mcu0_sb_data_array_QW3_cnt[j+1]=mcu0_sb_data_array_QW3_cnt[j+1]-1;
12038 if (mcu0_sb_quadword==4 && mcu0_sb_data_array_QW4_cnt[j+1]>0) mcu0_sb_data_array_QW4_cnt[j+1]=mcu0_sb_data_array_QW4_cnt[j+1]-1;
12039 end
12040 else begin
12041 if (mcu0_sb_quadword==1 && mcu0_sb_data_array_QW1_cnt[j]>0) mcu0_sb_data_array_QW1_cnt[j]=mcu0_sb_data_array_QW1_cnt[j]-1;
12042 if (mcu0_sb_quadword==2 && mcu0_sb_data_array_QW2_cnt[j]>0) mcu0_sb_data_array_QW2_cnt[j]=mcu0_sb_data_array_QW2_cnt[j]-1;
12043 if (mcu0_sb_quadword==3 && mcu0_sb_data_array_QW3_cnt[j]>0) mcu0_sb_data_array_QW3_cnt[j]=mcu0_sb_data_array_QW3_cnt[j]-1;
12044 if (mcu0_sb_quadword==4 && mcu0_sb_data_array_QW4_cnt[j]>0) mcu0_sb_data_array_QW4_cnt[j]=mcu0_sb_data_array_QW4_cnt[j]-1;
12045 end
12046 end
12047 SBQW1=0; SBQW2=0; SBQW3=0; SBQW4=0;
12048 trigger_SB=0;
12049
12050`ifdef FC_CRC_INJECT
12051end
12052`endif
12053
12054`else //mcusat
12055 if ( mcu0_sb_err_enable==1 &&
12056 (!mcu0_esr_fbr && !mcu0_esr_fbu) && (~mcu0_esr_fbu || mcu0_inject_fbu_err) &&
12057 ((`MCU0.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
12058 (`MCU0.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
12059 (`MCU0.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
12060 `MCU0.fbdic.fbdic_scr_frame_req==1'b1 ||
12061 `MCU0.fbdic.fbdic_issue_pre_all_cmd ||
12062 `MCU0.fbdic.fbdic_issue_cke_cmd ||
12063 mcu0_drif_dram_cmd_a==`ACT ||
12064 mcu0_drif_dram_cmd_a==`WR ||
12065 mcu0_drif_dram_cmd_a==`RD ||
12066 mcu0_drif_dram_cmd_b==`ACT ||
12067 mcu0_drif_dram_cmd_b==`WR ||
12068 mcu0_drif_dram_cmd_b==`WRDATA ||
12069 (mcu0_drif_dram_cmd_b==`CMD_OTHER && mcu0_drif_dram_addr_b == `CMD_OTHER_REF) ||
12070 (mcu0_drif_dram_cmd_c==`CMD_OTHER && mcu0_drif_dram_addr_c == `CMD_OTHER_PDE) ||
12071 (mcu0_drif_dram_cmd_c==`CMD_OTHER && mcu0_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
12072 mcu0_drif_dram_cmd_c==`ACT ||
12073 mcu0_drif_dram_cmd_c==`WR) &&
12074 (`MCU0.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
12075 (mcu0_sb_channel_error_cnt>0) &&
12076 (`MCU0.drif.drif_err_state == 5'h1 || mcu0_inject_fbu_err))
12077 begin
12078
12079 if (mcu0_sb_err_random)
12080 repeat (3+mcu0_sb_random_cycle) @ (posedge drl2clk);
12081 else
12082 repeat (3) @ (posedge drl2clk);
12083 repeat (10) @ (posedge sclk);
12084
12085
12086 if (mcu0_enable_ch0_err_inj) begin
12087 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq = 12'h1;
12088 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period = 12'h1;
12089 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num = 12'h1;
12090
12091 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq = 12'h1;
12092 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period = 12'h1;
12093 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num = 12'h1;
12094
12095 if (mcu0_sb_err_random) begin
12096 if (mcu0_sb_bit_time_mask[0]) begin
12097 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps0_crc_mask = mcu0_sb_lane_mask;
12098 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps0_crc_mask = mcu0_sb_lane_mask;
12099 end
12100 if (mcu0_sb_bit_time_mask[1]) begin
12101 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps1_crc_mask = mcu0_sb_lane_mask;
12102 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps1_crc_mask = mcu0_sb_lane_mask;
12103 end
12104 if (mcu0_sb_bit_time_mask[2]) begin
12105 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps2_crc_mask = mcu0_sb_lane_mask;
12106 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps2_crc_mask = mcu0_sb_lane_mask;
12107 end
12108 if (mcu0_sb_bit_time_mask[3]) begin
12109 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps3_crc_mask = mcu0_sb_lane_mask;
12110 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps3_crc_mask = mcu0_sb_lane_mask;
12111 end
12112 if (mcu0_sb_bit_time_mask[4]) begin
12113 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps4_crc_mask = mcu0_sb_lane_mask;
12114 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps4_crc_mask = mcu0_sb_lane_mask;
12115 end
12116 if (mcu0_sb_bit_time_mask[5]) begin
12117 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps5_crc_mask = mcu0_sb_lane_mask;
12118 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps5_crc_mask = mcu0_sb_lane_mask;
12119 end
12120 if (mcu0_sb_bit_time_mask[6]) begin
12121 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps6_crc_mask = mcu0_sb_lane_mask;
12122 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps6_crc_mask = mcu0_sb_lane_mask;
12123 end
12124 if (mcu0_sb_bit_time_mask[7]) begin
12125 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps7_crc_mask = mcu0_sb_lane_mask;
12126 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps7_crc_mask = mcu0_sb_lane_mask;
12127 end
12128 if (mcu0_sb_bit_time_mask[8]) begin
12129 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps8_crc_mask = mcu0_sb_lane_mask;
12130 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps8_crc_mask = mcu0_sb_lane_mask;
12131 end
12132 if (mcu0_sb_bit_time_mask[9]) begin
12133 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps9_crc_mask = mcu0_sb_lane_mask;
12134 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps9_crc_mask = mcu0_sb_lane_mask;
12135 end
12136 if (mcu0_sb_bit_time_mask[10]) begin
12137 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps10_crc_mask = mcu0_sb_lane_mask;
12138 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps10_crc_mask = mcu0_sb_lane_mask;
12139 end
12140 if (mcu0_sb_bit_time_mask[11]) begin
12141 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps11_crc_mask = mcu0_sb_lane_mask;
12142 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps11_crc_mask = mcu0_sb_lane_mask;
12143 end
12144 end
12145
12146 if (mcu0_inject_fbu_err && !mcu0_esr_fbu)
12147 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 SB - MCU0 (mcu0_sb_bit_time_mask[11:0] is %b, mcu0_sb_lane_mask[9:0] is %b)",mcu0_sb_bit_time_mask,mcu0_sb_lane_mask);
12148 else if (!mcu0_esr_fbr)
12149 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 SB - MCU0 (mcu0_sb_bit_time_mask[11:0] is %b, mcu0_sb_lane_mask[9:0] is %b)",mcu0_sb_bit_time_mask,mcu0_sb_lane_mask);
12150
12151 end
12152
12153 if (mcu0_enable_ch1_err_inj) begin
12154 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq = 12'h1;
12155 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period = 12'h1;
12156 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num = 12'h1;
12157
12158 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq = 12'h1;
12159 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period = 12'h1;
12160 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num = 12'h1;
12161
12162 if (mcu0_sb_err_random) begin
12163 if (mcu0_sb_bit_time_mask[0]) begin
12164 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps0_crc_mask = mcu0_sb_lane_mask;
12165 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps0_crc_mask = mcu0_sb_lane_mask;
12166 end
12167 if (mcu0_sb_bit_time_mask[1]) begin
12168 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps1_crc_mask = mcu0_sb_lane_mask;
12169 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps1_crc_mask = mcu0_sb_lane_mask;
12170 end
12171 if (mcu0_sb_bit_time_mask[2]) begin
12172 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps2_crc_mask = mcu0_sb_lane_mask;
12173 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps2_crc_mask = mcu0_sb_lane_mask;
12174 end
12175 if (mcu0_sb_bit_time_mask[3]) begin
12176 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps3_crc_mask = mcu0_sb_lane_mask;
12177 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps3_crc_mask = mcu0_sb_lane_mask;
12178 end
12179 if (mcu0_sb_bit_time_mask[4]) begin
12180 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps4_crc_mask = mcu0_sb_lane_mask;
12181 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps4_crc_mask = mcu0_sb_lane_mask;
12182 end
12183 if (mcu0_sb_bit_time_mask[5]) begin
12184 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps5_crc_mask = mcu0_sb_lane_mask;
12185 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps5_crc_mask = mcu0_sb_lane_mask;
12186 end
12187 if (mcu0_sb_bit_time_mask[6]) begin
12188 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps6_crc_mask = mcu0_sb_lane_mask;
12189 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps6_crc_mask = mcu0_sb_lane_mask;
12190 end
12191 if (mcu0_sb_bit_time_mask[7]) begin
12192 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps7_crc_mask = mcu0_sb_lane_mask;
12193 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps7_crc_mask = mcu0_sb_lane_mask;
12194 end
12195 if (mcu0_sb_bit_time_mask[8]) begin
12196 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps8_crc_mask = mcu0_sb_lane_mask;
12197 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps8_crc_mask = mcu0_sb_lane_mask;
12198 end
12199 if (mcu0_sb_bit_time_mask[9]) begin
12200 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps9_crc_mask = mcu0_sb_lane_mask;
12201 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps9_crc_mask = mcu0_sb_lane_mask;
12202 end
12203 if (mcu0_sb_bit_time_mask[10]) begin
12204 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps10_crc_mask = mcu0_sb_lane_mask;
12205 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps10_crc_mask = mcu0_sb_lane_mask;
12206 end
12207 if (mcu0_sb_bit_time_mask[11]) begin
12208 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps11_crc_mask = mcu0_sb_lane_mask;
12209 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps11_crc_mask = mcu0_sb_lane_mask;
12210 end
12211 end
12212
12213 if (mcu0_inject_fbu_err && !mcu0_esr_fbu)
12214 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 SB - MCU0 (mcu0_sb_bit_time_mask[11:0] is %b, mcu0_sb_lane_mask[9:0] is %b)",mcu0_sb_bit_time_mask,mcu0_sb_lane_mask);
12215 else if (!mcu0_esr_fbr)
12216 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 SB - MCU0 (mcu0_sb_bit_time_mask[11:0] is %b, mcu0_sb_lane_mask[9:0] is %b)",mcu0_sb_bit_time_mask,mcu0_sb_lane_mask);
12217
12218 end
12219
12220 repeat (1) @ (posedge sclk);
12221
12222 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq;
12223 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period;
12224 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num;
12225
12226 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq;
12227 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period;
12228 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num;
12229
12230 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq;
12231 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period;
12232 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num;
12233
12234 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq;
12235 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period;
12236 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num;
12237
12238 if (mcu0_sb_err_random==0)
12239 mcu0_sb_channel_error_cnt=mcu0_sb_channel_error_cnt - 1;
12240 else begin
12241 mcu0_sb_err_enable = 0;
12242 mcu0_sb_lane_mask = 10'h1;
12243 mcu0_sb_bit_time_mask = 12'h1;
12244 end
12245 end
12246`endif
12247end
12248
12249end
12250
12251// --- MCU1 ---
12252
12253always @(fbdic_fbd_state_1)
12254begin
12255mcu1_sb_channel_error_cnt_tmp = mcu1_sb_channel_error_cnt;
12256end
12257
12258// If an error is detected and MCU went to disable state, stop the error
12259// injection
12260always @(posedge drl2clk)
12261begin
12262
12263 if ((mcu1_fbdic_tclktrain_done[1] == 1'b1)||
12264 (mcu1_fbdic_testing_done[1] == 1'b1) ||
12265 (mcu1_fbdic_polling_done[1] == 1'b1))
12266 begin
12267 repeat (50) @(posedge drl2clk);
12268 if(fbdic_fbd_state_1 == 0)
12269 begin
12270 mcu1_training_err_enable = 0;
12271 `PR_DEBUG("mcu_fmon",`DEBUG," DISABLED Err INJECTION IN TRAINING SEQUENCE");
12272 end
12273 end
12274
12275
12276end
12277
12278always @(posedge drl2clk)
12279begin
12280
12281@(posedge drl2clk);
12282
12283 if ((mcu1_training_err_enable == 1) &&
12284 (fbdic_fbd_state_1 == 2 || fbdic_fbd_state_1 == 3 ||
12285 fbdic_fbd_state_1 == 4 || fbdic_fbd_state_1 == 5) &&
12286 ( mcu1_sb_channel_error_cnt_tmp>0 ) )
12287 begin
12288
12289 if( fbdic_fbd_state_1 == 2 )
12290 begin
12291 repeat (100) @(posedge drl2clk);
12292 end
12293 else
12294 begin
12295 repeat (30) @(posedge drl2clk);
12296 end
12297
12298 `PR_DEBUG("mcu_fmon",`DEBUG," Entered Err Injection in TRAINING SEQUENCE SB Channel");
12299
12300 if (mcu1_enable_ch0_err_inj)
12301 begin
12302 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_freq = 12'h1;
12303 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_period = 12'h1;
12304 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_frame_num = 12'h1;
12305
12306 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_freq = 12'h1;
12307 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_period = 12'h1;
12308 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_frame_num = 12'h1;
12309 end
12310
12311 if (mcu1_enable_ch1_err_inj)
12312 begin
12313 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_freq = 12'h1;
12314 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_period = 12'h1;
12315 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_frame_num = 12'h1;
12316
12317 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_freq = 12'h1;
12318 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_period = 12'h1;
12319 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_frame_num = 12'h1;
12320 end
12321
12322 repeat (1) @ (posedge sclk);
12323
12324 release tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_freq;
12325 release tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_period;
12326 release tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_frame_num;
12327
12328 release tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_freq;
12329 release tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_period;
12330 release tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_frame_num;
12331
12332 release tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_freq;
12333 release tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_period;
12334 release tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_frame_num;
12335
12336 release tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_freq;
12337 release tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_period;
12338 release tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_frame_num;
12339
12340 mcu1_sb_channel_error_cnt_tmp = mcu1_sb_channel_error_cnt_tmp - 1;
12341
12342 repeat (3) @ (posedge sclk);
12343 end // if (mcu1_training_err_enable ..
12344end
12345
12346
12347
12348always @ ( mcu1_drif_dram_cmd_a or
12349 mcu1_drif_dram_cmd_b or
12350 mcu1_drif_dram_cmd_c or
12351 `MCU1.fbdic.fbdic_config_reg_write or
12352 `MCU1.fbdic.fbdic_config_reg_read or
12353 `MCU1.fbdic.fbdic_scr_frame_req or
12354 `MCU1.fbdic.fbdic_sync_frame_req or
12355 `MCU1.fbdic.fbdic_issue_pre_all_cmd or
12356 `MCU1.fbdic.fbdic_issue_cke_cmd
12357 )
12358begin
12359if (enabled && ~ras_corner_case)
12360begin
12361
12362 // --------- Random SB CRC Err Injection --------
12363 if (mcu1_sb_err_random) begin
12364 mcu1_sb_random_cycle = ({$random} % 3);
12365 if (mcu1_sb_crc_multiple_bit_times)
12366 mcu1_sb_bit_time_mask = $random;
12367 else begin
12368 mcu1_sb_random_bit_time = ({$random} % BIT_TIMES);
12369 mcu1_sb_bit_time_mask = mcu1_sb_bit_time_mask << mcu1_sb_random_bit_time;
12370 end
12371 if (mcu1_sb_crc_multiple_lanes)
12372 mcu1_sb_lane_mask = $random;
12373 else begin
12374 mcu1_sb_random_lane = ({$random} % SB_LANES);
12375 mcu1_sb_lane_mask = mcu1_sb_lane_mask << mcu1_sb_random_lane;
12376 end
12377 mcu1_sb_random_val = ({$random} % 100);
12378 if (!(mcu1_sb_random_val > MCU1_SB_RANDOM_WEIGHT)) mcu1_sb_err_enable=1;
12379 end
12380
12381
12382
12383
12384 if ( !stop_mcu1_sb_mask && !($time < stop_mcu1_sb_crc_inj_time) && !(stop_mcu1_sb_crc_inj_time == 0) )
12385 begin
12386 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on SB channel for MCU1, time now is %d",$time);
12387 force mcu1_sb_err_enable=0;
12388 stop_mcu1_sb_mask = 1;
12389 end
12390 else if ( !restart_mcu1_sb_mask && !($time < restart_mcu1_sb_crc_inj_time) && !(restart_mcu1_sb_crc_inj_time == 0) && (restart_mcu1_sb_crc_inj_time > stop_mcu1_sb_crc_inj_time) )
12391 begin
12392 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on SB channel for MCU1, time now is %d",$time);
12393 release mcu1_sb_err_enable;
12394 restart_mcu1_sb_mask=1;
12395 end
12396 else if ( !restart_stop_mcu1_sb_mask && !($time < restart_stop_mcu1_sb_crc_inj_time) && !(restart_stop_mcu1_sb_crc_inj_time == 0) && (restart_stop_mcu1_sb_crc_inj_time > restart_mcu1_sb_crc_inj_time) )
12397 begin
12398 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on SB channel for MCU1, time now is %d",$time);
12399 force mcu1_sb_err_enable=0;
12400 restart_stop_mcu1_sb_mask=1;
12401 end
12402
12403
12404
12405 if ( ( $test$plusargs("INJECT_CRC_MCU1_SB_ERRQ") && (mcu1_sb_err < 8) && mcu1_sb_err_random ) &&
12406 ( `MCU1.drif.reqq.drq0.drq_rdq_full == 0 && `MCU1.drif.reqq.drq0.drq_wrq_full == 0 ) && // check both rd and wr queues on both channels are empty
12407 ( `MCU1.drif.reqq.drq1.drq_rdq_full == 0 && `MCU1.drif.reqq.drq1.drq_wrq_full == 0 ) &&
12408 ( `MCU1.drif.reqq.drq0.drq_empty == 1 && `MCU1.drif.reqq.drq1.drq_empty == 1 ) && // check channel 0/1 dram rd/wr queues
12409 ( `MCU1.drif.errq.errq_empty == 1 && `MCU1.drif.reqq.woq_err_fifo_empty == 1 ) && // check also dram rd/wr ecc/crc error fifo
12410`ifdef FC_CRC_INJECT
12411 passed_bootEnd_mask==1 &&
12412`endif
12413 ((`MCU1.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
12414 (`MCU1.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
12415 (`MCU1.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
12416 `MCU1.fbdic.fbdic_scr_frame_req==1'b1 ||
12417 `MCU1.fbdic.fbdic_issue_pre_all_cmd ||
12418 `MCU1.fbdic.fbdic_issue_cke_cmd ||
12419 mcu1_drif_dram_cmd_a==`ACT ||
12420 mcu1_drif_dram_cmd_a==`WR ||
12421 mcu1_drif_dram_cmd_a==`RD ||
12422 mcu1_drif_dram_cmd_b==`ACT ||
12423 mcu1_drif_dram_cmd_b==`WR ||
12424 mcu1_drif_dram_cmd_b==`WRDATA ||
12425 (mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF) ||
12426 (mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_PDE) ||
12427 (mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
12428 mcu1_drif_dram_cmd_c==`ACT ||
12429 mcu1_drif_dram_cmd_c==`WR) )
12430 begin
12431 force mcu1_sb_err_enable=0;
12432 inject_crc_mcu1_sb_errq_mask=1;
12433 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Injecting CRC errors on SB channel in MCU1 via RD/WR queue tracking, errq loop count is %d (max. allowed is 8)",mcu1_sb_err);
12434 end
12435
12436
12437
12438 else if ( mcu1_sb_err_enable==1 && (~mcu1_esr_fbu || mcu1_inject_fbu_err) &&
12439 ((`MCU1.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
12440 (`MCU1.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
12441 (`MCU1.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
12442 `MCU1.fbdic.fbdic_scr_frame_req==1'b1 ||
12443 `MCU1.fbdic.fbdic_issue_pre_all_cmd ||
12444 `MCU1.fbdic.fbdic_issue_cke_cmd ||
12445 mcu1_drif_dram_cmd_a==`ACT ||
12446 mcu1_drif_dram_cmd_a==`WR ||
12447 mcu1_drif_dram_cmd_a==`RD ||
12448 mcu1_drif_dram_cmd_b==`ACT ||
12449 mcu1_drif_dram_cmd_b==`WR ||
12450 mcu1_drif_dram_cmd_b==`WRDATA ||
12451 (mcu1_drif_dram_cmd_b==`CMD_OTHER && mcu1_drif_dram_addr_b == `CMD_OTHER_REF) ||
12452 (mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_PDE) ||
12453 (mcu1_drif_dram_cmd_c==`CMD_OTHER && mcu1_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
12454 mcu1_drif_dram_cmd_c==`ACT ||
12455 mcu1_drif_dram_cmd_c==`WR) &&
12456 (`MCU1.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
12457 (mcu1_sb_channel_error_cnt>0) &&
12458`ifdef FC_CRC_INJECT
12459 passed_bootEnd_mask==1 &&
12460 (!mcu1_esr_fbr && !mcu1_esr_fbu) &&
12461`endif
12462 (`MCU1.drif.drif_err_state == 5'h1 || mcu1_inject_fbu_err) )
12463 inject_crc_mcu1_sb_mask=1;
12464
12465
12466 if ( inject_crc_mcu1_sb_errq_mask==1 || (inject_crc_mcu1_sb_errq_mask==0 && inject_crc_mcu1_sb_mask==1 ) )
12467 begin
12468
12469
12470 if (mcu1_sb_err_random)
12471 repeat (3+mcu1_sb_random_cycle) @ (posedge drl2clk);
12472 else
12473 repeat (3) @ (posedge drl2clk);
12474 repeat (10) @ (posedge sclk);
12475
12476
12477
12478 mcu1_sb_err = mcu1_sb_err + 1;
12479 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU1: SB --- injecting CRC error no. %d", mcu1_sb_err);
12480
12481
12482 if (mcu1_enable_ch0_err_inj) begin
12483 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_freq = 12'h1;
12484 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_period = 12'h1;
12485 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_frame_num = 12'h1;
12486
12487 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_freq = 12'h1;
12488 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_period = 12'h1;
12489 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_frame_num = 12'h1;
12490
12491 if (mcu1_sb_err_random) begin
12492 if (mcu1_sb_bit_time_mask[0]) begin
12493 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps0_crc_mask = mcu1_sb_lane_mask;
12494 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps0_crc_mask = mcu1_sb_lane_mask;
12495 end
12496 if (mcu1_sb_bit_time_mask[1]) begin
12497 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps1_crc_mask = mcu1_sb_lane_mask;
12498 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps1_crc_mask = mcu1_sb_lane_mask;
12499 end
12500 if (mcu1_sb_bit_time_mask[2]) begin
12501 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps2_crc_mask = mcu1_sb_lane_mask;
12502 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps2_crc_mask = mcu1_sb_lane_mask;
12503 end
12504 if (mcu1_sb_bit_time_mask[3]) begin
12505 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps3_crc_mask = mcu1_sb_lane_mask;
12506 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps3_crc_mask = mcu1_sb_lane_mask;
12507 end
12508 if (mcu1_sb_bit_time_mask[4]) begin
12509 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps4_crc_mask = mcu1_sb_lane_mask;
12510 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps4_crc_mask = mcu1_sb_lane_mask;
12511 end
12512 if (mcu1_sb_bit_time_mask[5]) begin
12513 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps5_crc_mask = mcu1_sb_lane_mask;
12514 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps5_crc_mask = mcu1_sb_lane_mask;
12515 end
12516 if (mcu1_sb_bit_time_mask[6]) begin
12517 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps6_crc_mask = mcu1_sb_lane_mask;
12518 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps6_crc_mask = mcu1_sb_lane_mask;
12519 end
12520 if (mcu1_sb_bit_time_mask[7]) begin
12521 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps7_crc_mask = mcu1_sb_lane_mask;
12522 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps7_crc_mask = mcu1_sb_lane_mask;
12523 end
12524 if (mcu1_sb_bit_time_mask[8]) begin
12525 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps8_crc_mask = mcu1_sb_lane_mask;
12526 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps8_crc_mask = mcu1_sb_lane_mask;
12527 end
12528 if (mcu1_sb_bit_time_mask[9]) begin
12529 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps9_crc_mask = mcu1_sb_lane_mask;
12530 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps9_crc_mask = mcu1_sb_lane_mask;
12531 end
12532 if (mcu1_sb_bit_time_mask[10]) begin
12533 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps10_crc_mask = mcu1_sb_lane_mask;
12534 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps10_crc_mask = mcu1_sb_lane_mask;
12535 end
12536 if (mcu1_sb_bit_time_mask[11]) begin
12537 force tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps11_crc_mask = mcu1_sb_lane_mask;
12538 force tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps11_crc_mask = mcu1_sb_lane_mask;
12539 end
12540 end
12541
12542 if (mcu1_inject_fbu_err && !mcu1_esr_fbu)
12543 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 SB - MCU1 (mcu1_sb_bit_time_mask[11:0] is %b, mcu1_sb_lane_mask[9:0] is %b)",mcu1_sb_bit_time_mask,mcu1_sb_lane_mask);
12544 else if (!mcu1_esr_fbr)
12545 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 SB - MCU1 (mcu1_sb_bit_time_mask[11:0] is %b, mcu1_sb_lane_mask[9:0] is %b)",mcu1_sb_bit_time_mask,mcu1_sb_lane_mask);
12546
12547 end
12548
12549 if (mcu1_enable_ch1_err_inj) begin
12550 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_freq = 12'h1;
12551 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_period = 12'h1;
12552 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_frame_num = 12'h1;
12553
12554 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_freq = 12'h1;
12555 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_period = 12'h1;
12556 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_frame_num = 12'h1;
12557
12558 if (mcu1_sb_err_random) begin
12559 if (mcu1_sb_bit_time_mask[0]) begin
12560 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps0_crc_mask = mcu1_sb_lane_mask;
12561 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps0_crc_mask = mcu1_sb_lane_mask;
12562 end
12563 if (mcu1_sb_bit_time_mask[1]) begin
12564 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps1_crc_mask = mcu1_sb_lane_mask;
12565 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps1_crc_mask = mcu1_sb_lane_mask;
12566 end
12567 if (mcu1_sb_bit_time_mask[2]) begin
12568 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps2_crc_mask = mcu1_sb_lane_mask;
12569 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps2_crc_mask = mcu1_sb_lane_mask;
12570 end
12571 if (mcu1_sb_bit_time_mask[3]) begin
12572 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps3_crc_mask = mcu1_sb_lane_mask;
12573 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps3_crc_mask = mcu1_sb_lane_mask;
12574 end
12575 if (mcu1_sb_bit_time_mask[4]) begin
12576 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps4_crc_mask = mcu1_sb_lane_mask;
12577 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps4_crc_mask = mcu1_sb_lane_mask;
12578 end
12579 if (mcu1_sb_bit_time_mask[5]) begin
12580 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps5_crc_mask = mcu1_sb_lane_mask;
12581 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps5_crc_mask = mcu1_sb_lane_mask;
12582 end
12583 if (mcu1_sb_bit_time_mask[6]) begin
12584 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps6_crc_mask = mcu1_sb_lane_mask;
12585 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps6_crc_mask = mcu1_sb_lane_mask;
12586 end
12587 if (mcu1_sb_bit_time_mask[7]) begin
12588 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps7_crc_mask = mcu1_sb_lane_mask;
12589 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps7_crc_mask = mcu1_sb_lane_mask;
12590 end
12591 if (mcu1_sb_bit_time_mask[8]) begin
12592 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps8_crc_mask = mcu1_sb_lane_mask;
12593 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps8_crc_mask = mcu1_sb_lane_mask;
12594 end
12595 if (mcu1_sb_bit_time_mask[9]) begin
12596 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps9_crc_mask = mcu1_sb_lane_mask;
12597 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps9_crc_mask = mcu1_sb_lane_mask;
12598 end
12599 if (mcu1_sb_bit_time_mask[10]) begin
12600 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps10_crc_mask = mcu1_sb_lane_mask;
12601 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps10_crc_mask = mcu1_sb_lane_mask;
12602 end
12603 if (mcu1_sb_bit_time_mask[11]) begin
12604 force tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps11_crc_mask = mcu1_sb_lane_mask;
12605 force tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps11_crc_mask = mcu1_sb_lane_mask;
12606 end
12607 end
12608
12609 if (mcu1_inject_fbu_err && !mcu1_esr_fbu)
12610 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 SB - MCU1 (mcu1_sb_bit_time_mask[11:0] is %b, mcu1_sb_lane_mask[9:0] is %b)",mcu1_sb_bit_time_mask,mcu1_sb_lane_mask);
12611 else if (!mcu1_esr_fbr)
12612 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 SB - MCU1 (mcu1_sb_bit_time_mask[11:0] is %b, mcu1_sb_lane_mask[9:0] is %b)",mcu1_sb_bit_time_mask,mcu1_sb_lane_mask);
12613
12614 end
12615
12616 repeat (1) @ (posedge sclk);
12617
12618 release tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_freq;
12619 release tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_crc_period;
12620 release tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_frame_num;
12621
12622 release tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_freq;
12623 release tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_crc_period;
12624 release tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_frame_num;
12625
12626 release tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_freq;
12627 release tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_crc_period;
12628 release tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_frame_num;
12629
12630 release tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_freq;
12631 release tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_crc_period;
12632 release tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_frame_num;
12633
12634 inject_crc_mcu1_sb_mask=0;
12635 if (mcu1_sb_err_random==0)
12636 mcu1_sb_channel_error_cnt=mcu1_sb_channel_error_cnt - 1;
12637 else begin
12638 mcu1_sb_err_enable = 0;
12639 mcu1_sb_lane_mask = 10'h1;
12640 mcu1_sb_bit_time_mask = 12'h1;
12641 end
12642 end
12643end
12644end
12645
12646// --- MCU2 ---
12647
12648always @(fbdic_fbd_state_2)
12649begin
12650mcu2_sb_channel_error_cnt_tmp = mcu2_sb_channel_error_cnt;
12651end
12652
12653// If an error is detected and MCU went to disable state, stop the error
12654// injection
12655always @(posedge drl2clk)
12656begin
12657
12658 if ((mcu2_fbdic_tclktrain_done[1] == 1'b1)||
12659 (mcu2_fbdic_testing_done[1] == 1'b1) ||
12660 (mcu2_fbdic_polling_done[1] == 1'b1))
12661 begin
12662 repeat (50) @(posedge drl2clk);
12663 if(fbdic_fbd_state_2 == 0)
12664 begin
12665 mcu2_training_err_enable = 0;
12666 `PR_DEBUG("mcu_fmon",`DEBUG," DISABLED Err INJECTION IN TRAINING SEQUENCE");
12667 end
12668 end
12669
12670
12671end
12672
12673always @(posedge drl2clk)
12674begin
12675
12676@(posedge drl2clk);
12677
12678 if ((mcu2_training_err_enable == 1) &&
12679 (fbdic_fbd_state_2 == 2 || fbdic_fbd_state_2 == 3 ||
12680 fbdic_fbd_state_2 == 4 || fbdic_fbd_state_2 == 5) &&
12681 ( mcu2_sb_channel_error_cnt_tmp>0 ) )
12682 begin
12683
12684 if( fbdic_fbd_state_2 == 2 )
12685 begin
12686 repeat (100) @(posedge drl2clk);
12687 end
12688 else
12689 begin
12690 repeat (30) @(posedge drl2clk);
12691 end
12692
12693 `PR_DEBUG("mcu_fmon",`DEBUG," Entered Err Injection in TRAINING SEQUENCE SB Channel");
12694
12695 if (mcu2_enable_ch0_err_inj)
12696 begin
12697 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_freq = 12'h1;
12698 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_period = 12'h1;
12699 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_frame_num = 12'h1;
12700
12701 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_freq = 12'h1;
12702 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_period = 12'h1;
12703 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_frame_num = 12'h1;
12704 end
12705
12706 if (mcu2_enable_ch1_err_inj)
12707 begin
12708 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_freq = 12'h1;
12709 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_period = 12'h1;
12710 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_frame_num = 12'h1;
12711
12712 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_freq = 12'h1;
12713 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_period = 12'h1;
12714 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_frame_num = 12'h1;
12715 end
12716
12717 repeat (1) @ (posedge sclk);
12718
12719 release tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_freq;
12720 release tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_period;
12721 release tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_frame_num;
12722
12723 release tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_freq;
12724 release tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_period;
12725 release tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_frame_num;
12726
12727 release tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_freq;
12728 release tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_period;
12729 release tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_frame_num;
12730
12731 release tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_freq;
12732 release tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_period;
12733 release tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_frame_num;
12734
12735 mcu2_sb_channel_error_cnt_tmp = mcu2_sb_channel_error_cnt_tmp - 1;
12736
12737 repeat (3) @ (posedge sclk);
12738 repeat (3) @ (posedge sclk);
12739 end // if (mcu2_training_err_enable ..
12740end
12741
12742
12743always @ ( mcu2_drif_dram_cmd_a or
12744 mcu2_drif_dram_cmd_b or
12745 mcu2_drif_dram_cmd_c or
12746 `MCU2.fbdic.fbdic_config_reg_write or
12747 `MCU2.fbdic.fbdic_config_reg_read or
12748 `MCU2.fbdic.fbdic_scr_frame_req or
12749 `MCU2.fbdic.fbdic_sync_frame_req or
12750 `MCU2.fbdic.fbdic_issue_pre_all_cmd or
12751 `MCU2.fbdic.fbdic_issue_cke_cmd
12752 )
12753begin
12754if (enabled && ~ras_corner_case)
12755begin
12756
12757
12758 // --------- Random SB CRC Err Injection --------
12759 if (mcu2_sb_err_random) begin
12760 mcu2_sb_random_cycle = ({$random} % 3);
12761 if (mcu2_sb_crc_multiple_bit_times)
12762 mcu2_sb_bit_time_mask = $random;
12763 else begin
12764 mcu2_sb_random_bit_time = ({$random} % BIT_TIMES);
12765 mcu2_sb_bit_time_mask = mcu2_sb_bit_time_mask << mcu2_sb_random_bit_time;
12766 end
12767 if (mcu2_sb_crc_multiple_lanes)
12768 mcu2_sb_lane_mask = $random;
12769 else begin
12770 mcu2_sb_random_lane = ({$random} % SB_LANES);
12771 mcu2_sb_lane_mask = mcu2_sb_lane_mask << mcu2_sb_random_lane;
12772 end
12773 mcu2_sb_random_val = ({$random} % 100);
12774 if (!(mcu2_sb_random_val > MCU2_SB_RANDOM_WEIGHT)) mcu2_sb_err_enable=1;
12775 end
12776
12777
12778
12779
12780 if ( !stop_mcu2_sb_mask && !($time < stop_mcu2_sb_crc_inj_time) && !(stop_mcu2_sb_crc_inj_time == 0) )
12781 begin
12782 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on SB channel for MCU2, time now is %d",$time);
12783 force mcu2_sb_err_enable=0;
12784 stop_mcu2_sb_mask = 1;
12785 end
12786 else if ( !restart_mcu2_sb_mask && !($time < restart_mcu2_sb_crc_inj_time) && !(restart_mcu2_sb_crc_inj_time == 0) && (restart_mcu2_sb_crc_inj_time > stop_mcu2_sb_crc_inj_time) )
12787 begin
12788 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on SB channel for MCU2, time now is %d",$time);
12789 release mcu2_sb_err_enable;
12790 restart_mcu2_sb_mask=1;
12791 end
12792 else if ( !restart_stop_mcu2_sb_mask && !($time < restart_stop_mcu2_sb_crc_inj_time) && !(restart_stop_mcu2_sb_crc_inj_time == 0) && (restart_stop_mcu2_sb_crc_inj_time > restart_mcu2_sb_crc_inj_time) )
12793 begin
12794 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on SB channel for MCU2, time now is %d",$time);
12795 force mcu2_sb_err_enable=0;
12796 restart_stop_mcu2_sb_mask=1;
12797 end
12798
12799
12800
12801 if ( ( $test$plusargs("INJECT_CRC_MCU2_SB_ERRQ") && (mcu2_sb_err < 8) && mcu2_sb_err_random ) &&
12802 ( `MCU2.drif.reqq.drq0.drq_rdq_full == 0 && `MCU2.drif.reqq.drq0.drq_wrq_full == 0 ) && // check both rd and wr queues on both channels are empty
12803 ( `MCU2.drif.reqq.drq1.drq_rdq_full == 0 && `MCU2.drif.reqq.drq1.drq_wrq_full == 0 ) &&
12804 ( `MCU2.drif.reqq.drq0.drq_empty == 1 && `MCU2.drif.reqq.drq1.drq_empty == 1 ) && // check channel 0/1 dram rd/wr queues
12805 ( `MCU2.drif.errq.errq_empty == 1 && `MCU2.drif.reqq.woq_err_fifo_empty == 1 ) && // check also dram rd/wr ecc/crc error fifo
12806`ifdef FC_CRC_INJECT
12807 passed_bootEnd_mask==1 &&
12808`endif
12809 ((`MCU2.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
12810 (`MCU2.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
12811 (`MCU2.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
12812 `MCU2.fbdic.fbdic_scr_frame_req==1'b1 ||
12813 `MCU2.fbdic.fbdic_issue_pre_all_cmd ||
12814 `MCU2.fbdic.fbdic_issue_cke_cmd ||
12815 mcu2_drif_dram_cmd_a==`ACT ||
12816 mcu2_drif_dram_cmd_a==`WR ||
12817 mcu2_drif_dram_cmd_a==`RD ||
12818 mcu2_drif_dram_cmd_b==`ACT ||
12819 mcu2_drif_dram_cmd_b==`WR ||
12820 mcu2_drif_dram_cmd_b==`WRDATA ||
12821 (mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF) ||
12822 (mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_PDE) ||
12823 (mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
12824 mcu2_drif_dram_cmd_c==`ACT ||
12825 mcu2_drif_dram_cmd_c==`WR) )
12826 begin
12827 force mcu2_sb_err_enable=0;
12828 inject_crc_mcu2_sb_errq_mask=1;
12829 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Injecting CRC errors on SB channel in MCU2 via RD/WR queue tracking, errq loop count is %d (max. allowed is 8)",mcu2_sb_err);
12830 end
12831
12832
12833 else if ( mcu2_sb_err_enable==1 && (~mcu2_esr_fbu || mcu2_inject_fbu_err) &&
12834 ((`MCU2.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
12835 (`MCU2.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
12836 (`MCU2.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
12837 `MCU2.fbdic.fbdic_scr_frame_req==1'b1 ||
12838 `MCU2.fbdic.fbdic_issue_pre_all_cmd ||
12839 `MCU2.fbdic.fbdic_issue_cke_cmd ||
12840 mcu2_drif_dram_cmd_a==`ACT ||
12841 mcu2_drif_dram_cmd_a==`WR ||
12842 mcu2_drif_dram_cmd_a==`RD ||
12843 mcu2_drif_dram_cmd_b==`ACT ||
12844 mcu2_drif_dram_cmd_b==`WR ||
12845 mcu2_drif_dram_cmd_b==`WRDATA ||
12846 (mcu2_drif_dram_cmd_b==`CMD_OTHER && mcu2_drif_dram_addr_b == `CMD_OTHER_REF) ||
12847 (mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_PDE) ||
12848 (mcu2_drif_dram_cmd_c==`CMD_OTHER && mcu2_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
12849 mcu2_drif_dram_cmd_c==`ACT ||
12850 mcu2_drif_dram_cmd_c==`WR) &&
12851 (`MCU2.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
12852 (mcu2_sb_channel_error_cnt>0) &&
12853`ifdef FC_CRC_INJECT
12854 passed_bootEnd_mask==1 &&
12855 (!mcu2_esr_fbr && !mcu2_esr_fbu) &&
12856`endif
12857 (`MCU2.drif.drif_err_state == 5'h1 || mcu2_inject_fbu_err) )
12858 inject_crc_mcu2_sb_mask=1;
12859
12860
12861 if ( inject_crc_mcu2_sb_errq_mask==1 || (inject_crc_mcu2_sb_errq_mask==0 && inject_crc_mcu2_sb_mask==1 ) )
12862 begin
12863
12864
12865 if (mcu2_sb_err_random)
12866 repeat (3+mcu2_sb_random_cycle) @ (posedge drl2clk);
12867 else
12868 repeat (3) @ (posedge drl2clk);
12869 repeat (10) @ (posedge sclk);
12870
12871
12872
12873 mcu2_sb_err = mcu2_sb_err + 1;
12874 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU2: SB --- injecting CRC error no. %d", mcu2_sb_err);
12875
12876
12877 if (mcu2_enable_ch0_err_inj) begin
12878 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_freq = 12'h1;
12879 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_period = 12'h1;
12880 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_frame_num = 12'h1;
12881
12882 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_freq = 12'h1;
12883 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_period = 12'h1;
12884 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_frame_num = 12'h1;
12885
12886 if (mcu2_sb_err_random) begin
12887 if (mcu2_sb_bit_time_mask[0]) begin
12888 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps0_crc_mask = mcu2_sb_lane_mask;
12889 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps0_crc_mask = mcu2_sb_lane_mask;
12890 end
12891 if (mcu2_sb_bit_time_mask[1]) begin
12892 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps1_crc_mask = mcu2_sb_lane_mask;
12893 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps1_crc_mask = mcu2_sb_lane_mask;
12894 end
12895 if (mcu2_sb_bit_time_mask[2]) begin
12896 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps2_crc_mask = mcu2_sb_lane_mask;
12897 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps2_crc_mask = mcu2_sb_lane_mask;
12898 end
12899 if (mcu2_sb_bit_time_mask[3]) begin
12900 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps3_crc_mask = mcu2_sb_lane_mask;
12901 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps3_crc_mask = mcu2_sb_lane_mask;
12902 end
12903 if (mcu2_sb_bit_time_mask[4]) begin
12904 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps4_crc_mask = mcu2_sb_lane_mask;
12905 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps4_crc_mask = mcu2_sb_lane_mask;
12906 end
12907 if (mcu2_sb_bit_time_mask[5]) begin
12908 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps5_crc_mask = mcu2_sb_lane_mask;
12909 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps5_crc_mask = mcu2_sb_lane_mask;
12910 end
12911 if (mcu2_sb_bit_time_mask[6]) begin
12912 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps6_crc_mask = mcu2_sb_lane_mask;
12913 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps6_crc_mask = mcu2_sb_lane_mask;
12914 end
12915 if (mcu2_sb_bit_time_mask[7]) begin
12916 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps7_crc_mask = mcu2_sb_lane_mask;
12917 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps7_crc_mask = mcu2_sb_lane_mask;
12918 end
12919 if (mcu2_sb_bit_time_mask[8]) begin
12920 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps8_crc_mask = mcu2_sb_lane_mask;
12921 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps8_crc_mask = mcu2_sb_lane_mask;
12922 end
12923 if (mcu2_sb_bit_time_mask[9]) begin
12924 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps9_crc_mask = mcu2_sb_lane_mask;
12925 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps9_crc_mask = mcu2_sb_lane_mask;
12926 end
12927 if (mcu2_sb_bit_time_mask[10]) begin
12928 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps10_crc_mask = mcu2_sb_lane_mask;
12929 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps10_crc_mask = mcu2_sb_lane_mask;
12930 end
12931 if (mcu2_sb_bit_time_mask[11]) begin
12932 force tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps11_crc_mask = mcu2_sb_lane_mask;
12933 force tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps11_crc_mask = mcu2_sb_lane_mask;
12934 end
12935 end
12936
12937 if (mcu2_inject_fbu_err && !mcu2_esr_fbu)
12938 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 SB - MCU2 (mcu2_sb_bit_time_mask[11:0] is %b, mcu2_sb_lane_mask[9:0] is %b)",mcu2_sb_bit_time_mask,mcu2_sb_lane_mask);
12939 else if (!mcu2_esr_fbr)
12940 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 SB - MCU2 (mcu2_sb_bit_time_mask[11:0] is %b, mcu2_sb_lane_mask[9:0] is %b)",mcu2_sb_bit_time_mask,mcu2_sb_lane_mask);
12941
12942 end
12943
12944 if (mcu2_enable_ch1_err_inj) begin
12945 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_freq = 12'h1;
12946 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_period = 12'h1;
12947 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_frame_num = 12'h1;
12948
12949 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_freq = 12'h1;
12950 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_period = 12'h1;
12951 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_frame_num = 12'h1;
12952
12953 if (mcu2_sb_err_random) begin
12954 if (mcu2_sb_bit_time_mask[0]) begin
12955 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps0_crc_mask = mcu2_sb_lane_mask;
12956 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps0_crc_mask = mcu2_sb_lane_mask;
12957 end
12958 if (mcu2_sb_bit_time_mask[1]) begin
12959 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps1_crc_mask = mcu2_sb_lane_mask;
12960 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps1_crc_mask = mcu2_sb_lane_mask;
12961 end
12962 if (mcu2_sb_bit_time_mask[2]) begin
12963 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps2_crc_mask = mcu2_sb_lane_mask;
12964 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps2_crc_mask = mcu2_sb_lane_mask;
12965 end
12966 if (mcu2_sb_bit_time_mask[3]) begin
12967 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps3_crc_mask = mcu2_sb_lane_mask;
12968 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps3_crc_mask = mcu2_sb_lane_mask;
12969 end
12970 if (mcu2_sb_bit_time_mask[4]) begin
12971 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps4_crc_mask = mcu2_sb_lane_mask;
12972 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps4_crc_mask = mcu2_sb_lane_mask;
12973 end
12974 if (mcu2_sb_bit_time_mask[5]) begin
12975 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps5_crc_mask = mcu2_sb_lane_mask;
12976 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps5_crc_mask = mcu2_sb_lane_mask;
12977 end
12978 if (mcu2_sb_bit_time_mask[6]) begin
12979 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps6_crc_mask = mcu2_sb_lane_mask;
12980 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps6_crc_mask = mcu2_sb_lane_mask;
12981 end
12982 if (mcu2_sb_bit_time_mask[7]) begin
12983 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps7_crc_mask = mcu2_sb_lane_mask;
12984 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps7_crc_mask = mcu2_sb_lane_mask;
12985 end
12986 if (mcu2_sb_bit_time_mask[8]) begin
12987 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps8_crc_mask = mcu2_sb_lane_mask;
12988 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps8_crc_mask = mcu2_sb_lane_mask;
12989 end
12990 if (mcu2_sb_bit_time_mask[9]) begin
12991 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps9_crc_mask = mcu2_sb_lane_mask;
12992 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps9_crc_mask = mcu2_sb_lane_mask;
12993 end
12994 if (mcu2_sb_bit_time_mask[10]) begin
12995 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps10_crc_mask = mcu2_sb_lane_mask;
12996 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps10_crc_mask = mcu2_sb_lane_mask;
12997 end
12998 if (mcu2_sb_bit_time_mask[11]) begin
12999 force tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps11_crc_mask = mcu2_sb_lane_mask;
13000 force tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps11_crc_mask = mcu2_sb_lane_mask;
13001 end
13002 end
13003
13004 if (mcu2_inject_fbu_err && !mcu2_esr_fbu)
13005 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 SB - MCU2 (mcu2_sb_bit_time_mask[11:0] is %b, mcu2_sb_lane_mask[9:0] is %b)",mcu2_sb_bit_time_mask,mcu2_sb_lane_mask);
13006 else if (!mcu2_esr_fbr)
13007 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 SB - MCU2 (mcu2_sb_bit_time_mask[11:0] is %b, mcu2_sb_lane_mask[9:0] is %b)",mcu2_sb_bit_time_mask,mcu2_sb_lane_mask);
13008
13009 end
13010
13011 repeat (1) @ (posedge sclk);
13012
13013 release tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_freq;
13014 release tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_crc_period;
13015 release tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_frame_num;
13016
13017 release tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_freq;
13018 release tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_crc_period;
13019 release tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_frame_num;
13020
13021 release tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_freq;
13022 release tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_crc_period;
13023 release tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_frame_num;
13024
13025 release tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_freq;
13026 release tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_crc_period;
13027 release tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_frame_num;
13028
13029 inject_crc_mcu2_sb_mask=0;
13030 if (mcu2_sb_err_random==0)
13031 mcu2_sb_channel_error_cnt=mcu2_sb_channel_error_cnt - 1;
13032 else begin
13033 mcu2_sb_err_enable = 0;
13034 mcu2_sb_lane_mask = 10'h1;
13035 mcu2_sb_bit_time_mask = 12'h1;
13036 end
13037 end
13038end
13039end
13040
13041// --- MCU3 ---
13042
13043always @(fbdic_fbd_state_3)
13044begin
13045mcu3_sb_channel_error_cnt_tmp = mcu3_sb_channel_error_cnt;
13046end
13047
13048// If an error is detected and MCU went to disable state, stop the error
13049// injection
13050always @(posedge drl2clk)
13051begin
13052
13053 if ((mcu3_fbdic_tclktrain_done[1] == 1'b1)||
13054 (mcu3_fbdic_testing_done[1] == 1'b1) ||
13055 (mcu3_fbdic_polling_done[1] == 1'b1))
13056 begin
13057 repeat (50) @(posedge drl2clk);
13058 if(fbdic_fbd_state_3 == 0)
13059 begin
13060 mcu3_training_err_enable = 0;
13061 `PR_DEBUG("mcu_fmon",`DEBUG," DISABLED Err INJECTION IN TRAINING SEQUENCE");
13062 end
13063 end
13064
13065
13066end
13067
13068always @(posedge drl2clk)
13069begin
13070
13071@(posedge drl2clk);
13072
13073 if ((mcu3_training_err_enable == 1) &&
13074 (fbdic_fbd_state_3 == 2 || fbdic_fbd_state_3 == 3 ||
13075 fbdic_fbd_state_3 == 4 || fbdic_fbd_state_3 == 5) &&
13076 ( mcu3_sb_channel_error_cnt_tmp>0 ) )
13077 begin
13078
13079 if( fbdic_fbd_state_3 == 2 )
13080 begin
13081 repeat (100) @(posedge drl2clk);
13082 end
13083 else
13084 begin
13085 repeat (30) @(posedge drl2clk);
13086 end
13087
13088 `PR_DEBUG("mcu_fmon",`DEBUG," Entered Err Injection in TRAINING SEQUENCE SB Channel");
13089
13090 if (mcu3_enable_ch0_err_inj)
13091 begin
13092 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_freq = 12'h1;
13093 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_period = 12'h1;
13094 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_frame_num = 12'h1;
13095
13096 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_freq = 12'h1;
13097 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_period = 12'h1;
13098 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_frame_num = 12'h1;
13099 end
13100
13101 if (mcu3_enable_ch1_err_inj)
13102 begin
13103 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_freq = 12'h1;
13104 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_period = 12'h1;
13105 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_frame_num = 12'h1;
13106
13107 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_freq = 12'h1;
13108 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_period = 12'h1;
13109 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_frame_num = 12'h1;
13110 end
13111
13112 repeat (1) @ (posedge sclk);
13113
13114 release tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_freq;
13115 release tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_period;
13116 release tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_frame_num;
13117
13118 release tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_freq;
13119 release tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_period;
13120 release tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_frame_num;
13121
13122 release tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_freq;
13123 release tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_period;
13124 release tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_frame_num;
13125
13126 release tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_freq;
13127 release tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_period;
13128 release tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_frame_num;
13129
13130 mcu3_sb_channel_error_cnt_tmp = mcu3_sb_channel_error_cnt_tmp - 1;
13131
13132 repeat (3) @ (posedge sclk);
13133 end // if (mcu3_training_err_enable ..
13134end
13135
13136
13137always @ ( mcu3_drif_dram_cmd_a or
13138 mcu3_drif_dram_cmd_b or
13139 mcu3_drif_dram_cmd_c or
13140 `MCU3.fbdic.fbdic_config_reg_write or
13141 `MCU3.fbdic.fbdic_config_reg_read or
13142 `MCU3.fbdic.fbdic_scr_frame_req or
13143 `MCU3.fbdic.fbdic_sync_frame_req or
13144 `MCU3.fbdic.fbdic_issue_pre_all_cmd or
13145 `MCU3.fbdic.fbdic_issue_cke_cmd
13146 )
13147begin
13148if (enabled && ~ras_corner_case)
13149begin
13150
13151 // --------- Random SB CRC Err Injection --------
13152 if (mcu3_sb_err_random) begin
13153 mcu3_sb_random_cycle = ({$random} % 3);
13154 if (mcu3_sb_crc_multiple_bit_times)
13155 mcu3_sb_bit_time_mask = $random;
13156 else begin
13157 mcu3_sb_random_bit_time = ({$random} % BIT_TIMES);
13158 mcu3_sb_bit_time_mask = mcu3_sb_bit_time_mask << mcu3_sb_random_bit_time;
13159 end
13160 if (mcu3_sb_crc_multiple_lanes)
13161 mcu3_sb_lane_mask = $random;
13162 else begin
13163 mcu3_sb_random_lane = ({$random} % SB_LANES);
13164 mcu3_sb_lane_mask = mcu3_sb_lane_mask << mcu3_sb_random_lane;
13165 end
13166 mcu3_sb_random_val = ({$random} % 100);
13167 if (!(mcu3_sb_random_val > MCU3_SB_RANDOM_WEIGHT)) mcu3_sb_err_enable=1;
13168 end
13169
13170
13171
13172
13173 if ( !stop_mcu3_sb_mask && !($time < stop_mcu3_sb_crc_inj_time) && !(stop_mcu3_sb_crc_inj_time == 0) )
13174 begin
13175 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping crc err injection on SB channel for MCU3, time now is %d",$time);
13176 force mcu3_sb_err_enable=0;
13177 stop_mcu3_sb_mask = 1;
13178 end
13179 else if ( !restart_mcu3_sb_mask && !($time < restart_mcu3_sb_crc_inj_time) && !(restart_mcu3_sb_crc_inj_time == 0) && (restart_mcu3_sb_crc_inj_time > stop_mcu3_sb_crc_inj_time) )
13180 begin
13181 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Restarting crc err injection on SB channel for MCU3, time now is %d",$time);
13182 release mcu3_sb_err_enable;
13183 restart_mcu3_sb_mask=1;
13184 end
13185 else if ( !restart_stop_mcu3_sb_mask && !($time < restart_stop_mcu3_sb_crc_inj_time) && !(restart_stop_mcu3_sb_crc_inj_time == 0) && (restart_stop_mcu3_sb_crc_inj_time > restart_mcu3_sb_crc_inj_time) )
13186 begin
13187 `PR_ALWAYS("mcu_fmon", `ALWAYS, "*** Stopping the restarted crc err injection on SB channel for MCU3, time now is %d",$time);
13188 force mcu3_sb_err_enable=0;
13189 restart_stop_mcu3_sb_mask=1;
13190 end
13191
13192
13193
13194 if ( ( $test$plusargs("INJECT_CRC_MCU3_SB_ERRQ") && (mcu3_sb_err < 8) && mcu3_sb_err_random ) &&
13195 ( `MCU3.drif.reqq.drq0.drq_rdq_full == 0 && `MCU3.drif.reqq.drq0.drq_wrq_full == 0 ) && // check both rd and wr queues on both channels are empty
13196 ( `MCU3.drif.reqq.drq1.drq_rdq_full == 0 && `MCU3.drif.reqq.drq1.drq_wrq_full == 0 ) &&
13197 ( `MCU3.drif.reqq.drq0.drq_empty == 1 && `MCU3.drif.reqq.drq1.drq_empty == 1 ) && // check channel 0/1 dram rd/wr queues
13198 ( `MCU3.drif.errq.errq_empty == 1 && `MCU3.drif.reqq.woq_err_fifo_empty == 1 ) && // check also dram rd/wr ecc/crc error fifo
13199`ifdef FC_CRC_INJECT
13200 passed_bootEnd_mask==1 &&
13201`endif
13202 ((`MCU3.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
13203 (`MCU3.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
13204 (`MCU3.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
13205 `MCU3.fbdic.fbdic_scr_frame_req==1'b1 ||
13206 `MCU3.fbdic.fbdic_issue_pre_all_cmd ||
13207 `MCU3.fbdic.fbdic_issue_cke_cmd ||
13208 mcu3_drif_dram_cmd_a==`ACT ||
13209 mcu3_drif_dram_cmd_a==`WR ||
13210 mcu3_drif_dram_cmd_a==`RD ||
13211 mcu3_drif_dram_cmd_b==`ACT ||
13212 mcu3_drif_dram_cmd_b==`WR ||
13213 mcu3_drif_dram_cmd_b==`WRDATA ||
13214 (mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF) ||
13215 (mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_PDE) ||
13216 (mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
13217 mcu3_drif_dram_cmd_c==`ACT ||
13218 mcu3_drif_dram_cmd_c==`WR) )
13219 begin
13220 force mcu3_sb_err_enable=0;
13221 inject_crc_mcu3_sb_errq_mask=1;
13222 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Injecting CRC errors on SB channel in MCU3 via RD/WR queue tracking, errq loop count is %d (max. allowed is 8)",mcu3_sb_err);
13223 end
13224
13225
13226 else if ( mcu3_sb_err_enable==1 && (~mcu3_esr_fbu || mcu3_inject_fbu_err) &&
13227 ((`MCU3.fbdic.fbdic_config_reg_write==1'b1 && ~mcu_bug_111483) ||
13228 (`MCU3.fbdic.fbdic_config_reg_read==1'b1 && ~mcu_bug_111547) ||
13229 (`MCU3.fbdic.fbdic_sync_frame_req==1'b1 && ~mcu_bug_111811) ||
13230 `MCU3.fbdic.fbdic_scr_frame_req==1'b1 ||
13231 `MCU3.fbdic.fbdic_issue_pre_all_cmd ||
13232 `MCU3.fbdic.fbdic_issue_cke_cmd ||
13233 mcu3_drif_dram_cmd_a==`ACT ||
13234 mcu3_drif_dram_cmd_a==`WR ||
13235 mcu3_drif_dram_cmd_a==`RD ||
13236 mcu3_drif_dram_cmd_b==`ACT ||
13237 mcu3_drif_dram_cmd_b==`WR ||
13238 mcu3_drif_dram_cmd_b==`WRDATA ||
13239 (mcu3_drif_dram_cmd_b==`CMD_OTHER && mcu3_drif_dram_addr_b == `CMD_OTHER_REF) ||
13240 (mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_PDE) ||
13241 (mcu3_drif_dram_cmd_c==`CMD_OTHER && mcu3_drif_dram_addr_c == `CMD_OTHER_SRPDX) ||
13242 mcu3_drif_dram_cmd_c==`ACT ||
13243 mcu3_drif_dram_cmd_c==`WR) &&
13244 (`MCU3.drif.pdmc0.pdmc_pd_cnt < 6'h23) &&
13245 (mcu3_sb_channel_error_cnt>0) &&
13246`ifdef FC_CRC_INJECT
13247 passed_bootEnd_mask==1 &&
13248 (!mcu3_esr_fbr && !mcu3_esr_fbu) &&
13249`endif
13250 (`MCU3.drif.drif_err_state == 5'h1 || mcu3_inject_fbu_err) )
13251 inject_crc_mcu3_sb_mask=1;
13252
13253
13254 if ( inject_crc_mcu3_sb_errq_mask==1 || (inject_crc_mcu3_sb_errq_mask==0 && inject_crc_mcu3_sb_mask==1 ) )
13255 begin
13256
13257
13258 if (mcu3_sb_err_random)
13259 repeat (3+mcu3_sb_random_cycle) @ (posedge drl2clk);
13260 else
13261 repeat (3) @ (posedge drl2clk);
13262 repeat (10) @ (posedge sclk);
13263
13264
13265
13266 mcu3_sb_err = mcu3_sb_err + 1;
13267 `PR_ALWAYS("mcu_fmon", `ALWAYS, "MCU3: SB --- injecting CRC error no. %d", mcu3_sb_err);
13268
13269
13270 if (mcu3_enable_ch0_err_inj) begin
13271 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_freq = 12'h1;
13272 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_period = 12'h1;
13273 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_frame_num = 12'h1;
13274
13275 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_freq = 12'h1;
13276 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_period = 12'h1;
13277 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_frame_num = 12'h1;
13278
13279 if (mcu3_sb_err_random) begin
13280 if (mcu3_sb_bit_time_mask[0]) begin
13281 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps0_crc_mask = mcu3_sb_lane_mask;
13282 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps0_crc_mask = mcu3_sb_lane_mask;
13283 end
13284 if (mcu3_sb_bit_time_mask[1]) begin
13285 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps1_crc_mask = mcu3_sb_lane_mask;
13286 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps1_crc_mask = mcu3_sb_lane_mask;
13287 end
13288 if (mcu3_sb_bit_time_mask[2]) begin
13289 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps2_crc_mask = mcu3_sb_lane_mask;
13290 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps2_crc_mask = mcu3_sb_lane_mask;
13291 end
13292 if (mcu3_sb_bit_time_mask[3]) begin
13293 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps3_crc_mask = mcu3_sb_lane_mask;
13294 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps3_crc_mask = mcu3_sb_lane_mask;
13295 end
13296 if (mcu3_sb_bit_time_mask[4]) begin
13297 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps4_crc_mask = mcu3_sb_lane_mask;
13298 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps4_crc_mask = mcu3_sb_lane_mask;
13299 end
13300 if (mcu3_sb_bit_time_mask[5]) begin
13301 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps5_crc_mask = mcu3_sb_lane_mask;
13302 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps5_crc_mask = mcu3_sb_lane_mask;
13303 end
13304 if (mcu3_sb_bit_time_mask[6]) begin
13305 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps6_crc_mask = mcu3_sb_lane_mask;
13306 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps6_crc_mask = mcu3_sb_lane_mask;
13307 end
13308 if (mcu3_sb_bit_time_mask[7]) begin
13309 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps7_crc_mask = mcu3_sb_lane_mask;
13310 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps7_crc_mask = mcu3_sb_lane_mask;
13311 end
13312 if (mcu3_sb_bit_time_mask[8]) begin
13313 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps8_crc_mask = mcu3_sb_lane_mask;
13314 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps8_crc_mask = mcu3_sb_lane_mask;
13315 end
13316 if (mcu3_sb_bit_time_mask[9]) begin
13317 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps9_crc_mask = mcu3_sb_lane_mask;
13318 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps9_crc_mask = mcu3_sb_lane_mask;
13319 end
13320 if (mcu3_sb_bit_time_mask[10]) begin
13321 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps10_crc_mask = mcu3_sb_lane_mask;
13322 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps10_crc_mask = mcu3_sb_lane_mask;
13323 end
13324 if (mcu3_sb_bit_time_mask[11]) begin
13325 force tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps11_crc_mask = mcu3_sb_lane_mask;
13326 force tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps11_crc_mask = mcu3_sb_lane_mask;
13327 end
13328 end
13329
13330 if (mcu3_inject_fbu_err && !mcu3_esr_fbu)
13331 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH0 SB - MCU3 (mcu3_sb_bit_time_mask[11:0] is %b, mcu3_sb_lane_mask[9:0] is %b)",mcu3_sb_bit_time_mask,mcu3_sb_lane_mask);
13332 else if (!mcu3_esr_fbr)
13333 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH0 SB - MCU3 (mcu3_sb_bit_time_mask[11:0] is %b, mcu3_sb_lane_mask[9:0] is %b)",mcu3_sb_bit_time_mask,mcu3_sb_lane_mask);
13334
13335 end
13336
13337 if (mcu3_enable_ch1_err_inj) begin
13338 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_freq = 12'h1;
13339 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_period = 12'h1;
13340 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_frame_num = 12'h1;
13341
13342 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_freq = 12'h1;
13343 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_period = 12'h1;
13344 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_frame_num = 12'h1;
13345
13346 if (mcu3_sb_err_random) begin
13347 if (mcu3_sb_bit_time_mask[0]) begin
13348 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps0_crc_mask = mcu3_sb_lane_mask;
13349 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps0_crc_mask = mcu3_sb_lane_mask;
13350 end
13351 if (mcu3_sb_bit_time_mask[1]) begin
13352 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps1_crc_mask = mcu3_sb_lane_mask;
13353 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps1_crc_mask = mcu3_sb_lane_mask;
13354 end
13355 if (mcu3_sb_bit_time_mask[2]) begin
13356 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps2_crc_mask = mcu3_sb_lane_mask;
13357 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps2_crc_mask = mcu3_sb_lane_mask;
13358 end
13359 if (mcu3_sb_bit_time_mask[3]) begin
13360 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps3_crc_mask = mcu3_sb_lane_mask;
13361 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps3_crc_mask = mcu3_sb_lane_mask;
13362 end
13363 if (mcu3_sb_bit_time_mask[4]) begin
13364 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps4_crc_mask = mcu3_sb_lane_mask;
13365 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps4_crc_mask = mcu3_sb_lane_mask;
13366 end
13367 if (mcu3_sb_bit_time_mask[5]) begin
13368 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps5_crc_mask = mcu3_sb_lane_mask;
13369 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps5_crc_mask = mcu3_sb_lane_mask;
13370 end
13371 if (mcu3_sb_bit_time_mask[6]) begin
13372 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps6_crc_mask = mcu3_sb_lane_mask;
13373 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps6_crc_mask = mcu3_sb_lane_mask;
13374 end
13375 if (mcu3_sb_bit_time_mask[7]) begin
13376 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps7_crc_mask = mcu3_sb_lane_mask;
13377 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps7_crc_mask = mcu3_sb_lane_mask;
13378 end
13379 if (mcu3_sb_bit_time_mask[8]) begin
13380 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps8_crc_mask = mcu3_sb_lane_mask;
13381 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps8_crc_mask = mcu3_sb_lane_mask;
13382 end
13383 if (mcu3_sb_bit_time_mask[9]) begin
13384 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps9_crc_mask = mcu3_sb_lane_mask;
13385 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps9_crc_mask = mcu3_sb_lane_mask;
13386 end
13387 if (mcu0_sb_bit_time_mask[10]) begin
13388 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps10_crc_mask = mcu0_sb_lane_mask;
13389 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps10_crc_mask = mcu0_sb_lane_mask;
13390 end
13391 if (mcu0_sb_bit_time_mask[11]) begin
13392 force tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps11_crc_mask = mcu0_sb_lane_mask;
13393 force tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps11_crc_mask = mcu0_sb_lane_mask;
13394 end
13395 end
13396
13397 if (mcu3_inject_fbu_err && !mcu3_esr_fbu)
13398 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBU on CH1 SB - MCU3 (mcu3_sb_bit_time_mask[11:0] is %b, mcu3_sb_lane_mask[9:0] is %b)",mcu3_sb_bit_time_mask,mcu3_sb_lane_mask);
13399 else if (!mcu3_esr_fbr)
13400 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: Will inject FBR on CH1 SB - MCU3 (mcu3_sb_bit_time_mask[11:0] is %b, mcu3_sb_lane_mask[9:0] is %b)",mcu3_sb_bit_time_mask,mcu3_sb_lane_mask);
13401
13402 end
13403
13404 repeat (1) @ (posedge sclk);
13405
13406 release tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_freq;
13407 release tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_crc_period;
13408 release tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_frame_num;
13409
13410 release tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_freq;
13411 release tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_crc_period;
13412 release tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_frame_num;
13413
13414 release tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_freq;
13415 release tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_crc_period;
13416 release tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_frame_num;
13417
13418 release tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_freq;
13419 release tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_crc_period;
13420 release tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_frame_num;
13421
13422 inject_crc_mcu3_sb_mask=0;
13423 if (mcu3_sb_err_random==0)
13424 mcu3_sb_channel_error_cnt=mcu3_sb_channel_error_cnt - 1;
13425 else begin
13426 mcu3_sb_err_enable = 0;
13427 mcu3_sb_lane_mask = 10'h1;
13428 mcu3_sb_bit_time_mask = 12'h1;
13429 end
13430 end
13431end
13432end
13433
13434`endif
13435
13436
13437//--------------------------------
13438// FBD Channel Error Checkers
13439//-------------------------------
13440
13441// --- FBR ---
13442
13443// --- MCU0 ---
13444
13445reg mcu0_l2t0_scb_secc_err_detected, mcu0_l2t1_scb_secc_err_detected;
13446
13447always @ (posedge (mcu0_esr_fbr && enabled))
13448begin
13449 @ (negedge drl2clk);
13450 repeat (2) @ (negedge l2clk);
13451 if ((mcu0_syndrome_AA || mcu0_syndrome_AF || mcu0_syndrome_SPE) && `MCU0.mcu_l2t0_data_vld_r0) begin
13452 if (mcu0_l2t0_scb_secc_err==1) mcu0_l2t0_scb_secc_err_detected = 1'b1;
13453 @ (negedge l2clk); if (mcu0_l2t0_scb_secc_err==1) mcu0_l2t0_scb_secc_err_detected = 1'b1;
13454 @ (negedge l2clk); if (mcu0_l2t0_scb_secc_err==1) mcu0_l2t0_scb_secc_err_detected = 1'b1;
13455 if (mcu0_l2t0_scb_secc_err_detected)
13456 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: mcu_l2t0_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13457 else
13458 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu_l2t0_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13459 @ (negedge l2clk);
13460 mcu0_l2t0_scb_secc_err_detected = 1'b0;
13461 end
13462
13463 if ((mcu0_syndrome_AA || mcu0_syndrome_AF || mcu0_syndrome_SPE) && `MCU0.mcu_l2t1_data_vld_r0) begin
13464 if (mcu0_l2t1_scb_secc_err==1) mcu0_l2t1_scb_secc_err_detected = 1'b1;
13465 @ (negedge l2clk); if (mcu0_l2t1_scb_secc_err==1) mcu0_l2t1_scb_secc_err_detected = 1'b1;
13466 @ (negedge l2clk); if (mcu0_l2t1_scb_secc_err==1) mcu0_l2t1_scb_secc_err_detected = 1'b1;
13467 if (mcu0_l2t1_scb_secc_err_detected)
13468 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: mcu_l2t1_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13469 else
13470 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu_l2t1_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13471 @ (negedge l2clk);
13472 mcu0_l2t1_scb_secc_err_detected = 1'b0;
13473 end
13474end
13475
13476always @ (posedge (mcu0_esr_fbr && enabled))
13477begin
13478 @ (negedge drl2clk);
13479 @ (posedge `MCU0.rdata.rdata_ddr_cmp_sync_en_d2);
13480#10;
13481 if (mcu0_syndrome_C && `MCU0.mcu_l2t0_data_vld_r0) begin
13482
13483 if (mcu0_l2t0_scb_secc_err!=1)
13484 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu_l2t0_scb_secc_err not asserted when FBR (C) is logged");
13485 else
13486 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: mcu_l2t0_scb_secc_err asserted when FBR (C) is logged");
13487 end
13488 if (mcu0_syndrome_C && `MCU0.mcu_l2t1_data_vld_r0) begin
13489 if (mcu0_l2t1_scb_secc_err!=1)
13490 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu_l2t1_scb_secc_err not asserted when FBR (C) is logged");
13491 else
13492 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: mcu_l2t1_scb_secc_err asserted when FBR (C) is logged");
13493 end
13494end
13495
13496// --- MCU1 ---
13497
13498reg mcu1_l2t0_scb_secc_err_detected, mcu1_l2t1_scb_secc_err_detected;
13499
13500always @ (posedge (mcu1_esr_fbr && enabled))
13501begin
13502 @ (negedge drl2clk);
13503 repeat (2) @ (negedge l2clk);
13504 if ((mcu1_syndrome_AA || mcu1_syndrome_AF || mcu1_syndrome_SPE) && `MCU1.mcu_l2t0_data_vld_r0) begin
13505 if (mcu1_l2t0_scb_secc_err==1) mcu1_l2t0_scb_secc_err_detected = 1'b1;
13506 @ (negedge l2clk); if (mcu1_l2t0_scb_secc_err==1) mcu1_l2t0_scb_secc_err_detected = 1'b1;
13507 @ (negedge l2clk); if (mcu1_l2t0_scb_secc_err==1) mcu1_l2t0_scb_secc_err_detected = 1'b1;
13508 if (mcu1_l2t0_scb_secc_err_detected)
13509 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: mcu_l2t0_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13510 else
13511 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu_l2t0_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13512 @ (negedge l2clk);
13513 mcu1_l2t0_scb_secc_err_detected = 1'b0;
13514 end
13515
13516 if ((mcu1_syndrome_AA || mcu1_syndrome_AF || mcu1_syndrome_SPE) && `MCU1.mcu_l2t1_data_vld_r0) begin
13517 if (mcu1_l2t1_scb_secc_err==1) mcu1_l2t1_scb_secc_err_detected = 1'b1;
13518 @ (negedge l2clk); if (mcu1_l2t1_scb_secc_err==1) mcu1_l2t1_scb_secc_err_detected = 1'b1;
13519 @ (negedge l2clk); if (mcu1_l2t1_scb_secc_err==1) mcu1_l2t1_scb_secc_err_detected = 1'b1;
13520 if (mcu1_l2t1_scb_secc_err_detected)
13521 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: mcu_l2t1_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13522 else
13523 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu_l2t1_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13524 @ (negedge l2clk);
13525 mcu1_l2t1_scb_secc_err_detected = 1'b0;
13526 end
13527end
13528
13529always @ (posedge (mcu1_esr_fbr && enabled))
13530begin
13531 @ (negedge drl2clk);
13532 @ (posedge `MCU1.rdata.rdata_ddr_cmp_sync_en_d2);
13533#10;
13534 if (mcu1_syndrome_C && `MCU1.mcu_l2t0_data_vld_r0) begin
13535 if (mcu1_l2t0_scb_secc_err!=1)
13536 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu_l2t0_scb_secc_err not asserted when FBR (C) is logged");
13537 else
13538 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: mcu_l2t0_scb_secc_err asserted when FBR (C) is logged");
13539 end
13540 if (mcu1_syndrome_C && `MCU1.mcu_l2t1_data_vld_r0) begin
13541 if (mcu1_l2t1_scb_secc_err!=1)
13542 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu_l2t1_scb_secc_err not asserted when FBR (C) is logged");
13543 else
13544 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: mcu_l2t1_scb_secc_err asserted when FBR (C) is logged");
13545 end
13546end
13547
13548// --- MCU2 ---
13549
13550reg mcu2_l2t0_scb_secc_err_detected, mcu2_l2t1_scb_secc_err_detected;
13551
13552always @ (posedge (mcu2_esr_fbr && enabled))
13553begin
13554 @ (negedge drl2clk);
13555 repeat (2) @ (negedge l2clk);
13556 if ((mcu2_syndrome_AA || mcu2_syndrome_AF || mcu2_syndrome_SPE) && `MCU2.mcu_l2t0_data_vld_r0) begin
13557 if (mcu2_l2t0_scb_secc_err==1) mcu2_l2t0_scb_secc_err_detected = 1'b1;
13558 @ (negedge l2clk); if (mcu2_l2t0_scb_secc_err==1) mcu2_l2t0_scb_secc_err_detected = 1'b1;
13559 @ (negedge l2clk); if (mcu2_l2t0_scb_secc_err==1) mcu2_l2t0_scb_secc_err_detected = 1'b1;
13560 if (mcu2_l2t0_scb_secc_err_detected)
13561 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: mcu_l2t0_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13562 else
13563 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu_l2t0_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13564 @ (negedge l2clk);
13565 mcu2_l2t0_scb_secc_err_detected = 1'b0;
13566 end
13567
13568 if ((mcu2_syndrome_AA || mcu2_syndrome_AF || mcu2_syndrome_SPE) && `MCU2.mcu_l2t1_data_vld_r0) begin
13569 if (mcu2_l2t1_scb_secc_err==1) mcu2_l2t1_scb_secc_err_detected = 1'b1;
13570 @ (negedge l2clk); if (mcu2_l2t1_scb_secc_err==1) mcu2_l2t1_scb_secc_err_detected = 1'b1;
13571 @ (negedge l2clk); if (mcu2_l2t1_scb_secc_err==1) mcu2_l2t1_scb_secc_err_detected = 1'b1;
13572 if (mcu2_l2t1_scb_secc_err_detected)
13573 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: mcu_l2t1_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13574 else
13575 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu_l2t1_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13576 @ (negedge l2clk);
13577 mcu2_l2t1_scb_secc_err_detected = 1'b0;
13578 end
13579end
13580
13581always @ (posedge (mcu2_esr_fbr && enabled))
13582begin
13583 @ (negedge drl2clk);
13584 @ (posedge `MCU2.rdata.rdata_ddr_cmp_sync_en_d2);
13585#10;
13586 if (mcu2_syndrome_C && `MCU2.mcu_l2t0_data_vld_r0) begin
13587 if (mcu2_l2t0_scb_secc_err!=1)
13588 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu_l2t0_scb_secc_err not asserted when FBR (C) is logged");
13589 else
13590 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: mcu_l2t0_scb_secc_err asserted when FBR (C) is logged");
13591 end
13592 if (mcu2_syndrome_C && `MCU2.mcu_l2t1_data_vld_r0) begin
13593 if (mcu2_l2t1_scb_secc_err!=1)
13594 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu_l2t1_scb_secc_err not asserted when FBR (C) is logged");
13595 else
13596 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: mcu_l2t1_scb_secc_err asserted when FBR (C) is logged");
13597 end
13598end
13599
13600// --- MCU3 ---
13601
13602reg mcu3_l2t0_scb_secc_err_detected, mcu3_l2t1_scb_secc_err_detected;
13603
13604always @ (posedge (mcu3_esr_fbr && enabled))
13605begin
13606 @ (negedge drl2clk);
13607 repeat (2) @ (negedge l2clk);
13608 if ((mcu3_syndrome_AA || mcu3_syndrome_AF || mcu3_syndrome_SPE) && `MCU3.mcu_l2t0_data_vld_r0) begin
13609 if (mcu3_l2t0_scb_secc_err==1) mcu3_l2t0_scb_secc_err_detected = 1'b1;
13610 @ (negedge l2clk); if (mcu3_l2t0_scb_secc_err==1) mcu3_l2t0_scb_secc_err_detected = 1'b1;
13611 @ (negedge l2clk); if (mcu3_l2t0_scb_secc_err==1) mcu3_l2t0_scb_secc_err_detected = 1'b1;
13612 if (mcu3_l2t0_scb_secc_err_detected)
13613 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: mcu_l2t0_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13614 else
13615 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu_l2t0_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13616 @ (negedge l2clk);
13617 mcu3_l2t0_scb_secc_err_detected = 1'b0;
13618 end
13619
13620 if ((mcu3_syndrome_AA || mcu3_syndrome_AF || mcu3_syndrome_SPE) && `MCU3.mcu_l2t1_data_vld_r0) begin
13621 if (mcu3_l2t1_scb_secc_err==1) mcu3_l2t1_scb_secc_err_detected = 1'b1;
13622 @ (negedge l2clk); if (mcu3_l2t1_scb_secc_err==1) mcu3_l2t1_scb_secc_err_detected = 1'b1;
13623 @ (negedge l2clk); if (mcu3_l2t1_scb_secc_err==1) mcu3_l2t1_scb_secc_err_detected = 1'b1;
13624 if (mcu3_l2t1_scb_secc_err_detected)
13625 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: mcu_l2t1_scb_secc_err asserted when FBR (AA/AF/SPE) is logged");
13626 else
13627 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu_l2t1_scb_secc_err not asserted when FBR (AA/AF/SPE) is logged");
13628 @ (negedge l2clk);
13629 mcu3_l2t1_scb_secc_err_detected = 1'b0;
13630 end
13631end
13632
13633always @ (posedge (mcu3_esr_fbr && enabled))
13634begin
13635 @ (negedge drl2clk);
13636 @ (posedge `MCU3.rdata.rdata_ddr_cmp_sync_en_d2);
13637#10;
13638 if (mcu3_syndrome_C && `MCU3.mcu_l2t0_data_vld_r0) begin
13639 if (mcu3_l2t0_scb_secc_err!=1)
13640 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu_l2t0_scb_secc_err not asserted when FBR (C) is logged");
13641 else
13642 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: mcu_l2t0_scb_secc_err asserted when FBR (C) is logged");
13643 end
13644 if (mcu3_syndrome_C && `MCU3.mcu_l2t1_data_vld_r0) begin
13645 if (mcu3_l2t1_scb_secc_err!=1)
13646 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu_l2t1_scb_secc_err not asserted when FBR (C) is logged");
13647 else
13648 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: mcu_l2t1_scb_secc_err asserted when FBR (C) is logged");
13649 end
13650end
13651
13652// --- FBU ---
13653
13654// --- MCU0 ---
13655
13656always @ (posedge (mcu0_esr_fbu && enabled && mcu0_fbdic_chnl_reset_error))
13657if (mcu0_synd_C)
13658begin
13659 // --- mcu0_l2t0_mecc_err_r3 or mcu0_l2t1_mecc_err_r3 or mcu0_l2t0_scb_mecc_err or mcu0_l2t1_scb_mecc_err assertion check : Window of 12 l2clks ---
13660 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13661 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13662 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13663 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13664 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13665 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13666 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13667 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13668 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13669 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13670 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13671 @ (negedge l2clk); if (mcu0_l2t0_mecc_err_r3==1 || mcu0_l2t1_mecc_err_r3==1 || mcu0_l2t0_scb_mecc_err || mcu0_l2t1_scb_mecc_err) mcu0_l2t_mecc_err_r3_detected = 1'b1;
13672 if (~mcu0_l2t_mecc_err_r3_detected)
13673 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu_l2t0_mecc_err_r3 or mcu_l2t1_mecc_err_r3 or mcu_l2t1_scb_mecc_err or mcu_l2t1_scb_mecc_err not asserted when ESR.FBU and SYND.C is logged");
13674 @ (negedge l2clk);
13675 mcu0_l2t_mecc_err_r3_detected = 1'b0;
13676end
13677
13678always @ (posedge (mcu0_esr_fbu && mcu0_synd_SPE && ~mcu0_synd_C && enabled)) // FBU.C -> P1
13679begin
13680 // --- mcu0_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13681 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13682 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13683 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13684 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13685 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13686 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13687 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13688 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13689 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13690 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13691 if (~mcu0_l2t0_scb_mecc_err_detected)
13692 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu0_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.SPE is logged");
13693 @ (negedge l2clk);
13694 mcu0_l2t0_scb_mecc_err_detected = 1'b0;
13695end
13696
13697`ifdef ENABLE_FBU_AF
13698always @ (posedge (mcu0_esr_fbu && mcu0_synd_AF && ~mcu0_synd_C && enabled)) // FBU.C -> P1
13699begin
13700 // --- mcu0_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13701 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13702 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13703 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13704 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13705 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13706 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13707 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13708 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13709 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13710 @ (negedge l2clk); if (mcu0_l2t0_scb_mecc_err==1) mcu0_l2t0_scb_mecc_err_detected = 1'b1;
13711 if (~mcu0_l2t0_scb_mecc_err_detected)
13712 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: mcu0_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.AF is logged");
13713 @ (negedge l2clk);
13714 mcu0_l2t0_scb_mecc_err_detected = 1'b0;
13715end
13716`endif
13717
13718// --- MCU1 ---
13719
13720always @ (posedge (mcu1_esr_fbu && enabled && mcu1_fbdic_chnl_reset_error))
13721if (mcu1_synd_C)
13722begin
13723 // --- mcu1_l2t0_mecc_err_r3 or mcu1_l2t1_mecc_err_r3 or mcu1_l2t0_scb_mecc_err or mcu1_l2t1_scb_mecc_err assertion check : Window of 12 l2clks ---
13724 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13725 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13726 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13727 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13728 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13729 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13730 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13731 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13732 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13733 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13734 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13735 @ (negedge l2clk); if (mcu1_l2t0_mecc_err_r3==1 || mcu1_l2t1_mecc_err_r3==1 || mcu1_l2t0_scb_mecc_err || mcu1_l2t1_scb_mecc_err) mcu1_l2t_mecc_err_r3_detected = 1'b1;
13736 if (~mcu1_l2t_mecc_err_r3_detected)
13737 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu_l2t0_mecc_err_r3 or mcu_l2t1_mecc_err_r3 or mcu_l2t1_scb_mecc_err or mcu_l2t1_scb_mecc_err not asserted when ESR.FBU and SYND.C is logged");
13738 @ (negedge l2clk);
13739 mcu1_l2t_mecc_err_r3_detected = 1'b0;
13740end
13741
13742always @ (posedge (mcu1_esr_fbu && mcu1_synd_SPE && ~mcu1_synd_C && enabled)) // FBU.C -> P1
13743begin
13744 // --- mcu1_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13745 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13746 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13747 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13748 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13749 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13750 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13751 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13752 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13753 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13754 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13755 if (~mcu1_l2t0_scb_mecc_err_detected)
13756 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu1_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.SPE is logged");
13757 @ (negedge l2clk);
13758 mcu1_l2t0_scb_mecc_err_detected = 1'b0;
13759end
13760
13761`ifdef ENABLE_FBU_AF
13762always @ (posedge (mcu1_esr_fbu && mcu1_synd_AF && ~mcu1_synd_C && enabled)) // FBU.C -> P1
13763begin
13764 // --- mcu1_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13765 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13766 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13767 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13768 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13769 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13770 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13771 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13772 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13773 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13774 @ (negedge l2clk); if (mcu1_l2t0_scb_mecc_err==1) mcu1_l2t0_scb_mecc_err_detected = 1'b1;
13775 if (~mcu1_l2t0_scb_mecc_err_detected)
13776 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: mcu1_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.AF is logged");
13777 @ (negedge l2clk);
13778 mcu1_l2t0_scb_mecc_err_detected = 1'b0;
13779end
13780`endif
13781
13782// --- MCU2 ---
13783
13784always @ (posedge (mcu2_esr_fbu && enabled && mcu2_fbdic_chnl_reset_error))
13785if (mcu2_synd_C)
13786begin
13787 // --- mcu2_l2t0_mecc_err_r3 or mcu2_l2t1_mecc_err_r3 or mcu2_l2t0_scb_mecc_err or mcu2_l2t1_scb_mecc_err assertion check : Window of 12 l2clks ---
13788 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13789 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13790 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13791 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13792 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13793 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13794 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13795 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13796 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13797 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13798 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13799 @ (negedge l2clk); if (mcu2_l2t0_mecc_err_r3==1 || mcu2_l2t1_mecc_err_r3==1 || mcu2_l2t0_scb_mecc_err || mcu2_l2t1_scb_mecc_err) mcu2_l2t_mecc_err_r3_detected = 1'b1;
13800 if (~mcu2_l2t_mecc_err_r3_detected)
13801 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu_l2t0_mecc_err_r3 or mcu_l2t1_mecc_err_r3 or mcu_l2t1_scb_mecc_err or mcu_l2t1_scb_mecc_err not asserted when ESR.FBU and SYND.C is logged");
13802 @ (negedge l2clk);
13803 mcu2_l2t_mecc_err_r3_detected = 1'b0;
13804end
13805
13806always @ (posedge (mcu2_esr_fbu && mcu2_synd_SPE && ~mcu2_synd_C && enabled)) // FBU.C -> P1
13807begin
13808 // --- mcu2_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13809 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13810 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13811 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13812 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13813 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13814 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13815 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13816 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13817 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13818 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13819 if (~mcu2_l2t0_scb_mecc_err_detected)
13820 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu2_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.SPE is logged");
13821 @ (negedge l2clk);
13822 mcu2_l2t0_scb_mecc_err_detected = 1'b0;
13823end
13824
13825`ifdef ENABLE_FBU_AF
13826always @ (posedge (mcu2_esr_fbu && mcu2_synd_AF && ~mcu2_synd_C && enabled)) // FBU.C -> P1
13827begin
13828 // --- mcu2_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13829 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13830 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13831 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13832 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13833 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13834 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13835 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13836 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13837 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13838 @ (negedge l2clk); if (mcu2_l2t0_scb_mecc_err==1) mcu2_l2t0_scb_mecc_err_detected = 1'b1;
13839 if (~mcu2_l2t0_scb_mecc_err_detected)
13840 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: mcu2_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.AF is logged");
13841 @ (negedge l2clk);
13842 mcu2_l2t0_scb_mecc_err_detected = 1'b0;
13843end
13844`endif
13845
13846// --- MCU3 ---
13847
13848always @ (posedge (mcu3_esr_fbu && enabled && mcu3_fbdic_chnl_reset_error))
13849if (mcu3_synd_C)
13850begin
13851 // --- mcu3_l2t0_mecc_err_r3 or mcu3_l2t1_mecc_err_r3 or mcu3_l2t0_scb_mecc_err or mcu3_l2t1_scb_mecc_err assertion check : Window of 12 l2clks ---
13852 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13853 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13854 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13855 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13856 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13857 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13858 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13859 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13860 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13861 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13862 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13863 @ (negedge l2clk); if (mcu3_l2t0_mecc_err_r3==1 || mcu3_l2t1_mecc_err_r3==1 || mcu3_l2t0_scb_mecc_err || mcu3_l2t1_scb_mecc_err) mcu3_l2t_mecc_err_r3_detected = 1'b1;
13864 if (~mcu3_l2t_mecc_err_r3_detected)
13865 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu_l2t0_mecc_err_r3 or mcu_l2t1_mecc_err_r3 or mcu_l2t1_scb_mecc_err or mcu_l2t1_scb_mecc_err not asserted when ESR.FBU and SYND.C is logged");
13866 @ (negedge l2clk);
13867 mcu3_l2t_mecc_err_r3_detected = 1'b0;
13868end
13869
13870always @ (posedge (mcu3_esr_fbu && mcu3_synd_SPE && ~mcu3_synd_C && enabled)) // FBU.C -> P1
13871begin
13872 // --- mcu3_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13873 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13874 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13875 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13876 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13877 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13878 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13879 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13880 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13881 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13882 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13883 if (~mcu3_l2t0_scb_mecc_err_detected)
13884 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu3_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.SPE is logged");
13885 @ (negedge l2clk);
13886 mcu3_l2t0_scb_mecc_err_detected = 1'b0;
13887end
13888
13889`ifdef ENABLE_FBU_AF
13890always @ (posedge (mcu3_esr_fbu && mcu3_synd_AF && ~mcu3_synd_C && enabled)) // FBU.C -> P1
13891begin
13892 // --- mcu3_l2t0_scb_mecc_err assertion check : Window of 10 l2clks
13893 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13894 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13895 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13896 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13897 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13898 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13899 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13900 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13901 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13902 @ (negedge l2clk); if (mcu3_l2t0_scb_mecc_err==1) mcu3_l2t0_scb_mecc_err_detected = 1'b1;
13903 if (~mcu3_l2t0_scb_mecc_err_detected)
13904 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: mcu3_l2t0_scb_mecc_err not asserted when ESR.FBU and SYND.AF is logged");
13905 @ (negedge l2clk);
13906 mcu3_l2t0_scb_mecc_err_detected = 1'b0;
13907end
13908`endif
13909
13910//-----------------------------------
13911// Disable mcu_fmon during Warm Reset
13912//-----------------------------------
13913
13914`ifdef MCUSAT
13915always @ (posedge rst_wmr_protect)
13916begin
13917 if (!($test$plusargs("mcu_fmon_disable"))) begin
13918 enabled = 1'b0;
13919 fbd_init_check = 1'b0;
13920 end
13921end
13922
13923always @ (negedge rst_wmr_protect)
13924begin
13925 if (!($test$plusargs("mcu_fmon_disable")))
13926 enabled = 1'b1;
13927end
13928`else
13929always @ (tb_top.flush_reset_complete)
13930begin
13931 if (tb_top.flush_reset_complete == 1'b0) begin
13932 if (!($test$plusargs("mcu_fmon_disable"))) begin
13933 enabled = 1'b0;
13934 fbd_init_check = 1'b0;
13935
13936 // --- reset all reg variables used in this monitor/checker
13937
13938 mcu0_start_pd_check_0 = 0;
13939 mcu0_start_pd_check_1 = 0;
13940 mcu0_start_pd_check_2 = 0;
13941 mcu0_start_pd_check_3 = 0;
13942 mcu0_start_pd_check_4 = 0;
13943 mcu0_start_pd_check_5 = 0;
13944 mcu0_start_pd_check_6 = 0;
13945 mcu0_start_pd_check_7 = 0;
13946 mcu0_start_pd_check_8 = 0;
13947 mcu0_start_pd_check_9 = 0;
13948 mcu0_start_pd_check_a = 0;
13949 mcu0_start_pd_check_b = 0;
13950 mcu0_start_pd_check_c = 0;
13951 mcu0_start_pd_check_d = 0;
13952 mcu0_start_pd_check_e = 0;
13953 mcu0_start_pd_check_f = 0;
13954
13955 mcu0_drif_dram_ras_addr_a = 16'h0;
13956 mcu0_drif_dram_ras_addr_b = 16'h0;
13957 mcu0_drif_dram_ras_addr_c = 16'h0;
13958 mcu1_drif_dram_ras_addr_a = 16'h0;
13959 mcu1_drif_dram_ras_addr_b = 16'h0;
13960 mcu1_drif_dram_ras_addr_c = 16'h0;
13961 mcu2_drif_dram_ras_addr_a = 16'h0;
13962 mcu2_drif_dram_ras_addr_b = 16'h0;
13963 mcu2_drif_dram_ras_addr_c = 16'h0;
13964 mcu3_drif_dram_ras_addr_a = 16'h0;
13965 mcu3_drif_dram_ras_addr_b = 16'h0;
13966 mcu3_drif_dram_ras_addr_c = 16'h0;
13967
13968 mcu0_physical_addr_a = 40'h0;
13969 mcu0_physical_addr_b = 40'h0;
13970 mcu0_physical_addr_c = 40'h0;
13971 mcu1_physical_addr_a = 40'h0;
13972 mcu1_physical_addr_b = 40'h0;
13973 mcu1_physical_addr_c = 40'h0;
13974 mcu2_physical_addr_a = 40'h0;
13975 mcu2_physical_addr_b = 40'h0;
13976 mcu2_physical_addr_c = 40'h0;
13977 mcu3_physical_addr_a = 40'h0;
13978 mcu3_physical_addr_b = 40'h0;
13979 mcu3_physical_addr_c = 40'h0;
13980
13981 sync_frame_UI_err_0a = 12'h0;
13982 sync_frame_UI_err_0b = 12'h0;
13983 sync_frame_UI_err_1a = 12'h0;
13984 sync_frame_UI_err_1b = 12'h0;
13985 sync_frame_UI_err_2a = 12'h0;
13986 sync_frame_UI_err_2b = 12'h0;
13987 sync_frame_UI_err_3a = 12'h0;
13988 sync_frame_UI_err_3b = 12'h0;
13989
13990 mcu0_drif_dram_cmd_a_prev = 3'b0;
13991 mcu0_drif_dram_cmd_b_prev = 3'b0;
13992 mcu0_drif_dram_cmd_c_prev = 3'b0;
13993 mcu1_drif_dram_cmd_a_prev = 3'b0;
13994 mcu1_drif_dram_cmd_b_prev = 3'b0;
13995 mcu1_drif_dram_cmd_c_prev = 3'b0;
13996 mcu2_drif_dram_cmd_a_prev = 3'b0;
13997 mcu2_drif_dram_cmd_b_prev = 3'b0;
13998 mcu2_drif_dram_cmd_c_prev = 3'b0;
13999 mcu3_drif_dram_cmd_a_prev = 3'b0;
14000 mcu3_drif_dram_cmd_b_prev = 3'b0;
14001 mcu3_drif_dram_cmd_c_prev = 3'b0;
14002
14003 mcu0_drif_ucb_wr_req_vld_REG = 1'b0;
14004 mcu1_drif_ucb_wr_req_vld_REG = 1'b0;
14005 mcu2_drif_ucb_wr_req_vld_REG = 1'b0;
14006 mcu3_drif_ucb_wr_req_vld_REG = 1'b0;
14007
14008 mcu0_drif_ucb_rd_req_vld_REG = 1'b0;
14009 mcu1_drif_ucb_rd_req_vld_REG = 1'b0;
14010 mcu2_drif_ucb_rd_req_vld_REG = 1'b0;
14011 mcu3_drif_ucb_rd_req_vld_REG = 1'b0;
14012
14013 mcu0_drif_dram_cmd_a_REG = 3'b0;
14014 mcu0_drif_dram_cmd_b_REG = 3'b0;
14015 mcu0_drif_dram_cmd_c_REG = 3'b0;
14016 mcu1_drif_dram_cmd_a_REG = 3'b0;
14017 mcu1_drif_dram_cmd_b_REG = 3'b0;
14018 mcu1_drif_dram_cmd_c_REG = 3'b0;
14019 mcu2_drif_dram_cmd_a_REG = 3'b0;
14020 mcu2_drif_dram_cmd_b_REG = 3'b0;
14021 mcu2_drif_dram_cmd_c_REG = 3'b0;
14022 mcu3_drif_dram_cmd_a_REG = 3'b0;
14023 mcu3_drif_dram_cmd_b_REG = 3'b0;
14024 mcu3_drif_dram_cmd_c_REG = 3'b0;
14025 end
14026 end
14027 if (tb_top.flush_reset_complete == 1'b1)
14028 if (!($test$plusargs("mcu_fmon_disable")))
14029 enabled = 1'b1;
14030end
14031`endif
14032
14033
14034//-------------------------------------------------------
14035// NB FAILOVER LANE - MCU AUTO RECONFIGURION TESTING
14036//-------------------------------------------------------
14037
14038initial
14039begin
14040 @ (posedge drl2clk);
14041
14042 if ($test$plusargs("fbdimm0a_nblane0_stuckat1")) force tb_top.fbdimm0a_rx_p_top[0] = 1'b1;
14043 if ($test$plusargs("fbdimm0b_nblane0_stuckat1")) force tb_top.fbdimm0b_rx_p_top[0] = 1'b1;
14044
14045 if ($test$plusargs("fbdimm0a_nblane1_stuckat1")) force tb_top.fbdimm0a_rx_p_top[1] = 1'b1;
14046 if ($test$plusargs("fbdimm0b_nblane1_stuckat1")) force tb_top.fbdimm0b_rx_p_top[1] = 1'b1;
14047
14048 if ($test$plusargs("fbdimm0a_nblane2_stuckat1")) force tb_top.fbdimm0a_rx_p_top[2] = 1'b1;
14049 if ($test$plusargs("fbdimm0b_nblane2_stuckat1")) force tb_top.fbdimm0b_rx_p_top[2] = 1'b1;
14050
14051 if ($test$plusargs("fbdimm0a_nblane3_stuckat1")) force tb_top.fbdimm0a_rx_p_top[3] = 1'b1;
14052 if ($test$plusargs("fbdimm0b_nblane3_stuckat1")) force tb_top.fbdimm0b_rx_p_top[3] = 1'b1;
14053
14054 if ($test$plusargs("fbdimm0a_nblane4_stuckat1")) force tb_top.fbdimm0a_rx_p_top[4] = 1'b1;
14055 if ($test$plusargs("fbdimm0b_nblane4_stuckat1")) force tb_top.fbdimm0b_rx_p_top[4] = 1'b1;
14056
14057 if ($test$plusargs("fbdimm0a_nblane5_stuckat1")) force tb_top.fbdimm0a_rx_p_top[5] = 1'b1;
14058 if ($test$plusargs("fbdimm0b_nblane5_stuckat1")) force tb_top.fbdimm0b_rx_p_top[5] = 1'b1;
14059
14060 if ($test$plusargs("fbdimm0a_nblane6_stuckat1")) force tb_top.fbdimm0a_rx_p_top[6] = 1'b1;
14061 if ($test$plusargs("fbdimm0b_nblane6_stuckat1")) force tb_top.fbdimm0b_rx_p_top[6] = 1'b1;
14062
14063 if ($test$plusargs("fbdimm0a_nblane7_stuckat1")) force tb_top.fbdimm0a_rx_p_top[7] = 1'b1;
14064 if ($test$plusargs("fbdimm0b_nblane7_stuckat1")) force tb_top.fbdimm0b_rx_p_top[7] = 1'b1;
14065
14066 if ($test$plusargs("fbdimm0a_nblane8_stuckat1")) force tb_top.fbdimm0a_rx_p_top[8] = 1'b1;
14067 if ($test$plusargs("fbdimm0b_nblane8_stuckat1")) force tb_top.fbdimm0b_rx_p_top[8] = 1'b1;
14068
14069 if ($test$plusargs("fbdimm0a_nblane9_stuckat1")) force tb_top.fbdimm0a_rx_p_top[9] = 1'b1;
14070 if ($test$plusargs("fbdimm0b_nblane9_stuckat1")) force tb_top.fbdimm0b_rx_p_top[9] = 1'b1;
14071
14072 if ($test$plusargs("fbdimm0a_nblane10_stuckat1")) force tb_top.fbdimm0a_rx_p_top[10] = 1'b1;
14073 if ($test$plusargs("fbdimm0b_nblane10_stuckat1")) force tb_top.fbdimm0b_rx_p_top[10] = 1'b1;
14074
14075 if ($test$plusargs("fbdimm0a_nblane11_stuckat1")) force tb_top.fbdimm0a_rx_p_top[11] = 1'b1;
14076 if ($test$plusargs("fbdimm0b_nblane11_stuckat1")) force tb_top.fbdimm0b_rx_p_top[11] = 1'b1;
14077
14078 if ($test$plusargs("fbdimm0a_nblane12_stuckat1")) force tb_top.fbdimm0a_rx_p_top[12] = 1'b1;
14079 if ($test$plusargs("fbdimm0b_nblane12_stuckat1")) force tb_top.fbdimm0b_rx_p_top[12] = 1'b1;
14080
14081 if ($test$plusargs("fbdimm0a_nblane13_stuckat1")) force tb_top.fbdimm0a_rx_p_top[13] = 1'b1;
14082 if ($test$plusargs("fbdimm0b_nblane13_stuckat1")) force tb_top.fbdimm0b_rx_p_top[13] = 1'b1;
14083
14084end
14085
14086//------------------------------------------------------
14087// SB FAILOVER LANE - MCU AUTO RECONFIGURION TESTING
14088//------------------------------------------------------
14089
14090initial
14091begin
14092 @ (posedge drl2clk);
14093
14094 if ($test$plusargs("fbdimm0a_sblane0_stuckat1")) force fbdimm0a_tx_p_top[0] = 1'b1;
14095 if ($test$plusargs("fbdimm0b_sblane0_stuckat1")) force fbdimm0b_tx_p_top[0] = 1'b1;
14096
14097 if ($test$plusargs("fbdimm0a_sblane1_stuckat1")) force fbdimm0a_tx_p_top[1] = 1'b1;
14098 if ($test$plusargs("fbdimm0b_sblane1_stuckat1")) force fbdimm0b_tx_p_top[1] = 1'b1;
14099
14100 if ($test$plusargs("fbdimm0a_sblane2_stuckat1")) force fbdimm0a_tx_p_top[2] = 1'b1;
14101 if ($test$plusargs("fbdimm0b_sblane2_stuckat1")) force fbdimm0b_tx_p_top[2] = 1'b1;
14102
14103 if ($test$plusargs("fbdimm0a_sblane3_stuckat1")) force fbdimm0a_tx_p_top[3] = 1'b1;
14104 if ($test$plusargs("fbdimm0b_sblane3_stuckat1")) force fbdimm0b_tx_p_top[3] = 1'b1;
14105
14106 if ($test$plusargs("fbdimm0a_sblane4_stuckat1")) force fbdimm0a_tx_p_top[4] = 1'b1;
14107 if ($test$plusargs("fbdimm0b_sblane4_stuckat1")) force fbdimm0b_tx_p_top[4] = 1'b1;
14108
14109 if ($test$plusargs("fbdimm0a_sblane5_stuckat1")) force fbdimm0a_tx_p_top[5] = 1'b1;
14110 if ($test$plusargs("fbdimm0b_sblane5_stuckat1")) force fbdimm0b_tx_p_top[5] = 1'b1;
14111
14112 if ($test$plusargs("fbdimm0a_sblane6_stuckat1")) force fbdimm0a_tx_p_top[6] = 1'b1;
14113 if ($test$plusargs("fbdimm0b_sblane6_stuckat1")) force fbdimm0b_tx_p_top[6] = 1'b1;
14114
14115 if ($test$plusargs("fbdimm0a_sblane7_stuckat1")) force fbdimm0a_tx_p_top[7] = 1'b1;
14116 if ($test$plusargs("fbdimm0b_sblane7_stuckat1")) force fbdimm0b_tx_p_top[7] = 1'b1;
14117
14118 if ($test$plusargs("fbdimm0a_sblane8_stuckat1")) force fbdimm0a_tx_p_top[8] = 1'b1;
14119 if ($test$plusargs("fbdimm0b_sblane8_stuckat1")) force fbdimm0b_tx_p_top[8] = 1'b1;
14120
14121 if ($test$plusargs("fbdimm0a_sblane9_stuckat1")) force fbdimm0a_tx_p_top[9] = 1'b1;
14122 if ($test$plusargs("fbdimm0b_sblane9_stuckat1")) force fbdimm0b_tx_p_top[9] = 1'b1;
14123end
14124
14125//-------------------------------------------
14126// SERDES LOOPBACK (Blunt_End) Testing
14127//-------------------------------------------
14128
14129initial
14130begin
14131 #1000;
14132 if ($test$plusargs("SERDES_BLUNTEND")) begin
14133 fork
14134 begin
14135 @ (posedge `MCU0.fbdic.fbdic_loopback[1]);
14136 repeat (10) @ (posedge drl2clk);
14137 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h3fff;
14138 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h0;
14139 repeat (20) @ (posedge drl2clk);
14140 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h0;
14141 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h3fff;
14142 repeat (20) @ (posedge drl2clk);
14143 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h3aaa;
14144 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h0555;
14145 repeat (20) @ (posedge drl2clk);
14146 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h0;
14147 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h3fff;
14148 @ (posedge `MCU0.fbdic.fbdic_loopback[0]);
14149 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h3fff;
14150 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h0;
14151 repeat (20) @ (posedge drl2clk);
14152 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h0;
14153 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h3fff;
14154 repeat (20) @ (posedge drl2clk);
14155 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h3aaf;
14156 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h0550;
14157 repeat (20) @ (posedge drl2clk);
14158 force tb_top.fbdimm0a_rx_p_top[13:0] = 14'h0;
14159 force tb_top.fbdimm0a_rx_n_top[13:0] = 14'h3fff;
14160 end
14161 begin
14162 @ (posedge `MCU0.fbdic.fbdic_loopback[1]);
14163 repeat (20) @ (posedge drl2clk);
14164 if (fbdimm0a_tx_p_top[9:0] != 10'h3ff)
14165 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14166 repeat (20) @ (posedge drl2clk);
14167 if (fbdimm0a_tx_p_top[9:0] != 10'h0)
14168 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14169 repeat (20) @ (posedge drl2clk);
14170 if (fbdimm0a_tx_p_top[9:0] != 10'h2aa)
14171 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14172 repeat (20) @ (posedge drl2clk);
14173 if (fbdimm0a_tx_p_top[9:0] != 10'h0)
14174 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14175 @ (posedge `MCU0.fbdic.fbdic_loopback[0]);
14176 repeat (10) @ (posedge drl2clk);
14177 if (fbdimm0a_tx_p_top[9:0] != 10'h3ff)
14178 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14179 repeat (20) @ (posedge drl2clk);
14180 if (fbdimm0a_tx_p_top[9:0] != 10'h0)
14181 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14182 repeat (20) @ (posedge drl2clk);
14183 if (fbdimm0a_tx_p_top[9:0] != 10'h3aa)
14184 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14185 repeat (20) @ (posedge drl2clk);
14186 if (fbdimm0a_tx_p_top[9:0] != 10'h0)
14187 `PR_ERROR("mcu_fmon", `ERROR, "SERDES Blunt-End Loop Back Test Failed TX != RX");
14188 end
14189 join
14190 end
14191end
14192
14193//-------------------------------------------
14194// SERDES LANE INV Testing
14195//-------------------------------------------
14196
14197initial
14198begin
14199 #1000;
14200 if ($test$plusargs("SERDES_INVERT"))
14201 begin
14202 @ (posedge `MCU0.fbdic.fbdic_fbd_state[0]);
14203 force tb_top.fbdimm0a_rx_p_top = 14'h3fff;
14204 force tb_top.fbdimm0b_rx_p_top = 14'h3fff;
14205
14206 @ (posedge `MCU0.fbdic.fbdic_sds_invert[0]);
14207 repeat (10) @ (posedge drl2clk);
14208 if (fbdimm0a_tx_p_top[9:0] != 10'h0 || fbdimm0b_tx_p_top[9:0] != 10'h0)
14209 `PR_ERROR("mcu_fmon", `ERROR, "TX SERDES Lane Invert Test Failed !!!");
14210 else
14211 `PR_DEBUG("mcu_fmon", `DEBUG, "TX SERDES Lane Invert Test Passed !!!");
14212
14213 if (`CPU.fsr0_mcu0_data != 168'h0 || `CPU.fsr1_mcu0_data != 168'h0)
14214 `PR_ERROR("mcu_fmon", `ERROR, "RX SERDES Lane Invert Test Failed !!!");
14215 else
14216 `PR_DEBUG("mcu_fmon", `DEBUG, "RX SERDES Lane Invert Test Passed !!!");
14217
14218 end
14219end
14220
14221
14222
14223integer mcu0_idle_frame_cnt;
14224integer mcu1_idle_frame_cnt;
14225integer mcu2_idle_frame_cnt;
14226integer mcu3_idle_frame_cnt;
14227
14228reg mcu0_idle_frame_detected;
14229reg mcu1_idle_frame_detected;
14230reg mcu2_idle_frame_detected;
14231reg mcu3_idle_frame_detected;
14232
14233reg idle_frame_checker_enable;
14234
14235initial begin
14236 mcu0_idle_frame_cnt=0;
14237 mcu1_idle_frame_cnt=0;
14238 mcu2_idle_frame_cnt=0;
14239 mcu3_idle_frame_cnt=0;
14240
14241 mcu0_idle_frame_detected=0;
14242 mcu1_idle_frame_detected=0;
14243 mcu2_idle_frame_detected=0;
14244 mcu3_idle_frame_detected=0;
14245
14246 #5;
14247 if (($test$plusargs("RANDOM_ENV")) || ($test$plusargs("RANDOM_PARAM")))
14248 idle_frame_checker_enable = 1;
14249 else
14250 idle_frame_checker_enable = 0;
14251end
14252
14253always @ (posedge drl2clk)
14254if (enabled && idle_frame_checker_enable)
14255begin
14256 if (`MCU0.fbdic.fbdic_l0_state) begin
14257 if (`MCU0.fbdic.fbdic_idle_frame)
14258 mcu0_idle_frame_detected = 1'b1;
14259 mcu0_idle_frame_cnt = mcu0_idle_frame_cnt + 1;
14260 end
14261
14262 if (mcu0_idle_frame_cnt == 200) // expected to see idle frame frame match with in 200 dram clock cycles
14263 begin
14264 if (mcu0_idle_frame_detected == 0)
14265 `PR_ERROR("mcu_fmon", `ERROR, "MCU0 IDLE LFSR is out-of-sync with AMB IDLE LFSR *** N2 T.O. 1.0 BUG 111811 ***");
14266 else begin
14267 mcu0_idle_frame_cnt=0;
14268 mcu0_idle_frame_detected=0;
14269 end
14270 end
14271end
14272
14273always @ (posedge drl2clk)
14274if (enabled && idle_frame_checker_enable)
14275begin
14276 if (`MCU1.fbdic.fbdic_l0_state) begin
14277 if (`MCU1.fbdic.fbdic_idle_frame)
14278 mcu1_idle_frame_detected = 1'b1;
14279 mcu1_idle_frame_cnt = mcu1_idle_frame_cnt + 1;
14280 end
14281
14282 if (mcu1_idle_frame_cnt == 200) // expected to see idle frame frame match with in 200 dram clock cycles
14283 begin
14284 if (mcu1_idle_frame_detected == 0)
14285 `PR_ERROR("mcu_fmon", `ERROR, "MCU1 IDLE LFSR is out-of-sync with AMB IDLE LFSR *** N2 T.O. BUG 111811 ***");
14286 else begin
14287 mcu1_idle_frame_cnt=0;
14288 mcu1_idle_frame_detected=0;
14289 end
14290 end
14291end
14292
14293always @ (posedge drl2clk)
14294if (enabled && idle_frame_checker_enable)
14295begin
14296 if (`MCU2.fbdic.fbdic_l0_state) begin
14297 if (`MCU2.fbdic.fbdic_idle_frame)
14298 mcu2_idle_frame_detected = 1'b1;
14299 mcu2_idle_frame_cnt = mcu2_idle_frame_cnt + 1;
14300 end
14301
14302 if (mcu2_idle_frame_cnt == 200) // expected to see idle frame frame match with in 200 dram clock cycles
14303 begin
14304 if (mcu2_idle_frame_detected == 0)
14305 `PR_ERROR("mcu_fmon", `ERROR, "MCU2 IDLE LFSR is out-of-sync with AMB IDLE LFSR *** N2 T.O. BUG 111811 ***");
14306 else begin
14307 mcu2_idle_frame_cnt=0;
14308 mcu2_idle_frame_detected=0;
14309 end
14310 end
14311end
14312
14313always @ (posedge drl2clk)
14314if (enabled && idle_frame_checker_enable)
14315begin
14316 if (`MCU3.fbdic.fbdic_l0_state) begin
14317 if (`MCU3.fbdic.fbdic_idle_frame)
14318 mcu3_idle_frame_detected = 1'b1;
14319 mcu3_idle_frame_cnt = mcu3_idle_frame_cnt + 1;
14320 end
14321
14322 if (mcu3_idle_frame_cnt == 200) // expected to see idle frame frame match with in 200 dram clock cycles
14323 begin
14324 if (mcu3_idle_frame_detected == 0)
14325 `PR_ERROR("mcu_fmon", `ERROR, "MCU3 IDLE LFSR is out-of-sync with AMB IDLE LFSR *** N2 T.O. BUG 111811 ***");
14326 else begin
14327 mcu3_idle_frame_cnt=0;
14328 mcu3_idle_frame_detected=0;
14329 end
14330 end
14331end
14332
14333// added the following logic added to validate when more than 34 read errors are encountered, error queue will wrap around
14334
14335integer mcu0_err_fifo_enq_counter;
14336integer mcu1_err_fifo_enq_counter;
14337integer mcu2_err_fifo_enq_counter;
14338integer mcu3_err_fifo_enq_counter;
14339
14340initial begin
14341 mcu0_err_fifo_enq_counter=0;
14342 mcu1_err_fifo_enq_counter=0;
14343 mcu2_err_fifo_enq_counter=0;
14344 mcu3_err_fifo_enq_counter=0;
14345end
14346
14347always @(posedge `MCU0.rdpctl_err_fifo_enq) begin
14348 if (`MCU0.rdpctl_err_fifo_enq == 1'b1) begin //make sure it is 0->1 and not 0->x
14349 mcu0_err_fifo_enq_counter = mcu0_err_fifo_enq_counter + 1; //increment
14350 if ($test$plusargs("MCU_ERR_FIFO_ENQ"))
14351 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: *** error fifo queue counter reached %d !!! ***", mcu0_err_fifo_enq_counter);
14352 end
14353end
14354
14355always @(posedge `MCU1.rdpctl_err_fifo_enq) begin
14356 if (`MCU1.rdpctl_err_fifo_enq == 1'b1) begin //make sure it is 0->1 and not 0->x
14357 mcu1_err_fifo_enq_counter = mcu1_err_fifo_enq_counter + 1; //increment
14358 if ($test$plusargs("MCU_ERR_FIFO_ENQ"))
14359 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU1: *** error fifo queue counter reached %d !!! ***", mcu1_err_fifo_enq_counter);
14360 end
14361end
14362
14363always @(posedge `MCU2.rdpctl_err_fifo_enq) begin
14364 if (`MCU2.rdpctl_err_fifo_enq == 1'b1) begin //make sure it is 0->1 and not 0->x
14365 mcu2_err_fifo_enq_counter = mcu2_err_fifo_enq_counter + 1; //increment
14366 if ($test$plusargs("MCU_ERR_FIFO_ENQ"))
14367 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU2: *** error fifo queue counter reached %d !!! ***", mcu2_err_fifo_enq_counter);
14368 end
14369end
14370
14371always @(posedge `MCU3.rdpctl_err_fifo_enq) begin
14372 if (`MCU3.rdpctl_err_fifo_enq == 1'b1) begin //make sure it is 0->1 and not 0->x
14373 mcu3_err_fifo_enq_counter = mcu3_err_fifo_enq_counter + 1; //increment
14374 if ($test$plusargs("MCU_ERR_FIFO_ENQ"))
14375 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU3: *** error fifo queue counter reached %d !!! ***", mcu3_err_fifo_enq_counter);
14376 end
14377end
14378
14379`ifdef MCUSAT_AND_FC
14380
14381// --- MCU RAS CORNER CASES ---
14382
14383integer clkcycle;
14384reg corner_case_1;
14385reg corner_case_2;
14386reg corner_case_3;
14387reg corner_case_4;
14388
14389initial begin
14390 clkcycle = 1;
14391`ifndef AXIS
14392 $value$plusargs("SET_CLKCYCLE=%d",clkcycle);
14393`endif
14394
14395 #5;
14396 if ($test$plusargs("CORNER_CASE_1"))
14397 corner_case_1 = 1;
14398 else
14399 corner_case_1 = 0;
14400
14401 if ($test$plusargs("CORNER_CASE_2"))
14402 corner_case_2 = 1;
14403 else
14404 corner_case_2 = 0;
14405
14406 if ($test$plusargs("CORNER_CASE_3"))
14407 corner_case_3 = 1;
14408 else
14409 corner_case_3 = 0;
14410
14411 if ($test$plusargs("CORNER_CASE_4"))
14412 corner_case_4 = 1;
14413 else
14414 corner_case_4 = 0;
14415
14416end
14417
14418// --- Corner Cases: Inject SB errors before 1st SYNC frame ---
14419
14420always @ (`MCU0.fbdic.fbdic_sync_frame_req)
14421if (enabled && ras_corner_case)
14422begin
14423
14424 if ((mcu0_sb_err_enable==1) &&
14425 (`MCU0.fbdic.fbdic_sync_frame_req==1) &&
14426 (mcu0_sb_channel_error_cnt>0) &&
14427 (`MCU0.drif.drif_err_state == 5'h1) &&
14428 corner_case_1)
14429 begin
14430 repeat (clkcycle) @ (posedge drl2clk);
14431 repeat (10) @ (posedge sclk);
14432
14433 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq = 12'h1;
14434 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period = 12'h1;
14435 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num = 12'h1;
14436
14437 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq = 12'h1;
14438 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period = 12'h1;
14439 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num = 12'h1;
14440
14441 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq = 12'h1;
14442 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period = 12'h1;
14443 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num = 12'h1;
14444
14445 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq = 12'h1;
14446 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period = 12'h1;
14447 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num = 12'h1;
14448
14449 repeat (1) @ (posedge sclk);
14450
14451 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq;
14452 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period;
14453 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num;
14454
14455 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq;
14456 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period;
14457 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num;
14458
14459 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq;
14460 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period;
14461 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num;
14462
14463 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq;
14464 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period;
14465 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num;
14466
14467 mcu0_sb_channel_error_cnt=mcu0_sb_channel_error_cnt - 1;
14468 if (mcu0_sb_channel_error_cnt==0)
14469 mcu0_sb_err_enable=0;
14470 end
14471end
14472
14473always @ (`MCU0.fbdic.fbdic_scr_frame_req or `MCU0.fbdic.fbdic_issue_pre_all_cmd or `MCU0.fbdic.fbdic_issue_cke_cmd or `MCU0.fbdic.fbdic_sync_frame_req or mcu0_drif_dram_cmd_a)
14474if (enabled && ras_corner_case)
14475begin
14476
14477 if ((mcu0_sb_err_enable==1 || mcu0_nb_err_enable==1) &&
14478 ((`MCU0.fbdic.fbdic_scr_frame_req) ||
14479 (`MCU0.fbdic.fbdic_sync_frame_req) ||
14480 (`MCU0.fbdic.fbdic_issue_pre_all_cmd) ||
14481 (`MCU0.fbdic.fbdic_issue_cke_cmd) ||
14482 (mcu0_drif_dram_cmd_a==`RD)) &&
14483 (mcu0_sb_channel_error_cnt>0 || mcu0_nb_channel_error_cnt>0) &&
14484 corner_case_2)
14485 begin
14486
14487 fork
14488 begin
14489
14490 if (`MCU0.fbdic.fbdic_scr_frame_req==1 && mcu0_nb_err_enable) begin
14491 clkcycle=mcu0_chnl_lat-4;
14492 repeat (clkcycle) @ (posedge drl2clk);
14493 repeat (10) @ (posedge sclk);
14494
14495 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_freq = 12'h1;
14496 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_period = 12'h1;
14497 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_frame_num = 12'h1;
14498
14499 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_freq = 12'h1;
14500 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_period = 12'h1;
14501 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_frame_num = 12'h1;
14502
14503 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_freq = 12'h1;
14504 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_period = 12'h1;
14505 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_frame_num = 12'h1;
14506
14507 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_freq = 12'h1;
14508 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_period = 12'h1;
14509 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_frame_num = 12'h1;
14510
14511 repeat (1) @ (posedge sclk);
14512
14513 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_freq;
14514 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_period;
14515 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_frame_num;
14516
14517 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_freq;
14518 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_period;
14519 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_frame_num;
14520
14521 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_freq;
14522 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_period;
14523 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_frame_num;
14524
14525 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_freq;
14526 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_period;
14527 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_frame_num;
14528
14529 mcu0_nb_channel_error_cnt=mcu0_nb_channel_error_cnt - 1;
14530 end
14531 end
14532
14533 begin
14534
14535 if (((mcu0_drif_dram_cmd_a==`RD) ||
14536 (`MCU0.fbdic.fbdic_scr_frame_req && ~corner_case_3 && ~corner_case_4) ||
14537 (`MCU0.fbdic.fbdic_issue_cke_cmd && corner_case_3) ||
14538 (`MCU0.fbdic.fbdic_issue_pre_all_cmd && corner_case_4) ||
14539 (`MCU0.fbdic.fbdic_err_state[5] && `MCU0.fbdic.fbdic_sync_frame_req)) &&
14540 mcu0_sb_err_enable) begin
14541 clkcycle=3;
14542 repeat (clkcycle) @ (posedge drl2clk);
14543 repeat (10) @ (posedge sclk);
14544
14545 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq = 12'h1;
14546 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period = 12'h1;
14547 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num = 12'h1;
14548
14549 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq = 12'h1;
14550 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period = 12'h1;
14551 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num = 12'h1;
14552
14553 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq = 12'h1;
14554 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period = 12'h1;
14555 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num = 12'h1;
14556
14557 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq = 12'h1;
14558 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period = 12'h1;
14559 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num = 12'h1;
14560
14561 repeat (1) @ (posedge sclk);
14562
14563 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq;
14564 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period;
14565 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num;
14566
14567 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq;
14568 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period;
14569 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num;
14570
14571 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq;
14572 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period;
14573 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num;
14574
14575 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq;
14576 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period;
14577 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num;
14578
14579 mcu0_sb_channel_error_cnt=mcu0_sb_channel_error_cnt - 1;
14580 end
14581
14582 end
14583
14584 join
14585
14586 if (mcu0_sb_channel_error_cnt==0)
14587 mcu0_sb_err_enable=0;
14588
14589 if (mcu0_nb_channel_error_cnt==0)
14590 mcu0_nb_err_enable=0;
14591 end
14592end
14593
14594reg scrub_wrerr_cornercase;
14595
14596initial begin
14597 #1;
14598 if ($test$plusargs("SCRUB_WRERR_CORNERCASE"))
14599 scrub_wrerr_cornercase = 1;
14600 else
14601 scrub_wrerr_cornercase = 0;
14602
14603 if (scrub_wrerr_cornercase) begin
14604 #4380000;
14605
14606 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq = 12'h1;
14607 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period = 12'h1;
14608 force tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num = 12'h1;
14609 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq = 12'h1;
14610 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period = 12'h1;
14611 force tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num = 12'h1;
14612 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq = 12'h1;
14613 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period = 12'h1;
14614 force tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num = 12'h1;
14615 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq = 12'h1;
14616 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period = 12'h1;
14617 force tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num = 12'h1;
14618
14619 repeat (1) @ (posedge sclk);
14620
14621 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_freq;
14622 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_crc_period;
14623 release tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_frame_num;
14624 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_freq;
14625 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_crc_period;
14626 release tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_frame_num;
14627 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_freq;
14628 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_crc_period;
14629 release tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_frame_num;
14630 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_freq;
14631 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_crc_period;
14632 release tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_frame_num;
14633 end
14634end
14635
14636initial begin
14637 #1;
14638 if ($test$plusargs("BUG119328"))
14639 begin
14640 wait (`MCU0.drif.reqq.woq.woq_wr_err_state == 2'b10);
14641 wait ((`MCU0.fbdic.drif_dram_cmd_a == 3'b100)||(`MCU0.fbdic.drif_dram_cmd_b == 3'b100));
14642 wait ((`MCU0.fbdic.drif_dram_cmd_a == 3'b011)||(`MCU0.fbdic.drif_dram_cmd_b == 3'b011));
14643// #11760;
14644 #50249;
14645 #3000;
14646
14647 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_freq = 12'h1;
14648 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_period = 12'h1;
14649 force tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_frame_num = 12'h1;
14650 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_freq = 12'h1;
14651 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_period = 12'h1;
14652 force tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_frame_num = 12'h1;
14653 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_freq = 12'h1;
14654 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_period = 12'h1;
14655 force tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_frame_num = 12'h1;
14656 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_freq = 12'h1;
14657 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_period = 12'h1;
14658 force tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_frame_num = 12'h1;
14659
14660 repeat (1) @ (posedge sclk);
14661
14662 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_freq;
14663 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_crc_period;
14664 release tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_frame_num;
14665 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_freq;
14666 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_crc_period;
14667 release tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_frame_num;
14668 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_freq;
14669 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_crc_period;
14670 release tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_frame_num;
14671 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_freq;
14672 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_crc_period;
14673 release tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_frame_num;
14674 end
14675end
14676
14677`endif
14678
14679
14680//------------------------------------------------------------
14681// ----- Added CKE CMD & PRE_ALL checkers after SCR CMD ------
14682//------------------------------------------------------------
14683
14684always @ (posedge `MCU0.fbdic.fbdic_scr_frame_req)
14685if (enabled)
14686begin
14687 repeat (6) @ (negedge drl2clk);
14688 if (`MCU0.fbdic.fbdic_issue_cke_cmd != 1'b1)
14689 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: CKE CMD not issued 5 dram clock cycles after SCR cmd");
14690 repeat (6) @ (negedge drl2clk);
14691 if (`MCU0.fbdic.fbdic_issue_pre_all_cmd != 1'b1)
14692 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: PRE_ALL CMD not issued 6 dram clock cycles after CKE cmd");
14693end
14694
14695always @ (posedge `MCU1.fbdic.fbdic_scr_frame_req)
14696if (enabled)
14697begin
14698 repeat (6) @ (negedge drl2clk);
14699 if (`MCU1.fbdic.fbdic_issue_cke_cmd != 1'b1)
14700 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: CKE CMD not issued 5 dram clock cycles after SCR cmd");
14701 repeat (6) @ (negedge drl2clk);
14702 if (`MCU1.fbdic.fbdic_issue_pre_all_cmd != 1'b1)
14703 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: PRE_ALL CMD not issued 6 dram clock cycles after CKE cmd");
14704end
14705
14706always @ (posedge `MCU2.fbdic.fbdic_scr_frame_req)
14707if (enabled)
14708begin
14709 repeat (6) @ (negedge drl2clk);
14710 if (`MCU2.fbdic.fbdic_issue_cke_cmd != 1'b1)
14711 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: CKE CMD not issued 5 dram clock cycles after SCR cmd");
14712 repeat (6) @ (negedge drl2clk);
14713 if (`MCU2.fbdic.fbdic_issue_pre_all_cmd != 1'b1)
14714 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: PRE_ALL CMD not issued 6 dram clock cycles after CKE cmd");
14715end
14716
14717always @ (posedge `MCU3.fbdic.fbdic_scr_frame_req)
14718if (enabled)
14719begin
14720 repeat (6) @ (negedge drl2clk);
14721 if (`MCU3.fbdic.fbdic_issue_cke_cmd != 1'b1)
14722 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: CKE CMD not issued 5 dram clock cycles after SCR cmd");
14723 repeat (6) @ (negedge drl2clk);
14724 if (`MCU3.fbdic.fbdic_issue_pre_all_cmd != 1'b1)
14725 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: PRE_ALL CMD not issued 6 dram clock cycles after CKE cmd");
14726end
14727
14728
14729//SYNC_IER checker
14730always @ (negedge `MCU0.fbdic.fbdic_l0_state)
14731if (enabled)
14732begin
14733 if (`MCU0.fbdic.fbdic_sync_ier)
14734 begin
14735 repeat (3) @ (negedge drl2clk);
14736 if (`MCU0.fbdic.fbdic_sync_ier !== 1'b0)
14737 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: IER bit is not reset");
14738 end
14739end
14740
14741always @ (posedge (`MCU0.fbdic.fbdic_sync_ier && `MCU0.fbdic.fbdic_sync_frame_req))
14742if (enabled)
14743begin
14744 if (`MCU0.fbdic.fbdic_l0_state)
14745 begin
14746 @ (negedge drl2clk);
14747 if ((`MCU0.fbdic.fbdic_sync_frame_req) && (`MCU0.fbdic.fbdic_a_cmd_in[6] !== 1'b1))
14748 `PR_ERROR("mcu_fmon", `ERROR, "MCU0: Sync frame has IER=0");
14749 end
14750end
14751
14752always @ (negedge `MCU1.fbdic.fbdic_l0_state)
14753if (enabled)
14754begin
14755 if (`MCU1.fbdic.fbdic_sync_ier)
14756 begin
14757 repeat (3) @ (negedge drl2clk);
14758 if (`MCU1.fbdic.fbdic_sync_ier !== 1'b0)
14759 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: IER bit is not reset");
14760 end
14761end
14762
14763always @ (posedge (`MCU1.fbdic.fbdic_sync_ier && `MCU1.fbdic.fbdic_sync_frame_req))
14764if (enabled)
14765begin
14766 if (`MCU1.fbdic.fbdic_l0_state)
14767 begin
14768 @ (negedge drl2clk);
14769 if ((`MCU1.fbdic.fbdic_sync_frame_req) && (`MCU1.fbdic.fbdic_a_cmd_in[6] !== 1'b1))
14770 `PR_ERROR("mcu_fmon", `ERROR, "MCU1: Sync frame has IER=0");
14771 end
14772end
14773
14774always @ (negedge `MCU2.fbdic.fbdic_l0_state)
14775if (enabled)
14776begin
14777 if (`MCU2.fbdic.fbdic_sync_ier)
14778 begin
14779 repeat (3) @ (negedge drl2clk);
14780 if (`MCU2.fbdic.fbdic_sync_ier !== 1'b0)
14781 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: IER bit is not reset");
14782 end
14783end
14784
14785always @ (posedge (`MCU2.fbdic.fbdic_sync_ier && `MCU2.fbdic.fbdic_sync_frame_req))
14786if (enabled)
14787begin
14788 if (`MCU2.fbdic.fbdic_l0_state)
14789 begin
14790 @ (negedge drl2clk);
14791 if ((`MCU2.fbdic.fbdic_sync_frame_req) && (`MCU2.fbdic.fbdic_a_cmd_in[6] !== 1'b1))
14792 `PR_ERROR("mcu_fmon", `ERROR, "MCU2: Sync frame has IER=0");
14793 end
14794end
14795
14796always @ (negedge `MCU3.fbdic.fbdic_l0_state)
14797if (enabled)
14798begin
14799 if (`MCU3.fbdic.fbdic_sync_ier)
14800 begin
14801 repeat (3) @ (negedge drl2clk);
14802 if (`MCU3.fbdic.fbdic_sync_ier !== 1'b0)
14803 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: IER bit is not reset");
14804 end
14805end
14806
14807always @ (posedge (`MCU3.fbdic.fbdic_sync_ier && `MCU3.fbdic.fbdic_sync_frame_req))
14808if (enabled)
14809begin
14810 if (`MCU3.fbdic.fbdic_l0_state)
14811 begin
14812 @ (negedge drl2clk);
14813 if ((`MCU3.fbdic.fbdic_sync_frame_req) && (`MCU3.fbdic.fbdic_a_cmd_in[6] !== 1'b1))
14814 `PR_ERROR("mcu_fmon", `ERROR, "MCU3: Sync frame has IER=0");
14815 end
14816end
14817
14818
14819
14820//always @ (posedge (`MCU0.drif.reqq.woq.woq0_wr_queue_clear[0]))
14821always @ (posedge woq0_wrq_clr0)
14822begin
14823 if ($test$plusargs("BUG119648"))
14824 begin
14825 if (first_time)
14826 begin
14827 //$display("%d WOQ clear= %x\n",$time,woq0_wrq_clr0);
14828 force `MCU0.fbdic.fbdic_l0_state = 1'b0;
14829 first_time = 1'b0;
14830 repeat (10) @ (negedge drl2clk);
14831 release `MCU0.fbdic.fbdic_l0_state;
14832 end
14833 end
14834end
14835
14836
14837initial begin
14838 #1;
14839 if ($test$plusargs("MCU0_FASTRESET"))
14840 mcu0_fastreset = 1;
14841 else
14842 mcu0_fastreset = 0;
14843
14844 if (mcu0_fastreset) begin
14845 #4455001;
14846 force `CPU.mcu0.fbdic.fbdic_chnl_reset_en = 1'b1;
14847 force `CPU.mcu0.fbdic.fbdic_chnl_reset_in[0] = 1'b1;
14848 force `CPU.mcu0.fbdic.fbdic_chnl_reset_ld = 1'b1;
14849 wait (`CPU.mcu0.fbdic.fbdic_chnl_reset[0] == 1'b1);
14850 release `CPU.mcu0.fbdic.fbdic_chnl_reset_en;
14851 release `CPU.mcu0.fbdic.fbdic_chnl_reset_in[0];
14852 release `CPU.mcu0.fbdic.fbdic_chnl_reset_ld;
14853 end
14854end
14855
14856reg ts0_hdr, ts1_hdr, ts2_hdr, ts3_hdr, tsx_hdr;
14857reg [3:0] fbdic_seq_en;
14858integer tsx_rndm;
14859
14860
14861initial begin
14862 ts0_hdr = 0;
14863 ts1_hdr = 0;
14864 ts2_hdr = 0;
14865 ts3_hdr = 0;
14866 tsx_hdr = 0;
14867
14868 #1;
14869
14870 if ($test$plusargs("TS0_HDR"))
14871 ts0_hdr = 1;
14872 else
14873 ts0_hdr = 0;
14874
14875 if ($test$plusargs("TS1_HDR"))
14876 ts1_hdr = 1;
14877 else
14878 ts1_hdr = 0;
14879
14880 if ($test$plusargs("TS2_HDR"))
14881 ts2_hdr = 1;
14882 else
14883 ts2_hdr = 0;
14884
14885 if ($test$plusargs("TS3_HDR"))
14886 ts3_hdr = 1;
14887 else
14888 ts3_hdr = 0;
14889
14890 if ($test$plusargs("TSX_HDR")) // Random Header
14891 tsx_hdr = 1;
14892 else
14893 tsx_hdr = 0;
14894end
14895
14896always @ (posedge `MCU0.fbdic.fbdic_l0_state)
14897if (enabled)
14898begin
14899 if (ts0_hdr)
14900 fbdic_seq_en = 4'h1;
14901 else if (ts1_hdr)
14902 fbdic_seq_en = 4'h2;
14903 else if (ts2_hdr)
14904 fbdic_seq_en = 4'h4;
14905 else if (ts3_hdr)
14906 fbdic_seq_en = 4'h8;
14907 else if (tsx_hdr) begin
14908 tsx_rndm = ({$random(`PARGS.seed)} % 4);
14909 case(tsx_rndm)
14910 0: fbdic_seq_en = 4'h1;
14911 1: fbdic_seq_en = 4'h2;
14912 2: fbdic_seq_en = 4'h4;
14913 3: fbdic_seq_en = 4'h8;
14914 endcase
14915 end
14916
14917 wait (`MCU0.fbdic.fbdic_status_frame == 1'b1);
14918
14919 if (ts0_hdr || ts1_hdr || ts2_hdr || ts3_hdr || tsx_hdr)
14920 begin
14921 force `MCU0.fbdic.fbdic_sequence_en = fbdic_seq_en ;
14922 `PR_DEBUG("mcu_fmon", `DEBUG, "MCU0: Forced fbdic_sequence_en to %x", fbdic_seq_en);
14923 @ (posedge drl2clk);
14924 release `MCU0.fbdic.fbdic_sequence_en ;
14925 end
14926end
14927
14928
14929// added the following to be displayed *ONLY* at fullchip
14930
14931`ifdef FC_CRC_INJECT
14932// nb
14933
14934//0a and 0b
14935always @( posedge tb_top.crc_errinject_top.nb_crc_errinj0a_n.crc_en ) begin
14936
14937 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
14938 @( posedge tb_top.crc_errinject_top.nb_crc_errinj0a_n.sclk );
14939 if ( !( tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_in[(NB_LANES-1):0] ) )
14940 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj0a_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj0a_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj0a_n.pn_out[(NB_LANES-1):0],i);
14941
14942 end
14943
14944end
14945
14946
14947always @( posedge tb_top.crc_errinject_top.nb_crc_errinj0a_p.crc_en ) begin
14948
14949 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
14950 @( posedge tb_top.crc_errinject_top.nb_crc_errinj0a_p.sclk );
14951 if ( !( tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_in[(NB_LANES-1):0] ) )
14952 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj0a_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj0a_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj0a_p.pn_out[(NB_LANES-1):0],i);
14953
14954 end
14955
14956end
14957
14958
14959always @( posedge tb_top.crc_errinject_top.nb_crc_errinj0b_n.crc_en ) begin
14960
14961 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
14962 @( posedge tb_top.crc_errinject_top.nb_crc_errinj0b_n.sclk );
14963 if ( !( tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_in[(NB_LANES-1):0] ) )
14964 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj0b_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj0b_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj0b_n.pn_out[(NB_LANES-1):0],i);
14965
14966 end
14967
14968end
14969
14970
14971always @( posedge tb_top.crc_errinject_top.nb_crc_errinj0b_p.crc_en ) begin
14972
14973 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
14974 @( posedge tb_top.crc_errinject_top.nb_crc_errinj0b_p.sclk );
14975 if ( !( tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_in[(NB_LANES-1):0] ) )
14976 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj0b_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj0b_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj0b_p.pn_out[(NB_LANES-1):0],i);
14977
14978 end
14979
14980end
14981
14982
14983//1a and 1b
14984
14985always @( posedge tb_top.crc_errinject_top.nb_crc_errinj1a_n.crc_en ) begin
14986
14987 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
14988 @( posedge tb_top.crc_errinject_top.nb_crc_errinj1a_n.sclk );
14989 if ( !( tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_in[(NB_LANES-1):0] ) )
14990 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj1a_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj1a_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj1a_n.pn_out[(NB_LANES-1):0],i);
14991
14992 end
14993
14994end
14995
14996
14997always @( posedge tb_top.crc_errinject_top.nb_crc_errinj1a_p.crc_en ) begin
14998
14999 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15000 @( posedge tb_top.crc_errinject_top.nb_crc_errinj1a_p.sclk );
15001 if ( !( tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_in[(NB_LANES-1):0] ) )
15002 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj1a_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj1a_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj1a_p.pn_out[(NB_LANES-1):0],i);
15003
15004 end
15005
15006end
15007
15008
15009always @( posedge tb_top.crc_errinject_top.nb_crc_errinj1b_n.crc_en ) begin
15010
15011 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15012 @( posedge tb_top.crc_errinject_top.nb_crc_errinj1b_n.sclk );
15013 if ( !( tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_in[(NB_LANES-1):0] ) )
15014 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj1b_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj1b_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj1b_n.pn_out[(NB_LANES-1):0],i);
15015
15016 end
15017
15018end
15019
15020
15021always @( posedge tb_top.crc_errinject_top.nb_crc_errinj1b_p.crc_en ) begin
15022
15023 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15024 @( posedge tb_top.crc_errinject_top.nb_crc_errinj1b_p.sclk );
15025 if ( !( tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_in[(NB_LANES-1):0] ) )
15026 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj1b_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj1b_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj1b_p.pn_out[(NB_LANES-1):0],i);
15027
15028 end
15029
15030end
15031
15032
15033//2a and 2b
15034always @( posedge tb_top.crc_errinject_top.nb_crc_errinj2a_n.crc_en ) begin
15035
15036 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15037 @( posedge tb_top.crc_errinject_top.nb_crc_errinj2a_n.sclk );
15038 if ( !( tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_in[(NB_LANES-1):0] ) )
15039 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj2a_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj2a_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj2a_n.pn_out[(NB_LANES-1):0],i);
15040
15041 end
15042
15043end
15044
15045
15046always @( posedge tb_top.crc_errinject_top.nb_crc_errinj2a_p.crc_en ) begin
15047
15048 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15049 @( posedge tb_top.crc_errinject_top.nb_crc_errinj2a_p.sclk );
15050 if ( !( tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_in[(NB_LANES-1):0] ) )
15051 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj2a_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj2a_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj2a_p.pn_out[(NB_LANES-1):0],i);
15052
15053 end
15054
15055end
15056
15057
15058always @( posedge tb_top.crc_errinject_top.nb_crc_errinj2b_n.crc_en ) begin
15059
15060 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15061 @( posedge tb_top.crc_errinject_top.nb_crc_errinj2b_n.sclk );
15062 if ( !( tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_in[(NB_LANES-1):0] ) )
15063 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj2b_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj2b_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj2b_n.pn_out[(NB_LANES-1):0],i);
15064
15065 end
15066
15067end
15068
15069
15070always @( posedge tb_top.crc_errinject_top.nb_crc_errinj2b_p.crc_en ) begin
15071
15072 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15073 @( posedge tb_top.crc_errinject_top.nb_crc_errinj2b_p.sclk );
15074 if ( !( tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_in[(NB_LANES-1):0] ) )
15075 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj2b_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj2b_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj2b_p.pn_out[(NB_LANES-1):0],i);
15076
15077 end
15078
15079end
15080
15081
15082//3a and 3b
15083
15084always @( posedge tb_top.crc_errinject_top.nb_crc_errinj3a_n.crc_en ) begin
15085
15086 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15087 @( posedge tb_top.crc_errinject_top.nb_crc_errinj3a_n.sclk );
15088 if ( !( tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_in[(NB_LANES-1):0] ) )
15089 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj3a_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj3a_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj3a_n.pn_out[(NB_LANES-1):0],i);
15090
15091 end
15092
15093end
15094
15095
15096always @( posedge tb_top.crc_errinject_top.nb_crc_errinj3a_p.crc_en ) begin
15097
15098 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15099 @( posedge tb_top.crc_errinject_top.nb_crc_errinj3a_p.sclk );
15100 if ( !( tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_in[(NB_LANES-1):0] ) )
15101 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj3a_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj3a_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj3a_p.pn_out[(NB_LANES-1):0],i);
15102
15103 end
15104
15105end
15106
15107
15108always @( posedge tb_top.crc_errinject_top.nb_crc_errinj3b_n.crc_en ) begin
15109
15110 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15111 @( posedge tb_top.crc_errinject_top.nb_crc_errinj3b_n.sclk );
15112 if ( !( tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_in[(NB_LANES-1):0] ) )
15113 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj3b_n.pn_in[13:0] was %x, modif. packet nb_crc_errinj3b_n.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj3b_n.pn_out[(NB_LANES-1):0],i);
15114
15115 end
15116
15117end
15118
15119
15120always @( posedge tb_top.crc_errinject_top.nb_crc_errinj3b_p.crc_en ) begin
15121
15122 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15123 @( posedge tb_top.crc_errinject_top.nb_crc_errinj3b_p.sclk );
15124 if ( !( tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_out[(NB_LANES-1):0] == tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_in[(NB_LANES-1):0] ) )
15125 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet nb_crc_errinj3b_p.pn_in[13:0] was %x, modif. packet nb_crc_errinj3b_p.pn_out[13:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_in[(NB_LANES-1):0], tb_top.crc_errinject_top.nb_crc_errinj3b_p.pn_out[(NB_LANES-1):0],i);
15126
15127 end
15128
15129end
15130
15131
15132// sb
15133
15134//0a and 0b
15135always @( posedge tb_top.crc_errinject_top.sb_crc_errinj0a_n.crc_en ) begin
15136
15137 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15138 @( posedge tb_top.crc_errinject_top.sb_crc_errinj0a_n.link_clk );
15139 if ( !( tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_in[(SB_LANES-1):0] ) )
15140 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj0a_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj0a_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj0a_n.ps_out[(SB_LANES-1):0],i);
15141
15142 end
15143
15144end
15145
15146
15147always @( posedge tb_top.crc_errinject_top.sb_crc_errinj0a_p.crc_en ) begin
15148
15149 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15150 @( posedge tb_top.crc_errinject_top.sb_crc_errinj0a_p.link_clk );
15151 if ( !( tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_in[(SB_LANES-1):0] ) )
15152 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj0a_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj0a_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj0a_p.ps_out[(SB_LANES-1):0],i);
15153
15154 end
15155
15156end
15157
15158
15159always @( posedge tb_top.crc_errinject_top.sb_crc_errinj0b_n.crc_en ) begin
15160
15161 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15162 @( posedge tb_top.crc_errinject_top.sb_crc_errinj0b_n.link_clk );
15163 if ( !( tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_in[(SB_LANES-1):0] ) )
15164 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj0b_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj0b_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj0b_n.ps_out[(SB_LANES-1):0],i);
15165
15166 end
15167
15168end
15169
15170
15171always @( posedge tb_top.crc_errinject_top.sb_crc_errinj0b_p.crc_en ) begin
15172
15173 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15174 @( posedge tb_top.crc_errinject_top.sb_crc_errinj0b_p.link_clk );
15175 if ( !( tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_in[(SB_LANES-1):0] ) )
15176 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj0b_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj0b_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj0b_p.ps_out[(SB_LANES-1):0],i);
15177
15178 end
15179
15180end
15181
15182
15183//1a and 1b
15184
15185always @( posedge tb_top.crc_errinject_top.sb_crc_errinj1a_n.crc_en ) begin
15186
15187 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15188 @( posedge tb_top.crc_errinject_top.sb_crc_errinj1a_n.link_clk );
15189 if ( !( tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_in[(SB_LANES-1):0] ) )
15190 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj1a_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj1a_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj1a_n.ps_out[(SB_LANES-1):0],i);
15191
15192 end
15193
15194end
15195
15196
15197always @( posedge tb_top.crc_errinject_top.sb_crc_errinj1a_p.crc_en ) begin
15198
15199 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15200 @( posedge tb_top.crc_errinject_top.sb_crc_errinj1a_p.link_clk );
15201 if ( !( tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_in[(SB_LANES-1):0] ) )
15202 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj1a_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj1a_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj1a_p.ps_out[(SB_LANES-1):0],i);
15203
15204 end
15205
15206end
15207
15208
15209always @( posedge tb_top.crc_errinject_top.sb_crc_errinj1b_n.crc_en ) begin
15210
15211 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15212 @( posedge tb_top.crc_errinject_top.sb_crc_errinj1b_n.link_clk );
15213 if ( !( tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_in[(SB_LANES-1):0] ) )
15214 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj1b_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj1b_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj1b_n.ps_out[(SB_LANES-1):0],i);
15215
15216 end
15217
15218end
15219
15220
15221always @( posedge tb_top.crc_errinject_top.sb_crc_errinj1b_p.crc_en ) begin
15222
15223 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15224 @( posedge tb_top.crc_errinject_top.sb_crc_errinj1b_p.link_clk );
15225 if ( !( tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_in[(SB_LANES-1):0] ) )
15226 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj1b_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj1b_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj1b_p.ps_out[(SB_LANES-1):0],i);
15227
15228 end
15229
15230end
15231
15232
15233//2a and 2b
15234always @( posedge tb_top.crc_errinject_top.sb_crc_errinj2a_n.crc_en ) begin
15235
15236 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15237 @( posedge tb_top.crc_errinject_top.sb_crc_errinj2a_n.link_clk );
15238 if ( !( tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_in[(SB_LANES-1):0] ) )
15239 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj2a_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj2a_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj2a_n.ps_out[(SB_LANES-1):0],i);
15240
15241 end
15242
15243end
15244
15245
15246always @( posedge tb_top.crc_errinject_top.sb_crc_errinj2a_p.crc_en ) begin
15247
15248 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15249 @( posedge tb_top.crc_errinject_top.sb_crc_errinj2a_p.link_clk );
15250 if ( !( tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_in[(SB_LANES-1):0] ) )
15251 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj2a_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj2a_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj2a_p.ps_out[(SB_LANES-1):0],i);
15252
15253 end
15254
15255end
15256
15257
15258always @( posedge tb_top.crc_errinject_top.sb_crc_errinj2b_n.crc_en ) begin
15259
15260 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15261 @( posedge tb_top.crc_errinject_top.sb_crc_errinj2b_n.link_clk );
15262 if ( !( tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_in[(SB_LANES-1):0] ) )
15263 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj2b_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj2b_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj2b_n.ps_out[(SB_LANES-1):0],i);
15264
15265 end
15266
15267end
15268
15269
15270always @( posedge tb_top.crc_errinject_top.sb_crc_errinj2b_p.crc_en ) begin
15271
15272 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15273 @( posedge tb_top.crc_errinject_top.sb_crc_errinj2b_p.link_clk );
15274 if ( !( tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_in[(SB_LANES-1):0] ) )
15275 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj2b_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj2b_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj2b_p.ps_out[(SB_LANES-1):0],i);
15276
15277 end
15278
15279end
15280
15281
15282//3a and 3b
15283
15284always @( posedge tb_top.crc_errinject_top.sb_crc_errinj3a_n.crc_en ) begin
15285
15286 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15287 @( posedge tb_top.crc_errinject_top.sb_crc_errinj3a_n.link_clk );
15288 if ( !( tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_in[(SB_LANES-1):0] ) )
15289 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj3a_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj3a_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj3a_n.ps_out[(SB_LANES-1):0],i);
15290
15291 end
15292
15293end
15294
15295
15296always @( posedge tb_top.crc_errinject_top.sb_crc_errinj3a_p.crc_en ) begin
15297
15298 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15299 @( posedge tb_top.crc_errinject_top.sb_crc_errinj3a_p.link_clk );
15300 if ( !( tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_in[(SB_LANES-1):0] ) )
15301 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj3a_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj3a_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj3a_p.ps_out[(SB_LANES-1):0],i);
15302
15303 end
15304
15305end
15306
15307
15308always @( posedge tb_top.crc_errinject_top.sb_crc_errinj3b_n.crc_en ) begin
15309
15310 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15311 @( posedge tb_top.crc_errinject_top.sb_crc_errinj3b_n.link_clk );
15312 if ( !( tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_in[(SB_LANES-1):0] ) )
15313 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj3b_n.ps_in[9:0] was %x, modif. packet sb_crc_errinj3b_n.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj3b_n.ps_out[(SB_LANES-1):0],i);
15314
15315 end
15316
15317end
15318
15319
15320always @( posedge tb_top.crc_errinject_top.sb_crc_errinj3b_p.crc_en ) begin
15321
15322 for ( i=0; i < BIT_TIMES; i=i+1 ) begin
15323 @( posedge tb_top.crc_errinject_top.sb_crc_errinj3b_p.link_clk );
15324 if ( !( tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_out[(SB_LANES-1):0] == tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_in[(SB_LANES-1):0] ) )
15325 `PR_ALWAYS("mcu_fmon",`ALWAYS,"INFO: orig. packet sb_crc_errinj3b_p.ps_in[9:0] was %x, modif. packet sb_crc_errinj3b_p.ps_out[9:0] is %x, change happened for bit time %d", tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_in[(SB_LANES-1):0], tb_top.crc_errinject_top.sb_crc_errinj3b_p.ps_out[(SB_LANES-1):0],i);
15326
15327 end
15328
15329end
15330
15331/*
15332 //following added to dump and debug memory contents
15333 always @ (posedge global_monitor.trigger_RD) begin
15334 if ( ($test$plusargs("ONE_NIBBLE_ERROR") || $test$plusargs("MULTI_NIBBLE_ERROR")) && !$test$plusargs("ON_WRITE_NEW") ) begin
15335 #1000
15336 $fsdbDumpMem(global_monitor.mcu0_read_data_array_QW1);
15337 $fsdbDumpMem(global_monitor.mcu0_read_data_array_QW2);
15338 #3000
15339 $fsdbDumpMem(global_monitor.mcu0_read_data_array_QW3);
15340 $fsdbDumpMem(global_monitor.mcu0_read_data_array_QW4);
15341 end
15342 end
15343 always @ (posedge global_monitor.trigger_WR) begin
15344 if ( ($test$plusargs("ONE_NIBBLE_ERROR") || $test$plusargs("MULTI_NIBBLE_ERROR")) && $test$plusargs("ON_WRITE_NEW") ) begin
15345 #3000
15346 #1000
15347 $fsdbDumpMem(global_monitor.mcu0_write_data_array_QW1);
15348 #3000
15349 $fsdbDumpMem(global_monitor.mcu0_write_data_array_QW2);
15350 #3000
15351 $fsdbDumpMem(global_monitor.mcu0_write_data_array_QW3);
15352 #3000
15353 $fsdbDumpMem(global_monitor.mcu0_write_data_array_QW4);
15354 end
15355 end
15356*/
15357
15358 always @ (posedge mcu_fmon.trigger_NB) begin
15359 if ( $test$plusargs("MCU0_NB_ERR_ENABLE") || $test$plusargs("MCU0_NB_ERR_RANDOM") ) begin
15360 #1000
15361 $fsdbDumpMem(mcu_fmon.mcu0_nb_data_array_QW1);
15362 $fsdbDumpMem(mcu_fmon.mcu0_nb_data_array_QW2);
15363 #3000
15364 $fsdbDumpMem(mcu_fmon.mcu0_nb_data_array_QW3);
15365 $fsdbDumpMem(mcu_fmon.mcu0_nb_data_array_QW4);
15366 end
15367 end
15368 always @ (posedge mcu_fmon.trigger_SB) begin
15369 if ( $test$plusargs("MCU0_SB_ERR_ENABLE") || $test$plusargs("MCU0_SB_ERR_RANDOM") ) begin
15370 #3000
15371 #3000
15372 #1000
15373 $fsdbDumpMem(mcu_fmon.mcu0_sb_data_array_QW1);
15374 #3000
15375 $fsdbDumpMem(mcu_fmon.mcu0_sb_data_array_QW2);
15376 #3000
15377 $fsdbDumpMem(mcu_fmon.mcu0_sb_data_array_QW3);
15378 #3000
15379 $fsdbDumpMem(mcu_fmon.mcu0_sb_data_array_QW4);
15380 end
15381 end
15382
15383`endif
15384
15385endmodule
Full OpenSPARC design & verification tarball including full HDL.