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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / mcusat_cov_mon.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcusat_cov_mon.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`include "cross_module.h"
36
37`ifdef MCUSAT
38 `include "mcu_dispmonDefines.vh"
39`else
40 `include "defines.vh"
41 `include "dispmonDefines.vh"
42`endif
43
44// locally used defines
45`define DRAM_L2IF0 `DCTLPATH0.l2if0
46`define DRAM_L2IF1 `DCTLPATH0.l2if1
47`define DRAM_L2IF2 `DCTLPATH1.l2if0
48`define DRAM_L2IF3 `DCTLPATH1.l2if1
49`define DRAM_L2IF4 `DCTLPATH2.l2if0
50`define DRAM_L2IF5 `DCTLPATH2.l2if1
51`define DRAM_L2IF6 `DCTLPATH3.l2if0
52`define DRAM_L2IF7 `DCTLPATH3.l2if1
53
54`define MCU_CLK `TOP_MOD.cpu.mcu0.drl2clk
55
56module mcusat_cov_mon ( clk, rst_l);
57
58//--------------------------------------------------------------------------------------
59// Interface (note that most of the stuff is cross-module referencing,
60// so the interface is minimal
61//--------------------------------------------------------------------------------------
62 input clk; // the cpu clock
63 input rst_l; // reset (active low).
64
65//--------------------------------------------------------------------------------------
66// a variable which decides should we print all mcusat_cov_mon messages
67//--------------------------------------------------------------------------------------
68 reg enabled;
69 initial
70 begin
71 enabled = 1'b1;
72 if ($test$plusargs("mcusat_cov_mon_disable"))
73 enabled = 1'b0;
74 end
75
76// other declarations
77//--------------------------------------------------------------------------------------
78integer i,j;
79// This has to be a define and its value need be updated depending on max time
80// allowed in the que, 1000 for now
81wire [20:0] MAX_TIME = 1000000;
82
83wire rst_wmr_protect = `CPU.rst_wmr_protect;
84
85// logic for for 2-state simulation
86wire dram_rst_l_sig;
87assign dram_rst_l_sig = rst_l ;
88reg dram_rst_l;
89initial dram_rst_l = 0 ;
90
91always @(posedge clk) begin
92 while (dram_rst_l_sig !== 0) @(posedge clk) ;
93 dram_rst_l = 0 ;
94 while (dram_rst_l_sig !== 1) @(posedge clk) ;
95 dram_rst_l = 1 ;
96end
97
98
99// address for schooming read and write with same address
100// actual address is 0, but this is updated to indicate the autoprecharge condition.
101wire [31:0] SCHMOO_RD_WR_ADDR = 32'h10; // identical to que_rd_addr_picked[31:0]
102// cacheline not considered in the above case, it it here.
103wire [34:0] SCHMOO_SCRB_ADDR = {SCHMOO_RD_WR_ADDR[31:3], 3'b000, SCHMOO_RD_WR_ADDR[2:0]};
104
105wire cmp_clk;
106wire cmp_rst_l;
107assign cmp_clk = clk;
108assign cmp_rst_l = rst_l ;
109
110//--------------------------------------------------------------------------------------
111// RD and WR fifo
112//--------------------------------------------------------------------------------------
113//`define DRAM_PATH0 `DRAM_PATH0.dramctl0.dram_dctl.dram_que
114//`define DRAM_PATH1 `DRAM_PATH0.dramctl1.dram_dctl.dram_que
115//`define DRAM_PATH2 `DRAM_PATH1.dramctl0.dram_dctl.dram_que
116//`define DRAM_PATH3 `DRAM_PATH1.dramctl1.dram_dctl.dram_que
117 // read que request
118 wire dram_Ch0_l2b0_rd_req = `MCU0_L2IF0_CTL.l2t_mcu_rd_req;
119 wire [2:0] dram_Ch0_l2b0_rd_id = `MCU0_L2IF0_CTL.l2t_mcu_rd_req_id[2:0];
120 wire dram_Ch0_l2b0_errq_vld = (!`MCU0_DRIF_CTL.drif_err_fifo_empty) & (`MCU0_DRIF_CTL.rdpctl_err_fifo_data[0] == 0) ;
121 wire [2:0] dram_Ch0_l2b0_errq_id = `MCU0_DRIF_CTL.rdpctl_err_fifo_data[4:2];
122 // read que
123 wire dram_ch0_l2b0_rd_q_vld_0 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
124 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
125 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
126 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
127 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
128 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
129 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) |
130 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0])) };
131
132 wire dram_ch0_l2b0_rd_q_vld_1 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
133 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
134 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
135 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
136 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
137 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
138 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) |
139 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1])) };
140
141 wire dram_ch0_l2b0_rd_q_vld_2 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
142 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
143 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
144 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
145 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
146 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
147 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) |
148 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2])) };
149
150 wire dram_ch0_l2b0_rd_q_vld_3 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
151 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
152 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
153 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
154 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
155 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
156 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) |
157 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3])) };
158
159 wire dram_ch0_l2b0_rd_q_vld_4 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
160 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
161 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
162 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
163 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
164 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
165 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) |
166 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4])) };
167
168 wire dram_ch0_l2b0_rd_q_vld_5 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
169 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
170 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
171 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
172 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
173 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
174 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) |
175 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5])) };
176
177 wire dram_ch0_l2b0_rd_q_vld_6 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
178 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
179 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
180 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
181 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
182 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
183 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) |
184 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6])) };
185
186 wire dram_ch0_l2b0_rd_q_vld_7 = { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
187 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
188 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
189 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
190 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
191 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
192 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) |
193 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7])) };
194
195 wire [7:0] dram_ch0_l2b0_rd_q_valids = {dram_ch0_l2b0_rd_q_vld_7, dram_ch0_l2b0_rd_q_vld_6, dram_ch0_l2b0_rd_q_vld_5, dram_ch0_l2b0_rd_q_vld_4,
196 dram_ch0_l2b0_rd_q_vld_3, dram_ch0_l2b0_rd_q_vld_2, dram_ch0_l2b0_rd_q_vld_1, dram_ch0_l2b0_rd_q_vld_0};
197
198// Read request Q PA-Error
199 wire dram_ch0_l2b0_rd_q_addr_err_0 =
200 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
201 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
202 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
203 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
204 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
205 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
206 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
207 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
208
209 wire dram_ch0_l2b0_rd_q_addr_err_1 =
210 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
211 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
212 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
213 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
214 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
215 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
216 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
217 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) };
218
219 wire dram_ch0_l2b0_rd_q_addr_err_2 =
220 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
221 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
222 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
223 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
224 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
225 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
226 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
227 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
228
229 wire dram_ch0_l2b0_rd_q_addr_err_3 =
230 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
231 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
232 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
233 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
234 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
235 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
236 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
237 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
238
239 wire dram_ch0_l2b0_rd_q_addr_err_4 =
240 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
241 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
242 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
243 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
244 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
245 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
246 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
247 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
248
249 wire dram_ch0_l2b0_rd_q_addr_err_5 =
250 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
251 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
252 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
253 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
254 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
255 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
256 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
257 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
258
259 wire dram_ch0_l2b0_rd_q_addr_err_6 =
260 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
261 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
262 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
263 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
264 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
265 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
266 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
267 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
268
269 wire dram_ch0_l2b0_rd_q_addr_err_7 =
270 { ((`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent0[7]) |
271 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent1[7]) |
272 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent2[7]) |
273 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent3[7]) |
274 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent4[7]) |
275 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent5[7]) |
276 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent6[7]) |
277 ((`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU0_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ0_CTL.drq_rd_queue_ent7[7]) };
278
279 wire [7:0] dram_ch0_l2b0_rd_q_addr_err = {dram_ch0_l2b0_rd_q_addr_err_7, dram_ch0_l2b0_rd_q_addr_err_6, dram_ch0_l2b0_rd_q_addr_err_5, dram_ch0_l2b0_rd_q_addr_err_4,
280 dram_ch0_l2b0_rd_q_addr_err_3, dram_ch0_l2b0_rd_q_addr_err_2, dram_ch0_l2b0_rd_q_addr_err_1, dram_ch0_l2b0_rd_q_addr_err_0};
281
282 wire [7:0] dram_ch0_l2b0_drq_rd_queue_valid = {`MCU0_DRQ0_CTL.drq_rd_queue_valid[7:0]};
283 wire [3:0] dram_ch0_l2b0_drq_read_queue_cnt = {`MCU0_DRQ0_CTL.drq_read_queue_cnt[3:0]};
284
285// Read request Q PA-Error
286
287 wire [39:0] dram_Ch0_l2b0_rd_q_0 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[0],
288 `MCU0_L2B0_ADR_Q.rd_req_id_queue0[2:0],
289 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue0[3:0],
290 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue0[2:0],
291 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue0[14:0],
292 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue0[10:0],
293 3'b0 };
294
295 wire [39:0] dram_Ch0_l2b0_rd_q_1 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[1],
296 `MCU0_L2B0_ADR_Q.rd_req_id_queue1[2:0],
297 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue1[3:0],
298 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue1[2:0],
299 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue1[14:0],
300 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue1[10:0],
301 3'b0 };
302
303 wire [39:0] dram_Ch0_l2b0_rd_q_2 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[2],
304 `MCU0_L2B0_ADR_Q.rd_req_id_queue2[2:0],
305 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue2[3:0],
306 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue2[2:0],
307 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue2[14:0],
308 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue2[10:0],
309 3'b0 };
310
311 wire [39:0] dram_Ch0_l2b0_rd_q_3 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[3],
312 `MCU0_L2B0_ADR_Q.rd_req_id_queue3[2:0],
313 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue3[3:0],
314 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue3[2:0],
315 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue3[14:0],
316 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue3[10:0],
317 3'b0 };
318
319 wire [39:0] dram_Ch0_l2b0_rd_q_4 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[4],
320 `MCU0_L2B0_ADR_Q.rd_req_id_queue4[2:0],
321 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue4[3:0],
322 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue4[2:0],
323 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue4[14:0],
324 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue4[10:0],
325 3'b0 };
326
327 wire [39:0] dram_Ch0_l2b0_rd_q_5 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[5],
328 `MCU0_L2B0_ADR_Q.rd_req_id_queue5[2:0],
329 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue5[3:0],
330 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue5[2:0],
331 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue5[14:0],
332 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue5[10:0],
333 3'b0 };
334
335 wire [39:0] dram_Ch0_l2b0_rd_q_6 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[6],
336 `MCU0_L2B0_ADR_Q.rd_req_id_queue6[2:0],
337 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue6[3:0],
338 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue6[2:0],
339 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue6[14:0],
340 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue6[10:0],
341 3'b0 };
342
343 wire [39:0] dram_Ch0_l2b0_rd_q_7 = {`MCU0_DRQ0_CTL.drq_rdbuf_valids[7],
344 `MCU0_L2B0_ADR_Q.rd_req_id_queue7[2:0],
345 `MCU0_L2B0_ADR_Q.rank_rd_adr_queue7[3:0],
346 `MCU0_L2B0_ADR_Q.bank_rd_adr_queue7[2:0],
347 `MCU0_L2B0_ADR_Q.ras_rd_adr_queue7[14:0],
348 `MCU0_L2B0_ADR_Q.cas_rd_adr_queue7[10:0],
349 3'b0 };
350
351
352 reg [39:0] dram_Ch0_l2b0_rd_q[7:0];
353 // read que collapsing fifo
354 wire [11:0] dram_Ch0_l2b0_rd_colps_q_0 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent0[11:0]};
355 wire [11:0] dram_Ch0_l2b0_rd_colps_q_1 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent1[11:0]};
356 wire [11:0] dram_Ch0_l2b0_rd_colps_q_2 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent2[11:0]};
357 wire [11:0] dram_Ch0_l2b0_rd_colps_q_3 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent3[11:0]};
358 wire [11:0] dram_Ch0_l2b0_rd_colps_q_4 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent4[11:0]};
359 wire [11:0] dram_Ch0_l2b0_rd_colps_q_5 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent5[11:0]};
360 wire [11:0] dram_Ch0_l2b0_rd_colps_q_6 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent6[11:0]};
361 wire [11:0] dram_Ch0_l2b0_rd_colps_q_7 = {`MCU0_DRQ0_CTL.drq_rd_queue_ent7[11:0]};
362
363 reg [11:0] dram_Ch0_l2b0_rd_colps_q[7:0];
364
365 // read que write pointer
366 wire [7:0] dram_Ch0_l2b0_rd_que_wr_ptr = {`MCU0_DRQ0_CTL.drq_rd_adr_queue7_en,
367 `MCU0_DRQ0_CTL.drq_rd_adr_queue6_en,
368 `MCU0_DRQ0_CTL.drq_rd_adr_queue5_en,
369 `MCU0_DRQ0_CTL.drq_rd_adr_queue4_en,
370 `MCU0_DRQ0_CTL.drq_rd_adr_queue3_en,
371 `MCU0_DRQ0_CTL.drq_rd_adr_queue2_en,
372 `MCU0_DRQ0_CTL.drq_rd_adr_queue1_en,
373 `MCU0_DRQ0_CTL.drq_rd_adr_queue0_en};
374 // read que read pointer
375 wire [7:0] dram_Ch0_l2b0_rd_que_rd_ptr = {`MCU0_DRQ0_CTL.rdpctl_drq_clear_ent[7:0]};
376
377 // write que request
378 wire dram_Ch0_l2b0_wr_req = `MCU0_L2IF0_CTL.l2t_mcu_wr_req;
379 wire [2:0] dram_Ch0_l2b0_wr_addr = `MCU0_L2IF0_CTL.l2if_data_wr_addr;
380
381 wire [7:0] dram_ch0_l2b0_wr_q_valids = {`MCU0_DRQ0_CTL.drq_wr_queue_valid[7:0]};
382 wire [3:0] dram_ch0_l2b0_drq_write_queue_cnt = {`MCU0_DRQ0_CTL.drq_write_queue_cnt[3:0]};
383
384 wire [40:0] dram_Ch0_l2b0_wr_q_0 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[0],
385 `MCU0_DRQ0_CTL.drq_wrbuf_valids[0], //`DRAM_PATH0.writeqbank0vld0_arb,
386 `MCU0_DRQ0_CTL.drq_wr_queue_ent0[11:9],
387 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue0[3:0],
388 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue0[2:0],
389 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue0[14:0],
390 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue0[10:0],
391 3'b0};
392
393 wire [40:0] dram_Ch0_l2b0_wr_q_1 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[1],
394 `MCU0_DRQ0_CTL.drq_wrbuf_valids[1], //`DRAM_PATH0.writeqbank0vld0_arb,
395 `MCU0_DRQ0_CTL.drq_wr_queue_ent1[11:9],
396 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue1[3:0],
397 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue1[2:0],
398 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue1[14:0],
399 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue1[10:0],
400 3'b0};
401
402 wire [40:0] dram_Ch0_l2b0_wr_q_2 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[2],
403 `MCU0_DRQ0_CTL.drq_wrbuf_valids[2], //`DRAM_PATH0.writeqbank0vld0_arb,
404 `MCU0_DRQ0_CTL.drq_wr_queue_ent2[11:9],
405 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue2[3:0],
406 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue2[2:0],
407 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue2[14:0],
408 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue2[10:0],
409 3'b0};
410
411 wire [40:0] dram_Ch0_l2b0_wr_q_3 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[3],
412 `MCU0_DRQ0_CTL.drq_wrbuf_valids[3], //`DRAM_PATH0.writeqbank0vld0_arb,
413 `MCU0_DRQ0_CTL.drq_wr_queue_ent3[11:9],
414 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue3[3:0],
415 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue3[2:0],
416 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue3[14:0],
417 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue3[10:0],
418 3'b0};
419
420 wire [40:0] dram_Ch0_l2b0_wr_q_4 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[4],
421 `MCU0_DRQ0_CTL.drq_wrbuf_valids[4], //`DRAM_PATH0.writeqbank0vld0_arb,
422 `MCU0_DRQ0_CTL.drq_wr_queue_ent4[11:9],
423 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue4[3:0],
424 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue4[2:0],
425 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue4[14:0],
426 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue4[10:0],
427 3'b0};
428
429 wire [40:0] dram_Ch0_l2b0_wr_q_5 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[5],
430 `MCU0_DRQ0_CTL.drq_wrbuf_valids[5], //`DRAM_PATH0.writeqbank0vld0_arb,
431 `MCU0_DRQ0_CTL.drq_wr_queue_ent5[11:9],
432 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue5[3:0],
433 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue5[2:0],
434 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue5[14:0],
435 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue5[10:0],
436 3'b0};
437
438 wire [40:0] dram_Ch0_l2b0_wr_q_6 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[6],
439 `MCU0_DRQ0_CTL.drq_wrbuf_valids[6], //`DRAM_PATH0.writeqbank0vld0_arb,
440 `MCU0_DRQ0_CTL.drq_wr_queue_ent6[11:9],
441 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue6[3:0],
442 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue6[2:0],
443 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue6[14:0],
444 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue6[10:0],
445 3'b0};
446
447 wire [40:0] dram_Ch0_l2b0_wr_q_7 = {`MCU0_DRQ0_CTL.drq_wrbuf_valids[7],
448 `MCU0_DRQ0_CTL.drq_wrbuf_valids[7], //`DRAM_PATH0.writeqbank0vld0_arb,
449 `MCU0_DRQ0_CTL.drq_wr_queue_ent7[11:9],
450 `MCU0_L2B0_ADR_Q.rank_wr_adr_queue7[3:0],
451 `MCU0_L2B0_ADR_Q.bank_wr_adr_queue7[2:0],
452 `MCU0_L2B0_ADR_Q.ras_wr_adr_queue7[14:0],
453 `MCU0_L2B0_ADR_Q.cas_wr_adr_queue7[10:0],
454 3'b0};
455
456 reg [40:0] dram_Ch0_l2b0_wr_q[7:0];
457
458 // to not set valid for the fifo monitor
459 wire dram_Ch0_l2b0_pa_err = `MCU0_L2RDMX_DP.l2b0_wr_addr_err;
460
461 // write que collapsing fifo
462 wire [14:0] dram_Ch0_l2b0_wr_colps_q_0 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent0[14:0]};
463 wire [14:0] dram_Ch0_l2b0_wr_colps_q_1 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent1[14:0]};
464 wire [14:0] dram_Ch0_l2b0_wr_colps_q_2 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent2[14:0]};
465 wire [14:0] dram_Ch0_l2b0_wr_colps_q_3 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent3[14:0]};
466 wire [14:0] dram_Ch0_l2b0_wr_colps_q_4 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent4[14:0]};
467 wire [14:0] dram_Ch0_l2b0_wr_colps_q_5 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent5[14:0]};
468 wire [14:0] dram_Ch0_l2b0_wr_colps_q_6 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent6[14:0]};
469 wire [14:0] dram_Ch0_l2b0_wr_colps_q_7 = {`MCU0_DRQ0_CTL.drq_wr_queue_ent7[14:0]};
470
471 reg [14:0] dram_Ch0_l2b0_wr_colps_q[7:0];
472
473 // write que write pointer
474 wire [7:0] dram_Ch0_l2b0_wr_que_wr_ptr = {`MCU0_DRQ0_CTL.drq_wr_adr_queue7_en,
475 `MCU0_DRQ0_CTL.drq_wr_adr_queue6_en,
476 `MCU0_DRQ0_CTL.drq_wr_adr_queue5_en,
477 `MCU0_DRQ0_CTL.drq_wr_adr_queue4_en,
478 `MCU0_DRQ0_CTL.drq_wr_adr_queue3_en,
479 `MCU0_DRQ0_CTL.drq_wr_adr_queue2_en,
480 `MCU0_DRQ0_CTL.drq_wr_adr_queue1_en,
481 `MCU0_DRQ0_CTL.drq_wr_adr_queue0_en};
482
483 // write que arb read pointer
484
485 // write que data read pointer
486 /*wire [7:0] dram_Ch0_l2b0_wr_que_rd_ptr = {`MCU0_DRQ0_CTL.drq_wr_entry7_rank,
487 `MCU0_DRQ0_CTL.drq_wr_entry6_rank,
488 `MCU0_DRQ0_CTL.drq_wr_entry5_rank,
489 `MCU0_DRQ0_CTL.drq_wr_entry4_rank,
490 `MCU0_DRQ0_CTL.drq_wr_entry3_rank,
491 `MCU0_DRQ0_CTL.drq_wr_entry2_rank,
492 `MCU0_DRQ0_CTL.drq_wr_entry1_rank,
493 `MCU0_DRQ0_CTL.drq_wr_entry0_rank};*/
494 wire [7:0] dram_Ch0_l2b0_wr_que_rd_ptr = `MCU0_DRQ0_CTL.drq_wrq_clear_ent;
495
496
497// These signals are currently not used in cov obj
498// enable for 8 deep collps rd fifo
499 wire [7:0] dram_Ch0_l2b0_que_b0_index_en = {`MCU0_L2B0_ADR_Q.rd_adr_queue_sel[7:0]};
500
501
502// These signals are currently not used in cov obj
503// enable for 8 deep collps wr fifo
504 wire [7:0] dram_Ch0_l2b0_que_b0_wr_index_en= {`MCU0_L2B0_ADR_Q.wr_adr_queue_sel[7:0]};
505
506// These signals are currently not used in cov obj
507// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
508 wire [7:0] dram_Ch0_l2b0_que_b0_rd_in_val = `MCU0_DRQ0_CTL.drq_rd_entry0_val[7:0];
509
510 wire dram_Ch0_que_b0_rd_picked = `MCU0_DRIF_CTL.drif0_rd_picked;
511 wire dram_Ch0_que_b0_wr_picked = `MCU0_DRIF_CTL.drif0_wr_picked;
512 // read que request
513 wire dram_Ch0_l2b1_rd_req = `MCU0_L2IF1_CTL.l2t_mcu_rd_req;
514 wire [2:0] dram_Ch0_l2b1_rd_id = `MCU0_L2IF1_CTL.l2t_mcu_rd_req_id[2:0];
515 wire dram_Ch0_l2b1_errq_vld = (!`MCU0_DRIF_CTL.drif_err_fifo_empty) & (`MCU0_DRIF_CTL.rdpctl_err_fifo_data[0] == 1) ;
516 wire [2:0] dram_Ch0_l2b1_errq_id = `MCU0_DRIF_CTL.rdpctl_err_fifo_data[4:2];
517 // read que
518 wire dram_ch0_l2b1_rd_q_vld_0 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
519 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
520 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
521 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
522 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
523 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
524 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) |
525 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0])) };
526
527 wire dram_ch0_l2b1_rd_q_vld_1 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
528 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
529 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
530 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
531 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
532 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
533 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) |
534 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1])) };
535
536 wire dram_ch0_l2b1_rd_q_vld_2 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
537 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
538 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
539 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
540 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
541 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
542 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) |
543 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2])) };
544
545 wire dram_ch0_l2b1_rd_q_vld_3 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
546 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
547 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
548 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
549 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
550 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
551 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) |
552 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3])) };
553
554 wire dram_ch0_l2b1_rd_q_vld_4 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
555 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
556 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
557 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
558 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
559 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
560 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) |
561 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4])) };
562
563 wire dram_ch0_l2b1_rd_q_vld_5 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
564 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
565 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
566 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
567 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
568 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
569 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) |
570 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5])) };
571
572 wire dram_ch0_l2b1_rd_q_vld_6 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
573 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
574 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
575 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
576 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
577 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
578 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) |
579 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6])) };
580
581 wire dram_ch0_l2b1_rd_q_vld_7 = { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
582 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
583 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
584 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
585 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
586 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
587 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) |
588 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7])) };
589
590 wire [7:0] dram_ch0_l2b1_rd_q_valids = {dram_ch0_l2b1_rd_q_vld_7, dram_ch0_l2b1_rd_q_vld_6, dram_ch0_l2b1_rd_q_vld_5, dram_ch0_l2b1_rd_q_vld_4,
591 dram_ch0_l2b1_rd_q_vld_3, dram_ch0_l2b1_rd_q_vld_2, dram_ch0_l2b1_rd_q_vld_1, dram_ch0_l2b1_rd_q_vld_0};
592
593// Read request Q PA-Error
594 wire dram_ch0_l2b1_rd_q_addr_err_0 =
595 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
596 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
597 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
598 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
599 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
600 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
601 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
602 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
603
604 wire dram_ch0_l2b1_rd_q_addr_err_1 =
605 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
606 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
607 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
608 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
609 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
610 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
611 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
612 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) };
613
614 wire dram_ch0_l2b1_rd_q_addr_err_2 =
615 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
616 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
617 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
618 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
619 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
620 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
621 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
622 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
623
624 wire dram_ch0_l2b1_rd_q_addr_err_3 =
625 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
626 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
627 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
628 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
629 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
630 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
631 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
632 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
633
634 wire dram_ch0_l2b1_rd_q_addr_err_4 =
635 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
636 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
637 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
638 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
639 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
640 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
641 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
642 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
643
644 wire dram_ch0_l2b1_rd_q_addr_err_5 =
645 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
646 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
647 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
648 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
649 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
650 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
651 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
652 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
653
654 wire dram_ch0_l2b1_rd_q_addr_err_6 =
655 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
656 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
657 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
658 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
659 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
660 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
661 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
662 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
663
664 wire dram_ch0_l2b1_rd_q_addr_err_7 =
665 { ((`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent0[7]) |
666 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent1[7]) |
667 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent2[7]) |
668 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent3[7]) |
669 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent4[7]) |
670 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent5[7]) |
671 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent6[7]) |
672 ((`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU0_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU0_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU0_DRQ1_CTL.drq_rd_queue_ent7[7]) };
673
674 wire [7:0] dram_ch0_l2b1_rd_q_addr_err = {dram_ch0_l2b1_rd_q_addr_err_7, dram_ch0_l2b1_rd_q_addr_err_6, dram_ch0_l2b1_rd_q_addr_err_5, dram_ch0_l2b1_rd_q_addr_err_4,
675 dram_ch0_l2b1_rd_q_addr_err_3, dram_ch0_l2b1_rd_q_addr_err_2, dram_ch0_l2b1_rd_q_addr_err_1, dram_ch0_l2b1_rd_q_addr_err_0};
676
677 wire [7:0] dram_ch0_l2b1_drq_rd_queue_valid = {`MCU0_DRQ1_CTL.drq_rd_queue_valid[7:0]};
678 wire [3:0] dram_ch0_l2b1_drq_read_queue_cnt = {`MCU0_DRQ1_CTL.drq_read_queue_cnt[3:0]};
679
680// Read request Q PA-Error
681
682 wire [39:0] dram_Ch0_l2b1_rd_q_0 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[0],
683 `MCU0_L2B1_ADR_Q.rd_req_id_queue0[2:0],
684 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue0[3:0],
685 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue0[2:0],
686 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue0[14:0],
687 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue0[10:0],
688 3'b0 };
689
690 wire [39:0] dram_Ch0_l2b1_rd_q_1 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[1],
691 `MCU0_L2B1_ADR_Q.rd_req_id_queue1[2:0],
692 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue1[3:0],
693 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue1[2:0],
694 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue1[14:0],
695 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue1[10:0],
696 3'b0 };
697
698 wire [39:0] dram_Ch0_l2b1_rd_q_2 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[2],
699 `MCU0_L2B1_ADR_Q.rd_req_id_queue2[2:0],
700 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue2[3:0],
701 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue2[2:0],
702 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue2[14:0],
703 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue2[10:0],
704 3'b0 };
705
706 wire [39:0] dram_Ch0_l2b1_rd_q_3 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[3],
707 `MCU0_L2B1_ADR_Q.rd_req_id_queue3[2:0],
708 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue3[3:0],
709 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue3[2:0],
710 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue3[14:0],
711 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue3[10:0],
712 3'b0 };
713
714 wire [39:0] dram_Ch0_l2b1_rd_q_4 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[4],
715 `MCU0_L2B1_ADR_Q.rd_req_id_queue4[2:0],
716 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue4[3:0],
717 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue4[2:0],
718 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue4[14:0],
719 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue4[10:0],
720 3'b0 };
721
722 wire [39:0] dram_Ch0_l2b1_rd_q_5 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[5],
723 `MCU0_L2B1_ADR_Q.rd_req_id_queue5[2:0],
724 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue5[3:0],
725 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue5[2:0],
726 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue5[14:0],
727 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue5[10:0],
728 3'b0 };
729
730 wire [39:0] dram_Ch0_l2b1_rd_q_6 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[6],
731 `MCU0_L2B1_ADR_Q.rd_req_id_queue6[2:0],
732 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue6[3:0],
733 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue6[2:0],
734 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue6[14:0],
735 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue6[10:0],
736 3'b0 };
737
738 wire [39:0] dram_Ch0_l2b1_rd_q_7 = {`MCU0_DRQ1_CTL.drq_rdbuf_valids[7],
739 `MCU0_L2B1_ADR_Q.rd_req_id_queue7[2:0],
740 `MCU0_L2B1_ADR_Q.rank_rd_adr_queue7[3:0],
741 `MCU0_L2B1_ADR_Q.bank_rd_adr_queue7[2:0],
742 `MCU0_L2B1_ADR_Q.ras_rd_adr_queue7[14:0],
743 `MCU0_L2B1_ADR_Q.cas_rd_adr_queue7[10:0],
744 3'b0 };
745
746
747 reg [39:0] dram_Ch0_l2b1_rd_q[7:0];
748 // read que collapsing fifo
749 wire [11:0] dram_Ch0_l2b1_rd_colps_q_0 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent0[11:0]};
750 wire [11:0] dram_Ch0_l2b1_rd_colps_q_1 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent1[11:0]};
751 wire [11:0] dram_Ch0_l2b1_rd_colps_q_2 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent2[11:0]};
752 wire [11:0] dram_Ch0_l2b1_rd_colps_q_3 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent3[11:0]};
753 wire [11:0] dram_Ch0_l2b1_rd_colps_q_4 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent4[11:0]};
754 wire [11:0] dram_Ch0_l2b1_rd_colps_q_5 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent5[11:0]};
755 wire [11:0] dram_Ch0_l2b1_rd_colps_q_6 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent6[11:0]};
756 wire [11:0] dram_Ch0_l2b1_rd_colps_q_7 = {`MCU0_DRQ1_CTL.drq_rd_queue_ent7[11:0]};
757
758 reg [11:0] dram_Ch0_l2b1_rd_colps_q[7:0];
759
760 // read que write pointer
761 wire [7:0] dram_Ch0_l2b1_rd_que_wr_ptr = {`MCU0_DRQ1_CTL.drq_rd_adr_queue7_en,
762 `MCU0_DRQ1_CTL.drq_rd_adr_queue6_en,
763 `MCU0_DRQ1_CTL.drq_rd_adr_queue5_en,
764 `MCU0_DRQ1_CTL.drq_rd_adr_queue4_en,
765 `MCU0_DRQ1_CTL.drq_rd_adr_queue3_en,
766 `MCU0_DRQ1_CTL.drq_rd_adr_queue2_en,
767 `MCU0_DRQ1_CTL.drq_rd_adr_queue1_en,
768 `MCU0_DRQ1_CTL.drq_rd_adr_queue0_en};
769 // read que read pointer
770 wire [7:0] dram_Ch0_l2b1_rd_que_rd_ptr = {`MCU0_DRQ1_CTL.rdpctl_drq_clear_ent[7:0]};
771
772 // write que request
773 wire dram_Ch0_l2b1_wr_req = `MCU0_L2IF1_CTL.l2t_mcu_wr_req;
774 wire [2:0] dram_Ch0_l2b1_wr_addr = `MCU0_L2IF1_CTL.l2if_data_wr_addr;
775
776 wire [7:0] dram_ch0_l2b1_wr_q_valids = {`MCU0_DRQ1_CTL.drq_wr_queue_valid[7:0]};
777 wire [3:0] dram_ch0_l2b1_drq_write_queue_cnt = {`MCU0_DRQ1_CTL.drq_write_queue_cnt[3:0]};
778
779 wire [40:0] dram_Ch0_l2b1_wr_q_0 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[0],
780 `MCU0_DRQ1_CTL.drq_wrbuf_valids[0], //`DRAM_PATH0.writeqbank0vld0_arb,
781 `MCU0_DRQ1_CTL.drq_wr_queue_ent0[11:9],
782 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue0[3:0],
783 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue0[2:0],
784 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue0[14:0],
785 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue0[10:0],
786 3'b0};
787
788 wire [40:0] dram_Ch0_l2b1_wr_q_1 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[1],
789 `MCU0_DRQ1_CTL.drq_wrbuf_valids[1], //`DRAM_PATH0.writeqbank0vld0_arb,
790 `MCU0_DRQ1_CTL.drq_wr_queue_ent1[11:9],
791 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue1[3:0],
792 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue1[2:0],
793 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue1[14:0],
794 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue1[10:0],
795 3'b0};
796
797 wire [40:0] dram_Ch0_l2b1_wr_q_2 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[2],
798 `MCU0_DRQ1_CTL.drq_wrbuf_valids[2], //`DRAM_PATH0.writeqbank0vld0_arb,
799 `MCU0_DRQ1_CTL.drq_wr_queue_ent2[11:9],
800 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue2[3:0],
801 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue2[2:0],
802 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue2[14:0],
803 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue2[10:0],
804 3'b0};
805
806 wire [40:0] dram_Ch0_l2b1_wr_q_3 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[3],
807 `MCU0_DRQ1_CTL.drq_wrbuf_valids[3], //`DRAM_PATH0.writeqbank0vld0_arb,
808 `MCU0_DRQ1_CTL.drq_wr_queue_ent3[11:9],
809 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue3[3:0],
810 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue3[2:0],
811 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue3[14:0],
812 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue3[10:0],
813 3'b0};
814
815 wire [40:0] dram_Ch0_l2b1_wr_q_4 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[4],
816 `MCU0_DRQ1_CTL.drq_wrbuf_valids[4], //`DRAM_PATH0.writeqbank0vld0_arb,
817 `MCU0_DRQ1_CTL.drq_wr_queue_ent4[11:9],
818 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue4[3:0],
819 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue4[2:0],
820 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue4[14:0],
821 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue4[10:0],
822 3'b0};
823
824 wire [40:0] dram_Ch0_l2b1_wr_q_5 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[5],
825 `MCU0_DRQ1_CTL.drq_wrbuf_valids[5], //`DRAM_PATH0.writeqbank0vld0_arb,
826 `MCU0_DRQ1_CTL.drq_wr_queue_ent5[11:9],
827 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue5[3:0],
828 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue5[2:0],
829 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue5[14:0],
830 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue5[10:0],
831 3'b0};
832
833 wire [40:0] dram_Ch0_l2b1_wr_q_6 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[6],
834 `MCU0_DRQ1_CTL.drq_wrbuf_valids[6], //`DRAM_PATH0.writeqbank0vld0_arb,
835 `MCU0_DRQ1_CTL.drq_wr_queue_ent6[11:9],
836 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue6[3:0],
837 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue6[2:0],
838 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue6[14:0],
839 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue6[10:0],
840 3'b0};
841
842 wire [40:0] dram_Ch0_l2b1_wr_q_7 = {`MCU0_DRQ1_CTL.drq_wrbuf_valids[7],
843 `MCU0_DRQ1_CTL.drq_wrbuf_valids[7], //`DRAM_PATH0.writeqbank0vld0_arb,
844 `MCU0_DRQ1_CTL.drq_wr_queue_ent7[11:9],
845 `MCU0_L2B1_ADR_Q.rank_wr_adr_queue7[3:0],
846 `MCU0_L2B1_ADR_Q.bank_wr_adr_queue7[2:0],
847 `MCU0_L2B1_ADR_Q.ras_wr_adr_queue7[14:0],
848 `MCU0_L2B1_ADR_Q.cas_wr_adr_queue7[10:0],
849 3'b0};
850
851 reg [40:0] dram_Ch0_l2b1_wr_q[7:0];
852
853 // to not set valid for the fifo monitor
854 wire dram_Ch0_l2b1_pa_err = `MCU0_L2RDMX_DP.l2b1_wr_addr_err;
855
856 // write que collapsing fifo
857 wire [14:0] dram_Ch0_l2b1_wr_colps_q_0 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent0[14:0]};
858 wire [14:0] dram_Ch0_l2b1_wr_colps_q_1 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent1[14:0]};
859 wire [14:0] dram_Ch0_l2b1_wr_colps_q_2 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent2[14:0]};
860 wire [14:0] dram_Ch0_l2b1_wr_colps_q_3 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent3[14:0]};
861 wire [14:0] dram_Ch0_l2b1_wr_colps_q_4 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent4[14:0]};
862 wire [14:0] dram_Ch0_l2b1_wr_colps_q_5 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent5[14:0]};
863 wire [14:0] dram_Ch0_l2b1_wr_colps_q_6 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent6[14:0]};
864 wire [14:0] dram_Ch0_l2b1_wr_colps_q_7 = {`MCU0_DRQ1_CTL.drq_wr_queue_ent7[14:0]};
865
866 reg [14:0] dram_Ch0_l2b1_wr_colps_q[7:0];
867
868 // write que write pointer
869 wire [7:0] dram_Ch0_l2b1_wr_que_wr_ptr = {`MCU0_DRQ1_CTL.drq_wr_adr_queue7_en,
870 `MCU0_DRQ1_CTL.drq_wr_adr_queue6_en,
871 `MCU0_DRQ1_CTL.drq_wr_adr_queue5_en,
872 `MCU0_DRQ1_CTL.drq_wr_adr_queue4_en,
873 `MCU0_DRQ1_CTL.drq_wr_adr_queue3_en,
874 `MCU0_DRQ1_CTL.drq_wr_adr_queue2_en,
875 `MCU0_DRQ1_CTL.drq_wr_adr_queue1_en,
876 `MCU0_DRQ1_CTL.drq_wr_adr_queue0_en};
877
878 // write que arb read pointer
879
880 // write que data read pointer
881 /*wire [7:0] dram_Ch0_l2b1_wr_que_rd_ptr = {`MCU0_DRQ1_CTL.drq_wr_entry7_rank,
882 `MCU0_DRQ1_CTL.drq_wr_entry6_rank,
883 `MCU0_DRQ1_CTL.drq_wr_entry5_rank,
884 `MCU0_DRQ1_CTL.drq_wr_entry4_rank,
885 `MCU0_DRQ1_CTL.drq_wr_entry3_rank,
886 `MCU0_DRQ1_CTL.drq_wr_entry2_rank,
887 `MCU0_DRQ1_CTL.drq_wr_entry1_rank,
888 `MCU0_DRQ1_CTL.drq_wr_entry0_rank};*/
889 wire [7:0] dram_Ch0_l2b1_wr_que_rd_ptr = `MCU0_DRQ1_CTL.drq_wrq_clear_ent;
890
891
892// These signals are currently not used in cov obj
893// enable for 8 deep collps rd fifo
894 wire [7:0] dram_Ch0_l2b1_que_b0_index_en = {`MCU0_L2B1_ADR_Q.rd_adr_queue_sel[7:0]};
895
896
897// These signals are currently not used in cov obj
898// enable for 8 deep collps wr fifo
899 wire [7:0] dram_Ch0_l2b1_que_b0_wr_index_en= {`MCU0_L2B1_ADR_Q.wr_adr_queue_sel[7:0]};
900
901// These signals are currently not used in cov obj
902// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
903 wire [7:0] dram_Ch0_l2b1_que_b0_rd_in_val = `MCU0_DRQ1_CTL.drq_rd_entry0_val[7:0];
904
905 wire dram_Ch0_que_b1_rd_picked = `MCU0_DRIF_CTL.drif1_rd_picked;
906 wire dram_Ch0_que_b1_wr_picked = `MCU0_DRIF_CTL.drif1_wr_picked;
907
908
909
910// MAQ Not Required wire [7:0] dram_Ch0_que_cas_picked = `MCU0_DRIF_CTL.drif_cas_picked_d1[7:0];
911// rd hits a wr in the wr Q
912 wire dram_Ch0_que_rd_wr_hit = `MCU0_DRIF_CTL.drif_wr_entry_pend_in;
913
914// MAQ N2 doesn't support // Signals that will be used to detect oldest entry to the same bank.
915// MAQ N2 doesn't support // in 2 channel mode this is the real indicator that the request is picked from this channel
916// MAQ N2 doesn't support wire dram_Ch0_que_this_ch_picked = (~`DRAM_PATH0.que_channel_disabled) ?
917// MAQ N2 doesn't support `DRAM_PATH0.que_ras_bank_picked_en && ~`DRAM_PATH0.que_channel_picked_internal:
918// MAQ N2 doesn't support `DRAM_PATH0.que_ras_bank_picked_en && `DRAM_PATH0.que_channel_picked_internal;
919// MAQ N2 doesn't support
920
921 wire [2:0] dram_Ch0_que_b0_index_picked = `MCU0_DRIF_CTL.drif_rdwr_index_picked[2:0];
922 wire dram_Ch0_que_b0_cmd_picked = `MCU0_DRIF_CTL.drif_rdwr_cmd_picked;
923 wire dram_ch0_drif_mclk_en = `MCU0_DRIF_CTL.drif_mclk_en;
924
925
926//----------------------------------------------------------------------------------------
927// Refresh to go and all CAS request to same CS are done, no new RAS issued.
928//----------------------------------------------------------------------------------------
929 wire [4:0] dram_Ch0_que_pos = `MCU0_DRIF_CTL.drif_mcu_state_enc;
930 wire dram_Ch0_que_ref_go = `MCU0_DRIF_CTL.drif_ref_go;
931 wire dram_Ch0_que_hw_selfrsh = `MCU0_DRIF_CTL.drif_hw_selfrsh;
932 wire dram_Ch0_pt_blk_new_openbank_d1 = `MCU0_DRIF_CTL.drif_blk_new_openbank;
933 wire dram_Ch0_que_cas_valid = ( (|(`MCU0_DRIF_CTL.drif_cas_picked)) &
934 (`MCU0_DRIF_CTL.drif_phy_bank_picked[1:0] == `MCU0_DRIF_CTL.drif_refresh_rank[1:0])
935 );
936 wire [15:0] dram_Ch0_ras_picked = `MCU0_DRIF_CTL.drif_ras_picked[15:0];
937 wire dram_Ch0_que_ras_picked = ( (|(`MCU0_DRIF_CTL.drif_ras_picked[15:0])) &
938 ({`MCU0_DRIF_CTL.drif_rank_adr, `MCU0_DRIF_CTL.drif_stacked_dimm} == `MCU0_DRIF_CTL.drif_refresh_rank[1:0])
939 );
940 wire [1:0] dram_Ch0_b0_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
941 wire [1:0] dram_Ch0_b1_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
942 wire [1:0] dram_Ch0_b2_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
943 wire [1:0] dram_Ch0_b3_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
944 wire [1:0] dram_Ch0_b4_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
945 wire [1:0] dram_Ch0_b5_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
946 wire [1:0] dram_Ch0_b6_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
947 wire [1:0] dram_Ch0_b7_phy_bank_bits = `MCU0_DRIF_CTL.drif_phy_bank_picked[1:0];
948 reg [1:0] dram_Ch0_b_phy_bank_bits[7:0];
949
950 wire [1:0] dram_Ch0_que_refresh_rank = `MCU0_DRIF_CTL.drif_refresh_rank[1:0];
951
952
953// ---- Starvation counter causing the wr to have priority ---
954 wire dram_Ch0_que_pick_wr_first = (`MCU0_DRIF_CTL.drif0_pick_wr_first |
955 `MCU0_DRIF_CTL.drif1_pick_wr_first);
956
957// ------ Scrub Related -------
958
959 // picking the que_split_scrb_addr as _que_scrb_addr_picked_
960 wire [31:0] dram_Ch0_que_scrb_addr_picked = `MCU0_DRIF_CTL.drif_scrub_addr;
961 wire dram_Ch0_que_scrb_picked = `MCU0_DRIF_CTL.drif_scrub_picked;
962 //somePersonwire dram_Ch0_que_scrb_rd_picked = `MCU0_DRIF_CTL.drif_scrub_picked; // MAQ
963 wire dram_Ch0_que_scrb_rd_picked = `MCU0_DRIF_CTL.drif_scrub_read_pending;
964 wire dram_Ch0_que_ras_bank_picked_en = |(`MCU0_DRIF_CTL.drif_ras_picked[15:0]);
965 wire dram_Ch0_que_scrb_write_req = `MCU0_DRIF_CTL.drif_scrub_write_req;
966
967// req valid and scrb valid, the scrb should be cleared first
968 wire [15:0] dram_Ch0_que_l2req_valid = `MCU0_DRIF_CTL.drif0_rd_bank_valids | `MCU0_DRIF_CTL.drif1_rd_bank_valids |
969 `MCU0_DRIF_CTL.drif_wr_bank_valids;
970 wire [15:0] dram_Ch0_scrb_indx_val = `MCU0_DRIF_CTL.drif_scrub_entry_val;
971
972// ------- DRAM REGISTERS --------
973
974 wire [8:0] dram_Ch0_chip_config_reg = {`MCU0_DRIF_CTL.drif_ras_addr_bits[3:0],
975 `MCU0_DRIF_CTL.drif_cas_addr_bits[3:0],
976 `MCU0_DRIF_CTL.drif_stacked_dimm};
977
978 wire [2:0] dram_Ch0_mode_reg = `MCU0_DRIF_CTL.mode_reg[6:4];
979 wire [3:0] dram_Ch0_rrd_reg = `MCU0_DRIF_CTL.rrd_reg;
980 wire [4:0] dram_Ch0_rc_reg = `MCU0_DRIF_CTL.rc_reg;
981 wire [3:0] dram_Ch0_rcd_reg = `MCU0_DRIF_CTL.rcd_reg;
982 wire [3:0] dram_Ch0_wtr_dly_reg = `MCU0_DRIF_CTL.wtr_dly_reg;
983 wire [3:0] dram_Ch0_rtw_dly_reg = `MCU0_DRIF_CTL.rtw_dly_reg;
984 wire [3:0] dram_Ch0_rtp_reg = `MCU0_DRIF_CTL.rtp_reg;
985 wire [3:0] dram_Ch0_ras_reg = `MCU0_DRIF_CTL.ras_reg;
986 wire [3:0] dram_Ch0_rp_reg = `MCU0_DRIF_CTL.rp_reg;
987 wire [3:0] dram_Ch0_wr_reg = `MCU0_DRIF_CTL.wr_reg;
988 wire [1:0] dram_Ch0_mrd_reg = `MCU0_DRIF_CTL.mrd_reg;
989 wire [1:0] dram_Ch0_iwtr_reg = `MCU0_DRIF_CTL.iwtr_reg;
990 wire [14:0] dram_Ch0_ext_mode_reg2 = `MCU0_DRIF_CTL.ext_mode_reg2;
991 wire [14:0] dram_Ch0_ext_mode_reg1 = `MCU0_DRIF_CTL.ext_mode_reg1;
992 wire [14:0] dram_Ch0_ext_mode_reg3 = `MCU0_DRIF_CTL.ext_mode_reg3;
993 wire dram_Ch0_que_eight_bank_mode = `MCU0_DRIF_CTL.drif_eight_bank_mode;
994 wire dram_Ch0_que_rank1_present = `MCU0_DRIF_CTL.drif_dimms_present[0];
995 wire dram_Ch0_que_channel_disabled = `MCU0_DRIF_CTL.drif_branch_disabled;
996 wire dram_Ch0_que_addr_bank_low_sel = `MCU0_DRIF_CTL.drif_addr_bank_low_sel;
997 wire dram_Ch0_que_init = `MCU0_DRIF_CTL.drif_init;
998// wire [2:0] dram_Ch0_que_data_del_cnt = `MCU0_DRIF_CTL.drif_data_del_cnt[2:0];
999// wire dram_Ch0_dram_io_pad_clk_inv = `MCU0_DRIF_CTL.mcu_ddp_pad_clk_inv;
1000// wire [1:0] dram_Ch0_dram_io_ptr_clk_inv = `MCU0_DRIF_CTL.mcu_ddp_ptr_clk_inv;
1001 wire dram_Ch0_que_wr_mode_reg_done = `MCU0_DRIF_CTL.drif_wr_mode_reg_done;
1002 wire dram_Ch0_que_init_status_reg = `MCU0_DRIF_CTL.drif_init_status_reg;
1003 wire [3:0] dram_Ch0_que_dimms_present = `MCU0_DRIF_CTL.drif_dimms_present;
1004 wire dram_Ch0_dram_fail_over_mode = `MCU0_DRIF_CTL.drif_fail_over_mode;
1005 wire [34:0] dram_Ch0_dram_fail_over_mask = `MCU0_DRIF_CTL.drif_fail_over_mask[34:0];
1006 wire dram_Ch0_que_dbg_trig_en = `MCU0_DRIF_CTL.rdpctl_dbg_trig_enable;
1007 wire [22:0] dram_Ch0_que_err_sts_reg = `MCU0_DRIF_CTL.rdpctl_err_sts_reg;
1008 wire [35:0] dram_Ch0_que_err_addr_reg = `MCU0_DRIF_CTL.rdpctl_err_addr_reg;
1009 wire dram_Ch0_err_inj_reg = `MCU0_DRIF_CTL.drif_err_inj_reg;
1010 wire dram_Ch0_sshot_err_reg = `MCU0_DRIF_CTL.drif_sshot_err_reg;
1011// wire [1:0] dram_Ch0_que_err_cnt = `MCU0_DRIF_CTL.rdpctl_err_cnt[17:16];
1012 wire [35:0] dram_Ch0_que_err_loc = `MCU0_DRIF_CTL.rdpctl_err_loc;
1013
1014 // NACK - for non existant register read
1015 wire dram_Ch0_que_l2if_ack_vld = `MCU0_DRIF_CTL.drif_rdata_ack_vld;
1016 wire dram_Ch0_que_l2if_nack_vld = `MCU0_DRIF_CTL.drif_rdata_nack_vld;
1017
1018 wire dram_Ch0_que_init_dram_done = `MCU0_DRIF_CTL.drif_init_mcu_done;
1019
1020// ----- DRAM L2IF INTERFACE -----
1021
1022 wire [127:0] dram_Ch0_dram_sctag_data = `MCU0.mcu_l2b_data_r3;
1023 // Error signal for update of error status, error location and error address register.
1024 //wire dram_Ch0_l2if_scrb_val_d2 = `DRAM_L2IF0.l2if_scrb_val_d3;
1025
1026 // l2if_scrb_data_val is now qualifying scrb in the rtl
1027 wire dram_Ch0_l2if_scrb_val_d2 = `MCU0_RDPCTL_CTL.rdpctl_scrub_data_valid;
1028
1029 wire [6:0] dram_Ch0_err_sts_reg = `MCU0_RDPCTL_CTL.rdpctl_err_sts_reg[25:19];
1030
1031 wire dram_Ch0_l2if_err_sts_reg_en6 = `MCU0_RDPCTL_CTL.rdpctl_meu_error_en;
1032 wire dram_Ch0_l2if_err_sts_reg_en5 = `MCU0_RDPCTL_CTL.rdpctl_mec_error_en;
1033 wire dram_Ch0_l2if_err_sts_reg_en4 = `MCU0_RDPCTL_CTL.rdpctl_dac_error_en;
1034 wire dram_Ch0_l2if_err_sts_reg_en3 = `MCU0_RDPCTL_CTL.rdpctl_dau_error_en;
1035 wire dram_Ch0_l2if_err_sts_reg_en2 = `MCU0_RDPCTL_CTL.rdpctl_dsc_error_en;
1036 wire dram_Ch0_l2if_err_sts_reg_en1 = `MCU0_RDPCTL_CTL.rdpctl_dsu_error_en;
1037 wire dram_Ch0_l2if_err_sts_reg_en0 = `MCU0_RDPCTL_CTL.rdpctl_err_sts_reg_en;
1038 wire dram_Ch0_l2if_err_sts_reg_en = `MCU0_RDPCTL_CTL.rdpctl_dbu_error_en;
1039 wire dram_Ch0_l2if_err_addr_reg_en = `MCU0_RDPCTL_CTL.rdpctl_err_addr_reg_en;
1040 wire dram_Ch0_l2if_secc_loc_en = `MCU0_RDPCTL_CTL.rdpctl_secc_loc_en;
1041
1042
1043 wire dram_Ch0_l2b0_sctag_dram_rd_req = `MCU0_L2IF0_CTL.l2t_mcu_rd_req;
1044 wire [2:0] dram_Ch0_l2b0_sctag_dram_rd_req_id = `MCU0_L2IF0_CTL.l2t_mcu_rd_req_id;
1045// wire [39:6] dram_Ch0_l2b0_sctag_dram_addr = {`MCU0_ADDRDP_DP.l2t0_mcu_addr_39to9, `MCU0_ADDRDP_DP.l2t0_mcu_addr_6to4};
1046 wire [39:5] dram_Ch0_l2b0_sctag_dram_addr = `MCU0_L2IF0_CTL.l2t_mcu_addr;
1047 wire dram_Ch0_l2b0_sctag_dram_rd_dummy_req = `MCU0_L2IF0_CTL.l2t_mcu_rd_dummy_req;
1048 wire dram_Ch0_l2b0_dram_sctag_rd_ack = `MCU0_L2IF0_CTL.mcu_l2t_rd_ack;
1049 wire dram_Ch0_l2b0_sctag_dram_wr_req = `MCU0_L2IF0_CTL.l2t_mcu_wr_req;
1050 wire dram_Ch0_l2b0_sctag_dram_data_vld = `MCU0_L2IF0_CTL.l2b_mcu_data_vld;
1051 wire [63:0] dram_Ch0_l2b0_sctag_dram_wr_data = `MCU0_L2RDMX_DP.l2b0_mcu_wr_data_r5;
1052 wire dram_Ch0_l2b0_dram_sctag_wr_ack = `MCU0_L2IF0_CTL.mcu_l2t_wr_ack;
1053 wire dram_Ch0_l2b0_dram_sctag_data_vld = `MCU0_RDATA_CTL.mcu_l2t0_data_vld_r0;
1054 wire [2:0] dram_Ch0_l2b0_dram_sctag_rd_req_id = `MCU0_RDATA_CTL.mcu_l2t0_rd_req_id_r0;
1055
1056// MAQ N2 doesn't support wire [3:0] dram_Ch0_l2if_b0_rd_val = `DRAM_L2IF0.l2if_b0_rd_val;
1057// MAQ N2 doesn't support wire [3:0] dram_Ch0_l2if_b1_rd_val = `DRAM_L2IF0.l2if_b1_rd_val;
1058 wire [3:0] dram_Ch0_l2b0_l2if_b0_wr_val = {`MCU0_L2IF0_CTL.l2if_wr_entry3,
1059 `MCU0_L2IF0_CTL.l2if_wr_entry2,
1060 `MCU0_L2IF0_CTL.l2if_wr_entry1,
1061 `MCU0_L2IF0_CTL.l2if_wr_entry0};
1062
1063 wire [3:0] dram_Ch0_l2b0_l2if_b1_wr_val = {`MCU0_L2IF0_CTL.l2if_wr_entry7,
1064 `MCU0_L2IF0_CTL.l2if_wr_entry6,
1065 `MCU0_L2IF0_CTL.l2if_wr_entry5,
1066 `MCU0_L2IF0_CTL.l2if_wr_entry4};
1067
1068// MAQ wire [5:0] dram_Ch0_l2b0_l2if_wr_b0_data_addr = `MCU0_L2IF0_CTL.l2if_wdq_wadr;
1069
1070 // Signals on L2 Interface that indicates Error
1071 wire dram_Ch0_l2b0_dram_sctag_secc_err = `MCU0_RDATA_CTL.mcu_l2t0_secc_err_r3;
1072 wire dram_Ch0_l2b0_dram_sctag_pa_err = `MCU0_L2RDMX_DP.l2b0_rd_addr_err | `MCU0_L2RDMX_DP.l2b0_wr_addr_err;
1073 wire dram_Ch0_l2b0_dram_sctag_mecc_err = `MCU0_RDATA_CTL.mcu_l2t0_mecc_err_r3;
1074 wire dram_Ch0_l2b0_dram_sctag_scb_secc_err = `MCU0_RDATA_CTL.mcu_l2t0_scb_secc_err;
1075 wire dram_Ch0_l2b0_dram_sctag_scb_mecc_err = `MCU0_RDATA_CTL.mcu_l2t0_scb_mecc_err;
1076
1077// qualified with vld since they can be on due to residual ( previous error )
1078/* wire dram_Ch0_l2b0_l2if_secc_err = `MCU0_RDATA_CTL.mcu_l2t0_secc_err_r3 &&
1079 (`MCU0_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
1080 `MCU0_RDPCTL_CTL.rdpctl_scrub_data_valid);
1081
1082 wire dram_Ch0_l2b0_l2if_mecc_err_partial = `MCU0_RDATA_CTL.mcu_l2t0_mecc_err_r3 &&
1083 (`MCU0_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
1084 `MCU0_RDPCTL_CTL.rdpctl_scrub_data_valid);
1085*/
1086 wire dram_Ch0_l2b0_l2if_secc_err = `MCU0_RDATA_CTL.mcu_l2t0_scb_secc_err_in ||
1087 `MCU0_RDATA_CTL.mcu_l2t0_secc_err_r1;
1088 wire dram_Ch0_l2b0_l2if_mecc_err_partial = `MCU0_RDATA_CTL.mcu_l2t0_scb_mecc_err_in ||
1089 `MCU0_RDATA_CTL.mcu_l2t0_mecc_err_r1;
1090 wire dram_Ch0_l2b0_l2if_pa_err = (`MCU0_L2RDMX_DP.l2b0_rd_addr_err || `MCU0_L2RDMX_DP.l2b0_wr_addr_err) &&
1091 `MCU0_RDATA_CTL.mcu_l2t0_data_vld_r0;
1092
1093 wire [1:0] dram_Ch0_l2b0_cpu_wr_en = `MCU0_L2IF0_CTL.l2if_wdq_we;
1094 wire [4:0] dram_Ch0_l2b0_cpu_wr_addr = `MCU0_L2IF0_CTL.l2if_wdq_wadr;
1095 wire dram_Ch0_l2b0_wdq_rd_en = `MCU0_DRIF_CTL.drif0_wdq_rd;
1096 wire [4:0] dram_Ch0_l2b0_wdq_radr = `MCU0_DRIF_CTL.drif0_wdq_radr;
1097
1098 wire dram_Ch0_l2b0_clspine_dram_txrd_sync = `MCU0_RDATA_CTL.rdata_cmp_ddr_sync_en;
1099 wire dram_Ch0_l2b0_clspine_dram_txwr_sync = `MCU0_RDATA_CTL.rdata_cmp_ddr_sync_en;
1100
1101// l2if wr entry valid ( for the actual data valid creation)
1102 wire [7:0] dram_Ch0_l2b0_l2if_wr_entry = {
1103 `MCU0_L2IF0_CTL.l2if_wr_entry7,
1104 `MCU0_L2IF0_CTL.l2if_wr_entry6,
1105 `MCU0_L2IF0_CTL.l2if_wr_entry5,
1106 `MCU0_L2IF0_CTL.l2if_wr_entry4,
1107 `MCU0_L2IF0_CTL.l2if_wr_entry3,
1108 `MCU0_L2IF0_CTL.l2if_wr_entry2,
1109 `MCU0_L2IF0_CTL.l2if_wr_entry1,
1110 `MCU0_L2IF0_CTL.l2if_wr_entry0
1111 };
1112
1113
1114
1115/* wire [8:0] dram_Ch0_l2b0_rd_adr_info_hi = {
1116 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1117 `MCU0_L2B0_ADRGEN_DP.addr_err,
1118 `MCU0_DRIF_CTL.drif_stack_adr,
1119 `MCU0_L2B0_ADRGEN_DP.rank_adr,
1120 `MCU0_L2B0_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1121 `MCU0_L2B0_ADRGEN_DP.bank_adr[1:0],
1122 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1123 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1124 };
1125
1126 wire [8:0] dram_Ch0_l2b0_wr_adr_info_hi = {
1127 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1128 `MCU0_L2B0_ADRGEN_DP.addr_err,
1129 `MCU0_DRIF_CTL.drif_stack_adr,
1130 `MCU0_L2B0_ADRGEN_DP.rank_adr,
1131 `MCU0_L2B0_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1132 `MCU0_L2B0_ADRGEN_DP.bank_adr[1:0],
1133 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1134 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1135 };
1136
1137 wire [8:0] dram_Ch0_l2b0_rd_adr_info_lo = {
1138 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1139 `MCU0_L2B0_ADRGEN_DP.addr_err,
1140 `MCU0_DRIF_CTL.drif_stack_adr,
1141 `MCU0_L2B0_ADRGEN_DP.rank_adr,
1142 `MCU0_L2B0_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1143 `MCU0_L2B0_ADRGEN_DP.bank_adr[1:0],
1144 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1145 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1146 };
1147
1148 wire [8:0] dram_Ch0_l2b0_wr_adr_info_lo = {
1149 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1150 `MCU0_L2B0_ADRGEN_DP.addr_err,
1151 `MCU0_DRIF_CTL.drif_stack_adr,
1152 `MCU0_L2B0_ADRGEN_DP.rank_adr,
1153 `MCU0_L2B0_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1154 `MCU0_L2B0_ADRGEN_DP.bank_adr[1:0],
1155 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1156 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1157 };*/
1158
1159
1160 wire dram_Ch0_l2b1_sctag_dram_rd_req = `MCU0_L2IF1_CTL.l2t_mcu_rd_req;
1161 wire [2:0] dram_Ch0_l2b1_sctag_dram_rd_req_id = `MCU0_L2IF1_CTL.l2t_mcu_rd_req_id;
1162// wire [39:6] dram_Ch0_l2b1_sctag_dram_addr = {`MCU0_ADDRDP_DP.l2t1_mcu_addr_39to9, `MCU0_ADDRDP_DP.l2t1_mcu_addr_6to4};
1163 wire [39:5] dram_Ch0_l2b1_sctag_dram_addr = `MCU0_L2IF1_CTL.l2t_mcu_addr;
1164 wire dram_Ch0_l2b1_sctag_dram_rd_dummy_req = `MCU0_L2IF1_CTL.l2t_mcu_rd_dummy_req;
1165 wire dram_Ch0_l2b1_dram_sctag_rd_ack = `MCU0_L2IF1_CTL.mcu_l2t_rd_ack;
1166 wire dram_Ch0_l2b1_sctag_dram_wr_req = `MCU0_L2IF1_CTL.l2t_mcu_wr_req;
1167 wire dram_Ch0_l2b1_sctag_dram_data_vld = `MCU0_L2IF1_CTL.l2b_mcu_data_vld;
1168 wire [63:0] dram_Ch0_l2b1_sctag_dram_wr_data = `MCU0_L2RDMX_DP.l2b1_mcu_wr_data_r5;
1169 wire dram_Ch0_l2b1_dram_sctag_wr_ack = `MCU0_L2IF1_CTL.mcu_l2t_wr_ack;
1170 wire dram_Ch0_l2b1_dram_sctag_data_vld = `MCU0_RDATA_CTL.mcu_l2t1_data_vld_r0;
1171 wire [2:0] dram_Ch0_l2b1_dram_sctag_rd_req_id = `MCU0_RDATA_CTL.mcu_l2t1_rd_req_id_r0;
1172
1173// MAQ N2 doesn't support wire [3:0] dram_Ch0_l2if_b0_rd_val = `DRAM_L2IF0.l2if_b0_rd_val;
1174// MAQ N2 doesn't support wire [3:0] dram_Ch0_l2if_b1_rd_val = `DRAM_L2IF0.l2if_b1_rd_val;
1175 wire [3:0] dram_Ch0_l2b1_l2if_b0_wr_val = {`MCU0_L2IF1_CTL.l2if_wr_entry3,
1176 `MCU0_L2IF1_CTL.l2if_wr_entry2,
1177 `MCU0_L2IF1_CTL.l2if_wr_entry1,
1178 `MCU0_L2IF1_CTL.l2if_wr_entry0};
1179
1180 wire [3:0] dram_Ch0_l2b1_l2if_b1_wr_val = {`MCU0_L2IF1_CTL.l2if_wr_entry7,
1181 `MCU0_L2IF1_CTL.l2if_wr_entry6,
1182 `MCU0_L2IF1_CTL.l2if_wr_entry5,
1183 `MCU0_L2IF1_CTL.l2if_wr_entry4};
1184
1185// MAQ wire [5:0] dram_Ch0_l2b1_l2if_wr_b0_data_addr = `MCU0_L2IF1_CTL.l2if_wdq_wadr;
1186
1187 // Signals on L2 Interface that indicates Error
1188 wire dram_Ch0_l2b1_dram_sctag_secc_err = `MCU0_RDATA_CTL.mcu_l2t1_secc_err_r3;
1189 wire dram_Ch0_l2b1_dram_sctag_pa_err = `MCU0_L2RDMX_DP.l2b1_rd_addr_err | `MCU0_L2RDMX_DP.l2b1_wr_addr_err;
1190 wire dram_Ch0_l2b1_dram_sctag_mecc_err = `MCU0_RDATA_CTL.mcu_l2t1_mecc_err_r3;
1191 wire dram_Ch0_l2b1_dram_sctag_scb_secc_err = `MCU0_RDATA_CTL.mcu_l2t1_scb_secc_err;
1192 wire dram_Ch0_l2b1_dram_sctag_scb_mecc_err = `MCU0_RDATA_CTL.mcu_l2t1_scb_mecc_err;
1193
1194// qualified with vld since they can be on due to residual ( previous error )
1195/* wire dram_Ch0_l2b1_l2if_secc_err = `MCU0_RDATA_CTL.mcu_l2t1_secc_err_r3 &&
1196 (`MCU0_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
1197 `MCU0_RDPCTL_CTL.rdpctl_scrub_data_valid);
1198
1199 wire dram_Ch0_l2b1_l2if_mecc_err_partial = `MCU0_RDATA_CTL.mcu_l2t1_mecc_err_r3 &&
1200 (`MCU0_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
1201 `MCU0_RDPCTL_CTL.rdpctl_scrub_data_valid);
1202*/
1203 wire dram_Ch0_l2b1_l2if_secc_err = `MCU0_RDATA_CTL.mcu_l2t1_scb_secc_err_in ||
1204 `MCU0_RDATA_CTL.mcu_l2t1_secc_err_r1;
1205 wire dram_Ch0_l2b1_l2if_mecc_err_partial = `MCU0_RDATA_CTL.mcu_l2t1_scb_mecc_err_in ||
1206 `MCU0_RDATA_CTL.mcu_l2t1_mecc_err_r1;
1207 wire dram_Ch0_l2b1_l2if_pa_err = (`MCU0_L2RDMX_DP.l2b1_rd_addr_err || `MCU0_L2RDMX_DP.l2b1_wr_addr_err) &&
1208 `MCU0_RDATA_CTL.mcu_l2t1_data_vld_r0;
1209
1210 wire [1:0] dram_Ch0_l2b1_cpu_wr_en = `MCU0_L2IF1_CTL.l2if_wdq_we;
1211 wire [4:0] dram_Ch0_l2b1_cpu_wr_addr = `MCU0_L2IF1_CTL.l2if_wdq_wadr;
1212 wire dram_Ch0_l2b1_wdq_rd_en = `MCU0_DRIF_CTL.drif1_wdq_rd;
1213 wire [4:0] dram_Ch0_l2b1_wdq_radr = `MCU0_DRIF_CTL.drif1_wdq_radr;
1214
1215 wire dram_Ch0_l2b1_clspine_dram_txrd_sync = `MCU0_RDATA_CTL.rdata_cmp_ddr_sync_en;
1216 wire dram_Ch0_l2b1_clspine_dram_txwr_sync = `MCU0_RDATA_CTL.rdata_cmp_ddr_sync_en;
1217
1218// l2if wr entry valid ( for the actual data valid creation)
1219 wire [7:0] dram_Ch0_l2b1_l2if_wr_entry = {
1220 `MCU0_L2IF1_CTL.l2if_wr_entry7,
1221 `MCU0_L2IF1_CTL.l2if_wr_entry6,
1222 `MCU0_L2IF1_CTL.l2if_wr_entry5,
1223 `MCU0_L2IF1_CTL.l2if_wr_entry4,
1224 `MCU0_L2IF1_CTL.l2if_wr_entry3,
1225 `MCU0_L2IF1_CTL.l2if_wr_entry2,
1226 `MCU0_L2IF1_CTL.l2if_wr_entry1,
1227 `MCU0_L2IF1_CTL.l2if_wr_entry0
1228 };
1229
1230
1231
1232/* wire [8:0] dram_Ch0_l2b1_rd_adr_info_hi = {
1233 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1234 `MCU0_L2B1_ADRGEN_DP.addr_err,
1235 `MCU0_DRIF_CTL.drif_stack_adr,
1236 `MCU0_L2B1_ADRGEN_DP.rank_adr,
1237 `MCU0_L2B1_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1238 `MCU0_L2B1_ADRGEN_DP.bank_adr[1:0],
1239 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1240 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1241 };
1242
1243 wire [8:0] dram_Ch0_l2b1_wr_adr_info_hi = {
1244 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1245 `MCU0_L2B1_ADRGEN_DP.addr_err,
1246 `MCU0_DRIF_CTL.drif_stack_adr,
1247 `MCU0_L2B1_ADRGEN_DP.rank_adr,
1248 `MCU0_L2B1_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1249 `MCU0_L2B1_ADRGEN_DP.bank_adr[1:0],
1250 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1251 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1252 };
1253
1254 wire [8:0] dram_Ch0_l2b1_rd_adr_info_lo = {
1255 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1256 `MCU0_L2B1_ADRGEN_DP.addr_err,
1257 `MCU0_DRIF_CTL.drif_stack_adr,
1258 `MCU0_L2B1_ADRGEN_DP.rank_adr,
1259 `MCU0_L2B1_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1260 `MCU0_L2B1_ADRGEN_DP.bank_adr[1:0],
1261 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1262 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1263 };
1264
1265 wire [8:0] dram_Ch0_l2b1_wr_adr_info_lo = {
1266 `MCU0_DRIF_CTL.drif_addr_bank_low_sel,
1267 `MCU0_L2B1_ADRGEN_DP.addr_err,
1268 `MCU0_DRIF_CTL.drif_stack_adr,
1269 `MCU0_L2B1_ADRGEN_DP.rank_adr,
1270 `MCU0_L2B1_ADRGEN_DP.bank_adr[2] && `MCU0_DRIF_CTL.drif_eight_bank_mode,
1271 `MCU0_L2B1_ADRGEN_DP.bank_adr[1:0],
1272 `MCU0_DRIF_CTL.drif_eight_bank_mode,
1273 1'b0 // `DRAM_L2IF0.dram_rd_addr_gen_hi.two_channel_mode
1274 };*/
1275
1276
1277
1278// ---- Performance counters ----
1279
1280 wire [7:0] dram_Ch0_perf_cntl = `MCU0_DRIF_CTL.drif_perf_cntl_reg;
1281 wire dram_Ch0_cnt0_sticky_bit = `MCU0_DRIF_CTL.drif_perf_cnt0_reg[31];
1282 wire dram_Ch0_cnt1_sticky_bit = `MCU0_DRIF_CTL.drif_perf_cnt1_reg[31];
1283
1284 // read que request
1285 wire dram_Ch1_l2b0_rd_req = `MCU1_L2IF0_CTL.l2t_mcu_rd_req;
1286 wire [2:0] dram_Ch1_l2b0_rd_id = `MCU1_L2IF0_CTL.l2t_mcu_rd_req_id[2:0];
1287 wire dram_Ch1_l2b0_errq_vld = (!`MCU1_DRIF_CTL.drif_err_fifo_empty) & (`MCU1_DRIF_CTL.rdpctl_err_fifo_data[0] == 0) ;
1288 wire [2:0] dram_Ch1_l2b0_errq_id = `MCU1_DRIF_CTL.rdpctl_err_fifo_data[4:2];
1289 // read que
1290 wire dram_ch1_l2b0_rd_q_vld_0 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1291 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1292 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1293 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1294 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1295 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1296 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) |
1297 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0])) };
1298
1299 wire dram_ch1_l2b0_rd_q_vld_1 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1300 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1301 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1302 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1303 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1304 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1305 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) |
1306 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1])) };
1307
1308 wire dram_ch1_l2b0_rd_q_vld_2 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1309 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1310 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1311 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1312 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1313 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1314 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) |
1315 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2])) };
1316
1317 wire dram_ch1_l2b0_rd_q_vld_3 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1318 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1319 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1320 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1321 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1322 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1323 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) |
1324 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3])) };
1325
1326 wire dram_ch1_l2b0_rd_q_vld_4 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1327 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1328 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1329 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1330 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1331 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1332 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) |
1333 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4])) };
1334
1335 wire dram_ch1_l2b0_rd_q_vld_5 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1336 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1337 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1338 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1339 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1340 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1341 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) |
1342 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5])) };
1343
1344 wire dram_ch1_l2b0_rd_q_vld_6 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1345 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1346 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1347 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1348 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1349 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1350 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) |
1351 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6])) };
1352
1353 wire dram_ch1_l2b0_rd_q_vld_7 = { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1354 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1355 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1356 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1357 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1358 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1359 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) |
1360 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7])) };
1361
1362 wire [7:0] dram_ch1_l2b0_rd_q_valids = {dram_ch1_l2b0_rd_q_vld_7, dram_ch1_l2b0_rd_q_vld_6, dram_ch1_l2b0_rd_q_vld_5, dram_ch1_l2b0_rd_q_vld_4,
1363 dram_ch1_l2b0_rd_q_vld_3, dram_ch1_l2b0_rd_q_vld_2, dram_ch1_l2b0_rd_q_vld_1, dram_ch1_l2b0_rd_q_vld_0};
1364
1365// Read request Q PA-Error
1366 wire dram_ch1_l2b0_rd_q_addr_err_0 =
1367 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1368 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1369 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1370 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1371 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1372 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1373 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1374 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1375
1376 wire dram_ch1_l2b0_rd_q_addr_err_1 =
1377 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1378 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1379 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1380 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1381 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1382 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1383 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1384 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) };
1385
1386 wire dram_ch1_l2b0_rd_q_addr_err_2 =
1387 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1388 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1389 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1390 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1391 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1392 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1393 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1394 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1395
1396 wire dram_ch1_l2b0_rd_q_addr_err_3 =
1397 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1398 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1399 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1400 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1401 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1402 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1403 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1404 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1405
1406 wire dram_ch1_l2b0_rd_q_addr_err_4 =
1407 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1408 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1409 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1410 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1411 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1412 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1413 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1414 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1415
1416 wire dram_ch1_l2b0_rd_q_addr_err_5 =
1417 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1418 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1419 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1420 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1421 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1422 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1423 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1424 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1425
1426 wire dram_ch1_l2b0_rd_q_addr_err_6 =
1427 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1428 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1429 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1430 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1431 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1432 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1433 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1434 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1435
1436 wire dram_ch1_l2b0_rd_q_addr_err_7 =
1437 { ((`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent0[7]) |
1438 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent1[7]) |
1439 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent2[7]) |
1440 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent3[7]) |
1441 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent4[7]) |
1442 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent5[7]) |
1443 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent6[7]) |
1444 ((`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU1_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ0_CTL.drq_rd_queue_ent7[7]) };
1445
1446 wire [7:0] dram_ch1_l2b0_rd_q_addr_err = {dram_ch1_l2b0_rd_q_addr_err_7, dram_ch1_l2b0_rd_q_addr_err_6, dram_ch1_l2b0_rd_q_addr_err_5, dram_ch1_l2b0_rd_q_addr_err_4,
1447 dram_ch1_l2b0_rd_q_addr_err_3, dram_ch1_l2b0_rd_q_addr_err_2, dram_ch1_l2b0_rd_q_addr_err_1, dram_ch1_l2b0_rd_q_addr_err_0};
1448
1449 wire [7:0] dram_ch1_l2b0_drq_rd_queue_valid = {`MCU1_DRQ0_CTL.drq_rd_queue_valid[7:0]};
1450 wire [3:0] dram_ch1_l2b0_drq_read_queue_cnt = {`MCU1_DRQ0_CTL.drq_read_queue_cnt[3:0]};
1451
1452// Read request Q PA-Error
1453
1454 wire [39:0] dram_Ch1_l2b0_rd_q_0 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[0],
1455 `MCU1_L2B0_ADR_Q.rd_req_id_queue0[2:0],
1456 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue0[3:0],
1457 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue0[2:0],
1458 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue0[14:0],
1459 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue0[10:0],
1460 3'b0 };
1461
1462 wire [39:0] dram_Ch1_l2b0_rd_q_1 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[1],
1463 `MCU1_L2B0_ADR_Q.rd_req_id_queue1[2:0],
1464 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue1[3:0],
1465 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue1[2:0],
1466 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue1[14:0],
1467 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue1[10:0],
1468 3'b0 };
1469
1470 wire [39:0] dram_Ch1_l2b0_rd_q_2 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[2],
1471 `MCU1_L2B0_ADR_Q.rd_req_id_queue2[2:0],
1472 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue2[3:0],
1473 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue2[2:0],
1474 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue2[14:0],
1475 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue2[10:0],
1476 3'b0 };
1477
1478 wire [39:0] dram_Ch1_l2b0_rd_q_3 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[3],
1479 `MCU1_L2B0_ADR_Q.rd_req_id_queue3[2:0],
1480 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue3[3:0],
1481 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue3[2:0],
1482 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue3[14:0],
1483 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue3[10:0],
1484 3'b0 };
1485
1486 wire [39:0] dram_Ch1_l2b0_rd_q_4 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[4],
1487 `MCU1_L2B0_ADR_Q.rd_req_id_queue4[2:0],
1488 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue4[3:0],
1489 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue4[2:0],
1490 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue4[14:0],
1491 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue4[10:0],
1492 3'b0 };
1493
1494 wire [39:0] dram_Ch1_l2b0_rd_q_5 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[5],
1495 `MCU1_L2B0_ADR_Q.rd_req_id_queue5[2:0],
1496 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue5[3:0],
1497 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue5[2:0],
1498 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue5[14:0],
1499 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue5[10:0],
1500 3'b0 };
1501
1502 wire [39:0] dram_Ch1_l2b0_rd_q_6 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[6],
1503 `MCU1_L2B0_ADR_Q.rd_req_id_queue6[2:0],
1504 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue6[3:0],
1505 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue6[2:0],
1506 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue6[14:0],
1507 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue6[10:0],
1508 3'b0 };
1509
1510 wire [39:0] dram_Ch1_l2b0_rd_q_7 = {`MCU1_DRQ0_CTL.drq_rdbuf_valids[7],
1511 `MCU1_L2B0_ADR_Q.rd_req_id_queue7[2:0],
1512 `MCU1_L2B0_ADR_Q.rank_rd_adr_queue7[3:0],
1513 `MCU1_L2B0_ADR_Q.bank_rd_adr_queue7[2:0],
1514 `MCU1_L2B0_ADR_Q.ras_rd_adr_queue7[14:0],
1515 `MCU1_L2B0_ADR_Q.cas_rd_adr_queue7[10:0],
1516 3'b0 };
1517
1518
1519 reg [39:0] dram_Ch1_l2b0_rd_q[7:0];
1520 // read que collapsing fifo
1521 wire [11:0] dram_Ch1_l2b0_rd_colps_q_0 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent0[11:0]};
1522 wire [11:0] dram_Ch1_l2b0_rd_colps_q_1 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent1[11:0]};
1523 wire [11:0] dram_Ch1_l2b0_rd_colps_q_2 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent2[11:0]};
1524 wire [11:0] dram_Ch1_l2b0_rd_colps_q_3 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent3[11:0]};
1525 wire [11:0] dram_Ch1_l2b0_rd_colps_q_4 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent4[11:0]};
1526 wire [11:0] dram_Ch1_l2b0_rd_colps_q_5 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent5[11:0]};
1527 wire [11:0] dram_Ch1_l2b0_rd_colps_q_6 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent6[11:0]};
1528 wire [11:0] dram_Ch1_l2b0_rd_colps_q_7 = {`MCU1_DRQ0_CTL.drq_rd_queue_ent7[11:0]};
1529
1530 reg [11:0] dram_Ch1_l2b0_rd_colps_q[7:0];
1531
1532 // read que write pointer
1533 wire [7:0] dram_Ch1_l2b0_rd_que_wr_ptr = {`MCU1_DRQ0_CTL.drq_rd_adr_queue7_en,
1534 `MCU1_DRQ0_CTL.drq_rd_adr_queue6_en,
1535 `MCU1_DRQ0_CTL.drq_rd_adr_queue5_en,
1536 `MCU1_DRQ0_CTL.drq_rd_adr_queue4_en,
1537 `MCU1_DRQ0_CTL.drq_rd_adr_queue3_en,
1538 `MCU1_DRQ0_CTL.drq_rd_adr_queue2_en,
1539 `MCU1_DRQ0_CTL.drq_rd_adr_queue1_en,
1540 `MCU1_DRQ0_CTL.drq_rd_adr_queue0_en};
1541 // read que read pointer
1542 wire [7:0] dram_Ch1_l2b0_rd_que_rd_ptr = {`MCU1_DRQ0_CTL.rdpctl_drq_clear_ent[7:0]};
1543
1544 // write que request
1545 wire dram_Ch1_l2b0_wr_req = `MCU1_L2IF0_CTL.l2t_mcu_wr_req;
1546 wire [2:0] dram_Ch1_l2b0_wr_addr = `MCU1_L2IF0_CTL.l2if_data_wr_addr;
1547
1548 wire [7:0] dram_ch1_l2b0_wr_q_valids = {`MCU1_DRQ0_CTL.drq_wr_queue_valid[7:0]};
1549 wire [3:0] dram_ch1_l2b0_drq_write_queue_cnt = {`MCU1_DRQ0_CTL.drq_write_queue_cnt[3:0]};
1550
1551 wire [40:0] dram_Ch1_l2b0_wr_q_0 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[0],
1552 `MCU1_DRQ0_CTL.drq_wrbuf_valids[0], //`DRAM_PATH1.writeqbank0vld0_arb,
1553 `MCU1_DRQ0_CTL.drq_wr_queue_ent0[11:9],
1554 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue0[3:0],
1555 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue0[2:0],
1556 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue0[14:0],
1557 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue0[10:0],
1558 3'b0};
1559
1560 wire [40:0] dram_Ch1_l2b0_wr_q_1 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[1],
1561 `MCU1_DRQ0_CTL.drq_wrbuf_valids[1], //`DRAM_PATH1.writeqbank0vld0_arb,
1562 `MCU1_DRQ0_CTL.drq_wr_queue_ent1[11:9],
1563 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue1[3:0],
1564 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue1[2:0],
1565 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue1[14:0],
1566 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue1[10:0],
1567 3'b0};
1568
1569 wire [40:0] dram_Ch1_l2b0_wr_q_2 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[2],
1570 `MCU1_DRQ0_CTL.drq_wrbuf_valids[2], //`DRAM_PATH1.writeqbank0vld0_arb,
1571 `MCU1_DRQ0_CTL.drq_wr_queue_ent2[11:9],
1572 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue2[3:0],
1573 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue2[2:0],
1574 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue2[14:0],
1575 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue2[10:0],
1576 3'b0};
1577
1578 wire [40:0] dram_Ch1_l2b0_wr_q_3 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[3],
1579 `MCU1_DRQ0_CTL.drq_wrbuf_valids[3], //`DRAM_PATH1.writeqbank0vld0_arb,
1580 `MCU1_DRQ0_CTL.drq_wr_queue_ent3[11:9],
1581 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue3[3:0],
1582 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue3[2:0],
1583 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue3[14:0],
1584 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue3[10:0],
1585 3'b0};
1586
1587 wire [40:0] dram_Ch1_l2b0_wr_q_4 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[4],
1588 `MCU1_DRQ0_CTL.drq_wrbuf_valids[4], //`DRAM_PATH1.writeqbank0vld0_arb,
1589 `MCU1_DRQ0_CTL.drq_wr_queue_ent4[11:9],
1590 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue4[3:0],
1591 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue4[2:0],
1592 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue4[14:0],
1593 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue4[10:0],
1594 3'b0};
1595
1596 wire [40:0] dram_Ch1_l2b0_wr_q_5 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[5],
1597 `MCU1_DRQ0_CTL.drq_wrbuf_valids[5], //`DRAM_PATH1.writeqbank0vld0_arb,
1598 `MCU1_DRQ0_CTL.drq_wr_queue_ent5[11:9],
1599 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue5[3:0],
1600 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue5[2:0],
1601 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue5[14:0],
1602 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue5[10:0],
1603 3'b0};
1604
1605 wire [40:0] dram_Ch1_l2b0_wr_q_6 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[6],
1606 `MCU1_DRQ0_CTL.drq_wrbuf_valids[6], //`DRAM_PATH1.writeqbank0vld0_arb,
1607 `MCU1_DRQ0_CTL.drq_wr_queue_ent6[11:9],
1608 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue6[3:0],
1609 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue6[2:0],
1610 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue6[14:0],
1611 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue6[10:0],
1612 3'b0};
1613
1614 wire [40:0] dram_Ch1_l2b0_wr_q_7 = {`MCU1_DRQ0_CTL.drq_wrbuf_valids[7],
1615 `MCU1_DRQ0_CTL.drq_wrbuf_valids[7], //`DRAM_PATH1.writeqbank0vld0_arb,
1616 `MCU1_DRQ0_CTL.drq_wr_queue_ent7[11:9],
1617 `MCU1_L2B0_ADR_Q.rank_wr_adr_queue7[3:0],
1618 `MCU1_L2B0_ADR_Q.bank_wr_adr_queue7[2:0],
1619 `MCU1_L2B0_ADR_Q.ras_wr_adr_queue7[14:0],
1620 `MCU1_L2B0_ADR_Q.cas_wr_adr_queue7[10:0],
1621 3'b0};
1622
1623 reg [40:0] dram_Ch1_l2b0_wr_q[7:0];
1624
1625 // to not set valid for the fifo monitor
1626 wire dram_Ch1_l2b0_pa_err = `MCU1_L2RDMX_DP.l2b0_wr_addr_err;
1627
1628 // write que collapsing fifo
1629 wire [14:0] dram_Ch1_l2b0_wr_colps_q_0 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent0[14:0]};
1630 wire [14:0] dram_Ch1_l2b0_wr_colps_q_1 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent1[14:0]};
1631 wire [14:0] dram_Ch1_l2b0_wr_colps_q_2 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent2[14:0]};
1632 wire [14:0] dram_Ch1_l2b0_wr_colps_q_3 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent3[14:0]};
1633 wire [14:0] dram_Ch1_l2b0_wr_colps_q_4 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent4[14:0]};
1634 wire [14:0] dram_Ch1_l2b0_wr_colps_q_5 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent5[14:0]};
1635 wire [14:0] dram_Ch1_l2b0_wr_colps_q_6 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent6[14:0]};
1636 wire [14:0] dram_Ch1_l2b0_wr_colps_q_7 = {`MCU1_DRQ0_CTL.drq_wr_queue_ent7[14:0]};
1637
1638 reg [14:0] dram_Ch1_l2b0_wr_colps_q[7:0];
1639
1640 // write que write pointer
1641 wire [7:0] dram_Ch1_l2b0_wr_que_wr_ptr = {`MCU1_DRQ0_CTL.drq_wr_adr_queue7_en,
1642 `MCU1_DRQ0_CTL.drq_wr_adr_queue6_en,
1643 `MCU1_DRQ0_CTL.drq_wr_adr_queue5_en,
1644 `MCU1_DRQ0_CTL.drq_wr_adr_queue4_en,
1645 `MCU1_DRQ0_CTL.drq_wr_adr_queue3_en,
1646 `MCU1_DRQ0_CTL.drq_wr_adr_queue2_en,
1647 `MCU1_DRQ0_CTL.drq_wr_adr_queue1_en,
1648 `MCU1_DRQ0_CTL.drq_wr_adr_queue0_en};
1649
1650 // write que arb read pointer
1651
1652 // write que data read pointer
1653 /*wire [7:0] dram_Ch1_l2b0_wr_que_rd_ptr = {`MCU1_DRQ0_CTL.drq_wr_entry7_rank,
1654 `MCU1_DRQ0_CTL.drq_wr_entry6_rank,
1655 `MCU1_DRQ0_CTL.drq_wr_entry5_rank,
1656 `MCU1_DRQ0_CTL.drq_wr_entry4_rank,
1657 `MCU1_DRQ0_CTL.drq_wr_entry3_rank,
1658 `MCU1_DRQ0_CTL.drq_wr_entry2_rank,
1659 `MCU1_DRQ0_CTL.drq_wr_entry1_rank,
1660 `MCU1_DRQ0_CTL.drq_wr_entry0_rank};*/
1661 wire [7:0] dram_Ch1_l2b0_wr_que_rd_ptr = `MCU1_DRQ0_CTL.drq_wrq_clear_ent;
1662
1663
1664// These signals are currently not used in cov obj
1665// enable for 8 deep collps rd fifo
1666 wire [7:0] dram_Ch1_l2b0_que_b0_index_en = {`MCU1_L2B0_ADR_Q.rd_adr_queue_sel[7:0]};
1667
1668
1669// These signals are currently not used in cov obj
1670// enable for 8 deep collps wr fifo
1671 wire [7:0] dram_Ch1_l2b0_que_b0_wr_index_en= {`MCU1_L2B0_ADR_Q.wr_adr_queue_sel[7:0]};
1672
1673// These signals are currently not used in cov obj
1674// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
1675 wire [7:0] dram_Ch1_l2b0_que_b0_rd_in_val = `MCU1_DRQ0_CTL.drq_rd_entry0_val[7:0];
1676
1677 wire dram_Ch1_que_b0_rd_picked = `MCU1_DRIF_CTL.drif0_rd_picked;
1678 wire dram_Ch1_que_b0_wr_picked = `MCU1_DRIF_CTL.drif0_wr_picked;
1679 // read que request
1680 wire dram_Ch1_l2b1_rd_req = `MCU1_L2IF1_CTL.l2t_mcu_rd_req;
1681 wire [2:0] dram_Ch1_l2b1_rd_id = `MCU1_L2IF1_CTL.l2t_mcu_rd_req_id[2:0];
1682 wire dram_Ch1_l2b1_errq_vld = (!`MCU1_DRIF_CTL.drif_err_fifo_empty) & (`MCU1_DRIF_CTL.rdpctl_err_fifo_data[0] == 1) ;
1683 wire [2:0] dram_Ch1_l2b1_errq_id = `MCU1_DRIF_CTL.rdpctl_err_fifo_data[4:2];
1684 // read que
1685 wire dram_ch1_l2b1_rd_q_vld_0 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1686 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1687 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1688 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1689 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1690 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1691 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) |
1692 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0])) };
1693
1694 wire dram_ch1_l2b1_rd_q_vld_1 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1695 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1696 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1697 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1698 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1699 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1700 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) |
1701 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1])) };
1702
1703 wire dram_ch1_l2b1_rd_q_vld_2 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1704 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1705 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1706 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1707 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1708 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1709 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) |
1710 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2])) };
1711
1712 wire dram_ch1_l2b1_rd_q_vld_3 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1713 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1714 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1715 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1716 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1717 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1718 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) |
1719 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3])) };
1720
1721 wire dram_ch1_l2b1_rd_q_vld_4 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1722 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1723 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1724 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1725 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1726 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1727 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) |
1728 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4])) };
1729
1730 wire dram_ch1_l2b1_rd_q_vld_5 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1731 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1732 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1733 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1734 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1735 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1736 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) |
1737 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5])) };
1738
1739 wire dram_ch1_l2b1_rd_q_vld_6 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1740 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1741 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1742 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1743 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1744 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1745 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) |
1746 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6])) };
1747
1748 wire dram_ch1_l2b1_rd_q_vld_7 = { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1749 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1750 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1751 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1752 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1753 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1754 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) |
1755 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7])) };
1756
1757 wire [7:0] dram_ch1_l2b1_rd_q_valids = {dram_ch1_l2b1_rd_q_vld_7, dram_ch1_l2b1_rd_q_vld_6, dram_ch1_l2b1_rd_q_vld_5, dram_ch1_l2b1_rd_q_vld_4,
1758 dram_ch1_l2b1_rd_q_vld_3, dram_ch1_l2b1_rd_q_vld_2, dram_ch1_l2b1_rd_q_vld_1, dram_ch1_l2b1_rd_q_vld_0};
1759
1760// Read request Q PA-Error
1761 wire dram_ch1_l2b1_rd_q_addr_err_0 =
1762 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1763 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1764 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1765 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1766 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1767 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1768 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1769 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1770
1771 wire dram_ch1_l2b1_rd_q_addr_err_1 =
1772 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1773 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1774 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1775 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1776 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1777 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1778 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1779 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) };
1780
1781 wire dram_ch1_l2b1_rd_q_addr_err_2 =
1782 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1783 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1784 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1785 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1786 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1787 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1788 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1789 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1790
1791 wire dram_ch1_l2b1_rd_q_addr_err_3 =
1792 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1793 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1794 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1795 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1796 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1797 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1798 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1799 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1800
1801 wire dram_ch1_l2b1_rd_q_addr_err_4 =
1802 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1803 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1804 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1805 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1806 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1807 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1808 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1809 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1810
1811 wire dram_ch1_l2b1_rd_q_addr_err_5 =
1812 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1813 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1814 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1815 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1816 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1817 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1818 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1819 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1820
1821 wire dram_ch1_l2b1_rd_q_addr_err_6 =
1822 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1823 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1824 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1825 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1826 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1827 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1828 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1829 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1830
1831 wire dram_ch1_l2b1_rd_q_addr_err_7 =
1832 { ((`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent0[7]) |
1833 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent1[7]) |
1834 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent2[7]) |
1835 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent3[7]) |
1836 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent4[7]) |
1837 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent5[7]) |
1838 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent6[7]) |
1839 ((`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU1_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU1_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU1_DRQ1_CTL.drq_rd_queue_ent7[7]) };
1840
1841 wire [7:0] dram_ch1_l2b1_rd_q_addr_err = {dram_ch1_l2b1_rd_q_addr_err_7, dram_ch1_l2b1_rd_q_addr_err_6, dram_ch1_l2b1_rd_q_addr_err_5, dram_ch1_l2b1_rd_q_addr_err_4,
1842 dram_ch1_l2b1_rd_q_addr_err_3, dram_ch1_l2b1_rd_q_addr_err_2, dram_ch1_l2b1_rd_q_addr_err_1, dram_ch1_l2b1_rd_q_addr_err_0};
1843
1844 wire [7:0] dram_ch1_l2b1_drq_rd_queue_valid = {`MCU1_DRQ1_CTL.drq_rd_queue_valid[7:0]};
1845 wire [3:0] dram_ch1_l2b1_drq_read_queue_cnt = {`MCU1_DRQ1_CTL.drq_read_queue_cnt[3:0]};
1846
1847// Read request Q PA-Error
1848
1849 wire [39:0] dram_Ch1_l2b1_rd_q_0 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[0],
1850 `MCU1_L2B1_ADR_Q.rd_req_id_queue0[2:0],
1851 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue0[3:0],
1852 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue0[2:0],
1853 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue0[14:0],
1854 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue0[10:0],
1855 3'b0 };
1856
1857 wire [39:0] dram_Ch1_l2b1_rd_q_1 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[1],
1858 `MCU1_L2B1_ADR_Q.rd_req_id_queue1[2:0],
1859 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue1[3:0],
1860 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue1[2:0],
1861 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue1[14:0],
1862 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue1[10:0],
1863 3'b0 };
1864
1865 wire [39:0] dram_Ch1_l2b1_rd_q_2 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[2],
1866 `MCU1_L2B1_ADR_Q.rd_req_id_queue2[2:0],
1867 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue2[3:0],
1868 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue2[2:0],
1869 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue2[14:0],
1870 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue2[10:0],
1871 3'b0 };
1872
1873 wire [39:0] dram_Ch1_l2b1_rd_q_3 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[3],
1874 `MCU1_L2B1_ADR_Q.rd_req_id_queue3[2:0],
1875 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue3[3:0],
1876 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue3[2:0],
1877 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue3[14:0],
1878 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue3[10:0],
1879 3'b0 };
1880
1881 wire [39:0] dram_Ch1_l2b1_rd_q_4 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[4],
1882 `MCU1_L2B1_ADR_Q.rd_req_id_queue4[2:0],
1883 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue4[3:0],
1884 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue4[2:0],
1885 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue4[14:0],
1886 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue4[10:0],
1887 3'b0 };
1888
1889 wire [39:0] dram_Ch1_l2b1_rd_q_5 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[5],
1890 `MCU1_L2B1_ADR_Q.rd_req_id_queue5[2:0],
1891 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue5[3:0],
1892 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue5[2:0],
1893 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue5[14:0],
1894 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue5[10:0],
1895 3'b0 };
1896
1897 wire [39:0] dram_Ch1_l2b1_rd_q_6 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[6],
1898 `MCU1_L2B1_ADR_Q.rd_req_id_queue6[2:0],
1899 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue6[3:0],
1900 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue6[2:0],
1901 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue6[14:0],
1902 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue6[10:0],
1903 3'b0 };
1904
1905 wire [39:0] dram_Ch1_l2b1_rd_q_7 = {`MCU1_DRQ1_CTL.drq_rdbuf_valids[7],
1906 `MCU1_L2B1_ADR_Q.rd_req_id_queue7[2:0],
1907 `MCU1_L2B1_ADR_Q.rank_rd_adr_queue7[3:0],
1908 `MCU1_L2B1_ADR_Q.bank_rd_adr_queue7[2:0],
1909 `MCU1_L2B1_ADR_Q.ras_rd_adr_queue7[14:0],
1910 `MCU1_L2B1_ADR_Q.cas_rd_adr_queue7[10:0],
1911 3'b0 };
1912
1913
1914 reg [39:0] dram_Ch1_l2b1_rd_q[7:0];
1915 // read que collapsing fifo
1916 wire [11:0] dram_Ch1_l2b1_rd_colps_q_0 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent0[11:0]};
1917 wire [11:0] dram_Ch1_l2b1_rd_colps_q_1 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent1[11:0]};
1918 wire [11:0] dram_Ch1_l2b1_rd_colps_q_2 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent2[11:0]};
1919 wire [11:0] dram_Ch1_l2b1_rd_colps_q_3 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent3[11:0]};
1920 wire [11:0] dram_Ch1_l2b1_rd_colps_q_4 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent4[11:0]};
1921 wire [11:0] dram_Ch1_l2b1_rd_colps_q_5 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent5[11:0]};
1922 wire [11:0] dram_Ch1_l2b1_rd_colps_q_6 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent6[11:0]};
1923 wire [11:0] dram_Ch1_l2b1_rd_colps_q_7 = {`MCU1_DRQ1_CTL.drq_rd_queue_ent7[11:0]};
1924
1925 reg [11:0] dram_Ch1_l2b1_rd_colps_q[7:0];
1926
1927 // read que write pointer
1928 wire [7:0] dram_Ch1_l2b1_rd_que_wr_ptr = {`MCU1_DRQ1_CTL.drq_rd_adr_queue7_en,
1929 `MCU1_DRQ1_CTL.drq_rd_adr_queue6_en,
1930 `MCU1_DRQ1_CTL.drq_rd_adr_queue5_en,
1931 `MCU1_DRQ1_CTL.drq_rd_adr_queue4_en,
1932 `MCU1_DRQ1_CTL.drq_rd_adr_queue3_en,
1933 `MCU1_DRQ1_CTL.drq_rd_adr_queue2_en,
1934 `MCU1_DRQ1_CTL.drq_rd_adr_queue1_en,
1935 `MCU1_DRQ1_CTL.drq_rd_adr_queue0_en};
1936 // read que read pointer
1937 wire [7:0] dram_Ch1_l2b1_rd_que_rd_ptr = {`MCU1_DRQ1_CTL.rdpctl_drq_clear_ent[7:0]};
1938
1939 // write que request
1940 wire dram_Ch1_l2b1_wr_req = `MCU1_L2IF1_CTL.l2t_mcu_wr_req;
1941 wire [2:0] dram_Ch1_l2b1_wr_addr = `MCU1_L2IF1_CTL.l2if_data_wr_addr;
1942
1943 wire [7:0] dram_ch1_l2b1_wr_q_valids = {`MCU1_DRQ1_CTL.drq_wr_queue_valid[7:0]};
1944 wire [3:0] dram_ch1_l2b1_drq_write_queue_cnt = {`MCU1_DRQ1_CTL.drq_write_queue_cnt[3:0]};
1945
1946 wire [40:0] dram_Ch1_l2b1_wr_q_0 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[0],
1947 `MCU1_DRQ1_CTL.drq_wrbuf_valids[0], //`DRAM_PATH1.writeqbank0vld0_arb,
1948 `MCU1_DRQ1_CTL.drq_wr_queue_ent0[11:9],
1949 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue0[3:0],
1950 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue0[2:0],
1951 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue0[14:0],
1952 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue0[10:0],
1953 3'b0};
1954
1955 wire [40:0] dram_Ch1_l2b1_wr_q_1 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[1],
1956 `MCU1_DRQ1_CTL.drq_wrbuf_valids[1], //`DRAM_PATH1.writeqbank0vld0_arb,
1957 `MCU1_DRQ1_CTL.drq_wr_queue_ent1[11:9],
1958 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue1[3:0],
1959 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue1[2:0],
1960 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue1[14:0],
1961 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue1[10:0],
1962 3'b0};
1963
1964 wire [40:0] dram_Ch1_l2b1_wr_q_2 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[2],
1965 `MCU1_DRQ1_CTL.drq_wrbuf_valids[2], //`DRAM_PATH1.writeqbank0vld0_arb,
1966 `MCU1_DRQ1_CTL.drq_wr_queue_ent2[11:9],
1967 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue2[3:0],
1968 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue2[2:0],
1969 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue2[14:0],
1970 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue2[10:0],
1971 3'b0};
1972
1973 wire [40:0] dram_Ch1_l2b1_wr_q_3 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[3],
1974 `MCU1_DRQ1_CTL.drq_wrbuf_valids[3], //`DRAM_PATH1.writeqbank0vld0_arb,
1975 `MCU1_DRQ1_CTL.drq_wr_queue_ent3[11:9],
1976 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue3[3:0],
1977 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue3[2:0],
1978 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue3[14:0],
1979 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue3[10:0],
1980 3'b0};
1981
1982 wire [40:0] dram_Ch1_l2b1_wr_q_4 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[4],
1983 `MCU1_DRQ1_CTL.drq_wrbuf_valids[4], //`DRAM_PATH1.writeqbank0vld0_arb,
1984 `MCU1_DRQ1_CTL.drq_wr_queue_ent4[11:9],
1985 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue4[3:0],
1986 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue4[2:0],
1987 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue4[14:0],
1988 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue4[10:0],
1989 3'b0};
1990
1991 wire [40:0] dram_Ch1_l2b1_wr_q_5 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[5],
1992 `MCU1_DRQ1_CTL.drq_wrbuf_valids[5], //`DRAM_PATH1.writeqbank0vld0_arb,
1993 `MCU1_DRQ1_CTL.drq_wr_queue_ent5[11:9],
1994 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue5[3:0],
1995 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue5[2:0],
1996 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue5[14:0],
1997 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue5[10:0],
1998 3'b0};
1999
2000 wire [40:0] dram_Ch1_l2b1_wr_q_6 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[6],
2001 `MCU1_DRQ1_CTL.drq_wrbuf_valids[6], //`DRAM_PATH1.writeqbank0vld0_arb,
2002 `MCU1_DRQ1_CTL.drq_wr_queue_ent6[11:9],
2003 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue6[3:0],
2004 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue6[2:0],
2005 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue6[14:0],
2006 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue6[10:0],
2007 3'b0};
2008
2009 wire [40:0] dram_Ch1_l2b1_wr_q_7 = {`MCU1_DRQ1_CTL.drq_wrbuf_valids[7],
2010 `MCU1_DRQ1_CTL.drq_wrbuf_valids[7], //`DRAM_PATH1.writeqbank0vld0_arb,
2011 `MCU1_DRQ1_CTL.drq_wr_queue_ent7[11:9],
2012 `MCU1_L2B1_ADR_Q.rank_wr_adr_queue7[3:0],
2013 `MCU1_L2B1_ADR_Q.bank_wr_adr_queue7[2:0],
2014 `MCU1_L2B1_ADR_Q.ras_wr_adr_queue7[14:0],
2015 `MCU1_L2B1_ADR_Q.cas_wr_adr_queue7[10:0],
2016 3'b0};
2017
2018 reg [40:0] dram_Ch1_l2b1_wr_q[7:0];
2019
2020 // to not set valid for the fifo monitor
2021 wire dram_Ch1_l2b1_pa_err = `MCU1_L2RDMX_DP.l2b1_wr_addr_err;
2022
2023 // write que collapsing fifo
2024 wire [14:0] dram_Ch1_l2b1_wr_colps_q_0 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent0[14:0]};
2025 wire [14:0] dram_Ch1_l2b1_wr_colps_q_1 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent1[14:0]};
2026 wire [14:0] dram_Ch1_l2b1_wr_colps_q_2 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent2[14:0]};
2027 wire [14:0] dram_Ch1_l2b1_wr_colps_q_3 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent3[14:0]};
2028 wire [14:0] dram_Ch1_l2b1_wr_colps_q_4 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent4[14:0]};
2029 wire [14:0] dram_Ch1_l2b1_wr_colps_q_5 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent5[14:0]};
2030 wire [14:0] dram_Ch1_l2b1_wr_colps_q_6 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent6[14:0]};
2031 wire [14:0] dram_Ch1_l2b1_wr_colps_q_7 = {`MCU1_DRQ1_CTL.drq_wr_queue_ent7[14:0]};
2032
2033 reg [14:0] dram_Ch1_l2b1_wr_colps_q[7:0];
2034
2035 // write que write pointer
2036 wire [7:0] dram_Ch1_l2b1_wr_que_wr_ptr = {`MCU1_DRQ1_CTL.drq_wr_adr_queue7_en,
2037 `MCU1_DRQ1_CTL.drq_wr_adr_queue6_en,
2038 `MCU1_DRQ1_CTL.drq_wr_adr_queue5_en,
2039 `MCU1_DRQ1_CTL.drq_wr_adr_queue4_en,
2040 `MCU1_DRQ1_CTL.drq_wr_adr_queue3_en,
2041 `MCU1_DRQ1_CTL.drq_wr_adr_queue2_en,
2042 `MCU1_DRQ1_CTL.drq_wr_adr_queue1_en,
2043 `MCU1_DRQ1_CTL.drq_wr_adr_queue0_en};
2044
2045 // write que arb read pointer
2046
2047 // write que data read pointer
2048 /*wire [7:0] dram_Ch1_l2b1_wr_que_rd_ptr = {`MCU1_DRQ1_CTL.drq_wr_entry7_rank,
2049 `MCU1_DRQ1_CTL.drq_wr_entry6_rank,
2050 `MCU1_DRQ1_CTL.drq_wr_entry5_rank,
2051 `MCU1_DRQ1_CTL.drq_wr_entry4_rank,
2052 `MCU1_DRQ1_CTL.drq_wr_entry3_rank,
2053 `MCU1_DRQ1_CTL.drq_wr_entry2_rank,
2054 `MCU1_DRQ1_CTL.drq_wr_entry1_rank,
2055 `MCU1_DRQ1_CTL.drq_wr_entry0_rank};*/
2056 wire [7:0] dram_Ch1_l2b1_wr_que_rd_ptr = `MCU1_DRQ1_CTL.drq_wrq_clear_ent;
2057
2058
2059// These signals are currently not used in cov obj
2060// enable for 8 deep collps rd fifo
2061 wire [7:0] dram_Ch1_l2b1_que_b0_index_en = {`MCU1_L2B1_ADR_Q.rd_adr_queue_sel[7:0]};
2062
2063
2064// These signals are currently not used in cov obj
2065// enable for 8 deep collps wr fifo
2066 wire [7:0] dram_Ch1_l2b1_que_b0_wr_index_en= {`MCU1_L2B1_ADR_Q.wr_adr_queue_sel[7:0]};
2067
2068// These signals are currently not used in cov obj
2069// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
2070 wire [7:0] dram_Ch1_l2b1_que_b0_rd_in_val = `MCU1_DRQ1_CTL.drq_rd_entry0_val[7:0];
2071
2072 wire dram_Ch1_que_b1_rd_picked = `MCU1_DRIF_CTL.drif1_rd_picked;
2073 wire dram_Ch1_que_b1_wr_picked = `MCU1_DRIF_CTL.drif1_wr_picked;
2074
2075
2076
2077// MAQ Not Required wire [7:0] dram_Ch1_que_cas_picked = `MCU1_DRIF_CTL.drif_cas_picked_d1[7:0];
2078// rd hits a wr in the wr Q
2079 wire dram_Ch1_que_rd_wr_hit = `MCU1_DRIF_CTL.drif_wr_entry_pend_in;
2080
2081// MAQ N2 doesn't support // Signals that will be used to detect oldest entry to the same bank.
2082// MAQ N2 doesn't support // in 2 channel mode this is the real indicator that the request is picked from this channel
2083// MAQ N2 doesn't support wire dram_Ch1_que_this_ch_picked = (~`DRAM_PATH1.que_channel_disabled) ?
2084// MAQ N2 doesn't support `DRAM_PATH1.que_ras_bank_picked_en && ~`DRAM_PATH1.que_channel_picked_internal:
2085// MAQ N2 doesn't support `DRAM_PATH1.que_ras_bank_picked_en && `DRAM_PATH1.que_channel_picked_internal;
2086// MAQ N2 doesn't support
2087
2088 wire [2:0] dram_Ch1_que_b0_index_picked = `MCU1_DRIF_CTL.drif_rdwr_index_picked[2:0];
2089 wire dram_Ch1_que_b0_cmd_picked = `MCU1_DRIF_CTL.drif_rdwr_cmd_picked;
2090 wire dram_ch1_drif_mclk_en = `MCU1_DRIF_CTL.drif_mclk_en;
2091
2092
2093//----------------------------------------------------------------------------------------
2094// Refresh to go and all CAS request to same CS are done, no new RAS issued.
2095//----------------------------------------------------------------------------------------
2096 wire [4:0] dram_Ch1_que_pos = `MCU1_DRIF_CTL.drif_mcu_state_enc;
2097 wire dram_Ch1_que_ref_go = `MCU1_DRIF_CTL.drif_ref_go;
2098 wire dram_Ch1_que_hw_selfrsh = `MCU1_DRIF_CTL.drif_hw_selfrsh;
2099 wire dram_Ch1_pt_blk_new_openbank_d1 = `MCU1_DRIF_CTL.drif_blk_new_openbank;
2100 wire dram_Ch1_que_cas_valid = ( (|(`MCU1_DRIF_CTL.drif_cas_picked)) &
2101 (`MCU1_DRIF_CTL.drif_phy_bank_picked[1:0] == `MCU1_DRIF_CTL.drif_refresh_rank[1:0])
2102 );
2103 wire [15:0] dram_Ch1_ras_picked = `MCU1_DRIF_CTL.drif_ras_picked[15:0];
2104 wire dram_Ch1_que_ras_picked = ( (|(`MCU1_DRIF_CTL.drif_ras_picked[15:0])) &
2105 ({`MCU1_DRIF_CTL.drif_rank_adr, `MCU1_DRIF_CTL.drif_stacked_dimm} == `MCU1_DRIF_CTL.drif_refresh_rank[1:0])
2106 );
2107 wire [1:0] dram_Ch1_b0_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2108 wire [1:0] dram_Ch1_b1_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2109 wire [1:0] dram_Ch1_b2_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2110 wire [1:0] dram_Ch1_b3_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2111 wire [1:0] dram_Ch1_b4_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2112 wire [1:0] dram_Ch1_b5_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2113 wire [1:0] dram_Ch1_b6_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2114 wire [1:0] dram_Ch1_b7_phy_bank_bits = `MCU1_DRIF_CTL.drif_phy_bank_picked[1:0];
2115 reg [1:0] dram_Ch1_b_phy_bank_bits[7:0];
2116
2117 wire [1:0] dram_Ch1_que_refresh_rank = `MCU1_DRIF_CTL.drif_refresh_rank[1:0];
2118
2119
2120// ---- Starvation counter causing the wr to have priority ---
2121 wire dram_Ch1_que_pick_wr_first = (`MCU1_DRIF_CTL.drif0_pick_wr_first |
2122 `MCU1_DRIF_CTL.drif1_pick_wr_first);
2123
2124// ------ Scrub Related -------
2125
2126 // picking the que_split_scrb_addr as _que_scrb_addr_picked_
2127 wire [31:0] dram_Ch1_que_scrb_addr_picked = `MCU1_DRIF_CTL.drif_scrub_addr;
2128 wire dram_Ch1_que_scrb_picked = `MCU1_DRIF_CTL.drif_scrub_picked;
2129 //somePersonwire dram_Ch1_que_scrb_rd_picked = `MCU1_DRIF_CTL.drif_scrub_picked; // MAQ
2130 wire dram_Ch1_que_scrb_rd_picked = `MCU1_DRIF_CTL.drif_scrub_read_pending;
2131 wire dram_Ch1_que_ras_bank_picked_en = |(`MCU1_DRIF_CTL.drif_ras_picked[15:0]);
2132 wire dram_Ch1_que_scrb_write_req = `MCU1_DRIF_CTL.drif_scrub_write_req;
2133
2134// req valid and scrb valid, the scrb should be cleared first
2135 wire [15:0] dram_Ch1_que_l2req_valid = `MCU1_DRIF_CTL.drif0_rd_bank_valids | `MCU1_DRIF_CTL.drif1_rd_bank_valids |
2136 `MCU1_DRIF_CTL.drif_wr_bank_valids;
2137 wire [15:0] dram_Ch1_scrb_indx_val = `MCU1_DRIF_CTL.drif_scrub_entry_val;
2138
2139// ------- DRAM REGISTERS --------
2140
2141 wire [8:0] dram_Ch1_chip_config_reg = {`MCU1_DRIF_CTL.drif_ras_addr_bits[3:0],
2142 `MCU1_DRIF_CTL.drif_cas_addr_bits[3:0],
2143 `MCU1_DRIF_CTL.drif_stacked_dimm};
2144
2145 wire [2:0] dram_Ch1_mode_reg = `MCU1_DRIF_CTL.mode_reg[6:4];
2146 wire [3:0] dram_Ch1_rrd_reg = `MCU1_DRIF_CTL.rrd_reg;
2147 wire [4:0] dram_Ch1_rc_reg = `MCU1_DRIF_CTL.rc_reg;
2148 wire [3:0] dram_Ch1_rcd_reg = `MCU1_DRIF_CTL.rcd_reg;
2149 wire [3:0] dram_Ch1_wtr_dly_reg = `MCU1_DRIF_CTL.wtr_dly_reg;
2150 wire [3:0] dram_Ch1_rtw_dly_reg = `MCU1_DRIF_CTL.rtw_dly_reg;
2151 wire [3:0] dram_Ch1_rtp_reg = `MCU1_DRIF_CTL.rtp_reg;
2152 wire [3:0] dram_Ch1_ras_reg = `MCU1_DRIF_CTL.ras_reg;
2153 wire [3:0] dram_Ch1_rp_reg = `MCU1_DRIF_CTL.rp_reg;
2154 wire [3:0] dram_Ch1_wr_reg = `MCU1_DRIF_CTL.wr_reg;
2155 wire [1:0] dram_Ch1_mrd_reg = `MCU1_DRIF_CTL.mrd_reg;
2156 wire [1:0] dram_Ch1_iwtr_reg = `MCU1_DRIF_CTL.iwtr_reg;
2157 wire [14:0] dram_Ch1_ext_mode_reg2 = `MCU1_DRIF_CTL.ext_mode_reg2;
2158 wire [14:0] dram_Ch1_ext_mode_reg1 = `MCU1_DRIF_CTL.ext_mode_reg1;
2159 wire [14:0] dram_Ch1_ext_mode_reg3 = `MCU1_DRIF_CTL.ext_mode_reg3;
2160 wire dram_Ch1_que_eight_bank_mode = `MCU1_DRIF_CTL.drif_eight_bank_mode;
2161 wire dram_Ch1_que_rank1_present = `MCU1_DRIF_CTL.drif_dimms_present[0];
2162 wire dram_Ch1_que_channel_disabled = `MCU1_DRIF_CTL.drif_branch_disabled;
2163 wire dram_Ch1_que_addr_bank_low_sel = `MCU1_DRIF_CTL.drif_addr_bank_low_sel;
2164 wire dram_Ch1_que_init = `MCU1_DRIF_CTL.drif_init;
2165// wire [2:0] dram_Ch1_que_data_del_cnt = `MCU1_DRIF_CTL.drif_data_del_cnt[2:0];
2166// wire dram_Ch1_dram_io_pad_clk_inv = `MCU1_DRIF_CTL.mcu_ddp_pad_clk_inv;
2167// wire [1:0] dram_Ch1_dram_io_ptr_clk_inv = `MCU1_DRIF_CTL.mcu_ddp_ptr_clk_inv;
2168 wire dram_Ch1_que_wr_mode_reg_done = `MCU1_DRIF_CTL.drif_wr_mode_reg_done;
2169 wire dram_Ch1_que_init_status_reg = `MCU1_DRIF_CTL.drif_init_status_reg;
2170 wire [3:0] dram_Ch1_que_dimms_present = `MCU1_DRIF_CTL.drif_dimms_present;
2171 wire dram_Ch1_dram_fail_over_mode = `MCU1_DRIF_CTL.drif_fail_over_mode;
2172 wire [34:0] dram_Ch1_dram_fail_over_mask = `MCU1_DRIF_CTL.drif_fail_over_mask[34:0];
2173 wire dram_Ch1_que_dbg_trig_en = `MCU1_DRIF_CTL.rdpctl_dbg_trig_enable;
2174 wire [22:0] dram_Ch1_que_err_sts_reg = `MCU1_DRIF_CTL.rdpctl_err_sts_reg;
2175 wire [35:0] dram_Ch1_que_err_addr_reg = `MCU1_DRIF_CTL.rdpctl_err_addr_reg;
2176 wire dram_Ch1_err_inj_reg = `MCU1_DRIF_CTL.drif_err_inj_reg;
2177 wire dram_Ch1_sshot_err_reg = `MCU1_DRIF_CTL.drif_sshot_err_reg;
2178// wire [1:0] dram_Ch1_que_err_cnt = `MCU1_DRIF_CTL.rdpctl_err_cnt[17:16];
2179 wire [35:0] dram_Ch1_que_err_loc = `MCU1_DRIF_CTL.rdpctl_err_loc;
2180
2181 // NACK - for non existant register read
2182 wire dram_Ch1_que_l2if_ack_vld = `MCU1_DRIF_CTL.drif_rdata_ack_vld;
2183 wire dram_Ch1_que_l2if_nack_vld = `MCU1_DRIF_CTL.drif_rdata_nack_vld;
2184
2185 wire dram_Ch1_que_init_dram_done = `MCU1_DRIF_CTL.drif_init_mcu_done;
2186
2187// ----- DRAM L2IF INTERFACE -----
2188
2189 wire [127:0] dram_Ch1_dram_sctag_data = `MCU1.mcu_l2b_data_r3;
2190 // Error signal for update of error status, error location and error address register.
2191 //wire dram_Ch1_l2if_scrb_val_d2 = `DRAM_L2IF1.l2if_scrb_val_d3;
2192
2193 // l2if_scrb_data_val is now qualifying scrb in the rtl
2194 wire dram_Ch1_l2if_scrb_val_d2 = `MCU1_RDPCTL_CTL.rdpctl_scrub_data_valid;
2195
2196 wire [6:0] dram_Ch1_err_sts_reg = `MCU1_RDPCTL_CTL.rdpctl_err_sts_reg[25:19];
2197
2198 wire dram_Ch1_l2if_err_sts_reg_en6 = `MCU1_RDPCTL_CTL.rdpctl_meu_error_en;
2199 wire dram_Ch1_l2if_err_sts_reg_en5 = `MCU1_RDPCTL_CTL.rdpctl_mec_error_en;
2200 wire dram_Ch1_l2if_err_sts_reg_en4 = `MCU1_RDPCTL_CTL.rdpctl_dac_error_en;
2201 wire dram_Ch1_l2if_err_sts_reg_en3 = `MCU1_RDPCTL_CTL.rdpctl_dau_error_en;
2202 wire dram_Ch1_l2if_err_sts_reg_en2 = `MCU1_RDPCTL_CTL.rdpctl_dsc_error_en;
2203 wire dram_Ch1_l2if_err_sts_reg_en1 = `MCU1_RDPCTL_CTL.rdpctl_dsu_error_en;
2204 wire dram_Ch1_l2if_err_sts_reg_en0 = `MCU1_RDPCTL_CTL.rdpctl_err_sts_reg_en;
2205 wire dram_Ch1_l2if_err_sts_reg_en = `MCU1_RDPCTL_CTL.rdpctl_dbu_error_en;
2206 wire dram_Ch1_l2if_err_addr_reg_en = `MCU1_RDPCTL_CTL.rdpctl_err_addr_reg_en;
2207 wire dram_Ch1_l2if_secc_loc_en = `MCU1_RDPCTL_CTL.rdpctl_secc_loc_en;
2208
2209
2210 wire dram_Ch1_l2b0_sctag_dram_rd_req = `MCU1_L2IF0_CTL.l2t_mcu_rd_req;
2211 wire [2:0] dram_Ch1_l2b0_sctag_dram_rd_req_id = `MCU1_L2IF0_CTL.l2t_mcu_rd_req_id;
2212// wire [39:6] dram_Ch1_l2b0_sctag_dram_addr = {`MCU1_ADDRDP_DP.l2t0_mcu_addr_39to9, `MCU1_ADDRDP_DP.l2t0_mcu_addr_6to4};
2213 wire [39:5] dram_Ch1_l2b0_sctag_dram_addr = `MCU1_L2IF0_CTL.l2t_mcu_addr;
2214 wire dram_Ch1_l2b0_sctag_dram_rd_dummy_req = `MCU1_L2IF0_CTL.l2t_mcu_rd_dummy_req;
2215 wire dram_Ch1_l2b0_dram_sctag_rd_ack = `MCU1_L2IF0_CTL.mcu_l2t_rd_ack;
2216 wire dram_Ch1_l2b0_sctag_dram_wr_req = `MCU1_L2IF0_CTL.l2t_mcu_wr_req;
2217 wire dram_Ch1_l2b0_sctag_dram_data_vld = `MCU1_L2IF0_CTL.l2b_mcu_data_vld;
2218 wire [63:0] dram_Ch1_l2b0_sctag_dram_wr_data = `MCU1_L2RDMX_DP.l2b0_mcu_wr_data_r5;
2219 wire dram_Ch1_l2b0_dram_sctag_wr_ack = `MCU1_L2IF0_CTL.mcu_l2t_wr_ack;
2220 wire dram_Ch1_l2b0_dram_sctag_data_vld = `MCU1_RDATA_CTL.mcu_l2t0_data_vld_r0;
2221 wire [2:0] dram_Ch1_l2b0_dram_sctag_rd_req_id = `MCU1_RDATA_CTL.mcu_l2t0_rd_req_id_r0;
2222
2223// MAQ N2 doesn't support wire [3:0] dram_Ch1_l2if_b0_rd_val = `DRAM_L2IF1.l2if_b0_rd_val;
2224// MAQ N2 doesn't support wire [3:0] dram_Ch1_l2if_b1_rd_val = `DRAM_L2IF1.l2if_b1_rd_val;
2225 wire [3:0] dram_Ch1_l2b0_l2if_b0_wr_val = {`MCU1_L2IF0_CTL.l2if_wr_entry3,
2226 `MCU1_L2IF0_CTL.l2if_wr_entry2,
2227 `MCU1_L2IF0_CTL.l2if_wr_entry1,
2228 `MCU1_L2IF0_CTL.l2if_wr_entry0};
2229
2230 wire [3:0] dram_Ch1_l2b0_l2if_b1_wr_val = {`MCU1_L2IF0_CTL.l2if_wr_entry7,
2231 `MCU1_L2IF0_CTL.l2if_wr_entry6,
2232 `MCU1_L2IF0_CTL.l2if_wr_entry5,
2233 `MCU1_L2IF0_CTL.l2if_wr_entry4};
2234
2235// MAQ wire [5:0] dram_Ch1_l2b0_l2if_wr_b0_data_addr = `MCU1_L2IF0_CTL.l2if_wdq_wadr;
2236
2237 // Signals on L2 Interface that indicates Error
2238 wire dram_Ch1_l2b0_dram_sctag_secc_err = `MCU1_RDATA_CTL.mcu_l2t0_secc_err_r3;
2239 wire dram_Ch1_l2b0_dram_sctag_pa_err = `MCU1_L2RDMX_DP.l2b0_rd_addr_err | `MCU1_L2RDMX_DP.l2b0_wr_addr_err;
2240 wire dram_Ch1_l2b0_dram_sctag_mecc_err = `MCU1_RDATA_CTL.mcu_l2t0_mecc_err_r3;
2241 wire dram_Ch1_l2b0_dram_sctag_scb_secc_err = `MCU1_RDATA_CTL.mcu_l2t0_scb_secc_err;
2242 wire dram_Ch1_l2b0_dram_sctag_scb_mecc_err = `MCU1_RDATA_CTL.mcu_l2t0_scb_mecc_err;
2243
2244// qualified with vld since they can be on due to residual ( previous error )
2245/* wire dram_Ch1_l2b0_l2if_secc_err = `MCU1_RDATA_CTL.mcu_l2t0_secc_err_r3 &&
2246 (`MCU1_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
2247 `MCU1_RDPCTL_CTL.rdpctl_scrub_data_valid);
2248
2249 wire dram_Ch1_l2b0_l2if_mecc_err_partial = `MCU1_RDATA_CTL.mcu_l2t0_mecc_err_r3 &&
2250 (`MCU1_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
2251 `MCU1_RDPCTL_CTL.rdpctl_scrub_data_valid);
2252*/
2253 wire dram_Ch1_l2b0_l2if_secc_err = `MCU1_RDATA_CTL.mcu_l2t0_scb_secc_err_in ||
2254 `MCU1_RDATA_CTL.mcu_l2t0_secc_err_r1;
2255 wire dram_Ch1_l2b0_l2if_mecc_err_partial = `MCU1_RDATA_CTL.mcu_l2t0_scb_mecc_err_in ||
2256 `MCU1_RDATA_CTL.mcu_l2t0_mecc_err_r1;
2257 wire dram_Ch1_l2b0_l2if_pa_err = (`MCU1_L2RDMX_DP.l2b0_rd_addr_err || `MCU1_L2RDMX_DP.l2b0_wr_addr_err) &&
2258 `MCU1_RDATA_CTL.mcu_l2t0_data_vld_r0;
2259
2260 wire [1:0] dram_Ch1_l2b0_cpu_wr_en = `MCU1_L2IF0_CTL.l2if_wdq_we;
2261 wire [4:0] dram_Ch1_l2b0_cpu_wr_addr = `MCU1_L2IF0_CTL.l2if_wdq_wadr;
2262 wire dram_Ch1_l2b0_wdq_rd_en = `MCU1_DRIF_CTL.drif0_wdq_rd;
2263 wire [4:0] dram_Ch1_l2b0_wdq_radr = `MCU1_DRIF_CTL.drif0_wdq_radr;
2264
2265 wire dram_Ch1_l2b0_clspine_dram_txrd_sync = `MCU1_RDATA_CTL.rdata_cmp_ddr_sync_en;
2266 wire dram_Ch1_l2b0_clspine_dram_txwr_sync = `MCU1_RDATA_CTL.rdata_cmp_ddr_sync_en;
2267
2268// l2if wr entry valid ( for the actual data valid creation)
2269 wire [7:0] dram_Ch1_l2b0_l2if_wr_entry = {
2270 `MCU1_L2IF0_CTL.l2if_wr_entry7,
2271 `MCU1_L2IF0_CTL.l2if_wr_entry6,
2272 `MCU1_L2IF0_CTL.l2if_wr_entry5,
2273 `MCU1_L2IF0_CTL.l2if_wr_entry4,
2274 `MCU1_L2IF0_CTL.l2if_wr_entry3,
2275 `MCU1_L2IF0_CTL.l2if_wr_entry2,
2276 `MCU1_L2IF0_CTL.l2if_wr_entry1,
2277 `MCU1_L2IF0_CTL.l2if_wr_entry0
2278 };
2279
2280
2281
2282/* wire [8:0] dram_Ch1_l2b0_rd_adr_info_hi = {
2283 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2284 `MCU1_L2B0_ADRGEN_DP.addr_err,
2285 `MCU1_DRIF_CTL.drif_stack_adr,
2286 `MCU1_L2B0_ADRGEN_DP.rank_adr,
2287 `MCU1_L2B0_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2288 `MCU1_L2B0_ADRGEN_DP.bank_adr[1:0],
2289 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2290 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2291 };
2292
2293 wire [8:0] dram_Ch1_l2b0_wr_adr_info_hi = {
2294 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2295 `MCU1_L2B0_ADRGEN_DP.addr_err,
2296 `MCU1_DRIF_CTL.drif_stack_adr,
2297 `MCU1_L2B0_ADRGEN_DP.rank_adr,
2298 `MCU1_L2B0_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2299 `MCU1_L2B0_ADRGEN_DP.bank_adr[1:0],
2300 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2301 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2302 };
2303
2304 wire [8:0] dram_Ch1_l2b0_rd_adr_info_lo = {
2305 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2306 `MCU1_L2B0_ADRGEN_DP.addr_err,
2307 `MCU1_DRIF_CTL.drif_stack_adr,
2308 `MCU1_L2B0_ADRGEN_DP.rank_adr,
2309 `MCU1_L2B0_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2310 `MCU1_L2B0_ADRGEN_DP.bank_adr[1:0],
2311 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2312 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2313 };
2314
2315 wire [8:0] dram_Ch1_l2b0_wr_adr_info_lo = {
2316 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2317 `MCU1_L2B0_ADRGEN_DP.addr_err,
2318 `MCU1_DRIF_CTL.drif_stack_adr,
2319 `MCU1_L2B0_ADRGEN_DP.rank_adr,
2320 `MCU1_L2B0_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2321 `MCU1_L2B0_ADRGEN_DP.bank_adr[1:0],
2322 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2323 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2324 };*/
2325
2326
2327 wire dram_Ch1_l2b1_sctag_dram_rd_req = `MCU1_L2IF1_CTL.l2t_mcu_rd_req;
2328 wire [2:0] dram_Ch1_l2b1_sctag_dram_rd_req_id = `MCU1_L2IF1_CTL.l2t_mcu_rd_req_id;
2329// wire [39:6] dram_Ch1_l2b1_sctag_dram_addr = {`MCU1_ADDRDP_DP.l2t1_mcu_addr_39to9, `MCU1_ADDRDP_DP.l2t1_mcu_addr_6to4};
2330 wire [39:5] dram_Ch1_l2b1_sctag_dram_addr = `MCU1_L2IF1_CTL.l2t_mcu_addr;
2331 wire dram_Ch1_l2b1_sctag_dram_rd_dummy_req = `MCU1_L2IF1_CTL.l2t_mcu_rd_dummy_req;
2332 wire dram_Ch1_l2b1_dram_sctag_rd_ack = `MCU1_L2IF1_CTL.mcu_l2t_rd_ack;
2333 wire dram_Ch1_l2b1_sctag_dram_wr_req = `MCU1_L2IF1_CTL.l2t_mcu_wr_req;
2334 wire dram_Ch1_l2b1_sctag_dram_data_vld = `MCU1_L2IF1_CTL.l2b_mcu_data_vld;
2335 wire [63:0] dram_Ch1_l2b1_sctag_dram_wr_data = `MCU1_L2RDMX_DP.l2b1_mcu_wr_data_r5;
2336 wire dram_Ch1_l2b1_dram_sctag_wr_ack = `MCU1_L2IF1_CTL.mcu_l2t_wr_ack;
2337 wire dram_Ch1_l2b1_dram_sctag_data_vld = `MCU1_RDATA_CTL.mcu_l2t1_data_vld_r0;
2338 wire [2:0] dram_Ch1_l2b1_dram_sctag_rd_req_id = `MCU1_RDATA_CTL.mcu_l2t1_rd_req_id_r0;
2339
2340// MAQ N2 doesn't support wire [3:0] dram_Ch1_l2if_b0_rd_val = `DRAM_L2IF1.l2if_b0_rd_val;
2341// MAQ N2 doesn't support wire [3:0] dram_Ch1_l2if_b1_rd_val = `DRAM_L2IF1.l2if_b1_rd_val;
2342 wire [3:0] dram_Ch1_l2b1_l2if_b0_wr_val = {`MCU1_L2IF1_CTL.l2if_wr_entry3,
2343 `MCU1_L2IF1_CTL.l2if_wr_entry2,
2344 `MCU1_L2IF1_CTL.l2if_wr_entry1,
2345 `MCU1_L2IF1_CTL.l2if_wr_entry0};
2346
2347 wire [3:0] dram_Ch1_l2b1_l2if_b1_wr_val = {`MCU1_L2IF1_CTL.l2if_wr_entry7,
2348 `MCU1_L2IF1_CTL.l2if_wr_entry6,
2349 `MCU1_L2IF1_CTL.l2if_wr_entry5,
2350 `MCU1_L2IF1_CTL.l2if_wr_entry4};
2351
2352// MAQ wire [5:0] dram_Ch1_l2b1_l2if_wr_b0_data_addr = `MCU1_L2IF1_CTL.l2if_wdq_wadr;
2353
2354 // Signals on L2 Interface that indicates Error
2355 wire dram_Ch1_l2b1_dram_sctag_secc_err = `MCU1_RDATA_CTL.mcu_l2t1_secc_err_r3;
2356 wire dram_Ch1_l2b1_dram_sctag_pa_err = `MCU1_L2RDMX_DP.l2b1_rd_addr_err | `MCU1_L2RDMX_DP.l2b1_wr_addr_err;
2357 wire dram_Ch1_l2b1_dram_sctag_mecc_err = `MCU1_RDATA_CTL.mcu_l2t1_mecc_err_r3;
2358 wire dram_Ch1_l2b1_dram_sctag_scb_secc_err = `MCU1_RDATA_CTL.mcu_l2t1_scb_secc_err;
2359 wire dram_Ch1_l2b1_dram_sctag_scb_mecc_err = `MCU1_RDATA_CTL.mcu_l2t1_scb_mecc_err;
2360
2361// qualified with vld since they can be on due to residual ( previous error )
2362/* wire dram_Ch1_l2b1_l2if_secc_err = `MCU1_RDATA_CTL.mcu_l2t1_secc_err_r3 &&
2363 (`MCU1_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
2364 `MCU1_RDPCTL_CTL.rdpctl_scrub_data_valid);
2365
2366 wire dram_Ch1_l2b1_l2if_mecc_err_partial = `MCU1_RDATA_CTL.mcu_l2t1_mecc_err_r3 &&
2367 (`MCU1_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
2368 `MCU1_RDPCTL_CTL.rdpctl_scrub_data_valid);
2369*/
2370 wire dram_Ch1_l2b1_l2if_secc_err = `MCU1_RDATA_CTL.mcu_l2t1_scb_secc_err_in ||
2371 `MCU1_RDATA_CTL.mcu_l2t1_secc_err_r1;
2372 wire dram_Ch1_l2b1_l2if_mecc_err_partial = `MCU1_RDATA_CTL.mcu_l2t1_scb_mecc_err_in ||
2373 `MCU1_RDATA_CTL.mcu_l2t1_mecc_err_r1;
2374 wire dram_Ch1_l2b1_l2if_pa_err = (`MCU1_L2RDMX_DP.l2b1_rd_addr_err || `MCU1_L2RDMX_DP.l2b1_wr_addr_err) &&
2375 `MCU1_RDATA_CTL.mcu_l2t1_data_vld_r0;
2376
2377 wire [1:0] dram_Ch1_l2b1_cpu_wr_en = `MCU1_L2IF1_CTL.l2if_wdq_we;
2378 wire [4:0] dram_Ch1_l2b1_cpu_wr_addr = `MCU1_L2IF1_CTL.l2if_wdq_wadr;
2379 wire dram_Ch1_l2b1_wdq_rd_en = `MCU1_DRIF_CTL.drif1_wdq_rd;
2380 wire [4:0] dram_Ch1_l2b1_wdq_radr = `MCU1_DRIF_CTL.drif1_wdq_radr;
2381
2382 wire dram_Ch1_l2b1_clspine_dram_txrd_sync = `MCU1_RDATA_CTL.rdata_cmp_ddr_sync_en;
2383 wire dram_Ch1_l2b1_clspine_dram_txwr_sync = `MCU1_RDATA_CTL.rdata_cmp_ddr_sync_en;
2384
2385// l2if wr entry valid ( for the actual data valid creation)
2386 wire [7:0] dram_Ch1_l2b1_l2if_wr_entry = {
2387 `MCU1_L2IF1_CTL.l2if_wr_entry7,
2388 `MCU1_L2IF1_CTL.l2if_wr_entry6,
2389 `MCU1_L2IF1_CTL.l2if_wr_entry5,
2390 `MCU1_L2IF1_CTL.l2if_wr_entry4,
2391 `MCU1_L2IF1_CTL.l2if_wr_entry3,
2392 `MCU1_L2IF1_CTL.l2if_wr_entry2,
2393 `MCU1_L2IF1_CTL.l2if_wr_entry1,
2394 `MCU1_L2IF1_CTL.l2if_wr_entry0
2395 };
2396
2397
2398
2399/* wire [8:0] dram_Ch1_l2b1_rd_adr_info_hi = {
2400 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2401 `MCU1_L2B1_ADRGEN_DP.addr_err,
2402 `MCU1_DRIF_CTL.drif_stack_adr,
2403 `MCU1_L2B1_ADRGEN_DP.rank_adr,
2404 `MCU1_L2B1_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2405 `MCU1_L2B1_ADRGEN_DP.bank_adr[1:0],
2406 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2407 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2408 };
2409
2410 wire [8:0] dram_Ch1_l2b1_wr_adr_info_hi = {
2411 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2412 `MCU1_L2B1_ADRGEN_DP.addr_err,
2413 `MCU1_DRIF_CTL.drif_stack_adr,
2414 `MCU1_L2B1_ADRGEN_DP.rank_adr,
2415 `MCU1_L2B1_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2416 `MCU1_L2B1_ADRGEN_DP.bank_adr[1:0],
2417 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2418 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2419 };
2420
2421 wire [8:0] dram_Ch1_l2b1_rd_adr_info_lo = {
2422 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2423 `MCU1_L2B1_ADRGEN_DP.addr_err,
2424 `MCU1_DRIF_CTL.drif_stack_adr,
2425 `MCU1_L2B1_ADRGEN_DP.rank_adr,
2426 `MCU1_L2B1_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2427 `MCU1_L2B1_ADRGEN_DP.bank_adr[1:0],
2428 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2429 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2430 };
2431
2432 wire [8:0] dram_Ch1_l2b1_wr_adr_info_lo = {
2433 `MCU1_DRIF_CTL.drif_addr_bank_low_sel,
2434 `MCU1_L2B1_ADRGEN_DP.addr_err,
2435 `MCU1_DRIF_CTL.drif_stack_adr,
2436 `MCU1_L2B1_ADRGEN_DP.rank_adr,
2437 `MCU1_L2B1_ADRGEN_DP.bank_adr[2] && `MCU1_DRIF_CTL.drif_eight_bank_mode,
2438 `MCU1_L2B1_ADRGEN_DP.bank_adr[1:0],
2439 `MCU1_DRIF_CTL.drif_eight_bank_mode,
2440 1'b0 // `DRAM_L2IF1.dram_rd_addr_gen_hi.two_channel_mode
2441 };*/
2442
2443
2444
2445// ---- Performance counters ----
2446
2447 wire [7:0] dram_Ch1_perf_cntl = `MCU1_DRIF_CTL.drif_perf_cntl_reg;
2448 wire dram_Ch1_cnt0_sticky_bit = `MCU1_DRIF_CTL.drif_perf_cnt0_reg[31];
2449 wire dram_Ch1_cnt1_sticky_bit = `MCU1_DRIF_CTL.drif_perf_cnt1_reg[31];
2450
2451 // read que request
2452 wire dram_Ch2_l2b0_rd_req = `MCU2_L2IF0_CTL.l2t_mcu_rd_req;
2453 wire [2:0] dram_Ch2_l2b0_rd_id = `MCU2_L2IF0_CTL.l2t_mcu_rd_req_id[2:0];
2454 wire dram_Ch2_l2b0_errq_vld = (!`MCU2_DRIF_CTL.drif_err_fifo_empty) & (`MCU2_DRIF_CTL.rdpctl_err_fifo_data[0] == 0) ;
2455 wire [2:0] dram_Ch2_l2b0_errq_id = `MCU2_DRIF_CTL.rdpctl_err_fifo_data[4:2];
2456 // read que
2457 wire dram_ch2_l2b0_rd_q_vld_0 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2458 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2459 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2460 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2461 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2462 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2463 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) |
2464 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0])) };
2465
2466 wire dram_ch2_l2b0_rd_q_vld_1 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2467 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2468 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2469 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2470 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2471 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2472 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) |
2473 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1])) };
2474
2475 wire dram_ch2_l2b0_rd_q_vld_2 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2476 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2477 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2478 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2479 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2480 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2481 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) |
2482 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2])) };
2483
2484 wire dram_ch2_l2b0_rd_q_vld_3 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2485 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2486 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2487 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2488 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2489 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2490 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) |
2491 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3])) };
2492
2493 wire dram_ch2_l2b0_rd_q_vld_4 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2494 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2495 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2496 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2497 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2498 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2499 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) |
2500 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4])) };
2501
2502 wire dram_ch2_l2b0_rd_q_vld_5 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2503 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2504 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2505 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2506 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2507 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2508 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) |
2509 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5])) };
2510
2511 wire dram_ch2_l2b0_rd_q_vld_6 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2512 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2513 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2514 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2515 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2516 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2517 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) |
2518 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6])) };
2519
2520 wire dram_ch2_l2b0_rd_q_vld_7 = { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2521 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2522 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2523 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2524 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2525 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2526 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) |
2527 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7])) };
2528
2529 wire [7:0] dram_ch2_l2b0_rd_q_valids = {dram_ch2_l2b0_rd_q_vld_7, dram_ch2_l2b0_rd_q_vld_6, dram_ch2_l2b0_rd_q_vld_5, dram_ch2_l2b0_rd_q_vld_4,
2530 dram_ch2_l2b0_rd_q_vld_3, dram_ch2_l2b0_rd_q_vld_2, dram_ch2_l2b0_rd_q_vld_1, dram_ch2_l2b0_rd_q_vld_0};
2531
2532// Read request Q PA-Error
2533 wire dram_ch2_l2b0_rd_q_addr_err_0 =
2534 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2535 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2536 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2537 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2538 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2539 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2540 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2541 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2542
2543 wire dram_ch2_l2b0_rd_q_addr_err_1 =
2544 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2545 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2546 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2547 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2548 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2549 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2550 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2551 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) };
2552
2553 wire dram_ch2_l2b0_rd_q_addr_err_2 =
2554 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2555 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2556 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2557 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2558 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2559 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2560 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2561 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2562
2563 wire dram_ch2_l2b0_rd_q_addr_err_3 =
2564 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2565 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2566 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2567 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2568 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2569 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2570 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2571 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2572
2573 wire dram_ch2_l2b0_rd_q_addr_err_4 =
2574 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2575 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2576 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2577 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2578 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2579 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2580 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2581 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2582
2583 wire dram_ch2_l2b0_rd_q_addr_err_5 =
2584 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2585 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2586 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2587 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2588 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2589 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2590 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2591 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2592
2593 wire dram_ch2_l2b0_rd_q_addr_err_6 =
2594 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2595 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2596 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2597 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2598 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2599 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2600 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2601 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2602
2603 wire dram_ch2_l2b0_rd_q_addr_err_7 =
2604 { ((`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent0[7]) |
2605 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent1[7]) |
2606 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent2[7]) |
2607 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent3[7]) |
2608 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent4[7]) |
2609 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent5[7]) |
2610 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent6[7]) |
2611 ((`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU2_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ0_CTL.drq_rd_queue_ent7[7]) };
2612
2613 wire [7:0] dram_ch2_l2b0_rd_q_addr_err = {dram_ch2_l2b0_rd_q_addr_err_7, dram_ch2_l2b0_rd_q_addr_err_6, dram_ch2_l2b0_rd_q_addr_err_5, dram_ch2_l2b0_rd_q_addr_err_4,
2614 dram_ch2_l2b0_rd_q_addr_err_3, dram_ch2_l2b0_rd_q_addr_err_2, dram_ch2_l2b0_rd_q_addr_err_1, dram_ch2_l2b0_rd_q_addr_err_0};
2615
2616 wire [7:0] dram_ch2_l2b0_drq_rd_queue_valid = {`MCU2_DRQ0_CTL.drq_rd_queue_valid[7:0]};
2617 wire [3:0] dram_ch2_l2b0_drq_read_queue_cnt = {`MCU2_DRQ0_CTL.drq_read_queue_cnt[3:0]};
2618
2619// Read request Q PA-Error
2620
2621 wire [39:0] dram_Ch2_l2b0_rd_q_0 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[0],
2622 `MCU2_L2B0_ADR_Q.rd_req_id_queue0[2:0],
2623 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue0[3:0],
2624 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue0[2:0],
2625 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue0[14:0],
2626 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue0[10:0],
2627 3'b0 };
2628
2629 wire [39:0] dram_Ch2_l2b0_rd_q_1 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[1],
2630 `MCU2_L2B0_ADR_Q.rd_req_id_queue1[2:0],
2631 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue1[3:0],
2632 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue1[2:0],
2633 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue1[14:0],
2634 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue1[10:0],
2635 3'b0 };
2636
2637 wire [39:0] dram_Ch2_l2b0_rd_q_2 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[2],
2638 `MCU2_L2B0_ADR_Q.rd_req_id_queue2[2:0],
2639 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue2[3:0],
2640 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue2[2:0],
2641 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue2[14:0],
2642 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue2[10:0],
2643 3'b0 };
2644
2645 wire [39:0] dram_Ch2_l2b0_rd_q_3 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[3],
2646 `MCU2_L2B0_ADR_Q.rd_req_id_queue3[2:0],
2647 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue3[3:0],
2648 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue3[2:0],
2649 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue3[14:0],
2650 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue3[10:0],
2651 3'b0 };
2652
2653 wire [39:0] dram_Ch2_l2b0_rd_q_4 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[4],
2654 `MCU2_L2B0_ADR_Q.rd_req_id_queue4[2:0],
2655 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue4[3:0],
2656 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue4[2:0],
2657 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue4[14:0],
2658 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue4[10:0],
2659 3'b0 };
2660
2661 wire [39:0] dram_Ch2_l2b0_rd_q_5 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[5],
2662 `MCU2_L2B0_ADR_Q.rd_req_id_queue5[2:0],
2663 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue5[3:0],
2664 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue5[2:0],
2665 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue5[14:0],
2666 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue5[10:0],
2667 3'b0 };
2668
2669 wire [39:0] dram_Ch2_l2b0_rd_q_6 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[6],
2670 `MCU2_L2B0_ADR_Q.rd_req_id_queue6[2:0],
2671 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue6[3:0],
2672 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue6[2:0],
2673 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue6[14:0],
2674 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue6[10:0],
2675 3'b0 };
2676
2677 wire [39:0] dram_Ch2_l2b0_rd_q_7 = {`MCU2_DRQ0_CTL.drq_rdbuf_valids[7],
2678 `MCU2_L2B0_ADR_Q.rd_req_id_queue7[2:0],
2679 `MCU2_L2B0_ADR_Q.rank_rd_adr_queue7[3:0],
2680 `MCU2_L2B0_ADR_Q.bank_rd_adr_queue7[2:0],
2681 `MCU2_L2B0_ADR_Q.ras_rd_adr_queue7[14:0],
2682 `MCU2_L2B0_ADR_Q.cas_rd_adr_queue7[10:0],
2683 3'b0 };
2684
2685
2686 reg [39:0] dram_Ch2_l2b0_rd_q[7:0];
2687 // read que collapsing fifo
2688 wire [11:0] dram_Ch2_l2b0_rd_colps_q_0 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent0[11:0]};
2689 wire [11:0] dram_Ch2_l2b0_rd_colps_q_1 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent1[11:0]};
2690 wire [11:0] dram_Ch2_l2b0_rd_colps_q_2 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent2[11:0]};
2691 wire [11:0] dram_Ch2_l2b0_rd_colps_q_3 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent3[11:0]};
2692 wire [11:0] dram_Ch2_l2b0_rd_colps_q_4 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent4[11:0]};
2693 wire [11:0] dram_Ch2_l2b0_rd_colps_q_5 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent5[11:0]};
2694 wire [11:0] dram_Ch2_l2b0_rd_colps_q_6 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent6[11:0]};
2695 wire [11:0] dram_Ch2_l2b0_rd_colps_q_7 = {`MCU2_DRQ0_CTL.drq_rd_queue_ent7[11:0]};
2696
2697 reg [11:0] dram_Ch2_l2b0_rd_colps_q[7:0];
2698
2699 // read que write pointer
2700 wire [7:0] dram_Ch2_l2b0_rd_que_wr_ptr = {`MCU2_DRQ0_CTL.drq_rd_adr_queue7_en,
2701 `MCU2_DRQ0_CTL.drq_rd_adr_queue6_en,
2702 `MCU2_DRQ0_CTL.drq_rd_adr_queue5_en,
2703 `MCU2_DRQ0_CTL.drq_rd_adr_queue4_en,
2704 `MCU2_DRQ0_CTL.drq_rd_adr_queue3_en,
2705 `MCU2_DRQ0_CTL.drq_rd_adr_queue2_en,
2706 `MCU2_DRQ0_CTL.drq_rd_adr_queue1_en,
2707 `MCU2_DRQ0_CTL.drq_rd_adr_queue0_en};
2708 // read que read pointer
2709 wire [7:0] dram_Ch2_l2b0_rd_que_rd_ptr = {`MCU2_DRQ0_CTL.rdpctl_drq_clear_ent[7:0]};
2710
2711 // write que request
2712 wire dram_Ch2_l2b0_wr_req = `MCU2_L2IF0_CTL.l2t_mcu_wr_req;
2713 wire [2:0] dram_Ch2_l2b0_wr_addr = `MCU2_L2IF0_CTL.l2if_data_wr_addr;
2714
2715 wire [7:0] dram_ch2_l2b0_wr_q_valids = {`MCU2_DRQ0_CTL.drq_wr_queue_valid[7:0]};
2716 wire [3:0] dram_ch2_l2b0_drq_write_queue_cnt = {`MCU2_DRQ0_CTL.drq_write_queue_cnt[3:0]};
2717
2718 wire [40:0] dram_Ch2_l2b0_wr_q_0 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[0],
2719 `MCU2_DRQ0_CTL.drq_wrbuf_valids[0], //`DRAM_PATH2.writeqbank0vld0_arb,
2720 `MCU2_DRQ0_CTL.drq_wr_queue_ent0[11:9],
2721 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue0[3:0],
2722 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue0[2:0],
2723 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue0[14:0],
2724 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue0[10:0],
2725 3'b0};
2726
2727 wire [40:0] dram_Ch2_l2b0_wr_q_1 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[1],
2728 `MCU2_DRQ0_CTL.drq_wrbuf_valids[1], //`DRAM_PATH2.writeqbank0vld0_arb,
2729 `MCU2_DRQ0_CTL.drq_wr_queue_ent1[11:9],
2730 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue1[3:0],
2731 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue1[2:0],
2732 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue1[14:0],
2733 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue1[10:0],
2734 3'b0};
2735
2736 wire [40:0] dram_Ch2_l2b0_wr_q_2 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[2],
2737 `MCU2_DRQ0_CTL.drq_wrbuf_valids[2], //`DRAM_PATH2.writeqbank0vld0_arb,
2738 `MCU2_DRQ0_CTL.drq_wr_queue_ent2[11:9],
2739 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue2[3:0],
2740 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue2[2:0],
2741 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue2[14:0],
2742 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue2[10:0],
2743 3'b0};
2744
2745 wire [40:0] dram_Ch2_l2b0_wr_q_3 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[3],
2746 `MCU2_DRQ0_CTL.drq_wrbuf_valids[3], //`DRAM_PATH2.writeqbank0vld0_arb,
2747 `MCU2_DRQ0_CTL.drq_wr_queue_ent3[11:9],
2748 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue3[3:0],
2749 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue3[2:0],
2750 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue3[14:0],
2751 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue3[10:0],
2752 3'b0};
2753
2754 wire [40:0] dram_Ch2_l2b0_wr_q_4 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[4],
2755 `MCU2_DRQ0_CTL.drq_wrbuf_valids[4], //`DRAM_PATH2.writeqbank0vld0_arb,
2756 `MCU2_DRQ0_CTL.drq_wr_queue_ent4[11:9],
2757 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue4[3:0],
2758 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue4[2:0],
2759 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue4[14:0],
2760 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue4[10:0],
2761 3'b0};
2762
2763 wire [40:0] dram_Ch2_l2b0_wr_q_5 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[5],
2764 `MCU2_DRQ0_CTL.drq_wrbuf_valids[5], //`DRAM_PATH2.writeqbank0vld0_arb,
2765 `MCU2_DRQ0_CTL.drq_wr_queue_ent5[11:9],
2766 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue5[3:0],
2767 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue5[2:0],
2768 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue5[14:0],
2769 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue5[10:0],
2770 3'b0};
2771
2772 wire [40:0] dram_Ch2_l2b0_wr_q_6 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[6],
2773 `MCU2_DRQ0_CTL.drq_wrbuf_valids[6], //`DRAM_PATH2.writeqbank0vld0_arb,
2774 `MCU2_DRQ0_CTL.drq_wr_queue_ent6[11:9],
2775 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue6[3:0],
2776 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue6[2:0],
2777 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue6[14:0],
2778 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue6[10:0],
2779 3'b0};
2780
2781 wire [40:0] dram_Ch2_l2b0_wr_q_7 = {`MCU2_DRQ0_CTL.drq_wrbuf_valids[7],
2782 `MCU2_DRQ0_CTL.drq_wrbuf_valids[7], //`DRAM_PATH2.writeqbank0vld0_arb,
2783 `MCU2_DRQ0_CTL.drq_wr_queue_ent7[11:9],
2784 `MCU2_L2B0_ADR_Q.rank_wr_adr_queue7[3:0],
2785 `MCU2_L2B0_ADR_Q.bank_wr_adr_queue7[2:0],
2786 `MCU2_L2B0_ADR_Q.ras_wr_adr_queue7[14:0],
2787 `MCU2_L2B0_ADR_Q.cas_wr_adr_queue7[10:0],
2788 3'b0};
2789
2790 reg [40:0] dram_Ch2_l2b0_wr_q[7:0];
2791
2792 // to not set valid for the fifo monitor
2793 wire dram_Ch2_l2b0_pa_err = `MCU2_L2RDMX_DP.l2b0_wr_addr_err;
2794
2795 // write que collapsing fifo
2796 wire [14:0] dram_Ch2_l2b0_wr_colps_q_0 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent0[14:0]};
2797 wire [14:0] dram_Ch2_l2b0_wr_colps_q_1 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent1[14:0]};
2798 wire [14:0] dram_Ch2_l2b0_wr_colps_q_2 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent2[14:0]};
2799 wire [14:0] dram_Ch2_l2b0_wr_colps_q_3 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent3[14:0]};
2800 wire [14:0] dram_Ch2_l2b0_wr_colps_q_4 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent4[14:0]};
2801 wire [14:0] dram_Ch2_l2b0_wr_colps_q_5 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent5[14:0]};
2802 wire [14:0] dram_Ch2_l2b0_wr_colps_q_6 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent6[14:0]};
2803 wire [14:0] dram_Ch2_l2b0_wr_colps_q_7 = {`MCU2_DRQ0_CTL.drq_wr_queue_ent7[14:0]};
2804
2805 reg [14:0] dram_Ch2_l2b0_wr_colps_q[7:0];
2806
2807 // write que write pointer
2808 wire [7:0] dram_Ch2_l2b0_wr_que_wr_ptr = {`MCU2_DRQ0_CTL.drq_wr_adr_queue7_en,
2809 `MCU2_DRQ0_CTL.drq_wr_adr_queue6_en,
2810 `MCU2_DRQ0_CTL.drq_wr_adr_queue5_en,
2811 `MCU2_DRQ0_CTL.drq_wr_adr_queue4_en,
2812 `MCU2_DRQ0_CTL.drq_wr_adr_queue3_en,
2813 `MCU2_DRQ0_CTL.drq_wr_adr_queue2_en,
2814 `MCU2_DRQ0_CTL.drq_wr_adr_queue1_en,
2815 `MCU2_DRQ0_CTL.drq_wr_adr_queue0_en};
2816
2817 // write que arb read pointer
2818
2819 // write que data read pointer
2820 /*wire [7:0] dram_Ch2_l2b0_wr_que_rd_ptr = {`MCU2_DRQ0_CTL.drq_wr_entry7_rank,
2821 `MCU2_DRQ0_CTL.drq_wr_entry6_rank,
2822 `MCU2_DRQ0_CTL.drq_wr_entry5_rank,
2823 `MCU2_DRQ0_CTL.drq_wr_entry4_rank,
2824 `MCU2_DRQ0_CTL.drq_wr_entry3_rank,
2825 `MCU2_DRQ0_CTL.drq_wr_entry2_rank,
2826 `MCU2_DRQ0_CTL.drq_wr_entry1_rank,
2827 `MCU2_DRQ0_CTL.drq_wr_entry0_rank};*/
2828 wire [7:0] dram_Ch2_l2b0_wr_que_rd_ptr = `MCU2_DRQ0_CTL.drq_wrq_clear_ent;
2829
2830
2831// These signals are currently not used in cov obj
2832// enable for 8 deep collps rd fifo
2833 wire [7:0] dram_Ch2_l2b0_que_b0_index_en = {`MCU2_L2B0_ADR_Q.rd_adr_queue_sel[7:0]};
2834
2835
2836// These signals are currently not used in cov obj
2837// enable for 8 deep collps wr fifo
2838 wire [7:0] dram_Ch2_l2b0_que_b0_wr_index_en= {`MCU2_L2B0_ADR_Q.wr_adr_queue_sel[7:0]};
2839
2840// These signals are currently not used in cov obj
2841// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
2842 wire [7:0] dram_Ch2_l2b0_que_b0_rd_in_val = `MCU2_DRQ0_CTL.drq_rd_entry0_val[7:0];
2843
2844 wire dram_Ch2_que_b0_rd_picked = `MCU2_DRIF_CTL.drif0_rd_picked;
2845 wire dram_Ch2_que_b0_wr_picked = `MCU2_DRIF_CTL.drif0_wr_picked;
2846 // read que request
2847 wire dram_Ch2_l2b1_rd_req = `MCU2_L2IF1_CTL.l2t_mcu_rd_req;
2848 wire [2:0] dram_Ch2_l2b1_rd_id = `MCU2_L2IF1_CTL.l2t_mcu_rd_req_id[2:0];
2849 wire dram_Ch2_l2b1_errq_vld = (!`MCU2_DRIF_CTL.drif_err_fifo_empty) & (`MCU2_DRIF_CTL.rdpctl_err_fifo_data[0] == 1) ;
2850 wire [2:0] dram_Ch2_l2b1_errq_id = `MCU2_DRIF_CTL.rdpctl_err_fifo_data[4:2];
2851 // read que
2852 wire dram_ch2_l2b1_rd_q_vld_0 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2853 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2854 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2855 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2856 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2857 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2858 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) |
2859 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0])) };
2860
2861 wire dram_ch2_l2b1_rd_q_vld_1 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2862 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2863 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2864 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2865 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2866 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2867 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) |
2868 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1])) };
2869
2870 wire dram_ch2_l2b1_rd_q_vld_2 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2871 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2872 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2873 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2874 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2875 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2876 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) |
2877 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2])) };
2878
2879 wire dram_ch2_l2b1_rd_q_vld_3 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2880 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2881 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2882 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2883 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2884 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2885 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) |
2886 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3])) };
2887
2888 wire dram_ch2_l2b1_rd_q_vld_4 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2889 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2890 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2891 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2892 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2893 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2894 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) |
2895 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4])) };
2896
2897 wire dram_ch2_l2b1_rd_q_vld_5 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2898 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2899 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2900 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2901 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2902 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2903 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) |
2904 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5])) };
2905
2906 wire dram_ch2_l2b1_rd_q_vld_6 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2907 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2908 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2909 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2910 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2911 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2912 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) |
2913 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6])) };
2914
2915 wire dram_ch2_l2b1_rd_q_vld_7 = { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2916 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2917 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2918 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2919 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2920 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2921 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) |
2922 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7])) };
2923
2924 wire [7:0] dram_ch2_l2b1_rd_q_valids = {dram_ch2_l2b1_rd_q_vld_7, dram_ch2_l2b1_rd_q_vld_6, dram_ch2_l2b1_rd_q_vld_5, dram_ch2_l2b1_rd_q_vld_4,
2925 dram_ch2_l2b1_rd_q_vld_3, dram_ch2_l2b1_rd_q_vld_2, dram_ch2_l2b1_rd_q_vld_1, dram_ch2_l2b1_rd_q_vld_0};
2926
2927// Read request Q PA-Error
2928 wire dram_ch2_l2b1_rd_q_addr_err_0 =
2929 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2930 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2931 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2932 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2933 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2934 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2935 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2936 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
2937
2938 wire dram_ch2_l2b1_rd_q_addr_err_1 =
2939 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2940 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2941 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2942 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2943 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2944 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2945 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2946 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) };
2947
2948 wire dram_ch2_l2b1_rd_q_addr_err_2 =
2949 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2950 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2951 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2952 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2953 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2954 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2955 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2956 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
2957
2958 wire dram_ch2_l2b1_rd_q_addr_err_3 =
2959 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2960 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2961 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2962 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2963 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2964 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2965 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2966 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
2967
2968 wire dram_ch2_l2b1_rd_q_addr_err_4 =
2969 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2970 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2971 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2972 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2973 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2974 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2975 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2976 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
2977
2978 wire dram_ch2_l2b1_rd_q_addr_err_5 =
2979 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2980 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2981 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2982 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2983 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2984 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2985 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2986 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
2987
2988 wire dram_ch2_l2b1_rd_q_addr_err_6 =
2989 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
2990 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
2991 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
2992 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
2993 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
2994 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
2995 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
2996 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
2997
2998 wire dram_ch2_l2b1_rd_q_addr_err_7 =
2999 { ((`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent0[7]) |
3000 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent1[7]) |
3001 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent2[7]) |
3002 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent3[7]) |
3003 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent4[7]) |
3004 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent5[7]) |
3005 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent6[7]) |
3006 ((`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU2_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU2_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU2_DRQ1_CTL.drq_rd_queue_ent7[7]) };
3007
3008 wire [7:0] dram_ch2_l2b1_rd_q_addr_err = {dram_ch2_l2b1_rd_q_addr_err_7, dram_ch2_l2b1_rd_q_addr_err_6, dram_ch2_l2b1_rd_q_addr_err_5, dram_ch2_l2b1_rd_q_addr_err_4,
3009 dram_ch2_l2b1_rd_q_addr_err_3, dram_ch2_l2b1_rd_q_addr_err_2, dram_ch2_l2b1_rd_q_addr_err_1, dram_ch2_l2b1_rd_q_addr_err_0};
3010
3011 wire [7:0] dram_ch2_l2b1_drq_rd_queue_valid = {`MCU2_DRQ1_CTL.drq_rd_queue_valid[7:0]};
3012 wire [3:0] dram_ch2_l2b1_drq_read_queue_cnt = {`MCU2_DRQ1_CTL.drq_read_queue_cnt[3:0]};
3013
3014// Read request Q PA-Error
3015
3016 wire [39:0] dram_Ch2_l2b1_rd_q_0 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[0],
3017 `MCU2_L2B1_ADR_Q.rd_req_id_queue0[2:0],
3018 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue0[3:0],
3019 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue0[2:0],
3020 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue0[14:0],
3021 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue0[10:0],
3022 3'b0 };
3023
3024 wire [39:0] dram_Ch2_l2b1_rd_q_1 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[1],
3025 `MCU2_L2B1_ADR_Q.rd_req_id_queue1[2:0],
3026 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue1[3:0],
3027 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue1[2:0],
3028 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue1[14:0],
3029 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue1[10:0],
3030 3'b0 };
3031
3032 wire [39:0] dram_Ch2_l2b1_rd_q_2 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[2],
3033 `MCU2_L2B1_ADR_Q.rd_req_id_queue2[2:0],
3034 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue2[3:0],
3035 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue2[2:0],
3036 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue2[14:0],
3037 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue2[10:0],
3038 3'b0 };
3039
3040 wire [39:0] dram_Ch2_l2b1_rd_q_3 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[3],
3041 `MCU2_L2B1_ADR_Q.rd_req_id_queue3[2:0],
3042 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue3[3:0],
3043 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue3[2:0],
3044 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue3[14:0],
3045 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue3[10:0],
3046 3'b0 };
3047
3048 wire [39:0] dram_Ch2_l2b1_rd_q_4 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[4],
3049 `MCU2_L2B1_ADR_Q.rd_req_id_queue4[2:0],
3050 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue4[3:0],
3051 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue4[2:0],
3052 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue4[14:0],
3053 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue4[10:0],
3054 3'b0 };
3055
3056 wire [39:0] dram_Ch2_l2b1_rd_q_5 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[5],
3057 `MCU2_L2B1_ADR_Q.rd_req_id_queue5[2:0],
3058 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue5[3:0],
3059 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue5[2:0],
3060 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue5[14:0],
3061 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue5[10:0],
3062 3'b0 };
3063
3064 wire [39:0] dram_Ch2_l2b1_rd_q_6 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[6],
3065 `MCU2_L2B1_ADR_Q.rd_req_id_queue6[2:0],
3066 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue6[3:0],
3067 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue6[2:0],
3068 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue6[14:0],
3069 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue6[10:0],
3070 3'b0 };
3071
3072 wire [39:0] dram_Ch2_l2b1_rd_q_7 = {`MCU2_DRQ1_CTL.drq_rdbuf_valids[7],
3073 `MCU2_L2B1_ADR_Q.rd_req_id_queue7[2:0],
3074 `MCU2_L2B1_ADR_Q.rank_rd_adr_queue7[3:0],
3075 `MCU2_L2B1_ADR_Q.bank_rd_adr_queue7[2:0],
3076 `MCU2_L2B1_ADR_Q.ras_rd_adr_queue7[14:0],
3077 `MCU2_L2B1_ADR_Q.cas_rd_adr_queue7[10:0],
3078 3'b0 };
3079
3080
3081 reg [39:0] dram_Ch2_l2b1_rd_q[7:0];
3082 // read que collapsing fifo
3083 wire [11:0] dram_Ch2_l2b1_rd_colps_q_0 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent0[11:0]};
3084 wire [11:0] dram_Ch2_l2b1_rd_colps_q_1 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent1[11:0]};
3085 wire [11:0] dram_Ch2_l2b1_rd_colps_q_2 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent2[11:0]};
3086 wire [11:0] dram_Ch2_l2b1_rd_colps_q_3 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent3[11:0]};
3087 wire [11:0] dram_Ch2_l2b1_rd_colps_q_4 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent4[11:0]};
3088 wire [11:0] dram_Ch2_l2b1_rd_colps_q_5 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent5[11:0]};
3089 wire [11:0] dram_Ch2_l2b1_rd_colps_q_6 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent6[11:0]};
3090 wire [11:0] dram_Ch2_l2b1_rd_colps_q_7 = {`MCU2_DRQ1_CTL.drq_rd_queue_ent7[11:0]};
3091
3092 reg [11:0] dram_Ch2_l2b1_rd_colps_q[7:0];
3093
3094 // read que write pointer
3095 wire [7:0] dram_Ch2_l2b1_rd_que_wr_ptr = {`MCU2_DRQ1_CTL.drq_rd_adr_queue7_en,
3096 `MCU2_DRQ1_CTL.drq_rd_adr_queue6_en,
3097 `MCU2_DRQ1_CTL.drq_rd_adr_queue5_en,
3098 `MCU2_DRQ1_CTL.drq_rd_adr_queue4_en,
3099 `MCU2_DRQ1_CTL.drq_rd_adr_queue3_en,
3100 `MCU2_DRQ1_CTL.drq_rd_adr_queue2_en,
3101 `MCU2_DRQ1_CTL.drq_rd_adr_queue1_en,
3102 `MCU2_DRQ1_CTL.drq_rd_adr_queue0_en};
3103 // read que read pointer
3104 wire [7:0] dram_Ch2_l2b1_rd_que_rd_ptr = {`MCU2_DRQ1_CTL.rdpctl_drq_clear_ent[7:0]};
3105
3106 // write que request
3107 wire dram_Ch2_l2b1_wr_req = `MCU2_L2IF1_CTL.l2t_mcu_wr_req;
3108 wire [2:0] dram_Ch2_l2b1_wr_addr = `MCU2_L2IF1_CTL.l2if_data_wr_addr;
3109
3110 wire [7:0] dram_ch2_l2b1_wr_q_valids = {`MCU2_DRQ1_CTL.drq_wr_queue_valid[7:0]};
3111 wire [3:0] dram_ch2_l2b1_drq_write_queue_cnt = {`MCU2_DRQ1_CTL.drq_write_queue_cnt[3:0]};
3112
3113 wire [40:0] dram_Ch2_l2b1_wr_q_0 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[0],
3114 `MCU2_DRQ1_CTL.drq_wrbuf_valids[0], //`DRAM_PATH2.writeqbank0vld0_arb,
3115 `MCU2_DRQ1_CTL.drq_wr_queue_ent0[11:9],
3116 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue0[3:0],
3117 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue0[2:0],
3118 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue0[14:0],
3119 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue0[10:0],
3120 3'b0};
3121
3122 wire [40:0] dram_Ch2_l2b1_wr_q_1 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[1],
3123 `MCU2_DRQ1_CTL.drq_wrbuf_valids[1], //`DRAM_PATH2.writeqbank0vld0_arb,
3124 `MCU2_DRQ1_CTL.drq_wr_queue_ent1[11:9],
3125 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue1[3:0],
3126 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue1[2:0],
3127 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue1[14:0],
3128 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue1[10:0],
3129 3'b0};
3130
3131 wire [40:0] dram_Ch2_l2b1_wr_q_2 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[2],
3132 `MCU2_DRQ1_CTL.drq_wrbuf_valids[2], //`DRAM_PATH2.writeqbank0vld0_arb,
3133 `MCU2_DRQ1_CTL.drq_wr_queue_ent2[11:9],
3134 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue2[3:0],
3135 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue2[2:0],
3136 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue2[14:0],
3137 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue2[10:0],
3138 3'b0};
3139
3140 wire [40:0] dram_Ch2_l2b1_wr_q_3 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[3],
3141 `MCU2_DRQ1_CTL.drq_wrbuf_valids[3], //`DRAM_PATH2.writeqbank0vld0_arb,
3142 `MCU2_DRQ1_CTL.drq_wr_queue_ent3[11:9],
3143 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue3[3:0],
3144 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue3[2:0],
3145 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue3[14:0],
3146 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue3[10:0],
3147 3'b0};
3148
3149 wire [40:0] dram_Ch2_l2b1_wr_q_4 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[4],
3150 `MCU2_DRQ1_CTL.drq_wrbuf_valids[4], //`DRAM_PATH2.writeqbank0vld0_arb,
3151 `MCU2_DRQ1_CTL.drq_wr_queue_ent4[11:9],
3152 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue4[3:0],
3153 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue4[2:0],
3154 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue4[14:0],
3155 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue4[10:0],
3156 3'b0};
3157
3158 wire [40:0] dram_Ch2_l2b1_wr_q_5 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[5],
3159 `MCU2_DRQ1_CTL.drq_wrbuf_valids[5], //`DRAM_PATH2.writeqbank0vld0_arb,
3160 `MCU2_DRQ1_CTL.drq_wr_queue_ent5[11:9],
3161 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue5[3:0],
3162 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue5[2:0],
3163 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue5[14:0],
3164 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue5[10:0],
3165 3'b0};
3166
3167 wire [40:0] dram_Ch2_l2b1_wr_q_6 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[6],
3168 `MCU2_DRQ1_CTL.drq_wrbuf_valids[6], //`DRAM_PATH2.writeqbank0vld0_arb,
3169 `MCU2_DRQ1_CTL.drq_wr_queue_ent6[11:9],
3170 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue6[3:0],
3171 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue6[2:0],
3172 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue6[14:0],
3173 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue6[10:0],
3174 3'b0};
3175
3176 wire [40:0] dram_Ch2_l2b1_wr_q_7 = {`MCU2_DRQ1_CTL.drq_wrbuf_valids[7],
3177 `MCU2_DRQ1_CTL.drq_wrbuf_valids[7], //`DRAM_PATH2.writeqbank0vld0_arb,
3178 `MCU2_DRQ1_CTL.drq_wr_queue_ent7[11:9],
3179 `MCU2_L2B1_ADR_Q.rank_wr_adr_queue7[3:0],
3180 `MCU2_L2B1_ADR_Q.bank_wr_adr_queue7[2:0],
3181 `MCU2_L2B1_ADR_Q.ras_wr_adr_queue7[14:0],
3182 `MCU2_L2B1_ADR_Q.cas_wr_adr_queue7[10:0],
3183 3'b0};
3184
3185 reg [40:0] dram_Ch2_l2b1_wr_q[7:0];
3186
3187 // to not set valid for the fifo monitor
3188 wire dram_Ch2_l2b1_pa_err = `MCU2_L2RDMX_DP.l2b1_wr_addr_err;
3189
3190 // write que collapsing fifo
3191 wire [14:0] dram_Ch2_l2b1_wr_colps_q_0 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent0[14:0]};
3192 wire [14:0] dram_Ch2_l2b1_wr_colps_q_1 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent1[14:0]};
3193 wire [14:0] dram_Ch2_l2b1_wr_colps_q_2 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent2[14:0]};
3194 wire [14:0] dram_Ch2_l2b1_wr_colps_q_3 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent3[14:0]};
3195 wire [14:0] dram_Ch2_l2b1_wr_colps_q_4 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent4[14:0]};
3196 wire [14:0] dram_Ch2_l2b1_wr_colps_q_5 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent5[14:0]};
3197 wire [14:0] dram_Ch2_l2b1_wr_colps_q_6 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent6[14:0]};
3198 wire [14:0] dram_Ch2_l2b1_wr_colps_q_7 = {`MCU2_DRQ1_CTL.drq_wr_queue_ent7[14:0]};
3199
3200 reg [14:0] dram_Ch2_l2b1_wr_colps_q[7:0];
3201
3202 // write que write pointer
3203 wire [7:0] dram_Ch2_l2b1_wr_que_wr_ptr = {`MCU2_DRQ1_CTL.drq_wr_adr_queue7_en,
3204 `MCU2_DRQ1_CTL.drq_wr_adr_queue6_en,
3205 `MCU2_DRQ1_CTL.drq_wr_adr_queue5_en,
3206 `MCU2_DRQ1_CTL.drq_wr_adr_queue4_en,
3207 `MCU2_DRQ1_CTL.drq_wr_adr_queue3_en,
3208 `MCU2_DRQ1_CTL.drq_wr_adr_queue2_en,
3209 `MCU2_DRQ1_CTL.drq_wr_adr_queue1_en,
3210 `MCU2_DRQ1_CTL.drq_wr_adr_queue0_en};
3211
3212 // write que arb read pointer
3213
3214 // write que data read pointer
3215 /*wire [7:0] dram_Ch2_l2b1_wr_que_rd_ptr = {`MCU2_DRQ1_CTL.drq_wr_entry7_rank,
3216 `MCU2_DRQ1_CTL.drq_wr_entry6_rank,
3217 `MCU2_DRQ1_CTL.drq_wr_entry5_rank,
3218 `MCU2_DRQ1_CTL.drq_wr_entry4_rank,
3219 `MCU2_DRQ1_CTL.drq_wr_entry3_rank,
3220 `MCU2_DRQ1_CTL.drq_wr_entry2_rank,
3221 `MCU2_DRQ1_CTL.drq_wr_entry1_rank,
3222 `MCU2_DRQ1_CTL.drq_wr_entry0_rank};*/
3223 wire [7:0] dram_Ch2_l2b1_wr_que_rd_ptr = `MCU2_DRQ1_CTL.drq_wrq_clear_ent;
3224
3225
3226// These signals are currently not used in cov obj
3227// enable for 8 deep collps rd fifo
3228 wire [7:0] dram_Ch2_l2b1_que_b0_index_en = {`MCU2_L2B1_ADR_Q.rd_adr_queue_sel[7:0]};
3229
3230
3231// These signals are currently not used in cov obj
3232// enable for 8 deep collps wr fifo
3233 wire [7:0] dram_Ch2_l2b1_que_b0_wr_index_en= {`MCU2_L2B1_ADR_Q.wr_adr_queue_sel[7:0]};
3234
3235// These signals are currently not used in cov obj
3236// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
3237 wire [7:0] dram_Ch2_l2b1_que_b0_rd_in_val = `MCU2_DRQ1_CTL.drq_rd_entry0_val[7:0];
3238
3239 wire dram_Ch2_que_b1_rd_picked = `MCU2_DRIF_CTL.drif1_rd_picked;
3240 wire dram_Ch2_que_b1_wr_picked = `MCU2_DRIF_CTL.drif1_wr_picked;
3241
3242
3243
3244// MAQ Not Required wire [7:0] dram_Ch2_que_cas_picked = `MCU2_DRIF_CTL.drif_cas_picked_d1[7:0];
3245// rd hits a wr in the wr Q
3246 wire dram_Ch2_que_rd_wr_hit = `MCU2_DRIF_CTL.drif_wr_entry_pend_in;
3247
3248// MAQ N2 doesn't support // Signals that will be used to detect oldest entry to the same bank.
3249// MAQ N2 doesn't support // in 2 channel mode this is the real indicator that the request is picked from this channel
3250// MAQ N2 doesn't support wire dram_Ch2_que_this_ch_picked = (~`DRAM_PATH2.que_channel_disabled) ?
3251// MAQ N2 doesn't support `DRAM_PATH2.que_ras_bank_picked_en && ~`DRAM_PATH2.que_channel_picked_internal:
3252// MAQ N2 doesn't support `DRAM_PATH2.que_ras_bank_picked_en && `DRAM_PATH2.que_channel_picked_internal;
3253// MAQ N2 doesn't support
3254
3255 wire [2:0] dram_Ch2_que_b0_index_picked = `MCU2_DRIF_CTL.drif_rdwr_index_picked[2:0];
3256 wire dram_Ch2_que_b0_cmd_picked = `MCU2_DRIF_CTL.drif_rdwr_cmd_picked;
3257 wire dram_ch2_drif_mclk_en = `MCU2_DRIF_CTL.drif_mclk_en;
3258
3259
3260//----------------------------------------------------------------------------------------
3261// Refresh to go and all CAS request to same CS are done, no new RAS issued.
3262//----------------------------------------------------------------------------------------
3263 wire [4:0] dram_Ch2_que_pos = `MCU2_DRIF_CTL.drif_mcu_state_enc;
3264 wire dram_Ch2_que_ref_go = `MCU2_DRIF_CTL.drif_ref_go;
3265 wire dram_Ch2_que_hw_selfrsh = `MCU2_DRIF_CTL.drif_hw_selfrsh;
3266 wire dram_Ch2_pt_blk_new_openbank_d1 = `MCU2_DRIF_CTL.drif_blk_new_openbank;
3267 wire dram_Ch2_que_cas_valid = ( (|(`MCU2_DRIF_CTL.drif_cas_picked)) &
3268 (`MCU2_DRIF_CTL.drif_phy_bank_picked[1:0] == `MCU2_DRIF_CTL.drif_refresh_rank[1:0])
3269 );
3270 wire [15:0] dram_Ch2_ras_picked = `MCU2_DRIF_CTL.drif_ras_picked[15:0];
3271 wire dram_Ch2_que_ras_picked = ( (|(`MCU2_DRIF_CTL.drif_ras_picked[15:0])) &
3272 ({`MCU2_DRIF_CTL.drif_rank_adr, `MCU2_DRIF_CTL.drif_stacked_dimm} == `MCU2_DRIF_CTL.drif_refresh_rank[1:0])
3273 );
3274 wire [1:0] dram_Ch2_b0_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3275 wire [1:0] dram_Ch2_b1_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3276 wire [1:0] dram_Ch2_b2_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3277 wire [1:0] dram_Ch2_b3_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3278 wire [1:0] dram_Ch2_b4_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3279 wire [1:0] dram_Ch2_b5_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3280 wire [1:0] dram_Ch2_b6_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3281 wire [1:0] dram_Ch2_b7_phy_bank_bits = `MCU2_DRIF_CTL.drif_phy_bank_picked[1:0];
3282 reg [1:0] dram_Ch2_b_phy_bank_bits[7:0];
3283
3284 wire [1:0] dram_Ch2_que_refresh_rank = `MCU2_DRIF_CTL.drif_refresh_rank[1:0];
3285
3286
3287// ---- Starvation counter causing the wr to have priority ---
3288 wire dram_Ch2_que_pick_wr_first = (`MCU2_DRIF_CTL.drif0_pick_wr_first |
3289 `MCU2_DRIF_CTL.drif1_pick_wr_first);
3290
3291// ------ Scrub Related -------
3292
3293 // picking the que_split_scrb_addr as _que_scrb_addr_picked_
3294 wire [31:0] dram_Ch2_que_scrb_addr_picked = `MCU2_DRIF_CTL.drif_scrub_addr;
3295 wire dram_Ch2_que_scrb_picked = `MCU2_DRIF_CTL.drif_scrub_picked;
3296 //somePersonwire dram_Ch2_que_scrb_rd_picked = `MCU2_DRIF_CTL.drif_scrub_picked; // MAQ
3297 wire dram_Ch2_que_scrb_rd_picked = `MCU2_DRIF_CTL.drif_scrub_read_pending;
3298 wire dram_Ch2_que_ras_bank_picked_en = |(`MCU2_DRIF_CTL.drif_ras_picked[15:0]);
3299 wire dram_Ch2_que_scrb_write_req = `MCU2_DRIF_CTL.drif_scrub_write_req;
3300
3301// req valid and scrb valid, the scrb should be cleared first
3302 wire [15:0] dram_Ch2_que_l2req_valid = `MCU2_DRIF_CTL.drif0_rd_bank_valids | `MCU2_DRIF_CTL.drif1_rd_bank_valids |
3303 `MCU2_DRIF_CTL.drif_wr_bank_valids;
3304 wire [15:0] dram_Ch2_scrb_indx_val = `MCU2_DRIF_CTL.drif_scrub_entry_val;
3305
3306// ------- DRAM REGISTERS --------
3307
3308 wire [8:0] dram_Ch2_chip_config_reg = {`MCU2_DRIF_CTL.drif_ras_addr_bits[3:0],
3309 `MCU2_DRIF_CTL.drif_cas_addr_bits[3:0],
3310 `MCU2_DRIF_CTL.drif_stacked_dimm};
3311
3312 wire [2:0] dram_Ch2_mode_reg = `MCU2_DRIF_CTL.mode_reg[6:4];
3313 wire [3:0] dram_Ch2_rrd_reg = `MCU2_DRIF_CTL.rrd_reg;
3314 wire [4:0] dram_Ch2_rc_reg = `MCU2_DRIF_CTL.rc_reg;
3315 wire [3:0] dram_Ch2_rcd_reg = `MCU2_DRIF_CTL.rcd_reg;
3316 wire [3:0] dram_Ch2_wtr_dly_reg = `MCU2_DRIF_CTL.wtr_dly_reg;
3317 wire [3:0] dram_Ch2_rtw_dly_reg = `MCU2_DRIF_CTL.rtw_dly_reg;
3318 wire [3:0] dram_Ch2_rtp_reg = `MCU2_DRIF_CTL.rtp_reg;
3319 wire [3:0] dram_Ch2_ras_reg = `MCU2_DRIF_CTL.ras_reg;
3320 wire [3:0] dram_Ch2_rp_reg = `MCU2_DRIF_CTL.rp_reg;
3321 wire [3:0] dram_Ch2_wr_reg = `MCU2_DRIF_CTL.wr_reg;
3322 wire [1:0] dram_Ch2_mrd_reg = `MCU2_DRIF_CTL.mrd_reg;
3323 wire [1:0] dram_Ch2_iwtr_reg = `MCU2_DRIF_CTL.iwtr_reg;
3324 wire [14:0] dram_Ch2_ext_mode_reg2 = `MCU2_DRIF_CTL.ext_mode_reg2;
3325 wire [14:0] dram_Ch2_ext_mode_reg1 = `MCU2_DRIF_CTL.ext_mode_reg1;
3326 wire [14:0] dram_Ch2_ext_mode_reg3 = `MCU2_DRIF_CTL.ext_mode_reg3;
3327 wire dram_Ch2_que_eight_bank_mode = `MCU2_DRIF_CTL.drif_eight_bank_mode;
3328 wire dram_Ch2_que_rank1_present = `MCU2_DRIF_CTL.drif_dimms_present[0];
3329 wire dram_Ch2_que_channel_disabled = `MCU2_DRIF_CTL.drif_branch_disabled;
3330 wire dram_Ch2_que_addr_bank_low_sel = `MCU2_DRIF_CTL.drif_addr_bank_low_sel;
3331 wire dram_Ch2_que_init = `MCU2_DRIF_CTL.drif_init;
3332// wire [2:0] dram_Ch2_que_data_del_cnt = `MCU2_DRIF_CTL.drif_data_del_cnt[2:0];
3333// wire dram_Ch2_dram_io_pad_clk_inv = `MCU2_DRIF_CTL.mcu_ddp_pad_clk_inv;
3334// wire [1:0] dram_Ch2_dram_io_ptr_clk_inv = `MCU2_DRIF_CTL.mcu_ddp_ptr_clk_inv;
3335 wire dram_Ch2_que_wr_mode_reg_done = `MCU2_DRIF_CTL.drif_wr_mode_reg_done;
3336 wire dram_Ch2_que_init_status_reg = `MCU2_DRIF_CTL.drif_init_status_reg;
3337 wire [3:0] dram_Ch2_que_dimms_present = `MCU2_DRIF_CTL.drif_dimms_present;
3338 wire dram_Ch2_dram_fail_over_mode = `MCU2_DRIF_CTL.drif_fail_over_mode;
3339 wire [34:0] dram_Ch2_dram_fail_over_mask = `MCU2_DRIF_CTL.drif_fail_over_mask[34:0];
3340 wire dram_Ch2_que_dbg_trig_en = `MCU2_DRIF_CTL.rdpctl_dbg_trig_enable;
3341 wire [22:0] dram_Ch2_que_err_sts_reg = `MCU2_DRIF_CTL.rdpctl_err_sts_reg;
3342 wire [35:0] dram_Ch2_que_err_addr_reg = `MCU2_DRIF_CTL.rdpctl_err_addr_reg;
3343 wire dram_Ch2_err_inj_reg = `MCU2_DRIF_CTL.drif_err_inj_reg;
3344 wire dram_Ch2_sshot_err_reg = `MCU2_DRIF_CTL.drif_sshot_err_reg;
3345// wire [1:0] dram_Ch2_que_err_cnt = `MCU2_DRIF_CTL.rdpctl_err_cnt[17:16];
3346 wire [35:0] dram_Ch2_que_err_loc = `MCU2_DRIF_CTL.rdpctl_err_loc;
3347
3348 // NACK - for non existant register read
3349 wire dram_Ch2_que_l2if_ack_vld = `MCU2_DRIF_CTL.drif_rdata_ack_vld;
3350 wire dram_Ch2_que_l2if_nack_vld = `MCU2_DRIF_CTL.drif_rdata_nack_vld;
3351
3352 wire dram_Ch2_que_init_dram_done = `MCU2_DRIF_CTL.drif_init_mcu_done;
3353
3354// ----- DRAM L2IF INTERFACE -----
3355
3356 wire [127:0] dram_Ch2_dram_sctag_data = `MCU2.mcu_l2b_data_r3;
3357 // Error signal for update of error status, error location and error address register.
3358 //wire dram_Ch2_l2if_scrb_val_d2 = `DRAM_L2IF2.l2if_scrb_val_d3;
3359
3360 // l2if_scrb_data_val is now qualifying scrb in the rtl
3361 wire dram_Ch2_l2if_scrb_val_d2 = `MCU2_RDPCTL_CTL.rdpctl_scrub_data_valid;
3362
3363 wire [6:0] dram_Ch2_err_sts_reg = `MCU2_RDPCTL_CTL.rdpctl_err_sts_reg[25:19];
3364
3365 wire dram_Ch2_l2if_err_sts_reg_en6 = `MCU2_RDPCTL_CTL.rdpctl_meu_error_en;
3366 wire dram_Ch2_l2if_err_sts_reg_en5 = `MCU2_RDPCTL_CTL.rdpctl_mec_error_en;
3367 wire dram_Ch2_l2if_err_sts_reg_en4 = `MCU2_RDPCTL_CTL.rdpctl_dac_error_en;
3368 wire dram_Ch2_l2if_err_sts_reg_en3 = `MCU2_RDPCTL_CTL.rdpctl_dau_error_en;
3369 wire dram_Ch2_l2if_err_sts_reg_en2 = `MCU2_RDPCTL_CTL.rdpctl_dsc_error_en;
3370 wire dram_Ch2_l2if_err_sts_reg_en1 = `MCU2_RDPCTL_CTL.rdpctl_dsu_error_en;
3371 wire dram_Ch2_l2if_err_sts_reg_en0 = `MCU2_RDPCTL_CTL.rdpctl_err_sts_reg_en;
3372 wire dram_Ch2_l2if_err_sts_reg_en = `MCU2_RDPCTL_CTL.rdpctl_dbu_error_en;
3373 wire dram_Ch2_l2if_err_addr_reg_en = `MCU2_RDPCTL_CTL.rdpctl_err_addr_reg_en;
3374 wire dram_Ch2_l2if_secc_loc_en = `MCU2_RDPCTL_CTL.rdpctl_secc_loc_en;
3375
3376
3377 wire dram_Ch2_l2b0_sctag_dram_rd_req = `MCU2_L2IF0_CTL.l2t_mcu_rd_req;
3378 wire [2:0] dram_Ch2_l2b0_sctag_dram_rd_req_id = `MCU2_L2IF0_CTL.l2t_mcu_rd_req_id;
3379// wire [39:6] dram_Ch2_l2b0_sctag_dram_addr = {`MCU2_ADDRDP_DP.l2t0_mcu_addr_39to9, `MCU2_ADDRDP_DP.l2t0_mcu_addr_6to4};
3380 wire [39:5] dram_Ch2_l2b0_sctag_dram_addr = `MCU2_L2IF0_CTL.l2t_mcu_addr;
3381 wire dram_Ch2_l2b0_sctag_dram_rd_dummy_req = `MCU2_L2IF0_CTL.l2t_mcu_rd_dummy_req;
3382 wire dram_Ch2_l2b0_dram_sctag_rd_ack = `MCU2_L2IF0_CTL.mcu_l2t_rd_ack;
3383 wire dram_Ch2_l2b0_sctag_dram_wr_req = `MCU2_L2IF0_CTL.l2t_mcu_wr_req;
3384 wire dram_Ch2_l2b0_sctag_dram_data_vld = `MCU2_L2IF0_CTL.l2b_mcu_data_vld;
3385 wire [63:0] dram_Ch2_l2b0_sctag_dram_wr_data = `MCU2_L2RDMX_DP.l2b0_mcu_wr_data_r5;
3386 wire dram_Ch2_l2b0_dram_sctag_wr_ack = `MCU2_L2IF0_CTL.mcu_l2t_wr_ack;
3387 wire dram_Ch2_l2b0_dram_sctag_data_vld = `MCU2_RDATA_CTL.mcu_l2t0_data_vld_r0;
3388 wire [2:0] dram_Ch2_l2b0_dram_sctag_rd_req_id = `MCU2_RDATA_CTL.mcu_l2t0_rd_req_id_r0;
3389
3390// MAQ N2 doesn't support wire [3:0] dram_Ch2_l2if_b0_rd_val = `DRAM_L2IF2.l2if_b0_rd_val;
3391// MAQ N2 doesn't support wire [3:0] dram_Ch2_l2if_b1_rd_val = `DRAM_L2IF2.l2if_b1_rd_val;
3392 wire [3:0] dram_Ch2_l2b0_l2if_b0_wr_val = {`MCU2_L2IF0_CTL.l2if_wr_entry3,
3393 `MCU2_L2IF0_CTL.l2if_wr_entry2,
3394 `MCU2_L2IF0_CTL.l2if_wr_entry1,
3395 `MCU2_L2IF0_CTL.l2if_wr_entry0};
3396
3397 wire [3:0] dram_Ch2_l2b0_l2if_b1_wr_val = {`MCU2_L2IF0_CTL.l2if_wr_entry7,
3398 `MCU2_L2IF0_CTL.l2if_wr_entry6,
3399 `MCU2_L2IF0_CTL.l2if_wr_entry5,
3400 `MCU2_L2IF0_CTL.l2if_wr_entry4};
3401
3402// MAQ wire [5:0] dram_Ch2_l2b0_l2if_wr_b0_data_addr = `MCU2_L2IF0_CTL.l2if_wdq_wadr;
3403
3404 // Signals on L2 Interface that indicates Error
3405 wire dram_Ch2_l2b0_dram_sctag_secc_err = `MCU2_RDATA_CTL.mcu_l2t0_secc_err_r3;
3406 wire dram_Ch2_l2b0_dram_sctag_pa_err = `MCU2_L2RDMX_DP.l2b0_rd_addr_err | `MCU2_L2RDMX_DP.l2b0_wr_addr_err;
3407 wire dram_Ch2_l2b0_dram_sctag_mecc_err = `MCU2_RDATA_CTL.mcu_l2t0_mecc_err_r3;
3408 wire dram_Ch2_l2b0_dram_sctag_scb_secc_err = `MCU2_RDATA_CTL.mcu_l2t0_scb_secc_err;
3409 wire dram_Ch2_l2b0_dram_sctag_scb_mecc_err = `MCU2_RDATA_CTL.mcu_l2t0_scb_mecc_err;
3410
3411// qualified with vld since they can be on due to residual ( previous error )
3412/* wire dram_Ch2_l2b0_l2if_secc_err = `MCU2_RDATA_CTL.mcu_l2t0_secc_err_r3 &&
3413 (`MCU2_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
3414 `MCU2_RDPCTL_CTL.rdpctl_scrub_data_valid);
3415
3416 wire dram_Ch2_l2b0_l2if_mecc_err_partial = `MCU2_RDATA_CTL.mcu_l2t0_mecc_err_r3 &&
3417 (`MCU2_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
3418 `MCU2_RDPCTL_CTL.rdpctl_scrub_data_valid);
3419*/
3420 wire dram_Ch2_l2b0_l2if_secc_err = `MCU2_RDATA_CTL.mcu_l2t0_scb_secc_err_in ||
3421 `MCU2_RDATA_CTL.mcu_l2t0_secc_err_r1;
3422 wire dram_Ch2_l2b0_l2if_mecc_err_partial = `MCU2_RDATA_CTL.mcu_l2t0_scb_mecc_err_in ||
3423 `MCU2_RDATA_CTL.mcu_l2t0_mecc_err_r1;
3424 wire dram_Ch2_l2b0_l2if_pa_err = (`MCU2_L2RDMX_DP.l2b0_rd_addr_err || `MCU2_L2RDMX_DP.l2b0_wr_addr_err) &&
3425 `MCU2_RDATA_CTL.mcu_l2t0_data_vld_r0;
3426
3427 wire [1:0] dram_Ch2_l2b0_cpu_wr_en = `MCU2_L2IF0_CTL.l2if_wdq_we;
3428 wire [4:0] dram_Ch2_l2b0_cpu_wr_addr = `MCU2_L2IF0_CTL.l2if_wdq_wadr;
3429 wire dram_Ch2_l2b0_wdq_rd_en = `MCU2_DRIF_CTL.drif0_wdq_rd;
3430 wire [4:0] dram_Ch2_l2b0_wdq_radr = `MCU2_DRIF_CTL.drif0_wdq_radr;
3431
3432 wire dram_Ch2_l2b0_clspine_dram_txrd_sync = `MCU2_RDATA_CTL.rdata_cmp_ddr_sync_en;
3433 wire dram_Ch2_l2b0_clspine_dram_txwr_sync = `MCU2_RDATA_CTL.rdata_cmp_ddr_sync_en;
3434
3435// l2if wr entry valid ( for the actual data valid creation)
3436 wire [7:0] dram_Ch2_l2b0_l2if_wr_entry = {
3437 `MCU2_L2IF0_CTL.l2if_wr_entry7,
3438 `MCU2_L2IF0_CTL.l2if_wr_entry6,
3439 `MCU2_L2IF0_CTL.l2if_wr_entry5,
3440 `MCU2_L2IF0_CTL.l2if_wr_entry4,
3441 `MCU2_L2IF0_CTL.l2if_wr_entry3,
3442 `MCU2_L2IF0_CTL.l2if_wr_entry2,
3443 `MCU2_L2IF0_CTL.l2if_wr_entry1,
3444 `MCU2_L2IF0_CTL.l2if_wr_entry0
3445 };
3446
3447
3448
3449/* wire [8:0] dram_Ch2_l2b0_rd_adr_info_hi = {
3450 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3451 `MCU2_L2B0_ADRGEN_DP.addr_err,
3452 `MCU2_DRIF_CTL.drif_stack_adr,
3453 `MCU2_L2B0_ADRGEN_DP.rank_adr,
3454 `MCU2_L2B0_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3455 `MCU2_L2B0_ADRGEN_DP.bank_adr[1:0],
3456 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3457 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3458 };
3459
3460 wire [8:0] dram_Ch2_l2b0_wr_adr_info_hi = {
3461 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3462 `MCU2_L2B0_ADRGEN_DP.addr_err,
3463 `MCU2_DRIF_CTL.drif_stack_adr,
3464 `MCU2_L2B0_ADRGEN_DP.rank_adr,
3465 `MCU2_L2B0_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3466 `MCU2_L2B0_ADRGEN_DP.bank_adr[1:0],
3467 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3468 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3469 };
3470
3471 wire [8:0] dram_Ch2_l2b0_rd_adr_info_lo = {
3472 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3473 `MCU2_L2B0_ADRGEN_DP.addr_err,
3474 `MCU2_DRIF_CTL.drif_stack_adr,
3475 `MCU2_L2B0_ADRGEN_DP.rank_adr,
3476 `MCU2_L2B0_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3477 `MCU2_L2B0_ADRGEN_DP.bank_adr[1:0],
3478 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3479 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3480 };
3481
3482 wire [8:0] dram_Ch2_l2b0_wr_adr_info_lo = {
3483 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3484 `MCU2_L2B0_ADRGEN_DP.addr_err,
3485 `MCU2_DRIF_CTL.drif_stack_adr,
3486 `MCU2_L2B0_ADRGEN_DP.rank_adr,
3487 `MCU2_L2B0_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3488 `MCU2_L2B0_ADRGEN_DP.bank_adr[1:0],
3489 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3490 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3491 };*/
3492
3493
3494 wire dram_Ch2_l2b1_sctag_dram_rd_req = `MCU2_L2IF1_CTL.l2t_mcu_rd_req;
3495 wire [2:0] dram_Ch2_l2b1_sctag_dram_rd_req_id = `MCU2_L2IF1_CTL.l2t_mcu_rd_req_id;
3496// wire [39:6] dram_Ch2_l2b1_sctag_dram_addr = {`MCU2_ADDRDP_DP.l2t1_mcu_addr_39to9, `MCU2_ADDRDP_DP.l2t1_mcu_addr_6to4};
3497 wire [39:5] dram_Ch2_l2b1_sctag_dram_addr = `MCU2_L2IF1_CTL.l2t_mcu_addr;
3498 wire dram_Ch2_l2b1_sctag_dram_rd_dummy_req = `MCU2_L2IF1_CTL.l2t_mcu_rd_dummy_req;
3499 wire dram_Ch2_l2b1_dram_sctag_rd_ack = `MCU2_L2IF1_CTL.mcu_l2t_rd_ack;
3500 wire dram_Ch2_l2b1_sctag_dram_wr_req = `MCU2_L2IF1_CTL.l2t_mcu_wr_req;
3501 wire dram_Ch2_l2b1_sctag_dram_data_vld = `MCU2_L2IF1_CTL.l2b_mcu_data_vld;
3502 wire [63:0] dram_Ch2_l2b1_sctag_dram_wr_data = `MCU2_L2RDMX_DP.l2b1_mcu_wr_data_r5;
3503 wire dram_Ch2_l2b1_dram_sctag_wr_ack = `MCU2_L2IF1_CTL.mcu_l2t_wr_ack;
3504 wire dram_Ch2_l2b1_dram_sctag_data_vld = `MCU2_RDATA_CTL.mcu_l2t1_data_vld_r0;
3505 wire [2:0] dram_Ch2_l2b1_dram_sctag_rd_req_id = `MCU2_RDATA_CTL.mcu_l2t1_rd_req_id_r0;
3506
3507// MAQ N2 doesn't support wire [3:0] dram_Ch2_l2if_b0_rd_val = `DRAM_L2IF2.l2if_b0_rd_val;
3508// MAQ N2 doesn't support wire [3:0] dram_Ch2_l2if_b1_rd_val = `DRAM_L2IF2.l2if_b1_rd_val;
3509 wire [3:0] dram_Ch2_l2b1_l2if_b0_wr_val = {`MCU2_L2IF1_CTL.l2if_wr_entry3,
3510 `MCU2_L2IF1_CTL.l2if_wr_entry2,
3511 `MCU2_L2IF1_CTL.l2if_wr_entry1,
3512 `MCU2_L2IF1_CTL.l2if_wr_entry0};
3513
3514 wire [3:0] dram_Ch2_l2b1_l2if_b1_wr_val = {`MCU2_L2IF1_CTL.l2if_wr_entry7,
3515 `MCU2_L2IF1_CTL.l2if_wr_entry6,
3516 `MCU2_L2IF1_CTL.l2if_wr_entry5,
3517 `MCU2_L2IF1_CTL.l2if_wr_entry4};
3518
3519// MAQ wire [5:0] dram_Ch2_l2b1_l2if_wr_b0_data_addr = `MCU2_L2IF1_CTL.l2if_wdq_wadr;
3520
3521 // Signals on L2 Interface that indicates Error
3522 wire dram_Ch2_l2b1_dram_sctag_secc_err = `MCU2_RDATA_CTL.mcu_l2t1_secc_err_r3;
3523 wire dram_Ch2_l2b1_dram_sctag_pa_err = `MCU2_L2RDMX_DP.l2b1_rd_addr_err | `MCU2_L2RDMX_DP.l2b1_wr_addr_err;
3524 wire dram_Ch2_l2b1_dram_sctag_mecc_err = `MCU2_RDATA_CTL.mcu_l2t1_mecc_err_r3;
3525 wire dram_Ch2_l2b1_dram_sctag_scb_secc_err = `MCU2_RDATA_CTL.mcu_l2t1_scb_secc_err;
3526 wire dram_Ch2_l2b1_dram_sctag_scb_mecc_err = `MCU2_RDATA_CTL.mcu_l2t1_scb_mecc_err;
3527
3528// qualified with vld since they can be on due to residual ( previous error )
3529/* wire dram_Ch2_l2b1_l2if_secc_err = `MCU2_RDATA_CTL.mcu_l2t1_secc_err_r3 &&
3530 (`MCU2_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
3531 `MCU2_RDPCTL_CTL.rdpctl_scrub_data_valid);
3532
3533 wire dram_Ch2_l2b1_l2if_mecc_err_partial = `MCU2_RDATA_CTL.mcu_l2t1_mecc_err_r3 &&
3534 (`MCU2_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
3535 `MCU2_RDPCTL_CTL.rdpctl_scrub_data_valid);
3536*/
3537 wire dram_Ch2_l2b1_l2if_secc_err = `MCU2_RDATA_CTL.mcu_l2t1_scb_secc_err_in ||
3538 `MCU2_RDATA_CTL.mcu_l2t1_secc_err_r1;
3539 wire dram_Ch2_l2b1_l2if_mecc_err_partial = `MCU2_RDATA_CTL.mcu_l2t1_scb_mecc_err_in ||
3540 `MCU2_RDATA_CTL.mcu_l2t1_mecc_err_r1;
3541 wire dram_Ch2_l2b1_l2if_pa_err = (`MCU2_L2RDMX_DP.l2b1_rd_addr_err || `MCU2_L2RDMX_DP.l2b1_wr_addr_err) &&
3542 `MCU2_RDATA_CTL.mcu_l2t1_data_vld_r0;
3543
3544 wire [1:0] dram_Ch2_l2b1_cpu_wr_en = `MCU2_L2IF1_CTL.l2if_wdq_we;
3545 wire [4:0] dram_Ch2_l2b1_cpu_wr_addr = `MCU2_L2IF1_CTL.l2if_wdq_wadr;
3546 wire dram_Ch2_l2b1_wdq_rd_en = `MCU2_DRIF_CTL.drif1_wdq_rd;
3547 wire [4:0] dram_Ch2_l2b1_wdq_radr = `MCU2_DRIF_CTL.drif1_wdq_radr;
3548
3549 wire dram_Ch2_l2b1_clspine_dram_txrd_sync = `MCU2_RDATA_CTL.rdata_cmp_ddr_sync_en;
3550 wire dram_Ch2_l2b1_clspine_dram_txwr_sync = `MCU2_RDATA_CTL.rdata_cmp_ddr_sync_en;
3551
3552// l2if wr entry valid ( for the actual data valid creation)
3553 wire [7:0] dram_Ch2_l2b1_l2if_wr_entry = {
3554 `MCU2_L2IF1_CTL.l2if_wr_entry7,
3555 `MCU2_L2IF1_CTL.l2if_wr_entry6,
3556 `MCU2_L2IF1_CTL.l2if_wr_entry5,
3557 `MCU2_L2IF1_CTL.l2if_wr_entry4,
3558 `MCU2_L2IF1_CTL.l2if_wr_entry3,
3559 `MCU2_L2IF1_CTL.l2if_wr_entry2,
3560 `MCU2_L2IF1_CTL.l2if_wr_entry1,
3561 `MCU2_L2IF1_CTL.l2if_wr_entry0
3562 };
3563
3564
3565
3566/* wire [8:0] dram_Ch2_l2b1_rd_adr_info_hi = {
3567 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3568 `MCU2_L2B1_ADRGEN_DP.addr_err,
3569 `MCU2_DRIF_CTL.drif_stack_adr,
3570 `MCU2_L2B1_ADRGEN_DP.rank_adr,
3571 `MCU2_L2B1_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3572 `MCU2_L2B1_ADRGEN_DP.bank_adr[1:0],
3573 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3574 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3575 };
3576
3577 wire [8:0] dram_Ch2_l2b1_wr_adr_info_hi = {
3578 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3579 `MCU2_L2B1_ADRGEN_DP.addr_err,
3580 `MCU2_DRIF_CTL.drif_stack_adr,
3581 `MCU2_L2B1_ADRGEN_DP.rank_adr,
3582 `MCU2_L2B1_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3583 `MCU2_L2B1_ADRGEN_DP.bank_adr[1:0],
3584 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3585 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3586 };
3587
3588 wire [8:0] dram_Ch2_l2b1_rd_adr_info_lo = {
3589 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3590 `MCU2_L2B1_ADRGEN_DP.addr_err,
3591 `MCU2_DRIF_CTL.drif_stack_adr,
3592 `MCU2_L2B1_ADRGEN_DP.rank_adr,
3593 `MCU2_L2B1_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3594 `MCU2_L2B1_ADRGEN_DP.bank_adr[1:0],
3595 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3596 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3597 };
3598
3599 wire [8:0] dram_Ch2_l2b1_wr_adr_info_lo = {
3600 `MCU2_DRIF_CTL.drif_addr_bank_low_sel,
3601 `MCU2_L2B1_ADRGEN_DP.addr_err,
3602 `MCU2_DRIF_CTL.drif_stack_adr,
3603 `MCU2_L2B1_ADRGEN_DP.rank_adr,
3604 `MCU2_L2B1_ADRGEN_DP.bank_adr[2] && `MCU2_DRIF_CTL.drif_eight_bank_mode,
3605 `MCU2_L2B1_ADRGEN_DP.bank_adr[1:0],
3606 `MCU2_DRIF_CTL.drif_eight_bank_mode,
3607 1'b0 // `DRAM_L2IF2.dram_rd_addr_gen_hi.two_channel_mode
3608 };*/
3609
3610
3611
3612// ---- Performance counters ----
3613
3614 wire [7:0] dram_Ch2_perf_cntl = `MCU2_DRIF_CTL.drif_perf_cntl_reg;
3615 wire dram_Ch2_cnt0_sticky_bit = `MCU2_DRIF_CTL.drif_perf_cnt0_reg[31];
3616 wire dram_Ch2_cnt1_sticky_bit = `MCU2_DRIF_CTL.drif_perf_cnt1_reg[31];
3617
3618 // read que request
3619 wire dram_Ch3_l2b0_rd_req = `MCU3_L2IF0_CTL.l2t_mcu_rd_req;
3620 wire [2:0] dram_Ch3_l2b0_rd_id = `MCU3_L2IF0_CTL.l2t_mcu_rd_req_id[2:0];
3621 wire dram_Ch3_l2b0_errq_vld = (!`MCU3_DRIF_CTL.drif_err_fifo_empty) & (`MCU3_DRIF_CTL.rdpctl_err_fifo_data[0] == 0) ;
3622 wire [2:0] dram_Ch3_l2b0_errq_id = `MCU3_DRIF_CTL.rdpctl_err_fifo_data[4:2];
3623 // read que
3624 wire dram_ch3_l2b0_rd_q_vld_0 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3625 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3626 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3627 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3628 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3629 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3630 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) |
3631 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0])) };
3632
3633 wire dram_ch3_l2b0_rd_q_vld_1 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3634 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3635 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3636 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3637 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3638 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3639 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) |
3640 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1])) };
3641
3642 wire dram_ch3_l2b0_rd_q_vld_2 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3643 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3644 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3645 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3646 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3647 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3648 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) |
3649 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2])) };
3650
3651 wire dram_ch3_l2b0_rd_q_vld_3 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3652 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3653 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3654 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3655 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3656 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3657 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) |
3658 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3])) };
3659
3660 wire dram_ch3_l2b0_rd_q_vld_4 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3661 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3662 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3663 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3664 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3665 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3666 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) |
3667 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4])) };
3668
3669 wire dram_ch3_l2b0_rd_q_vld_5 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3670 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3671 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3672 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3673 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3674 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3675 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) |
3676 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5])) };
3677
3678 wire dram_ch3_l2b0_rd_q_vld_6 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3679 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3680 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3681 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3682 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3683 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3684 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) |
3685 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6])) };
3686
3687 wire dram_ch3_l2b0_rd_q_vld_7 = { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3688 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3689 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3690 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3691 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3692 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3693 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) |
3694 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7])) };
3695
3696 wire [7:0] dram_ch3_l2b0_rd_q_valids = {dram_ch3_l2b0_rd_q_vld_7, dram_ch3_l2b0_rd_q_vld_6, dram_ch3_l2b0_rd_q_vld_5, dram_ch3_l2b0_rd_q_vld_4,
3697 dram_ch3_l2b0_rd_q_vld_3, dram_ch3_l2b0_rd_q_vld_2, dram_ch3_l2b0_rd_q_vld_1, dram_ch3_l2b0_rd_q_vld_0};
3698
3699// Read request Q PA-Error
3700 wire dram_ch3_l2b0_rd_q_addr_err_0 =
3701 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3702 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3703 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3704 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3705 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3706 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3707 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3708 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3709
3710 wire dram_ch3_l2b0_rd_q_addr_err_1 =
3711 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3712 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3713 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3714 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3715 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3716 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3717 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3718 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) };
3719
3720 wire dram_ch3_l2b0_rd_q_addr_err_2 =
3721 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3722 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3723 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3724 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3725 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3726 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3727 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3728 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3729
3730 wire dram_ch3_l2b0_rd_q_addr_err_3 =
3731 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3732 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3733 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3734 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3735 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3736 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3737 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3738 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3739
3740 wire dram_ch3_l2b0_rd_q_addr_err_4 =
3741 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3742 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3743 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3744 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3745 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3746 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3747 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3748 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3749
3750 wire dram_ch3_l2b0_rd_q_addr_err_5 =
3751 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3752 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3753 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3754 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3755 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3756 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3757 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3758 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3759
3760 wire dram_ch3_l2b0_rd_q_addr_err_6 =
3761 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3762 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3763 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3764 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3765 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3766 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3767 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3768 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3769
3770 wire dram_ch3_l2b0_rd_q_addr_err_7 =
3771 { ((`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent0[7]) |
3772 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent1[7]) |
3773 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent2[7]) |
3774 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent3[7]) |
3775 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent4[7]) |
3776 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent5[7]) |
3777 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent6[7]) |
3778 ((`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU3_DRQ0_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ0_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ0_CTL.drq_rd_queue_ent7[7]) };
3779
3780 wire [7:0] dram_ch3_l2b0_rd_q_addr_err = {dram_ch3_l2b0_rd_q_addr_err_7, dram_ch3_l2b0_rd_q_addr_err_6, dram_ch3_l2b0_rd_q_addr_err_5, dram_ch3_l2b0_rd_q_addr_err_4,
3781 dram_ch3_l2b0_rd_q_addr_err_3, dram_ch3_l2b0_rd_q_addr_err_2, dram_ch3_l2b0_rd_q_addr_err_1, dram_ch3_l2b0_rd_q_addr_err_0};
3782
3783 wire [7:0] dram_ch3_l2b0_drq_rd_queue_valid = {`MCU3_DRQ0_CTL.drq_rd_queue_valid[7:0]};
3784 wire [3:0] dram_ch3_l2b0_drq_read_queue_cnt = {`MCU3_DRQ0_CTL.drq_read_queue_cnt[3:0]};
3785
3786// Read request Q PA-Error
3787
3788 wire [39:0] dram_Ch3_l2b0_rd_q_0 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[0],
3789 `MCU3_L2B0_ADR_Q.rd_req_id_queue0[2:0],
3790 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue0[3:0],
3791 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue0[2:0],
3792 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue0[14:0],
3793 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue0[10:0],
3794 3'b0 };
3795
3796 wire [39:0] dram_Ch3_l2b0_rd_q_1 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[1],
3797 `MCU3_L2B0_ADR_Q.rd_req_id_queue1[2:0],
3798 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue1[3:0],
3799 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue1[2:0],
3800 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue1[14:0],
3801 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue1[10:0],
3802 3'b0 };
3803
3804 wire [39:0] dram_Ch3_l2b0_rd_q_2 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[2],
3805 `MCU3_L2B0_ADR_Q.rd_req_id_queue2[2:0],
3806 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue2[3:0],
3807 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue2[2:0],
3808 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue2[14:0],
3809 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue2[10:0],
3810 3'b0 };
3811
3812 wire [39:0] dram_Ch3_l2b0_rd_q_3 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[3],
3813 `MCU3_L2B0_ADR_Q.rd_req_id_queue3[2:0],
3814 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue3[3:0],
3815 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue3[2:0],
3816 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue3[14:0],
3817 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue3[10:0],
3818 3'b0 };
3819
3820 wire [39:0] dram_Ch3_l2b0_rd_q_4 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[4],
3821 `MCU3_L2B0_ADR_Q.rd_req_id_queue4[2:0],
3822 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue4[3:0],
3823 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue4[2:0],
3824 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue4[14:0],
3825 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue4[10:0],
3826 3'b0 };
3827
3828 wire [39:0] dram_Ch3_l2b0_rd_q_5 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[5],
3829 `MCU3_L2B0_ADR_Q.rd_req_id_queue5[2:0],
3830 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue5[3:0],
3831 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue5[2:0],
3832 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue5[14:0],
3833 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue5[10:0],
3834 3'b0 };
3835
3836 wire [39:0] dram_Ch3_l2b0_rd_q_6 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[6],
3837 `MCU3_L2B0_ADR_Q.rd_req_id_queue6[2:0],
3838 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue6[3:0],
3839 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue6[2:0],
3840 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue6[14:0],
3841 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue6[10:0],
3842 3'b0 };
3843
3844 wire [39:0] dram_Ch3_l2b0_rd_q_7 = {`MCU3_DRQ0_CTL.drq_rdbuf_valids[7],
3845 `MCU3_L2B0_ADR_Q.rd_req_id_queue7[2:0],
3846 `MCU3_L2B0_ADR_Q.rank_rd_adr_queue7[3:0],
3847 `MCU3_L2B0_ADR_Q.bank_rd_adr_queue7[2:0],
3848 `MCU3_L2B0_ADR_Q.ras_rd_adr_queue7[14:0],
3849 `MCU3_L2B0_ADR_Q.cas_rd_adr_queue7[10:0],
3850 3'b0 };
3851
3852
3853 reg [39:0] dram_Ch3_l2b0_rd_q[7:0];
3854 // read que collapsing fifo
3855 wire [11:0] dram_Ch3_l2b0_rd_colps_q_0 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent0[11:0]};
3856 wire [11:0] dram_Ch3_l2b0_rd_colps_q_1 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent1[11:0]};
3857 wire [11:0] dram_Ch3_l2b0_rd_colps_q_2 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent2[11:0]};
3858 wire [11:0] dram_Ch3_l2b0_rd_colps_q_3 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent3[11:0]};
3859 wire [11:0] dram_Ch3_l2b0_rd_colps_q_4 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent4[11:0]};
3860 wire [11:0] dram_Ch3_l2b0_rd_colps_q_5 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent5[11:0]};
3861 wire [11:0] dram_Ch3_l2b0_rd_colps_q_6 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent6[11:0]};
3862 wire [11:0] dram_Ch3_l2b0_rd_colps_q_7 = {`MCU3_DRQ0_CTL.drq_rd_queue_ent7[11:0]};
3863
3864 reg [11:0] dram_Ch3_l2b0_rd_colps_q[7:0];
3865
3866 // read que write pointer
3867 wire [7:0] dram_Ch3_l2b0_rd_que_wr_ptr = {`MCU3_DRQ0_CTL.drq_rd_adr_queue7_en,
3868 `MCU3_DRQ0_CTL.drq_rd_adr_queue6_en,
3869 `MCU3_DRQ0_CTL.drq_rd_adr_queue5_en,
3870 `MCU3_DRQ0_CTL.drq_rd_adr_queue4_en,
3871 `MCU3_DRQ0_CTL.drq_rd_adr_queue3_en,
3872 `MCU3_DRQ0_CTL.drq_rd_adr_queue2_en,
3873 `MCU3_DRQ0_CTL.drq_rd_adr_queue1_en,
3874 `MCU3_DRQ0_CTL.drq_rd_adr_queue0_en};
3875 // read que read pointer
3876 wire [7:0] dram_Ch3_l2b0_rd_que_rd_ptr = {`MCU3_DRQ0_CTL.rdpctl_drq_clear_ent[7:0]};
3877
3878 // write que request
3879 wire dram_Ch3_l2b0_wr_req = `MCU3_L2IF0_CTL.l2t_mcu_wr_req;
3880 wire [2:0] dram_Ch3_l2b0_wr_addr = `MCU3_L2IF0_CTL.l2if_data_wr_addr;
3881
3882 wire [7:0] dram_ch3_l2b0_wr_q_valids = {`MCU3_DRQ0_CTL.drq_wr_queue_valid[7:0]};
3883 wire [3:0] dram_ch3_l2b0_drq_write_queue_cnt = {`MCU3_DRQ0_CTL.drq_write_queue_cnt[3:0]};
3884
3885 wire [40:0] dram_Ch3_l2b0_wr_q_0 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[0],
3886 `MCU3_DRQ0_CTL.drq_wrbuf_valids[0], //`DRAM_PATH3.writeqbank0vld0_arb,
3887 `MCU3_DRQ0_CTL.drq_wr_queue_ent0[11:9],
3888 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue0[3:0],
3889 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue0[2:0],
3890 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue0[14:0],
3891 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue0[10:0],
3892 3'b0};
3893
3894 wire [40:0] dram_Ch3_l2b0_wr_q_1 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[1],
3895 `MCU3_DRQ0_CTL.drq_wrbuf_valids[1], //`DRAM_PATH3.writeqbank0vld0_arb,
3896 `MCU3_DRQ0_CTL.drq_wr_queue_ent1[11:9],
3897 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue1[3:0],
3898 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue1[2:0],
3899 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue1[14:0],
3900 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue1[10:0],
3901 3'b0};
3902
3903 wire [40:0] dram_Ch3_l2b0_wr_q_2 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[2],
3904 `MCU3_DRQ0_CTL.drq_wrbuf_valids[2], //`DRAM_PATH3.writeqbank0vld0_arb,
3905 `MCU3_DRQ0_CTL.drq_wr_queue_ent2[11:9],
3906 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue2[3:0],
3907 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue2[2:0],
3908 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue2[14:0],
3909 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue2[10:0],
3910 3'b0};
3911
3912 wire [40:0] dram_Ch3_l2b0_wr_q_3 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[3],
3913 `MCU3_DRQ0_CTL.drq_wrbuf_valids[3], //`DRAM_PATH3.writeqbank0vld0_arb,
3914 `MCU3_DRQ0_CTL.drq_wr_queue_ent3[11:9],
3915 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue3[3:0],
3916 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue3[2:0],
3917 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue3[14:0],
3918 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue3[10:0],
3919 3'b0};
3920
3921 wire [40:0] dram_Ch3_l2b0_wr_q_4 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[4],
3922 `MCU3_DRQ0_CTL.drq_wrbuf_valids[4], //`DRAM_PATH3.writeqbank0vld0_arb,
3923 `MCU3_DRQ0_CTL.drq_wr_queue_ent4[11:9],
3924 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue4[3:0],
3925 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue4[2:0],
3926 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue4[14:0],
3927 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue4[10:0],
3928 3'b0};
3929
3930 wire [40:0] dram_Ch3_l2b0_wr_q_5 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[5],
3931 `MCU3_DRQ0_CTL.drq_wrbuf_valids[5], //`DRAM_PATH3.writeqbank0vld0_arb,
3932 `MCU3_DRQ0_CTL.drq_wr_queue_ent5[11:9],
3933 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue5[3:0],
3934 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue5[2:0],
3935 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue5[14:0],
3936 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue5[10:0],
3937 3'b0};
3938
3939 wire [40:0] dram_Ch3_l2b0_wr_q_6 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[6],
3940 `MCU3_DRQ0_CTL.drq_wrbuf_valids[6], //`DRAM_PATH3.writeqbank0vld0_arb,
3941 `MCU3_DRQ0_CTL.drq_wr_queue_ent6[11:9],
3942 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue6[3:0],
3943 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue6[2:0],
3944 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue6[14:0],
3945 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue6[10:0],
3946 3'b0};
3947
3948 wire [40:0] dram_Ch3_l2b0_wr_q_7 = {`MCU3_DRQ0_CTL.drq_wrbuf_valids[7],
3949 `MCU3_DRQ0_CTL.drq_wrbuf_valids[7], //`DRAM_PATH3.writeqbank0vld0_arb,
3950 `MCU3_DRQ0_CTL.drq_wr_queue_ent7[11:9],
3951 `MCU3_L2B0_ADR_Q.rank_wr_adr_queue7[3:0],
3952 `MCU3_L2B0_ADR_Q.bank_wr_adr_queue7[2:0],
3953 `MCU3_L2B0_ADR_Q.ras_wr_adr_queue7[14:0],
3954 `MCU3_L2B0_ADR_Q.cas_wr_adr_queue7[10:0],
3955 3'b0};
3956
3957 reg [40:0] dram_Ch3_l2b0_wr_q[7:0];
3958
3959 // to not set valid for the fifo monitor
3960 wire dram_Ch3_l2b0_pa_err = `MCU3_L2RDMX_DP.l2b0_wr_addr_err;
3961
3962 // write que collapsing fifo
3963 wire [14:0] dram_Ch3_l2b0_wr_colps_q_0 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent0[14:0]};
3964 wire [14:0] dram_Ch3_l2b0_wr_colps_q_1 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent1[14:0]};
3965 wire [14:0] dram_Ch3_l2b0_wr_colps_q_2 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent2[14:0]};
3966 wire [14:0] dram_Ch3_l2b0_wr_colps_q_3 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent3[14:0]};
3967 wire [14:0] dram_Ch3_l2b0_wr_colps_q_4 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent4[14:0]};
3968 wire [14:0] dram_Ch3_l2b0_wr_colps_q_5 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent5[14:0]};
3969 wire [14:0] dram_Ch3_l2b0_wr_colps_q_6 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent6[14:0]};
3970 wire [14:0] dram_Ch3_l2b0_wr_colps_q_7 = {`MCU3_DRQ0_CTL.drq_wr_queue_ent7[14:0]};
3971
3972 reg [14:0] dram_Ch3_l2b0_wr_colps_q[7:0];
3973
3974 // write que write pointer
3975 wire [7:0] dram_Ch3_l2b0_wr_que_wr_ptr = {`MCU3_DRQ0_CTL.drq_wr_adr_queue7_en,
3976 `MCU3_DRQ0_CTL.drq_wr_adr_queue6_en,
3977 `MCU3_DRQ0_CTL.drq_wr_adr_queue5_en,
3978 `MCU3_DRQ0_CTL.drq_wr_adr_queue4_en,
3979 `MCU3_DRQ0_CTL.drq_wr_adr_queue3_en,
3980 `MCU3_DRQ0_CTL.drq_wr_adr_queue2_en,
3981 `MCU3_DRQ0_CTL.drq_wr_adr_queue1_en,
3982 `MCU3_DRQ0_CTL.drq_wr_adr_queue0_en};
3983
3984 // write que arb read pointer
3985
3986 // write que data read pointer
3987 /*wire [7:0] dram_Ch3_l2b0_wr_que_rd_ptr = {`MCU3_DRQ0_CTL.drq_wr_entry7_rank,
3988 `MCU3_DRQ0_CTL.drq_wr_entry6_rank,
3989 `MCU3_DRQ0_CTL.drq_wr_entry5_rank,
3990 `MCU3_DRQ0_CTL.drq_wr_entry4_rank,
3991 `MCU3_DRQ0_CTL.drq_wr_entry3_rank,
3992 `MCU3_DRQ0_CTL.drq_wr_entry2_rank,
3993 `MCU3_DRQ0_CTL.drq_wr_entry1_rank,
3994 `MCU3_DRQ0_CTL.drq_wr_entry0_rank};*/
3995 wire [7:0] dram_Ch3_l2b0_wr_que_rd_ptr = `MCU3_DRQ0_CTL.drq_wrq_clear_ent;
3996
3997
3998// These signals are currently not used in cov obj
3999// enable for 8 deep collps rd fifo
4000 wire [7:0] dram_Ch3_l2b0_que_b0_index_en = {`MCU3_L2B0_ADR_Q.rd_adr_queue_sel[7:0]};
4001
4002
4003// These signals are currently not used in cov obj
4004// enable for 8 deep collps wr fifo
4005 wire [7:0] dram_Ch3_l2b0_que_b0_wr_index_en= {`MCU3_L2B0_ADR_Q.wr_adr_queue_sel[7:0]};
4006
4007// These signals are currently not used in cov obj
4008// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
4009 wire [7:0] dram_Ch3_l2b0_que_b0_rd_in_val = `MCU3_DRQ0_CTL.drq_rd_entry0_val[7:0];
4010
4011 wire dram_Ch3_que_b0_rd_picked = `MCU3_DRIF_CTL.drif0_rd_picked;
4012 wire dram_Ch3_que_b0_wr_picked = `MCU3_DRIF_CTL.drif0_wr_picked;
4013 // read que request
4014 wire dram_Ch3_l2b1_rd_req = `MCU3_L2IF1_CTL.l2t_mcu_rd_req;
4015 wire [2:0] dram_Ch3_l2b1_rd_id = `MCU3_L2IF1_CTL.l2t_mcu_rd_req_id[2:0];
4016 wire dram_Ch3_l2b1_errq_vld = (!`MCU3_DRIF_CTL.drif_err_fifo_empty) & (`MCU3_DRIF_CTL.rdpctl_err_fifo_data[0] == 1) ;
4017 wire [2:0] dram_Ch3_l2b1_errq_id = `MCU3_DRIF_CTL.rdpctl_err_fifo_data[4:2];
4018 // read que
4019 wire dram_ch3_l2b1_rd_q_vld_0 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4020 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4021 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4022 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4023 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4024 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4025 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) |
4026 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0])) };
4027
4028 wire dram_ch3_l2b1_rd_q_vld_1 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4029 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4030 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4031 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4032 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4033 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4034 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) |
4035 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1])) };
4036
4037 wire dram_ch3_l2b1_rd_q_vld_2 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4038 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4039 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4040 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4041 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4042 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4043 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) |
4044 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2])) };
4045
4046 wire dram_ch3_l2b1_rd_q_vld_3 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4047 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4048 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4049 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4050 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4051 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4052 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) |
4053 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3])) };
4054
4055 wire dram_ch3_l2b1_rd_q_vld_4 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4056 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4057 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4058 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4059 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4060 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4061 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) |
4062 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4])) };
4063
4064 wire dram_ch3_l2b1_rd_q_vld_5 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4065 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4066 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4067 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4068 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4069 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4070 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) |
4071 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5])) };
4072
4073 wire dram_ch3_l2b1_rd_q_vld_6 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4074 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4075 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4076 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4077 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4078 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4079 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) |
4080 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6])) };
4081
4082 wire dram_ch3_l2b1_rd_q_vld_7 = { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4083 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4084 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4085 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4086 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4087 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4088 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) |
4089 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7])) };
4090
4091 wire [7:0] dram_ch3_l2b1_rd_q_valids = {dram_ch3_l2b1_rd_q_vld_7, dram_ch3_l2b1_rd_q_vld_6, dram_ch3_l2b1_rd_q_vld_5, dram_ch3_l2b1_rd_q_vld_4,
4092 dram_ch3_l2b1_rd_q_vld_3, dram_ch3_l2b1_rd_q_vld_2, dram_ch3_l2b1_rd_q_vld_1, dram_ch3_l2b1_rd_q_vld_0};
4093
4094// Read request Q PA-Error
4095 wire dram_ch3_l2b1_rd_q_addr_err_0 =
4096 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4097 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4098 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4099 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4100 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4101 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4102 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4103 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h0) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[0]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4104
4105 wire dram_ch3_l2b1_rd_q_addr_err_1 =
4106 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4107 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4108 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4109 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4110 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4111 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4112 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4113 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h1) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[1]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) };
4114
4115 wire dram_ch3_l2b1_rd_q_addr_err_2 =
4116 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4117 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4118 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4119 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4120 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4121 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4122 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4123 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h2) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[2]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4124
4125 wire dram_ch3_l2b1_rd_q_addr_err_3 =
4126 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4127 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4128 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4129 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4130 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4131 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4132 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4133 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h3) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[3]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4134
4135 wire dram_ch3_l2b1_rd_q_addr_err_4 =
4136 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4137 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4138 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4139 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4140 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4141 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4142 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4143 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h4) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[4]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4144
4145 wire dram_ch3_l2b1_rd_q_addr_err_5 =
4146 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4147 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4148 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4149 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4150 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4151 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4152 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4153 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h5) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[5]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4154
4155 wire dram_ch3_l2b1_rd_q_addr_err_6 =
4156 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4157 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4158 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4159 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4160 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4161 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4162 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4163 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h6) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[6]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4164
4165 wire dram_ch3_l2b1_rd_q_addr_err_7 =
4166 { ((`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[0]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent0[7]) |
4167 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[1]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent1[7]) |
4168 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[2]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent2[7]) |
4169 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[3]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent3[7]) |
4170 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[4]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent4[7]) |
4171 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[5]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent5[7]) |
4172 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[6]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent6[7]) |
4173 ((`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:9] == 3'h7) & (`MCU3_DRQ1_CTL.drq_rd_queue_valid[7]) & (`MCU3_DRQ1_CTL.drq_rdbuf_valids[7]) & `MCU3_DRQ1_CTL.drq_rd_queue_ent7[7]) };
4174
4175 wire [7:0] dram_ch3_l2b1_rd_q_addr_err = {dram_ch3_l2b1_rd_q_addr_err_7, dram_ch3_l2b1_rd_q_addr_err_6, dram_ch3_l2b1_rd_q_addr_err_5, dram_ch3_l2b1_rd_q_addr_err_4,
4176 dram_ch3_l2b1_rd_q_addr_err_3, dram_ch3_l2b1_rd_q_addr_err_2, dram_ch3_l2b1_rd_q_addr_err_1, dram_ch3_l2b1_rd_q_addr_err_0};
4177
4178 wire [7:0] dram_ch3_l2b1_drq_rd_queue_valid = {`MCU3_DRQ1_CTL.drq_rd_queue_valid[7:0]};
4179 wire [3:0] dram_ch3_l2b1_drq_read_queue_cnt = {`MCU3_DRQ1_CTL.drq_read_queue_cnt[3:0]};
4180
4181// Read request Q PA-Error
4182
4183 wire [39:0] dram_Ch3_l2b1_rd_q_0 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[0],
4184 `MCU3_L2B1_ADR_Q.rd_req_id_queue0[2:0],
4185 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue0[3:0],
4186 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue0[2:0],
4187 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue0[14:0],
4188 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue0[10:0],
4189 3'b0 };
4190
4191 wire [39:0] dram_Ch3_l2b1_rd_q_1 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[1],
4192 `MCU3_L2B1_ADR_Q.rd_req_id_queue1[2:0],
4193 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue1[3:0],
4194 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue1[2:0],
4195 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue1[14:0],
4196 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue1[10:0],
4197 3'b0 };
4198
4199 wire [39:0] dram_Ch3_l2b1_rd_q_2 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[2],
4200 `MCU3_L2B1_ADR_Q.rd_req_id_queue2[2:0],
4201 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue2[3:0],
4202 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue2[2:0],
4203 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue2[14:0],
4204 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue2[10:0],
4205 3'b0 };
4206
4207 wire [39:0] dram_Ch3_l2b1_rd_q_3 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[3],
4208 `MCU3_L2B1_ADR_Q.rd_req_id_queue3[2:0],
4209 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue3[3:0],
4210 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue3[2:0],
4211 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue3[14:0],
4212 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue3[10:0],
4213 3'b0 };
4214
4215 wire [39:0] dram_Ch3_l2b1_rd_q_4 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[4],
4216 `MCU3_L2B1_ADR_Q.rd_req_id_queue4[2:0],
4217 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue4[3:0],
4218 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue4[2:0],
4219 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue4[14:0],
4220 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue4[10:0],
4221 3'b0 };
4222
4223 wire [39:0] dram_Ch3_l2b1_rd_q_5 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[5],
4224 `MCU3_L2B1_ADR_Q.rd_req_id_queue5[2:0],
4225 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue5[3:0],
4226 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue5[2:0],
4227 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue5[14:0],
4228 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue5[10:0],
4229 3'b0 };
4230
4231 wire [39:0] dram_Ch3_l2b1_rd_q_6 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[6],
4232 `MCU3_L2B1_ADR_Q.rd_req_id_queue6[2:0],
4233 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue6[3:0],
4234 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue6[2:0],
4235 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue6[14:0],
4236 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue6[10:0],
4237 3'b0 };
4238
4239 wire [39:0] dram_Ch3_l2b1_rd_q_7 = {`MCU3_DRQ1_CTL.drq_rdbuf_valids[7],
4240 `MCU3_L2B1_ADR_Q.rd_req_id_queue7[2:0],
4241 `MCU3_L2B1_ADR_Q.rank_rd_adr_queue7[3:0],
4242 `MCU3_L2B1_ADR_Q.bank_rd_adr_queue7[2:0],
4243 `MCU3_L2B1_ADR_Q.ras_rd_adr_queue7[14:0],
4244 `MCU3_L2B1_ADR_Q.cas_rd_adr_queue7[10:0],
4245 3'b0 };
4246
4247
4248 reg [39:0] dram_Ch3_l2b1_rd_q[7:0];
4249 // read que collapsing fifo
4250 wire [11:0] dram_Ch3_l2b1_rd_colps_q_0 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent0[11:0]};
4251 wire [11:0] dram_Ch3_l2b1_rd_colps_q_1 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent1[11:0]};
4252 wire [11:0] dram_Ch3_l2b1_rd_colps_q_2 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent2[11:0]};
4253 wire [11:0] dram_Ch3_l2b1_rd_colps_q_3 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent3[11:0]};
4254 wire [11:0] dram_Ch3_l2b1_rd_colps_q_4 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent4[11:0]};
4255 wire [11:0] dram_Ch3_l2b1_rd_colps_q_5 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent5[11:0]};
4256 wire [11:0] dram_Ch3_l2b1_rd_colps_q_6 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent6[11:0]};
4257 wire [11:0] dram_Ch3_l2b1_rd_colps_q_7 = {`MCU3_DRQ1_CTL.drq_rd_queue_ent7[11:0]};
4258
4259 reg [11:0] dram_Ch3_l2b1_rd_colps_q[7:0];
4260
4261 // read que write pointer
4262 wire [7:0] dram_Ch3_l2b1_rd_que_wr_ptr = {`MCU3_DRQ1_CTL.drq_rd_adr_queue7_en,
4263 `MCU3_DRQ1_CTL.drq_rd_adr_queue6_en,
4264 `MCU3_DRQ1_CTL.drq_rd_adr_queue5_en,
4265 `MCU3_DRQ1_CTL.drq_rd_adr_queue4_en,
4266 `MCU3_DRQ1_CTL.drq_rd_adr_queue3_en,
4267 `MCU3_DRQ1_CTL.drq_rd_adr_queue2_en,
4268 `MCU3_DRQ1_CTL.drq_rd_adr_queue1_en,
4269 `MCU3_DRQ1_CTL.drq_rd_adr_queue0_en};
4270 // read que read pointer
4271 wire [7:0] dram_Ch3_l2b1_rd_que_rd_ptr = {`MCU3_DRQ1_CTL.rdpctl_drq_clear_ent[7:0]};
4272
4273 // write que request
4274 wire dram_Ch3_l2b1_wr_req = `MCU3_L2IF1_CTL.l2t_mcu_wr_req;
4275 wire [2:0] dram_Ch3_l2b1_wr_addr = `MCU3_L2IF1_CTL.l2if_data_wr_addr;
4276
4277 wire [7:0] dram_ch3_l2b1_wr_q_valids = {`MCU3_DRQ1_CTL.drq_wr_queue_valid[7:0]};
4278 wire [3:0] dram_ch3_l2b1_drq_write_queue_cnt = {`MCU3_DRQ1_CTL.drq_write_queue_cnt[3:0]};
4279
4280 wire [40:0] dram_Ch3_l2b1_wr_q_0 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[0],
4281 `MCU3_DRQ1_CTL.drq_wrbuf_valids[0], //`DRAM_PATH3.writeqbank0vld0_arb,
4282 `MCU3_DRQ1_CTL.drq_wr_queue_ent0[11:9],
4283 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue0[3:0],
4284 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue0[2:0],
4285 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue0[14:0],
4286 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue0[10:0],
4287 3'b0};
4288
4289 wire [40:0] dram_Ch3_l2b1_wr_q_1 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[1],
4290 `MCU3_DRQ1_CTL.drq_wrbuf_valids[1], //`DRAM_PATH3.writeqbank0vld0_arb,
4291 `MCU3_DRQ1_CTL.drq_wr_queue_ent1[11:9],
4292 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue1[3:0],
4293 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue1[2:0],
4294 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue1[14:0],
4295 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue1[10:0],
4296 3'b0};
4297
4298 wire [40:0] dram_Ch3_l2b1_wr_q_2 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[2],
4299 `MCU3_DRQ1_CTL.drq_wrbuf_valids[2], //`DRAM_PATH3.writeqbank0vld0_arb,
4300 `MCU3_DRQ1_CTL.drq_wr_queue_ent2[11:9],
4301 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue2[3:0],
4302 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue2[2:0],
4303 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue2[14:0],
4304 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue2[10:0],
4305 3'b0};
4306
4307 wire [40:0] dram_Ch3_l2b1_wr_q_3 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[3],
4308 `MCU3_DRQ1_CTL.drq_wrbuf_valids[3], //`DRAM_PATH3.writeqbank0vld0_arb,
4309 `MCU3_DRQ1_CTL.drq_wr_queue_ent3[11:9],
4310 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue3[3:0],
4311 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue3[2:0],
4312 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue3[14:0],
4313 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue3[10:0],
4314 3'b0};
4315
4316 wire [40:0] dram_Ch3_l2b1_wr_q_4 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[4],
4317 `MCU3_DRQ1_CTL.drq_wrbuf_valids[4], //`DRAM_PATH3.writeqbank0vld0_arb,
4318 `MCU3_DRQ1_CTL.drq_wr_queue_ent4[11:9],
4319 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue4[3:0],
4320 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue4[2:0],
4321 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue4[14:0],
4322 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue4[10:0],
4323 3'b0};
4324
4325 wire [40:0] dram_Ch3_l2b1_wr_q_5 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[5],
4326 `MCU3_DRQ1_CTL.drq_wrbuf_valids[5], //`DRAM_PATH3.writeqbank0vld0_arb,
4327 `MCU3_DRQ1_CTL.drq_wr_queue_ent5[11:9],
4328 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue5[3:0],
4329 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue5[2:0],
4330 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue5[14:0],
4331 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue5[10:0],
4332 3'b0};
4333
4334 wire [40:0] dram_Ch3_l2b1_wr_q_6 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[6],
4335 `MCU3_DRQ1_CTL.drq_wrbuf_valids[6], //`DRAM_PATH3.writeqbank0vld0_arb,
4336 `MCU3_DRQ1_CTL.drq_wr_queue_ent6[11:9],
4337 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue6[3:0],
4338 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue6[2:0],
4339 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue6[14:0],
4340 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue6[10:0],
4341 3'b0};
4342
4343 wire [40:0] dram_Ch3_l2b1_wr_q_7 = {`MCU3_DRQ1_CTL.drq_wrbuf_valids[7],
4344 `MCU3_DRQ1_CTL.drq_wrbuf_valids[7], //`DRAM_PATH3.writeqbank0vld0_arb,
4345 `MCU3_DRQ1_CTL.drq_wr_queue_ent7[11:9],
4346 `MCU3_L2B1_ADR_Q.rank_wr_adr_queue7[3:0],
4347 `MCU3_L2B1_ADR_Q.bank_wr_adr_queue7[2:0],
4348 `MCU3_L2B1_ADR_Q.ras_wr_adr_queue7[14:0],
4349 `MCU3_L2B1_ADR_Q.cas_wr_adr_queue7[10:0],
4350 3'b0};
4351
4352 reg [40:0] dram_Ch3_l2b1_wr_q[7:0];
4353
4354 // to not set valid for the fifo monitor
4355 wire dram_Ch3_l2b1_pa_err = `MCU3_L2RDMX_DP.l2b1_wr_addr_err;
4356
4357 // write que collapsing fifo
4358 wire [14:0] dram_Ch3_l2b1_wr_colps_q_0 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent0[14:0]};
4359 wire [14:0] dram_Ch3_l2b1_wr_colps_q_1 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent1[14:0]};
4360 wire [14:0] dram_Ch3_l2b1_wr_colps_q_2 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent2[14:0]};
4361 wire [14:0] dram_Ch3_l2b1_wr_colps_q_3 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent3[14:0]};
4362 wire [14:0] dram_Ch3_l2b1_wr_colps_q_4 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent4[14:0]};
4363 wire [14:0] dram_Ch3_l2b1_wr_colps_q_5 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent5[14:0]};
4364 wire [14:0] dram_Ch3_l2b1_wr_colps_q_6 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent6[14:0]};
4365 wire [14:0] dram_Ch3_l2b1_wr_colps_q_7 = {`MCU3_DRQ1_CTL.drq_wr_queue_ent7[14:0]};
4366
4367 reg [14:0] dram_Ch3_l2b1_wr_colps_q[7:0];
4368
4369 // write que write pointer
4370 wire [7:0] dram_Ch3_l2b1_wr_que_wr_ptr = {`MCU3_DRQ1_CTL.drq_wr_adr_queue7_en,
4371 `MCU3_DRQ1_CTL.drq_wr_adr_queue6_en,
4372 `MCU3_DRQ1_CTL.drq_wr_adr_queue5_en,
4373 `MCU3_DRQ1_CTL.drq_wr_adr_queue4_en,
4374 `MCU3_DRQ1_CTL.drq_wr_adr_queue3_en,
4375 `MCU3_DRQ1_CTL.drq_wr_adr_queue2_en,
4376 `MCU3_DRQ1_CTL.drq_wr_adr_queue1_en,
4377 `MCU3_DRQ1_CTL.drq_wr_adr_queue0_en};
4378
4379 // write que arb read pointer
4380
4381 // write que data read pointer
4382 /*wire [7:0] dram_Ch3_l2b1_wr_que_rd_ptr = {`MCU3_DRQ1_CTL.drq_wr_entry7_rank,
4383 `MCU3_DRQ1_CTL.drq_wr_entry6_rank,
4384 `MCU3_DRQ1_CTL.drq_wr_entry5_rank,
4385 `MCU3_DRQ1_CTL.drq_wr_entry4_rank,
4386 `MCU3_DRQ1_CTL.drq_wr_entry3_rank,
4387 `MCU3_DRQ1_CTL.drq_wr_entry2_rank,
4388 `MCU3_DRQ1_CTL.drq_wr_entry1_rank,
4389 `MCU3_DRQ1_CTL.drq_wr_entry0_rank};*/
4390 wire [7:0] dram_Ch3_l2b1_wr_que_rd_ptr = `MCU3_DRQ1_CTL.drq_wrq_clear_ent;
4391
4392
4393// These signals are currently not used in cov obj
4394// enable for 8 deep collps rd fifo
4395 wire [7:0] dram_Ch3_l2b1_que_b0_index_en = {`MCU3_L2B1_ADR_Q.rd_adr_queue_sel[7:0]};
4396
4397
4398// These signals are currently not used in cov obj
4399// enable for 8 deep collps wr fifo
4400 wire [7:0] dram_Ch3_l2b1_que_b0_wr_index_en= {`MCU3_L2B1_ADR_Q.wr_adr_queue_sel[7:0]};
4401
4402// These signals are currently not used in cov obj
4403// indicating that the rd is picked the moment it comes in, if to the same bank no req pend/no refresh
4404 wire [7:0] dram_Ch3_l2b1_que_b0_rd_in_val = `MCU3_DRQ1_CTL.drq_rd_entry0_val[7:0];
4405
4406 wire dram_Ch3_que_b1_rd_picked = `MCU3_DRIF_CTL.drif1_rd_picked;
4407 wire dram_Ch3_que_b1_wr_picked = `MCU3_DRIF_CTL.drif1_wr_picked;
4408
4409
4410
4411// MAQ Not Required wire [7:0] dram_Ch3_que_cas_picked = `MCU3_DRIF_CTL.drif_cas_picked_d1[7:0];
4412// rd hits a wr in the wr Q
4413 wire dram_Ch3_que_rd_wr_hit = `MCU3_DRIF_CTL.drif_wr_entry_pend_in;
4414
4415// MAQ N2 doesn't support // Signals that will be used to detect oldest entry to the same bank.
4416// MAQ N2 doesn't support // in 2 channel mode this is the real indicator that the request is picked from this channel
4417// MAQ N2 doesn't support wire dram_Ch3_que_this_ch_picked = (~`DRAM_PATH3.que_channel_disabled) ?
4418// MAQ N2 doesn't support `DRAM_PATH3.que_ras_bank_picked_en && ~`DRAM_PATH3.que_channel_picked_internal:
4419// MAQ N2 doesn't support `DRAM_PATH3.que_ras_bank_picked_en && `DRAM_PATH3.que_channel_picked_internal;
4420// MAQ N2 doesn't support
4421
4422 wire [2:0] dram_Ch3_que_b0_index_picked = `MCU3_DRIF_CTL.drif_rdwr_index_picked[2:0];
4423 wire dram_Ch3_que_b0_cmd_picked = `MCU3_DRIF_CTL.drif_rdwr_cmd_picked;
4424 wire dram_ch3_drif_mclk_en = `MCU3_DRIF_CTL.drif_mclk_en;
4425
4426
4427//----------------------------------------------------------------------------------------
4428// Refresh to go and all CAS request to same CS are done, no new RAS issued.
4429//----------------------------------------------------------------------------------------
4430 wire [4:0] dram_Ch3_que_pos = `MCU3_DRIF_CTL.drif_mcu_state_enc;
4431 wire dram_Ch3_que_ref_go = `MCU3_DRIF_CTL.drif_ref_go;
4432 wire dram_Ch3_que_hw_selfrsh = `MCU3_DRIF_CTL.drif_hw_selfrsh;
4433 wire dram_Ch3_pt_blk_new_openbank_d1 = `MCU3_DRIF_CTL.drif_blk_new_openbank;
4434 wire dram_Ch3_que_cas_valid = ( (|(`MCU3_DRIF_CTL.drif_cas_picked)) &
4435 (`MCU3_DRIF_CTL.drif_phy_bank_picked[1:0] == `MCU3_DRIF_CTL.drif_refresh_rank[1:0])
4436 );
4437 wire [15:0] dram_Ch3_ras_picked = `MCU3_DRIF_CTL.drif_ras_picked[15:0];
4438 wire dram_Ch3_que_ras_picked = ( (|(`MCU3_DRIF_CTL.drif_ras_picked[15:0])) &
4439 ({`MCU3_DRIF_CTL.drif_rank_adr, `MCU3_DRIF_CTL.drif_stacked_dimm} == `MCU3_DRIF_CTL.drif_refresh_rank[1:0])
4440 );
4441 wire [1:0] dram_Ch3_b0_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4442 wire [1:0] dram_Ch3_b1_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4443 wire [1:0] dram_Ch3_b2_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4444 wire [1:0] dram_Ch3_b3_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4445 wire [1:0] dram_Ch3_b4_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4446 wire [1:0] dram_Ch3_b5_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4447 wire [1:0] dram_Ch3_b6_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4448 wire [1:0] dram_Ch3_b7_phy_bank_bits = `MCU3_DRIF_CTL.drif_phy_bank_picked[1:0];
4449 reg [1:0] dram_Ch3_b_phy_bank_bits[7:0];
4450
4451 wire [1:0] dram_Ch3_que_refresh_rank = `MCU3_DRIF_CTL.drif_refresh_rank[1:0];
4452
4453
4454// ---- Starvation counter causing the wr to have priority ---
4455 wire dram_Ch3_que_pick_wr_first = (`MCU3_DRIF_CTL.drif0_pick_wr_first |
4456 `MCU3_DRIF_CTL.drif1_pick_wr_first);
4457
4458// ------ Scrub Related -------
4459
4460 // picking the que_split_scrb_addr as _que_scrb_addr_picked_
4461 wire [31:0] dram_Ch3_que_scrb_addr_picked = `MCU3_DRIF_CTL.drif_scrub_addr;
4462 wire dram_Ch3_que_scrb_picked = `MCU3_DRIF_CTL.drif_scrub_picked;
4463 //somePersonwire dram_Ch3_que_scrb_rd_picked = `MCU3_DRIF_CTL.drif_scrub_picked; // MAQ
4464 wire dram_Ch3_que_scrb_rd_picked = `MCU3_DRIF_CTL.drif_scrub_read_pending;
4465 wire dram_Ch3_que_ras_bank_picked_en = |(`MCU3_DRIF_CTL.drif_ras_picked[15:0]);
4466 wire dram_Ch3_que_scrb_write_req = `MCU3_DRIF_CTL.drif_scrub_write_req;
4467
4468// req valid and scrb valid, the scrb should be cleared first
4469 wire [15:0] dram_Ch3_que_l2req_valid = `MCU3_DRIF_CTL.drif0_rd_bank_valids | `MCU3_DRIF_CTL.drif1_rd_bank_valids |
4470 `MCU3_DRIF_CTL.drif_wr_bank_valids;
4471 wire [15:0] dram_Ch3_scrb_indx_val = `MCU3_DRIF_CTL.drif_scrub_entry_val;
4472
4473// ------- DRAM REGISTERS --------
4474
4475 wire [8:0] dram_Ch3_chip_config_reg = {`MCU3_DRIF_CTL.drif_ras_addr_bits[3:0],
4476 `MCU3_DRIF_CTL.drif_cas_addr_bits[3:0],
4477 `MCU3_DRIF_CTL.drif_stacked_dimm};
4478
4479 wire [2:0] dram_Ch3_mode_reg = `MCU3_DRIF_CTL.mode_reg[6:4];
4480 wire [3:0] dram_Ch3_rrd_reg = `MCU3_DRIF_CTL.rrd_reg;
4481 wire [4:0] dram_Ch3_rc_reg = `MCU3_DRIF_CTL.rc_reg;
4482 wire [3:0] dram_Ch3_rcd_reg = `MCU3_DRIF_CTL.rcd_reg;
4483 wire [3:0] dram_Ch3_wtr_dly_reg = `MCU3_DRIF_CTL.wtr_dly_reg;
4484 wire [3:0] dram_Ch3_rtw_dly_reg = `MCU3_DRIF_CTL.rtw_dly_reg;
4485 wire [3:0] dram_Ch3_rtp_reg = `MCU3_DRIF_CTL.rtp_reg;
4486 wire [3:0] dram_Ch3_ras_reg = `MCU3_DRIF_CTL.ras_reg;
4487 wire [3:0] dram_Ch3_rp_reg = `MCU3_DRIF_CTL.rp_reg;
4488 wire [3:0] dram_Ch3_wr_reg = `MCU3_DRIF_CTL.wr_reg;
4489 wire [1:0] dram_Ch3_mrd_reg = `MCU3_DRIF_CTL.mrd_reg;
4490 wire [1:0] dram_Ch3_iwtr_reg = `MCU3_DRIF_CTL.iwtr_reg;
4491 wire [14:0] dram_Ch3_ext_mode_reg2 = `MCU3_DRIF_CTL.ext_mode_reg2;
4492 wire [14:0] dram_Ch3_ext_mode_reg1 = `MCU3_DRIF_CTL.ext_mode_reg1;
4493 wire [14:0] dram_Ch3_ext_mode_reg3 = `MCU3_DRIF_CTL.ext_mode_reg3;
4494 wire dram_Ch3_que_eight_bank_mode = `MCU3_DRIF_CTL.drif_eight_bank_mode;
4495 wire dram_Ch3_que_rank1_present = `MCU3_DRIF_CTL.drif_dimms_present[0];
4496 wire dram_Ch3_que_channel_disabled = `MCU3_DRIF_CTL.drif_branch_disabled;
4497 wire dram_Ch3_que_addr_bank_low_sel = `MCU3_DRIF_CTL.drif_addr_bank_low_sel;
4498 wire dram_Ch3_que_init = `MCU3_DRIF_CTL.drif_init;
4499// wire [2:0] dram_Ch3_que_data_del_cnt = `MCU3_DRIF_CTL.drif_data_del_cnt[2:0];
4500// wire dram_Ch3_dram_io_pad_clk_inv = `MCU3_DRIF_CTL.mcu_ddp_pad_clk_inv;
4501// wire [1:0] dram_Ch3_dram_io_ptr_clk_inv = `MCU3_DRIF_CTL.mcu_ddp_ptr_clk_inv;
4502 wire dram_Ch3_que_wr_mode_reg_done = `MCU3_DRIF_CTL.drif_wr_mode_reg_done;
4503 wire dram_Ch3_que_init_status_reg = `MCU3_DRIF_CTL.drif_init_status_reg;
4504 wire [3:0] dram_Ch3_que_dimms_present = `MCU3_DRIF_CTL.drif_dimms_present;
4505 wire dram_Ch3_dram_fail_over_mode = `MCU3_DRIF_CTL.drif_fail_over_mode;
4506 wire [34:0] dram_Ch3_dram_fail_over_mask = `MCU3_DRIF_CTL.drif_fail_over_mask[34:0];
4507 wire dram_Ch3_que_dbg_trig_en = `MCU3_DRIF_CTL.rdpctl_dbg_trig_enable;
4508 wire [22:0] dram_Ch3_que_err_sts_reg = `MCU3_DRIF_CTL.rdpctl_err_sts_reg;
4509 wire [35:0] dram_Ch3_que_err_addr_reg = `MCU3_DRIF_CTL.rdpctl_err_addr_reg;
4510 wire dram_Ch3_err_inj_reg = `MCU3_DRIF_CTL.drif_err_inj_reg;
4511 wire dram_Ch3_sshot_err_reg = `MCU3_DRIF_CTL.drif_sshot_err_reg;
4512// wire [1:0] dram_Ch3_que_err_cnt = `MCU3_DRIF_CTL.rdpctl_err_cnt[17:16];
4513 wire [35:0] dram_Ch3_que_err_loc = `MCU3_DRIF_CTL.rdpctl_err_loc;
4514
4515 // NACK - for non existant register read
4516 wire dram_Ch3_que_l2if_ack_vld = `MCU3_DRIF_CTL.drif_rdata_ack_vld;
4517 wire dram_Ch3_que_l2if_nack_vld = `MCU3_DRIF_CTL.drif_rdata_nack_vld;
4518
4519 wire dram_Ch3_que_init_dram_done = `MCU3_DRIF_CTL.drif_init_mcu_done;
4520
4521// ----- DRAM L2IF INTERFACE -----
4522
4523 wire [127:0] dram_Ch3_dram_sctag_data = `MCU3.mcu_l2b_data_r3;
4524 // Error signal for update of error status, error location and error address register.
4525 //wire dram_Ch3_l2if_scrb_val_d2 = `DRAM_L2IF3.l2if_scrb_val_d3;
4526
4527 // l2if_scrb_data_val is now qualifying scrb in the rtl
4528 wire dram_Ch3_l2if_scrb_val_d2 = `MCU3_RDPCTL_CTL.rdpctl_scrub_data_valid;
4529
4530 wire [6:0] dram_Ch3_err_sts_reg = `MCU3_RDPCTL_CTL.rdpctl_err_sts_reg[25:19];
4531
4532 wire dram_Ch3_l2if_err_sts_reg_en6 = `MCU3_RDPCTL_CTL.rdpctl_meu_error_en;
4533 wire dram_Ch3_l2if_err_sts_reg_en5 = `MCU3_RDPCTL_CTL.rdpctl_mec_error_en;
4534 wire dram_Ch3_l2if_err_sts_reg_en4 = `MCU3_RDPCTL_CTL.rdpctl_dac_error_en;
4535 wire dram_Ch3_l2if_err_sts_reg_en3 = `MCU3_RDPCTL_CTL.rdpctl_dau_error_en;
4536 wire dram_Ch3_l2if_err_sts_reg_en2 = `MCU3_RDPCTL_CTL.rdpctl_dsc_error_en;
4537 wire dram_Ch3_l2if_err_sts_reg_en1 = `MCU3_RDPCTL_CTL.rdpctl_dsu_error_en;
4538 wire dram_Ch3_l2if_err_sts_reg_en0 = `MCU3_RDPCTL_CTL.rdpctl_err_sts_reg_en;
4539 wire dram_Ch3_l2if_err_sts_reg_en = `MCU3_RDPCTL_CTL.rdpctl_dbu_error_en;
4540 wire dram_Ch3_l2if_err_addr_reg_en = `MCU3_RDPCTL_CTL.rdpctl_err_addr_reg_en;
4541 wire dram_Ch3_l2if_secc_loc_en = `MCU3_RDPCTL_CTL.rdpctl_secc_loc_en;
4542
4543
4544 wire dram_Ch3_l2b0_sctag_dram_rd_req = `MCU3_L2IF0_CTL.l2t_mcu_rd_req;
4545 wire [2:0] dram_Ch3_l2b0_sctag_dram_rd_req_id = `MCU3_L2IF0_CTL.l2t_mcu_rd_req_id;
4546// wire [39:6] dram_Ch3_l2b0_sctag_dram_addr = {`MCU3_ADDRDP_DP.l2t0_mcu_addr_39to9, `MCU3_ADDRDP_DP.l2t0_mcu_addr_6to4};
4547 wire [39:5] dram_Ch3_l2b0_sctag_dram_addr = `MCU3_L2IF0_CTL.l2t_mcu_addr;
4548 wire dram_Ch3_l2b0_sctag_dram_rd_dummy_req = `MCU3_L2IF0_CTL.l2t_mcu_rd_dummy_req;
4549 wire dram_Ch3_l2b0_dram_sctag_rd_ack = `MCU3_L2IF0_CTL.mcu_l2t_rd_ack;
4550 wire dram_Ch3_l2b0_sctag_dram_wr_req = `MCU3_L2IF0_CTL.l2t_mcu_wr_req;
4551 wire dram_Ch3_l2b0_sctag_dram_data_vld = `MCU3_L2IF0_CTL.l2b_mcu_data_vld;
4552 wire [63:0] dram_Ch3_l2b0_sctag_dram_wr_data = `MCU3_L2RDMX_DP.l2b0_mcu_wr_data_r5;
4553 wire dram_Ch3_l2b0_dram_sctag_wr_ack = `MCU3_L2IF0_CTL.mcu_l2t_wr_ack;
4554 wire dram_Ch3_l2b0_dram_sctag_data_vld = `MCU3_RDATA_CTL.mcu_l2t0_data_vld_r0;
4555 wire [2:0] dram_Ch3_l2b0_dram_sctag_rd_req_id = `MCU3_RDATA_CTL.mcu_l2t0_rd_req_id_r0;
4556
4557// MAQ N2 doesn't support wire [3:0] dram_Ch3_l2if_b0_rd_val = `DRAM_L2IF3.l2if_b0_rd_val;
4558// MAQ N2 doesn't support wire [3:0] dram_Ch3_l2if_b1_rd_val = `DRAM_L2IF3.l2if_b1_rd_val;
4559 wire [3:0] dram_Ch3_l2b0_l2if_b0_wr_val = {`MCU3_L2IF0_CTL.l2if_wr_entry3,
4560 `MCU3_L2IF0_CTL.l2if_wr_entry2,
4561 `MCU3_L2IF0_CTL.l2if_wr_entry1,
4562 `MCU3_L2IF0_CTL.l2if_wr_entry0};
4563
4564 wire [3:0] dram_Ch3_l2b0_l2if_b1_wr_val = {`MCU3_L2IF0_CTL.l2if_wr_entry7,
4565 `MCU3_L2IF0_CTL.l2if_wr_entry6,
4566 `MCU3_L2IF0_CTL.l2if_wr_entry5,
4567 `MCU3_L2IF0_CTL.l2if_wr_entry4};
4568
4569// MAQ wire [5:0] dram_Ch3_l2b0_l2if_wr_b0_data_addr = `MCU3_L2IF0_CTL.l2if_wdq_wadr;
4570
4571 // Signals on L2 Interface that indicates Error
4572 wire dram_Ch3_l2b0_dram_sctag_secc_err = `MCU3_RDATA_CTL.mcu_l2t0_secc_err_r3;
4573 wire dram_Ch3_l2b0_dram_sctag_pa_err = `MCU3_L2RDMX_DP.l2b0_rd_addr_err | `MCU3_L2RDMX_DP.l2b0_wr_addr_err;
4574 wire dram_Ch3_l2b0_dram_sctag_mecc_err = `MCU3_RDATA_CTL.mcu_l2t0_mecc_err_r3;
4575 wire dram_Ch3_l2b0_dram_sctag_scb_secc_err = `MCU3_RDATA_CTL.mcu_l2t0_scb_secc_err;
4576 wire dram_Ch3_l2b0_dram_sctag_scb_mecc_err = `MCU3_RDATA_CTL.mcu_l2t0_scb_mecc_err;
4577
4578// qualified with vld since they can be on due to residual ( previous error )
4579/* wire dram_Ch3_l2b0_l2if_secc_err = `MCU3_RDATA_CTL.mcu_l2t0_secc_err_r3 &&
4580 (`MCU3_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
4581 `MCU3_RDPCTL_CTL.rdpctl_scrub_data_valid);
4582
4583 wire dram_Ch3_l2b0_l2if_mecc_err_partial = `MCU3_RDATA_CTL.mcu_l2t0_mecc_err_r3 &&
4584 (`MCU3_RDATA_CTL.mcu_l2t0_data_vld_r0 ||
4585 `MCU3_RDPCTL_CTL.rdpctl_scrub_data_valid);
4586*/
4587 wire dram_Ch3_l2b0_l2if_secc_err = `MCU3_RDATA_CTL.mcu_l2t0_scb_secc_err_in ||
4588 `MCU3_RDATA_CTL.mcu_l2t0_secc_err_r1;
4589 wire dram_Ch3_l2b0_l2if_mecc_err_partial = `MCU3_RDATA_CTL.mcu_l2t0_scb_mecc_err_in ||
4590 `MCU3_RDATA_CTL.mcu_l2t0_mecc_err_r1;
4591 wire dram_Ch3_l2b0_l2if_pa_err = (`MCU3_L2RDMX_DP.l2b0_rd_addr_err || `MCU3_L2RDMX_DP.l2b0_wr_addr_err) &&
4592 `MCU3_RDATA_CTL.mcu_l2t0_data_vld_r0;
4593
4594 wire [1:0] dram_Ch3_l2b0_cpu_wr_en = `MCU3_L2IF0_CTL.l2if_wdq_we;
4595 wire [4:0] dram_Ch3_l2b0_cpu_wr_addr = `MCU3_L2IF0_CTL.l2if_wdq_wadr;
4596 wire dram_Ch3_l2b0_wdq_rd_en = `MCU3_DRIF_CTL.drif0_wdq_rd;
4597 wire [4:0] dram_Ch3_l2b0_wdq_radr = `MCU3_DRIF_CTL.drif0_wdq_radr;
4598
4599 wire dram_Ch3_l2b0_clspine_dram_txrd_sync = `MCU3_RDATA_CTL.rdata_cmp_ddr_sync_en;
4600 wire dram_Ch3_l2b0_clspine_dram_txwr_sync = `MCU3_RDATA_CTL.rdata_cmp_ddr_sync_en;
4601
4602// l2if wr entry valid ( for the actual data valid creation)
4603 wire [7:0] dram_Ch3_l2b0_l2if_wr_entry = {
4604 `MCU3_L2IF0_CTL.l2if_wr_entry7,
4605 `MCU3_L2IF0_CTL.l2if_wr_entry6,
4606 `MCU3_L2IF0_CTL.l2if_wr_entry5,
4607 `MCU3_L2IF0_CTL.l2if_wr_entry4,
4608 `MCU3_L2IF0_CTL.l2if_wr_entry3,
4609 `MCU3_L2IF0_CTL.l2if_wr_entry2,
4610 `MCU3_L2IF0_CTL.l2if_wr_entry1,
4611 `MCU3_L2IF0_CTL.l2if_wr_entry0
4612 };
4613
4614
4615
4616/* wire [8:0] dram_Ch3_l2b0_rd_adr_info_hi = {
4617 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4618 `MCU3_L2B0_ADRGEN_DP.addr_err,
4619 `MCU3_DRIF_CTL.drif_stack_adr,
4620 `MCU3_L2B0_ADRGEN_DP.rank_adr,
4621 `MCU3_L2B0_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4622 `MCU3_L2B0_ADRGEN_DP.bank_adr[1:0],
4623 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4624 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4625 };
4626
4627 wire [8:0] dram_Ch3_l2b0_wr_adr_info_hi = {
4628 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4629 `MCU3_L2B0_ADRGEN_DP.addr_err,
4630 `MCU3_DRIF_CTL.drif_stack_adr,
4631 `MCU3_L2B0_ADRGEN_DP.rank_adr,
4632 `MCU3_L2B0_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4633 `MCU3_L2B0_ADRGEN_DP.bank_adr[1:0],
4634 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4635 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4636 };
4637
4638 wire [8:0] dram_Ch3_l2b0_rd_adr_info_lo = {
4639 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4640 `MCU3_L2B0_ADRGEN_DP.addr_err,
4641 `MCU3_DRIF_CTL.drif_stack_adr,
4642 `MCU3_L2B0_ADRGEN_DP.rank_adr,
4643 `MCU3_L2B0_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4644 `MCU3_L2B0_ADRGEN_DP.bank_adr[1:0],
4645 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4646 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4647 };
4648
4649 wire [8:0] dram_Ch3_l2b0_wr_adr_info_lo = {
4650 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4651 `MCU3_L2B0_ADRGEN_DP.addr_err,
4652 `MCU3_DRIF_CTL.drif_stack_adr,
4653 `MCU3_L2B0_ADRGEN_DP.rank_adr,
4654 `MCU3_L2B0_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4655 `MCU3_L2B0_ADRGEN_DP.bank_adr[1:0],
4656 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4657 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4658 };*/
4659
4660
4661 wire dram_Ch3_l2b1_sctag_dram_rd_req = `MCU3_L2IF1_CTL.l2t_mcu_rd_req;
4662 wire [2:0] dram_Ch3_l2b1_sctag_dram_rd_req_id = `MCU3_L2IF1_CTL.l2t_mcu_rd_req_id;
4663// wire [39:6] dram_Ch3_l2b1_sctag_dram_addr = {`MCU3_ADDRDP_DP.l2t1_mcu_addr_39to9, `MCU3_ADDRDP_DP.l2t1_mcu_addr_6to4};
4664 wire [39:5] dram_Ch3_l2b1_sctag_dram_addr = `MCU3_L2IF1_CTL.l2t_mcu_addr;
4665 wire dram_Ch3_l2b1_sctag_dram_rd_dummy_req = `MCU3_L2IF1_CTL.l2t_mcu_rd_dummy_req;
4666 wire dram_Ch3_l2b1_dram_sctag_rd_ack = `MCU3_L2IF1_CTL.mcu_l2t_rd_ack;
4667 wire dram_Ch3_l2b1_sctag_dram_wr_req = `MCU3_L2IF1_CTL.l2t_mcu_wr_req;
4668 wire dram_Ch3_l2b1_sctag_dram_data_vld = `MCU3_L2IF1_CTL.l2b_mcu_data_vld;
4669 wire [63:0] dram_Ch3_l2b1_sctag_dram_wr_data = `MCU3_L2RDMX_DP.l2b1_mcu_wr_data_r5;
4670 wire dram_Ch3_l2b1_dram_sctag_wr_ack = `MCU3_L2IF1_CTL.mcu_l2t_wr_ack;
4671 wire dram_Ch3_l2b1_dram_sctag_data_vld = `MCU3_RDATA_CTL.mcu_l2t1_data_vld_r0;
4672 wire [2:0] dram_Ch3_l2b1_dram_sctag_rd_req_id = `MCU3_RDATA_CTL.mcu_l2t1_rd_req_id_r0;
4673
4674// MAQ N2 doesn't support wire [3:0] dram_Ch3_l2if_b0_rd_val = `DRAM_L2IF3.l2if_b0_rd_val;
4675// MAQ N2 doesn't support wire [3:0] dram_Ch3_l2if_b1_rd_val = `DRAM_L2IF3.l2if_b1_rd_val;
4676 wire [3:0] dram_Ch3_l2b1_l2if_b0_wr_val = {`MCU3_L2IF1_CTL.l2if_wr_entry3,
4677 `MCU3_L2IF1_CTL.l2if_wr_entry2,
4678 `MCU3_L2IF1_CTL.l2if_wr_entry1,
4679 `MCU3_L2IF1_CTL.l2if_wr_entry0};
4680
4681 wire [3:0] dram_Ch3_l2b1_l2if_b1_wr_val = {`MCU3_L2IF1_CTL.l2if_wr_entry7,
4682 `MCU3_L2IF1_CTL.l2if_wr_entry6,
4683 `MCU3_L2IF1_CTL.l2if_wr_entry5,
4684 `MCU3_L2IF1_CTL.l2if_wr_entry4};
4685
4686// MAQ wire [5:0] dram_Ch3_l2b1_l2if_wr_b0_data_addr = `MCU3_L2IF1_CTL.l2if_wdq_wadr;
4687
4688 // Signals on L2 Interface that indicates Error
4689 wire dram_Ch3_l2b1_dram_sctag_secc_err = `MCU3_RDATA_CTL.mcu_l2t1_secc_err_r3;
4690 wire dram_Ch3_l2b1_dram_sctag_pa_err = `MCU3_L2RDMX_DP.l2b1_rd_addr_err | `MCU3_L2RDMX_DP.l2b1_wr_addr_err;
4691 wire dram_Ch3_l2b1_dram_sctag_mecc_err = `MCU3_RDATA_CTL.mcu_l2t1_mecc_err_r3;
4692 wire dram_Ch3_l2b1_dram_sctag_scb_secc_err = `MCU3_RDATA_CTL.mcu_l2t1_scb_secc_err;
4693 wire dram_Ch3_l2b1_dram_sctag_scb_mecc_err = `MCU3_RDATA_CTL.mcu_l2t1_scb_mecc_err;
4694
4695// qualified with vld since they can be on due to residual ( previous error )
4696/* wire dram_Ch3_l2b1_l2if_secc_err = `MCU3_RDATA_CTL.mcu_l2t1_secc_err_r3 &&
4697 (`MCU3_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
4698 `MCU3_RDPCTL_CTL.rdpctl_scrub_data_valid);
4699
4700 wire dram_Ch3_l2b1_l2if_mecc_err_partial = `MCU3_RDATA_CTL.mcu_l2t1_mecc_err_r3 &&
4701 (`MCU3_RDATA_CTL.mcu_l2t1_data_vld_r0 ||
4702 `MCU3_RDPCTL_CTL.rdpctl_scrub_data_valid);
4703*/
4704 wire dram_Ch3_l2b1_l2if_secc_err = `MCU3_RDATA_CTL.mcu_l2t1_scb_secc_err_in ||
4705 `MCU3_RDATA_CTL.mcu_l2t1_secc_err_r1;
4706 wire dram_Ch3_l2b1_l2if_mecc_err_partial = `MCU3_RDATA_CTL.mcu_l2t1_scb_mecc_err_in ||
4707 `MCU3_RDATA_CTL.mcu_l2t1_mecc_err_r1;
4708 wire dram_Ch3_l2b1_l2if_pa_err = (`MCU3_L2RDMX_DP.l2b1_rd_addr_err || `MCU3_L2RDMX_DP.l2b1_wr_addr_err) &&
4709 `MCU3_RDATA_CTL.mcu_l2t1_data_vld_r0;
4710
4711 wire [1:0] dram_Ch3_l2b1_cpu_wr_en = `MCU3_L2IF1_CTL.l2if_wdq_we;
4712 wire [4:0] dram_Ch3_l2b1_cpu_wr_addr = `MCU3_L2IF1_CTL.l2if_wdq_wadr;
4713 wire dram_Ch3_l2b1_wdq_rd_en = `MCU3_DRIF_CTL.drif1_wdq_rd;
4714 wire [4:0] dram_Ch3_l2b1_wdq_radr = `MCU3_DRIF_CTL.drif1_wdq_radr;
4715
4716 wire dram_Ch3_l2b1_clspine_dram_txrd_sync = `MCU3_RDATA_CTL.rdata_cmp_ddr_sync_en;
4717 wire dram_Ch3_l2b1_clspine_dram_txwr_sync = `MCU3_RDATA_CTL.rdata_cmp_ddr_sync_en;
4718
4719// l2if wr entry valid ( for the actual data valid creation)
4720 wire [7:0] dram_Ch3_l2b1_l2if_wr_entry = {
4721 `MCU3_L2IF1_CTL.l2if_wr_entry7,
4722 `MCU3_L2IF1_CTL.l2if_wr_entry6,
4723 `MCU3_L2IF1_CTL.l2if_wr_entry5,
4724 `MCU3_L2IF1_CTL.l2if_wr_entry4,
4725 `MCU3_L2IF1_CTL.l2if_wr_entry3,
4726 `MCU3_L2IF1_CTL.l2if_wr_entry2,
4727 `MCU3_L2IF1_CTL.l2if_wr_entry1,
4728 `MCU3_L2IF1_CTL.l2if_wr_entry0
4729 };
4730
4731
4732
4733/* wire [8:0] dram_Ch3_l2b1_rd_adr_info_hi = {
4734 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4735 `MCU3_L2B1_ADRGEN_DP.addr_err,
4736 `MCU3_DRIF_CTL.drif_stack_adr,
4737 `MCU3_L2B1_ADRGEN_DP.rank_adr,
4738 `MCU3_L2B1_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4739 `MCU3_L2B1_ADRGEN_DP.bank_adr[1:0],
4740 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4741 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4742 };
4743
4744 wire [8:0] dram_Ch3_l2b1_wr_adr_info_hi = {
4745 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4746 `MCU3_L2B1_ADRGEN_DP.addr_err,
4747 `MCU3_DRIF_CTL.drif_stack_adr,
4748 `MCU3_L2B1_ADRGEN_DP.rank_adr,
4749 `MCU3_L2B1_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4750 `MCU3_L2B1_ADRGEN_DP.bank_adr[1:0],
4751 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4752 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4753 };
4754
4755 wire [8:0] dram_Ch3_l2b1_rd_adr_info_lo = {
4756 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4757 `MCU3_L2B1_ADRGEN_DP.addr_err,
4758 `MCU3_DRIF_CTL.drif_stack_adr,
4759 `MCU3_L2B1_ADRGEN_DP.rank_adr,
4760 `MCU3_L2B1_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4761 `MCU3_L2B1_ADRGEN_DP.bank_adr[1:0],
4762 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4763 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4764 };
4765
4766 wire [8:0] dram_Ch3_l2b1_wr_adr_info_lo = {
4767 `MCU3_DRIF_CTL.drif_addr_bank_low_sel,
4768 `MCU3_L2B1_ADRGEN_DP.addr_err,
4769 `MCU3_DRIF_CTL.drif_stack_adr,
4770 `MCU3_L2B1_ADRGEN_DP.rank_adr,
4771 `MCU3_L2B1_ADRGEN_DP.bank_adr[2] && `MCU3_DRIF_CTL.drif_eight_bank_mode,
4772 `MCU3_L2B1_ADRGEN_DP.bank_adr[1:0],
4773 `MCU3_DRIF_CTL.drif_eight_bank_mode,
4774 1'b0 // `DRAM_L2IF3.dram_rd_addr_gen_hi.two_channel_mode
4775 };*/
4776
4777
4778
4779// ---- Performance counters ----
4780
4781 wire [7:0] dram_Ch3_perf_cntl = `MCU3_DRIF_CTL.drif_perf_cntl_reg;
4782 wire dram_Ch3_cnt0_sticky_bit = `MCU3_DRIF_CTL.drif_perf_cnt0_reg[31];
4783 wire dram_Ch3_cnt1_sticky_bit = `MCU3_DRIF_CTL.drif_perf_cnt1_reg[31];
4784
4785
4786// -------- FIFO CONDITIONs ----------
4787
4788
4789// ----- RD Q -------
4790
4791always @(dram_Ch0_l2b0_rd_q_0 or dram_Ch0_l2b0_rd_q_1 or dram_Ch0_l2b0_rd_q_2 or dram_Ch0_l2b0_rd_q_3 or
4792 dram_Ch0_l2b0_rd_q_4 or dram_Ch0_l2b0_rd_q_5 or dram_Ch0_l2b0_rd_q_6 or dram_Ch0_l2b0_rd_q_7 or
4793 dram_rst_l)
4794begin
4795 if(~dram_rst_l)
4796 begin
4797 dram_Ch0_l2b0_rd_q[0] = 0;
4798 dram_Ch0_l2b0_rd_q[1] = 0;
4799 dram_Ch0_l2b0_rd_q[2] = 0;
4800 dram_Ch0_l2b0_rd_q[3] = 0;
4801 dram_Ch0_l2b0_rd_q[4] = 0;
4802 dram_Ch0_l2b0_rd_q[5] = 0;
4803 dram_Ch0_l2b0_rd_q[6] = 0;
4804 dram_Ch0_l2b0_rd_q[7] = 0;
4805 end
4806 else
4807 begin
4808 dram_Ch0_l2b0_rd_q[0] = dram_Ch0_l2b0_rd_q_0;
4809 dram_Ch0_l2b0_rd_q[1] = dram_Ch0_l2b0_rd_q_1;
4810 dram_Ch0_l2b0_rd_q[2] = dram_Ch0_l2b0_rd_q_2;
4811 dram_Ch0_l2b0_rd_q[3] = dram_Ch0_l2b0_rd_q_3;
4812 dram_Ch0_l2b0_rd_q[4] = dram_Ch0_l2b0_rd_q_4;
4813 dram_Ch0_l2b0_rd_q[5] = dram_Ch0_l2b0_rd_q_5;
4814 dram_Ch0_l2b0_rd_q[6] = dram_Ch0_l2b0_rd_q_6;
4815 dram_Ch0_l2b0_rd_q[7] = dram_Ch0_l2b0_rd_q_7;
4816 end
4817end
4818always @(dram_Ch0_l2b1_rd_q_0 or dram_Ch0_l2b1_rd_q_1 or dram_Ch0_l2b1_rd_q_2 or dram_Ch0_l2b1_rd_q_3 or
4819 dram_Ch0_l2b1_rd_q_4 or dram_Ch0_l2b1_rd_q_5 or dram_Ch0_l2b1_rd_q_6 or dram_Ch0_l2b1_rd_q_7 or
4820 dram_rst_l)
4821begin
4822 if(~dram_rst_l)
4823 begin
4824 dram_Ch0_l2b1_rd_q[0] = 0;
4825 dram_Ch0_l2b1_rd_q[1] = 0;
4826 dram_Ch0_l2b1_rd_q[2] = 0;
4827 dram_Ch0_l2b1_rd_q[3] = 0;
4828 dram_Ch0_l2b1_rd_q[4] = 0;
4829 dram_Ch0_l2b1_rd_q[5] = 0;
4830 dram_Ch0_l2b1_rd_q[6] = 0;
4831 dram_Ch0_l2b1_rd_q[7] = 0;
4832 end
4833 else
4834 begin
4835 dram_Ch0_l2b1_rd_q[0] = dram_Ch0_l2b1_rd_q_0;
4836 dram_Ch0_l2b1_rd_q[1] = dram_Ch0_l2b1_rd_q_1;
4837 dram_Ch0_l2b1_rd_q[2] = dram_Ch0_l2b1_rd_q_2;
4838 dram_Ch0_l2b1_rd_q[3] = dram_Ch0_l2b1_rd_q_3;
4839 dram_Ch0_l2b1_rd_q[4] = dram_Ch0_l2b1_rd_q_4;
4840 dram_Ch0_l2b1_rd_q[5] = dram_Ch0_l2b1_rd_q_5;
4841 dram_Ch0_l2b1_rd_q[6] = dram_Ch0_l2b1_rd_q_6;
4842 dram_Ch0_l2b1_rd_q[7] = dram_Ch0_l2b1_rd_q_7;
4843 end
4844end
4845always @(dram_Ch1_l2b0_rd_q_0 or dram_Ch1_l2b0_rd_q_1 or dram_Ch1_l2b0_rd_q_2 or dram_Ch1_l2b0_rd_q_3 or
4846 dram_Ch1_l2b0_rd_q_4 or dram_Ch1_l2b0_rd_q_5 or dram_Ch1_l2b0_rd_q_6 or dram_Ch1_l2b0_rd_q_7 or
4847 dram_rst_l)
4848begin
4849 if(~dram_rst_l)
4850 begin
4851 dram_Ch1_l2b0_rd_q[0] = 0;
4852 dram_Ch1_l2b0_rd_q[1] = 0;
4853 dram_Ch1_l2b0_rd_q[2] = 0;
4854 dram_Ch1_l2b0_rd_q[3] = 0;
4855 dram_Ch1_l2b0_rd_q[4] = 0;
4856 dram_Ch1_l2b0_rd_q[5] = 0;
4857 dram_Ch1_l2b0_rd_q[6] = 0;
4858 dram_Ch1_l2b0_rd_q[7] = 0;
4859 end
4860 else
4861 begin
4862 dram_Ch1_l2b0_rd_q[0] = dram_Ch1_l2b0_rd_q_0;
4863 dram_Ch1_l2b0_rd_q[1] = dram_Ch1_l2b0_rd_q_1;
4864 dram_Ch1_l2b0_rd_q[2] = dram_Ch1_l2b0_rd_q_2;
4865 dram_Ch1_l2b0_rd_q[3] = dram_Ch1_l2b0_rd_q_3;
4866 dram_Ch1_l2b0_rd_q[4] = dram_Ch1_l2b0_rd_q_4;
4867 dram_Ch1_l2b0_rd_q[5] = dram_Ch1_l2b0_rd_q_5;
4868 dram_Ch1_l2b0_rd_q[6] = dram_Ch1_l2b0_rd_q_6;
4869 dram_Ch1_l2b0_rd_q[7] = dram_Ch1_l2b0_rd_q_7;
4870 end
4871end
4872always @(dram_Ch1_l2b1_rd_q_0 or dram_Ch1_l2b1_rd_q_1 or dram_Ch1_l2b1_rd_q_2 or dram_Ch1_l2b1_rd_q_3 or
4873 dram_Ch1_l2b1_rd_q_4 or dram_Ch1_l2b1_rd_q_5 or dram_Ch1_l2b1_rd_q_6 or dram_Ch1_l2b1_rd_q_7 or
4874 dram_rst_l)
4875begin
4876 if(~dram_rst_l)
4877 begin
4878 dram_Ch1_l2b1_rd_q[0] = 0;
4879 dram_Ch1_l2b1_rd_q[1] = 0;
4880 dram_Ch1_l2b1_rd_q[2] = 0;
4881 dram_Ch1_l2b1_rd_q[3] = 0;
4882 dram_Ch1_l2b1_rd_q[4] = 0;
4883 dram_Ch1_l2b1_rd_q[5] = 0;
4884 dram_Ch1_l2b1_rd_q[6] = 0;
4885 dram_Ch1_l2b1_rd_q[7] = 0;
4886 end
4887 else
4888 begin
4889 dram_Ch1_l2b1_rd_q[0] = dram_Ch1_l2b1_rd_q_0;
4890 dram_Ch1_l2b1_rd_q[1] = dram_Ch1_l2b1_rd_q_1;
4891 dram_Ch1_l2b1_rd_q[2] = dram_Ch1_l2b1_rd_q_2;
4892 dram_Ch1_l2b1_rd_q[3] = dram_Ch1_l2b1_rd_q_3;
4893 dram_Ch1_l2b1_rd_q[4] = dram_Ch1_l2b1_rd_q_4;
4894 dram_Ch1_l2b1_rd_q[5] = dram_Ch1_l2b1_rd_q_5;
4895 dram_Ch1_l2b1_rd_q[6] = dram_Ch1_l2b1_rd_q_6;
4896 dram_Ch1_l2b1_rd_q[7] = dram_Ch1_l2b1_rd_q_7;
4897 end
4898end
4899always @(dram_Ch2_l2b0_rd_q_0 or dram_Ch2_l2b0_rd_q_1 or dram_Ch2_l2b0_rd_q_2 or dram_Ch2_l2b0_rd_q_3 or
4900 dram_Ch2_l2b0_rd_q_4 or dram_Ch2_l2b0_rd_q_5 or dram_Ch2_l2b0_rd_q_6 or dram_Ch2_l2b0_rd_q_7 or
4901 dram_rst_l)
4902begin
4903 if(~dram_rst_l)
4904 begin
4905 dram_Ch2_l2b0_rd_q[0] = 0;
4906 dram_Ch2_l2b0_rd_q[1] = 0;
4907 dram_Ch2_l2b0_rd_q[2] = 0;
4908 dram_Ch2_l2b0_rd_q[3] = 0;
4909 dram_Ch2_l2b0_rd_q[4] = 0;
4910 dram_Ch2_l2b0_rd_q[5] = 0;
4911 dram_Ch2_l2b0_rd_q[6] = 0;
4912 dram_Ch2_l2b0_rd_q[7] = 0;
4913 end
4914 else
4915 begin
4916 dram_Ch2_l2b0_rd_q[0] = dram_Ch2_l2b0_rd_q_0;
4917 dram_Ch2_l2b0_rd_q[1] = dram_Ch2_l2b0_rd_q_1;
4918 dram_Ch2_l2b0_rd_q[2] = dram_Ch2_l2b0_rd_q_2;
4919 dram_Ch2_l2b0_rd_q[3] = dram_Ch2_l2b0_rd_q_3;
4920 dram_Ch2_l2b0_rd_q[4] = dram_Ch2_l2b0_rd_q_4;
4921 dram_Ch2_l2b0_rd_q[5] = dram_Ch2_l2b0_rd_q_5;
4922 dram_Ch2_l2b0_rd_q[6] = dram_Ch2_l2b0_rd_q_6;
4923 dram_Ch2_l2b0_rd_q[7] = dram_Ch2_l2b0_rd_q_7;
4924 end
4925end
4926always @(dram_Ch2_l2b1_rd_q_0 or dram_Ch2_l2b1_rd_q_1 or dram_Ch2_l2b1_rd_q_2 or dram_Ch2_l2b1_rd_q_3 or
4927 dram_Ch2_l2b1_rd_q_4 or dram_Ch2_l2b1_rd_q_5 or dram_Ch2_l2b1_rd_q_6 or dram_Ch2_l2b1_rd_q_7 or
4928 dram_rst_l)
4929begin
4930 if(~dram_rst_l)
4931 begin
4932 dram_Ch2_l2b1_rd_q[0] = 0;
4933 dram_Ch2_l2b1_rd_q[1] = 0;
4934 dram_Ch2_l2b1_rd_q[2] = 0;
4935 dram_Ch2_l2b1_rd_q[3] = 0;
4936 dram_Ch2_l2b1_rd_q[4] = 0;
4937 dram_Ch2_l2b1_rd_q[5] = 0;
4938 dram_Ch2_l2b1_rd_q[6] = 0;
4939 dram_Ch2_l2b1_rd_q[7] = 0;
4940 end
4941 else
4942 begin
4943 dram_Ch2_l2b1_rd_q[0] = dram_Ch2_l2b1_rd_q_0;
4944 dram_Ch2_l2b1_rd_q[1] = dram_Ch2_l2b1_rd_q_1;
4945 dram_Ch2_l2b1_rd_q[2] = dram_Ch2_l2b1_rd_q_2;
4946 dram_Ch2_l2b1_rd_q[3] = dram_Ch2_l2b1_rd_q_3;
4947 dram_Ch2_l2b1_rd_q[4] = dram_Ch2_l2b1_rd_q_4;
4948 dram_Ch2_l2b1_rd_q[5] = dram_Ch2_l2b1_rd_q_5;
4949 dram_Ch2_l2b1_rd_q[6] = dram_Ch2_l2b1_rd_q_6;
4950 dram_Ch2_l2b1_rd_q[7] = dram_Ch2_l2b1_rd_q_7;
4951 end
4952end
4953always @(dram_Ch3_l2b0_rd_q_0 or dram_Ch3_l2b0_rd_q_1 or dram_Ch3_l2b0_rd_q_2 or dram_Ch3_l2b0_rd_q_3 or
4954 dram_Ch3_l2b0_rd_q_4 or dram_Ch3_l2b0_rd_q_5 or dram_Ch3_l2b0_rd_q_6 or dram_Ch3_l2b0_rd_q_7 or
4955 dram_rst_l)
4956begin
4957 if(~dram_rst_l)
4958 begin
4959 dram_Ch3_l2b0_rd_q[0] = 0;
4960 dram_Ch3_l2b0_rd_q[1] = 0;
4961 dram_Ch3_l2b0_rd_q[2] = 0;
4962 dram_Ch3_l2b0_rd_q[3] = 0;
4963 dram_Ch3_l2b0_rd_q[4] = 0;
4964 dram_Ch3_l2b0_rd_q[5] = 0;
4965 dram_Ch3_l2b0_rd_q[6] = 0;
4966 dram_Ch3_l2b0_rd_q[7] = 0;
4967 end
4968 else
4969 begin
4970 dram_Ch3_l2b0_rd_q[0] = dram_Ch3_l2b0_rd_q_0;
4971 dram_Ch3_l2b0_rd_q[1] = dram_Ch3_l2b0_rd_q_1;
4972 dram_Ch3_l2b0_rd_q[2] = dram_Ch3_l2b0_rd_q_2;
4973 dram_Ch3_l2b0_rd_q[3] = dram_Ch3_l2b0_rd_q_3;
4974 dram_Ch3_l2b0_rd_q[4] = dram_Ch3_l2b0_rd_q_4;
4975 dram_Ch3_l2b0_rd_q[5] = dram_Ch3_l2b0_rd_q_5;
4976 dram_Ch3_l2b0_rd_q[6] = dram_Ch3_l2b0_rd_q_6;
4977 dram_Ch3_l2b0_rd_q[7] = dram_Ch3_l2b0_rd_q_7;
4978 end
4979end
4980always @(dram_Ch3_l2b1_rd_q_0 or dram_Ch3_l2b1_rd_q_1 or dram_Ch3_l2b1_rd_q_2 or dram_Ch3_l2b1_rd_q_3 or
4981 dram_Ch3_l2b1_rd_q_4 or dram_Ch3_l2b1_rd_q_5 or dram_Ch3_l2b1_rd_q_6 or dram_Ch3_l2b1_rd_q_7 or
4982 dram_rst_l)
4983begin
4984 if(~dram_rst_l)
4985 begin
4986 dram_Ch3_l2b1_rd_q[0] = 0;
4987 dram_Ch3_l2b1_rd_q[1] = 0;
4988 dram_Ch3_l2b1_rd_q[2] = 0;
4989 dram_Ch3_l2b1_rd_q[3] = 0;
4990 dram_Ch3_l2b1_rd_q[4] = 0;
4991 dram_Ch3_l2b1_rd_q[5] = 0;
4992 dram_Ch3_l2b1_rd_q[6] = 0;
4993 dram_Ch3_l2b1_rd_q[7] = 0;
4994 end
4995 else
4996 begin
4997 dram_Ch3_l2b1_rd_q[0] = dram_Ch3_l2b1_rd_q_0;
4998 dram_Ch3_l2b1_rd_q[1] = dram_Ch3_l2b1_rd_q_1;
4999 dram_Ch3_l2b1_rd_q[2] = dram_Ch3_l2b1_rd_q_2;
5000 dram_Ch3_l2b1_rd_q[3] = dram_Ch3_l2b1_rd_q_3;
5001 dram_Ch3_l2b1_rd_q[4] = dram_Ch3_l2b1_rd_q_4;
5002 dram_Ch3_l2b1_rd_q[5] = dram_Ch3_l2b1_rd_q_5;
5003 dram_Ch3_l2b1_rd_q[6] = dram_Ch3_l2b1_rd_q_6;
5004 dram_Ch3_l2b1_rd_q[7] = dram_Ch3_l2b1_rd_q_7;
5005 end
5006end
5007
5008// ---- RD COLPS FIFO -----
5009
5010always @( dram_Ch0_l2b0_rd_colps_q_0 or dram_Ch0_l2b0_rd_colps_q_1 or dram_Ch0_l2b0_rd_colps_q_2 or
5011 dram_Ch0_l2b0_rd_colps_q_3 or dram_Ch0_l2b0_rd_colps_q_4 or dram_Ch0_l2b0_rd_colps_q_5 or
5012 dram_Ch0_l2b0_rd_colps_q_6 or dram_Ch0_l2b0_rd_colps_q_7 or dram_rst_l)
5013begin
5014 if(~dram_rst_l)
5015 begin
5016 dram_Ch0_l2b0_rd_colps_q[0] = 0;
5017 dram_Ch0_l2b0_rd_colps_q[1] = 0;
5018 dram_Ch0_l2b0_rd_colps_q[2] = 0;
5019 dram_Ch0_l2b0_rd_colps_q[3] = 0;
5020 dram_Ch0_l2b0_rd_colps_q[4] = 0;
5021 dram_Ch0_l2b0_rd_colps_q[5] = 0;
5022 dram_Ch0_l2b0_rd_colps_q[6] = 0;
5023 dram_Ch0_l2b0_rd_colps_q[7] = 0;
5024 end
5025 else
5026 begin
5027 dram_Ch0_l2b0_rd_colps_q[0] = dram_Ch0_l2b0_rd_colps_q_0;
5028 dram_Ch0_l2b0_rd_colps_q[1] = dram_Ch0_l2b0_rd_colps_q_1;
5029 dram_Ch0_l2b0_rd_colps_q[2] = dram_Ch0_l2b0_rd_colps_q_2;
5030 dram_Ch0_l2b0_rd_colps_q[3] = dram_Ch0_l2b0_rd_colps_q_3;
5031 dram_Ch0_l2b0_rd_colps_q[4] = dram_Ch0_l2b0_rd_colps_q_4;
5032 dram_Ch0_l2b0_rd_colps_q[5] = dram_Ch0_l2b0_rd_colps_q_5;
5033 dram_Ch0_l2b0_rd_colps_q[6] = dram_Ch0_l2b0_rd_colps_q_6;
5034 dram_Ch0_l2b0_rd_colps_q[7] = dram_Ch0_l2b0_rd_colps_q_7;
5035 end
5036end
5037always @( dram_Ch0_l2b1_rd_colps_q_0 or dram_Ch0_l2b1_rd_colps_q_1 or dram_Ch0_l2b1_rd_colps_q_2 or
5038 dram_Ch0_l2b1_rd_colps_q_3 or dram_Ch0_l2b1_rd_colps_q_4 or dram_Ch0_l2b1_rd_colps_q_5 or
5039 dram_Ch0_l2b1_rd_colps_q_6 or dram_Ch0_l2b1_rd_colps_q_7 or dram_rst_l)
5040begin
5041 if(~dram_rst_l)
5042 begin
5043 dram_Ch0_l2b1_rd_colps_q[0] = 0;
5044 dram_Ch0_l2b1_rd_colps_q[1] = 0;
5045 dram_Ch0_l2b1_rd_colps_q[2] = 0;
5046 dram_Ch0_l2b1_rd_colps_q[3] = 0;
5047 dram_Ch0_l2b1_rd_colps_q[4] = 0;
5048 dram_Ch0_l2b1_rd_colps_q[5] = 0;
5049 dram_Ch0_l2b1_rd_colps_q[6] = 0;
5050 dram_Ch0_l2b1_rd_colps_q[7] = 0;
5051 end
5052 else
5053 begin
5054 dram_Ch0_l2b1_rd_colps_q[0] = dram_Ch0_l2b1_rd_colps_q_0;
5055 dram_Ch0_l2b1_rd_colps_q[1] = dram_Ch0_l2b1_rd_colps_q_1;
5056 dram_Ch0_l2b1_rd_colps_q[2] = dram_Ch0_l2b1_rd_colps_q_2;
5057 dram_Ch0_l2b1_rd_colps_q[3] = dram_Ch0_l2b1_rd_colps_q_3;
5058 dram_Ch0_l2b1_rd_colps_q[4] = dram_Ch0_l2b1_rd_colps_q_4;
5059 dram_Ch0_l2b1_rd_colps_q[5] = dram_Ch0_l2b1_rd_colps_q_5;
5060 dram_Ch0_l2b1_rd_colps_q[6] = dram_Ch0_l2b1_rd_colps_q_6;
5061 dram_Ch0_l2b1_rd_colps_q[7] = dram_Ch0_l2b1_rd_colps_q_7;
5062 end
5063end
5064always @( dram_Ch1_l2b0_rd_colps_q_0 or dram_Ch1_l2b0_rd_colps_q_1 or dram_Ch1_l2b0_rd_colps_q_2 or
5065 dram_Ch1_l2b0_rd_colps_q_3 or dram_Ch1_l2b0_rd_colps_q_4 or dram_Ch1_l2b0_rd_colps_q_5 or
5066 dram_Ch1_l2b0_rd_colps_q_6 or dram_Ch1_l2b0_rd_colps_q_7 or dram_rst_l)
5067begin
5068 if(~dram_rst_l)
5069 begin
5070 dram_Ch1_l2b0_rd_colps_q[0] = 0;
5071 dram_Ch1_l2b0_rd_colps_q[1] = 0;
5072 dram_Ch1_l2b0_rd_colps_q[2] = 0;
5073 dram_Ch1_l2b0_rd_colps_q[3] = 0;
5074 dram_Ch1_l2b0_rd_colps_q[4] = 0;
5075 dram_Ch1_l2b0_rd_colps_q[5] = 0;
5076 dram_Ch1_l2b0_rd_colps_q[6] = 0;
5077 dram_Ch1_l2b0_rd_colps_q[7] = 0;
5078 end
5079 else
5080 begin
5081 dram_Ch1_l2b0_rd_colps_q[0] = dram_Ch1_l2b0_rd_colps_q_0;
5082 dram_Ch1_l2b0_rd_colps_q[1] = dram_Ch1_l2b0_rd_colps_q_1;
5083 dram_Ch1_l2b0_rd_colps_q[2] = dram_Ch1_l2b0_rd_colps_q_2;
5084 dram_Ch1_l2b0_rd_colps_q[3] = dram_Ch1_l2b0_rd_colps_q_3;
5085 dram_Ch1_l2b0_rd_colps_q[4] = dram_Ch1_l2b0_rd_colps_q_4;
5086 dram_Ch1_l2b0_rd_colps_q[5] = dram_Ch1_l2b0_rd_colps_q_5;
5087 dram_Ch1_l2b0_rd_colps_q[6] = dram_Ch1_l2b0_rd_colps_q_6;
5088 dram_Ch1_l2b0_rd_colps_q[7] = dram_Ch1_l2b0_rd_colps_q_7;
5089 end
5090end
5091always @( dram_Ch1_l2b1_rd_colps_q_0 or dram_Ch1_l2b1_rd_colps_q_1 or dram_Ch1_l2b1_rd_colps_q_2 or
5092 dram_Ch1_l2b1_rd_colps_q_3 or dram_Ch1_l2b1_rd_colps_q_4 or dram_Ch1_l2b1_rd_colps_q_5 or
5093 dram_Ch1_l2b1_rd_colps_q_6 or dram_Ch1_l2b1_rd_colps_q_7 or dram_rst_l)
5094begin
5095 if(~dram_rst_l)
5096 begin
5097 dram_Ch1_l2b1_rd_colps_q[0] = 0;
5098 dram_Ch1_l2b1_rd_colps_q[1] = 0;
5099 dram_Ch1_l2b1_rd_colps_q[2] = 0;
5100 dram_Ch1_l2b1_rd_colps_q[3] = 0;
5101 dram_Ch1_l2b1_rd_colps_q[4] = 0;
5102 dram_Ch1_l2b1_rd_colps_q[5] = 0;
5103 dram_Ch1_l2b1_rd_colps_q[6] = 0;
5104 dram_Ch1_l2b1_rd_colps_q[7] = 0;
5105 end
5106 else
5107 begin
5108 dram_Ch1_l2b1_rd_colps_q[0] = dram_Ch1_l2b1_rd_colps_q_0;
5109 dram_Ch1_l2b1_rd_colps_q[1] = dram_Ch1_l2b1_rd_colps_q_1;
5110 dram_Ch1_l2b1_rd_colps_q[2] = dram_Ch1_l2b1_rd_colps_q_2;
5111 dram_Ch1_l2b1_rd_colps_q[3] = dram_Ch1_l2b1_rd_colps_q_3;
5112 dram_Ch1_l2b1_rd_colps_q[4] = dram_Ch1_l2b1_rd_colps_q_4;
5113 dram_Ch1_l2b1_rd_colps_q[5] = dram_Ch1_l2b1_rd_colps_q_5;
5114 dram_Ch1_l2b1_rd_colps_q[6] = dram_Ch1_l2b1_rd_colps_q_6;
5115 dram_Ch1_l2b1_rd_colps_q[7] = dram_Ch1_l2b1_rd_colps_q_7;
5116 end
5117end
5118always @( dram_Ch2_l2b0_rd_colps_q_0 or dram_Ch2_l2b0_rd_colps_q_1 or dram_Ch2_l2b0_rd_colps_q_2 or
5119 dram_Ch2_l2b0_rd_colps_q_3 or dram_Ch2_l2b0_rd_colps_q_4 or dram_Ch2_l2b0_rd_colps_q_5 or
5120 dram_Ch2_l2b0_rd_colps_q_6 or dram_Ch2_l2b0_rd_colps_q_7 or dram_rst_l)
5121begin
5122 if(~dram_rst_l)
5123 begin
5124 dram_Ch2_l2b0_rd_colps_q[0] = 0;
5125 dram_Ch2_l2b0_rd_colps_q[1] = 0;
5126 dram_Ch2_l2b0_rd_colps_q[2] = 0;
5127 dram_Ch2_l2b0_rd_colps_q[3] = 0;
5128 dram_Ch2_l2b0_rd_colps_q[4] = 0;
5129 dram_Ch2_l2b0_rd_colps_q[5] = 0;
5130 dram_Ch2_l2b0_rd_colps_q[6] = 0;
5131 dram_Ch2_l2b0_rd_colps_q[7] = 0;
5132 end
5133 else
5134 begin
5135 dram_Ch2_l2b0_rd_colps_q[0] = dram_Ch2_l2b0_rd_colps_q_0;
5136 dram_Ch2_l2b0_rd_colps_q[1] = dram_Ch2_l2b0_rd_colps_q_1;
5137 dram_Ch2_l2b0_rd_colps_q[2] = dram_Ch2_l2b0_rd_colps_q_2;
5138 dram_Ch2_l2b0_rd_colps_q[3] = dram_Ch2_l2b0_rd_colps_q_3;
5139 dram_Ch2_l2b0_rd_colps_q[4] = dram_Ch2_l2b0_rd_colps_q_4;
5140 dram_Ch2_l2b0_rd_colps_q[5] = dram_Ch2_l2b0_rd_colps_q_5;
5141 dram_Ch2_l2b0_rd_colps_q[6] = dram_Ch2_l2b0_rd_colps_q_6;
5142 dram_Ch2_l2b0_rd_colps_q[7] = dram_Ch2_l2b0_rd_colps_q_7;
5143 end
5144end
5145always @( dram_Ch2_l2b1_rd_colps_q_0 or dram_Ch2_l2b1_rd_colps_q_1 or dram_Ch2_l2b1_rd_colps_q_2 or
5146 dram_Ch2_l2b1_rd_colps_q_3 or dram_Ch2_l2b1_rd_colps_q_4 or dram_Ch2_l2b1_rd_colps_q_5 or
5147 dram_Ch2_l2b1_rd_colps_q_6 or dram_Ch2_l2b1_rd_colps_q_7 or dram_rst_l)
5148begin
5149 if(~dram_rst_l)
5150 begin
5151 dram_Ch2_l2b1_rd_colps_q[0] = 0;
5152 dram_Ch2_l2b1_rd_colps_q[1] = 0;
5153 dram_Ch2_l2b1_rd_colps_q[2] = 0;
5154 dram_Ch2_l2b1_rd_colps_q[3] = 0;
5155 dram_Ch2_l2b1_rd_colps_q[4] = 0;
5156 dram_Ch2_l2b1_rd_colps_q[5] = 0;
5157 dram_Ch2_l2b1_rd_colps_q[6] = 0;
5158 dram_Ch2_l2b1_rd_colps_q[7] = 0;
5159 end
5160 else
5161 begin
5162 dram_Ch2_l2b1_rd_colps_q[0] = dram_Ch2_l2b1_rd_colps_q_0;
5163 dram_Ch2_l2b1_rd_colps_q[1] = dram_Ch2_l2b1_rd_colps_q_1;
5164 dram_Ch2_l2b1_rd_colps_q[2] = dram_Ch2_l2b1_rd_colps_q_2;
5165 dram_Ch2_l2b1_rd_colps_q[3] = dram_Ch2_l2b1_rd_colps_q_3;
5166 dram_Ch2_l2b1_rd_colps_q[4] = dram_Ch2_l2b1_rd_colps_q_4;
5167 dram_Ch2_l2b1_rd_colps_q[5] = dram_Ch2_l2b1_rd_colps_q_5;
5168 dram_Ch2_l2b1_rd_colps_q[6] = dram_Ch2_l2b1_rd_colps_q_6;
5169 dram_Ch2_l2b1_rd_colps_q[7] = dram_Ch2_l2b1_rd_colps_q_7;
5170 end
5171end
5172always @( dram_Ch3_l2b0_rd_colps_q_0 or dram_Ch3_l2b0_rd_colps_q_1 or dram_Ch3_l2b0_rd_colps_q_2 or
5173 dram_Ch3_l2b0_rd_colps_q_3 or dram_Ch3_l2b0_rd_colps_q_4 or dram_Ch3_l2b0_rd_colps_q_5 or
5174 dram_Ch3_l2b0_rd_colps_q_6 or dram_Ch3_l2b0_rd_colps_q_7 or dram_rst_l)
5175begin
5176 if(~dram_rst_l)
5177 begin
5178 dram_Ch3_l2b0_rd_colps_q[0] = 0;
5179 dram_Ch3_l2b0_rd_colps_q[1] = 0;
5180 dram_Ch3_l2b0_rd_colps_q[2] = 0;
5181 dram_Ch3_l2b0_rd_colps_q[3] = 0;
5182 dram_Ch3_l2b0_rd_colps_q[4] = 0;
5183 dram_Ch3_l2b0_rd_colps_q[5] = 0;
5184 dram_Ch3_l2b0_rd_colps_q[6] = 0;
5185 dram_Ch3_l2b0_rd_colps_q[7] = 0;
5186 end
5187 else
5188 begin
5189 dram_Ch3_l2b0_rd_colps_q[0] = dram_Ch3_l2b0_rd_colps_q_0;
5190 dram_Ch3_l2b0_rd_colps_q[1] = dram_Ch3_l2b0_rd_colps_q_1;
5191 dram_Ch3_l2b0_rd_colps_q[2] = dram_Ch3_l2b0_rd_colps_q_2;
5192 dram_Ch3_l2b0_rd_colps_q[3] = dram_Ch3_l2b0_rd_colps_q_3;
5193 dram_Ch3_l2b0_rd_colps_q[4] = dram_Ch3_l2b0_rd_colps_q_4;
5194 dram_Ch3_l2b0_rd_colps_q[5] = dram_Ch3_l2b0_rd_colps_q_5;
5195 dram_Ch3_l2b0_rd_colps_q[6] = dram_Ch3_l2b0_rd_colps_q_6;
5196 dram_Ch3_l2b0_rd_colps_q[7] = dram_Ch3_l2b0_rd_colps_q_7;
5197 end
5198end
5199always @( dram_Ch3_l2b1_rd_colps_q_0 or dram_Ch3_l2b1_rd_colps_q_1 or dram_Ch3_l2b1_rd_colps_q_2 or
5200 dram_Ch3_l2b1_rd_colps_q_3 or dram_Ch3_l2b1_rd_colps_q_4 or dram_Ch3_l2b1_rd_colps_q_5 or
5201 dram_Ch3_l2b1_rd_colps_q_6 or dram_Ch3_l2b1_rd_colps_q_7 or dram_rst_l)
5202begin
5203 if(~dram_rst_l)
5204 begin
5205 dram_Ch3_l2b1_rd_colps_q[0] = 0;
5206 dram_Ch3_l2b1_rd_colps_q[1] = 0;
5207 dram_Ch3_l2b1_rd_colps_q[2] = 0;
5208 dram_Ch3_l2b1_rd_colps_q[3] = 0;
5209 dram_Ch3_l2b1_rd_colps_q[4] = 0;
5210 dram_Ch3_l2b1_rd_colps_q[5] = 0;
5211 dram_Ch3_l2b1_rd_colps_q[6] = 0;
5212 dram_Ch3_l2b1_rd_colps_q[7] = 0;
5213 end
5214 else
5215 begin
5216 dram_Ch3_l2b1_rd_colps_q[0] = dram_Ch3_l2b1_rd_colps_q_0;
5217 dram_Ch3_l2b1_rd_colps_q[1] = dram_Ch3_l2b1_rd_colps_q_1;
5218 dram_Ch3_l2b1_rd_colps_q[2] = dram_Ch3_l2b1_rd_colps_q_2;
5219 dram_Ch3_l2b1_rd_colps_q[3] = dram_Ch3_l2b1_rd_colps_q_3;
5220 dram_Ch3_l2b1_rd_colps_q[4] = dram_Ch3_l2b1_rd_colps_q_4;
5221 dram_Ch3_l2b1_rd_colps_q[5] = dram_Ch3_l2b1_rd_colps_q_5;
5222 dram_Ch3_l2b1_rd_colps_q[6] = dram_Ch3_l2b1_rd_colps_q_6;
5223 dram_Ch3_l2b1_rd_colps_q[7] = dram_Ch3_l2b1_rd_colps_q_7;
5224 end
5225end
5226
5227
5228// ------ WR Q -------
5229
5230always @(dram_Ch0_l2b0_wr_q_0 or dram_Ch0_l2b0_wr_q_1 or dram_Ch0_l2b0_wr_q_2 or dram_Ch0_l2b0_wr_q_3 or
5231 dram_Ch0_l2b0_wr_q_4 or dram_Ch0_l2b0_wr_q_5 or dram_Ch0_l2b0_wr_q_6 or dram_Ch0_l2b0_wr_q_7 or
5232 dram_rst_l)
5233begin
5234 dram_Ch0_l2b0_wr_q[0] = dram_Ch0_l2b0_wr_q_0;
5235 dram_Ch0_l2b0_wr_q[1] = dram_Ch0_l2b0_wr_q_1;
5236 dram_Ch0_l2b0_wr_q[2] = dram_Ch0_l2b0_wr_q_2;
5237 dram_Ch0_l2b0_wr_q[3] = dram_Ch0_l2b0_wr_q_3;
5238 dram_Ch0_l2b0_wr_q[4] = dram_Ch0_l2b0_wr_q_4;
5239 dram_Ch0_l2b0_wr_q[5] = dram_Ch0_l2b0_wr_q_5;
5240 dram_Ch0_l2b0_wr_q[6] = dram_Ch0_l2b0_wr_q_6;
5241 dram_Ch0_l2b0_wr_q[7] = dram_Ch0_l2b0_wr_q_7;
5242end
5243always @(dram_Ch0_l2b1_wr_q_0 or dram_Ch0_l2b1_wr_q_1 or dram_Ch0_l2b1_wr_q_2 or dram_Ch0_l2b1_wr_q_3 or
5244 dram_Ch0_l2b1_wr_q_4 or dram_Ch0_l2b1_wr_q_5 or dram_Ch0_l2b1_wr_q_6 or dram_Ch0_l2b1_wr_q_7 or
5245 dram_rst_l)
5246begin
5247 dram_Ch0_l2b1_wr_q[0] = dram_Ch0_l2b1_wr_q_0;
5248 dram_Ch0_l2b1_wr_q[1] = dram_Ch0_l2b1_wr_q_1;
5249 dram_Ch0_l2b1_wr_q[2] = dram_Ch0_l2b1_wr_q_2;
5250 dram_Ch0_l2b1_wr_q[3] = dram_Ch0_l2b1_wr_q_3;
5251 dram_Ch0_l2b1_wr_q[4] = dram_Ch0_l2b1_wr_q_4;
5252 dram_Ch0_l2b1_wr_q[5] = dram_Ch0_l2b1_wr_q_5;
5253 dram_Ch0_l2b1_wr_q[6] = dram_Ch0_l2b1_wr_q_6;
5254 dram_Ch0_l2b1_wr_q[7] = dram_Ch0_l2b1_wr_q_7;
5255end
5256always @(dram_Ch1_l2b0_wr_q_0 or dram_Ch1_l2b0_wr_q_1 or dram_Ch1_l2b0_wr_q_2 or dram_Ch1_l2b0_wr_q_3 or
5257 dram_Ch1_l2b0_wr_q_4 or dram_Ch1_l2b0_wr_q_5 or dram_Ch1_l2b0_wr_q_6 or dram_Ch1_l2b0_wr_q_7 or
5258 dram_rst_l)
5259begin
5260 dram_Ch1_l2b0_wr_q[0] = dram_Ch1_l2b0_wr_q_0;
5261 dram_Ch1_l2b0_wr_q[1] = dram_Ch1_l2b0_wr_q_1;
5262 dram_Ch1_l2b0_wr_q[2] = dram_Ch1_l2b0_wr_q_2;
5263 dram_Ch1_l2b0_wr_q[3] = dram_Ch1_l2b0_wr_q_3;
5264 dram_Ch1_l2b0_wr_q[4] = dram_Ch1_l2b0_wr_q_4;
5265 dram_Ch1_l2b0_wr_q[5] = dram_Ch1_l2b0_wr_q_5;
5266 dram_Ch1_l2b0_wr_q[6] = dram_Ch1_l2b0_wr_q_6;
5267 dram_Ch1_l2b0_wr_q[7] = dram_Ch1_l2b0_wr_q_7;
5268end
5269always @(dram_Ch1_l2b1_wr_q_0 or dram_Ch1_l2b1_wr_q_1 or dram_Ch1_l2b1_wr_q_2 or dram_Ch1_l2b1_wr_q_3 or
5270 dram_Ch1_l2b1_wr_q_4 or dram_Ch1_l2b1_wr_q_5 or dram_Ch1_l2b1_wr_q_6 or dram_Ch1_l2b1_wr_q_7 or
5271 dram_rst_l)
5272begin
5273 dram_Ch1_l2b1_wr_q[0] = dram_Ch1_l2b1_wr_q_0;
5274 dram_Ch1_l2b1_wr_q[1] = dram_Ch1_l2b1_wr_q_1;
5275 dram_Ch1_l2b1_wr_q[2] = dram_Ch1_l2b1_wr_q_2;
5276 dram_Ch1_l2b1_wr_q[3] = dram_Ch1_l2b1_wr_q_3;
5277 dram_Ch1_l2b1_wr_q[4] = dram_Ch1_l2b1_wr_q_4;
5278 dram_Ch1_l2b1_wr_q[5] = dram_Ch1_l2b1_wr_q_5;
5279 dram_Ch1_l2b1_wr_q[6] = dram_Ch1_l2b1_wr_q_6;
5280 dram_Ch1_l2b1_wr_q[7] = dram_Ch1_l2b1_wr_q_7;
5281end
5282always @(dram_Ch2_l2b0_wr_q_0 or dram_Ch2_l2b0_wr_q_1 or dram_Ch2_l2b0_wr_q_2 or dram_Ch2_l2b0_wr_q_3 or
5283 dram_Ch2_l2b0_wr_q_4 or dram_Ch2_l2b0_wr_q_5 or dram_Ch2_l2b0_wr_q_6 or dram_Ch2_l2b0_wr_q_7 or
5284 dram_rst_l)
5285begin
5286 dram_Ch2_l2b0_wr_q[0] = dram_Ch2_l2b0_wr_q_0;
5287 dram_Ch2_l2b0_wr_q[1] = dram_Ch2_l2b0_wr_q_1;
5288 dram_Ch2_l2b0_wr_q[2] = dram_Ch2_l2b0_wr_q_2;
5289 dram_Ch2_l2b0_wr_q[3] = dram_Ch2_l2b0_wr_q_3;
5290 dram_Ch2_l2b0_wr_q[4] = dram_Ch2_l2b0_wr_q_4;
5291 dram_Ch2_l2b0_wr_q[5] = dram_Ch2_l2b0_wr_q_5;
5292 dram_Ch2_l2b0_wr_q[6] = dram_Ch2_l2b0_wr_q_6;
5293 dram_Ch2_l2b0_wr_q[7] = dram_Ch2_l2b0_wr_q_7;
5294end
5295always @(dram_Ch2_l2b1_wr_q_0 or dram_Ch2_l2b1_wr_q_1 or dram_Ch2_l2b1_wr_q_2 or dram_Ch2_l2b1_wr_q_3 or
5296 dram_Ch2_l2b1_wr_q_4 or dram_Ch2_l2b1_wr_q_5 or dram_Ch2_l2b1_wr_q_6 or dram_Ch2_l2b1_wr_q_7 or
5297 dram_rst_l)
5298begin
5299 dram_Ch2_l2b1_wr_q[0] = dram_Ch2_l2b1_wr_q_0;
5300 dram_Ch2_l2b1_wr_q[1] = dram_Ch2_l2b1_wr_q_1;
5301 dram_Ch2_l2b1_wr_q[2] = dram_Ch2_l2b1_wr_q_2;
5302 dram_Ch2_l2b1_wr_q[3] = dram_Ch2_l2b1_wr_q_3;
5303 dram_Ch2_l2b1_wr_q[4] = dram_Ch2_l2b1_wr_q_4;
5304 dram_Ch2_l2b1_wr_q[5] = dram_Ch2_l2b1_wr_q_5;
5305 dram_Ch2_l2b1_wr_q[6] = dram_Ch2_l2b1_wr_q_6;
5306 dram_Ch2_l2b1_wr_q[7] = dram_Ch2_l2b1_wr_q_7;
5307end
5308always @(dram_Ch3_l2b0_wr_q_0 or dram_Ch3_l2b0_wr_q_1 or dram_Ch3_l2b0_wr_q_2 or dram_Ch3_l2b0_wr_q_3 or
5309 dram_Ch3_l2b0_wr_q_4 or dram_Ch3_l2b0_wr_q_5 or dram_Ch3_l2b0_wr_q_6 or dram_Ch3_l2b0_wr_q_7 or
5310 dram_rst_l)
5311begin
5312 dram_Ch3_l2b0_wr_q[0] = dram_Ch3_l2b0_wr_q_0;
5313 dram_Ch3_l2b0_wr_q[1] = dram_Ch3_l2b0_wr_q_1;
5314 dram_Ch3_l2b0_wr_q[2] = dram_Ch3_l2b0_wr_q_2;
5315 dram_Ch3_l2b0_wr_q[3] = dram_Ch3_l2b0_wr_q_3;
5316 dram_Ch3_l2b0_wr_q[4] = dram_Ch3_l2b0_wr_q_4;
5317 dram_Ch3_l2b0_wr_q[5] = dram_Ch3_l2b0_wr_q_5;
5318 dram_Ch3_l2b0_wr_q[6] = dram_Ch3_l2b0_wr_q_6;
5319 dram_Ch3_l2b0_wr_q[7] = dram_Ch3_l2b0_wr_q_7;
5320end
5321always @(dram_Ch3_l2b1_wr_q_0 or dram_Ch3_l2b1_wr_q_1 or dram_Ch3_l2b1_wr_q_2 or dram_Ch3_l2b1_wr_q_3 or
5322 dram_Ch3_l2b1_wr_q_4 or dram_Ch3_l2b1_wr_q_5 or dram_Ch3_l2b1_wr_q_6 or dram_Ch3_l2b1_wr_q_7 or
5323 dram_rst_l)
5324begin
5325 dram_Ch3_l2b1_wr_q[0] = dram_Ch3_l2b1_wr_q_0;
5326 dram_Ch3_l2b1_wr_q[1] = dram_Ch3_l2b1_wr_q_1;
5327 dram_Ch3_l2b1_wr_q[2] = dram_Ch3_l2b1_wr_q_2;
5328 dram_Ch3_l2b1_wr_q[3] = dram_Ch3_l2b1_wr_q_3;
5329 dram_Ch3_l2b1_wr_q[4] = dram_Ch3_l2b1_wr_q_4;
5330 dram_Ch3_l2b1_wr_q[5] = dram_Ch3_l2b1_wr_q_5;
5331 dram_Ch3_l2b1_wr_q[6] = dram_Ch3_l2b1_wr_q_6;
5332 dram_Ch3_l2b1_wr_q[7] = dram_Ch3_l2b1_wr_q_7;
5333end
5334
5335// ---- WR COLPS FIFO ----
5336
5337always @( dram_Ch0_l2b0_wr_colps_q_0 or dram_Ch0_l2b0_wr_colps_q_1 or dram_Ch0_l2b0_wr_colps_q_2 or
5338 dram_Ch0_l2b0_wr_colps_q_3 or dram_Ch0_l2b0_wr_colps_q_4 or dram_Ch0_l2b0_wr_colps_q_5 or
5339 dram_Ch0_l2b0_wr_colps_q_6 or dram_Ch0_l2b0_wr_colps_q_7 or dram_rst_l)
5340begin
5341 dram_Ch0_l2b0_wr_colps_q[0] = dram_Ch0_l2b0_wr_colps_q_0;
5342 dram_Ch0_l2b0_wr_colps_q[1] = dram_Ch0_l2b0_wr_colps_q_1;
5343 dram_Ch0_l2b0_wr_colps_q[2] = dram_Ch0_l2b0_wr_colps_q_2;
5344 dram_Ch0_l2b0_wr_colps_q[3] = dram_Ch0_l2b0_wr_colps_q_3;
5345 dram_Ch0_l2b0_wr_colps_q[4] = dram_Ch0_l2b0_wr_colps_q_4;
5346 dram_Ch0_l2b0_wr_colps_q[5] = dram_Ch0_l2b0_wr_colps_q_5;
5347 dram_Ch0_l2b0_wr_colps_q[6] = dram_Ch0_l2b0_wr_colps_q_6;
5348 dram_Ch0_l2b0_wr_colps_q[7] = dram_Ch0_l2b0_wr_colps_q_7;
5349end
5350always @( dram_Ch0_l2b1_wr_colps_q_0 or dram_Ch0_l2b1_wr_colps_q_1 or dram_Ch0_l2b1_wr_colps_q_2 or
5351 dram_Ch0_l2b1_wr_colps_q_3 or dram_Ch0_l2b1_wr_colps_q_4 or dram_Ch0_l2b1_wr_colps_q_5 or
5352 dram_Ch0_l2b1_wr_colps_q_6 or dram_Ch0_l2b1_wr_colps_q_7 or dram_rst_l)
5353begin
5354 dram_Ch0_l2b1_wr_colps_q[0] = dram_Ch0_l2b1_wr_colps_q_0;
5355 dram_Ch0_l2b1_wr_colps_q[1] = dram_Ch0_l2b1_wr_colps_q_1;
5356 dram_Ch0_l2b1_wr_colps_q[2] = dram_Ch0_l2b1_wr_colps_q_2;
5357 dram_Ch0_l2b1_wr_colps_q[3] = dram_Ch0_l2b1_wr_colps_q_3;
5358 dram_Ch0_l2b1_wr_colps_q[4] = dram_Ch0_l2b1_wr_colps_q_4;
5359 dram_Ch0_l2b1_wr_colps_q[5] = dram_Ch0_l2b1_wr_colps_q_5;
5360 dram_Ch0_l2b1_wr_colps_q[6] = dram_Ch0_l2b1_wr_colps_q_6;
5361 dram_Ch0_l2b1_wr_colps_q[7] = dram_Ch0_l2b1_wr_colps_q_7;
5362end
5363always @( dram_Ch1_l2b0_wr_colps_q_0 or dram_Ch1_l2b0_wr_colps_q_1 or dram_Ch1_l2b0_wr_colps_q_2 or
5364 dram_Ch1_l2b0_wr_colps_q_3 or dram_Ch1_l2b0_wr_colps_q_4 or dram_Ch1_l2b0_wr_colps_q_5 or
5365 dram_Ch1_l2b0_wr_colps_q_6 or dram_Ch1_l2b0_wr_colps_q_7 or dram_rst_l)
5366begin
5367 dram_Ch1_l2b0_wr_colps_q[0] = dram_Ch1_l2b0_wr_colps_q_0;
5368 dram_Ch1_l2b0_wr_colps_q[1] = dram_Ch1_l2b0_wr_colps_q_1;
5369 dram_Ch1_l2b0_wr_colps_q[2] = dram_Ch1_l2b0_wr_colps_q_2;
5370 dram_Ch1_l2b0_wr_colps_q[3] = dram_Ch1_l2b0_wr_colps_q_3;
5371 dram_Ch1_l2b0_wr_colps_q[4] = dram_Ch1_l2b0_wr_colps_q_4;
5372 dram_Ch1_l2b0_wr_colps_q[5] = dram_Ch1_l2b0_wr_colps_q_5;
5373 dram_Ch1_l2b0_wr_colps_q[6] = dram_Ch1_l2b0_wr_colps_q_6;
5374 dram_Ch1_l2b0_wr_colps_q[7] = dram_Ch1_l2b0_wr_colps_q_7;
5375end
5376always @( dram_Ch1_l2b1_wr_colps_q_0 or dram_Ch1_l2b1_wr_colps_q_1 or dram_Ch1_l2b1_wr_colps_q_2 or
5377 dram_Ch1_l2b1_wr_colps_q_3 or dram_Ch1_l2b1_wr_colps_q_4 or dram_Ch1_l2b1_wr_colps_q_5 or
5378 dram_Ch1_l2b1_wr_colps_q_6 or dram_Ch1_l2b1_wr_colps_q_7 or dram_rst_l)
5379begin
5380 dram_Ch1_l2b1_wr_colps_q[0] = dram_Ch1_l2b1_wr_colps_q_0;
5381 dram_Ch1_l2b1_wr_colps_q[1] = dram_Ch1_l2b1_wr_colps_q_1;
5382 dram_Ch1_l2b1_wr_colps_q[2] = dram_Ch1_l2b1_wr_colps_q_2;
5383 dram_Ch1_l2b1_wr_colps_q[3] = dram_Ch1_l2b1_wr_colps_q_3;
5384 dram_Ch1_l2b1_wr_colps_q[4] = dram_Ch1_l2b1_wr_colps_q_4;
5385 dram_Ch1_l2b1_wr_colps_q[5] = dram_Ch1_l2b1_wr_colps_q_5;
5386 dram_Ch1_l2b1_wr_colps_q[6] = dram_Ch1_l2b1_wr_colps_q_6;
5387 dram_Ch1_l2b1_wr_colps_q[7] = dram_Ch1_l2b1_wr_colps_q_7;
5388end
5389always @( dram_Ch2_l2b0_wr_colps_q_0 or dram_Ch2_l2b0_wr_colps_q_1 or dram_Ch2_l2b0_wr_colps_q_2 or
5390 dram_Ch2_l2b0_wr_colps_q_3 or dram_Ch2_l2b0_wr_colps_q_4 or dram_Ch2_l2b0_wr_colps_q_5 or
5391 dram_Ch2_l2b0_wr_colps_q_6 or dram_Ch2_l2b0_wr_colps_q_7 or dram_rst_l)
5392begin
5393 dram_Ch2_l2b0_wr_colps_q[0] = dram_Ch2_l2b0_wr_colps_q_0;
5394 dram_Ch2_l2b0_wr_colps_q[1] = dram_Ch2_l2b0_wr_colps_q_1;
5395 dram_Ch2_l2b0_wr_colps_q[2] = dram_Ch2_l2b0_wr_colps_q_2;
5396 dram_Ch2_l2b0_wr_colps_q[3] = dram_Ch2_l2b0_wr_colps_q_3;
5397 dram_Ch2_l2b0_wr_colps_q[4] = dram_Ch2_l2b0_wr_colps_q_4;
5398 dram_Ch2_l2b0_wr_colps_q[5] = dram_Ch2_l2b0_wr_colps_q_5;
5399 dram_Ch2_l2b0_wr_colps_q[6] = dram_Ch2_l2b0_wr_colps_q_6;
5400 dram_Ch2_l2b0_wr_colps_q[7] = dram_Ch2_l2b0_wr_colps_q_7;
5401end
5402always @( dram_Ch2_l2b1_wr_colps_q_0 or dram_Ch2_l2b1_wr_colps_q_1 or dram_Ch2_l2b1_wr_colps_q_2 or
5403 dram_Ch2_l2b1_wr_colps_q_3 or dram_Ch2_l2b1_wr_colps_q_4 or dram_Ch2_l2b1_wr_colps_q_5 or
5404 dram_Ch2_l2b1_wr_colps_q_6 or dram_Ch2_l2b1_wr_colps_q_7 or dram_rst_l)
5405begin
5406 dram_Ch2_l2b1_wr_colps_q[0] = dram_Ch2_l2b1_wr_colps_q_0;
5407 dram_Ch2_l2b1_wr_colps_q[1] = dram_Ch2_l2b1_wr_colps_q_1;
5408 dram_Ch2_l2b1_wr_colps_q[2] = dram_Ch2_l2b1_wr_colps_q_2;
5409 dram_Ch2_l2b1_wr_colps_q[3] = dram_Ch2_l2b1_wr_colps_q_3;
5410 dram_Ch2_l2b1_wr_colps_q[4] = dram_Ch2_l2b1_wr_colps_q_4;
5411 dram_Ch2_l2b1_wr_colps_q[5] = dram_Ch2_l2b1_wr_colps_q_5;
5412 dram_Ch2_l2b1_wr_colps_q[6] = dram_Ch2_l2b1_wr_colps_q_6;
5413 dram_Ch2_l2b1_wr_colps_q[7] = dram_Ch2_l2b1_wr_colps_q_7;
5414end
5415always @( dram_Ch3_l2b0_wr_colps_q_0 or dram_Ch3_l2b0_wr_colps_q_1 or dram_Ch3_l2b0_wr_colps_q_2 or
5416 dram_Ch3_l2b0_wr_colps_q_3 or dram_Ch3_l2b0_wr_colps_q_4 or dram_Ch3_l2b0_wr_colps_q_5 or
5417 dram_Ch3_l2b0_wr_colps_q_6 or dram_Ch3_l2b0_wr_colps_q_7 or dram_rst_l)
5418begin
5419 dram_Ch3_l2b0_wr_colps_q[0] = dram_Ch3_l2b0_wr_colps_q_0;
5420 dram_Ch3_l2b0_wr_colps_q[1] = dram_Ch3_l2b0_wr_colps_q_1;
5421 dram_Ch3_l2b0_wr_colps_q[2] = dram_Ch3_l2b0_wr_colps_q_2;
5422 dram_Ch3_l2b0_wr_colps_q[3] = dram_Ch3_l2b0_wr_colps_q_3;
5423 dram_Ch3_l2b0_wr_colps_q[4] = dram_Ch3_l2b0_wr_colps_q_4;
5424 dram_Ch3_l2b0_wr_colps_q[5] = dram_Ch3_l2b0_wr_colps_q_5;
5425 dram_Ch3_l2b0_wr_colps_q[6] = dram_Ch3_l2b0_wr_colps_q_6;
5426 dram_Ch3_l2b0_wr_colps_q[7] = dram_Ch3_l2b0_wr_colps_q_7;
5427end
5428always @( dram_Ch3_l2b1_wr_colps_q_0 or dram_Ch3_l2b1_wr_colps_q_1 or dram_Ch3_l2b1_wr_colps_q_2 or
5429 dram_Ch3_l2b1_wr_colps_q_3 or dram_Ch3_l2b1_wr_colps_q_4 or dram_Ch3_l2b1_wr_colps_q_5 or
5430 dram_Ch3_l2b1_wr_colps_q_6 or dram_Ch3_l2b1_wr_colps_q_7 or dram_rst_l)
5431begin
5432 dram_Ch3_l2b1_wr_colps_q[0] = dram_Ch3_l2b1_wr_colps_q_0;
5433 dram_Ch3_l2b1_wr_colps_q[1] = dram_Ch3_l2b1_wr_colps_q_1;
5434 dram_Ch3_l2b1_wr_colps_q[2] = dram_Ch3_l2b1_wr_colps_q_2;
5435 dram_Ch3_l2b1_wr_colps_q[3] = dram_Ch3_l2b1_wr_colps_q_3;
5436 dram_Ch3_l2b1_wr_colps_q[4] = dram_Ch3_l2b1_wr_colps_q_4;
5437 dram_Ch3_l2b1_wr_colps_q[5] = dram_Ch3_l2b1_wr_colps_q_5;
5438 dram_Ch3_l2b1_wr_colps_q[6] = dram_Ch3_l2b1_wr_colps_q_6;
5439 dram_Ch3_l2b1_wr_colps_q[7] = dram_Ch3_l2b1_wr_colps_q_7;
5440end
5441
5442// ---- WR COLPS FIFO -----
5443
5444always @( dram_Ch0_b0_phy_bank_bits or dram_Ch0_b1_phy_bank_bits or dram_Ch0_b2_phy_bank_bits or
5445 dram_Ch0_b3_phy_bank_bits or dram_Ch0_b4_phy_bank_bits or dram_Ch0_b5_phy_bank_bits or
5446 dram_Ch0_b6_phy_bank_bits or dram_Ch0_b7_phy_bank_bits or dram_rst_l)
5447begin
5448 dram_Ch0_b_phy_bank_bits[0] = dram_Ch0_b0_phy_bank_bits;
5449 dram_Ch0_b_phy_bank_bits[1] = dram_Ch0_b1_phy_bank_bits;
5450 dram_Ch0_b_phy_bank_bits[2] = dram_Ch0_b2_phy_bank_bits;
5451 dram_Ch0_b_phy_bank_bits[3] = dram_Ch0_b3_phy_bank_bits;
5452 dram_Ch0_b_phy_bank_bits[4] = dram_Ch0_b4_phy_bank_bits;
5453 dram_Ch0_b_phy_bank_bits[5] = dram_Ch0_b5_phy_bank_bits;
5454 dram_Ch0_b_phy_bank_bits[6] = dram_Ch0_b6_phy_bank_bits;
5455 dram_Ch0_b_phy_bank_bits[7] = dram_Ch0_b7_phy_bank_bits;
5456end
5457always @( dram_Ch1_b0_phy_bank_bits or dram_Ch1_b1_phy_bank_bits or dram_Ch1_b2_phy_bank_bits or
5458 dram_Ch1_b3_phy_bank_bits or dram_Ch1_b4_phy_bank_bits or dram_Ch1_b5_phy_bank_bits or
5459 dram_Ch1_b6_phy_bank_bits or dram_Ch1_b7_phy_bank_bits or dram_rst_l)
5460begin
5461 dram_Ch1_b_phy_bank_bits[0] = dram_Ch1_b0_phy_bank_bits;
5462 dram_Ch1_b_phy_bank_bits[1] = dram_Ch1_b1_phy_bank_bits;
5463 dram_Ch1_b_phy_bank_bits[2] = dram_Ch1_b2_phy_bank_bits;
5464 dram_Ch1_b_phy_bank_bits[3] = dram_Ch1_b3_phy_bank_bits;
5465 dram_Ch1_b_phy_bank_bits[4] = dram_Ch1_b4_phy_bank_bits;
5466 dram_Ch1_b_phy_bank_bits[5] = dram_Ch1_b5_phy_bank_bits;
5467 dram_Ch1_b_phy_bank_bits[6] = dram_Ch1_b6_phy_bank_bits;
5468 dram_Ch1_b_phy_bank_bits[7] = dram_Ch1_b7_phy_bank_bits;
5469end
5470always @( dram_Ch2_b0_phy_bank_bits or dram_Ch2_b1_phy_bank_bits or dram_Ch2_b2_phy_bank_bits or
5471 dram_Ch2_b3_phy_bank_bits or dram_Ch2_b4_phy_bank_bits or dram_Ch2_b5_phy_bank_bits or
5472 dram_Ch2_b6_phy_bank_bits or dram_Ch2_b7_phy_bank_bits or dram_rst_l)
5473begin
5474 dram_Ch2_b_phy_bank_bits[0] = dram_Ch2_b0_phy_bank_bits;
5475 dram_Ch2_b_phy_bank_bits[1] = dram_Ch2_b1_phy_bank_bits;
5476 dram_Ch2_b_phy_bank_bits[2] = dram_Ch2_b2_phy_bank_bits;
5477 dram_Ch2_b_phy_bank_bits[3] = dram_Ch2_b3_phy_bank_bits;
5478 dram_Ch2_b_phy_bank_bits[4] = dram_Ch2_b4_phy_bank_bits;
5479 dram_Ch2_b_phy_bank_bits[5] = dram_Ch2_b5_phy_bank_bits;
5480 dram_Ch2_b_phy_bank_bits[6] = dram_Ch2_b6_phy_bank_bits;
5481 dram_Ch2_b_phy_bank_bits[7] = dram_Ch2_b7_phy_bank_bits;
5482end
5483always @( dram_Ch3_b0_phy_bank_bits or dram_Ch3_b1_phy_bank_bits or dram_Ch3_b2_phy_bank_bits or
5484 dram_Ch3_b3_phy_bank_bits or dram_Ch3_b4_phy_bank_bits or dram_Ch3_b5_phy_bank_bits or
5485 dram_Ch3_b6_phy_bank_bits or dram_Ch3_b7_phy_bank_bits or dram_rst_l)
5486begin
5487 dram_Ch3_b_phy_bank_bits[0] = dram_Ch3_b0_phy_bank_bits;
5488 dram_Ch3_b_phy_bank_bits[1] = dram_Ch3_b1_phy_bank_bits;
5489 dram_Ch3_b_phy_bank_bits[2] = dram_Ch3_b2_phy_bank_bits;
5490 dram_Ch3_b_phy_bank_bits[3] = dram_Ch3_b3_phy_bank_bits;
5491 dram_Ch3_b_phy_bank_bits[4] = dram_Ch3_b4_phy_bank_bits;
5492 dram_Ch3_b_phy_bank_bits[5] = dram_Ch3_b5_phy_bank_bits;
5493 dram_Ch3_b_phy_bank_bits[6] = dram_Ch3_b6_phy_bank_bits;
5494 dram_Ch3_b_phy_bank_bits[7] = dram_Ch3_b7_phy_bank_bits;
5495end
5496
5497
5498// --------- READ Q (MAQ : Address Q) -----------
5499
5500// detecting rd q full
5501reg dram_Ch0_l2b0_rd_q_full;
5502reg [3:0] dram_Ch0_l2b0_rd_q_cnt;
5503reg l2b0_rd_q_full_0;
5504reg [39:0] l2b0_rd_q_loc_0;
5505reg [3:0] l2b0_rd_q_cnt_0;
5506
5507always @(posedge (`MCU_CLK && enabled))
5508begin
5509 if (~dram_rst_l)
5510 begin
5511 dram_Ch0_l2b0_rd_q_full <= 1'b0;
5512 dram_Ch0_l2b0_rd_q_cnt <= 4'b0;
5513 end
5514 else
5515 begin
5516 l2b0_rd_q_full_0 = 1;
5517 l2b0_rd_q_cnt_0 = 0;
5518 for (i=0;i<8;i=i+1) begin
5519 l2b0_rd_q_loc_0 = dram_Ch0_l2b0_rd_q[i];
5520 // if the read falls on same clock as write ( request served on same clock as it was received )
5521 //l2b0_rd_q_full_0 = (l2b0_rd_q_loc_0[39] && !dram_Ch0_l2b0_rd_que_rd_ptr[i]) && l2b0_rd_q_full_0;
5522 l2b0_rd_q_full_0 = (l2b0_rd_q_loc_0[39] && l2b0_rd_q_full_0);
5523 l2b0_rd_q_cnt_0 = l2b0_rd_q_cnt_0 + (l2b0_rd_q_loc_0[39] && !dram_Ch0_l2b0_rd_que_rd_ptr[i]);
5524 end
5525 dram_Ch0_l2b0_rd_q_full <= l2b0_rd_q_full_0;
5526 dram_Ch0_l2b0_rd_q_cnt <= l2b0_rd_q_cnt_0;
5527 end
5528end
5529reg dram_Ch0_l2b1_rd_q_full;
5530reg [3:0] dram_Ch0_l2b1_rd_q_cnt;
5531reg l2b1_rd_q_full_0;
5532reg [39:0] l2b1_rd_q_loc_0;
5533reg [3:0] l2b1_rd_q_cnt_0;
5534
5535always @(posedge (`MCU_CLK && enabled))
5536begin
5537 if (~dram_rst_l)
5538 begin
5539 dram_Ch0_l2b1_rd_q_full <= 1'b0;
5540 dram_Ch0_l2b1_rd_q_cnt <= 4'b0;
5541 end
5542 else
5543 begin
5544 l2b1_rd_q_full_0 = 1;
5545 l2b1_rd_q_cnt_0 = 0;
5546 for (i=0;i<8;i=i+1) begin
5547 l2b1_rd_q_loc_0 = dram_Ch0_l2b1_rd_q[i];
5548 // if the read falls on same clock as write ( request served on same clock as it was received )
5549 //l2b1_rd_q_full_0 = (l2b1_rd_q_loc_0[39] && !dram_Ch0_l2b1_rd_que_rd_ptr[i]) && l2b1_rd_q_full_0;
5550 l2b1_rd_q_full_0 = (l2b1_rd_q_loc_0[39] && l2b1_rd_q_full_0);
5551 l2b1_rd_q_cnt_0 = l2b1_rd_q_cnt_0 + (l2b1_rd_q_loc_0[39] && !dram_Ch0_l2b1_rd_que_rd_ptr[i]);
5552 end
5553 dram_Ch0_l2b1_rd_q_full <= l2b1_rd_q_full_0;
5554 dram_Ch0_l2b1_rd_q_cnt <= l2b1_rd_q_cnt_0;
5555 end
5556end
5557reg dram_Ch1_l2b0_rd_q_full;
5558reg [3:0] dram_Ch1_l2b0_rd_q_cnt;
5559reg l2b0_rd_q_full_1;
5560reg [39:0] l2b0_rd_q_loc_1;
5561reg [3:0] l2b0_rd_q_cnt_1;
5562
5563always @(posedge (`MCU_CLK && enabled))
5564begin
5565 if (~dram_rst_l)
5566 begin
5567 dram_Ch1_l2b0_rd_q_full <= 1'b0;
5568 dram_Ch1_l2b0_rd_q_cnt <= 4'b0;
5569 end
5570 else
5571 begin
5572 l2b0_rd_q_full_1 = 1;
5573 l2b0_rd_q_cnt_1 = 0;
5574 for (i=0;i<8;i=i+1) begin
5575 l2b0_rd_q_loc_1 = dram_Ch1_l2b0_rd_q[i];
5576 // if the read falls on same clock as write ( request served on same clock as it was received )
5577 //l2b0_rd_q_full_1 = (l2b0_rd_q_loc_1[39] && !dram_Ch1_l2b0_rd_que_rd_ptr[i]) && l2b0_rd_q_full_1;
5578 l2b0_rd_q_full_1 = (l2b0_rd_q_loc_1[39] && l2b0_rd_q_full_1);
5579 l2b0_rd_q_cnt_1 = l2b0_rd_q_cnt_1 + (l2b0_rd_q_loc_1[39] && !dram_Ch1_l2b0_rd_que_rd_ptr[i]);
5580 end
5581 dram_Ch1_l2b0_rd_q_full <= l2b0_rd_q_full_1;
5582 dram_Ch1_l2b0_rd_q_cnt <= l2b0_rd_q_cnt_1;
5583 end
5584end
5585reg dram_Ch1_l2b1_rd_q_full;
5586reg [3:0] dram_Ch1_l2b1_rd_q_cnt;
5587reg l2b1_rd_q_full_1;
5588reg [39:0] l2b1_rd_q_loc_1;
5589reg [3:0] l2b1_rd_q_cnt_1;
5590
5591always @(posedge (`MCU_CLK && enabled))
5592begin
5593 if (~dram_rst_l)
5594 begin
5595 dram_Ch1_l2b1_rd_q_full <= 1'b0;
5596 dram_Ch1_l2b1_rd_q_cnt <= 4'b0;
5597 end
5598 else
5599 begin
5600 l2b1_rd_q_full_1 = 1;
5601 l2b1_rd_q_cnt_1 = 0;
5602 for (i=0;i<8;i=i+1) begin
5603 l2b1_rd_q_loc_1 = dram_Ch1_l2b1_rd_q[i];
5604 // if the read falls on same clock as write ( request served on same clock as it was received )
5605 //l2b1_rd_q_full_1 = (l2b1_rd_q_loc_1[39] && !dram_Ch1_l2b1_rd_que_rd_ptr[i]) && l2b1_rd_q_full_1;
5606 l2b1_rd_q_full_1 = (l2b1_rd_q_loc_1[39] && l2b1_rd_q_full_1);
5607 l2b1_rd_q_cnt_1 = l2b1_rd_q_cnt_1 + (l2b1_rd_q_loc_1[39] && !dram_Ch1_l2b1_rd_que_rd_ptr[i]);
5608 end
5609 dram_Ch1_l2b1_rd_q_full <= l2b1_rd_q_full_1;
5610 dram_Ch1_l2b1_rd_q_cnt <= l2b1_rd_q_cnt_1;
5611 end
5612end
5613reg dram_Ch2_l2b0_rd_q_full;
5614reg [3:0] dram_Ch2_l2b0_rd_q_cnt;
5615reg l2b0_rd_q_full_2;
5616reg [39:0] l2b0_rd_q_loc_2;
5617reg [3:0] l2b0_rd_q_cnt_2;
5618
5619always @(posedge (`MCU_CLK && enabled))
5620begin
5621 if (~dram_rst_l)
5622 begin
5623 dram_Ch2_l2b0_rd_q_full <= 1'b0;
5624 dram_Ch2_l2b0_rd_q_cnt <= 4'b0;
5625 end
5626 else
5627 begin
5628 l2b0_rd_q_full_2 = 1;
5629 l2b0_rd_q_cnt_2 = 0;
5630 for (i=0;i<8;i=i+1) begin
5631 l2b0_rd_q_loc_2 = dram_Ch2_l2b0_rd_q[i];
5632 // if the read falls on same clock as write ( request served on same clock as it was received )
5633 //l2b0_rd_q_full_2 = (l2b0_rd_q_loc_2[39] && !dram_Ch2_l2b0_rd_que_rd_ptr[i]) && l2b0_rd_q_full_2;
5634 l2b0_rd_q_full_2 = (l2b0_rd_q_loc_2[39] && l2b0_rd_q_full_2);
5635 l2b0_rd_q_cnt_2 = l2b0_rd_q_cnt_2 + (l2b0_rd_q_loc_2[39] && !dram_Ch2_l2b0_rd_que_rd_ptr[i]);
5636 end
5637 dram_Ch2_l2b0_rd_q_full <= l2b0_rd_q_full_2;
5638 dram_Ch2_l2b0_rd_q_cnt <= l2b0_rd_q_cnt_2;
5639 end
5640end
5641reg dram_Ch2_l2b1_rd_q_full;
5642reg [3:0] dram_Ch2_l2b1_rd_q_cnt;
5643reg l2b1_rd_q_full_2;
5644reg [39:0] l2b1_rd_q_loc_2;
5645reg [3:0] l2b1_rd_q_cnt_2;
5646
5647always @(posedge (`MCU_CLK && enabled))
5648begin
5649 if (~dram_rst_l)
5650 begin
5651 dram_Ch2_l2b1_rd_q_full <= 1'b0;
5652 dram_Ch2_l2b1_rd_q_cnt <= 4'b0;
5653 end
5654 else
5655 begin
5656 l2b1_rd_q_full_2 = 1;
5657 l2b1_rd_q_cnt_2 = 0;
5658 for (i=0;i<8;i=i+1) begin
5659 l2b1_rd_q_loc_2 = dram_Ch2_l2b1_rd_q[i];
5660 // if the read falls on same clock as write ( request served on same clock as it was received )
5661 //l2b1_rd_q_full_2 = (l2b1_rd_q_loc_2[39] && !dram_Ch2_l2b1_rd_que_rd_ptr[i]) && l2b1_rd_q_full_2;
5662 l2b1_rd_q_full_2 = (l2b1_rd_q_loc_2[39] && l2b1_rd_q_full_2);
5663 l2b1_rd_q_cnt_2 = l2b1_rd_q_cnt_2 + (l2b1_rd_q_loc_2[39] && !dram_Ch2_l2b1_rd_que_rd_ptr[i]);
5664 end
5665 dram_Ch2_l2b1_rd_q_full <= l2b1_rd_q_full_2;
5666 dram_Ch2_l2b1_rd_q_cnt <= l2b1_rd_q_cnt_2;
5667 end
5668end
5669reg dram_Ch3_l2b0_rd_q_full;
5670reg [3:0] dram_Ch3_l2b0_rd_q_cnt;
5671reg l2b0_rd_q_full_3;
5672reg [39:0] l2b0_rd_q_loc_3;
5673reg [3:0] l2b0_rd_q_cnt_3;
5674
5675always @(posedge (`MCU_CLK && enabled))
5676begin
5677 if (~dram_rst_l)
5678 begin
5679 dram_Ch3_l2b0_rd_q_full <= 1'b0;
5680 dram_Ch3_l2b0_rd_q_cnt <= 4'b0;
5681 end
5682 else
5683 begin
5684 l2b0_rd_q_full_3 = 1;
5685 l2b0_rd_q_cnt_3 = 0;
5686 for (i=0;i<8;i=i+1) begin
5687 l2b0_rd_q_loc_3 = dram_Ch3_l2b0_rd_q[i];
5688 // if the read falls on same clock as write ( request served on same clock as it was received )
5689 //l2b0_rd_q_full_3 = (l2b0_rd_q_loc_3[39] && !dram_Ch3_l2b0_rd_que_rd_ptr[i]) && l2b0_rd_q_full_3;
5690 l2b0_rd_q_full_3 = (l2b0_rd_q_loc_3[39] && l2b0_rd_q_full_3);
5691 l2b0_rd_q_cnt_3 = l2b0_rd_q_cnt_3 + (l2b0_rd_q_loc_3[39] && !dram_Ch3_l2b0_rd_que_rd_ptr[i]);
5692 end
5693 dram_Ch3_l2b0_rd_q_full <= l2b0_rd_q_full_3;
5694 dram_Ch3_l2b0_rd_q_cnt <= l2b0_rd_q_cnt_3;
5695 end
5696end
5697reg dram_Ch3_l2b1_rd_q_full;
5698reg [3:0] dram_Ch3_l2b1_rd_q_cnt;
5699reg l2b1_rd_q_full_3;
5700reg [39:0] l2b1_rd_q_loc_3;
5701reg [3:0] l2b1_rd_q_cnt_3;
5702
5703always @(posedge (`MCU_CLK && enabled))
5704begin
5705 if (~dram_rst_l)
5706 begin
5707 dram_Ch3_l2b1_rd_q_full <= 1'b0;
5708 dram_Ch3_l2b1_rd_q_cnt <= 4'b0;
5709 end
5710 else
5711 begin
5712 l2b1_rd_q_full_3 = 1;
5713 l2b1_rd_q_cnt_3 = 0;
5714 for (i=0;i<8;i=i+1) begin
5715 l2b1_rd_q_loc_3 = dram_Ch3_l2b1_rd_q[i];
5716 // if the read falls on same clock as write ( request served on same clock as it was received )
5717 //l2b1_rd_q_full_3 = (l2b1_rd_q_loc_3[39] && !dram_Ch3_l2b1_rd_que_rd_ptr[i]) && l2b1_rd_q_full_3;
5718 l2b1_rd_q_full_3 = (l2b1_rd_q_loc_3[39] && l2b1_rd_q_full_3);
5719 l2b1_rd_q_cnt_3 = l2b1_rd_q_cnt_3 + (l2b1_rd_q_loc_3[39] && !dram_Ch3_l2b1_rd_que_rd_ptr[i]);
5720 end
5721 dram_Ch3_l2b1_rd_q_full <= l2b1_rd_q_full_3;
5722 dram_Ch3_l2b1_rd_q_cnt <= l2b1_rd_q_cnt_3;
5723 end
5724end
5725
5726
5727// ------ RD Q LATENCY COUNTING --------
5728
5729reg [31:0] dram_Ch0_l2b0_rd_q_lat;
5730always @(posedge (`MCU_CLK && enabled))
5731begin
5732 if (dram_Ch0_que_init_dram_done)
5733 begin
5734 dram_Ch0_l2b0_rd_q_lat <= dram_Ch0_l2b0_rd_q_lat + dram_Ch0_l2b0_rd_q_cnt;
5735 end else begin
5736 dram_Ch0_l2b0_rd_q_lat <= 4'b0;
5737 end
5738end
5739reg [31:0] dram_Ch0_l2b1_rd_q_lat;
5740always @(posedge (`MCU_CLK && enabled))
5741begin
5742 if (dram_Ch0_que_init_dram_done)
5743 begin
5744 dram_Ch0_l2b1_rd_q_lat <= dram_Ch0_l2b1_rd_q_lat + dram_Ch0_l2b1_rd_q_cnt;
5745 end else begin
5746 dram_Ch0_l2b1_rd_q_lat <= 4'b0;
5747 end
5748end
5749reg [31:0] dram_Ch1_l2b0_rd_q_lat;
5750always @(posedge (`MCU_CLK && enabled))
5751begin
5752 if (dram_Ch1_que_init_dram_done)
5753 begin
5754 dram_Ch1_l2b0_rd_q_lat <= dram_Ch1_l2b0_rd_q_lat + dram_Ch1_l2b0_rd_q_cnt;
5755 end else begin
5756 dram_Ch1_l2b0_rd_q_lat <= 4'b0;
5757 end
5758end
5759reg [31:0] dram_Ch1_l2b1_rd_q_lat;
5760always @(posedge (`MCU_CLK && enabled))
5761begin
5762 if (dram_Ch1_que_init_dram_done)
5763 begin
5764 dram_Ch1_l2b1_rd_q_lat <= dram_Ch1_l2b1_rd_q_lat + dram_Ch1_l2b1_rd_q_cnt;
5765 end else begin
5766 dram_Ch1_l2b1_rd_q_lat <= 4'b0;
5767 end
5768end
5769reg [31:0] dram_Ch2_l2b0_rd_q_lat;
5770always @(posedge (`MCU_CLK && enabled))
5771begin
5772 if (dram_Ch2_que_init_dram_done)
5773 begin
5774 dram_Ch2_l2b0_rd_q_lat <= dram_Ch2_l2b0_rd_q_lat + dram_Ch2_l2b0_rd_q_cnt;
5775 end else begin
5776 dram_Ch2_l2b0_rd_q_lat <= 4'b0;
5777 end
5778end
5779reg [31:0] dram_Ch2_l2b1_rd_q_lat;
5780always @(posedge (`MCU_CLK && enabled))
5781begin
5782 if (dram_Ch2_que_init_dram_done)
5783 begin
5784 dram_Ch2_l2b1_rd_q_lat <= dram_Ch2_l2b1_rd_q_lat + dram_Ch2_l2b1_rd_q_cnt;
5785 end else begin
5786 dram_Ch2_l2b1_rd_q_lat <= 4'b0;
5787 end
5788end
5789reg [31:0] dram_Ch3_l2b0_rd_q_lat;
5790always @(posedge (`MCU_CLK && enabled))
5791begin
5792 if (dram_Ch3_que_init_dram_done)
5793 begin
5794 dram_Ch3_l2b0_rd_q_lat <= dram_Ch3_l2b0_rd_q_lat + dram_Ch3_l2b0_rd_q_cnt;
5795 end else begin
5796 dram_Ch3_l2b0_rd_q_lat <= 4'b0;
5797 end
5798end
5799reg [31:0] dram_Ch3_l2b1_rd_q_lat;
5800always @(posedge (`MCU_CLK && enabled))
5801begin
5802 if (dram_Ch3_que_init_dram_done)
5803 begin
5804 dram_Ch3_l2b1_rd_q_lat <= dram_Ch3_l2b1_rd_q_lat + dram_Ch3_l2b1_rd_q_cnt;
5805 end else begin
5806 dram_Ch3_l2b1_rd_q_lat <= 4'b0;
5807 end
5808end
5809
5810
5811// ---- DETECTING RD COLLAPSING FIFO FULL (MAQ : Read Request Q)
5812reg dram_Ch0_l2b0_rd_colps_q_full;
5813reg colps_l2b0_rd_q_full_0;
5814reg [11:0] colps_l2b0_rd_q_loc_0;
5815reg [3:0] dram_Ch0_l2b0_rd_colps_q_cnt;
5816reg [3:0] colps_l2b0_rd_q_cnt_0;
5817reg [2:0] colps_l2b0_rd_indx_0;
5818reg colps_l2b0_rd_rst_vld_0;
5819always @(posedge (`MCU_CLK && enabled))
5820begin
5821 if (~dram_rst_l)
5822 begin
5823 dram_Ch0_l2b0_rd_colps_q_full <= 1'b0;
5824 dram_Ch0_l2b0_rd_colps_q_cnt <= 1'b0;
5825 end
5826 else
5827 begin
5828 colps_l2b0_rd_q_full_0 = 1;
5829 colps_l2b0_rd_q_cnt_0 = 0;
5830 // extract the index for which the reset occured
5831 colps_l2b0_rd_rst_vld_0 = 0;
5832 for (i=0;i<8;i=i+1) begin
5833 if (dram_Ch0_l2b0_rd_que_rd_ptr[i]) begin
5834 colps_l2b0_rd_indx_0 = i;
5835 colps_l2b0_rd_rst_vld_0 = 1;
5836 end
5837 end
5838 for (i=0;i<8;i=i+1) begin
5839 colps_l2b0_rd_q_loc_0 = dram_Ch0_l2b0_rd_colps_q[i];
5840 colps_l2b0_rd_q_loc_0[6] = dram_ch0_l2b0_drq_rd_queue_valid[i];
5841 if (colps_l2b0_rd_rst_vld_0 == 1) begin
5842 if ((colps_l2b0_rd_q_loc_0[11:9] != colps_l2b0_rd_indx_0) || ~colps_l2b0_rd_q_loc_0[6]) begin
5843 colps_l2b0_rd_q_full_0 = colps_l2b0_rd_q_loc_0[6] && colps_l2b0_rd_q_full_0;
5844 colps_l2b0_rd_q_cnt_0 = colps_l2b0_rd_q_cnt_0 + colps_l2b0_rd_q_loc_0[6];
5845 end
5846 end else begin
5847 colps_l2b0_rd_q_full_0 = colps_l2b0_rd_q_loc_0[6] && colps_l2b0_rd_q_full_0;
5848 colps_l2b0_rd_q_cnt_0 = colps_l2b0_rd_q_cnt_0 + colps_l2b0_rd_q_loc_0[6];
5849 end
5850 end
5851 dram_Ch0_l2b0_rd_colps_q_full <= colps_l2b0_rd_q_full_0;
5852 dram_Ch0_l2b0_rd_colps_q_cnt <= colps_l2b0_rd_q_cnt_0;
5853
5854 end
5855end
5856reg dram_Ch0_l2b1_rd_colps_q_full;
5857reg colps_l2b1_rd_q_full_0;
5858reg [11:0] colps_l2b1_rd_q_loc_0;
5859reg [3:0] dram_Ch0_l2b1_rd_colps_q_cnt;
5860reg [3:0] colps_l2b1_rd_q_cnt_0;
5861reg [2:0] colps_l2b1_rd_indx_0;
5862reg colps_l2b1_rd_rst_vld_0;
5863always @(posedge (`MCU_CLK && enabled))
5864begin
5865 if (~dram_rst_l)
5866 begin
5867 dram_Ch0_l2b1_rd_colps_q_full <= 1'b0;
5868 dram_Ch0_l2b1_rd_colps_q_cnt <= 1'b0;
5869 end
5870 else
5871 begin
5872 colps_l2b1_rd_q_full_0 = 1;
5873 colps_l2b1_rd_q_cnt_0 = 0;
5874 // extract the index for which the reset occured
5875 colps_l2b1_rd_rst_vld_0 = 0;
5876 for (i=0;i<8;i=i+1) begin
5877 if (dram_Ch0_l2b1_rd_que_rd_ptr[i]) begin
5878 colps_l2b1_rd_indx_0 = i;
5879 colps_l2b1_rd_rst_vld_0 = 1;
5880 end
5881 end
5882 for (i=0;i<8;i=i+1) begin
5883 colps_l2b1_rd_q_loc_0 = dram_Ch0_l2b1_rd_colps_q[i];
5884 colps_l2b1_rd_q_loc_0[6] = dram_ch0_l2b1_drq_rd_queue_valid[i];
5885 if (colps_l2b1_rd_rst_vld_0 == 1) begin
5886 if ((colps_l2b1_rd_q_loc_0[11:9] != colps_l2b1_rd_indx_0) || ~colps_l2b1_rd_q_loc_0[6]) begin
5887 colps_l2b1_rd_q_full_0 = colps_l2b1_rd_q_loc_0[6] && colps_l2b1_rd_q_full_0;
5888 colps_l2b1_rd_q_cnt_0 = colps_l2b1_rd_q_cnt_0 + colps_l2b1_rd_q_loc_0[6];
5889 end
5890 end else begin
5891 colps_l2b1_rd_q_full_0 = colps_l2b1_rd_q_loc_0[6] && colps_l2b1_rd_q_full_0;
5892 colps_l2b1_rd_q_cnt_0 = colps_l2b1_rd_q_cnt_0 + colps_l2b1_rd_q_loc_0[6];
5893 end
5894 end
5895 dram_Ch0_l2b1_rd_colps_q_full <= colps_l2b1_rd_q_full_0;
5896 dram_Ch0_l2b1_rd_colps_q_cnt <= colps_l2b1_rd_q_cnt_0;
5897
5898 end
5899end
5900reg dram_Ch1_l2b0_rd_colps_q_full;
5901reg colps_l2b0_rd_q_full_1;
5902reg [11:0] colps_l2b0_rd_q_loc_1;
5903reg [3:0] dram_Ch1_l2b0_rd_colps_q_cnt;
5904reg [3:0] colps_l2b0_rd_q_cnt_1;
5905reg [2:0] colps_l2b0_rd_indx_1;
5906reg colps_l2b0_rd_rst_vld_1;
5907always @(posedge (`MCU_CLK && enabled))
5908begin
5909 if (~dram_rst_l)
5910 begin
5911 dram_Ch1_l2b0_rd_colps_q_full <= 1'b0;
5912 dram_Ch1_l2b0_rd_colps_q_cnt <= 1'b0;
5913 end
5914 else
5915 begin
5916 colps_l2b0_rd_q_full_1 = 1;
5917 colps_l2b0_rd_q_cnt_1 = 0;
5918 // extract the index for which the reset occured
5919 colps_l2b0_rd_rst_vld_1 = 0;
5920 for (i=0;i<8;i=i+1) begin
5921 if (dram_Ch1_l2b0_rd_que_rd_ptr[i]) begin
5922 colps_l2b0_rd_indx_1 = i;
5923 colps_l2b0_rd_rst_vld_1 = 1;
5924 end
5925 end
5926 for (i=0;i<8;i=i+1) begin
5927 colps_l2b0_rd_q_loc_1 = dram_Ch1_l2b0_rd_colps_q[i];
5928 colps_l2b0_rd_q_loc_1[6] = dram_ch1_l2b0_drq_rd_queue_valid[i];
5929 if (colps_l2b0_rd_rst_vld_1 == 1) begin
5930 if ((colps_l2b0_rd_q_loc_1[11:9] != colps_l2b0_rd_indx_1) || ~colps_l2b0_rd_q_loc_1[6]) begin
5931 colps_l2b0_rd_q_full_1 = colps_l2b0_rd_q_loc_1[6] && colps_l2b0_rd_q_full_1;
5932 colps_l2b0_rd_q_cnt_1 = colps_l2b0_rd_q_cnt_1 + colps_l2b0_rd_q_loc_1[6];
5933 end
5934 end else begin
5935 colps_l2b0_rd_q_full_1 = colps_l2b0_rd_q_loc_1[6] && colps_l2b0_rd_q_full_1;
5936 colps_l2b0_rd_q_cnt_1 = colps_l2b0_rd_q_cnt_1 + colps_l2b0_rd_q_loc_1[6];
5937 end
5938 end
5939 dram_Ch1_l2b0_rd_colps_q_full <= colps_l2b0_rd_q_full_1;
5940 dram_Ch1_l2b0_rd_colps_q_cnt <= colps_l2b0_rd_q_cnt_1;
5941
5942 end
5943end
5944reg dram_Ch1_l2b1_rd_colps_q_full;
5945reg colps_l2b1_rd_q_full_1;
5946reg [11:0] colps_l2b1_rd_q_loc_1;
5947reg [3:0] dram_Ch1_l2b1_rd_colps_q_cnt;
5948reg [3:0] colps_l2b1_rd_q_cnt_1;
5949reg [2:0] colps_l2b1_rd_indx_1;
5950reg colps_l2b1_rd_rst_vld_1;
5951always @(posedge (`MCU_CLK && enabled))
5952begin
5953 if (~dram_rst_l)
5954 begin
5955 dram_Ch1_l2b1_rd_colps_q_full <= 1'b0;
5956 dram_Ch1_l2b1_rd_colps_q_cnt <= 1'b0;
5957 end
5958 else
5959 begin
5960 colps_l2b1_rd_q_full_1 = 1;
5961 colps_l2b1_rd_q_cnt_1 = 0;
5962 // extract the index for which the reset occured
5963 colps_l2b1_rd_rst_vld_1 = 0;
5964 for (i=0;i<8;i=i+1) begin
5965 if (dram_Ch1_l2b1_rd_que_rd_ptr[i]) begin
5966 colps_l2b1_rd_indx_1 = i;
5967 colps_l2b1_rd_rst_vld_1 = 1;
5968 end
5969 end
5970 for (i=0;i<8;i=i+1) begin
5971 colps_l2b1_rd_q_loc_1 = dram_Ch1_l2b1_rd_colps_q[i];
5972 colps_l2b1_rd_q_loc_1[6] = dram_ch1_l2b1_drq_rd_queue_valid[i];
5973 if (colps_l2b1_rd_rst_vld_1 == 1) begin
5974 if ((colps_l2b1_rd_q_loc_1[11:9] != colps_l2b1_rd_indx_1) || ~colps_l2b1_rd_q_loc_1[6]) begin
5975 colps_l2b1_rd_q_full_1 = colps_l2b1_rd_q_loc_1[6] && colps_l2b1_rd_q_full_1;
5976 colps_l2b1_rd_q_cnt_1 = colps_l2b1_rd_q_cnt_1 + colps_l2b1_rd_q_loc_1[6];
5977 end
5978 end else begin
5979 colps_l2b1_rd_q_full_1 = colps_l2b1_rd_q_loc_1[6] && colps_l2b1_rd_q_full_1;
5980 colps_l2b1_rd_q_cnt_1 = colps_l2b1_rd_q_cnt_1 + colps_l2b1_rd_q_loc_1[6];
5981 end
5982 end
5983 dram_Ch1_l2b1_rd_colps_q_full <= colps_l2b1_rd_q_full_1;
5984 dram_Ch1_l2b1_rd_colps_q_cnt <= colps_l2b1_rd_q_cnt_1;
5985
5986 end
5987end
5988reg dram_Ch2_l2b0_rd_colps_q_full;
5989reg colps_l2b0_rd_q_full_2;
5990reg [11:0] colps_l2b0_rd_q_loc_2;
5991reg [3:0] dram_Ch2_l2b0_rd_colps_q_cnt;
5992reg [3:0] colps_l2b0_rd_q_cnt_2;
5993reg [2:0] colps_l2b0_rd_indx_2;
5994reg colps_l2b0_rd_rst_vld_2;
5995always @(posedge (`MCU_CLK && enabled))
5996begin
5997 if (~dram_rst_l)
5998 begin
5999 dram_Ch2_l2b0_rd_colps_q_full <= 1'b0;
6000 dram_Ch2_l2b0_rd_colps_q_cnt <= 1'b0;
6001 end
6002 else
6003 begin
6004 colps_l2b0_rd_q_full_2 = 1;
6005 colps_l2b0_rd_q_cnt_2 = 0;
6006 // extract the index for which the reset occured
6007 colps_l2b0_rd_rst_vld_2 = 0;
6008 for (i=0;i<8;i=i+1) begin
6009 if (dram_Ch2_l2b0_rd_que_rd_ptr[i]) begin
6010 colps_l2b0_rd_indx_2 = i;
6011 colps_l2b0_rd_rst_vld_2 = 1;
6012 end
6013 end
6014 for (i=0;i<8;i=i+1) begin
6015 colps_l2b0_rd_q_loc_2 = dram_Ch2_l2b0_rd_colps_q[i];
6016 colps_l2b0_rd_q_loc_2[6] = dram_ch2_l2b0_drq_rd_queue_valid[i];
6017 if (colps_l2b0_rd_rst_vld_2 == 1) begin
6018 if ((colps_l2b0_rd_q_loc_2[11:9] != colps_l2b0_rd_indx_2) || ~colps_l2b0_rd_q_loc_2[6]) begin
6019 colps_l2b0_rd_q_full_2 = colps_l2b0_rd_q_loc_2[6] && colps_l2b0_rd_q_full_2;
6020 colps_l2b0_rd_q_cnt_2 = colps_l2b0_rd_q_cnt_2 + colps_l2b0_rd_q_loc_2[6];
6021 end
6022 end else begin
6023 colps_l2b0_rd_q_full_2 = colps_l2b0_rd_q_loc_2[6] && colps_l2b0_rd_q_full_2;
6024 colps_l2b0_rd_q_cnt_2 = colps_l2b0_rd_q_cnt_2 + colps_l2b0_rd_q_loc_2[6];
6025 end
6026 end
6027 dram_Ch2_l2b0_rd_colps_q_full <= colps_l2b0_rd_q_full_2;
6028 dram_Ch2_l2b0_rd_colps_q_cnt <= colps_l2b0_rd_q_cnt_2;
6029
6030 end
6031end
6032reg dram_Ch2_l2b1_rd_colps_q_full;
6033reg colps_l2b1_rd_q_full_2;
6034reg [11:0] colps_l2b1_rd_q_loc_2;
6035reg [3:0] dram_Ch2_l2b1_rd_colps_q_cnt;
6036reg [3:0] colps_l2b1_rd_q_cnt_2;
6037reg [2:0] colps_l2b1_rd_indx_2;
6038reg colps_l2b1_rd_rst_vld_2;
6039always @(posedge (`MCU_CLK && enabled))
6040begin
6041 if (~dram_rst_l)
6042 begin
6043 dram_Ch2_l2b1_rd_colps_q_full <= 1'b0;
6044 dram_Ch2_l2b1_rd_colps_q_cnt <= 1'b0;
6045 end
6046 else
6047 begin
6048 colps_l2b1_rd_q_full_2 = 1;
6049 colps_l2b1_rd_q_cnt_2 = 0;
6050 // extract the index for which the reset occured
6051 colps_l2b1_rd_rst_vld_2 = 0;
6052 for (i=0;i<8;i=i+1) begin
6053 if (dram_Ch2_l2b1_rd_que_rd_ptr[i]) begin
6054 colps_l2b1_rd_indx_2 = i;
6055 colps_l2b1_rd_rst_vld_2 = 1;
6056 end
6057 end
6058 for (i=0;i<8;i=i+1) begin
6059 colps_l2b1_rd_q_loc_2 = dram_Ch2_l2b1_rd_colps_q[i];
6060 colps_l2b1_rd_q_loc_2[6] = dram_ch2_l2b1_drq_rd_queue_valid[i];
6061 if (colps_l2b1_rd_rst_vld_2 == 1) begin
6062 if ((colps_l2b1_rd_q_loc_2[11:9] != colps_l2b1_rd_indx_2) || ~colps_l2b1_rd_q_loc_2[6]) begin
6063 colps_l2b1_rd_q_full_2 = colps_l2b1_rd_q_loc_2[6] && colps_l2b1_rd_q_full_2;
6064 colps_l2b1_rd_q_cnt_2 = colps_l2b1_rd_q_cnt_2 + colps_l2b1_rd_q_loc_2[6];
6065 end
6066 end else begin
6067 colps_l2b1_rd_q_full_2 = colps_l2b1_rd_q_loc_2[6] && colps_l2b1_rd_q_full_2;
6068 colps_l2b1_rd_q_cnt_2 = colps_l2b1_rd_q_cnt_2 + colps_l2b1_rd_q_loc_2[6];
6069 end
6070 end
6071 dram_Ch2_l2b1_rd_colps_q_full <= colps_l2b1_rd_q_full_2;
6072 dram_Ch2_l2b1_rd_colps_q_cnt <= colps_l2b1_rd_q_cnt_2;
6073
6074 end
6075end
6076reg dram_Ch3_l2b0_rd_colps_q_full;
6077reg colps_l2b0_rd_q_full_3;
6078reg [11:0] colps_l2b0_rd_q_loc_3;
6079reg [3:0] dram_Ch3_l2b0_rd_colps_q_cnt;
6080reg [3:0] colps_l2b0_rd_q_cnt_3;
6081reg [2:0] colps_l2b0_rd_indx_3;
6082reg colps_l2b0_rd_rst_vld_3;
6083always @(posedge (`MCU_CLK && enabled))
6084begin
6085 if (~dram_rst_l)
6086 begin
6087 dram_Ch3_l2b0_rd_colps_q_full <= 1'b0;
6088 dram_Ch3_l2b0_rd_colps_q_cnt <= 1'b0;
6089 end
6090 else
6091 begin
6092 colps_l2b0_rd_q_full_3 = 1;
6093 colps_l2b0_rd_q_cnt_3 = 0;
6094 // extract the index for which the reset occured
6095 colps_l2b0_rd_rst_vld_3 = 0;
6096 for (i=0;i<8;i=i+1) begin
6097 if (dram_Ch3_l2b0_rd_que_rd_ptr[i]) begin
6098 colps_l2b0_rd_indx_3 = i;
6099 colps_l2b0_rd_rst_vld_3 = 1;
6100 end
6101 end
6102 for (i=0;i<8;i=i+1) begin
6103 colps_l2b0_rd_q_loc_3 = dram_Ch3_l2b0_rd_colps_q[i];
6104 colps_l2b0_rd_q_loc_3[6] = dram_ch3_l2b0_drq_rd_queue_valid[i];
6105 if (colps_l2b0_rd_rst_vld_3 == 1) begin
6106 if ((colps_l2b0_rd_q_loc_3[11:9] != colps_l2b0_rd_indx_3) || ~colps_l2b0_rd_q_loc_3[6]) begin
6107 colps_l2b0_rd_q_full_3 = colps_l2b0_rd_q_loc_3[6] && colps_l2b0_rd_q_full_3;
6108 colps_l2b0_rd_q_cnt_3 = colps_l2b0_rd_q_cnt_3 + colps_l2b0_rd_q_loc_3[6];
6109 end
6110 end else begin
6111 colps_l2b0_rd_q_full_3 = colps_l2b0_rd_q_loc_3[6] && colps_l2b0_rd_q_full_3;
6112 colps_l2b0_rd_q_cnt_3 = colps_l2b0_rd_q_cnt_3 + colps_l2b0_rd_q_loc_3[6];
6113 end
6114 end
6115 dram_Ch3_l2b0_rd_colps_q_full <= colps_l2b0_rd_q_full_3;
6116 dram_Ch3_l2b0_rd_colps_q_cnt <= colps_l2b0_rd_q_cnt_3;
6117
6118 end
6119end
6120reg dram_Ch3_l2b1_rd_colps_q_full;
6121reg colps_l2b1_rd_q_full_3;
6122reg [11:0] colps_l2b1_rd_q_loc_3;
6123reg [3:0] dram_Ch3_l2b1_rd_colps_q_cnt;
6124reg [3:0] colps_l2b1_rd_q_cnt_3;
6125reg [2:0] colps_l2b1_rd_indx_3;
6126reg colps_l2b1_rd_rst_vld_3;
6127always @(posedge (`MCU_CLK && enabled))
6128begin
6129 if (~dram_rst_l)
6130 begin
6131 dram_Ch3_l2b1_rd_colps_q_full <= 1'b0;
6132 dram_Ch3_l2b1_rd_colps_q_cnt <= 1'b0;
6133 end
6134 else
6135 begin
6136 colps_l2b1_rd_q_full_3 = 1;
6137 colps_l2b1_rd_q_cnt_3 = 0;
6138 // extract the index for which the reset occured
6139 colps_l2b1_rd_rst_vld_3 = 0;
6140 for (i=0;i<8;i=i+1) begin
6141 if (dram_Ch3_l2b1_rd_que_rd_ptr[i]) begin
6142 colps_l2b1_rd_indx_3 = i;
6143 colps_l2b1_rd_rst_vld_3 = 1;
6144 end
6145 end
6146 for (i=0;i<8;i=i+1) begin
6147 colps_l2b1_rd_q_loc_3 = dram_Ch3_l2b1_rd_colps_q[i];
6148 colps_l2b1_rd_q_loc_3[6] = dram_ch3_l2b1_drq_rd_queue_valid[i];
6149 if (colps_l2b1_rd_rst_vld_3 == 1) begin
6150 if ((colps_l2b1_rd_q_loc_3[11:9] != colps_l2b1_rd_indx_3) || ~colps_l2b1_rd_q_loc_3[6]) begin
6151 colps_l2b1_rd_q_full_3 = colps_l2b1_rd_q_loc_3[6] && colps_l2b1_rd_q_full_3;
6152 colps_l2b1_rd_q_cnt_3 = colps_l2b1_rd_q_cnt_3 + colps_l2b1_rd_q_loc_3[6];
6153 end
6154 end else begin
6155 colps_l2b1_rd_q_full_3 = colps_l2b1_rd_q_loc_3[6] && colps_l2b1_rd_q_full_3;
6156 colps_l2b1_rd_q_cnt_3 = colps_l2b1_rd_q_cnt_3 + colps_l2b1_rd_q_loc_3[6];
6157 end
6158 end
6159 dram_Ch3_l2b1_rd_colps_q_full <= colps_l2b1_rd_q_full_3;
6160 dram_Ch3_l2b1_rd_colps_q_cnt <= colps_l2b1_rd_q_cnt_3;
6161
6162 end
6163end
6164
6165
6166// ---- DETECTING RD Q EMPTY (MAQ : Read Address Q) ------
6167
6168reg dram_Ch0_l2b0_rd_q_empty;
6169reg l2b0_rd_q_empty_0;
6170reg [39:0] l2b0_rd_q_loc1_0;
6171always @(posedge (`MCU_CLK && enabled))
6172begin
6173 if (~dram_rst_l)
6174 begin
6175 dram_Ch0_l2b0_rd_q_empty <= 1'b0;
6176 end
6177 else
6178 begin
6179 l2b0_rd_q_empty_0 = 0;
6180 for (i=0;i<8;i=i+1) begin
6181 l2b0_rd_q_loc1_0 = dram_Ch0_l2b0_rd_q[i];
6182 l2b0_rd_q_empty_0 = l2b0_rd_q_loc1_0[39] || l2b0_rd_q_empty_0;
6183 end
6184 dram_Ch0_l2b0_rd_q_empty <= ~l2b0_rd_q_empty_0;
6185
6186 end
6187end
6188reg dram_Ch0_l2b1_rd_q_empty;
6189reg l2b1_rd_q_empty_0;
6190reg [39:0] l2b1_rd_q_loc1_0;
6191always @(posedge (`MCU_CLK && enabled))
6192begin
6193 if (~dram_rst_l)
6194 begin
6195 dram_Ch0_l2b1_rd_q_empty <= 1'b0;
6196 end
6197 else
6198 begin
6199 l2b1_rd_q_empty_0 = 0;
6200 for (i=0;i<8;i=i+1) begin
6201 l2b1_rd_q_loc1_0 = dram_Ch0_l2b1_rd_q[i];
6202 l2b1_rd_q_empty_0 = l2b1_rd_q_loc1_0[39] || l2b1_rd_q_empty_0;
6203 end
6204 dram_Ch0_l2b1_rd_q_empty <= ~l2b1_rd_q_empty_0;
6205
6206 end
6207end
6208reg dram_Ch1_l2b0_rd_q_empty;
6209reg l2b0_rd_q_empty_1;
6210reg [39:0] l2b0_rd_q_loc1_1;
6211always @(posedge (`MCU_CLK && enabled))
6212begin
6213 if (~dram_rst_l)
6214 begin
6215 dram_Ch1_l2b0_rd_q_empty <= 1'b0;
6216 end
6217 else
6218 begin
6219 l2b0_rd_q_empty_1 = 0;
6220 for (i=0;i<8;i=i+1) begin
6221 l2b0_rd_q_loc1_1 = dram_Ch1_l2b0_rd_q[i];
6222 l2b0_rd_q_empty_1 = l2b0_rd_q_loc1_1[39] || l2b0_rd_q_empty_1;
6223 end
6224 dram_Ch1_l2b0_rd_q_empty <= ~l2b0_rd_q_empty_1;
6225
6226 end
6227end
6228reg dram_Ch1_l2b1_rd_q_empty;
6229reg l2b1_rd_q_empty_1;
6230reg [39:0] l2b1_rd_q_loc1_1;
6231always @(posedge (`MCU_CLK && enabled))
6232begin
6233 if (~dram_rst_l)
6234 begin
6235 dram_Ch1_l2b1_rd_q_empty <= 1'b0;
6236 end
6237 else
6238 begin
6239 l2b1_rd_q_empty_1 = 0;
6240 for (i=0;i<8;i=i+1) begin
6241 l2b1_rd_q_loc1_1 = dram_Ch1_l2b1_rd_q[i];
6242 l2b1_rd_q_empty_1 = l2b1_rd_q_loc1_1[39] || l2b1_rd_q_empty_1;
6243 end
6244 dram_Ch1_l2b1_rd_q_empty <= ~l2b1_rd_q_empty_1;
6245
6246 end
6247end
6248reg dram_Ch2_l2b0_rd_q_empty;
6249reg l2b0_rd_q_empty_2;
6250reg [39:0] l2b0_rd_q_loc1_2;
6251always @(posedge (`MCU_CLK && enabled))
6252begin
6253 if (~dram_rst_l)
6254 begin
6255 dram_Ch2_l2b0_rd_q_empty <= 1'b0;
6256 end
6257 else
6258 begin
6259 l2b0_rd_q_empty_2 = 0;
6260 for (i=0;i<8;i=i+1) begin
6261 l2b0_rd_q_loc1_2 = dram_Ch2_l2b0_rd_q[i];
6262 l2b0_rd_q_empty_2 = l2b0_rd_q_loc1_2[39] || l2b0_rd_q_empty_2;
6263 end
6264 dram_Ch2_l2b0_rd_q_empty <= ~l2b0_rd_q_empty_2;
6265
6266 end
6267end
6268reg dram_Ch2_l2b1_rd_q_empty;
6269reg l2b1_rd_q_empty_2;
6270reg [39:0] l2b1_rd_q_loc1_2;
6271always @(posedge (`MCU_CLK && enabled))
6272begin
6273 if (~dram_rst_l)
6274 begin
6275 dram_Ch2_l2b1_rd_q_empty <= 1'b0;
6276 end
6277 else
6278 begin
6279 l2b1_rd_q_empty_2 = 0;
6280 for (i=0;i<8;i=i+1) begin
6281 l2b1_rd_q_loc1_2 = dram_Ch2_l2b1_rd_q[i];
6282 l2b1_rd_q_empty_2 = l2b1_rd_q_loc1_2[39] || l2b1_rd_q_empty_2;
6283 end
6284 dram_Ch2_l2b1_rd_q_empty <= ~l2b1_rd_q_empty_2;
6285
6286 end
6287end
6288reg dram_Ch3_l2b0_rd_q_empty;
6289reg l2b0_rd_q_empty_3;
6290reg [39:0] l2b0_rd_q_loc1_3;
6291always @(posedge (`MCU_CLK && enabled))
6292begin
6293 if (~dram_rst_l)
6294 begin
6295 dram_Ch3_l2b0_rd_q_empty <= 1'b0;
6296 end
6297 else
6298 begin
6299 l2b0_rd_q_empty_3 = 0;
6300 for (i=0;i<8;i=i+1) begin
6301 l2b0_rd_q_loc1_3 = dram_Ch3_l2b0_rd_q[i];
6302 l2b0_rd_q_empty_3 = l2b0_rd_q_loc1_3[39] || l2b0_rd_q_empty_3;
6303 end
6304 dram_Ch3_l2b0_rd_q_empty <= ~l2b0_rd_q_empty_3;
6305
6306 end
6307end
6308reg dram_Ch3_l2b1_rd_q_empty;
6309reg l2b1_rd_q_empty_3;
6310reg [39:0] l2b1_rd_q_loc1_3;
6311always @(posedge (`MCU_CLK && enabled))
6312begin
6313 if (~dram_rst_l)
6314 begin
6315 dram_Ch3_l2b1_rd_q_empty <= 1'b0;
6316 end
6317 else
6318 begin
6319 l2b1_rd_q_empty_3 = 0;
6320 for (i=0;i<8;i=i+1) begin
6321 l2b1_rd_q_loc1_3 = dram_Ch3_l2b1_rd_q[i];
6322 l2b1_rd_q_empty_3 = l2b1_rd_q_loc1_3[39] || l2b1_rd_q_empty_3;
6323 end
6324 dram_Ch3_l2b1_rd_q_empty <= ~l2b1_rd_q_empty_3;
6325
6326 end
6327end
6328
6329// ---- DETECTING RD COLLAPSING FIFO EMPTY (MAQ : Read Request Q) -----
6330reg dram_Ch0_l2b0_rd_colps_q_empty;
6331reg colps_l2b0_rd_q_empty_0;
6332reg [11:0] colps_l2b0_rd_q_loc1_0;
6333always @(posedge (`MCU_CLK && enabled))
6334begin
6335 if (~dram_rst_l)
6336 begin
6337 dram_Ch0_l2b0_rd_colps_q_empty <= 1'b0;
6338 end
6339 else
6340 begin
6341 colps_l2b0_rd_q_empty_0 = 0;
6342 for (i=0;i<8;i=i+1) begin
6343 colps_l2b0_rd_q_loc1_0 = dram_Ch0_l2b0_rd_colps_q[i];
6344 colps_l2b0_rd_q_loc1_0[6] = dram_ch0_l2b0_drq_rd_queue_valid[i];
6345 colps_l2b0_rd_q_empty_0 = colps_l2b0_rd_q_loc1_0[6] || colps_l2b0_rd_q_empty_0;
6346 end
6347 dram_Ch0_l2b0_rd_colps_q_empty <= ~colps_l2b0_rd_q_empty_0;
6348 end
6349end
6350reg dram_Ch0_l2b1_rd_colps_q_empty;
6351reg colps_l2b1_rd_q_empty_0;
6352reg [11:0] colps_l2b1_rd_q_loc1_0;
6353always @(posedge (`MCU_CLK && enabled))
6354begin
6355 if (~dram_rst_l)
6356 begin
6357 dram_Ch0_l2b1_rd_colps_q_empty <= 1'b0;
6358 end
6359 else
6360 begin
6361 colps_l2b1_rd_q_empty_0 = 0;
6362 for (i=0;i<8;i=i+1) begin
6363 colps_l2b1_rd_q_loc1_0 = dram_Ch0_l2b1_rd_colps_q[i];
6364 colps_l2b1_rd_q_loc1_0[6] = dram_ch0_l2b1_drq_rd_queue_valid[i];
6365 colps_l2b1_rd_q_empty_0 = colps_l2b1_rd_q_loc1_0[6] || colps_l2b1_rd_q_empty_0;
6366 end
6367 dram_Ch0_l2b1_rd_colps_q_empty <= ~colps_l2b1_rd_q_empty_0;
6368 end
6369end
6370reg dram_Ch1_l2b0_rd_colps_q_empty;
6371reg colps_l2b0_rd_q_empty_1;
6372reg [11:0] colps_l2b0_rd_q_loc1_1;
6373always @(posedge (`MCU_CLK && enabled))
6374begin
6375 if (~dram_rst_l)
6376 begin
6377 dram_Ch1_l2b0_rd_colps_q_empty <= 1'b0;
6378 end
6379 else
6380 begin
6381 colps_l2b0_rd_q_empty_1 = 0;
6382 for (i=0;i<8;i=i+1) begin
6383 colps_l2b0_rd_q_loc1_1 = dram_Ch1_l2b0_rd_colps_q[i];
6384 colps_l2b0_rd_q_loc1_1[6] = dram_ch1_l2b0_drq_rd_queue_valid[i];
6385 colps_l2b0_rd_q_empty_1 = colps_l2b0_rd_q_loc1_1[6] || colps_l2b0_rd_q_empty_1;
6386 end
6387 dram_Ch1_l2b0_rd_colps_q_empty <= ~colps_l2b0_rd_q_empty_1;
6388 end
6389end
6390reg dram_Ch1_l2b1_rd_colps_q_empty;
6391reg colps_l2b1_rd_q_empty_1;
6392reg [11:0] colps_l2b1_rd_q_loc1_1;
6393always @(posedge (`MCU_CLK && enabled))
6394begin
6395 if (~dram_rst_l)
6396 begin
6397 dram_Ch1_l2b1_rd_colps_q_empty <= 1'b0;
6398 end
6399 else
6400 begin
6401 colps_l2b1_rd_q_empty_1 = 0;
6402 for (i=0;i<8;i=i+1) begin
6403 colps_l2b1_rd_q_loc1_1 = dram_Ch1_l2b1_rd_colps_q[i];
6404 colps_l2b1_rd_q_loc1_1[6] = dram_ch1_l2b1_drq_rd_queue_valid[i];
6405 colps_l2b1_rd_q_empty_1 = colps_l2b1_rd_q_loc1_1[6] || colps_l2b1_rd_q_empty_1;
6406 end
6407 dram_Ch1_l2b1_rd_colps_q_empty <= ~colps_l2b1_rd_q_empty_1;
6408 end
6409end
6410reg dram_Ch2_l2b0_rd_colps_q_empty;
6411reg colps_l2b0_rd_q_empty_2;
6412reg [11:0] colps_l2b0_rd_q_loc1_2;
6413always @(posedge (`MCU_CLK && enabled))
6414begin
6415 if (~dram_rst_l)
6416 begin
6417 dram_Ch2_l2b0_rd_colps_q_empty <= 1'b0;
6418 end
6419 else
6420 begin
6421 colps_l2b0_rd_q_empty_2 = 0;
6422 for (i=0;i<8;i=i+1) begin
6423 colps_l2b0_rd_q_loc1_2 = dram_Ch2_l2b0_rd_colps_q[i];
6424 colps_l2b0_rd_q_loc1_2[6] = dram_ch2_l2b0_drq_rd_queue_valid[i];
6425 colps_l2b0_rd_q_empty_2 = colps_l2b0_rd_q_loc1_2[6] || colps_l2b0_rd_q_empty_2;
6426 end
6427 dram_Ch2_l2b0_rd_colps_q_empty <= ~colps_l2b0_rd_q_empty_2;
6428 end
6429end
6430reg dram_Ch2_l2b1_rd_colps_q_empty;
6431reg colps_l2b1_rd_q_empty_2;
6432reg [11:0] colps_l2b1_rd_q_loc1_2;
6433always @(posedge (`MCU_CLK && enabled))
6434begin
6435 if (~dram_rst_l)
6436 begin
6437 dram_Ch2_l2b1_rd_colps_q_empty <= 1'b0;
6438 end
6439 else
6440 begin
6441 colps_l2b1_rd_q_empty_2 = 0;
6442 for (i=0;i<8;i=i+1) begin
6443 colps_l2b1_rd_q_loc1_2 = dram_Ch2_l2b1_rd_colps_q[i];
6444 colps_l2b1_rd_q_loc1_2[6] = dram_ch2_l2b1_drq_rd_queue_valid[i];
6445 colps_l2b1_rd_q_empty_2 = colps_l2b1_rd_q_loc1_2[6] || colps_l2b1_rd_q_empty_2;
6446 end
6447 dram_Ch2_l2b1_rd_colps_q_empty <= ~colps_l2b1_rd_q_empty_2;
6448 end
6449end
6450reg dram_Ch3_l2b0_rd_colps_q_empty;
6451reg colps_l2b0_rd_q_empty_3;
6452reg [11:0] colps_l2b0_rd_q_loc1_3;
6453always @(posedge (`MCU_CLK && enabled))
6454begin
6455 if (~dram_rst_l)
6456 begin
6457 dram_Ch3_l2b0_rd_colps_q_empty <= 1'b0;
6458 end
6459 else
6460 begin
6461 colps_l2b0_rd_q_empty_3 = 0;
6462 for (i=0;i<8;i=i+1) begin
6463 colps_l2b0_rd_q_loc1_3 = dram_Ch3_l2b0_rd_colps_q[i];
6464 colps_l2b0_rd_q_loc1_3[6] = dram_ch3_l2b0_drq_rd_queue_valid[i];
6465 colps_l2b0_rd_q_empty_3 = colps_l2b0_rd_q_loc1_3[6] || colps_l2b0_rd_q_empty_3;
6466 end
6467 dram_Ch3_l2b0_rd_colps_q_empty <= ~colps_l2b0_rd_q_empty_3;
6468 end
6469end
6470reg dram_Ch3_l2b1_rd_colps_q_empty;
6471reg colps_l2b1_rd_q_empty_3;
6472reg [11:0] colps_l2b1_rd_q_loc1_3;
6473always @(posedge (`MCU_CLK && enabled))
6474begin
6475 if (~dram_rst_l)
6476 begin
6477 dram_Ch3_l2b1_rd_colps_q_empty <= 1'b0;
6478 end
6479 else
6480 begin
6481 colps_l2b1_rd_q_empty_3 = 0;
6482 for (i=0;i<8;i=i+1) begin
6483 colps_l2b1_rd_q_loc1_3 = dram_Ch3_l2b1_rd_colps_q[i];
6484 colps_l2b1_rd_q_loc1_3[6] = dram_ch3_l2b1_drq_rd_queue_valid[i];
6485 colps_l2b1_rd_q_empty_3 = colps_l2b1_rd_q_loc1_3[6] || colps_l2b1_rd_q_empty_3;
6486 end
6487 dram_Ch3_l2b1_rd_colps_q_empty <= ~colps_l2b1_rd_q_empty_3;
6488 end
6489end
6490
6491// ------ CROSS BETWEEN RD Q AND RD COLLAPSING FIFO ------
6492
6493reg [2:0] l2b0_rd_index_0;
6494reg [2:0] l2b0_curr_index_0;
6495reg [39:0] l2b0_rd_q_0;
6496reg [11:0] colps_l2b0_rd_q_loc2_0;
6497always @(posedge (`MCU_CLK && enabled))
6498begin
6499 if (~dram_rst_l)
6500 begin
6501 end
6502
6503 else
6504 if (dram_ch0_l2b0_drq_read_queue_cnt != 4'b0000)
6505 begin
6506
6507 // collapsing fifo indexes to the read q. If there is no
6508 // corresponding valid entry then error.
6509 for(i=0;i<8;i=i+1) begin
6510 colps_l2b0_rd_q_loc2_0 = dram_Ch0_l2b0_rd_colps_q[i];
6511 if (dram_ch0_l2b0_drq_rd_queue_valid[i]) begin
6512 l2b0_rd_index_0 = colps_l2b0_rd_q_loc2_0[11:9];
6513 l2b0_rd_q_0 = dram_Ch0_l2b0_rd_q[l2b0_rd_index_0];
6514/*mb156858*/ if (l2b0_rd_q_0[39] == 1'b0 ) begin
6515 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
6516 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 0);
6517 end
6518 end
6519 end
6520
6521 // all entries in the collapsing fifo should be unique
6522 for(i=0;i<8;i=i+1) begin
6523 colps_l2b0_rd_q_loc2_0 = dram_Ch0_l2b0_rd_colps_q[i];
6524 if (dram_ch0_l2b0_drq_rd_queue_valid[i]) begin
6525 l2b0_curr_index_0 = colps_l2b0_rd_q_loc2_0[11:9];
6526 for(j=i+1;j<8;j=j+1) begin
6527 colps_l2b0_rd_q_loc2_0 = dram_Ch0_l2b0_rd_colps_q[j];
6528
6529/*mb156858 if (dram_ch0_l2b0_drq_rd_queue_valid[j] && ( colps_l2b0_rd_q_loc2_0[11:9] == l2b0_curr_index_0)) begin
6530 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
6531 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 0);
6532 end */
6533 end
6534 end
6535 end
6536
6537 end
6538end
6539reg [2:0] l2b1_rd_index_0;
6540reg [2:0] l2b1_curr_index_0;
6541reg [39:0] l2b1_rd_q_0;
6542reg [11:0] colps_l2b1_rd_q_loc2_0;
6543always @(posedge (`MCU_CLK && enabled))
6544begin
6545 if (~dram_rst_l)
6546 begin
6547 end
6548
6549 else
6550 if (dram_ch0_l2b1_drq_read_queue_cnt != 4'b0000)
6551 begin
6552
6553 // collapsing fifo indexes to the read q. If there is no
6554 // corresponding valid entry then error.
6555 for(i=0;i<8;i=i+1) begin
6556 colps_l2b1_rd_q_loc2_0 = dram_Ch0_l2b1_rd_colps_q[i];
6557 if (dram_ch0_l2b1_drq_rd_queue_valid[i]) begin
6558 l2b1_rd_index_0 = colps_l2b1_rd_q_loc2_0[11:9];
6559 l2b1_rd_q_0 = dram_Ch0_l2b1_rd_q[l2b1_rd_index_0];
6560/*mb156858*/ if (l2b1_rd_q_0[39] == 1'b0 ) begin
6561 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
6562 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 0);
6563 end
6564 end
6565 end
6566
6567 // all entries in the collapsing fifo should be unique
6568 for(i=0;i<8;i=i+1) begin
6569 colps_l2b1_rd_q_loc2_0 = dram_Ch0_l2b1_rd_colps_q[i];
6570 if (dram_ch0_l2b1_drq_rd_queue_valid[i]) begin
6571 l2b1_curr_index_0 = colps_l2b1_rd_q_loc2_0[11:9];
6572 for(j=i+1;j<8;j=j+1) begin
6573 colps_l2b1_rd_q_loc2_0 = dram_Ch0_l2b1_rd_colps_q[j];
6574
6575/*mb156858 if (dram_ch0_l2b1_drq_rd_queue_valid[j] && ( colps_l2b1_rd_q_loc2_0[11:9] == l2b1_curr_index_0)) begin
6576 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
6577 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 0);
6578 end */
6579 end
6580 end
6581 end
6582
6583 end
6584end
6585reg [2:0] l2b0_rd_index_1;
6586reg [2:0] l2b0_curr_index_1;
6587reg [39:0] l2b0_rd_q_1;
6588reg [11:0] colps_l2b0_rd_q_loc2_1;
6589always @(posedge (`MCU_CLK && enabled))
6590begin
6591 if (~dram_rst_l)
6592 begin
6593 end
6594
6595 else
6596 if (dram_ch1_l2b0_drq_read_queue_cnt != 4'b0000)
6597 begin
6598
6599 // collapsing fifo indexes to the read q. If there is no
6600 // corresponding valid entry then error.
6601 for(i=0;i<8;i=i+1) begin
6602 colps_l2b0_rd_q_loc2_1 = dram_Ch1_l2b0_rd_colps_q[i];
6603 if (dram_ch1_l2b0_drq_rd_queue_valid[i]) begin
6604 l2b0_rd_index_1 = colps_l2b0_rd_q_loc2_1[11:9];
6605 l2b0_rd_q_1 = dram_Ch1_l2b0_rd_q[l2b0_rd_index_1];
6606/*mb156858*/ if (l2b0_rd_q_1[39] == 1'b0 ) begin
6607 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
6608 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 1);
6609 end
6610 end
6611 end
6612
6613 // all entries in the collapsing fifo should be unique
6614 for(i=0;i<8;i=i+1) begin
6615 colps_l2b0_rd_q_loc2_1 = dram_Ch1_l2b0_rd_colps_q[i];
6616 if (dram_ch1_l2b0_drq_rd_queue_valid[i]) begin
6617 l2b0_curr_index_1 = colps_l2b0_rd_q_loc2_1[11:9];
6618 for(j=i+1;j<8;j=j+1) begin
6619 colps_l2b0_rd_q_loc2_1 = dram_Ch1_l2b0_rd_colps_q[j];
6620
6621/*mb156858 if (dram_ch1_l2b0_drq_rd_queue_valid[j] && ( colps_l2b0_rd_q_loc2_1[11:9] == l2b0_curr_index_1)) begin
6622 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
6623 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 1);
6624 end */
6625 end
6626 end
6627 end
6628
6629 end
6630end
6631reg [2:0] l2b1_rd_index_1;
6632reg [2:0] l2b1_curr_index_1;
6633reg [39:0] l2b1_rd_q_1;
6634reg [11:0] colps_l2b1_rd_q_loc2_1;
6635always @(posedge (`MCU_CLK && enabled))
6636begin
6637 if (~dram_rst_l)
6638 begin
6639 end
6640
6641 else
6642 if (dram_ch1_l2b1_drq_read_queue_cnt != 4'b0000)
6643 begin
6644
6645 // collapsing fifo indexes to the read q. If there is no
6646 // corresponding valid entry then error.
6647 for(i=0;i<8;i=i+1) begin
6648 colps_l2b1_rd_q_loc2_1 = dram_Ch1_l2b1_rd_colps_q[i];
6649 if (dram_ch1_l2b1_drq_rd_queue_valid[i]) begin
6650 l2b1_rd_index_1 = colps_l2b1_rd_q_loc2_1[11:9];
6651 l2b1_rd_q_1 = dram_Ch1_l2b1_rd_q[l2b1_rd_index_1];
6652/*mb156858*/ if (l2b1_rd_q_1[39] == 1'b0 ) begin
6653 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
6654 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 1);
6655 end
6656 end
6657 end
6658
6659 // all entries in the collapsing fifo should be unique
6660 for(i=0;i<8;i=i+1) begin
6661 colps_l2b1_rd_q_loc2_1 = dram_Ch1_l2b1_rd_colps_q[i];
6662 if (dram_ch1_l2b1_drq_rd_queue_valid[i]) begin
6663 l2b1_curr_index_1 = colps_l2b1_rd_q_loc2_1[11:9];
6664 for(j=i+1;j<8;j=j+1) begin
6665 colps_l2b1_rd_q_loc2_1 = dram_Ch1_l2b1_rd_colps_q[j];
6666
6667/*mb156858 if (dram_ch1_l2b1_drq_rd_queue_valid[j] && ( colps_l2b1_rd_q_loc2_1[11:9] == l2b1_curr_index_1)) begin
6668 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
6669 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 1);
6670 end */
6671 end
6672 end
6673 end
6674
6675 end
6676end
6677reg [2:0] l2b0_rd_index_2;
6678reg [2:0] l2b0_curr_index_2;
6679reg [39:0] l2b0_rd_q_2;
6680reg [11:0] colps_l2b0_rd_q_loc2_2;
6681always @(posedge (`MCU_CLK && enabled))
6682begin
6683 if (~dram_rst_l)
6684 begin
6685 end
6686
6687 else
6688 if (dram_ch2_l2b0_drq_read_queue_cnt != 4'b0000)
6689 begin
6690
6691 // collapsing fifo indexes to the read q. If there is no
6692 // corresponding valid entry then error.
6693 for(i=0;i<8;i=i+1) begin
6694 colps_l2b0_rd_q_loc2_2 = dram_Ch2_l2b0_rd_colps_q[i];
6695 if (dram_ch2_l2b0_drq_rd_queue_valid[i]) begin
6696 l2b0_rd_index_2 = colps_l2b0_rd_q_loc2_2[11:9];
6697 l2b0_rd_q_2 = dram_Ch2_l2b0_rd_q[l2b0_rd_index_2];
6698/*mb156858*/ if (l2b0_rd_q_2[39] == 1'b0 ) begin
6699 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
6700 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 2);
6701 end
6702 end
6703 end
6704
6705 // all entries in the collapsing fifo should be unique
6706 for(i=0;i<8;i=i+1) begin
6707 colps_l2b0_rd_q_loc2_2 = dram_Ch2_l2b0_rd_colps_q[i];
6708 if (dram_ch2_l2b0_drq_rd_queue_valid[i]) begin
6709 l2b0_curr_index_2 = colps_l2b0_rd_q_loc2_2[11:9];
6710 for(j=i+1;j<8;j=j+1) begin
6711 colps_l2b0_rd_q_loc2_2 = dram_Ch2_l2b0_rd_colps_q[j];
6712
6713/*mb156858 if (dram_ch2_l2b0_drq_rd_queue_valid[j] && ( colps_l2b0_rd_q_loc2_2[11:9] == l2b0_curr_index_2)) begin
6714 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
6715 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 2);
6716 end */
6717 end
6718 end
6719 end
6720
6721 end
6722end
6723reg [2:0] l2b1_rd_index_2;
6724reg [2:0] l2b1_curr_index_2;
6725reg [39:0] l2b1_rd_q_2;
6726reg [11:0] colps_l2b1_rd_q_loc2_2;
6727always @(posedge (`MCU_CLK && enabled))
6728begin
6729 if (~dram_rst_l)
6730 begin
6731 end
6732
6733 else
6734 if (dram_ch2_l2b1_drq_read_queue_cnt != 4'b0000)
6735 begin
6736
6737 // collapsing fifo indexes to the read q. If there is no
6738 // corresponding valid entry then error.
6739 for(i=0;i<8;i=i+1) begin
6740 colps_l2b1_rd_q_loc2_2 = dram_Ch2_l2b1_rd_colps_q[i];
6741 if (dram_ch2_l2b1_drq_rd_queue_valid[i]) begin
6742 l2b1_rd_index_2 = colps_l2b1_rd_q_loc2_2[11:9];
6743 l2b1_rd_q_2 = dram_Ch2_l2b1_rd_q[l2b1_rd_index_2];
6744/*mb156858*/ if (l2b1_rd_q_2[39] == 1'b0 ) begin
6745 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
6746 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 2);
6747 end
6748 end
6749 end
6750
6751 // all entries in the collapsing fifo should be unique
6752 for(i=0;i<8;i=i+1) begin
6753 colps_l2b1_rd_q_loc2_2 = dram_Ch2_l2b1_rd_colps_q[i];
6754 if (dram_ch2_l2b1_drq_rd_queue_valid[i]) begin
6755 l2b1_curr_index_2 = colps_l2b1_rd_q_loc2_2[11:9];
6756 for(j=i+1;j<8;j=j+1) begin
6757 colps_l2b1_rd_q_loc2_2 = dram_Ch2_l2b1_rd_colps_q[j];
6758
6759/*mb156858 if (dram_ch2_l2b1_drq_rd_queue_valid[j] && ( colps_l2b1_rd_q_loc2_2[11:9] == l2b1_curr_index_2)) begin
6760 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
6761 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 2);
6762 end */
6763 end
6764 end
6765 end
6766
6767 end
6768end
6769reg [2:0] l2b0_rd_index_3;
6770reg [2:0] l2b0_curr_index_3;
6771reg [39:0] l2b0_rd_q_3;
6772reg [11:0] colps_l2b0_rd_q_loc2_3;
6773always @(posedge (`MCU_CLK && enabled))
6774begin
6775 if (~dram_rst_l)
6776 begin
6777 end
6778
6779 else
6780 if (dram_ch3_l2b0_drq_read_queue_cnt != 4'b0000)
6781 begin
6782
6783 // collapsing fifo indexes to the read q. If there is no
6784 // corresponding valid entry then error.
6785 for(i=0;i<8;i=i+1) begin
6786 colps_l2b0_rd_q_loc2_3 = dram_Ch3_l2b0_rd_colps_q[i];
6787 if (dram_ch3_l2b0_drq_rd_queue_valid[i]) begin
6788 l2b0_rd_index_3 = colps_l2b0_rd_q_loc2_3[11:9];
6789 l2b0_rd_q_3 = dram_Ch3_l2b0_rd_q[l2b0_rd_index_3];
6790/*mb156858*/ if (l2b0_rd_q_3[39] == 1'b0 ) begin
6791 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
6792 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 3);
6793 end
6794 end
6795 end
6796
6797 // all entries in the collapsing fifo should be unique
6798 for(i=0;i<8;i=i+1) begin
6799 colps_l2b0_rd_q_loc2_3 = dram_Ch3_l2b0_rd_colps_q[i];
6800 if (dram_ch3_l2b0_drq_rd_queue_valid[i]) begin
6801 l2b0_curr_index_3 = colps_l2b0_rd_q_loc2_3[11:9];
6802 for(j=i+1;j<8;j=j+1) begin
6803 colps_l2b0_rd_q_loc2_3 = dram_Ch3_l2b0_rd_colps_q[j];
6804
6805/*mb156858 if (dram_ch3_l2b0_drq_rd_queue_valid[j] && ( colps_l2b0_rd_q_loc2_3[11:9] == l2b0_curr_index_3)) begin
6806 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
6807 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 3);
6808 end */
6809 end
6810 end
6811 end
6812
6813 end
6814end
6815reg [2:0] l2b1_rd_index_3;
6816reg [2:0] l2b1_curr_index_3;
6817reg [39:0] l2b1_rd_q_3;
6818reg [11:0] colps_l2b1_rd_q_loc2_3;
6819always @(posedge (`MCU_CLK && enabled))
6820begin
6821 if (~dram_rst_l)
6822 begin
6823 end
6824
6825 else
6826 if (dram_ch3_l2b1_drq_read_queue_cnt != 4'b0000)
6827 begin
6828
6829 // collapsing fifo indexes to the read q. If there is no
6830 // corresponding valid entry then error.
6831 for(i=0;i<8;i=i+1) begin
6832 colps_l2b1_rd_q_loc2_3 = dram_Ch3_l2b1_rd_colps_q[i];
6833 if (dram_ch3_l2b1_drq_rd_queue_valid[i]) begin
6834 l2b1_rd_index_3 = colps_l2b1_rd_q_loc2_3[11:9];
6835 l2b1_rd_q_3 = dram_Ch3_l2b1_rd_q[l2b1_rd_index_3];
6836/*mb156858*/ if (l2b1_rd_q_3[39] == 1'b0 ) begin
6837 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
6838 finish_test("RD Q : No valid entry in RD Q for entry in collpsing rd fifo", 3);
6839 end
6840 end
6841 end
6842
6843 // all entries in the collapsing fifo should be unique
6844 for(i=0;i<8;i=i+1) begin
6845 colps_l2b1_rd_q_loc2_3 = dram_Ch3_l2b1_rd_colps_q[i];
6846 if (dram_ch3_l2b1_drq_rd_queue_valid[i]) begin
6847 l2b1_curr_index_3 = colps_l2b1_rd_q_loc2_3[11:9];
6848 for(j=i+1;j<8;j=j+1) begin
6849 colps_l2b1_rd_q_loc2_3 = dram_Ch3_l2b1_rd_colps_q[j];
6850
6851/*mb156858 if (dram_ch3_l2b1_drq_rd_queue_valid[j] && ( colps_l2b1_rd_q_loc2_3[11:9] == l2b1_curr_index_3)) begin
6852 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
6853 finish_test(" RD Q : The valid entries in the read collapsing fifo are not unique ", 3);
6854 end */
6855 end
6856 end
6857 end
6858
6859 end
6860end
6861
6862// This can actually happen. The ack should not be given if the fifo is full
6863// rd fifo full and write to read fifo
6864//. for ( 4 = 0; 4 < 4; 4++ ) {
6865//always @( dram_Ch4_rd_colps_q_full or dram_Ch4_rd_q_full or dram_Ch4_rd_req )
6866//begin
6867//if (dram_rst_l) begin
6868// if ((dram_Ch4_rd_colps_q_full || dram_Ch4_rd_q_full) && dram_Ch4_rd_req)
6869// begin
6870// `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 4 ");
6871// finish_test(" RD Q : Error Read Q full and writing into the Read Q ", 4);
6872// end
6873//end
6874//end
6875//.}
6876
6877// rd reqid in use and read with the same id
6878 reg [39:0] l2b0_rd_q_loc2_0;
6879always @( posedge (clk && enabled))
6880begin
6881if (~dram_rst_l)
6882 l2b0_rd_q_loc2_0 = 0;
6883else
6884begin
6885 if ( dram_Ch0_l2b0_rd_req) begin
6886 for(i=0;i<8;i=i+1) begin
6887 l2b0_rd_q_loc2_0 = dram_Ch0_l2b0_rd_q[i];
6888 // MAQ if ((l2b0_rd_q_loc2_0[38:36] == dram_Ch0_l2b0_rd_id) && l2b0_rd_q_loc2_0[39]) begin
6889 if ((l2b0_rd_q_loc2_0[38:36] == dram_Ch0_l2b0_rd_id) && dram_ch0_l2b0_rd_q_valids[i]) begin
6890 if (!(dram_Ch0_l2b0_errq_vld & (dram_Ch0_l2b0_errq_id == dram_Ch0_l2b0_rd_id))) begin
6891 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
6892 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 0);
6893 end
6894 end
6895 end
6896 end
6897end
6898end
6899 reg [39:0] l2b1_rd_q_loc2_0;
6900always @( posedge (clk && enabled))
6901begin
6902if (~dram_rst_l)
6903 l2b1_rd_q_loc2_0 = 0;
6904else
6905begin
6906 if ( dram_Ch0_l2b1_rd_req) begin
6907 for(i=0;i<8;i=i+1) begin
6908 l2b1_rd_q_loc2_0 = dram_Ch0_l2b1_rd_q[i];
6909 // MAQ if ((l2b1_rd_q_loc2_0[38:36] == dram_Ch0_l2b1_rd_id) && l2b1_rd_q_loc2_0[39]) begin
6910 if ((l2b1_rd_q_loc2_0[38:36] == dram_Ch0_l2b1_rd_id) && dram_ch0_l2b1_rd_q_valids[i]) begin
6911 if (!(dram_Ch0_l2b1_errq_vld & (dram_Ch0_l2b1_errq_id == dram_Ch0_l2b1_rd_id))) begin
6912 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
6913 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 0);
6914 end
6915 end
6916 end
6917 end
6918end
6919end
6920 reg [39:0] l2b0_rd_q_loc2_1;
6921always @( posedge (clk && enabled))
6922begin
6923if (~dram_rst_l)
6924 l2b0_rd_q_loc2_1 = 0;
6925else
6926begin
6927 if ( dram_Ch1_l2b0_rd_req) begin
6928 for(i=0;i<8;i=i+1) begin
6929 l2b0_rd_q_loc2_1 = dram_Ch1_l2b0_rd_q[i];
6930 // MAQ if ((l2b0_rd_q_loc2_1[38:36] == dram_Ch1_l2b0_rd_id) && l2b0_rd_q_loc2_1[39]) begin
6931 if ((l2b0_rd_q_loc2_1[38:36] == dram_Ch1_l2b0_rd_id) && dram_ch1_l2b0_rd_q_valids[i]) begin
6932 if (!(dram_Ch1_l2b0_errq_vld & (dram_Ch1_l2b0_errq_id == dram_Ch1_l2b0_rd_id))) begin
6933 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
6934 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 1);
6935 end
6936 end
6937 end
6938 end
6939end
6940end
6941 reg [39:0] l2b1_rd_q_loc2_1;
6942always @( posedge (clk && enabled))
6943begin
6944if (~dram_rst_l)
6945 l2b1_rd_q_loc2_1 = 0;
6946else
6947begin
6948 if ( dram_Ch1_l2b1_rd_req) begin
6949 for(i=0;i<8;i=i+1) begin
6950 l2b1_rd_q_loc2_1 = dram_Ch1_l2b1_rd_q[i];
6951 // MAQ if ((l2b1_rd_q_loc2_1[38:36] == dram_Ch1_l2b1_rd_id) && l2b1_rd_q_loc2_1[39]) begin
6952 if ((l2b1_rd_q_loc2_1[38:36] == dram_Ch1_l2b1_rd_id) && dram_ch1_l2b1_rd_q_valids[i]) begin
6953 if (!(dram_Ch1_l2b1_errq_vld & (dram_Ch1_l2b1_errq_id == dram_Ch1_l2b1_rd_id))) begin
6954 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
6955 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 1);
6956 end
6957 end
6958 end
6959 end
6960end
6961end
6962 reg [39:0] l2b0_rd_q_loc2_2;
6963always @( posedge (clk && enabled))
6964begin
6965if (~dram_rst_l)
6966 l2b0_rd_q_loc2_2 = 0;
6967else
6968begin
6969 if ( dram_Ch2_l2b0_rd_req) begin
6970 for(i=0;i<8;i=i+1) begin
6971 l2b0_rd_q_loc2_2 = dram_Ch2_l2b0_rd_q[i];
6972 // MAQ if ((l2b0_rd_q_loc2_2[38:36] == dram_Ch2_l2b0_rd_id) && l2b0_rd_q_loc2_2[39]) begin
6973 if ((l2b0_rd_q_loc2_2[38:36] == dram_Ch2_l2b0_rd_id) && dram_ch2_l2b0_rd_q_valids[i]) begin
6974 if (!(dram_Ch2_l2b0_errq_vld & (dram_Ch2_l2b0_errq_id == dram_Ch2_l2b0_rd_id))) begin
6975 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
6976 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 2);
6977 end
6978 end
6979 end
6980 end
6981end
6982end
6983 reg [39:0] l2b1_rd_q_loc2_2;
6984always @( posedge (clk && enabled))
6985begin
6986if (~dram_rst_l)
6987 l2b1_rd_q_loc2_2 = 0;
6988else
6989begin
6990 if ( dram_Ch2_l2b1_rd_req) begin
6991 for(i=0;i<8;i=i+1) begin
6992 l2b1_rd_q_loc2_2 = dram_Ch2_l2b1_rd_q[i];
6993 // MAQ if ((l2b1_rd_q_loc2_2[38:36] == dram_Ch2_l2b1_rd_id) && l2b1_rd_q_loc2_2[39]) begin
6994 if ((l2b1_rd_q_loc2_2[38:36] == dram_Ch2_l2b1_rd_id) && dram_ch2_l2b1_rd_q_valids[i]) begin
6995 if (!(dram_Ch2_l2b1_errq_vld & (dram_Ch2_l2b1_errq_id == dram_Ch2_l2b1_rd_id))) begin
6996 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
6997 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 2);
6998 end
6999 end
7000 end
7001 end
7002end
7003end
7004 reg [39:0] l2b0_rd_q_loc2_3;
7005always @( posedge (clk && enabled))
7006begin
7007if (~dram_rst_l)
7008 l2b0_rd_q_loc2_3 = 0;
7009else
7010begin
7011 if ( dram_Ch3_l2b0_rd_req) begin
7012 for(i=0;i<8;i=i+1) begin
7013 l2b0_rd_q_loc2_3 = dram_Ch3_l2b0_rd_q[i];
7014 // MAQ if ((l2b0_rd_q_loc2_3[38:36] == dram_Ch3_l2b0_rd_id) && l2b0_rd_q_loc2_3[39]) begin
7015 if ((l2b0_rd_q_loc2_3[38:36] == dram_Ch3_l2b0_rd_id) && dram_ch3_l2b0_rd_q_valids[i]) begin
7016 if (!(dram_Ch3_l2b0_errq_vld & (dram_Ch3_l2b0_errq_id == dram_Ch3_l2b0_rd_id))) begin
7017 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
7018 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 3);
7019 end
7020 end
7021 end
7022 end
7023end
7024end
7025 reg [39:0] l2b1_rd_q_loc2_3;
7026always @( posedge (clk && enabled))
7027begin
7028if (~dram_rst_l)
7029 l2b1_rd_q_loc2_3 = 0;
7030else
7031begin
7032 if ( dram_Ch3_l2b1_rd_req) begin
7033 for(i=0;i<8;i=i+1) begin
7034 l2b1_rd_q_loc2_3 = dram_Ch3_l2b1_rd_q[i];
7035 // MAQ if ((l2b1_rd_q_loc2_3[38:36] == dram_Ch3_l2b1_rd_id) && l2b1_rd_q_loc2_3[39]) begin
7036 if ((l2b1_rd_q_loc2_3[38:36] == dram_Ch3_l2b1_rd_id) && dram_ch3_l2b1_rd_q_valids[i]) begin
7037 if (!(dram_Ch3_l2b1_errq_vld & (dram_Ch3_l2b1_errq_id == dram_Ch3_l2b1_rd_id))) begin
7038 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
7039 finish_test(" RD Q : Error Read Request ID in use and Rd with same ID issued ", 3);
7040 end
7041 end
7042 end
7043 end
7044end
7045end
7046
7047
7048// rd q valid and data written ( overwritting an existing entry ) (MAQ : Read Address Q)
7049 reg [39:0] l2b0_rd_q_loc3_0;
7050always @( posedge (`MCU_CLK && enabled))
7051//always @ (dram_Ch0_l2b0_rd_que_wr_ptr)
7052begin
7053if (dram_rst_l) begin
7054 for(i=0;i<8;i=i+1) begin
7055 l2b0_rd_q_loc3_0 = dram_Ch0_l2b0_rd_q[i];
7056 if ((dram_Ch0_l2b0_rd_que_wr_ptr[i] == 1'b1) && (l2b0_rd_q_loc3_0[39] == 1'b1)) begin
7057 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
7058 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 0);
7059 end
7060 end
7061end
7062end
7063 reg [39:0] l2b1_rd_q_loc3_0;
7064always @( posedge (`MCU_CLK && enabled))
7065//always @ (dram_Ch0_l2b1_rd_que_wr_ptr)
7066begin
7067if (dram_rst_l) begin
7068 for(i=0;i<8;i=i+1) begin
7069 l2b1_rd_q_loc3_0 = dram_Ch0_l2b1_rd_q[i];
7070 if ((dram_Ch0_l2b1_rd_que_wr_ptr[i] == 1'b1) && (l2b1_rd_q_loc3_0[39] == 1'b1)) begin
7071 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
7072 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 0);
7073 end
7074 end
7075end
7076end
7077 reg [39:0] l2b0_rd_q_loc3_1;
7078always @( posedge (`MCU_CLK && enabled))
7079//always @ (dram_Ch1_l2b0_rd_que_wr_ptr)
7080begin
7081if (dram_rst_l) begin
7082 for(i=0;i<8;i=i+1) begin
7083 l2b0_rd_q_loc3_1 = dram_Ch1_l2b0_rd_q[i];
7084 if ((dram_Ch1_l2b0_rd_que_wr_ptr[i] == 1'b1) && (l2b0_rd_q_loc3_1[39] == 1'b1)) begin
7085 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
7086 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 1);
7087 end
7088 end
7089end
7090end
7091 reg [39:0] l2b1_rd_q_loc3_1;
7092always @( posedge (`MCU_CLK && enabled))
7093//always @ (dram_Ch1_l2b1_rd_que_wr_ptr)
7094begin
7095if (dram_rst_l) begin
7096 for(i=0;i<8;i=i+1) begin
7097 l2b1_rd_q_loc3_1 = dram_Ch1_l2b1_rd_q[i];
7098 if ((dram_Ch1_l2b1_rd_que_wr_ptr[i] == 1'b1) && (l2b1_rd_q_loc3_1[39] == 1'b1)) begin
7099 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
7100 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 1);
7101 end
7102 end
7103end
7104end
7105 reg [39:0] l2b0_rd_q_loc3_2;
7106always @( posedge (`MCU_CLK && enabled))
7107//always @ (dram_Ch2_l2b0_rd_que_wr_ptr)
7108begin
7109if (dram_rst_l) begin
7110 for(i=0;i<8;i=i+1) begin
7111 l2b0_rd_q_loc3_2 = dram_Ch2_l2b0_rd_q[i];
7112 if ((dram_Ch2_l2b0_rd_que_wr_ptr[i] == 1'b1) && (l2b0_rd_q_loc3_2[39] == 1'b1)) begin
7113 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
7114 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 2);
7115 end
7116 end
7117end
7118end
7119 reg [39:0] l2b1_rd_q_loc3_2;
7120always @( posedge (`MCU_CLK && enabled))
7121//always @ (dram_Ch2_l2b1_rd_que_wr_ptr)
7122begin
7123if (dram_rst_l) begin
7124 for(i=0;i<8;i=i+1) begin
7125 l2b1_rd_q_loc3_2 = dram_Ch2_l2b1_rd_q[i];
7126 if ((dram_Ch2_l2b1_rd_que_wr_ptr[i] == 1'b1) && (l2b1_rd_q_loc3_2[39] == 1'b1)) begin
7127 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
7128 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 2);
7129 end
7130 end
7131end
7132end
7133 reg [39:0] l2b0_rd_q_loc3_3;
7134always @( posedge (`MCU_CLK && enabled))
7135//always @ (dram_Ch3_l2b0_rd_que_wr_ptr)
7136begin
7137if (dram_rst_l) begin
7138 for(i=0;i<8;i=i+1) begin
7139 l2b0_rd_q_loc3_3 = dram_Ch3_l2b0_rd_q[i];
7140 if ((dram_Ch3_l2b0_rd_que_wr_ptr[i] == 1'b1) && (l2b0_rd_q_loc3_3[39] == 1'b1)) begin
7141 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
7142 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 3);
7143 end
7144 end
7145end
7146end
7147 reg [39:0] l2b1_rd_q_loc3_3;
7148always @( posedge (`MCU_CLK && enabled))
7149//always @ (dram_Ch3_l2b1_rd_que_wr_ptr)
7150begin
7151if (dram_rst_l) begin
7152 for(i=0;i<8;i=i+1) begin
7153 l2b1_rd_q_loc3_3 = dram_Ch3_l2b1_rd_q[i];
7154 if ((dram_Ch3_l2b1_rd_que_wr_ptr[i] == 1'b1) && (l2b1_rd_q_loc3_3[39] == 1'b1)) begin
7155 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
7156 finish_test(" RD Q : Read Q : OverWriting to a valid RD Q location", 3);
7157 end
7158 end
7159end
7160end
7161
7162// ---- RD Q NOT VALID AND DATA READ ( RD_PTR FOR RD QUE ASSERTED ) (MAQ : Read Address Q) -----
7163
7164 reg [39:0] l2b0_rd_q_loc4_0;
7165always @( posedge (`MCU_CLK && enabled))
7166//always @ (dram_Ch0_l2b0_rd_que_rd_ptr)
7167begin
7168if (dram_rst_l) begin
7169 for(i=0;i<8;i=i+1) begin
7170 l2b0_rd_q_loc4_0 = dram_Ch0_l2b0_rd_q[i];
7171 if ((dram_Ch0_l2b0_rd_que_rd_ptr[i] == 1'b1) && (l2b0_rd_q_loc4_0[39] == 1'b0)) begin
7172 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
7173 finish_test(" RD Q : Clearing a RD Q location which is not valid", 0);
7174 end
7175 end
7176end
7177end
7178 reg [39:0] l2b1_rd_q_loc4_0;
7179always @( posedge (`MCU_CLK && enabled))
7180//always @ (dram_Ch0_l2b1_rd_que_rd_ptr)
7181begin
7182if (dram_rst_l) begin
7183 for(i=0;i<8;i=i+1) begin
7184 l2b1_rd_q_loc4_0 = dram_Ch0_l2b1_rd_q[i];
7185 if ((dram_Ch0_l2b1_rd_que_rd_ptr[i] == 1'b1) && (l2b1_rd_q_loc4_0[39] == 1'b0)) begin
7186 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
7187 finish_test(" RD Q : Clearing a RD Q location which is not valid", 0);
7188 end
7189 end
7190end
7191end
7192 reg [39:0] l2b0_rd_q_loc4_1;
7193always @( posedge (`MCU_CLK && enabled))
7194//always @ (dram_Ch1_l2b0_rd_que_rd_ptr)
7195begin
7196if (dram_rst_l) begin
7197 for(i=0;i<8;i=i+1) begin
7198 l2b0_rd_q_loc4_1 = dram_Ch1_l2b0_rd_q[i];
7199 if ((dram_Ch1_l2b0_rd_que_rd_ptr[i] == 1'b1) && (l2b0_rd_q_loc4_1[39] == 1'b0)) begin
7200 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
7201 finish_test(" RD Q : Clearing a RD Q location which is not valid", 1);
7202 end
7203 end
7204end
7205end
7206 reg [39:0] l2b1_rd_q_loc4_1;
7207always @( posedge (`MCU_CLK && enabled))
7208//always @ (dram_Ch1_l2b1_rd_que_rd_ptr)
7209begin
7210if (dram_rst_l) begin
7211 for(i=0;i<8;i=i+1) begin
7212 l2b1_rd_q_loc4_1 = dram_Ch1_l2b1_rd_q[i];
7213 if ((dram_Ch1_l2b1_rd_que_rd_ptr[i] == 1'b1) && (l2b1_rd_q_loc4_1[39] == 1'b0)) begin
7214 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
7215 finish_test(" RD Q : Clearing a RD Q location which is not valid", 1);
7216 end
7217 end
7218end
7219end
7220 reg [39:0] l2b0_rd_q_loc4_2;
7221always @( posedge (`MCU_CLK && enabled))
7222//always @ (dram_Ch2_l2b0_rd_que_rd_ptr)
7223begin
7224if (dram_rst_l) begin
7225 for(i=0;i<8;i=i+1) begin
7226 l2b0_rd_q_loc4_2 = dram_Ch2_l2b0_rd_q[i];
7227 if ((dram_Ch2_l2b0_rd_que_rd_ptr[i] == 1'b1) && (l2b0_rd_q_loc4_2[39] == 1'b0)) begin
7228 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
7229 finish_test(" RD Q : Clearing a RD Q location which is not valid", 2);
7230 end
7231 end
7232end
7233end
7234 reg [39:0] l2b1_rd_q_loc4_2;
7235always @( posedge (`MCU_CLK && enabled))
7236//always @ (dram_Ch2_l2b1_rd_que_rd_ptr)
7237begin
7238if (dram_rst_l) begin
7239 for(i=0;i<8;i=i+1) begin
7240 l2b1_rd_q_loc4_2 = dram_Ch2_l2b1_rd_q[i];
7241 if ((dram_Ch2_l2b1_rd_que_rd_ptr[i] == 1'b1) && (l2b1_rd_q_loc4_2[39] == 1'b0)) begin
7242 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
7243 finish_test(" RD Q : Clearing a RD Q location which is not valid", 2);
7244 end
7245 end
7246end
7247end
7248 reg [39:0] l2b0_rd_q_loc4_3;
7249always @( posedge (`MCU_CLK && enabled))
7250//always @ (dram_Ch3_l2b0_rd_que_rd_ptr)
7251begin
7252if (dram_rst_l) begin
7253 for(i=0;i<8;i=i+1) begin
7254 l2b0_rd_q_loc4_3 = dram_Ch3_l2b0_rd_q[i];
7255 if ((dram_Ch3_l2b0_rd_que_rd_ptr[i] == 1'b1) && (l2b0_rd_q_loc4_3[39] == 1'b0)) begin
7256 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
7257 finish_test(" RD Q : Clearing a RD Q location which is not valid", 3);
7258 end
7259 end
7260end
7261end
7262 reg [39:0] l2b1_rd_q_loc4_3;
7263always @( posedge (`MCU_CLK && enabled))
7264//always @ (dram_Ch3_l2b1_rd_que_rd_ptr)
7265begin
7266if (dram_rst_l) begin
7267 for(i=0;i<8;i=i+1) begin
7268 l2b1_rd_q_loc4_3 = dram_Ch3_l2b1_rd_q[i];
7269 if ((dram_Ch3_l2b1_rd_que_rd_ptr[i] == 1'b1) && (l2b1_rd_q_loc4_3[39] == 1'b0)) begin
7270 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
7271 finish_test(" RD Q : Clearing a RD Q location which is not valid", 3);
7272 end
7273 end
7274end
7275end
7276
7277
7278// ----- Monitor allocation and deallocation time for each entry in the rd q (MAQ : Read Address Q) ------
7279
7280 reg [39:0] l2b0_rd_q_loc5_0;
7281reg [10:0] dram_Ch0_l2b0_rd_q_cntr [7:0];
7282wire [10:0] dram_Ch0_l2b0_rd_q_cntr_0 = dram_Ch0_l2b0_rd_q_cntr[0];
7283wire [10:0] dram_Ch0_l2b0_rd_q_cntr_1 = dram_Ch0_l2b0_rd_q_cntr[1];
7284wire [10:0] dram_Ch0_l2b0_rd_q_cntr_2 = dram_Ch0_l2b0_rd_q_cntr[2];
7285wire [10:0] dram_Ch0_l2b0_rd_q_cntr_3 = dram_Ch0_l2b0_rd_q_cntr[3];
7286wire [10:0] dram_Ch0_l2b0_rd_q_cntr_4 = dram_Ch0_l2b0_rd_q_cntr[4];
7287wire [10:0] dram_Ch0_l2b0_rd_q_cntr_5 = dram_Ch0_l2b0_rd_q_cntr[5];
7288wire [10:0] dram_Ch0_l2b0_rd_q_cntr_6 = dram_Ch0_l2b0_rd_q_cntr[6];
7289wire [10:0] dram_Ch0_l2b0_rd_q_cntr_7 = dram_Ch0_l2b0_rd_q_cntr[7];
7290
7291reg [10:0] dram_Ch0_l2b0_rd_q_cnt_max;
7292reg [2:0] dram_Ch0_l2b0_rd_q_cnt_max_entry;
7293
7294 reg [40:0] l2b0_wr_q_loc7_0;
7295always @ (posedge (`MCU_CLK && enabled))
7296begin
7297 if (~dram_rst_l)
7298 begin
7299 dram_Ch0_l2b0_rd_q_cnt_max = 0;
7300 dram_Ch0_l2b0_rd_q_cnt_max_entry = 0;
7301 for(i=0;i<8;i=i+1) begin
7302 dram_Ch0_l2b0_rd_q_cntr[i] = 0;
7303 end
7304 end
7305 else
7306 begin
7307 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
7308 for(i=0;i<8;i=i+1) begin
7309 l2b0_rd_q_loc5_0 = dram_Ch0_l2b0_rd_q[i];
7310 dram_Ch0_l2b0_rd_q_cntr[i] <= (l2b0_rd_q_loc5_0[39] == 1'b1) ? dram_Ch0_l2b0_rd_q_cntr[i] + 1 : 0;
7311 if ( dram_Ch0_l2b0_rd_q_cntr[i] > dram_Ch0_l2b0_rd_q_cnt_max ) begin
7312 dram_Ch0_l2b0_rd_q_cnt_max = dram_Ch0_l2b0_rd_q_cntr[i];
7313 dram_Ch0_l2b0_rd_q_cnt_max_entry = i;
7314 end
7315 if ( dram_Ch0_l2b0_rd_q_cntr[i] > MAX_TIME ) begin
7316 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
7317 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 0);
7318 end
7319 end
7320 end
7321 end
7322end
7323 reg [39:0] l2b1_rd_q_loc5_0;
7324reg [10:0] dram_Ch0_l2b1_rd_q_cntr [7:0];
7325wire [10:0] dram_Ch0_l2b1_rd_q_cntr_0 = dram_Ch0_l2b1_rd_q_cntr[0];
7326wire [10:0] dram_Ch0_l2b1_rd_q_cntr_1 = dram_Ch0_l2b1_rd_q_cntr[1];
7327wire [10:0] dram_Ch0_l2b1_rd_q_cntr_2 = dram_Ch0_l2b1_rd_q_cntr[2];
7328wire [10:0] dram_Ch0_l2b1_rd_q_cntr_3 = dram_Ch0_l2b1_rd_q_cntr[3];
7329wire [10:0] dram_Ch0_l2b1_rd_q_cntr_4 = dram_Ch0_l2b1_rd_q_cntr[4];
7330wire [10:0] dram_Ch0_l2b1_rd_q_cntr_5 = dram_Ch0_l2b1_rd_q_cntr[5];
7331wire [10:0] dram_Ch0_l2b1_rd_q_cntr_6 = dram_Ch0_l2b1_rd_q_cntr[6];
7332wire [10:0] dram_Ch0_l2b1_rd_q_cntr_7 = dram_Ch0_l2b1_rd_q_cntr[7];
7333
7334reg [10:0] dram_Ch0_l2b1_rd_q_cnt_max;
7335reg [2:0] dram_Ch0_l2b1_rd_q_cnt_max_entry;
7336
7337 reg [40:0] l2b1_wr_q_loc7_0;
7338always @ (posedge (`MCU_CLK && enabled))
7339begin
7340 if (~dram_rst_l)
7341 begin
7342 dram_Ch0_l2b1_rd_q_cnt_max = 0;
7343 dram_Ch0_l2b1_rd_q_cnt_max_entry = 0;
7344 for(i=0;i<8;i=i+1) begin
7345 dram_Ch0_l2b1_rd_q_cntr[i] = 0;
7346 end
7347 end
7348 else
7349 begin
7350 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
7351 for(i=0;i<8;i=i+1) begin
7352 l2b1_rd_q_loc5_0 = dram_Ch0_l2b1_rd_q[i];
7353 dram_Ch0_l2b1_rd_q_cntr[i] <= (l2b1_rd_q_loc5_0[39] == 1'b1) ? dram_Ch0_l2b1_rd_q_cntr[i] + 1 : 0;
7354 if ( dram_Ch0_l2b1_rd_q_cntr[i] > dram_Ch0_l2b1_rd_q_cnt_max ) begin
7355 dram_Ch0_l2b1_rd_q_cnt_max = dram_Ch0_l2b1_rd_q_cntr[i];
7356 dram_Ch0_l2b1_rd_q_cnt_max_entry = i;
7357 end
7358 if ( dram_Ch0_l2b1_rd_q_cntr[i] > MAX_TIME ) begin
7359 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
7360 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 0);
7361 end
7362 end
7363 end
7364 end
7365end
7366 reg [39:0] l2b0_rd_q_loc5_1;
7367reg [10:0] dram_Ch1_l2b0_rd_q_cntr [7:0];
7368wire [10:0] dram_Ch1_l2b0_rd_q_cntr_0 = dram_Ch1_l2b0_rd_q_cntr[0];
7369wire [10:0] dram_Ch1_l2b0_rd_q_cntr_1 = dram_Ch1_l2b0_rd_q_cntr[1];
7370wire [10:0] dram_Ch1_l2b0_rd_q_cntr_2 = dram_Ch1_l2b0_rd_q_cntr[2];
7371wire [10:0] dram_Ch1_l2b0_rd_q_cntr_3 = dram_Ch1_l2b0_rd_q_cntr[3];
7372wire [10:0] dram_Ch1_l2b0_rd_q_cntr_4 = dram_Ch1_l2b0_rd_q_cntr[4];
7373wire [10:0] dram_Ch1_l2b0_rd_q_cntr_5 = dram_Ch1_l2b0_rd_q_cntr[5];
7374wire [10:0] dram_Ch1_l2b0_rd_q_cntr_6 = dram_Ch1_l2b0_rd_q_cntr[6];
7375wire [10:0] dram_Ch1_l2b0_rd_q_cntr_7 = dram_Ch1_l2b0_rd_q_cntr[7];
7376
7377reg [10:0] dram_Ch1_l2b0_rd_q_cnt_max;
7378reg [2:0] dram_Ch1_l2b0_rd_q_cnt_max_entry;
7379
7380 reg [40:0] l2b0_wr_q_loc7_1;
7381always @ (posedge (`MCU_CLK && enabled))
7382begin
7383 if (~dram_rst_l)
7384 begin
7385 dram_Ch1_l2b0_rd_q_cnt_max = 0;
7386 dram_Ch1_l2b0_rd_q_cnt_max_entry = 0;
7387 for(i=0;i<8;i=i+1) begin
7388 dram_Ch1_l2b0_rd_q_cntr[i] = 0;
7389 end
7390 end
7391 else
7392 begin
7393 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
7394 for(i=0;i<8;i=i+1) begin
7395 l2b0_rd_q_loc5_1 = dram_Ch1_l2b0_rd_q[i];
7396 dram_Ch1_l2b0_rd_q_cntr[i] <= (l2b0_rd_q_loc5_1[39] == 1'b1) ? dram_Ch1_l2b0_rd_q_cntr[i] + 1 : 0;
7397 if ( dram_Ch1_l2b0_rd_q_cntr[i] > dram_Ch1_l2b0_rd_q_cnt_max ) begin
7398 dram_Ch1_l2b0_rd_q_cnt_max = dram_Ch1_l2b0_rd_q_cntr[i];
7399 dram_Ch1_l2b0_rd_q_cnt_max_entry = i;
7400 end
7401 if ( dram_Ch1_l2b0_rd_q_cntr[i] > MAX_TIME ) begin
7402 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
7403 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 1);
7404 end
7405 end
7406 end
7407 end
7408end
7409 reg [39:0] l2b1_rd_q_loc5_1;
7410reg [10:0] dram_Ch1_l2b1_rd_q_cntr [7:0];
7411wire [10:0] dram_Ch1_l2b1_rd_q_cntr_0 = dram_Ch1_l2b1_rd_q_cntr[0];
7412wire [10:0] dram_Ch1_l2b1_rd_q_cntr_1 = dram_Ch1_l2b1_rd_q_cntr[1];
7413wire [10:0] dram_Ch1_l2b1_rd_q_cntr_2 = dram_Ch1_l2b1_rd_q_cntr[2];
7414wire [10:0] dram_Ch1_l2b1_rd_q_cntr_3 = dram_Ch1_l2b1_rd_q_cntr[3];
7415wire [10:0] dram_Ch1_l2b1_rd_q_cntr_4 = dram_Ch1_l2b1_rd_q_cntr[4];
7416wire [10:0] dram_Ch1_l2b1_rd_q_cntr_5 = dram_Ch1_l2b1_rd_q_cntr[5];
7417wire [10:0] dram_Ch1_l2b1_rd_q_cntr_6 = dram_Ch1_l2b1_rd_q_cntr[6];
7418wire [10:0] dram_Ch1_l2b1_rd_q_cntr_7 = dram_Ch1_l2b1_rd_q_cntr[7];
7419
7420reg [10:0] dram_Ch1_l2b1_rd_q_cnt_max;
7421reg [2:0] dram_Ch1_l2b1_rd_q_cnt_max_entry;
7422
7423 reg [40:0] l2b1_wr_q_loc7_1;
7424always @ (posedge (`MCU_CLK && enabled))
7425begin
7426 if (~dram_rst_l)
7427 begin
7428 dram_Ch1_l2b1_rd_q_cnt_max = 0;
7429 dram_Ch1_l2b1_rd_q_cnt_max_entry = 0;
7430 for(i=0;i<8;i=i+1) begin
7431 dram_Ch1_l2b1_rd_q_cntr[i] = 0;
7432 end
7433 end
7434 else
7435 begin
7436 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
7437 for(i=0;i<8;i=i+1) begin
7438 l2b1_rd_q_loc5_1 = dram_Ch1_l2b1_rd_q[i];
7439 dram_Ch1_l2b1_rd_q_cntr[i] <= (l2b1_rd_q_loc5_1[39] == 1'b1) ? dram_Ch1_l2b1_rd_q_cntr[i] + 1 : 0;
7440 if ( dram_Ch1_l2b1_rd_q_cntr[i] > dram_Ch1_l2b1_rd_q_cnt_max ) begin
7441 dram_Ch1_l2b1_rd_q_cnt_max = dram_Ch1_l2b1_rd_q_cntr[i];
7442 dram_Ch1_l2b1_rd_q_cnt_max_entry = i;
7443 end
7444 if ( dram_Ch1_l2b1_rd_q_cntr[i] > MAX_TIME ) begin
7445 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
7446 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 1);
7447 end
7448 end
7449 end
7450 end
7451end
7452 reg [39:0] l2b0_rd_q_loc5_2;
7453reg [10:0] dram_Ch2_l2b0_rd_q_cntr [7:0];
7454wire [10:0] dram_Ch2_l2b0_rd_q_cntr_0 = dram_Ch2_l2b0_rd_q_cntr[0];
7455wire [10:0] dram_Ch2_l2b0_rd_q_cntr_1 = dram_Ch2_l2b0_rd_q_cntr[1];
7456wire [10:0] dram_Ch2_l2b0_rd_q_cntr_2 = dram_Ch2_l2b0_rd_q_cntr[2];
7457wire [10:0] dram_Ch2_l2b0_rd_q_cntr_3 = dram_Ch2_l2b0_rd_q_cntr[3];
7458wire [10:0] dram_Ch2_l2b0_rd_q_cntr_4 = dram_Ch2_l2b0_rd_q_cntr[4];
7459wire [10:0] dram_Ch2_l2b0_rd_q_cntr_5 = dram_Ch2_l2b0_rd_q_cntr[5];
7460wire [10:0] dram_Ch2_l2b0_rd_q_cntr_6 = dram_Ch2_l2b0_rd_q_cntr[6];
7461wire [10:0] dram_Ch2_l2b0_rd_q_cntr_7 = dram_Ch2_l2b0_rd_q_cntr[7];
7462
7463reg [10:0] dram_Ch2_l2b0_rd_q_cnt_max;
7464reg [2:0] dram_Ch2_l2b0_rd_q_cnt_max_entry;
7465
7466 reg [40:0] l2b0_wr_q_loc7_2;
7467always @ (posedge (`MCU_CLK && enabled))
7468begin
7469 if (~dram_rst_l)
7470 begin
7471 dram_Ch2_l2b0_rd_q_cnt_max = 0;
7472 dram_Ch2_l2b0_rd_q_cnt_max_entry = 0;
7473 for(i=0;i<8;i=i+1) begin
7474 dram_Ch2_l2b0_rd_q_cntr[i] = 0;
7475 end
7476 end
7477 else
7478 begin
7479 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
7480 for(i=0;i<8;i=i+1) begin
7481 l2b0_rd_q_loc5_2 = dram_Ch2_l2b0_rd_q[i];
7482 dram_Ch2_l2b0_rd_q_cntr[i] <= (l2b0_rd_q_loc5_2[39] == 1'b1) ? dram_Ch2_l2b0_rd_q_cntr[i] + 1 : 0;
7483 if ( dram_Ch2_l2b0_rd_q_cntr[i] > dram_Ch2_l2b0_rd_q_cnt_max ) begin
7484 dram_Ch2_l2b0_rd_q_cnt_max = dram_Ch2_l2b0_rd_q_cntr[i];
7485 dram_Ch2_l2b0_rd_q_cnt_max_entry = i;
7486 end
7487 if ( dram_Ch2_l2b0_rd_q_cntr[i] > MAX_TIME ) begin
7488 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
7489 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 2);
7490 end
7491 end
7492 end
7493 end
7494end
7495 reg [39:0] l2b1_rd_q_loc5_2;
7496reg [10:0] dram_Ch2_l2b1_rd_q_cntr [7:0];
7497wire [10:0] dram_Ch2_l2b1_rd_q_cntr_0 = dram_Ch2_l2b1_rd_q_cntr[0];
7498wire [10:0] dram_Ch2_l2b1_rd_q_cntr_1 = dram_Ch2_l2b1_rd_q_cntr[1];
7499wire [10:0] dram_Ch2_l2b1_rd_q_cntr_2 = dram_Ch2_l2b1_rd_q_cntr[2];
7500wire [10:0] dram_Ch2_l2b1_rd_q_cntr_3 = dram_Ch2_l2b1_rd_q_cntr[3];
7501wire [10:0] dram_Ch2_l2b1_rd_q_cntr_4 = dram_Ch2_l2b1_rd_q_cntr[4];
7502wire [10:0] dram_Ch2_l2b1_rd_q_cntr_5 = dram_Ch2_l2b1_rd_q_cntr[5];
7503wire [10:0] dram_Ch2_l2b1_rd_q_cntr_6 = dram_Ch2_l2b1_rd_q_cntr[6];
7504wire [10:0] dram_Ch2_l2b1_rd_q_cntr_7 = dram_Ch2_l2b1_rd_q_cntr[7];
7505
7506reg [10:0] dram_Ch2_l2b1_rd_q_cnt_max;
7507reg [2:0] dram_Ch2_l2b1_rd_q_cnt_max_entry;
7508
7509 reg [40:0] l2b1_wr_q_loc7_2;
7510always @ (posedge (`MCU_CLK && enabled))
7511begin
7512 if (~dram_rst_l)
7513 begin
7514 dram_Ch2_l2b1_rd_q_cnt_max = 0;
7515 dram_Ch2_l2b1_rd_q_cnt_max_entry = 0;
7516 for(i=0;i<8;i=i+1) begin
7517 dram_Ch2_l2b1_rd_q_cntr[i] = 0;
7518 end
7519 end
7520 else
7521 begin
7522 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
7523 for(i=0;i<8;i=i+1) begin
7524 l2b1_rd_q_loc5_2 = dram_Ch2_l2b1_rd_q[i];
7525 dram_Ch2_l2b1_rd_q_cntr[i] <= (l2b1_rd_q_loc5_2[39] == 1'b1) ? dram_Ch2_l2b1_rd_q_cntr[i] + 1 : 0;
7526 if ( dram_Ch2_l2b1_rd_q_cntr[i] > dram_Ch2_l2b1_rd_q_cnt_max ) begin
7527 dram_Ch2_l2b1_rd_q_cnt_max = dram_Ch2_l2b1_rd_q_cntr[i];
7528 dram_Ch2_l2b1_rd_q_cnt_max_entry = i;
7529 end
7530 if ( dram_Ch2_l2b1_rd_q_cntr[i] > MAX_TIME ) begin
7531 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
7532 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 2);
7533 end
7534 end
7535 end
7536 end
7537end
7538 reg [39:0] l2b0_rd_q_loc5_3;
7539reg [10:0] dram_Ch3_l2b0_rd_q_cntr [7:0];
7540wire [10:0] dram_Ch3_l2b0_rd_q_cntr_0 = dram_Ch3_l2b0_rd_q_cntr[0];
7541wire [10:0] dram_Ch3_l2b0_rd_q_cntr_1 = dram_Ch3_l2b0_rd_q_cntr[1];
7542wire [10:0] dram_Ch3_l2b0_rd_q_cntr_2 = dram_Ch3_l2b0_rd_q_cntr[2];
7543wire [10:0] dram_Ch3_l2b0_rd_q_cntr_3 = dram_Ch3_l2b0_rd_q_cntr[3];
7544wire [10:0] dram_Ch3_l2b0_rd_q_cntr_4 = dram_Ch3_l2b0_rd_q_cntr[4];
7545wire [10:0] dram_Ch3_l2b0_rd_q_cntr_5 = dram_Ch3_l2b0_rd_q_cntr[5];
7546wire [10:0] dram_Ch3_l2b0_rd_q_cntr_6 = dram_Ch3_l2b0_rd_q_cntr[6];
7547wire [10:0] dram_Ch3_l2b0_rd_q_cntr_7 = dram_Ch3_l2b0_rd_q_cntr[7];
7548
7549reg [10:0] dram_Ch3_l2b0_rd_q_cnt_max;
7550reg [2:0] dram_Ch3_l2b0_rd_q_cnt_max_entry;
7551
7552 reg [40:0] l2b0_wr_q_loc7_3;
7553always @ (posedge (`MCU_CLK && enabled))
7554begin
7555 if (~dram_rst_l)
7556 begin
7557 dram_Ch3_l2b0_rd_q_cnt_max = 0;
7558 dram_Ch3_l2b0_rd_q_cnt_max_entry = 0;
7559 for(i=0;i<8;i=i+1) begin
7560 dram_Ch3_l2b0_rd_q_cntr[i] = 0;
7561 end
7562 end
7563 else
7564 begin
7565 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
7566 for(i=0;i<8;i=i+1) begin
7567 l2b0_rd_q_loc5_3 = dram_Ch3_l2b0_rd_q[i];
7568 dram_Ch3_l2b0_rd_q_cntr[i] <= (l2b0_rd_q_loc5_3[39] == 1'b1) ? dram_Ch3_l2b0_rd_q_cntr[i] + 1 : 0;
7569 if ( dram_Ch3_l2b0_rd_q_cntr[i] > dram_Ch3_l2b0_rd_q_cnt_max ) begin
7570 dram_Ch3_l2b0_rd_q_cnt_max = dram_Ch3_l2b0_rd_q_cntr[i];
7571 dram_Ch3_l2b0_rd_q_cnt_max_entry = i;
7572 end
7573 if ( dram_Ch3_l2b0_rd_q_cntr[i] > MAX_TIME ) begin
7574 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
7575 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 3);
7576 end
7577 end
7578 end
7579 end
7580end
7581 reg [39:0] l2b1_rd_q_loc5_3;
7582reg [10:0] dram_Ch3_l2b1_rd_q_cntr [7:0];
7583wire [10:0] dram_Ch3_l2b1_rd_q_cntr_0 = dram_Ch3_l2b1_rd_q_cntr[0];
7584wire [10:0] dram_Ch3_l2b1_rd_q_cntr_1 = dram_Ch3_l2b1_rd_q_cntr[1];
7585wire [10:0] dram_Ch3_l2b1_rd_q_cntr_2 = dram_Ch3_l2b1_rd_q_cntr[2];
7586wire [10:0] dram_Ch3_l2b1_rd_q_cntr_3 = dram_Ch3_l2b1_rd_q_cntr[3];
7587wire [10:0] dram_Ch3_l2b1_rd_q_cntr_4 = dram_Ch3_l2b1_rd_q_cntr[4];
7588wire [10:0] dram_Ch3_l2b1_rd_q_cntr_5 = dram_Ch3_l2b1_rd_q_cntr[5];
7589wire [10:0] dram_Ch3_l2b1_rd_q_cntr_6 = dram_Ch3_l2b1_rd_q_cntr[6];
7590wire [10:0] dram_Ch3_l2b1_rd_q_cntr_7 = dram_Ch3_l2b1_rd_q_cntr[7];
7591
7592reg [10:0] dram_Ch3_l2b1_rd_q_cnt_max;
7593reg [2:0] dram_Ch3_l2b1_rd_q_cnt_max_entry;
7594
7595 reg [40:0] l2b1_wr_q_loc7_3;
7596always @ (posedge (`MCU_CLK && enabled))
7597begin
7598 if (~dram_rst_l)
7599 begin
7600 dram_Ch3_l2b1_rd_q_cnt_max = 0;
7601 dram_Ch3_l2b1_rd_q_cnt_max_entry = 0;
7602 for(i=0;i<8;i=i+1) begin
7603 dram_Ch3_l2b1_rd_q_cntr[i] = 0;
7604 end
7605 end
7606 else
7607 begin
7608 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
7609 for(i=0;i<8;i=i+1) begin
7610 l2b1_rd_q_loc5_3 = dram_Ch3_l2b1_rd_q[i];
7611 dram_Ch3_l2b1_rd_q_cntr[i] <= (l2b1_rd_q_loc5_3[39] == 1'b1) ? dram_Ch3_l2b1_rd_q_cntr[i] + 1 : 0;
7612 if ( dram_Ch3_l2b1_rd_q_cntr[i] > dram_Ch3_l2b1_rd_q_cnt_max ) begin
7613 dram_Ch3_l2b1_rd_q_cnt_max = dram_Ch3_l2b1_rd_q_cntr[i];
7614 dram_Ch3_l2b1_rd_q_cnt_max_entry = i;
7615 end
7616 if ( dram_Ch3_l2b1_rd_q_cntr[i] > MAX_TIME ) begin
7617 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
7618 finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 3);
7619 end
7620 end
7621 end
7622 end
7623end
7624
7625// -------------- WRITE Q ---------------
7626
7627// detecting wr q full
7628reg dram_Ch0_l2b0_wr_q_full;
7629reg dram_Ch0_l2b0_wr_q_full_arb;
7630reg [3:0] dram_Ch0_l2b0_wr_q_cnt;
7631// MAQ N2 doesn't support reg [3:0] dram_Ch0_l2b0_wr_q_cnt_arb;
7632reg l2b0_wr_q_full_0;
7633reg l2b0_wr_q_full_0_arb;
7634reg [40:0] l2b0_wr_q_loc_0;
7635reg [3:0] l2b0_wr_q_cnt_0;
7636reg [3:0] l2b0_wr_q_cnt_0_arb;
7637
7638always @(posedge (`MCU_CLK && enabled))
7639begin
7640 if (~dram_rst_l)
7641 begin
7642 dram_Ch0_l2b0_wr_q_full <= 1'b0;
7643 dram_Ch0_l2b0_wr_q_full_arb <= 1'b0;
7644 dram_Ch0_l2b0_wr_q_cnt <= 4'b0;
7645// MAQ N2 doesn't support dram_Ch0_l2b0_wr_q_cnt_arb <= 4'b0;
7646 end
7647 else
7648 begin
7649 l2b0_wr_q_full_0 = 1;
7650 l2b0_wr_q_full_0_arb = 1;
7651 l2b0_wr_q_cnt_0 = 0;
7652 l2b0_wr_q_cnt_0_arb = 0;
7653 for (i=0;i<8;i=i+1) begin
7654 l2b0_wr_q_loc_0 = dram_Ch0_l2b0_wr_q[i];
7655 l2b0_wr_q_full_0 = l2b0_wr_q_loc_0[40] && l2b0_wr_q_full_0;
7656 //l2b0_wr_q_full_0_arb = (l2b0_wr_q_loc_0[39] && !dram_Ch0_l2b0_wr_que_rd_ptr_arb[i]) && l2b0_wr_q_full_0_arb;
7657 l2b0_wr_q_full_0_arb = (l2b0_wr_q_loc_0[39] && l2b0_wr_q_full_0_arb);
7658 l2b0_wr_q_cnt_0 = l2b0_wr_q_cnt_0 + l2b0_wr_q_loc_0[40];
7659
7660// MAQ N2 doesn't support l2b0_wr_q_cnt_0_arb = l2b0_wr_q_cnt_0_arb + (l2b0_wr_q_loc_0[39] && !dram_Ch0_l2b0_wr_que_rd_ptr_arb[i]);
7661
7662 end
7663 dram_Ch0_l2b0_wr_q_full <= l2b0_wr_q_full_0;
7664 dram_Ch0_l2b0_wr_q_full_arb <= l2b0_wr_q_full_0_arb;
7665 dram_Ch0_l2b0_wr_q_cnt <= l2b0_wr_q_cnt_0;
7666// MAQ N2 doesn't support dram_Ch0_l2b0_wr_q_cnt_arb <= l2b0_wr_q_cnt_0_arb;
7667 end
7668end
7669reg dram_Ch0_l2b1_wr_q_full;
7670reg dram_Ch0_l2b1_wr_q_full_arb;
7671reg [3:0] dram_Ch0_l2b1_wr_q_cnt;
7672// MAQ N2 doesn't support reg [3:0] dram_Ch0_l2b1_wr_q_cnt_arb;
7673reg l2b1_wr_q_full_0;
7674reg l2b1_wr_q_full_0_arb;
7675reg [40:0] l2b1_wr_q_loc_0;
7676reg [3:0] l2b1_wr_q_cnt_0;
7677reg [3:0] l2b1_wr_q_cnt_0_arb;
7678
7679always @(posedge (`MCU_CLK && enabled))
7680begin
7681 if (~dram_rst_l)
7682 begin
7683 dram_Ch0_l2b1_wr_q_full <= 1'b0;
7684 dram_Ch0_l2b1_wr_q_full_arb <= 1'b0;
7685 dram_Ch0_l2b1_wr_q_cnt <= 4'b0;
7686// MAQ N2 doesn't support dram_Ch0_l2b1_wr_q_cnt_arb <= 4'b0;
7687 end
7688 else
7689 begin
7690 l2b1_wr_q_full_0 = 1;
7691 l2b1_wr_q_full_0_arb = 1;
7692 l2b1_wr_q_cnt_0 = 0;
7693 l2b1_wr_q_cnt_0_arb = 0;
7694 for (i=0;i<8;i=i+1) begin
7695 l2b1_wr_q_loc_0 = dram_Ch0_l2b1_wr_q[i];
7696 l2b1_wr_q_full_0 = l2b1_wr_q_loc_0[40] && l2b1_wr_q_full_0;
7697 //l2b1_wr_q_full_0_arb = (l2b1_wr_q_loc_0[39] && !dram_Ch0_l2b1_wr_que_rd_ptr_arb[i]) && l2b1_wr_q_full_0_arb;
7698 l2b1_wr_q_full_0_arb = (l2b1_wr_q_loc_0[39] && l2b1_wr_q_full_0_arb);
7699 l2b1_wr_q_cnt_0 = l2b1_wr_q_cnt_0 + l2b1_wr_q_loc_0[40];
7700
7701// MAQ N2 doesn't support l2b1_wr_q_cnt_0_arb = l2b1_wr_q_cnt_0_arb + (l2b1_wr_q_loc_0[39] && !dram_Ch0_l2b1_wr_que_rd_ptr_arb[i]);
7702
7703 end
7704 dram_Ch0_l2b1_wr_q_full <= l2b1_wr_q_full_0;
7705 dram_Ch0_l2b1_wr_q_full_arb <= l2b1_wr_q_full_0_arb;
7706 dram_Ch0_l2b1_wr_q_cnt <= l2b1_wr_q_cnt_0;
7707// MAQ N2 doesn't support dram_Ch0_l2b1_wr_q_cnt_arb <= l2b1_wr_q_cnt_0_arb;
7708 end
7709end
7710reg dram_Ch1_l2b0_wr_q_full;
7711reg dram_Ch1_l2b0_wr_q_full_arb;
7712reg [3:0] dram_Ch1_l2b0_wr_q_cnt;
7713// MAQ N2 doesn't support reg [3:0] dram_Ch1_l2b0_wr_q_cnt_arb;
7714reg l2b0_wr_q_full_1;
7715reg l2b0_wr_q_full_1_arb;
7716reg [40:0] l2b0_wr_q_loc_1;
7717reg [3:0] l2b0_wr_q_cnt_1;
7718reg [3:0] l2b0_wr_q_cnt_1_arb;
7719
7720always @(posedge (`MCU_CLK && enabled))
7721begin
7722 if (~dram_rst_l)
7723 begin
7724 dram_Ch1_l2b0_wr_q_full <= 1'b0;
7725 dram_Ch1_l2b0_wr_q_full_arb <= 1'b0;
7726 dram_Ch1_l2b0_wr_q_cnt <= 4'b0;
7727// MAQ N2 doesn't support dram_Ch1_l2b0_wr_q_cnt_arb <= 4'b0;
7728 end
7729 else
7730 begin
7731 l2b0_wr_q_full_1 = 1;
7732 l2b0_wr_q_full_1_arb = 1;
7733 l2b0_wr_q_cnt_1 = 0;
7734 l2b0_wr_q_cnt_1_arb = 0;
7735 for (i=0;i<8;i=i+1) begin
7736 l2b0_wr_q_loc_1 = dram_Ch1_l2b0_wr_q[i];
7737 l2b0_wr_q_full_1 = l2b0_wr_q_loc_1[40] && l2b0_wr_q_full_1;
7738 //l2b0_wr_q_full_1_arb = (l2b0_wr_q_loc_1[39] && !dram_Ch1_l2b0_wr_que_rd_ptr_arb[i]) && l2b0_wr_q_full_1_arb;
7739 l2b0_wr_q_full_1_arb = (l2b0_wr_q_loc_1[39] && l2b0_wr_q_full_1_arb);
7740 l2b0_wr_q_cnt_1 = l2b0_wr_q_cnt_1 + l2b0_wr_q_loc_1[40];
7741
7742// MAQ N2 doesn't support l2b0_wr_q_cnt_1_arb = l2b0_wr_q_cnt_1_arb + (l2b0_wr_q_loc_1[39] && !dram_Ch1_l2b0_wr_que_rd_ptr_arb[i]);
7743
7744 end
7745 dram_Ch1_l2b0_wr_q_full <= l2b0_wr_q_full_1;
7746 dram_Ch1_l2b0_wr_q_full_arb <= l2b0_wr_q_full_1_arb;
7747 dram_Ch1_l2b0_wr_q_cnt <= l2b0_wr_q_cnt_1;
7748// MAQ N2 doesn't support dram_Ch1_l2b0_wr_q_cnt_arb <= l2b0_wr_q_cnt_1_arb;
7749 end
7750end
7751reg dram_Ch1_l2b1_wr_q_full;
7752reg dram_Ch1_l2b1_wr_q_full_arb;
7753reg [3:0] dram_Ch1_l2b1_wr_q_cnt;
7754// MAQ N2 doesn't support reg [3:0] dram_Ch1_l2b1_wr_q_cnt_arb;
7755reg l2b1_wr_q_full_1;
7756reg l2b1_wr_q_full_1_arb;
7757reg [40:0] l2b1_wr_q_loc_1;
7758reg [3:0] l2b1_wr_q_cnt_1;
7759reg [3:0] l2b1_wr_q_cnt_1_arb;
7760
7761always @(posedge (`MCU_CLK && enabled))
7762begin
7763 if (~dram_rst_l)
7764 begin
7765 dram_Ch1_l2b1_wr_q_full <= 1'b0;
7766 dram_Ch1_l2b1_wr_q_full_arb <= 1'b0;
7767 dram_Ch1_l2b1_wr_q_cnt <= 4'b0;
7768// MAQ N2 doesn't support dram_Ch1_l2b1_wr_q_cnt_arb <= 4'b0;
7769 end
7770 else
7771 begin
7772 l2b1_wr_q_full_1 = 1;
7773 l2b1_wr_q_full_1_arb = 1;
7774 l2b1_wr_q_cnt_1 = 0;
7775 l2b1_wr_q_cnt_1_arb = 0;
7776 for (i=0;i<8;i=i+1) begin
7777 l2b1_wr_q_loc_1 = dram_Ch1_l2b1_wr_q[i];
7778 l2b1_wr_q_full_1 = l2b1_wr_q_loc_1[40] && l2b1_wr_q_full_1;
7779 //l2b1_wr_q_full_1_arb = (l2b1_wr_q_loc_1[39] && !dram_Ch1_l2b1_wr_que_rd_ptr_arb[i]) && l2b1_wr_q_full_1_arb;
7780 l2b1_wr_q_full_1_arb = (l2b1_wr_q_loc_1[39] && l2b1_wr_q_full_1_arb);
7781 l2b1_wr_q_cnt_1 = l2b1_wr_q_cnt_1 + l2b1_wr_q_loc_1[40];
7782
7783// MAQ N2 doesn't support l2b1_wr_q_cnt_1_arb = l2b1_wr_q_cnt_1_arb + (l2b1_wr_q_loc_1[39] && !dram_Ch1_l2b1_wr_que_rd_ptr_arb[i]);
7784
7785 end
7786 dram_Ch1_l2b1_wr_q_full <= l2b1_wr_q_full_1;
7787 dram_Ch1_l2b1_wr_q_full_arb <= l2b1_wr_q_full_1_arb;
7788 dram_Ch1_l2b1_wr_q_cnt <= l2b1_wr_q_cnt_1;
7789// MAQ N2 doesn't support dram_Ch1_l2b1_wr_q_cnt_arb <= l2b1_wr_q_cnt_1_arb;
7790 end
7791end
7792reg dram_Ch2_l2b0_wr_q_full;
7793reg dram_Ch2_l2b0_wr_q_full_arb;
7794reg [3:0] dram_Ch2_l2b0_wr_q_cnt;
7795// MAQ N2 doesn't support reg [3:0] dram_Ch2_l2b0_wr_q_cnt_arb;
7796reg l2b0_wr_q_full_2;
7797reg l2b0_wr_q_full_2_arb;
7798reg [40:0] l2b0_wr_q_loc_2;
7799reg [3:0] l2b0_wr_q_cnt_2;
7800reg [3:0] l2b0_wr_q_cnt_2_arb;
7801
7802always @(posedge (`MCU_CLK && enabled))
7803begin
7804 if (~dram_rst_l)
7805 begin
7806 dram_Ch2_l2b0_wr_q_full <= 1'b0;
7807 dram_Ch2_l2b0_wr_q_full_arb <= 1'b0;
7808 dram_Ch2_l2b0_wr_q_cnt <= 4'b0;
7809// MAQ N2 doesn't support dram_Ch2_l2b0_wr_q_cnt_arb <= 4'b0;
7810 end
7811 else
7812 begin
7813 l2b0_wr_q_full_2 = 1;
7814 l2b0_wr_q_full_2_arb = 1;
7815 l2b0_wr_q_cnt_2 = 0;
7816 l2b0_wr_q_cnt_2_arb = 0;
7817 for (i=0;i<8;i=i+1) begin
7818 l2b0_wr_q_loc_2 = dram_Ch2_l2b0_wr_q[i];
7819 l2b0_wr_q_full_2 = l2b0_wr_q_loc_2[40] && l2b0_wr_q_full_2;
7820 //l2b0_wr_q_full_2_arb = (l2b0_wr_q_loc_2[39] && !dram_Ch2_l2b0_wr_que_rd_ptr_arb[i]) && l2b0_wr_q_full_2_arb;
7821 l2b0_wr_q_full_2_arb = (l2b0_wr_q_loc_2[39] && l2b0_wr_q_full_2_arb);
7822 l2b0_wr_q_cnt_2 = l2b0_wr_q_cnt_2 + l2b0_wr_q_loc_2[40];
7823
7824// MAQ N2 doesn't support l2b0_wr_q_cnt_2_arb = l2b0_wr_q_cnt_2_arb + (l2b0_wr_q_loc_2[39] && !dram_Ch2_l2b0_wr_que_rd_ptr_arb[i]);
7825
7826 end
7827 dram_Ch2_l2b0_wr_q_full <= l2b0_wr_q_full_2;
7828 dram_Ch2_l2b0_wr_q_full_arb <= l2b0_wr_q_full_2_arb;
7829 dram_Ch2_l2b0_wr_q_cnt <= l2b0_wr_q_cnt_2;
7830// MAQ N2 doesn't support dram_Ch2_l2b0_wr_q_cnt_arb <= l2b0_wr_q_cnt_2_arb;
7831 end
7832end
7833reg dram_Ch2_l2b1_wr_q_full;
7834reg dram_Ch2_l2b1_wr_q_full_arb;
7835reg [3:0] dram_Ch2_l2b1_wr_q_cnt;
7836// MAQ N2 doesn't support reg [3:0] dram_Ch2_l2b1_wr_q_cnt_arb;
7837reg l2b1_wr_q_full_2;
7838reg l2b1_wr_q_full_2_arb;
7839reg [40:0] l2b1_wr_q_loc_2;
7840reg [3:0] l2b1_wr_q_cnt_2;
7841reg [3:0] l2b1_wr_q_cnt_2_arb;
7842
7843always @(posedge (`MCU_CLK && enabled))
7844begin
7845 if (~dram_rst_l)
7846 begin
7847 dram_Ch2_l2b1_wr_q_full <= 1'b0;
7848 dram_Ch2_l2b1_wr_q_full_arb <= 1'b0;
7849 dram_Ch2_l2b1_wr_q_cnt <= 4'b0;
7850// MAQ N2 doesn't support dram_Ch2_l2b1_wr_q_cnt_arb <= 4'b0;
7851 end
7852 else
7853 begin
7854 l2b1_wr_q_full_2 = 1;
7855 l2b1_wr_q_full_2_arb = 1;
7856 l2b1_wr_q_cnt_2 = 0;
7857 l2b1_wr_q_cnt_2_arb = 0;
7858 for (i=0;i<8;i=i+1) begin
7859 l2b1_wr_q_loc_2 = dram_Ch2_l2b1_wr_q[i];
7860 l2b1_wr_q_full_2 = l2b1_wr_q_loc_2[40] && l2b1_wr_q_full_2;
7861 //l2b1_wr_q_full_2_arb = (l2b1_wr_q_loc_2[39] && !dram_Ch2_l2b1_wr_que_rd_ptr_arb[i]) && l2b1_wr_q_full_2_arb;
7862 l2b1_wr_q_full_2_arb = (l2b1_wr_q_loc_2[39] && l2b1_wr_q_full_2_arb);
7863 l2b1_wr_q_cnt_2 = l2b1_wr_q_cnt_2 + l2b1_wr_q_loc_2[40];
7864
7865// MAQ N2 doesn't support l2b1_wr_q_cnt_2_arb = l2b1_wr_q_cnt_2_arb + (l2b1_wr_q_loc_2[39] && !dram_Ch2_l2b1_wr_que_rd_ptr_arb[i]);
7866
7867 end
7868 dram_Ch2_l2b1_wr_q_full <= l2b1_wr_q_full_2;
7869 dram_Ch2_l2b1_wr_q_full_arb <= l2b1_wr_q_full_2_arb;
7870 dram_Ch2_l2b1_wr_q_cnt <= l2b1_wr_q_cnt_2;
7871// MAQ N2 doesn't support dram_Ch2_l2b1_wr_q_cnt_arb <= l2b1_wr_q_cnt_2_arb;
7872 end
7873end
7874reg dram_Ch3_l2b0_wr_q_full;
7875reg dram_Ch3_l2b0_wr_q_full_arb;
7876reg [3:0] dram_Ch3_l2b0_wr_q_cnt;
7877// MAQ N2 doesn't support reg [3:0] dram_Ch3_l2b0_wr_q_cnt_arb;
7878reg l2b0_wr_q_full_3;
7879reg l2b0_wr_q_full_3_arb;
7880reg [40:0] l2b0_wr_q_loc_3;
7881reg [3:0] l2b0_wr_q_cnt_3;
7882reg [3:0] l2b0_wr_q_cnt_3_arb;
7883
7884always @(posedge (`MCU_CLK && enabled))
7885begin
7886 if (~dram_rst_l)
7887 begin
7888 dram_Ch3_l2b0_wr_q_full <= 1'b0;
7889 dram_Ch3_l2b0_wr_q_full_arb <= 1'b0;
7890 dram_Ch3_l2b0_wr_q_cnt <= 4'b0;
7891// MAQ N2 doesn't support dram_Ch3_l2b0_wr_q_cnt_arb <= 4'b0;
7892 end
7893 else
7894 begin
7895 l2b0_wr_q_full_3 = 1;
7896 l2b0_wr_q_full_3_arb = 1;
7897 l2b0_wr_q_cnt_3 = 0;
7898 l2b0_wr_q_cnt_3_arb = 0;
7899 for (i=0;i<8;i=i+1) begin
7900 l2b0_wr_q_loc_3 = dram_Ch3_l2b0_wr_q[i];
7901 l2b0_wr_q_full_3 = l2b0_wr_q_loc_3[40] && l2b0_wr_q_full_3;
7902 //l2b0_wr_q_full_3_arb = (l2b0_wr_q_loc_3[39] && !dram_Ch3_l2b0_wr_que_rd_ptr_arb[i]) && l2b0_wr_q_full_3_arb;
7903 l2b0_wr_q_full_3_arb = (l2b0_wr_q_loc_3[39] && l2b0_wr_q_full_3_arb);
7904 l2b0_wr_q_cnt_3 = l2b0_wr_q_cnt_3 + l2b0_wr_q_loc_3[40];
7905
7906// MAQ N2 doesn't support l2b0_wr_q_cnt_3_arb = l2b0_wr_q_cnt_3_arb + (l2b0_wr_q_loc_3[39] && !dram_Ch3_l2b0_wr_que_rd_ptr_arb[i]);
7907
7908 end
7909 dram_Ch3_l2b0_wr_q_full <= l2b0_wr_q_full_3;
7910 dram_Ch3_l2b0_wr_q_full_arb <= l2b0_wr_q_full_3_arb;
7911 dram_Ch3_l2b0_wr_q_cnt <= l2b0_wr_q_cnt_3;
7912// MAQ N2 doesn't support dram_Ch3_l2b0_wr_q_cnt_arb <= l2b0_wr_q_cnt_3_arb;
7913 end
7914end
7915reg dram_Ch3_l2b1_wr_q_full;
7916reg dram_Ch3_l2b1_wr_q_full_arb;
7917reg [3:0] dram_Ch3_l2b1_wr_q_cnt;
7918// MAQ N2 doesn't support reg [3:0] dram_Ch3_l2b1_wr_q_cnt_arb;
7919reg l2b1_wr_q_full_3;
7920reg l2b1_wr_q_full_3_arb;
7921reg [40:0] l2b1_wr_q_loc_3;
7922reg [3:0] l2b1_wr_q_cnt_3;
7923reg [3:0] l2b1_wr_q_cnt_3_arb;
7924
7925always @(posedge (`MCU_CLK && enabled))
7926begin
7927 if (~dram_rst_l)
7928 begin
7929 dram_Ch3_l2b1_wr_q_full <= 1'b0;
7930 dram_Ch3_l2b1_wr_q_full_arb <= 1'b0;
7931 dram_Ch3_l2b1_wr_q_cnt <= 4'b0;
7932// MAQ N2 doesn't support dram_Ch3_l2b1_wr_q_cnt_arb <= 4'b0;
7933 end
7934 else
7935 begin
7936 l2b1_wr_q_full_3 = 1;
7937 l2b1_wr_q_full_3_arb = 1;
7938 l2b1_wr_q_cnt_3 = 0;
7939 l2b1_wr_q_cnt_3_arb = 0;
7940 for (i=0;i<8;i=i+1) begin
7941 l2b1_wr_q_loc_3 = dram_Ch3_l2b1_wr_q[i];
7942 l2b1_wr_q_full_3 = l2b1_wr_q_loc_3[40] && l2b1_wr_q_full_3;
7943 //l2b1_wr_q_full_3_arb = (l2b1_wr_q_loc_3[39] && !dram_Ch3_l2b1_wr_que_rd_ptr_arb[i]) && l2b1_wr_q_full_3_arb;
7944 l2b1_wr_q_full_3_arb = (l2b1_wr_q_loc_3[39] && l2b1_wr_q_full_3_arb);
7945 l2b1_wr_q_cnt_3 = l2b1_wr_q_cnt_3 + l2b1_wr_q_loc_3[40];
7946
7947// MAQ N2 doesn't support l2b1_wr_q_cnt_3_arb = l2b1_wr_q_cnt_3_arb + (l2b1_wr_q_loc_3[39] && !dram_Ch3_l2b1_wr_que_rd_ptr_arb[i]);
7948
7949 end
7950 dram_Ch3_l2b1_wr_q_full <= l2b1_wr_q_full_3;
7951 dram_Ch3_l2b1_wr_q_full_arb <= l2b1_wr_q_full_3_arb;
7952 dram_Ch3_l2b1_wr_q_cnt <= l2b1_wr_q_cnt_3;
7953// MAQ N2 doesn't support dram_Ch3_l2b1_wr_q_cnt_arb <= l2b1_wr_q_cnt_3_arb;
7954 end
7955end
7956
7957// ----- DETECTING WR Q EMPTY -----
7958
7959reg dram_Ch0_l2b0_wr_q_empty;
7960reg dram_Ch0_l2b0_wr_q_empty_arb;
7961reg l2b0_wr_q_empty_0;
7962reg l2b0_wr_q_empty_0_arb;
7963reg [40:0] l2b0_wr_q_loc1_0;
7964always @(posedge (`MCU_CLK && enabled))
7965begin
7966 if (~dram_rst_l)
7967 begin
7968 dram_Ch0_l2b0_wr_q_empty <= 1'b0;
7969 dram_Ch0_l2b0_wr_q_empty_arb <= 1'b0;
7970 end
7971 else
7972 begin
7973 l2b0_wr_q_empty_0 = 0;
7974 l2b0_wr_q_empty_0_arb = 0;
7975 for (i=0;i<8;i=i+1) begin
7976 l2b0_wr_q_loc1_0 = dram_Ch0_l2b0_wr_q[i];
7977 l2b0_wr_q_empty_0 = l2b0_wr_q_loc1_0[40] || l2b0_wr_q_empty_0;
7978 l2b0_wr_q_empty_0_arb = l2b0_wr_q_loc1_0[39] || l2b0_wr_q_empty_0_arb;
7979 end
7980 dram_Ch0_l2b0_wr_q_empty <= ~l2b0_wr_q_empty_0;
7981 dram_Ch0_l2b0_wr_q_empty_arb <= ~l2b0_wr_q_empty_0_arb;
7982
7983 end
7984end
7985reg dram_Ch0_l2b1_wr_q_empty;
7986reg dram_Ch0_l2b1_wr_q_empty_arb;
7987reg l2b1_wr_q_empty_0;
7988reg l2b1_wr_q_empty_0_arb;
7989reg [40:0] l2b1_wr_q_loc1_0;
7990always @(posedge (`MCU_CLK && enabled))
7991begin
7992 if (~dram_rst_l)
7993 begin
7994 dram_Ch0_l2b1_wr_q_empty <= 1'b0;
7995 dram_Ch0_l2b1_wr_q_empty_arb <= 1'b0;
7996 end
7997 else
7998 begin
7999 l2b1_wr_q_empty_0 = 0;
8000 l2b1_wr_q_empty_0_arb = 0;
8001 for (i=0;i<8;i=i+1) begin
8002 l2b1_wr_q_loc1_0 = dram_Ch0_l2b1_wr_q[i];
8003 l2b1_wr_q_empty_0 = l2b1_wr_q_loc1_0[40] || l2b1_wr_q_empty_0;
8004 l2b1_wr_q_empty_0_arb = l2b1_wr_q_loc1_0[39] || l2b1_wr_q_empty_0_arb;
8005 end
8006 dram_Ch0_l2b1_wr_q_empty <= ~l2b1_wr_q_empty_0;
8007 dram_Ch0_l2b1_wr_q_empty_arb <= ~l2b1_wr_q_empty_0_arb;
8008
8009 end
8010end
8011reg dram_Ch1_l2b0_wr_q_empty;
8012reg dram_Ch1_l2b0_wr_q_empty_arb;
8013reg l2b0_wr_q_empty_1;
8014reg l2b0_wr_q_empty_1_arb;
8015reg [40:0] l2b0_wr_q_loc1_1;
8016always @(posedge (`MCU_CLK && enabled))
8017begin
8018 if (~dram_rst_l)
8019 begin
8020 dram_Ch1_l2b0_wr_q_empty <= 1'b0;
8021 dram_Ch1_l2b0_wr_q_empty_arb <= 1'b0;
8022 end
8023 else
8024 begin
8025 l2b0_wr_q_empty_1 = 0;
8026 l2b0_wr_q_empty_1_arb = 0;
8027 for (i=0;i<8;i=i+1) begin
8028 l2b0_wr_q_loc1_1 = dram_Ch1_l2b0_wr_q[i];
8029 l2b0_wr_q_empty_1 = l2b0_wr_q_loc1_1[40] || l2b0_wr_q_empty_1;
8030 l2b0_wr_q_empty_1_arb = l2b0_wr_q_loc1_1[39] || l2b0_wr_q_empty_1_arb;
8031 end
8032 dram_Ch1_l2b0_wr_q_empty <= ~l2b0_wr_q_empty_1;
8033 dram_Ch1_l2b0_wr_q_empty_arb <= ~l2b0_wr_q_empty_1_arb;
8034
8035 end
8036end
8037reg dram_Ch1_l2b1_wr_q_empty;
8038reg dram_Ch1_l2b1_wr_q_empty_arb;
8039reg l2b1_wr_q_empty_1;
8040reg l2b1_wr_q_empty_1_arb;
8041reg [40:0] l2b1_wr_q_loc1_1;
8042always @(posedge (`MCU_CLK && enabled))
8043begin
8044 if (~dram_rst_l)
8045 begin
8046 dram_Ch1_l2b1_wr_q_empty <= 1'b0;
8047 dram_Ch1_l2b1_wr_q_empty_arb <= 1'b0;
8048 end
8049 else
8050 begin
8051 l2b1_wr_q_empty_1 = 0;
8052 l2b1_wr_q_empty_1_arb = 0;
8053 for (i=0;i<8;i=i+1) begin
8054 l2b1_wr_q_loc1_1 = dram_Ch1_l2b1_wr_q[i];
8055 l2b1_wr_q_empty_1 = l2b1_wr_q_loc1_1[40] || l2b1_wr_q_empty_1;
8056 l2b1_wr_q_empty_1_arb = l2b1_wr_q_loc1_1[39] || l2b1_wr_q_empty_1_arb;
8057 end
8058 dram_Ch1_l2b1_wr_q_empty <= ~l2b1_wr_q_empty_1;
8059 dram_Ch1_l2b1_wr_q_empty_arb <= ~l2b1_wr_q_empty_1_arb;
8060
8061 end
8062end
8063reg dram_Ch2_l2b0_wr_q_empty;
8064reg dram_Ch2_l2b0_wr_q_empty_arb;
8065reg l2b0_wr_q_empty_2;
8066reg l2b0_wr_q_empty_2_arb;
8067reg [40:0] l2b0_wr_q_loc1_2;
8068always @(posedge (`MCU_CLK && enabled))
8069begin
8070 if (~dram_rst_l)
8071 begin
8072 dram_Ch2_l2b0_wr_q_empty <= 1'b0;
8073 dram_Ch2_l2b0_wr_q_empty_arb <= 1'b0;
8074 end
8075 else
8076 begin
8077 l2b0_wr_q_empty_2 = 0;
8078 l2b0_wr_q_empty_2_arb = 0;
8079 for (i=0;i<8;i=i+1) begin
8080 l2b0_wr_q_loc1_2 = dram_Ch2_l2b0_wr_q[i];
8081 l2b0_wr_q_empty_2 = l2b0_wr_q_loc1_2[40] || l2b0_wr_q_empty_2;
8082 l2b0_wr_q_empty_2_arb = l2b0_wr_q_loc1_2[39] || l2b0_wr_q_empty_2_arb;
8083 end
8084 dram_Ch2_l2b0_wr_q_empty <= ~l2b0_wr_q_empty_2;
8085 dram_Ch2_l2b0_wr_q_empty_arb <= ~l2b0_wr_q_empty_2_arb;
8086
8087 end
8088end
8089reg dram_Ch2_l2b1_wr_q_empty;
8090reg dram_Ch2_l2b1_wr_q_empty_arb;
8091reg l2b1_wr_q_empty_2;
8092reg l2b1_wr_q_empty_2_arb;
8093reg [40:0] l2b1_wr_q_loc1_2;
8094always @(posedge (`MCU_CLK && enabled))
8095begin
8096 if (~dram_rst_l)
8097 begin
8098 dram_Ch2_l2b1_wr_q_empty <= 1'b0;
8099 dram_Ch2_l2b1_wr_q_empty_arb <= 1'b0;
8100 end
8101 else
8102 begin
8103 l2b1_wr_q_empty_2 = 0;
8104 l2b1_wr_q_empty_2_arb = 0;
8105 for (i=0;i<8;i=i+1) begin
8106 l2b1_wr_q_loc1_2 = dram_Ch2_l2b1_wr_q[i];
8107 l2b1_wr_q_empty_2 = l2b1_wr_q_loc1_2[40] || l2b1_wr_q_empty_2;
8108 l2b1_wr_q_empty_2_arb = l2b1_wr_q_loc1_2[39] || l2b1_wr_q_empty_2_arb;
8109 end
8110 dram_Ch2_l2b1_wr_q_empty <= ~l2b1_wr_q_empty_2;
8111 dram_Ch2_l2b1_wr_q_empty_arb <= ~l2b1_wr_q_empty_2_arb;
8112
8113 end
8114end
8115reg dram_Ch3_l2b0_wr_q_empty;
8116reg dram_Ch3_l2b0_wr_q_empty_arb;
8117reg l2b0_wr_q_empty_3;
8118reg l2b0_wr_q_empty_3_arb;
8119reg [40:0] l2b0_wr_q_loc1_3;
8120always @(posedge (`MCU_CLK && enabled))
8121begin
8122 if (~dram_rst_l)
8123 begin
8124 dram_Ch3_l2b0_wr_q_empty <= 1'b0;
8125 dram_Ch3_l2b0_wr_q_empty_arb <= 1'b0;
8126 end
8127 else
8128 begin
8129 l2b0_wr_q_empty_3 = 0;
8130 l2b0_wr_q_empty_3_arb = 0;
8131 for (i=0;i<8;i=i+1) begin
8132 l2b0_wr_q_loc1_3 = dram_Ch3_l2b0_wr_q[i];
8133 l2b0_wr_q_empty_3 = l2b0_wr_q_loc1_3[40] || l2b0_wr_q_empty_3;
8134 l2b0_wr_q_empty_3_arb = l2b0_wr_q_loc1_3[39] || l2b0_wr_q_empty_3_arb;
8135 end
8136 dram_Ch3_l2b0_wr_q_empty <= ~l2b0_wr_q_empty_3;
8137 dram_Ch3_l2b0_wr_q_empty_arb <= ~l2b0_wr_q_empty_3_arb;
8138
8139 end
8140end
8141reg dram_Ch3_l2b1_wr_q_empty;
8142reg dram_Ch3_l2b1_wr_q_empty_arb;
8143reg l2b1_wr_q_empty_3;
8144reg l2b1_wr_q_empty_3_arb;
8145reg [40:0] l2b1_wr_q_loc1_3;
8146always @(posedge (`MCU_CLK && enabled))
8147begin
8148 if (~dram_rst_l)
8149 begin
8150 dram_Ch3_l2b1_wr_q_empty <= 1'b0;
8151 dram_Ch3_l2b1_wr_q_empty_arb <= 1'b0;
8152 end
8153 else
8154 begin
8155 l2b1_wr_q_empty_3 = 0;
8156 l2b1_wr_q_empty_3_arb = 0;
8157 for (i=0;i<8;i=i+1) begin
8158 l2b1_wr_q_loc1_3 = dram_Ch3_l2b1_wr_q[i];
8159 l2b1_wr_q_empty_3 = l2b1_wr_q_loc1_3[40] || l2b1_wr_q_empty_3;
8160 l2b1_wr_q_empty_3_arb = l2b1_wr_q_loc1_3[39] || l2b1_wr_q_empty_3_arb;
8161 end
8162 dram_Ch3_l2b1_wr_q_empty <= ~l2b1_wr_q_empty_3;
8163 dram_Ch3_l2b1_wr_q_empty_arb <= ~l2b1_wr_q_empty_3_arb;
8164
8165 end
8166end
8167
8168// ----- DETECTING WR COLLAPSING FIFO EMPTY ------
8169
8170reg dram_Ch0_l2b0_wr_colps_q_empty;
8171reg colps_l2b0_wr_q_empty_0;
8172reg [14:0] colps_l2b0_wr_q_loc1_0;
8173
8174always @(posedge (`MCU_CLK && enabled))
8175begin
8176 if (~dram_rst_l)
8177 begin
8178 dram_Ch0_l2b0_wr_colps_q_empty <= 1'b0;
8179 end
8180 else
8181 begin
8182 colps_l2b0_wr_q_empty_0 = 0;
8183 for (i=0;i<8;i=i+1) begin
8184 colps_l2b0_wr_q_loc1_0 = dram_Ch0_l2b0_wr_colps_q[i];
8185 colps_l2b0_wr_q_loc1_0[6] = dram_ch0_l2b0_wr_q_valids[i];
8186 colps_l2b0_wr_q_empty_0 = colps_l2b0_wr_q_loc1_0[6] || colps_l2b0_wr_q_empty_0;
8187 end
8188 dram_Ch0_l2b0_wr_colps_q_empty <= ~colps_l2b0_wr_q_empty_0;
8189 end
8190end
8191reg dram_Ch0_l2b1_wr_colps_q_empty;
8192reg colps_l2b1_wr_q_empty_0;
8193reg [14:0] colps_l2b1_wr_q_loc1_0;
8194
8195always @(posedge (`MCU_CLK && enabled))
8196begin
8197 if (~dram_rst_l)
8198 begin
8199 dram_Ch0_l2b1_wr_colps_q_empty <= 1'b0;
8200 end
8201 else
8202 begin
8203 colps_l2b1_wr_q_empty_0 = 0;
8204 for (i=0;i<8;i=i+1) begin
8205 colps_l2b1_wr_q_loc1_0 = dram_Ch0_l2b1_wr_colps_q[i];
8206 colps_l2b1_wr_q_loc1_0[6] = dram_ch0_l2b1_wr_q_valids[i];
8207 colps_l2b1_wr_q_empty_0 = colps_l2b1_wr_q_loc1_0[6] || colps_l2b1_wr_q_empty_0;
8208 end
8209 dram_Ch0_l2b1_wr_colps_q_empty <= ~colps_l2b1_wr_q_empty_0;
8210 end
8211end
8212reg dram_Ch1_l2b0_wr_colps_q_empty;
8213reg colps_l2b0_wr_q_empty_1;
8214reg [14:0] colps_l2b0_wr_q_loc1_1;
8215
8216always @(posedge (`MCU_CLK && enabled))
8217begin
8218 if (~dram_rst_l)
8219 begin
8220 dram_Ch1_l2b0_wr_colps_q_empty <= 1'b0;
8221 end
8222 else
8223 begin
8224 colps_l2b0_wr_q_empty_1 = 0;
8225 for (i=0;i<8;i=i+1) begin
8226 colps_l2b0_wr_q_loc1_1 = dram_Ch1_l2b0_wr_colps_q[i];
8227 colps_l2b0_wr_q_loc1_1[6] = dram_ch1_l2b0_wr_q_valids[i];
8228 colps_l2b0_wr_q_empty_1 = colps_l2b0_wr_q_loc1_1[6] || colps_l2b0_wr_q_empty_1;
8229 end
8230 dram_Ch1_l2b0_wr_colps_q_empty <= ~colps_l2b0_wr_q_empty_1;
8231 end
8232end
8233reg dram_Ch1_l2b1_wr_colps_q_empty;
8234reg colps_l2b1_wr_q_empty_1;
8235reg [14:0] colps_l2b1_wr_q_loc1_1;
8236
8237always @(posedge (`MCU_CLK && enabled))
8238begin
8239 if (~dram_rst_l)
8240 begin
8241 dram_Ch1_l2b1_wr_colps_q_empty <= 1'b0;
8242 end
8243 else
8244 begin
8245 colps_l2b1_wr_q_empty_1 = 0;
8246 for (i=0;i<8;i=i+1) begin
8247 colps_l2b1_wr_q_loc1_1 = dram_Ch1_l2b1_wr_colps_q[i];
8248 colps_l2b1_wr_q_loc1_1[6] = dram_ch1_l2b1_wr_q_valids[i];
8249 colps_l2b1_wr_q_empty_1 = colps_l2b1_wr_q_loc1_1[6] || colps_l2b1_wr_q_empty_1;
8250 end
8251 dram_Ch1_l2b1_wr_colps_q_empty <= ~colps_l2b1_wr_q_empty_1;
8252 end
8253end
8254reg dram_Ch2_l2b0_wr_colps_q_empty;
8255reg colps_l2b0_wr_q_empty_2;
8256reg [14:0] colps_l2b0_wr_q_loc1_2;
8257
8258always @(posedge (`MCU_CLK && enabled))
8259begin
8260 if (~dram_rst_l)
8261 begin
8262 dram_Ch2_l2b0_wr_colps_q_empty <= 1'b0;
8263 end
8264 else
8265 begin
8266 colps_l2b0_wr_q_empty_2 = 0;
8267 for (i=0;i<8;i=i+1) begin
8268 colps_l2b0_wr_q_loc1_2 = dram_Ch2_l2b0_wr_colps_q[i];
8269 colps_l2b0_wr_q_loc1_2[6] = dram_ch2_l2b0_wr_q_valids[i];
8270 colps_l2b0_wr_q_empty_2 = colps_l2b0_wr_q_loc1_2[6] || colps_l2b0_wr_q_empty_2;
8271 end
8272 dram_Ch2_l2b0_wr_colps_q_empty <= ~colps_l2b0_wr_q_empty_2;
8273 end
8274end
8275reg dram_Ch2_l2b1_wr_colps_q_empty;
8276reg colps_l2b1_wr_q_empty_2;
8277reg [14:0] colps_l2b1_wr_q_loc1_2;
8278
8279always @(posedge (`MCU_CLK && enabled))
8280begin
8281 if (~dram_rst_l)
8282 begin
8283 dram_Ch2_l2b1_wr_colps_q_empty <= 1'b0;
8284 end
8285 else
8286 begin
8287 colps_l2b1_wr_q_empty_2 = 0;
8288 for (i=0;i<8;i=i+1) begin
8289 colps_l2b1_wr_q_loc1_2 = dram_Ch2_l2b1_wr_colps_q[i];
8290 colps_l2b1_wr_q_loc1_2[6] = dram_ch2_l2b1_wr_q_valids[i];
8291 colps_l2b1_wr_q_empty_2 = colps_l2b1_wr_q_loc1_2[6] || colps_l2b1_wr_q_empty_2;
8292 end
8293 dram_Ch2_l2b1_wr_colps_q_empty <= ~colps_l2b1_wr_q_empty_2;
8294 end
8295end
8296reg dram_Ch3_l2b0_wr_colps_q_empty;
8297reg colps_l2b0_wr_q_empty_3;
8298reg [14:0] colps_l2b0_wr_q_loc1_3;
8299
8300always @(posedge (`MCU_CLK && enabled))
8301begin
8302 if (~dram_rst_l)
8303 begin
8304 dram_Ch3_l2b0_wr_colps_q_empty <= 1'b0;
8305 end
8306 else
8307 begin
8308 colps_l2b0_wr_q_empty_3 = 0;
8309 for (i=0;i<8;i=i+1) begin
8310 colps_l2b0_wr_q_loc1_3 = dram_Ch3_l2b0_wr_colps_q[i];
8311 colps_l2b0_wr_q_loc1_3[6] = dram_ch3_l2b0_wr_q_valids[i];
8312 colps_l2b0_wr_q_empty_3 = colps_l2b0_wr_q_loc1_3[6] || colps_l2b0_wr_q_empty_3;
8313 end
8314 dram_Ch3_l2b0_wr_colps_q_empty <= ~colps_l2b0_wr_q_empty_3;
8315 end
8316end
8317reg dram_Ch3_l2b1_wr_colps_q_empty;
8318reg colps_l2b1_wr_q_empty_3;
8319reg [14:0] colps_l2b1_wr_q_loc1_3;
8320
8321always @(posedge (`MCU_CLK && enabled))
8322begin
8323 if (~dram_rst_l)
8324 begin
8325 dram_Ch3_l2b1_wr_colps_q_empty <= 1'b0;
8326 end
8327 else
8328 begin
8329 colps_l2b1_wr_q_empty_3 = 0;
8330 for (i=0;i<8;i=i+1) begin
8331 colps_l2b1_wr_q_loc1_3 = dram_Ch3_l2b1_wr_colps_q[i];
8332 colps_l2b1_wr_q_loc1_3[6] = dram_ch3_l2b1_wr_q_valids[i];
8333 colps_l2b1_wr_q_empty_3 = colps_l2b1_wr_q_loc1_3[6] || colps_l2b1_wr_q_empty_3;
8334 end
8335 dram_Ch3_l2b1_wr_colps_q_empty <= ~colps_l2b1_wr_q_empty_3;
8336 end
8337end
8338
8339// ------ CROSS BETWEEN WR Q AND WR COLLAPSING FIFO -------
8340
8341reg [2:0] l2b0_wr_index_0;
8342reg [2:0] l2b0_wr_curr_index_0;
8343reg [40:0] l2b0_wr_q_0;
8344reg [14:0] colps_l2b0_wr_q_loc2_0;
8345
8346always @(posedge (`MCU_CLK && enabled))
8347begin
8348 if (~dram_rst_l)
8349 begin
8350 end
8351
8352 else
8353 if (dram_ch0_l2b0_drq_write_queue_cnt != 4'b0000)
8354 begin
8355
8356 // collapsing fifo indexes to the read q. If there is no
8357 // corresponding valid entry then error.
8358 for(i=0;i<8;i=i+1) begin
8359 colps_l2b0_wr_q_loc2_0 = dram_Ch0_l2b0_wr_colps_q[i];
8360 if (dram_ch0_l2b0_wr_q_valids[i]) begin
8361 l2b0_wr_index_0 = colps_l2b0_wr_q_loc2_0[11:9];
8362 l2b0_wr_q_0 = dram_Ch0_l2b0_wr_q[l2b0_wr_index_0];
8363/*mb156858*/ if ((l2b0_wr_q_0[39] == 1'b0) || (l2b0_wr_q_0[40] == 1'b0)) begin
8364 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
8365 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 0);
8366 end
8367 end
8368 end
8369
8370 // all entries in the collapsing fifo should be unique
8371 for(i=0;i<8;i=i+1) begin
8372 colps_l2b0_wr_q_loc2_0 = dram_Ch0_l2b0_wr_colps_q[i];
8373 if (dram_ch0_l2b0_wr_q_valids[i]) begin
8374 l2b0_wr_curr_index_0 = colps_l2b0_wr_q_loc2_0[11:9];
8375 for(j=i+1;j<8;j=j+1) begin
8376 colps_l2b0_wr_q_loc2_0 = dram_Ch0_l2b0_wr_colps_q[j];
8377
8378/*mb156858 if (dram_ch0_l2b0_wr_q_valids[j] && ( colps_l2b0_wr_q_loc2_0[11:9] == l2b0_wr_curr_index_0)) begin
8379 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
8380 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 0);
8381 end */
8382 end
8383 end
8384 end
8385
8386 end
8387end
8388reg [2:0] l2b1_wr_index_0;
8389reg [2:0] l2b1_wr_curr_index_0;
8390reg [40:0] l2b1_wr_q_0;
8391reg [14:0] colps_l2b1_wr_q_loc2_0;
8392
8393always @(posedge (`MCU_CLK && enabled))
8394begin
8395 if (~dram_rst_l)
8396 begin
8397 end
8398
8399 else
8400 if (dram_ch0_l2b1_drq_write_queue_cnt != 4'b0000)
8401 begin
8402
8403 // collapsing fifo indexes to the read q. If there is no
8404 // corresponding valid entry then error.
8405 for(i=0;i<8;i=i+1) begin
8406 colps_l2b1_wr_q_loc2_0 = dram_Ch0_l2b1_wr_colps_q[i];
8407 if (dram_ch0_l2b1_wr_q_valids[i]) begin
8408 l2b1_wr_index_0 = colps_l2b1_wr_q_loc2_0[11:9];
8409 l2b1_wr_q_0 = dram_Ch0_l2b1_wr_q[l2b1_wr_index_0];
8410/*mb156858*/ if ((l2b1_wr_q_0[39] == 1'b0) || (l2b1_wr_q_0[40] == 1'b0)) begin
8411 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
8412 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 0);
8413 end
8414 end
8415 end
8416
8417 // all entries in the collapsing fifo should be unique
8418 for(i=0;i<8;i=i+1) begin
8419 colps_l2b1_wr_q_loc2_0 = dram_Ch0_l2b1_wr_colps_q[i];
8420 if (dram_ch0_l2b1_wr_q_valids[i]) begin
8421 l2b1_wr_curr_index_0 = colps_l2b1_wr_q_loc2_0[11:9];
8422 for(j=i+1;j<8;j=j+1) begin
8423 colps_l2b1_wr_q_loc2_0 = dram_Ch0_l2b1_wr_colps_q[j];
8424
8425/*mb156858 if (dram_ch0_l2b1_wr_q_valids[j] && ( colps_l2b1_wr_q_loc2_0[11:9] == l2b1_wr_curr_index_0)) begin
8426 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
8427 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 0);
8428 end */
8429 end
8430 end
8431 end
8432
8433 end
8434end
8435reg [2:0] l2b0_wr_index_1;
8436reg [2:0] l2b0_wr_curr_index_1;
8437reg [40:0] l2b0_wr_q_1;
8438reg [14:0] colps_l2b0_wr_q_loc2_1;
8439
8440always @(posedge (`MCU_CLK && enabled))
8441begin
8442 if (~dram_rst_l)
8443 begin
8444 end
8445
8446 else
8447 if (dram_ch1_l2b0_drq_write_queue_cnt != 4'b0000)
8448 begin
8449
8450 // collapsing fifo indexes to the read q. If there is no
8451 // corresponding valid entry then error.
8452 for(i=0;i<8;i=i+1) begin
8453 colps_l2b0_wr_q_loc2_1 = dram_Ch1_l2b0_wr_colps_q[i];
8454 if (dram_ch1_l2b0_wr_q_valids[i]) begin
8455 l2b0_wr_index_1 = colps_l2b0_wr_q_loc2_1[11:9];
8456 l2b0_wr_q_1 = dram_Ch1_l2b0_wr_q[l2b0_wr_index_1];
8457/*mb156858*/ if ((l2b0_wr_q_1[39] == 1'b0) || (l2b0_wr_q_1[40] == 1'b0)) begin
8458 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
8459 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 1);
8460 end
8461 end
8462 end
8463
8464 // all entries in the collapsing fifo should be unique
8465 for(i=0;i<8;i=i+1) begin
8466 colps_l2b0_wr_q_loc2_1 = dram_Ch1_l2b0_wr_colps_q[i];
8467 if (dram_ch1_l2b0_wr_q_valids[i]) begin
8468 l2b0_wr_curr_index_1 = colps_l2b0_wr_q_loc2_1[11:9];
8469 for(j=i+1;j<8;j=j+1) begin
8470 colps_l2b0_wr_q_loc2_1 = dram_Ch1_l2b0_wr_colps_q[j];
8471
8472/*mb156858 if (dram_ch1_l2b0_wr_q_valids[j] && ( colps_l2b0_wr_q_loc2_1[11:9] == l2b0_wr_curr_index_1)) begin
8473 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
8474 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 1);
8475 end */
8476 end
8477 end
8478 end
8479
8480 end
8481end
8482reg [2:0] l2b1_wr_index_1;
8483reg [2:0] l2b1_wr_curr_index_1;
8484reg [40:0] l2b1_wr_q_1;
8485reg [14:0] colps_l2b1_wr_q_loc2_1;
8486
8487always @(posedge (`MCU_CLK && enabled))
8488begin
8489 if (~dram_rst_l)
8490 begin
8491 end
8492
8493 else
8494 if (dram_ch1_l2b1_drq_write_queue_cnt != 4'b0000)
8495 begin
8496
8497 // collapsing fifo indexes to the read q. If there is no
8498 // corresponding valid entry then error.
8499 for(i=0;i<8;i=i+1) begin
8500 colps_l2b1_wr_q_loc2_1 = dram_Ch1_l2b1_wr_colps_q[i];
8501 if (dram_ch1_l2b1_wr_q_valids[i]) begin
8502 l2b1_wr_index_1 = colps_l2b1_wr_q_loc2_1[11:9];
8503 l2b1_wr_q_1 = dram_Ch1_l2b1_wr_q[l2b1_wr_index_1];
8504/*mb156858*/ if ((l2b1_wr_q_1[39] == 1'b0) || (l2b1_wr_q_1[40] == 1'b0)) begin
8505 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
8506 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 1);
8507 end
8508 end
8509 end
8510
8511 // all entries in the collapsing fifo should be unique
8512 for(i=0;i<8;i=i+1) begin
8513 colps_l2b1_wr_q_loc2_1 = dram_Ch1_l2b1_wr_colps_q[i];
8514 if (dram_ch1_l2b1_wr_q_valids[i]) begin
8515 l2b1_wr_curr_index_1 = colps_l2b1_wr_q_loc2_1[11:9];
8516 for(j=i+1;j<8;j=j+1) begin
8517 colps_l2b1_wr_q_loc2_1 = dram_Ch1_l2b1_wr_colps_q[j];
8518
8519/*mb156858 if (dram_ch1_l2b1_wr_q_valids[j] && ( colps_l2b1_wr_q_loc2_1[11:9] == l2b1_wr_curr_index_1)) begin
8520 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
8521 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 1);
8522 end */
8523 end
8524 end
8525 end
8526
8527 end
8528end
8529reg [2:0] l2b0_wr_index_2;
8530reg [2:0] l2b0_wr_curr_index_2;
8531reg [40:0] l2b0_wr_q_2;
8532reg [14:0] colps_l2b0_wr_q_loc2_2;
8533
8534always @(posedge (`MCU_CLK && enabled))
8535begin
8536 if (~dram_rst_l)
8537 begin
8538 end
8539
8540 else
8541 if (dram_ch2_l2b0_drq_write_queue_cnt != 4'b0000)
8542 begin
8543
8544 // collapsing fifo indexes to the read q. If there is no
8545 // corresponding valid entry then error.
8546 for(i=0;i<8;i=i+1) begin
8547 colps_l2b0_wr_q_loc2_2 = dram_Ch2_l2b0_wr_colps_q[i];
8548 if (dram_ch2_l2b0_wr_q_valids[i]) begin
8549 l2b0_wr_index_2 = colps_l2b0_wr_q_loc2_2[11:9];
8550 l2b0_wr_q_2 = dram_Ch2_l2b0_wr_q[l2b0_wr_index_2];
8551/*mb156858*/ if ((l2b0_wr_q_2[39] == 1'b0) || (l2b0_wr_q_2[40] == 1'b0)) begin
8552 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
8553 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 2);
8554 end
8555 end
8556 end
8557
8558 // all entries in the collapsing fifo should be unique
8559 for(i=0;i<8;i=i+1) begin
8560 colps_l2b0_wr_q_loc2_2 = dram_Ch2_l2b0_wr_colps_q[i];
8561 if (dram_ch2_l2b0_wr_q_valids[i]) begin
8562 l2b0_wr_curr_index_2 = colps_l2b0_wr_q_loc2_2[11:9];
8563 for(j=i+1;j<8;j=j+1) begin
8564 colps_l2b0_wr_q_loc2_2 = dram_Ch2_l2b0_wr_colps_q[j];
8565
8566/*mb156858 if (dram_ch2_l2b0_wr_q_valids[j] && ( colps_l2b0_wr_q_loc2_2[11:9] == l2b0_wr_curr_index_2)) begin
8567 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
8568 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 2);
8569 end */
8570 end
8571 end
8572 end
8573
8574 end
8575end
8576reg [2:0] l2b1_wr_index_2;
8577reg [2:0] l2b1_wr_curr_index_2;
8578reg [40:0] l2b1_wr_q_2;
8579reg [14:0] colps_l2b1_wr_q_loc2_2;
8580
8581always @(posedge (`MCU_CLK && enabled))
8582begin
8583 if (~dram_rst_l)
8584 begin
8585 end
8586
8587 else
8588 if (dram_ch2_l2b1_drq_write_queue_cnt != 4'b0000)
8589 begin
8590
8591 // collapsing fifo indexes to the read q. If there is no
8592 // corresponding valid entry then error.
8593 for(i=0;i<8;i=i+1) begin
8594 colps_l2b1_wr_q_loc2_2 = dram_Ch2_l2b1_wr_colps_q[i];
8595 if (dram_ch2_l2b1_wr_q_valids[i]) begin
8596 l2b1_wr_index_2 = colps_l2b1_wr_q_loc2_2[11:9];
8597 l2b1_wr_q_2 = dram_Ch2_l2b1_wr_q[l2b1_wr_index_2];
8598/*mb156858*/ if ((l2b1_wr_q_2[39] == 1'b0) || (l2b1_wr_q_2[40] == 1'b0)) begin
8599 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
8600 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 2);
8601 end
8602 end
8603 end
8604
8605 // all entries in the collapsing fifo should be unique
8606 for(i=0;i<8;i=i+1) begin
8607 colps_l2b1_wr_q_loc2_2 = dram_Ch2_l2b1_wr_colps_q[i];
8608 if (dram_ch2_l2b1_wr_q_valids[i]) begin
8609 l2b1_wr_curr_index_2 = colps_l2b1_wr_q_loc2_2[11:9];
8610 for(j=i+1;j<8;j=j+1) begin
8611 colps_l2b1_wr_q_loc2_2 = dram_Ch2_l2b1_wr_colps_q[j];
8612
8613/*mb156858 if (dram_ch2_l2b1_wr_q_valids[j] && ( colps_l2b1_wr_q_loc2_2[11:9] == l2b1_wr_curr_index_2)) begin
8614 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
8615 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 2);
8616 end */
8617 end
8618 end
8619 end
8620
8621 end
8622end
8623reg [2:0] l2b0_wr_index_3;
8624reg [2:0] l2b0_wr_curr_index_3;
8625reg [40:0] l2b0_wr_q_3;
8626reg [14:0] colps_l2b0_wr_q_loc2_3;
8627
8628always @(posedge (`MCU_CLK && enabled))
8629begin
8630 if (~dram_rst_l)
8631 begin
8632 end
8633
8634 else
8635 if (dram_ch3_l2b0_drq_write_queue_cnt != 4'b0000)
8636 begin
8637
8638 // collapsing fifo indexes to the read q. If there is no
8639 // corresponding valid entry then error.
8640 for(i=0;i<8;i=i+1) begin
8641 colps_l2b0_wr_q_loc2_3 = dram_Ch3_l2b0_wr_colps_q[i];
8642 if (dram_ch3_l2b0_wr_q_valids[i]) begin
8643 l2b0_wr_index_3 = colps_l2b0_wr_q_loc2_3[11:9];
8644 l2b0_wr_q_3 = dram_Ch3_l2b0_wr_q[l2b0_wr_index_3];
8645/*mb156858*/ if ((l2b0_wr_q_3[39] == 1'b0) || (l2b0_wr_q_3[40] == 1'b0)) begin
8646 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
8647 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 3);
8648 end
8649 end
8650 end
8651
8652 // all entries in the collapsing fifo should be unique
8653 for(i=0;i<8;i=i+1) begin
8654 colps_l2b0_wr_q_loc2_3 = dram_Ch3_l2b0_wr_colps_q[i];
8655 if (dram_ch3_l2b0_wr_q_valids[i]) begin
8656 l2b0_wr_curr_index_3 = colps_l2b0_wr_q_loc2_3[11:9];
8657 for(j=i+1;j<8;j=j+1) begin
8658 colps_l2b0_wr_q_loc2_3 = dram_Ch3_l2b0_wr_colps_q[j];
8659
8660/*mb156858 if (dram_ch3_l2b0_wr_q_valids[j] && ( colps_l2b0_wr_q_loc2_3[11:9] == l2b0_wr_curr_index_3)) begin
8661 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
8662 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 3);
8663 end */
8664 end
8665 end
8666 end
8667
8668 end
8669end
8670reg [2:0] l2b1_wr_index_3;
8671reg [2:0] l2b1_wr_curr_index_3;
8672reg [40:0] l2b1_wr_q_3;
8673reg [14:0] colps_l2b1_wr_q_loc2_3;
8674
8675always @(posedge (`MCU_CLK && enabled))
8676begin
8677 if (~dram_rst_l)
8678 begin
8679 end
8680
8681 else
8682 if (dram_ch3_l2b1_drq_write_queue_cnt != 4'b0000)
8683 begin
8684
8685 // collapsing fifo indexes to the read q. If there is no
8686 // corresponding valid entry then error.
8687 for(i=0;i<8;i=i+1) begin
8688 colps_l2b1_wr_q_loc2_3 = dram_Ch3_l2b1_wr_colps_q[i];
8689 if (dram_ch3_l2b1_wr_q_valids[i]) begin
8690 l2b1_wr_index_3 = colps_l2b1_wr_q_loc2_3[11:9];
8691 l2b1_wr_q_3 = dram_Ch3_l2b1_wr_q[l2b1_wr_index_3];
8692/*mb156858*/ if ((l2b1_wr_q_3[39] == 1'b0) || (l2b1_wr_q_3[40] == 1'b0)) begin
8693 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
8694 finish_test(" WR Q : No valid entry in WR Q for entry in collpsing WR fifo ", 3);
8695 end
8696 end
8697 end
8698
8699 // all entries in the collapsing fifo should be unique
8700 for(i=0;i<8;i=i+1) begin
8701 colps_l2b1_wr_q_loc2_3 = dram_Ch3_l2b1_wr_colps_q[i];
8702 if (dram_ch3_l2b1_wr_q_valids[i]) begin
8703 l2b1_wr_curr_index_3 = colps_l2b1_wr_q_loc2_3[11:9];
8704 for(j=i+1;j<8;j=j+1) begin
8705 colps_l2b1_wr_q_loc2_3 = dram_Ch3_l2b1_wr_colps_q[j];
8706
8707/*mb156858 if (dram_ch3_l2b1_wr_q_valids[j] && ( colps_l2b1_wr_q_loc2_3[11:9] == l2b1_wr_curr_index_3)) begin
8708 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
8709 finish_test(" WR Q : The valid entries in the write collapsing fifo are not unique", 3);
8710 end */
8711 end
8712 end
8713 end
8714
8715 end
8716end
8717
8718// WR QUE OR ARB REQUEST VALID WITHOUT DATA VALId
8719
8720 reg [40:0] l2b0_wr_q_loc2_0;
8721always @( posedge clk)
8722begin
8723if (dram_rst_l) begin
8724 for(i=0;i<8;i=i+1) begin
8725 l2b0_wr_q_loc2_0 = dram_Ch0_l2b0_wr_q[i];
8726 if (l2b0_wr_q_loc2_0[39] && !l2b0_wr_q_loc2_0[40]) begin
8727 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
8728 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 0);
8729 end
8730 end
8731end
8732end
8733 reg [40:0] l2b1_wr_q_loc2_0;
8734always @( posedge clk)
8735begin
8736if (dram_rst_l) begin
8737 for(i=0;i<8;i=i+1) begin
8738 l2b1_wr_q_loc2_0 = dram_Ch0_l2b1_wr_q[i];
8739 if (l2b1_wr_q_loc2_0[39] && !l2b1_wr_q_loc2_0[40]) begin
8740 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
8741 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 0);
8742 end
8743 end
8744end
8745end
8746 reg [40:0] l2b0_wr_q_loc2_1;
8747always @( posedge clk)
8748begin
8749if (dram_rst_l) begin
8750 for(i=0;i<8;i=i+1) begin
8751 l2b0_wr_q_loc2_1 = dram_Ch1_l2b0_wr_q[i];
8752 if (l2b0_wr_q_loc2_1[39] && !l2b0_wr_q_loc2_1[40]) begin
8753 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
8754 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 1);
8755 end
8756 end
8757end
8758end
8759 reg [40:0] l2b1_wr_q_loc2_1;
8760always @( posedge clk)
8761begin
8762if (dram_rst_l) begin
8763 for(i=0;i<8;i=i+1) begin
8764 l2b1_wr_q_loc2_1 = dram_Ch1_l2b1_wr_q[i];
8765 if (l2b1_wr_q_loc2_1[39] && !l2b1_wr_q_loc2_1[40]) begin
8766 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
8767 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 1);
8768 end
8769 end
8770end
8771end
8772 reg [40:0] l2b0_wr_q_loc2_2;
8773always @( posedge clk)
8774begin
8775if (dram_rst_l) begin
8776 for(i=0;i<8;i=i+1) begin
8777 l2b0_wr_q_loc2_2 = dram_Ch2_l2b0_wr_q[i];
8778 if (l2b0_wr_q_loc2_2[39] && !l2b0_wr_q_loc2_2[40]) begin
8779 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
8780 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 2);
8781 end
8782 end
8783end
8784end
8785 reg [40:0] l2b1_wr_q_loc2_2;
8786always @( posedge clk)
8787begin
8788if (dram_rst_l) begin
8789 for(i=0;i<8;i=i+1) begin
8790 l2b1_wr_q_loc2_2 = dram_Ch2_l2b1_wr_q[i];
8791 if (l2b1_wr_q_loc2_2[39] && !l2b1_wr_q_loc2_2[40]) begin
8792 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
8793 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 2);
8794 end
8795 end
8796end
8797end
8798 reg [40:0] l2b0_wr_q_loc2_3;
8799always @( posedge clk)
8800begin
8801if (dram_rst_l) begin
8802 for(i=0;i<8;i=i+1) begin
8803 l2b0_wr_q_loc2_3 = dram_Ch3_l2b0_wr_q[i];
8804 if (l2b0_wr_q_loc2_3[39] && !l2b0_wr_q_loc2_3[40]) begin
8805 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
8806 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 3);
8807 end
8808 end
8809end
8810end
8811 reg [40:0] l2b1_wr_q_loc2_3;
8812always @( posedge clk)
8813begin
8814if (dram_rst_l) begin
8815 for(i=0;i<8;i=i+1) begin
8816 l2b1_wr_q_loc2_3 = dram_Ch3_l2b1_wr_q[i];
8817 if (l2b1_wr_q_loc2_3[39] && !l2b1_wr_q_loc2_3[40]) begin
8818 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
8819 finish_test(" WR Q : Arb wr req valid and data valid not Valid ", 3);
8820 end
8821 end
8822end
8823end
8824
8825// actual data valid creation.
8826reg [7:0] dram_Ch0_l2b0_wr_que_dv_actual;
8827reg [7:0] dram_Ch0_l2b0_l2if_wr_entry_d1;
8828always @( posedge clk)
8829begin
8830if (~dram_rst_l) begin
8831 dram_Ch0_l2b0_wr_que_dv_actual[7:0] <= 8'b0;
8832 dram_Ch0_l2b0_l2if_wr_entry_d1[7:0] <= 8'b0;
8833end else begin
8834 dram_Ch0_l2b0_l2if_wr_entry_d1[7:0] <= dram_Ch0_l2b0_l2if_wr_entry[7:0];
8835 for(i=0;i<8;i=i+1) begin
8836 if (dram_Ch0_l2b0_wr_que_rd_ptr[i]) begin
8837 dram_Ch0_l2b0_wr_que_dv_actual[i] <= 1'b0;
8838 end else begin
8839 if (dram_Ch0_l2b0_l2if_wr_entry[i] == 1) begin
8840 dram_Ch0_l2b0_wr_que_dv_actual[i] <= 1'b1;
8841 end
8842 end
8843 end
8844end
8845end
8846reg [7:0] dram_Ch0_l2b1_wr_que_dv_actual;
8847reg [7:0] dram_Ch0_l2b1_l2if_wr_entry_d1;
8848always @( posedge clk)
8849begin
8850if (~dram_rst_l) begin
8851 dram_Ch0_l2b1_wr_que_dv_actual[7:0] <= 8'b0;
8852 dram_Ch0_l2b1_l2if_wr_entry_d1[7:0] <= 8'b0;
8853end else begin
8854 dram_Ch0_l2b1_l2if_wr_entry_d1[7:0] <= dram_Ch0_l2b1_l2if_wr_entry[7:0];
8855 for(i=0;i<8;i=i+1) begin
8856 if (dram_Ch0_l2b1_wr_que_rd_ptr[i]) begin
8857 dram_Ch0_l2b1_wr_que_dv_actual[i] <= 1'b0;
8858 end else begin
8859 if (dram_Ch0_l2b1_l2if_wr_entry[i] == 1) begin
8860 dram_Ch0_l2b1_wr_que_dv_actual[i] <= 1'b1;
8861 end
8862 end
8863 end
8864end
8865end
8866reg [7:0] dram_Ch1_l2b0_wr_que_dv_actual;
8867reg [7:0] dram_Ch1_l2b0_l2if_wr_entry_d1;
8868always @( posedge clk)
8869begin
8870if (~dram_rst_l) begin
8871 dram_Ch1_l2b0_wr_que_dv_actual[7:0] <= 8'b0;
8872 dram_Ch1_l2b0_l2if_wr_entry_d1[7:0] <= 8'b0;
8873end else begin
8874 dram_Ch1_l2b0_l2if_wr_entry_d1[7:0] <= dram_Ch1_l2b0_l2if_wr_entry[7:0];
8875 for(i=0;i<8;i=i+1) begin
8876 if (dram_Ch1_l2b0_wr_que_rd_ptr[i]) begin
8877 dram_Ch1_l2b0_wr_que_dv_actual[i] <= 1'b0;
8878 end else begin
8879 if (dram_Ch1_l2b0_l2if_wr_entry[i] == 1) begin
8880 dram_Ch1_l2b0_wr_que_dv_actual[i] <= 1'b1;
8881 end
8882 end
8883 end
8884end
8885end
8886reg [7:0] dram_Ch1_l2b1_wr_que_dv_actual;
8887reg [7:0] dram_Ch1_l2b1_l2if_wr_entry_d1;
8888always @( posedge clk)
8889begin
8890if (~dram_rst_l) begin
8891 dram_Ch1_l2b1_wr_que_dv_actual[7:0] <= 8'b0;
8892 dram_Ch1_l2b1_l2if_wr_entry_d1[7:0] <= 8'b0;
8893end else begin
8894 dram_Ch1_l2b1_l2if_wr_entry_d1[7:0] <= dram_Ch1_l2b1_l2if_wr_entry[7:0];
8895 for(i=0;i<8;i=i+1) begin
8896 if (dram_Ch1_l2b1_wr_que_rd_ptr[i]) begin
8897 dram_Ch1_l2b1_wr_que_dv_actual[i] <= 1'b0;
8898 end else begin
8899 if (dram_Ch1_l2b1_l2if_wr_entry[i] == 1) begin
8900 dram_Ch1_l2b1_wr_que_dv_actual[i] <= 1'b1;
8901 end
8902 end
8903 end
8904end
8905end
8906reg [7:0] dram_Ch2_l2b0_wr_que_dv_actual;
8907reg [7:0] dram_Ch2_l2b0_l2if_wr_entry_d1;
8908always @( posedge clk)
8909begin
8910if (~dram_rst_l) begin
8911 dram_Ch2_l2b0_wr_que_dv_actual[7:0] <= 8'b0;
8912 dram_Ch2_l2b0_l2if_wr_entry_d1[7:0] <= 8'b0;
8913end else begin
8914 dram_Ch2_l2b0_l2if_wr_entry_d1[7:0] <= dram_Ch2_l2b0_l2if_wr_entry[7:0];
8915 for(i=0;i<8;i=i+1) begin
8916 if (dram_Ch2_l2b0_wr_que_rd_ptr[i]) begin
8917 dram_Ch2_l2b0_wr_que_dv_actual[i] <= 1'b0;
8918 end else begin
8919 if (dram_Ch2_l2b0_l2if_wr_entry[i] == 1) begin
8920 dram_Ch2_l2b0_wr_que_dv_actual[i] <= 1'b1;
8921 end
8922 end
8923 end
8924end
8925end
8926reg [7:0] dram_Ch2_l2b1_wr_que_dv_actual;
8927reg [7:0] dram_Ch2_l2b1_l2if_wr_entry_d1;
8928always @( posedge clk)
8929begin
8930if (~dram_rst_l) begin
8931 dram_Ch2_l2b1_wr_que_dv_actual[7:0] <= 8'b0;
8932 dram_Ch2_l2b1_l2if_wr_entry_d1[7:0] <= 8'b0;
8933end else begin
8934 dram_Ch2_l2b1_l2if_wr_entry_d1[7:0] <= dram_Ch2_l2b1_l2if_wr_entry[7:0];
8935 for(i=0;i<8;i=i+1) begin
8936 if (dram_Ch2_l2b1_wr_que_rd_ptr[i]) begin
8937 dram_Ch2_l2b1_wr_que_dv_actual[i] <= 1'b0;
8938 end else begin
8939 if (dram_Ch2_l2b1_l2if_wr_entry[i] == 1) begin
8940 dram_Ch2_l2b1_wr_que_dv_actual[i] <= 1'b1;
8941 end
8942 end
8943 end
8944end
8945end
8946reg [7:0] dram_Ch3_l2b0_wr_que_dv_actual;
8947reg [7:0] dram_Ch3_l2b0_l2if_wr_entry_d1;
8948always @( posedge clk)
8949begin
8950if (~dram_rst_l) begin
8951 dram_Ch3_l2b0_wr_que_dv_actual[7:0] <= 8'b0;
8952 dram_Ch3_l2b0_l2if_wr_entry_d1[7:0] <= 8'b0;
8953end else begin
8954 dram_Ch3_l2b0_l2if_wr_entry_d1[7:0] <= dram_Ch3_l2b0_l2if_wr_entry[7:0];
8955 for(i=0;i<8;i=i+1) begin
8956 if (dram_Ch3_l2b0_wr_que_rd_ptr[i]) begin
8957 dram_Ch3_l2b0_wr_que_dv_actual[i] <= 1'b0;
8958 end else begin
8959 if (dram_Ch3_l2b0_l2if_wr_entry[i] == 1) begin
8960 dram_Ch3_l2b0_wr_que_dv_actual[i] <= 1'b1;
8961 end
8962 end
8963 end
8964end
8965end
8966reg [7:0] dram_Ch3_l2b1_wr_que_dv_actual;
8967reg [7:0] dram_Ch3_l2b1_l2if_wr_entry_d1;
8968always @( posedge clk)
8969begin
8970if (~dram_rst_l) begin
8971 dram_Ch3_l2b1_wr_que_dv_actual[7:0] <= 8'b0;
8972 dram_Ch3_l2b1_l2if_wr_entry_d1[7:0] <= 8'b0;
8973end else begin
8974 dram_Ch3_l2b1_l2if_wr_entry_d1[7:0] <= dram_Ch3_l2b1_l2if_wr_entry[7:0];
8975 for(i=0;i<8;i=i+1) begin
8976 if (dram_Ch3_l2b1_wr_que_rd_ptr[i]) begin
8977 dram_Ch3_l2b1_wr_que_dv_actual[i] <= 1'b0;
8978 end else begin
8979 if (dram_Ch3_l2b1_l2if_wr_entry[i] == 1) begin
8980 dram_Ch3_l2b1_wr_que_dv_actual[i] <= 1'b1;
8981 end
8982 end
8983 end
8984end
8985end
8986
8987
8988// -------- Monitor for making sure that valid data is there in the fifo when write data is read from the DRAM Side. ( Data valid before CAS issued ) ------
8989
8990
8991wire [63:0] l2b0_dv_0;
8992reg [63:0] l2b0_dv_0_reg;
8993
8994wire [1:0] wr_en_l2b0_0 = ~dram_Ch0_l2b0_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_0 = dram_Ch0_cpu_wr_en;
8995wire [4:0] l2b0_wr_addr_0 = dram_Ch0_l2b0_cpu_wr_addr;
8996wire rd_en_l2b0_0 = ~dram_Ch0_l2b0_wdq_rd_en;
8997wire [4:0] rd_addr_l2b0_0 = dram_Ch0_l2b0_wdq_radr[4:0];
8998
8999// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
9000// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
9001// $p dv index
9002// $q 0 1 2 3
9003// $r addr
9004
9005assign l2b0_dv_0[0] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 0) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[0] ) &&
9006 ~((rd_addr_l2b0_0 == 0) && !rd_en_l2b0_0);
9007assign l2b0_dv_0[1] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 0) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[1] ) &&
9008 ~((rd_addr_l2b0_0 == 0) && !rd_en_l2b0_0);
9009assign l2b0_dv_0[2] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 1) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[2] ) &&
9010 ~((rd_addr_l2b0_0 == 1) && !rd_en_l2b0_0);
9011assign l2b0_dv_0[3] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 1) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[3] ) &&
9012 ~((rd_addr_l2b0_0 == 1) && !rd_en_l2b0_0);
9013assign l2b0_dv_0[4] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 2) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[4] ) &&
9014 ~((rd_addr_l2b0_0 == 2) && !rd_en_l2b0_0);
9015assign l2b0_dv_0[5] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 2) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[5] ) &&
9016 ~((rd_addr_l2b0_0 == 2) && !rd_en_l2b0_0);
9017assign l2b0_dv_0[6] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 3) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[6] ) &&
9018 ~((rd_addr_l2b0_0 == 3) && !rd_en_l2b0_0);
9019assign l2b0_dv_0[7] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 3) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[7] ) &&
9020 ~((rd_addr_l2b0_0 == 3) && !rd_en_l2b0_0);
9021assign l2b0_dv_0[8] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 4) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[8] ) &&
9022 ~((rd_addr_l2b0_0 == 4) && !rd_en_l2b0_0);
9023assign l2b0_dv_0[9] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 4) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[9] ) &&
9024 ~((rd_addr_l2b0_0 == 4) && !rd_en_l2b0_0);
9025assign l2b0_dv_0[10] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 5) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[10] ) &&
9026 ~((rd_addr_l2b0_0 == 5) && !rd_en_l2b0_0);
9027assign l2b0_dv_0[11] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 5) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[11] ) &&
9028 ~((rd_addr_l2b0_0 == 5) && !rd_en_l2b0_0);
9029assign l2b0_dv_0[12] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 6) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[12] ) &&
9030 ~((rd_addr_l2b0_0 == 6) && !rd_en_l2b0_0);
9031assign l2b0_dv_0[13] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 6) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[13] ) &&
9032 ~((rd_addr_l2b0_0 == 6) && !rd_en_l2b0_0);
9033assign l2b0_dv_0[14] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 7) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[14] ) &&
9034 ~((rd_addr_l2b0_0 == 7) && !rd_en_l2b0_0);
9035assign l2b0_dv_0[15] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 7) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[15] ) &&
9036 ~((rd_addr_l2b0_0 == 7) && !rd_en_l2b0_0);
9037assign l2b0_dv_0[16] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 8) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[16] ) &&
9038 ~((rd_addr_l2b0_0 == 8) && !rd_en_l2b0_0);
9039assign l2b0_dv_0[17] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 8) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[17] ) &&
9040 ~((rd_addr_l2b0_0 == 8) && !rd_en_l2b0_0);
9041assign l2b0_dv_0[18] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 9) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[18] ) &&
9042 ~((rd_addr_l2b0_0 == 9) && !rd_en_l2b0_0);
9043assign l2b0_dv_0[19] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 9) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[19] ) &&
9044 ~((rd_addr_l2b0_0 == 9) && !rd_en_l2b0_0);
9045assign l2b0_dv_0[20] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 10) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[20] ) &&
9046 ~((rd_addr_l2b0_0 == 10) && !rd_en_l2b0_0);
9047assign l2b0_dv_0[21] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 10) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[21] ) &&
9048 ~((rd_addr_l2b0_0 == 10) && !rd_en_l2b0_0);
9049assign l2b0_dv_0[22] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 11) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[22] ) &&
9050 ~((rd_addr_l2b0_0 == 11) && !rd_en_l2b0_0);
9051assign l2b0_dv_0[23] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 11) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[23] ) &&
9052 ~((rd_addr_l2b0_0 == 11) && !rd_en_l2b0_0);
9053assign l2b0_dv_0[24] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 12) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[24] ) &&
9054 ~((rd_addr_l2b0_0 == 12) && !rd_en_l2b0_0);
9055assign l2b0_dv_0[25] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 12) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[25] ) &&
9056 ~((rd_addr_l2b0_0 == 12) && !rd_en_l2b0_0);
9057assign l2b0_dv_0[26] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 13) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[26] ) &&
9058 ~((rd_addr_l2b0_0 == 13) && !rd_en_l2b0_0);
9059assign l2b0_dv_0[27] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 13) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[27] ) &&
9060 ~((rd_addr_l2b0_0 == 13) && !rd_en_l2b0_0);
9061assign l2b0_dv_0[28] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 14) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[28] ) &&
9062 ~((rd_addr_l2b0_0 == 14) && !rd_en_l2b0_0);
9063assign l2b0_dv_0[29] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 14) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[29] ) &&
9064 ~((rd_addr_l2b0_0 == 14) && !rd_en_l2b0_0);
9065assign l2b0_dv_0[30] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 15) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[30] ) &&
9066 ~((rd_addr_l2b0_0 == 15) && !rd_en_l2b0_0);
9067assign l2b0_dv_0[31] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 15) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[31] ) &&
9068 ~((rd_addr_l2b0_0 == 15) && !rd_en_l2b0_0);
9069assign l2b0_dv_0[32] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 16) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[32] ) &&
9070 ~((rd_addr_l2b0_0 == 16) && !rd_en_l2b0_0);
9071assign l2b0_dv_0[33] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 16) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[33] ) &&
9072 ~((rd_addr_l2b0_0 == 16) && !rd_en_l2b0_0);
9073assign l2b0_dv_0[34] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 17) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[34] ) &&
9074 ~((rd_addr_l2b0_0 == 17) && !rd_en_l2b0_0);
9075assign l2b0_dv_0[35] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 17) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[35] ) &&
9076 ~((rd_addr_l2b0_0 == 17) && !rd_en_l2b0_0);
9077assign l2b0_dv_0[36] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 18) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[36] ) &&
9078 ~((rd_addr_l2b0_0 == 18) && !rd_en_l2b0_0);
9079assign l2b0_dv_0[37] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 18) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[37] ) &&
9080 ~((rd_addr_l2b0_0 == 18) && !rd_en_l2b0_0);
9081assign l2b0_dv_0[38] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 19) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[38] ) &&
9082 ~((rd_addr_l2b0_0 == 19) && !rd_en_l2b0_0);
9083assign l2b0_dv_0[39] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 19) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[39] ) &&
9084 ~((rd_addr_l2b0_0 == 19) && !rd_en_l2b0_0);
9085assign l2b0_dv_0[40] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 20) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[40] ) &&
9086 ~((rd_addr_l2b0_0 == 20) && !rd_en_l2b0_0);
9087assign l2b0_dv_0[41] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 20) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[41] ) &&
9088 ~((rd_addr_l2b0_0 == 20) && !rd_en_l2b0_0);
9089assign l2b0_dv_0[42] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 21) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[42] ) &&
9090 ~((rd_addr_l2b0_0 == 21) && !rd_en_l2b0_0);
9091assign l2b0_dv_0[43] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 21) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[43] ) &&
9092 ~((rd_addr_l2b0_0 == 21) && !rd_en_l2b0_0);
9093assign l2b0_dv_0[44] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 22) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[44] ) &&
9094 ~((rd_addr_l2b0_0 == 22) && !rd_en_l2b0_0);
9095assign l2b0_dv_0[45] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 22) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[45] ) &&
9096 ~((rd_addr_l2b0_0 == 22) && !rd_en_l2b0_0);
9097assign l2b0_dv_0[46] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 23) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[46] ) &&
9098 ~((rd_addr_l2b0_0 == 23) && !rd_en_l2b0_0);
9099assign l2b0_dv_0[47] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 23) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[47] ) &&
9100 ~((rd_addr_l2b0_0 == 23) && !rd_en_l2b0_0);
9101assign l2b0_dv_0[48] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 24) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[48] ) &&
9102 ~((rd_addr_l2b0_0 == 24) && !rd_en_l2b0_0);
9103assign l2b0_dv_0[49] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 24) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[49] ) &&
9104 ~((rd_addr_l2b0_0 == 24) && !rd_en_l2b0_0);
9105assign l2b0_dv_0[50] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 25) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[50] ) &&
9106 ~((rd_addr_l2b0_0 == 25) && !rd_en_l2b0_0);
9107assign l2b0_dv_0[51] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 25) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[51] ) &&
9108 ~((rd_addr_l2b0_0 == 25) && !rd_en_l2b0_0);
9109assign l2b0_dv_0[52] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 26) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[52] ) &&
9110 ~((rd_addr_l2b0_0 == 26) && !rd_en_l2b0_0);
9111assign l2b0_dv_0[53] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 26) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[53] ) &&
9112 ~((rd_addr_l2b0_0 == 26) && !rd_en_l2b0_0);
9113assign l2b0_dv_0[54] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 27) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[54] ) &&
9114 ~((rd_addr_l2b0_0 == 27) && !rd_en_l2b0_0);
9115assign l2b0_dv_0[55] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 27) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[55] ) &&
9116 ~((rd_addr_l2b0_0 == 27) && !rd_en_l2b0_0);
9117assign l2b0_dv_0[56] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 28) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[56] ) &&
9118 ~((rd_addr_l2b0_0 == 28) && !rd_en_l2b0_0);
9119assign l2b0_dv_0[57] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 28) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[57] ) &&
9120 ~((rd_addr_l2b0_0 == 28) && !rd_en_l2b0_0);
9121assign l2b0_dv_0[58] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 29) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[58] ) &&
9122 ~((rd_addr_l2b0_0 == 29) && !rd_en_l2b0_0);
9123assign l2b0_dv_0[59] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 29) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[59] ) &&
9124 ~((rd_addr_l2b0_0 == 29) && !rd_en_l2b0_0);
9125assign l2b0_dv_0[60] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 30) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[60] ) &&
9126 ~((rd_addr_l2b0_0 == 30) && !rd_en_l2b0_0);
9127assign l2b0_dv_0[61] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 30) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[61] ) &&
9128 ~((rd_addr_l2b0_0 == 30) && !rd_en_l2b0_0);
9129assign l2b0_dv_0[62] = ((!wr_en_l2b0_0[0] && (l2b0_wr_addr_0 == 31) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[62] ) &&
9130 ~((rd_addr_l2b0_0 == 31) && !rd_en_l2b0_0);
9131assign l2b0_dv_0[63] = ((!wr_en_l2b0_0[1] && (l2b0_wr_addr_0 == 31) && !dram_Ch0_l2b0_pa_err) || l2b0_dv_0_reg[63] ) &&
9132 ~((rd_addr_l2b0_0 == 31) && !rd_en_l2b0_0);
9133
9134always @(posedge (cmp_clk && enabled)) begin
9135 if (~cmp_rst_l)
9136 begin
9137 l2b0_dv_0_reg <= 64'b0;
9138 end
9139 else begin
9140 l2b0_dv_0_reg <= l2b0_dv_0;
9141 end
9142end
9143
9144// actual monitor
9145// if read and the locations dv not valid
9146// monitoring in cmp_clk and so should be monitored only on the first clock
9147// after which the rd may be valid in the dram clock
9148reg dram_rst_l_l2b0_0_1;
9149reg [5:0] addr_reg_l2b0_0;
9150always @ (posedge (cmp_clk && enabled))
9151begin
9152if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
9153end else begin
9154
9155// need to delay as on 1st dram clk after reset the rd_en has still not
9156dram_rst_l_l2b0_0_1 <= #1 dram_rst_l;
9157addr_reg_l2b0_0 <= #1 {rd_en_l2b0_0, rd_addr_l2b0_0};
9158
9159if (dram_rst_l_l2b0_0_1 && (~rd_en_l2b0_0) &&
9160 (addr_reg_l2b0_0 != {rd_en_l2b0_0, rd_addr_l2b0_0}) &&
9161 (rd_addr_l2b0_0[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
9162/*mb156858 if (!l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 0] || !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 1] ||
9163 !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 2] || !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 3] ||
9164 !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 4] || !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 5] ||
9165 !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 6] || !l2b0_dv_0_reg[rd_addr_l2b0_0*2 + 7]) begin
9166 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
9167 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b0_0, l2b0_dv_0_reg);
9168 finish_test(" CAS Issued Data not valid ", 0);
9169 end */
9170end
9171end
9172end
9173
9174
9175// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
9176
9177always @ (posedge (cmp_clk && enabled))
9178begin
9179if (cmp_rst_l && (~wr_en_l2b0_0[0])) begin
9180 if (l2b0_dv_0_reg[l2b0_wr_addr_0*2 + 0]) begin
9181 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
9182 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_0,wr_en_l2b0_0, l2b0_dv_0_reg);
9183 finish_test(" Data Overwritten in write fifo ", 0);
9184 end
9185end
9186if (cmp_rst_l && (~wr_en_l2b0_0[1])) begin
9187 if (l2b0_dv_0_reg[l2b0_wr_addr_0*2 + 1]) begin
9188 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
9189 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_0,wr_en_l2b0_0, l2b0_dv_0_reg);
9190 finish_test(" Data Overwritten in write fifo ", 0);
9191 end
9192end
9193end
9194
9195
9196wire [63:0] l2b1_dv_0;
9197reg [63:0] l2b1_dv_0_reg;
9198
9199wire [1:0] wr_en_l2b1_0 = ~dram_Ch0_l2b1_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_0 = dram_Ch0_cpu_wr_en;
9200wire [4:0] l2b1_wr_addr_0 = dram_Ch0_l2b1_cpu_wr_addr;
9201wire rd_en_l2b1_0 = ~dram_Ch0_l2b1_wdq_rd_en;
9202wire [4:0] rd_addr_l2b1_0 = dram_Ch0_l2b1_wdq_radr[4:0];
9203
9204// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
9205// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
9206// $p dv index
9207// $q 0 1 2 3
9208// $r addr
9209
9210assign l2b1_dv_0[0] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 0) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[0] ) &&
9211 ~((rd_addr_l2b1_0 == 0) && !rd_en_l2b1_0);
9212assign l2b1_dv_0[1] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 0) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[1] ) &&
9213 ~((rd_addr_l2b1_0 == 0) && !rd_en_l2b1_0);
9214assign l2b1_dv_0[2] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 1) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[2] ) &&
9215 ~((rd_addr_l2b1_0 == 1) && !rd_en_l2b1_0);
9216assign l2b1_dv_0[3] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 1) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[3] ) &&
9217 ~((rd_addr_l2b1_0 == 1) && !rd_en_l2b1_0);
9218assign l2b1_dv_0[4] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 2) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[4] ) &&
9219 ~((rd_addr_l2b1_0 == 2) && !rd_en_l2b1_0);
9220assign l2b1_dv_0[5] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 2) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[5] ) &&
9221 ~((rd_addr_l2b1_0 == 2) && !rd_en_l2b1_0);
9222assign l2b1_dv_0[6] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 3) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[6] ) &&
9223 ~((rd_addr_l2b1_0 == 3) && !rd_en_l2b1_0);
9224assign l2b1_dv_0[7] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 3) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[7] ) &&
9225 ~((rd_addr_l2b1_0 == 3) && !rd_en_l2b1_0);
9226assign l2b1_dv_0[8] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 4) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[8] ) &&
9227 ~((rd_addr_l2b1_0 == 4) && !rd_en_l2b1_0);
9228assign l2b1_dv_0[9] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 4) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[9] ) &&
9229 ~((rd_addr_l2b1_0 == 4) && !rd_en_l2b1_0);
9230assign l2b1_dv_0[10] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 5) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[10] ) &&
9231 ~((rd_addr_l2b1_0 == 5) && !rd_en_l2b1_0);
9232assign l2b1_dv_0[11] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 5) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[11] ) &&
9233 ~((rd_addr_l2b1_0 == 5) && !rd_en_l2b1_0);
9234assign l2b1_dv_0[12] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 6) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[12] ) &&
9235 ~((rd_addr_l2b1_0 == 6) && !rd_en_l2b1_0);
9236assign l2b1_dv_0[13] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 6) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[13] ) &&
9237 ~((rd_addr_l2b1_0 == 6) && !rd_en_l2b1_0);
9238assign l2b1_dv_0[14] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 7) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[14] ) &&
9239 ~((rd_addr_l2b1_0 == 7) && !rd_en_l2b1_0);
9240assign l2b1_dv_0[15] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 7) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[15] ) &&
9241 ~((rd_addr_l2b1_0 == 7) && !rd_en_l2b1_0);
9242assign l2b1_dv_0[16] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 8) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[16] ) &&
9243 ~((rd_addr_l2b1_0 == 8) && !rd_en_l2b1_0);
9244assign l2b1_dv_0[17] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 8) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[17] ) &&
9245 ~((rd_addr_l2b1_0 == 8) && !rd_en_l2b1_0);
9246assign l2b1_dv_0[18] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 9) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[18] ) &&
9247 ~((rd_addr_l2b1_0 == 9) && !rd_en_l2b1_0);
9248assign l2b1_dv_0[19] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 9) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[19] ) &&
9249 ~((rd_addr_l2b1_0 == 9) && !rd_en_l2b1_0);
9250assign l2b1_dv_0[20] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 10) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[20] ) &&
9251 ~((rd_addr_l2b1_0 == 10) && !rd_en_l2b1_0);
9252assign l2b1_dv_0[21] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 10) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[21] ) &&
9253 ~((rd_addr_l2b1_0 == 10) && !rd_en_l2b1_0);
9254assign l2b1_dv_0[22] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 11) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[22] ) &&
9255 ~((rd_addr_l2b1_0 == 11) && !rd_en_l2b1_0);
9256assign l2b1_dv_0[23] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 11) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[23] ) &&
9257 ~((rd_addr_l2b1_0 == 11) && !rd_en_l2b1_0);
9258assign l2b1_dv_0[24] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 12) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[24] ) &&
9259 ~((rd_addr_l2b1_0 == 12) && !rd_en_l2b1_0);
9260assign l2b1_dv_0[25] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 12) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[25] ) &&
9261 ~((rd_addr_l2b1_0 == 12) && !rd_en_l2b1_0);
9262assign l2b1_dv_0[26] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 13) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[26] ) &&
9263 ~((rd_addr_l2b1_0 == 13) && !rd_en_l2b1_0);
9264assign l2b1_dv_0[27] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 13) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[27] ) &&
9265 ~((rd_addr_l2b1_0 == 13) && !rd_en_l2b1_0);
9266assign l2b1_dv_0[28] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 14) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[28] ) &&
9267 ~((rd_addr_l2b1_0 == 14) && !rd_en_l2b1_0);
9268assign l2b1_dv_0[29] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 14) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[29] ) &&
9269 ~((rd_addr_l2b1_0 == 14) && !rd_en_l2b1_0);
9270assign l2b1_dv_0[30] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 15) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[30] ) &&
9271 ~((rd_addr_l2b1_0 == 15) && !rd_en_l2b1_0);
9272assign l2b1_dv_0[31] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 15) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[31] ) &&
9273 ~((rd_addr_l2b1_0 == 15) && !rd_en_l2b1_0);
9274assign l2b1_dv_0[32] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 16) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[32] ) &&
9275 ~((rd_addr_l2b1_0 == 16) && !rd_en_l2b1_0);
9276assign l2b1_dv_0[33] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 16) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[33] ) &&
9277 ~((rd_addr_l2b1_0 == 16) && !rd_en_l2b1_0);
9278assign l2b1_dv_0[34] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 17) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[34] ) &&
9279 ~((rd_addr_l2b1_0 == 17) && !rd_en_l2b1_0);
9280assign l2b1_dv_0[35] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 17) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[35] ) &&
9281 ~((rd_addr_l2b1_0 == 17) && !rd_en_l2b1_0);
9282assign l2b1_dv_0[36] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 18) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[36] ) &&
9283 ~((rd_addr_l2b1_0 == 18) && !rd_en_l2b1_0);
9284assign l2b1_dv_0[37] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 18) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[37] ) &&
9285 ~((rd_addr_l2b1_0 == 18) && !rd_en_l2b1_0);
9286assign l2b1_dv_0[38] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 19) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[38] ) &&
9287 ~((rd_addr_l2b1_0 == 19) && !rd_en_l2b1_0);
9288assign l2b1_dv_0[39] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 19) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[39] ) &&
9289 ~((rd_addr_l2b1_0 == 19) && !rd_en_l2b1_0);
9290assign l2b1_dv_0[40] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 20) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[40] ) &&
9291 ~((rd_addr_l2b1_0 == 20) && !rd_en_l2b1_0);
9292assign l2b1_dv_0[41] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 20) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[41] ) &&
9293 ~((rd_addr_l2b1_0 == 20) && !rd_en_l2b1_0);
9294assign l2b1_dv_0[42] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 21) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[42] ) &&
9295 ~((rd_addr_l2b1_0 == 21) && !rd_en_l2b1_0);
9296assign l2b1_dv_0[43] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 21) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[43] ) &&
9297 ~((rd_addr_l2b1_0 == 21) && !rd_en_l2b1_0);
9298assign l2b1_dv_0[44] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 22) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[44] ) &&
9299 ~((rd_addr_l2b1_0 == 22) && !rd_en_l2b1_0);
9300assign l2b1_dv_0[45] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 22) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[45] ) &&
9301 ~((rd_addr_l2b1_0 == 22) && !rd_en_l2b1_0);
9302assign l2b1_dv_0[46] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 23) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[46] ) &&
9303 ~((rd_addr_l2b1_0 == 23) && !rd_en_l2b1_0);
9304assign l2b1_dv_0[47] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 23) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[47] ) &&
9305 ~((rd_addr_l2b1_0 == 23) && !rd_en_l2b1_0);
9306assign l2b1_dv_0[48] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 24) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[48] ) &&
9307 ~((rd_addr_l2b1_0 == 24) && !rd_en_l2b1_0);
9308assign l2b1_dv_0[49] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 24) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[49] ) &&
9309 ~((rd_addr_l2b1_0 == 24) && !rd_en_l2b1_0);
9310assign l2b1_dv_0[50] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 25) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[50] ) &&
9311 ~((rd_addr_l2b1_0 == 25) && !rd_en_l2b1_0);
9312assign l2b1_dv_0[51] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 25) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[51] ) &&
9313 ~((rd_addr_l2b1_0 == 25) && !rd_en_l2b1_0);
9314assign l2b1_dv_0[52] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 26) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[52] ) &&
9315 ~((rd_addr_l2b1_0 == 26) && !rd_en_l2b1_0);
9316assign l2b1_dv_0[53] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 26) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[53] ) &&
9317 ~((rd_addr_l2b1_0 == 26) && !rd_en_l2b1_0);
9318assign l2b1_dv_0[54] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 27) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[54] ) &&
9319 ~((rd_addr_l2b1_0 == 27) && !rd_en_l2b1_0);
9320assign l2b1_dv_0[55] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 27) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[55] ) &&
9321 ~((rd_addr_l2b1_0 == 27) && !rd_en_l2b1_0);
9322assign l2b1_dv_0[56] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 28) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[56] ) &&
9323 ~((rd_addr_l2b1_0 == 28) && !rd_en_l2b1_0);
9324assign l2b1_dv_0[57] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 28) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[57] ) &&
9325 ~((rd_addr_l2b1_0 == 28) && !rd_en_l2b1_0);
9326assign l2b1_dv_0[58] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 29) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[58] ) &&
9327 ~((rd_addr_l2b1_0 == 29) && !rd_en_l2b1_0);
9328assign l2b1_dv_0[59] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 29) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[59] ) &&
9329 ~((rd_addr_l2b1_0 == 29) && !rd_en_l2b1_0);
9330assign l2b1_dv_0[60] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 30) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[60] ) &&
9331 ~((rd_addr_l2b1_0 == 30) && !rd_en_l2b1_0);
9332assign l2b1_dv_0[61] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 30) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[61] ) &&
9333 ~((rd_addr_l2b1_0 == 30) && !rd_en_l2b1_0);
9334assign l2b1_dv_0[62] = ((!wr_en_l2b1_0[0] && (l2b1_wr_addr_0 == 31) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[62] ) &&
9335 ~((rd_addr_l2b1_0 == 31) && !rd_en_l2b1_0);
9336assign l2b1_dv_0[63] = ((!wr_en_l2b1_0[1] && (l2b1_wr_addr_0 == 31) && !dram_Ch0_l2b1_pa_err) || l2b1_dv_0_reg[63] ) &&
9337 ~((rd_addr_l2b1_0 == 31) && !rd_en_l2b1_0);
9338
9339always @(posedge (cmp_clk && enabled)) begin
9340 if (~cmp_rst_l)
9341 begin
9342 l2b1_dv_0_reg <= 64'b0;
9343 end
9344 else begin
9345 l2b1_dv_0_reg <= l2b1_dv_0;
9346 end
9347end
9348
9349// actual monitor
9350// if read and the locations dv not valid
9351// monitoring in cmp_clk and so should be monitored only on the first clock
9352// after which the rd may be valid in the dram clock
9353reg dram_rst_l_l2b1_0_1;
9354reg [5:0] addr_reg_l2b1_0;
9355always @ (posedge (cmp_clk && enabled))
9356begin
9357if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
9358end else begin
9359
9360// need to delay as on 1st dram clk after reset the rd_en has still not
9361dram_rst_l_l2b1_0_1 <= #1 dram_rst_l;
9362addr_reg_l2b1_0 <= #1 {rd_en_l2b1_0, rd_addr_l2b1_0};
9363
9364if (dram_rst_l_l2b1_0_1 && (~rd_en_l2b1_0) &&
9365 (addr_reg_l2b1_0 != {rd_en_l2b1_0, rd_addr_l2b1_0}) &&
9366 (rd_addr_l2b1_0[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
9367/*mb156858 if (!l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 0] || !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 1] ||
9368 !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 2] || !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 3] ||
9369 !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 4] || !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 5] ||
9370 !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 6] || !l2b1_dv_0_reg[rd_addr_l2b1_0*2 + 7]) begin
9371 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
9372 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b1_0, l2b1_dv_0_reg);
9373 finish_test(" CAS Issued Data not valid ", 0);
9374 end */
9375end
9376end
9377end
9378
9379
9380// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
9381
9382always @ (posedge (cmp_clk && enabled))
9383begin
9384if (cmp_rst_l && (~wr_en_l2b1_0[0])) begin
9385 if (l2b1_dv_0_reg[l2b1_wr_addr_0*2 + 0]) begin
9386 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
9387 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_0,wr_en_l2b1_0, l2b1_dv_0_reg);
9388 finish_test(" Data Overwritten in write fifo ", 0);
9389 end
9390end
9391if (cmp_rst_l && (~wr_en_l2b1_0[1])) begin
9392 if (l2b1_dv_0_reg[l2b1_wr_addr_0*2 + 1]) begin
9393 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
9394 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_0,wr_en_l2b1_0, l2b1_dv_0_reg);
9395 finish_test(" Data Overwritten in write fifo ", 0);
9396 end
9397end
9398end
9399
9400
9401wire [63:0] l2b0_dv_1;
9402reg [63:0] l2b0_dv_1_reg;
9403
9404wire [1:0] wr_en_l2b0_1 = ~dram_Ch1_l2b0_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_1 = dram_Ch1_cpu_wr_en;
9405wire [4:0] l2b0_wr_addr_1 = dram_Ch1_l2b0_cpu_wr_addr;
9406wire rd_en_l2b0_1 = ~dram_Ch1_l2b0_wdq_rd_en;
9407wire [4:0] rd_addr_l2b0_1 = dram_Ch1_l2b0_wdq_radr[4:0];
9408
9409// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
9410// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
9411// $p dv index
9412// $q 0 1 2 3
9413// $r addr
9414
9415assign l2b0_dv_1[0] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 0) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[0] ) &&
9416 ~((rd_addr_l2b0_1 == 0) && !rd_en_l2b0_1);
9417assign l2b0_dv_1[1] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 0) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[1] ) &&
9418 ~((rd_addr_l2b0_1 == 0) && !rd_en_l2b0_1);
9419assign l2b0_dv_1[2] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 1) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[2] ) &&
9420 ~((rd_addr_l2b0_1 == 1) && !rd_en_l2b0_1);
9421assign l2b0_dv_1[3] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 1) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[3] ) &&
9422 ~((rd_addr_l2b0_1 == 1) && !rd_en_l2b0_1);
9423assign l2b0_dv_1[4] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 2) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[4] ) &&
9424 ~((rd_addr_l2b0_1 == 2) && !rd_en_l2b0_1);
9425assign l2b0_dv_1[5] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 2) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[5] ) &&
9426 ~((rd_addr_l2b0_1 == 2) && !rd_en_l2b0_1);
9427assign l2b0_dv_1[6] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 3) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[6] ) &&
9428 ~((rd_addr_l2b0_1 == 3) && !rd_en_l2b0_1);
9429assign l2b0_dv_1[7] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 3) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[7] ) &&
9430 ~((rd_addr_l2b0_1 == 3) && !rd_en_l2b0_1);
9431assign l2b0_dv_1[8] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 4) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[8] ) &&
9432 ~((rd_addr_l2b0_1 == 4) && !rd_en_l2b0_1);
9433assign l2b0_dv_1[9] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 4) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[9] ) &&
9434 ~((rd_addr_l2b0_1 == 4) && !rd_en_l2b0_1);
9435assign l2b0_dv_1[10] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 5) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[10] ) &&
9436 ~((rd_addr_l2b0_1 == 5) && !rd_en_l2b0_1);
9437assign l2b0_dv_1[11] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 5) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[11] ) &&
9438 ~((rd_addr_l2b0_1 == 5) && !rd_en_l2b0_1);
9439assign l2b0_dv_1[12] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 6) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[12] ) &&
9440 ~((rd_addr_l2b0_1 == 6) && !rd_en_l2b0_1);
9441assign l2b0_dv_1[13] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 6) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[13] ) &&
9442 ~((rd_addr_l2b0_1 == 6) && !rd_en_l2b0_1);
9443assign l2b0_dv_1[14] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 7) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[14] ) &&
9444 ~((rd_addr_l2b0_1 == 7) && !rd_en_l2b0_1);
9445assign l2b0_dv_1[15] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 7) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[15] ) &&
9446 ~((rd_addr_l2b0_1 == 7) && !rd_en_l2b0_1);
9447assign l2b0_dv_1[16] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 8) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[16] ) &&
9448 ~((rd_addr_l2b0_1 == 8) && !rd_en_l2b0_1);
9449assign l2b0_dv_1[17] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 8) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[17] ) &&
9450 ~((rd_addr_l2b0_1 == 8) && !rd_en_l2b0_1);
9451assign l2b0_dv_1[18] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 9) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[18] ) &&
9452 ~((rd_addr_l2b0_1 == 9) && !rd_en_l2b0_1);
9453assign l2b0_dv_1[19] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 9) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[19] ) &&
9454 ~((rd_addr_l2b0_1 == 9) && !rd_en_l2b0_1);
9455assign l2b0_dv_1[20] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 10) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[20] ) &&
9456 ~((rd_addr_l2b0_1 == 10) && !rd_en_l2b0_1);
9457assign l2b0_dv_1[21] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 10) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[21] ) &&
9458 ~((rd_addr_l2b0_1 == 10) && !rd_en_l2b0_1);
9459assign l2b0_dv_1[22] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 11) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[22] ) &&
9460 ~((rd_addr_l2b0_1 == 11) && !rd_en_l2b0_1);
9461assign l2b0_dv_1[23] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 11) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[23] ) &&
9462 ~((rd_addr_l2b0_1 == 11) && !rd_en_l2b0_1);
9463assign l2b0_dv_1[24] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 12) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[24] ) &&
9464 ~((rd_addr_l2b0_1 == 12) && !rd_en_l2b0_1);
9465assign l2b0_dv_1[25] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 12) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[25] ) &&
9466 ~((rd_addr_l2b0_1 == 12) && !rd_en_l2b0_1);
9467assign l2b0_dv_1[26] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 13) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[26] ) &&
9468 ~((rd_addr_l2b0_1 == 13) && !rd_en_l2b0_1);
9469assign l2b0_dv_1[27] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 13) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[27] ) &&
9470 ~((rd_addr_l2b0_1 == 13) && !rd_en_l2b0_1);
9471assign l2b0_dv_1[28] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 14) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[28] ) &&
9472 ~((rd_addr_l2b0_1 == 14) && !rd_en_l2b0_1);
9473assign l2b0_dv_1[29] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 14) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[29] ) &&
9474 ~((rd_addr_l2b0_1 == 14) && !rd_en_l2b0_1);
9475assign l2b0_dv_1[30] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 15) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[30] ) &&
9476 ~((rd_addr_l2b0_1 == 15) && !rd_en_l2b0_1);
9477assign l2b0_dv_1[31] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 15) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[31] ) &&
9478 ~((rd_addr_l2b0_1 == 15) && !rd_en_l2b0_1);
9479assign l2b0_dv_1[32] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 16) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[32] ) &&
9480 ~((rd_addr_l2b0_1 == 16) && !rd_en_l2b0_1);
9481assign l2b0_dv_1[33] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 16) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[33] ) &&
9482 ~((rd_addr_l2b0_1 == 16) && !rd_en_l2b0_1);
9483assign l2b0_dv_1[34] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 17) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[34] ) &&
9484 ~((rd_addr_l2b0_1 == 17) && !rd_en_l2b0_1);
9485assign l2b0_dv_1[35] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 17) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[35] ) &&
9486 ~((rd_addr_l2b0_1 == 17) && !rd_en_l2b0_1);
9487assign l2b0_dv_1[36] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 18) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[36] ) &&
9488 ~((rd_addr_l2b0_1 == 18) && !rd_en_l2b0_1);
9489assign l2b0_dv_1[37] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 18) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[37] ) &&
9490 ~((rd_addr_l2b0_1 == 18) && !rd_en_l2b0_1);
9491assign l2b0_dv_1[38] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 19) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[38] ) &&
9492 ~((rd_addr_l2b0_1 == 19) && !rd_en_l2b0_1);
9493assign l2b0_dv_1[39] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 19) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[39] ) &&
9494 ~((rd_addr_l2b0_1 == 19) && !rd_en_l2b0_1);
9495assign l2b0_dv_1[40] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 20) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[40] ) &&
9496 ~((rd_addr_l2b0_1 == 20) && !rd_en_l2b0_1);
9497assign l2b0_dv_1[41] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 20) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[41] ) &&
9498 ~((rd_addr_l2b0_1 == 20) && !rd_en_l2b0_1);
9499assign l2b0_dv_1[42] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 21) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[42] ) &&
9500 ~((rd_addr_l2b0_1 == 21) && !rd_en_l2b0_1);
9501assign l2b0_dv_1[43] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 21) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[43] ) &&
9502 ~((rd_addr_l2b0_1 == 21) && !rd_en_l2b0_1);
9503assign l2b0_dv_1[44] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 22) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[44] ) &&
9504 ~((rd_addr_l2b0_1 == 22) && !rd_en_l2b0_1);
9505assign l2b0_dv_1[45] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 22) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[45] ) &&
9506 ~((rd_addr_l2b0_1 == 22) && !rd_en_l2b0_1);
9507assign l2b0_dv_1[46] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 23) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[46] ) &&
9508 ~((rd_addr_l2b0_1 == 23) && !rd_en_l2b0_1);
9509assign l2b0_dv_1[47] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 23) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[47] ) &&
9510 ~((rd_addr_l2b0_1 == 23) && !rd_en_l2b0_1);
9511assign l2b0_dv_1[48] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 24) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[48] ) &&
9512 ~((rd_addr_l2b0_1 == 24) && !rd_en_l2b0_1);
9513assign l2b0_dv_1[49] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 24) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[49] ) &&
9514 ~((rd_addr_l2b0_1 == 24) && !rd_en_l2b0_1);
9515assign l2b0_dv_1[50] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 25) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[50] ) &&
9516 ~((rd_addr_l2b0_1 == 25) && !rd_en_l2b0_1);
9517assign l2b0_dv_1[51] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 25) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[51] ) &&
9518 ~((rd_addr_l2b0_1 == 25) && !rd_en_l2b0_1);
9519assign l2b0_dv_1[52] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 26) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[52] ) &&
9520 ~((rd_addr_l2b0_1 == 26) && !rd_en_l2b0_1);
9521assign l2b0_dv_1[53] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 26) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[53] ) &&
9522 ~((rd_addr_l2b0_1 == 26) && !rd_en_l2b0_1);
9523assign l2b0_dv_1[54] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 27) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[54] ) &&
9524 ~((rd_addr_l2b0_1 == 27) && !rd_en_l2b0_1);
9525assign l2b0_dv_1[55] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 27) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[55] ) &&
9526 ~((rd_addr_l2b0_1 == 27) && !rd_en_l2b0_1);
9527assign l2b0_dv_1[56] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 28) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[56] ) &&
9528 ~((rd_addr_l2b0_1 == 28) && !rd_en_l2b0_1);
9529assign l2b0_dv_1[57] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 28) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[57] ) &&
9530 ~((rd_addr_l2b0_1 == 28) && !rd_en_l2b0_1);
9531assign l2b0_dv_1[58] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 29) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[58] ) &&
9532 ~((rd_addr_l2b0_1 == 29) && !rd_en_l2b0_1);
9533assign l2b0_dv_1[59] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 29) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[59] ) &&
9534 ~((rd_addr_l2b0_1 == 29) && !rd_en_l2b0_1);
9535assign l2b0_dv_1[60] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 30) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[60] ) &&
9536 ~((rd_addr_l2b0_1 == 30) && !rd_en_l2b0_1);
9537assign l2b0_dv_1[61] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 30) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[61] ) &&
9538 ~((rd_addr_l2b0_1 == 30) && !rd_en_l2b0_1);
9539assign l2b0_dv_1[62] = ((!wr_en_l2b0_1[0] && (l2b0_wr_addr_1 == 31) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[62] ) &&
9540 ~((rd_addr_l2b0_1 == 31) && !rd_en_l2b0_1);
9541assign l2b0_dv_1[63] = ((!wr_en_l2b0_1[1] && (l2b0_wr_addr_1 == 31) && !dram_Ch1_l2b0_pa_err) || l2b0_dv_1_reg[63] ) &&
9542 ~((rd_addr_l2b0_1 == 31) && !rd_en_l2b0_1);
9543
9544always @(posedge (cmp_clk && enabled)) begin
9545 if (~cmp_rst_l)
9546 begin
9547 l2b0_dv_1_reg <= 64'b0;
9548 end
9549 else begin
9550 l2b0_dv_1_reg <= l2b0_dv_1;
9551 end
9552end
9553
9554// actual monitor
9555// if read and the locations dv not valid
9556// monitoring in cmp_clk and so should be monitored only on the first clock
9557// after which the rd may be valid in the dram clock
9558reg dram_rst_l_l2b0_1_1;
9559reg [5:0] addr_reg_l2b0_1;
9560always @ (posedge (cmp_clk && enabled))
9561begin
9562if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
9563end else begin
9564
9565// need to delay as on 1st dram clk after reset the rd_en has still not
9566dram_rst_l_l2b0_1_1 <= #1 dram_rst_l;
9567addr_reg_l2b0_1 <= #1 {rd_en_l2b0_1, rd_addr_l2b0_1};
9568
9569if (dram_rst_l_l2b0_1_1 && (~rd_en_l2b0_1) &&
9570 (addr_reg_l2b0_1 != {rd_en_l2b0_1, rd_addr_l2b0_1}) &&
9571 (rd_addr_l2b0_1[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
9572/*mb156858 if (!l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 0] || !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 1] ||
9573 !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 2] || !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 3] ||
9574 !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 4] || !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 5] ||
9575 !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 6] || !l2b0_dv_1_reg[rd_addr_l2b0_1*2 + 7]) begin
9576 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
9577 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b0_1, l2b0_dv_1_reg);
9578 finish_test(" CAS Issued Data not valid ", 1);
9579 end */
9580end
9581end
9582end
9583
9584
9585// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
9586
9587always @ (posedge (cmp_clk && enabled))
9588begin
9589if (cmp_rst_l && (~wr_en_l2b0_1[0])) begin
9590 if (l2b0_dv_1_reg[l2b0_wr_addr_1*2 + 0]) begin
9591 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
9592 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_1,wr_en_l2b0_1, l2b0_dv_1_reg);
9593 finish_test(" Data Overwritten in write fifo ", 1);
9594 end
9595end
9596if (cmp_rst_l && (~wr_en_l2b0_1[1])) begin
9597 if (l2b0_dv_1_reg[l2b0_wr_addr_1*2 + 1]) begin
9598 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
9599 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_1,wr_en_l2b0_1, l2b0_dv_1_reg);
9600 finish_test(" Data Overwritten in write fifo ", 1);
9601 end
9602end
9603end
9604
9605
9606wire [63:0] l2b1_dv_1;
9607reg [63:0] l2b1_dv_1_reg;
9608
9609wire [1:0] wr_en_l2b1_1 = ~dram_Ch1_l2b1_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_1 = dram_Ch1_cpu_wr_en;
9610wire [4:0] l2b1_wr_addr_1 = dram_Ch1_l2b1_cpu_wr_addr;
9611wire rd_en_l2b1_1 = ~dram_Ch1_l2b1_wdq_rd_en;
9612wire [4:0] rd_addr_l2b1_1 = dram_Ch1_l2b1_wdq_radr[4:0];
9613
9614// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
9615// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
9616// $p dv index
9617// $q 0 1 2 3
9618// $r addr
9619
9620assign l2b1_dv_1[0] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 0) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[0] ) &&
9621 ~((rd_addr_l2b1_1 == 0) && !rd_en_l2b1_1);
9622assign l2b1_dv_1[1] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 0) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[1] ) &&
9623 ~((rd_addr_l2b1_1 == 0) && !rd_en_l2b1_1);
9624assign l2b1_dv_1[2] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 1) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[2] ) &&
9625 ~((rd_addr_l2b1_1 == 1) && !rd_en_l2b1_1);
9626assign l2b1_dv_1[3] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 1) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[3] ) &&
9627 ~((rd_addr_l2b1_1 == 1) && !rd_en_l2b1_1);
9628assign l2b1_dv_1[4] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 2) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[4] ) &&
9629 ~((rd_addr_l2b1_1 == 2) && !rd_en_l2b1_1);
9630assign l2b1_dv_1[5] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 2) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[5] ) &&
9631 ~((rd_addr_l2b1_1 == 2) && !rd_en_l2b1_1);
9632assign l2b1_dv_1[6] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 3) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[6] ) &&
9633 ~((rd_addr_l2b1_1 == 3) && !rd_en_l2b1_1);
9634assign l2b1_dv_1[7] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 3) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[7] ) &&
9635 ~((rd_addr_l2b1_1 == 3) && !rd_en_l2b1_1);
9636assign l2b1_dv_1[8] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 4) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[8] ) &&
9637 ~((rd_addr_l2b1_1 == 4) && !rd_en_l2b1_1);
9638assign l2b1_dv_1[9] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 4) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[9] ) &&
9639 ~((rd_addr_l2b1_1 == 4) && !rd_en_l2b1_1);
9640assign l2b1_dv_1[10] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 5) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[10] ) &&
9641 ~((rd_addr_l2b1_1 == 5) && !rd_en_l2b1_1);
9642assign l2b1_dv_1[11] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 5) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[11] ) &&
9643 ~((rd_addr_l2b1_1 == 5) && !rd_en_l2b1_1);
9644assign l2b1_dv_1[12] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 6) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[12] ) &&
9645 ~((rd_addr_l2b1_1 == 6) && !rd_en_l2b1_1);
9646assign l2b1_dv_1[13] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 6) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[13] ) &&
9647 ~((rd_addr_l2b1_1 == 6) && !rd_en_l2b1_1);
9648assign l2b1_dv_1[14] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 7) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[14] ) &&
9649 ~((rd_addr_l2b1_1 == 7) && !rd_en_l2b1_1);
9650assign l2b1_dv_1[15] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 7) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[15] ) &&
9651 ~((rd_addr_l2b1_1 == 7) && !rd_en_l2b1_1);
9652assign l2b1_dv_1[16] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 8) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[16] ) &&
9653 ~((rd_addr_l2b1_1 == 8) && !rd_en_l2b1_1);
9654assign l2b1_dv_1[17] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 8) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[17] ) &&
9655 ~((rd_addr_l2b1_1 == 8) && !rd_en_l2b1_1);
9656assign l2b1_dv_1[18] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 9) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[18] ) &&
9657 ~((rd_addr_l2b1_1 == 9) && !rd_en_l2b1_1);
9658assign l2b1_dv_1[19] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 9) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[19] ) &&
9659 ~((rd_addr_l2b1_1 == 9) && !rd_en_l2b1_1);
9660assign l2b1_dv_1[20] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 10) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[20] ) &&
9661 ~((rd_addr_l2b1_1 == 10) && !rd_en_l2b1_1);
9662assign l2b1_dv_1[21] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 10) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[21] ) &&
9663 ~((rd_addr_l2b1_1 == 10) && !rd_en_l2b1_1);
9664assign l2b1_dv_1[22] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 11) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[22] ) &&
9665 ~((rd_addr_l2b1_1 == 11) && !rd_en_l2b1_1);
9666assign l2b1_dv_1[23] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 11) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[23] ) &&
9667 ~((rd_addr_l2b1_1 == 11) && !rd_en_l2b1_1);
9668assign l2b1_dv_1[24] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 12) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[24] ) &&
9669 ~((rd_addr_l2b1_1 == 12) && !rd_en_l2b1_1);
9670assign l2b1_dv_1[25] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 12) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[25] ) &&
9671 ~((rd_addr_l2b1_1 == 12) && !rd_en_l2b1_1);
9672assign l2b1_dv_1[26] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 13) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[26] ) &&
9673 ~((rd_addr_l2b1_1 == 13) && !rd_en_l2b1_1);
9674assign l2b1_dv_1[27] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 13) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[27] ) &&
9675 ~((rd_addr_l2b1_1 == 13) && !rd_en_l2b1_1);
9676assign l2b1_dv_1[28] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 14) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[28] ) &&
9677 ~((rd_addr_l2b1_1 == 14) && !rd_en_l2b1_1);
9678assign l2b1_dv_1[29] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 14) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[29] ) &&
9679 ~((rd_addr_l2b1_1 == 14) && !rd_en_l2b1_1);
9680assign l2b1_dv_1[30] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 15) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[30] ) &&
9681 ~((rd_addr_l2b1_1 == 15) && !rd_en_l2b1_1);
9682assign l2b1_dv_1[31] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 15) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[31] ) &&
9683 ~((rd_addr_l2b1_1 == 15) && !rd_en_l2b1_1);
9684assign l2b1_dv_1[32] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 16) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[32] ) &&
9685 ~((rd_addr_l2b1_1 == 16) && !rd_en_l2b1_1);
9686assign l2b1_dv_1[33] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 16) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[33] ) &&
9687 ~((rd_addr_l2b1_1 == 16) && !rd_en_l2b1_1);
9688assign l2b1_dv_1[34] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 17) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[34] ) &&
9689 ~((rd_addr_l2b1_1 == 17) && !rd_en_l2b1_1);
9690assign l2b1_dv_1[35] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 17) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[35] ) &&
9691 ~((rd_addr_l2b1_1 == 17) && !rd_en_l2b1_1);
9692assign l2b1_dv_1[36] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 18) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[36] ) &&
9693 ~((rd_addr_l2b1_1 == 18) && !rd_en_l2b1_1);
9694assign l2b1_dv_1[37] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 18) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[37] ) &&
9695 ~((rd_addr_l2b1_1 == 18) && !rd_en_l2b1_1);
9696assign l2b1_dv_1[38] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 19) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[38] ) &&
9697 ~((rd_addr_l2b1_1 == 19) && !rd_en_l2b1_1);
9698assign l2b1_dv_1[39] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 19) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[39] ) &&
9699 ~((rd_addr_l2b1_1 == 19) && !rd_en_l2b1_1);
9700assign l2b1_dv_1[40] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 20) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[40] ) &&
9701 ~((rd_addr_l2b1_1 == 20) && !rd_en_l2b1_1);
9702assign l2b1_dv_1[41] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 20) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[41] ) &&
9703 ~((rd_addr_l2b1_1 == 20) && !rd_en_l2b1_1);
9704assign l2b1_dv_1[42] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 21) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[42] ) &&
9705 ~((rd_addr_l2b1_1 == 21) && !rd_en_l2b1_1);
9706assign l2b1_dv_1[43] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 21) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[43] ) &&
9707 ~((rd_addr_l2b1_1 == 21) && !rd_en_l2b1_1);
9708assign l2b1_dv_1[44] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 22) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[44] ) &&
9709 ~((rd_addr_l2b1_1 == 22) && !rd_en_l2b1_1);
9710assign l2b1_dv_1[45] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 22) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[45] ) &&
9711 ~((rd_addr_l2b1_1 == 22) && !rd_en_l2b1_1);
9712assign l2b1_dv_1[46] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 23) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[46] ) &&
9713 ~((rd_addr_l2b1_1 == 23) && !rd_en_l2b1_1);
9714assign l2b1_dv_1[47] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 23) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[47] ) &&
9715 ~((rd_addr_l2b1_1 == 23) && !rd_en_l2b1_1);
9716assign l2b1_dv_1[48] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 24) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[48] ) &&
9717 ~((rd_addr_l2b1_1 == 24) && !rd_en_l2b1_1);
9718assign l2b1_dv_1[49] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 24) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[49] ) &&
9719 ~((rd_addr_l2b1_1 == 24) && !rd_en_l2b1_1);
9720assign l2b1_dv_1[50] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 25) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[50] ) &&
9721 ~((rd_addr_l2b1_1 == 25) && !rd_en_l2b1_1);
9722assign l2b1_dv_1[51] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 25) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[51] ) &&
9723 ~((rd_addr_l2b1_1 == 25) && !rd_en_l2b1_1);
9724assign l2b1_dv_1[52] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 26) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[52] ) &&
9725 ~((rd_addr_l2b1_1 == 26) && !rd_en_l2b1_1);
9726assign l2b1_dv_1[53] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 26) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[53] ) &&
9727 ~((rd_addr_l2b1_1 == 26) && !rd_en_l2b1_1);
9728assign l2b1_dv_1[54] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 27) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[54] ) &&
9729 ~((rd_addr_l2b1_1 == 27) && !rd_en_l2b1_1);
9730assign l2b1_dv_1[55] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 27) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[55] ) &&
9731 ~((rd_addr_l2b1_1 == 27) && !rd_en_l2b1_1);
9732assign l2b1_dv_1[56] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 28) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[56] ) &&
9733 ~((rd_addr_l2b1_1 == 28) && !rd_en_l2b1_1);
9734assign l2b1_dv_1[57] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 28) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[57] ) &&
9735 ~((rd_addr_l2b1_1 == 28) && !rd_en_l2b1_1);
9736assign l2b1_dv_1[58] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 29) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[58] ) &&
9737 ~((rd_addr_l2b1_1 == 29) && !rd_en_l2b1_1);
9738assign l2b1_dv_1[59] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 29) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[59] ) &&
9739 ~((rd_addr_l2b1_1 == 29) && !rd_en_l2b1_1);
9740assign l2b1_dv_1[60] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 30) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[60] ) &&
9741 ~((rd_addr_l2b1_1 == 30) && !rd_en_l2b1_1);
9742assign l2b1_dv_1[61] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 30) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[61] ) &&
9743 ~((rd_addr_l2b1_1 == 30) && !rd_en_l2b1_1);
9744assign l2b1_dv_1[62] = ((!wr_en_l2b1_1[0] && (l2b1_wr_addr_1 == 31) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[62] ) &&
9745 ~((rd_addr_l2b1_1 == 31) && !rd_en_l2b1_1);
9746assign l2b1_dv_1[63] = ((!wr_en_l2b1_1[1] && (l2b1_wr_addr_1 == 31) && !dram_Ch1_l2b1_pa_err) || l2b1_dv_1_reg[63] ) &&
9747 ~((rd_addr_l2b1_1 == 31) && !rd_en_l2b1_1);
9748
9749always @(posedge (cmp_clk && enabled)) begin
9750 if (~cmp_rst_l)
9751 begin
9752 l2b1_dv_1_reg <= 64'b0;
9753 end
9754 else begin
9755 l2b1_dv_1_reg <= l2b1_dv_1;
9756 end
9757end
9758
9759// actual monitor
9760// if read and the locations dv not valid
9761// monitoring in cmp_clk and so should be monitored only on the first clock
9762// after which the rd may be valid in the dram clock
9763reg dram_rst_l_l2b1_1_1;
9764reg [5:0] addr_reg_l2b1_1;
9765always @ (posedge (cmp_clk && enabled))
9766begin
9767if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
9768end else begin
9769
9770// need to delay as on 1st dram clk after reset the rd_en has still not
9771dram_rst_l_l2b1_1_1 <= #1 dram_rst_l;
9772addr_reg_l2b1_1 <= #1 {rd_en_l2b1_1, rd_addr_l2b1_1};
9773
9774if (dram_rst_l_l2b1_1_1 && (~rd_en_l2b1_1) &&
9775 (addr_reg_l2b1_1 != {rd_en_l2b1_1, rd_addr_l2b1_1}) &&
9776 (rd_addr_l2b1_1[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
9777/*mb156858 if (!l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 0] || !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 1] ||
9778 !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 2] || !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 3] ||
9779 !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 4] || !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 5] ||
9780 !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 6] || !l2b1_dv_1_reg[rd_addr_l2b1_1*2 + 7]) begin
9781 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
9782 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b1_1, l2b1_dv_1_reg);
9783 finish_test(" CAS Issued Data not valid ", 1);
9784 end */
9785end
9786end
9787end
9788
9789
9790// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
9791
9792always @ (posedge (cmp_clk && enabled))
9793begin
9794if (cmp_rst_l && (~wr_en_l2b1_1[0])) begin
9795 if (l2b1_dv_1_reg[l2b1_wr_addr_1*2 + 0]) begin
9796 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
9797 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_1,wr_en_l2b1_1, l2b1_dv_1_reg);
9798 finish_test(" Data Overwritten in write fifo ", 1);
9799 end
9800end
9801if (cmp_rst_l && (~wr_en_l2b1_1[1])) begin
9802 if (l2b1_dv_1_reg[l2b1_wr_addr_1*2 + 1]) begin
9803 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
9804 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_1,wr_en_l2b1_1, l2b1_dv_1_reg);
9805 finish_test(" Data Overwritten in write fifo ", 1);
9806 end
9807end
9808end
9809
9810
9811wire [63:0] l2b0_dv_2;
9812reg [63:0] l2b0_dv_2_reg;
9813
9814wire [1:0] wr_en_l2b0_2 = ~dram_Ch2_l2b0_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_2 = dram_Ch2_cpu_wr_en;
9815wire [4:0] l2b0_wr_addr_2 = dram_Ch2_l2b0_cpu_wr_addr;
9816wire rd_en_l2b0_2 = ~dram_Ch2_l2b0_wdq_rd_en;
9817wire [4:0] rd_addr_l2b0_2 = dram_Ch2_l2b0_wdq_radr[4:0];
9818
9819// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
9820// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
9821// $p dv index
9822// $q 0 1 2 3
9823// $r addr
9824
9825assign l2b0_dv_2[0] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 0) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[0] ) &&
9826 ~((rd_addr_l2b0_2 == 0) && !rd_en_l2b0_2);
9827assign l2b0_dv_2[1] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 0) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[1] ) &&
9828 ~((rd_addr_l2b0_2 == 0) && !rd_en_l2b0_2);
9829assign l2b0_dv_2[2] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 1) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[2] ) &&
9830 ~((rd_addr_l2b0_2 == 1) && !rd_en_l2b0_2);
9831assign l2b0_dv_2[3] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 1) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[3] ) &&
9832 ~((rd_addr_l2b0_2 == 1) && !rd_en_l2b0_2);
9833assign l2b0_dv_2[4] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 2) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[4] ) &&
9834 ~((rd_addr_l2b0_2 == 2) && !rd_en_l2b0_2);
9835assign l2b0_dv_2[5] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 2) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[5] ) &&
9836 ~((rd_addr_l2b0_2 == 2) && !rd_en_l2b0_2);
9837assign l2b0_dv_2[6] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 3) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[6] ) &&
9838 ~((rd_addr_l2b0_2 == 3) && !rd_en_l2b0_2);
9839assign l2b0_dv_2[7] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 3) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[7] ) &&
9840 ~((rd_addr_l2b0_2 == 3) && !rd_en_l2b0_2);
9841assign l2b0_dv_2[8] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 4) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[8] ) &&
9842 ~((rd_addr_l2b0_2 == 4) && !rd_en_l2b0_2);
9843assign l2b0_dv_2[9] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 4) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[9] ) &&
9844 ~((rd_addr_l2b0_2 == 4) && !rd_en_l2b0_2);
9845assign l2b0_dv_2[10] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 5) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[10] ) &&
9846 ~((rd_addr_l2b0_2 == 5) && !rd_en_l2b0_2);
9847assign l2b0_dv_2[11] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 5) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[11] ) &&
9848 ~((rd_addr_l2b0_2 == 5) && !rd_en_l2b0_2);
9849assign l2b0_dv_2[12] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 6) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[12] ) &&
9850 ~((rd_addr_l2b0_2 == 6) && !rd_en_l2b0_2);
9851assign l2b0_dv_2[13] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 6) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[13] ) &&
9852 ~((rd_addr_l2b0_2 == 6) && !rd_en_l2b0_2);
9853assign l2b0_dv_2[14] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 7) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[14] ) &&
9854 ~((rd_addr_l2b0_2 == 7) && !rd_en_l2b0_2);
9855assign l2b0_dv_2[15] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 7) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[15] ) &&
9856 ~((rd_addr_l2b0_2 == 7) && !rd_en_l2b0_2);
9857assign l2b0_dv_2[16] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 8) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[16] ) &&
9858 ~((rd_addr_l2b0_2 == 8) && !rd_en_l2b0_2);
9859assign l2b0_dv_2[17] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 8) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[17] ) &&
9860 ~((rd_addr_l2b0_2 == 8) && !rd_en_l2b0_2);
9861assign l2b0_dv_2[18] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 9) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[18] ) &&
9862 ~((rd_addr_l2b0_2 == 9) && !rd_en_l2b0_2);
9863assign l2b0_dv_2[19] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 9) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[19] ) &&
9864 ~((rd_addr_l2b0_2 == 9) && !rd_en_l2b0_2);
9865assign l2b0_dv_2[20] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 10) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[20] ) &&
9866 ~((rd_addr_l2b0_2 == 10) && !rd_en_l2b0_2);
9867assign l2b0_dv_2[21] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 10) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[21] ) &&
9868 ~((rd_addr_l2b0_2 == 10) && !rd_en_l2b0_2);
9869assign l2b0_dv_2[22] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 11) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[22] ) &&
9870 ~((rd_addr_l2b0_2 == 11) && !rd_en_l2b0_2);
9871assign l2b0_dv_2[23] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 11) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[23] ) &&
9872 ~((rd_addr_l2b0_2 == 11) && !rd_en_l2b0_2);
9873assign l2b0_dv_2[24] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 12) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[24] ) &&
9874 ~((rd_addr_l2b0_2 == 12) && !rd_en_l2b0_2);
9875assign l2b0_dv_2[25] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 12) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[25] ) &&
9876 ~((rd_addr_l2b0_2 == 12) && !rd_en_l2b0_2);
9877assign l2b0_dv_2[26] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 13) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[26] ) &&
9878 ~((rd_addr_l2b0_2 == 13) && !rd_en_l2b0_2);
9879assign l2b0_dv_2[27] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 13) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[27] ) &&
9880 ~((rd_addr_l2b0_2 == 13) && !rd_en_l2b0_2);
9881assign l2b0_dv_2[28] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 14) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[28] ) &&
9882 ~((rd_addr_l2b0_2 == 14) && !rd_en_l2b0_2);
9883assign l2b0_dv_2[29] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 14) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[29] ) &&
9884 ~((rd_addr_l2b0_2 == 14) && !rd_en_l2b0_2);
9885assign l2b0_dv_2[30] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 15) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[30] ) &&
9886 ~((rd_addr_l2b0_2 == 15) && !rd_en_l2b0_2);
9887assign l2b0_dv_2[31] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 15) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[31] ) &&
9888 ~((rd_addr_l2b0_2 == 15) && !rd_en_l2b0_2);
9889assign l2b0_dv_2[32] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 16) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[32] ) &&
9890 ~((rd_addr_l2b0_2 == 16) && !rd_en_l2b0_2);
9891assign l2b0_dv_2[33] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 16) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[33] ) &&
9892 ~((rd_addr_l2b0_2 == 16) && !rd_en_l2b0_2);
9893assign l2b0_dv_2[34] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 17) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[34] ) &&
9894 ~((rd_addr_l2b0_2 == 17) && !rd_en_l2b0_2);
9895assign l2b0_dv_2[35] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 17) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[35] ) &&
9896 ~((rd_addr_l2b0_2 == 17) && !rd_en_l2b0_2);
9897assign l2b0_dv_2[36] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 18) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[36] ) &&
9898 ~((rd_addr_l2b0_2 == 18) && !rd_en_l2b0_2);
9899assign l2b0_dv_2[37] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 18) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[37] ) &&
9900 ~((rd_addr_l2b0_2 == 18) && !rd_en_l2b0_2);
9901assign l2b0_dv_2[38] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 19) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[38] ) &&
9902 ~((rd_addr_l2b0_2 == 19) && !rd_en_l2b0_2);
9903assign l2b0_dv_2[39] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 19) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[39] ) &&
9904 ~((rd_addr_l2b0_2 == 19) && !rd_en_l2b0_2);
9905assign l2b0_dv_2[40] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 20) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[40] ) &&
9906 ~((rd_addr_l2b0_2 == 20) && !rd_en_l2b0_2);
9907assign l2b0_dv_2[41] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 20) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[41] ) &&
9908 ~((rd_addr_l2b0_2 == 20) && !rd_en_l2b0_2);
9909assign l2b0_dv_2[42] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 21) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[42] ) &&
9910 ~((rd_addr_l2b0_2 == 21) && !rd_en_l2b0_2);
9911assign l2b0_dv_2[43] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 21) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[43] ) &&
9912 ~((rd_addr_l2b0_2 == 21) && !rd_en_l2b0_2);
9913assign l2b0_dv_2[44] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 22) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[44] ) &&
9914 ~((rd_addr_l2b0_2 == 22) && !rd_en_l2b0_2);
9915assign l2b0_dv_2[45] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 22) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[45] ) &&
9916 ~((rd_addr_l2b0_2 == 22) && !rd_en_l2b0_2);
9917assign l2b0_dv_2[46] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 23) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[46] ) &&
9918 ~((rd_addr_l2b0_2 == 23) && !rd_en_l2b0_2);
9919assign l2b0_dv_2[47] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 23) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[47] ) &&
9920 ~((rd_addr_l2b0_2 == 23) && !rd_en_l2b0_2);
9921assign l2b0_dv_2[48] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 24) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[48] ) &&
9922 ~((rd_addr_l2b0_2 == 24) && !rd_en_l2b0_2);
9923assign l2b0_dv_2[49] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 24) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[49] ) &&
9924 ~((rd_addr_l2b0_2 == 24) && !rd_en_l2b0_2);
9925assign l2b0_dv_2[50] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 25) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[50] ) &&
9926 ~((rd_addr_l2b0_2 == 25) && !rd_en_l2b0_2);
9927assign l2b0_dv_2[51] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 25) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[51] ) &&
9928 ~((rd_addr_l2b0_2 == 25) && !rd_en_l2b0_2);
9929assign l2b0_dv_2[52] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 26) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[52] ) &&
9930 ~((rd_addr_l2b0_2 == 26) && !rd_en_l2b0_2);
9931assign l2b0_dv_2[53] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 26) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[53] ) &&
9932 ~((rd_addr_l2b0_2 == 26) && !rd_en_l2b0_2);
9933assign l2b0_dv_2[54] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 27) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[54] ) &&
9934 ~((rd_addr_l2b0_2 == 27) && !rd_en_l2b0_2);
9935assign l2b0_dv_2[55] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 27) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[55] ) &&
9936 ~((rd_addr_l2b0_2 == 27) && !rd_en_l2b0_2);
9937assign l2b0_dv_2[56] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 28) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[56] ) &&
9938 ~((rd_addr_l2b0_2 == 28) && !rd_en_l2b0_2);
9939assign l2b0_dv_2[57] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 28) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[57] ) &&
9940 ~((rd_addr_l2b0_2 == 28) && !rd_en_l2b0_2);
9941assign l2b0_dv_2[58] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 29) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[58] ) &&
9942 ~((rd_addr_l2b0_2 == 29) && !rd_en_l2b0_2);
9943assign l2b0_dv_2[59] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 29) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[59] ) &&
9944 ~((rd_addr_l2b0_2 == 29) && !rd_en_l2b0_2);
9945assign l2b0_dv_2[60] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 30) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[60] ) &&
9946 ~((rd_addr_l2b0_2 == 30) && !rd_en_l2b0_2);
9947assign l2b0_dv_2[61] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 30) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[61] ) &&
9948 ~((rd_addr_l2b0_2 == 30) && !rd_en_l2b0_2);
9949assign l2b0_dv_2[62] = ((!wr_en_l2b0_2[0] && (l2b0_wr_addr_2 == 31) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[62] ) &&
9950 ~((rd_addr_l2b0_2 == 31) && !rd_en_l2b0_2);
9951assign l2b0_dv_2[63] = ((!wr_en_l2b0_2[1] && (l2b0_wr_addr_2 == 31) && !dram_Ch2_l2b0_pa_err) || l2b0_dv_2_reg[63] ) &&
9952 ~((rd_addr_l2b0_2 == 31) && !rd_en_l2b0_2);
9953
9954always @(posedge (cmp_clk && enabled)) begin
9955 if (~cmp_rst_l)
9956 begin
9957 l2b0_dv_2_reg <= 64'b0;
9958 end
9959 else begin
9960 l2b0_dv_2_reg <= l2b0_dv_2;
9961 end
9962end
9963
9964// actual monitor
9965// if read and the locations dv not valid
9966// monitoring in cmp_clk and so should be monitored only on the first clock
9967// after which the rd may be valid in the dram clock
9968reg dram_rst_l_l2b0_2_1;
9969reg [5:0] addr_reg_l2b0_2;
9970always @ (posedge (cmp_clk && enabled))
9971begin
9972if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
9973end else begin
9974
9975// need to delay as on 1st dram clk after reset the rd_en has still not
9976dram_rst_l_l2b0_2_1 <= #1 dram_rst_l;
9977addr_reg_l2b0_2 <= #1 {rd_en_l2b0_2, rd_addr_l2b0_2};
9978
9979if (dram_rst_l_l2b0_2_1 && (~rd_en_l2b0_2) &&
9980 (addr_reg_l2b0_2 != {rd_en_l2b0_2, rd_addr_l2b0_2}) &&
9981 (rd_addr_l2b0_2[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
9982/*mb156858 if (!l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 0] || !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 1] ||
9983 !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 2] || !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 3] ||
9984 !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 4] || !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 5] ||
9985 !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 6] || !l2b0_dv_2_reg[rd_addr_l2b0_2*2 + 7]) begin
9986 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
9987 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b0_2, l2b0_dv_2_reg);
9988 finish_test(" CAS Issued Data not valid ", 2);
9989 end */
9990end
9991end
9992end
9993
9994
9995// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
9996
9997always @ (posedge (cmp_clk && enabled))
9998begin
9999if (cmp_rst_l && (~wr_en_l2b0_2[0])) begin
10000 if (l2b0_dv_2_reg[l2b0_wr_addr_2*2 + 0]) begin
10001 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
10002 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_2,wr_en_l2b0_2, l2b0_dv_2_reg);
10003 finish_test(" Data Overwritten in write fifo ", 2);
10004 end
10005end
10006if (cmp_rst_l && (~wr_en_l2b0_2[1])) begin
10007 if (l2b0_dv_2_reg[l2b0_wr_addr_2*2 + 1]) begin
10008 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
10009 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_2,wr_en_l2b0_2, l2b0_dv_2_reg);
10010 finish_test(" Data Overwritten in write fifo ", 2);
10011 end
10012end
10013end
10014
10015
10016wire [63:0] l2b1_dv_2;
10017reg [63:0] l2b1_dv_2_reg;
10018
10019wire [1:0] wr_en_l2b1_2 = ~dram_Ch2_l2b1_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_2 = dram_Ch2_cpu_wr_en;
10020wire [4:0] l2b1_wr_addr_2 = dram_Ch2_l2b1_cpu_wr_addr;
10021wire rd_en_l2b1_2 = ~dram_Ch2_l2b1_wdq_rd_en;
10022wire [4:0] rd_addr_l2b1_2 = dram_Ch2_l2b1_wdq_radr[4:0];
10023
10024// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
10025// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
10026// $p dv index
10027// $q 0 1 2 3
10028// $r addr
10029
10030assign l2b1_dv_2[0] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 0) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[0] ) &&
10031 ~((rd_addr_l2b1_2 == 0) && !rd_en_l2b1_2);
10032assign l2b1_dv_2[1] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 0) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[1] ) &&
10033 ~((rd_addr_l2b1_2 == 0) && !rd_en_l2b1_2);
10034assign l2b1_dv_2[2] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 1) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[2] ) &&
10035 ~((rd_addr_l2b1_2 == 1) && !rd_en_l2b1_2);
10036assign l2b1_dv_2[3] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 1) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[3] ) &&
10037 ~((rd_addr_l2b1_2 == 1) && !rd_en_l2b1_2);
10038assign l2b1_dv_2[4] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 2) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[4] ) &&
10039 ~((rd_addr_l2b1_2 == 2) && !rd_en_l2b1_2);
10040assign l2b1_dv_2[5] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 2) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[5] ) &&
10041 ~((rd_addr_l2b1_2 == 2) && !rd_en_l2b1_2);
10042assign l2b1_dv_2[6] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 3) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[6] ) &&
10043 ~((rd_addr_l2b1_2 == 3) && !rd_en_l2b1_2);
10044assign l2b1_dv_2[7] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 3) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[7] ) &&
10045 ~((rd_addr_l2b1_2 == 3) && !rd_en_l2b1_2);
10046assign l2b1_dv_2[8] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 4) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[8] ) &&
10047 ~((rd_addr_l2b1_2 == 4) && !rd_en_l2b1_2);
10048assign l2b1_dv_2[9] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 4) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[9] ) &&
10049 ~((rd_addr_l2b1_2 == 4) && !rd_en_l2b1_2);
10050assign l2b1_dv_2[10] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 5) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[10] ) &&
10051 ~((rd_addr_l2b1_2 == 5) && !rd_en_l2b1_2);
10052assign l2b1_dv_2[11] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 5) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[11] ) &&
10053 ~((rd_addr_l2b1_2 == 5) && !rd_en_l2b1_2);
10054assign l2b1_dv_2[12] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 6) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[12] ) &&
10055 ~((rd_addr_l2b1_2 == 6) && !rd_en_l2b1_2);
10056assign l2b1_dv_2[13] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 6) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[13] ) &&
10057 ~((rd_addr_l2b1_2 == 6) && !rd_en_l2b1_2);
10058assign l2b1_dv_2[14] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 7) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[14] ) &&
10059 ~((rd_addr_l2b1_2 == 7) && !rd_en_l2b1_2);
10060assign l2b1_dv_2[15] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 7) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[15] ) &&
10061 ~((rd_addr_l2b1_2 == 7) && !rd_en_l2b1_2);
10062assign l2b1_dv_2[16] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 8) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[16] ) &&
10063 ~((rd_addr_l2b1_2 == 8) && !rd_en_l2b1_2);
10064assign l2b1_dv_2[17] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 8) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[17] ) &&
10065 ~((rd_addr_l2b1_2 == 8) && !rd_en_l2b1_2);
10066assign l2b1_dv_2[18] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 9) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[18] ) &&
10067 ~((rd_addr_l2b1_2 == 9) && !rd_en_l2b1_2);
10068assign l2b1_dv_2[19] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 9) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[19] ) &&
10069 ~((rd_addr_l2b1_2 == 9) && !rd_en_l2b1_2);
10070assign l2b1_dv_2[20] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 10) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[20] ) &&
10071 ~((rd_addr_l2b1_2 == 10) && !rd_en_l2b1_2);
10072assign l2b1_dv_2[21] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 10) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[21] ) &&
10073 ~((rd_addr_l2b1_2 == 10) && !rd_en_l2b1_2);
10074assign l2b1_dv_2[22] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 11) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[22] ) &&
10075 ~((rd_addr_l2b1_2 == 11) && !rd_en_l2b1_2);
10076assign l2b1_dv_2[23] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 11) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[23] ) &&
10077 ~((rd_addr_l2b1_2 == 11) && !rd_en_l2b1_2);
10078assign l2b1_dv_2[24] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 12) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[24] ) &&
10079 ~((rd_addr_l2b1_2 == 12) && !rd_en_l2b1_2);
10080assign l2b1_dv_2[25] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 12) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[25] ) &&
10081 ~((rd_addr_l2b1_2 == 12) && !rd_en_l2b1_2);
10082assign l2b1_dv_2[26] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 13) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[26] ) &&
10083 ~((rd_addr_l2b1_2 == 13) && !rd_en_l2b1_2);
10084assign l2b1_dv_2[27] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 13) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[27] ) &&
10085 ~((rd_addr_l2b1_2 == 13) && !rd_en_l2b1_2);
10086assign l2b1_dv_2[28] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 14) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[28] ) &&
10087 ~((rd_addr_l2b1_2 == 14) && !rd_en_l2b1_2);
10088assign l2b1_dv_2[29] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 14) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[29] ) &&
10089 ~((rd_addr_l2b1_2 == 14) && !rd_en_l2b1_2);
10090assign l2b1_dv_2[30] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 15) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[30] ) &&
10091 ~((rd_addr_l2b1_2 == 15) && !rd_en_l2b1_2);
10092assign l2b1_dv_2[31] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 15) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[31] ) &&
10093 ~((rd_addr_l2b1_2 == 15) && !rd_en_l2b1_2);
10094assign l2b1_dv_2[32] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 16) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[32] ) &&
10095 ~((rd_addr_l2b1_2 == 16) && !rd_en_l2b1_2);
10096assign l2b1_dv_2[33] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 16) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[33] ) &&
10097 ~((rd_addr_l2b1_2 == 16) && !rd_en_l2b1_2);
10098assign l2b1_dv_2[34] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 17) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[34] ) &&
10099 ~((rd_addr_l2b1_2 == 17) && !rd_en_l2b1_2);
10100assign l2b1_dv_2[35] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 17) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[35] ) &&
10101 ~((rd_addr_l2b1_2 == 17) && !rd_en_l2b1_2);
10102assign l2b1_dv_2[36] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 18) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[36] ) &&
10103 ~((rd_addr_l2b1_2 == 18) && !rd_en_l2b1_2);
10104assign l2b1_dv_2[37] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 18) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[37] ) &&
10105 ~((rd_addr_l2b1_2 == 18) && !rd_en_l2b1_2);
10106assign l2b1_dv_2[38] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 19) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[38] ) &&
10107 ~((rd_addr_l2b1_2 == 19) && !rd_en_l2b1_2);
10108assign l2b1_dv_2[39] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 19) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[39] ) &&
10109 ~((rd_addr_l2b1_2 == 19) && !rd_en_l2b1_2);
10110assign l2b1_dv_2[40] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 20) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[40] ) &&
10111 ~((rd_addr_l2b1_2 == 20) && !rd_en_l2b1_2);
10112assign l2b1_dv_2[41] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 20) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[41] ) &&
10113 ~((rd_addr_l2b1_2 == 20) && !rd_en_l2b1_2);
10114assign l2b1_dv_2[42] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 21) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[42] ) &&
10115 ~((rd_addr_l2b1_2 == 21) && !rd_en_l2b1_2);
10116assign l2b1_dv_2[43] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 21) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[43] ) &&
10117 ~((rd_addr_l2b1_2 == 21) && !rd_en_l2b1_2);
10118assign l2b1_dv_2[44] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 22) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[44] ) &&
10119 ~((rd_addr_l2b1_2 == 22) && !rd_en_l2b1_2);
10120assign l2b1_dv_2[45] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 22) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[45] ) &&
10121 ~((rd_addr_l2b1_2 == 22) && !rd_en_l2b1_2);
10122assign l2b1_dv_2[46] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 23) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[46] ) &&
10123 ~((rd_addr_l2b1_2 == 23) && !rd_en_l2b1_2);
10124assign l2b1_dv_2[47] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 23) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[47] ) &&
10125 ~((rd_addr_l2b1_2 == 23) && !rd_en_l2b1_2);
10126assign l2b1_dv_2[48] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 24) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[48] ) &&
10127 ~((rd_addr_l2b1_2 == 24) && !rd_en_l2b1_2);
10128assign l2b1_dv_2[49] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 24) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[49] ) &&
10129 ~((rd_addr_l2b1_2 == 24) && !rd_en_l2b1_2);
10130assign l2b1_dv_2[50] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 25) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[50] ) &&
10131 ~((rd_addr_l2b1_2 == 25) && !rd_en_l2b1_2);
10132assign l2b1_dv_2[51] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 25) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[51] ) &&
10133 ~((rd_addr_l2b1_2 == 25) && !rd_en_l2b1_2);
10134assign l2b1_dv_2[52] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 26) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[52] ) &&
10135 ~((rd_addr_l2b1_2 == 26) && !rd_en_l2b1_2);
10136assign l2b1_dv_2[53] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 26) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[53] ) &&
10137 ~((rd_addr_l2b1_2 == 26) && !rd_en_l2b1_2);
10138assign l2b1_dv_2[54] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 27) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[54] ) &&
10139 ~((rd_addr_l2b1_2 == 27) && !rd_en_l2b1_2);
10140assign l2b1_dv_2[55] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 27) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[55] ) &&
10141 ~((rd_addr_l2b1_2 == 27) && !rd_en_l2b1_2);
10142assign l2b1_dv_2[56] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 28) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[56] ) &&
10143 ~((rd_addr_l2b1_2 == 28) && !rd_en_l2b1_2);
10144assign l2b1_dv_2[57] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 28) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[57] ) &&
10145 ~((rd_addr_l2b1_2 == 28) && !rd_en_l2b1_2);
10146assign l2b1_dv_2[58] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 29) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[58] ) &&
10147 ~((rd_addr_l2b1_2 == 29) && !rd_en_l2b1_2);
10148assign l2b1_dv_2[59] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 29) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[59] ) &&
10149 ~((rd_addr_l2b1_2 == 29) && !rd_en_l2b1_2);
10150assign l2b1_dv_2[60] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 30) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[60] ) &&
10151 ~((rd_addr_l2b1_2 == 30) && !rd_en_l2b1_2);
10152assign l2b1_dv_2[61] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 30) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[61] ) &&
10153 ~((rd_addr_l2b1_2 == 30) && !rd_en_l2b1_2);
10154assign l2b1_dv_2[62] = ((!wr_en_l2b1_2[0] && (l2b1_wr_addr_2 == 31) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[62] ) &&
10155 ~((rd_addr_l2b1_2 == 31) && !rd_en_l2b1_2);
10156assign l2b1_dv_2[63] = ((!wr_en_l2b1_2[1] && (l2b1_wr_addr_2 == 31) && !dram_Ch2_l2b1_pa_err) || l2b1_dv_2_reg[63] ) &&
10157 ~((rd_addr_l2b1_2 == 31) && !rd_en_l2b1_2);
10158
10159always @(posedge (cmp_clk && enabled)) begin
10160 if (~cmp_rst_l)
10161 begin
10162 l2b1_dv_2_reg <= 64'b0;
10163 end
10164 else begin
10165 l2b1_dv_2_reg <= l2b1_dv_2;
10166 end
10167end
10168
10169// actual monitor
10170// if read and the locations dv not valid
10171// monitoring in cmp_clk and so should be monitored only on the first clock
10172// after which the rd may be valid in the dram clock
10173reg dram_rst_l_l2b1_2_1;
10174reg [5:0] addr_reg_l2b1_2;
10175always @ (posedge (cmp_clk && enabled))
10176begin
10177if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
10178end else begin
10179
10180// need to delay as on 1st dram clk after reset the rd_en has still not
10181dram_rst_l_l2b1_2_1 <= #1 dram_rst_l;
10182addr_reg_l2b1_2 <= #1 {rd_en_l2b1_2, rd_addr_l2b1_2};
10183
10184if (dram_rst_l_l2b1_2_1 && (~rd_en_l2b1_2) &&
10185 (addr_reg_l2b1_2 != {rd_en_l2b1_2, rd_addr_l2b1_2}) &&
10186 (rd_addr_l2b1_2[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
10187/*mb156858 if (!l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 0] || !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 1] ||
10188 !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 2] || !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 3] ||
10189 !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 4] || !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 5] ||
10190 !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 6] || !l2b1_dv_2_reg[rd_addr_l2b1_2*2 + 7]) begin
10191 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
10192 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b1_2, l2b1_dv_2_reg);
10193 finish_test(" CAS Issued Data not valid ", 2);
10194 end */
10195end
10196end
10197end
10198
10199
10200// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
10201
10202always @ (posedge (cmp_clk && enabled))
10203begin
10204if (cmp_rst_l && (~wr_en_l2b1_2[0])) begin
10205 if (l2b1_dv_2_reg[l2b1_wr_addr_2*2 + 0]) begin
10206 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
10207 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_2,wr_en_l2b1_2, l2b1_dv_2_reg);
10208 finish_test(" Data Overwritten in write fifo ", 2);
10209 end
10210end
10211if (cmp_rst_l && (~wr_en_l2b1_2[1])) begin
10212 if (l2b1_dv_2_reg[l2b1_wr_addr_2*2 + 1]) begin
10213 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
10214 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_2,wr_en_l2b1_2, l2b1_dv_2_reg);
10215 finish_test(" Data Overwritten in write fifo ", 2);
10216 end
10217end
10218end
10219
10220
10221wire [63:0] l2b0_dv_3;
10222reg [63:0] l2b0_dv_3_reg;
10223
10224wire [1:0] wr_en_l2b0_3 = ~dram_Ch3_l2b0_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_3 = dram_Ch3_cpu_wr_en;
10225wire [4:0] l2b0_wr_addr_3 = dram_Ch3_l2b0_cpu_wr_addr;
10226wire rd_en_l2b0_3 = ~dram_Ch3_l2b0_wdq_rd_en;
10227wire [4:0] rd_addr_l2b0_3 = dram_Ch3_l2b0_wdq_radr[4:0];
10228
10229// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
10230// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
10231// $p dv index
10232// $q 0 1 2 3
10233// $r addr
10234
10235assign l2b0_dv_3[0] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 0) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[0] ) &&
10236 ~((rd_addr_l2b0_3 == 0) && !rd_en_l2b0_3);
10237assign l2b0_dv_3[1] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 0) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[1] ) &&
10238 ~((rd_addr_l2b0_3 == 0) && !rd_en_l2b0_3);
10239assign l2b0_dv_3[2] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 1) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[2] ) &&
10240 ~((rd_addr_l2b0_3 == 1) && !rd_en_l2b0_3);
10241assign l2b0_dv_3[3] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 1) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[3] ) &&
10242 ~((rd_addr_l2b0_3 == 1) && !rd_en_l2b0_3);
10243assign l2b0_dv_3[4] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 2) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[4] ) &&
10244 ~((rd_addr_l2b0_3 == 2) && !rd_en_l2b0_3);
10245assign l2b0_dv_3[5] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 2) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[5] ) &&
10246 ~((rd_addr_l2b0_3 == 2) && !rd_en_l2b0_3);
10247assign l2b0_dv_3[6] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 3) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[6] ) &&
10248 ~((rd_addr_l2b0_3 == 3) && !rd_en_l2b0_3);
10249assign l2b0_dv_3[7] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 3) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[7] ) &&
10250 ~((rd_addr_l2b0_3 == 3) && !rd_en_l2b0_3);
10251assign l2b0_dv_3[8] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 4) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[8] ) &&
10252 ~((rd_addr_l2b0_3 == 4) && !rd_en_l2b0_3);
10253assign l2b0_dv_3[9] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 4) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[9] ) &&
10254 ~((rd_addr_l2b0_3 == 4) && !rd_en_l2b0_3);
10255assign l2b0_dv_3[10] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 5) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[10] ) &&
10256 ~((rd_addr_l2b0_3 == 5) && !rd_en_l2b0_3);
10257assign l2b0_dv_3[11] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 5) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[11] ) &&
10258 ~((rd_addr_l2b0_3 == 5) && !rd_en_l2b0_3);
10259assign l2b0_dv_3[12] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 6) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[12] ) &&
10260 ~((rd_addr_l2b0_3 == 6) && !rd_en_l2b0_3);
10261assign l2b0_dv_3[13] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 6) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[13] ) &&
10262 ~((rd_addr_l2b0_3 == 6) && !rd_en_l2b0_3);
10263assign l2b0_dv_3[14] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 7) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[14] ) &&
10264 ~((rd_addr_l2b0_3 == 7) && !rd_en_l2b0_3);
10265assign l2b0_dv_3[15] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 7) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[15] ) &&
10266 ~((rd_addr_l2b0_3 == 7) && !rd_en_l2b0_3);
10267assign l2b0_dv_3[16] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 8) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[16] ) &&
10268 ~((rd_addr_l2b0_3 == 8) && !rd_en_l2b0_3);
10269assign l2b0_dv_3[17] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 8) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[17] ) &&
10270 ~((rd_addr_l2b0_3 == 8) && !rd_en_l2b0_3);
10271assign l2b0_dv_3[18] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 9) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[18] ) &&
10272 ~((rd_addr_l2b0_3 == 9) && !rd_en_l2b0_3);
10273assign l2b0_dv_3[19] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 9) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[19] ) &&
10274 ~((rd_addr_l2b0_3 == 9) && !rd_en_l2b0_3);
10275assign l2b0_dv_3[20] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 10) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[20] ) &&
10276 ~((rd_addr_l2b0_3 == 10) && !rd_en_l2b0_3);
10277assign l2b0_dv_3[21] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 10) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[21] ) &&
10278 ~((rd_addr_l2b0_3 == 10) && !rd_en_l2b0_3);
10279assign l2b0_dv_3[22] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 11) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[22] ) &&
10280 ~((rd_addr_l2b0_3 == 11) && !rd_en_l2b0_3);
10281assign l2b0_dv_3[23] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 11) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[23] ) &&
10282 ~((rd_addr_l2b0_3 == 11) && !rd_en_l2b0_3);
10283assign l2b0_dv_3[24] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 12) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[24] ) &&
10284 ~((rd_addr_l2b0_3 == 12) && !rd_en_l2b0_3);
10285assign l2b0_dv_3[25] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 12) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[25] ) &&
10286 ~((rd_addr_l2b0_3 == 12) && !rd_en_l2b0_3);
10287assign l2b0_dv_3[26] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 13) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[26] ) &&
10288 ~((rd_addr_l2b0_3 == 13) && !rd_en_l2b0_3);
10289assign l2b0_dv_3[27] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 13) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[27] ) &&
10290 ~((rd_addr_l2b0_3 == 13) && !rd_en_l2b0_3);
10291assign l2b0_dv_3[28] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 14) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[28] ) &&
10292 ~((rd_addr_l2b0_3 == 14) && !rd_en_l2b0_3);
10293assign l2b0_dv_3[29] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 14) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[29] ) &&
10294 ~((rd_addr_l2b0_3 == 14) && !rd_en_l2b0_3);
10295assign l2b0_dv_3[30] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 15) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[30] ) &&
10296 ~((rd_addr_l2b0_3 == 15) && !rd_en_l2b0_3);
10297assign l2b0_dv_3[31] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 15) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[31] ) &&
10298 ~((rd_addr_l2b0_3 == 15) && !rd_en_l2b0_3);
10299assign l2b0_dv_3[32] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 16) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[32] ) &&
10300 ~((rd_addr_l2b0_3 == 16) && !rd_en_l2b0_3);
10301assign l2b0_dv_3[33] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 16) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[33] ) &&
10302 ~((rd_addr_l2b0_3 == 16) && !rd_en_l2b0_3);
10303assign l2b0_dv_3[34] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 17) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[34] ) &&
10304 ~((rd_addr_l2b0_3 == 17) && !rd_en_l2b0_3);
10305assign l2b0_dv_3[35] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 17) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[35] ) &&
10306 ~((rd_addr_l2b0_3 == 17) && !rd_en_l2b0_3);
10307assign l2b0_dv_3[36] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 18) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[36] ) &&
10308 ~((rd_addr_l2b0_3 == 18) && !rd_en_l2b0_3);
10309assign l2b0_dv_3[37] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 18) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[37] ) &&
10310 ~((rd_addr_l2b0_3 == 18) && !rd_en_l2b0_3);
10311assign l2b0_dv_3[38] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 19) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[38] ) &&
10312 ~((rd_addr_l2b0_3 == 19) && !rd_en_l2b0_3);
10313assign l2b0_dv_3[39] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 19) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[39] ) &&
10314 ~((rd_addr_l2b0_3 == 19) && !rd_en_l2b0_3);
10315assign l2b0_dv_3[40] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 20) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[40] ) &&
10316 ~((rd_addr_l2b0_3 == 20) && !rd_en_l2b0_3);
10317assign l2b0_dv_3[41] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 20) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[41] ) &&
10318 ~((rd_addr_l2b0_3 == 20) && !rd_en_l2b0_3);
10319assign l2b0_dv_3[42] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 21) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[42] ) &&
10320 ~((rd_addr_l2b0_3 == 21) && !rd_en_l2b0_3);
10321assign l2b0_dv_3[43] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 21) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[43] ) &&
10322 ~((rd_addr_l2b0_3 == 21) && !rd_en_l2b0_3);
10323assign l2b0_dv_3[44] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 22) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[44] ) &&
10324 ~((rd_addr_l2b0_3 == 22) && !rd_en_l2b0_3);
10325assign l2b0_dv_3[45] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 22) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[45] ) &&
10326 ~((rd_addr_l2b0_3 == 22) && !rd_en_l2b0_3);
10327assign l2b0_dv_3[46] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 23) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[46] ) &&
10328 ~((rd_addr_l2b0_3 == 23) && !rd_en_l2b0_3);
10329assign l2b0_dv_3[47] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 23) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[47] ) &&
10330 ~((rd_addr_l2b0_3 == 23) && !rd_en_l2b0_3);
10331assign l2b0_dv_3[48] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 24) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[48] ) &&
10332 ~((rd_addr_l2b0_3 == 24) && !rd_en_l2b0_3);
10333assign l2b0_dv_3[49] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 24) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[49] ) &&
10334 ~((rd_addr_l2b0_3 == 24) && !rd_en_l2b0_3);
10335assign l2b0_dv_3[50] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 25) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[50] ) &&
10336 ~((rd_addr_l2b0_3 == 25) && !rd_en_l2b0_3);
10337assign l2b0_dv_3[51] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 25) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[51] ) &&
10338 ~((rd_addr_l2b0_3 == 25) && !rd_en_l2b0_3);
10339assign l2b0_dv_3[52] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 26) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[52] ) &&
10340 ~((rd_addr_l2b0_3 == 26) && !rd_en_l2b0_3);
10341assign l2b0_dv_3[53] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 26) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[53] ) &&
10342 ~((rd_addr_l2b0_3 == 26) && !rd_en_l2b0_3);
10343assign l2b0_dv_3[54] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 27) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[54] ) &&
10344 ~((rd_addr_l2b0_3 == 27) && !rd_en_l2b0_3);
10345assign l2b0_dv_3[55] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 27) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[55] ) &&
10346 ~((rd_addr_l2b0_3 == 27) && !rd_en_l2b0_3);
10347assign l2b0_dv_3[56] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 28) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[56] ) &&
10348 ~((rd_addr_l2b0_3 == 28) && !rd_en_l2b0_3);
10349assign l2b0_dv_3[57] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 28) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[57] ) &&
10350 ~((rd_addr_l2b0_3 == 28) && !rd_en_l2b0_3);
10351assign l2b0_dv_3[58] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 29) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[58] ) &&
10352 ~((rd_addr_l2b0_3 == 29) && !rd_en_l2b0_3);
10353assign l2b0_dv_3[59] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 29) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[59] ) &&
10354 ~((rd_addr_l2b0_3 == 29) && !rd_en_l2b0_3);
10355assign l2b0_dv_3[60] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 30) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[60] ) &&
10356 ~((rd_addr_l2b0_3 == 30) && !rd_en_l2b0_3);
10357assign l2b0_dv_3[61] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 30) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[61] ) &&
10358 ~((rd_addr_l2b0_3 == 30) && !rd_en_l2b0_3);
10359assign l2b0_dv_3[62] = ((!wr_en_l2b0_3[0] && (l2b0_wr_addr_3 == 31) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[62] ) &&
10360 ~((rd_addr_l2b0_3 == 31) && !rd_en_l2b0_3);
10361assign l2b0_dv_3[63] = ((!wr_en_l2b0_3[1] && (l2b0_wr_addr_3 == 31) && !dram_Ch3_l2b0_pa_err) || l2b0_dv_3_reg[63] ) &&
10362 ~((rd_addr_l2b0_3 == 31) && !rd_en_l2b0_3);
10363
10364always @(posedge (cmp_clk && enabled)) begin
10365 if (~cmp_rst_l)
10366 begin
10367 l2b0_dv_3_reg <= 64'b0;
10368 end
10369 else begin
10370 l2b0_dv_3_reg <= l2b0_dv_3;
10371 end
10372end
10373
10374// actual monitor
10375// if read and the locations dv not valid
10376// monitoring in cmp_clk and so should be monitored only on the first clock
10377// after which the rd may be valid in the dram clock
10378reg dram_rst_l_l2b0_3_1;
10379reg [5:0] addr_reg_l2b0_3;
10380always @ (posedge (cmp_clk && enabled))
10381begin
10382if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
10383end else begin
10384
10385// need to delay as on 1st dram clk after reset the rd_en has still not
10386dram_rst_l_l2b0_3_1 <= #1 dram_rst_l;
10387addr_reg_l2b0_3 <= #1 {rd_en_l2b0_3, rd_addr_l2b0_3};
10388
10389if (dram_rst_l_l2b0_3_1 && (~rd_en_l2b0_3) &&
10390 (addr_reg_l2b0_3 != {rd_en_l2b0_3, rd_addr_l2b0_3}) &&
10391 (rd_addr_l2b0_3[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
10392/*mb156858 if (!l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 0] || !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 1] ||
10393 !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 2] || !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 3] ||
10394 !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 4] || !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 5] ||
10395 !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 6] || !l2b0_dv_3_reg[rd_addr_l2b0_3*2 + 7]) begin
10396 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
10397 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b0_3, l2b0_dv_3_reg);
10398 finish_test(" CAS Issued Data not valid ", 3);
10399 end */
10400end
10401end
10402end
10403
10404
10405// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
10406
10407always @ (posedge (cmp_clk && enabled))
10408begin
10409if (cmp_rst_l && (~wr_en_l2b0_3[0])) begin
10410 if (l2b0_dv_3_reg[l2b0_wr_addr_3*2 + 0]) begin
10411 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
10412 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_3,wr_en_l2b0_3, l2b0_dv_3_reg);
10413 finish_test(" Data Overwritten in write fifo ", 3);
10414 end
10415end
10416if (cmp_rst_l && (~wr_en_l2b0_3[1])) begin
10417 if (l2b0_dv_3_reg[l2b0_wr_addr_3*2 + 1]) begin
10418 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
10419 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b0_wr_addr_3,wr_en_l2b0_3, l2b0_dv_3_reg);
10420 finish_test(" Data Overwritten in write fifo ", 3);
10421 end
10422end
10423end
10424
10425
10426wire [63:0] l2b1_dv_3;
10427reg [63:0] l2b1_dv_3_reg;
10428
10429wire [1:0] wr_en_l2b1_3 = ~dram_Ch3_l2b1_cpu_wr_en; // MAQ Active High wr_en in N2 wire [3:0] wr_en_3 = dram_Ch3_cpu_wr_en;
10430wire [4:0] l2b1_wr_addr_3 = dram_Ch3_l2b1_cpu_wr_addr;
10431wire rd_en_l2b1_3 = ~dram_Ch3_l2b1_wdq_rd_en;
10432wire [4:0] rd_addr_l2b1_3 = dram_Ch3_l2b1_wdq_radr[4:0];
10433
10434// there are 0-63 data valids, each (of the 4) instance in dram_mem.v
10435// has 64 bit data. total size per instance = 32 deep // MAQ 16 deep.
10436// $p dv index
10437// $q 0 1 2 3
10438// $r addr
10439
10440assign l2b1_dv_3[0] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 0) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[0] ) &&
10441 ~((rd_addr_l2b1_3 == 0) && !rd_en_l2b1_3);
10442assign l2b1_dv_3[1] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 0) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[1] ) &&
10443 ~((rd_addr_l2b1_3 == 0) && !rd_en_l2b1_3);
10444assign l2b1_dv_3[2] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 1) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[2] ) &&
10445 ~((rd_addr_l2b1_3 == 1) && !rd_en_l2b1_3);
10446assign l2b1_dv_3[3] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 1) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[3] ) &&
10447 ~((rd_addr_l2b1_3 == 1) && !rd_en_l2b1_3);
10448assign l2b1_dv_3[4] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 2) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[4] ) &&
10449 ~((rd_addr_l2b1_3 == 2) && !rd_en_l2b1_3);
10450assign l2b1_dv_3[5] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 2) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[5] ) &&
10451 ~((rd_addr_l2b1_3 == 2) && !rd_en_l2b1_3);
10452assign l2b1_dv_3[6] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 3) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[6] ) &&
10453 ~((rd_addr_l2b1_3 == 3) && !rd_en_l2b1_3);
10454assign l2b1_dv_3[7] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 3) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[7] ) &&
10455 ~((rd_addr_l2b1_3 == 3) && !rd_en_l2b1_3);
10456assign l2b1_dv_3[8] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 4) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[8] ) &&
10457 ~((rd_addr_l2b1_3 == 4) && !rd_en_l2b1_3);
10458assign l2b1_dv_3[9] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 4) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[9] ) &&
10459 ~((rd_addr_l2b1_3 == 4) && !rd_en_l2b1_3);
10460assign l2b1_dv_3[10] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 5) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[10] ) &&
10461 ~((rd_addr_l2b1_3 == 5) && !rd_en_l2b1_3);
10462assign l2b1_dv_3[11] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 5) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[11] ) &&
10463 ~((rd_addr_l2b1_3 == 5) && !rd_en_l2b1_3);
10464assign l2b1_dv_3[12] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 6) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[12] ) &&
10465 ~((rd_addr_l2b1_3 == 6) && !rd_en_l2b1_3);
10466assign l2b1_dv_3[13] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 6) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[13] ) &&
10467 ~((rd_addr_l2b1_3 == 6) && !rd_en_l2b1_3);
10468assign l2b1_dv_3[14] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 7) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[14] ) &&
10469 ~((rd_addr_l2b1_3 == 7) && !rd_en_l2b1_3);
10470assign l2b1_dv_3[15] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 7) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[15] ) &&
10471 ~((rd_addr_l2b1_3 == 7) && !rd_en_l2b1_3);
10472assign l2b1_dv_3[16] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 8) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[16] ) &&
10473 ~((rd_addr_l2b1_3 == 8) && !rd_en_l2b1_3);
10474assign l2b1_dv_3[17] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 8) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[17] ) &&
10475 ~((rd_addr_l2b1_3 == 8) && !rd_en_l2b1_3);
10476assign l2b1_dv_3[18] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 9) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[18] ) &&
10477 ~((rd_addr_l2b1_3 == 9) && !rd_en_l2b1_3);
10478assign l2b1_dv_3[19] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 9) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[19] ) &&
10479 ~((rd_addr_l2b1_3 == 9) && !rd_en_l2b1_3);
10480assign l2b1_dv_3[20] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 10) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[20] ) &&
10481 ~((rd_addr_l2b1_3 == 10) && !rd_en_l2b1_3);
10482assign l2b1_dv_3[21] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 10) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[21] ) &&
10483 ~((rd_addr_l2b1_3 == 10) && !rd_en_l2b1_3);
10484assign l2b1_dv_3[22] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 11) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[22] ) &&
10485 ~((rd_addr_l2b1_3 == 11) && !rd_en_l2b1_3);
10486assign l2b1_dv_3[23] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 11) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[23] ) &&
10487 ~((rd_addr_l2b1_3 == 11) && !rd_en_l2b1_3);
10488assign l2b1_dv_3[24] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 12) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[24] ) &&
10489 ~((rd_addr_l2b1_3 == 12) && !rd_en_l2b1_3);
10490assign l2b1_dv_3[25] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 12) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[25] ) &&
10491 ~((rd_addr_l2b1_3 == 12) && !rd_en_l2b1_3);
10492assign l2b1_dv_3[26] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 13) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[26] ) &&
10493 ~((rd_addr_l2b1_3 == 13) && !rd_en_l2b1_3);
10494assign l2b1_dv_3[27] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 13) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[27] ) &&
10495 ~((rd_addr_l2b1_3 == 13) && !rd_en_l2b1_3);
10496assign l2b1_dv_3[28] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 14) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[28] ) &&
10497 ~((rd_addr_l2b1_3 == 14) && !rd_en_l2b1_3);
10498assign l2b1_dv_3[29] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 14) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[29] ) &&
10499 ~((rd_addr_l2b1_3 == 14) && !rd_en_l2b1_3);
10500assign l2b1_dv_3[30] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 15) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[30] ) &&
10501 ~((rd_addr_l2b1_3 == 15) && !rd_en_l2b1_3);
10502assign l2b1_dv_3[31] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 15) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[31] ) &&
10503 ~((rd_addr_l2b1_3 == 15) && !rd_en_l2b1_3);
10504assign l2b1_dv_3[32] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 16) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[32] ) &&
10505 ~((rd_addr_l2b1_3 == 16) && !rd_en_l2b1_3);
10506assign l2b1_dv_3[33] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 16) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[33] ) &&
10507 ~((rd_addr_l2b1_3 == 16) && !rd_en_l2b1_3);
10508assign l2b1_dv_3[34] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 17) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[34] ) &&
10509 ~((rd_addr_l2b1_3 == 17) && !rd_en_l2b1_3);
10510assign l2b1_dv_3[35] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 17) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[35] ) &&
10511 ~((rd_addr_l2b1_3 == 17) && !rd_en_l2b1_3);
10512assign l2b1_dv_3[36] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 18) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[36] ) &&
10513 ~((rd_addr_l2b1_3 == 18) && !rd_en_l2b1_3);
10514assign l2b1_dv_3[37] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 18) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[37] ) &&
10515 ~((rd_addr_l2b1_3 == 18) && !rd_en_l2b1_3);
10516assign l2b1_dv_3[38] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 19) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[38] ) &&
10517 ~((rd_addr_l2b1_3 == 19) && !rd_en_l2b1_3);
10518assign l2b1_dv_3[39] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 19) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[39] ) &&
10519 ~((rd_addr_l2b1_3 == 19) && !rd_en_l2b1_3);
10520assign l2b1_dv_3[40] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 20) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[40] ) &&
10521 ~((rd_addr_l2b1_3 == 20) && !rd_en_l2b1_3);
10522assign l2b1_dv_3[41] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 20) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[41] ) &&
10523 ~((rd_addr_l2b1_3 == 20) && !rd_en_l2b1_3);
10524assign l2b1_dv_3[42] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 21) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[42] ) &&
10525 ~((rd_addr_l2b1_3 == 21) && !rd_en_l2b1_3);
10526assign l2b1_dv_3[43] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 21) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[43] ) &&
10527 ~((rd_addr_l2b1_3 == 21) && !rd_en_l2b1_3);
10528assign l2b1_dv_3[44] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 22) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[44] ) &&
10529 ~((rd_addr_l2b1_3 == 22) && !rd_en_l2b1_3);
10530assign l2b1_dv_3[45] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 22) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[45] ) &&
10531 ~((rd_addr_l2b1_3 == 22) && !rd_en_l2b1_3);
10532assign l2b1_dv_3[46] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 23) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[46] ) &&
10533 ~((rd_addr_l2b1_3 == 23) && !rd_en_l2b1_3);
10534assign l2b1_dv_3[47] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 23) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[47] ) &&
10535 ~((rd_addr_l2b1_3 == 23) && !rd_en_l2b1_3);
10536assign l2b1_dv_3[48] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 24) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[48] ) &&
10537 ~((rd_addr_l2b1_3 == 24) && !rd_en_l2b1_3);
10538assign l2b1_dv_3[49] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 24) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[49] ) &&
10539 ~((rd_addr_l2b1_3 == 24) && !rd_en_l2b1_3);
10540assign l2b1_dv_3[50] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 25) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[50] ) &&
10541 ~((rd_addr_l2b1_3 == 25) && !rd_en_l2b1_3);
10542assign l2b1_dv_3[51] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 25) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[51] ) &&
10543 ~((rd_addr_l2b1_3 == 25) && !rd_en_l2b1_3);
10544assign l2b1_dv_3[52] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 26) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[52] ) &&
10545 ~((rd_addr_l2b1_3 == 26) && !rd_en_l2b1_3);
10546assign l2b1_dv_3[53] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 26) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[53] ) &&
10547 ~((rd_addr_l2b1_3 == 26) && !rd_en_l2b1_3);
10548assign l2b1_dv_3[54] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 27) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[54] ) &&
10549 ~((rd_addr_l2b1_3 == 27) && !rd_en_l2b1_3);
10550assign l2b1_dv_3[55] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 27) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[55] ) &&
10551 ~((rd_addr_l2b1_3 == 27) && !rd_en_l2b1_3);
10552assign l2b1_dv_3[56] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 28) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[56] ) &&
10553 ~((rd_addr_l2b1_3 == 28) && !rd_en_l2b1_3);
10554assign l2b1_dv_3[57] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 28) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[57] ) &&
10555 ~((rd_addr_l2b1_3 == 28) && !rd_en_l2b1_3);
10556assign l2b1_dv_3[58] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 29) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[58] ) &&
10557 ~((rd_addr_l2b1_3 == 29) && !rd_en_l2b1_3);
10558assign l2b1_dv_3[59] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 29) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[59] ) &&
10559 ~((rd_addr_l2b1_3 == 29) && !rd_en_l2b1_3);
10560assign l2b1_dv_3[60] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 30) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[60] ) &&
10561 ~((rd_addr_l2b1_3 == 30) && !rd_en_l2b1_3);
10562assign l2b1_dv_3[61] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 30) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[61] ) &&
10563 ~((rd_addr_l2b1_3 == 30) && !rd_en_l2b1_3);
10564assign l2b1_dv_3[62] = ((!wr_en_l2b1_3[0] && (l2b1_wr_addr_3 == 31) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[62] ) &&
10565 ~((rd_addr_l2b1_3 == 31) && !rd_en_l2b1_3);
10566assign l2b1_dv_3[63] = ((!wr_en_l2b1_3[1] && (l2b1_wr_addr_3 == 31) && !dram_Ch3_l2b1_pa_err) || l2b1_dv_3_reg[63] ) &&
10567 ~((rd_addr_l2b1_3 == 31) && !rd_en_l2b1_3);
10568
10569always @(posedge (cmp_clk && enabled)) begin
10570 if (~cmp_rst_l)
10571 begin
10572 l2b1_dv_3_reg <= 64'b0;
10573 end
10574 else begin
10575 l2b1_dv_3_reg <= l2b1_dv_3;
10576 end
10577end
10578
10579// actual monitor
10580// if read and the locations dv not valid
10581// monitoring in cmp_clk and so should be monitored only on the first clock
10582// after which the rd may be valid in the dram clock
10583reg dram_rst_l_l2b1_3_1;
10584reg [5:0] addr_reg_l2b1_3;
10585always @ (posedge (cmp_clk && enabled))
10586begin
10587if($test$plusargs("WARM_RESET") || $test$plusargs("freq_change")) begin
10588end else begin
10589
10590// need to delay as on 1st dram clk after reset the rd_en has still not
10591dram_rst_l_l2b1_3_1 <= #1 dram_rst_l;
10592addr_reg_l2b1_3 <= #1 {rd_en_l2b1_3, rd_addr_l2b1_3};
10593
10594if (dram_rst_l_l2b1_3_1 && (~rd_en_l2b1_3) &&
10595 (addr_reg_l2b1_3 != {rd_en_l2b1_3, rd_addr_l2b1_3}) &&
10596 (rd_addr_l2b1_3[2:0] == 0) ) begin // MAQ added condition to check only for 1st rd
10597/*mb156858 if (!l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 0] || !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 1] ||
10598 !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 2] || !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 3] ||
10599 !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 4] || !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 5] ||
10600 !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 6] || !l2b1_dv_3_reg[rd_addr_l2b1_3*2 + 7]) begin
10601 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
10602 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x is read but not valid, fifo valids = %x", $time, rd_addr_l2b1_3, l2b1_dv_3_reg);
10603 finish_test(" CAS Issued Data not valid ", 3);
10604 end */
10605end
10606end
10607end
10608
10609
10610// ---- IF WRITE AND THE LOCATIONS DV ALREADY VALID -----
10611
10612always @ (posedge (cmp_clk && enabled))
10613begin
10614if (cmp_rst_l && (~wr_en_l2b1_3[0])) begin
10615 if (l2b1_dv_3_reg[l2b1_wr_addr_3*2 + 0]) begin
10616 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
10617 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_3,wr_en_l2b1_3, l2b1_dv_3_reg);
10618 finish_test(" Data Overwritten in write fifo ", 3);
10619 end
10620end
10621if (cmp_rst_l && (~wr_en_l2b1_3[1])) begin
10622 if (l2b1_dv_3_reg[l2b1_wr_addr_3*2 + 1]) begin
10623 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
10624 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d fifo address = %x, wr_enable = %x, is written but already valid, fifo valids = %x", $time, l2b1_wr_addr_3,wr_en_l2b1_3, l2b1_dv_3_reg);
10625 finish_test(" Data Overwritten in write fifo ", 3);
10626 end
10627end
10628end
10629
10630
10631
10632// ----- WR Q VALID AND DATA WRITTEN ( OVERWRITTING AN EXISTING ENTRY ) -----
10633
10634 reg [40:0] l2b0_wr_q_loc4_0;
10635always @ (dram_Ch0_l2b0_wr_que_wr_ptr)
10636begin
10637if (dram_rst_l) begin
10638 for(i=0;i<8;i=i+1) begin
10639 l2b0_wr_q_loc4_0 = dram_Ch0_l2b0_wr_q[i];
10640 if ((dram_Ch0_l2b0_wr_que_wr_ptr[i] == 1'b1) && ((l2b0_wr_q_loc4_0[39] || l2b0_wr_q_loc4_0[40]) == 1'b1)) begin
10641 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
10642 finish_test(" WR Q : OverWriting to a valid WR Q location", 0);
10643 end
10644 end
10645end
10646end
10647 reg [40:0] l2b1_wr_q_loc4_0;
10648always @ (dram_Ch0_l2b1_wr_que_wr_ptr)
10649begin
10650if (dram_rst_l) begin
10651 for(i=0;i<8;i=i+1) begin
10652 l2b1_wr_q_loc4_0 = dram_Ch0_l2b1_wr_q[i];
10653 if ((dram_Ch0_l2b1_wr_que_wr_ptr[i] == 1'b1) && ((l2b1_wr_q_loc4_0[39] || l2b1_wr_q_loc4_0[40]) == 1'b1)) begin
10654 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
10655 finish_test(" WR Q : OverWriting to a valid WR Q location", 0);
10656 end
10657 end
10658end
10659end
10660 reg [40:0] l2b0_wr_q_loc4_1;
10661always @ (dram_Ch1_l2b0_wr_que_wr_ptr)
10662begin
10663if (dram_rst_l) begin
10664 for(i=0;i<8;i=i+1) begin
10665 l2b0_wr_q_loc4_1 = dram_Ch1_l2b0_wr_q[i];
10666 if ((dram_Ch1_l2b0_wr_que_wr_ptr[i] == 1'b1) && ((l2b0_wr_q_loc4_1[39] || l2b0_wr_q_loc4_1[40]) == 1'b1)) begin
10667 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
10668 finish_test(" WR Q : OverWriting to a valid WR Q location", 1);
10669 end
10670 end
10671end
10672end
10673 reg [40:0] l2b1_wr_q_loc4_1;
10674always @ (dram_Ch1_l2b1_wr_que_wr_ptr)
10675begin
10676if (dram_rst_l) begin
10677 for(i=0;i<8;i=i+1) begin
10678 l2b1_wr_q_loc4_1 = dram_Ch1_l2b1_wr_q[i];
10679 if ((dram_Ch1_l2b1_wr_que_wr_ptr[i] == 1'b1) && ((l2b1_wr_q_loc4_1[39] || l2b1_wr_q_loc4_1[40]) == 1'b1)) begin
10680 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
10681 finish_test(" WR Q : OverWriting to a valid WR Q location", 1);
10682 end
10683 end
10684end
10685end
10686 reg [40:0] l2b0_wr_q_loc4_2;
10687always @ (dram_Ch2_l2b0_wr_que_wr_ptr)
10688begin
10689if (dram_rst_l) begin
10690 for(i=0;i<8;i=i+1) begin
10691 l2b0_wr_q_loc4_2 = dram_Ch2_l2b0_wr_q[i];
10692 if ((dram_Ch2_l2b0_wr_que_wr_ptr[i] == 1'b1) && ((l2b0_wr_q_loc4_2[39] || l2b0_wr_q_loc4_2[40]) == 1'b1)) begin
10693 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
10694 finish_test(" WR Q : OverWriting to a valid WR Q location", 2);
10695 end
10696 end
10697end
10698end
10699 reg [40:0] l2b1_wr_q_loc4_2;
10700always @ (dram_Ch2_l2b1_wr_que_wr_ptr)
10701begin
10702if (dram_rst_l) begin
10703 for(i=0;i<8;i=i+1) begin
10704 l2b1_wr_q_loc4_2 = dram_Ch2_l2b1_wr_q[i];
10705 if ((dram_Ch2_l2b1_wr_que_wr_ptr[i] == 1'b1) && ((l2b1_wr_q_loc4_2[39] || l2b1_wr_q_loc4_2[40]) == 1'b1)) begin
10706 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
10707 finish_test(" WR Q : OverWriting to a valid WR Q location", 2);
10708 end
10709 end
10710end
10711end
10712 reg [40:0] l2b0_wr_q_loc4_3;
10713always @ (dram_Ch3_l2b0_wr_que_wr_ptr)
10714begin
10715if (dram_rst_l) begin
10716 for(i=0;i<8;i=i+1) begin
10717 l2b0_wr_q_loc4_3 = dram_Ch3_l2b0_wr_q[i];
10718 if ((dram_Ch3_l2b0_wr_que_wr_ptr[i] == 1'b1) && ((l2b0_wr_q_loc4_3[39] || l2b0_wr_q_loc4_3[40]) == 1'b1)) begin
10719 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
10720 finish_test(" WR Q : OverWriting to a valid WR Q location", 3);
10721 end
10722 end
10723end
10724end
10725 reg [40:0] l2b1_wr_q_loc4_3;
10726always @ (dram_Ch3_l2b1_wr_que_wr_ptr)
10727begin
10728if (dram_rst_l) begin
10729 for(i=0;i<8;i=i+1) begin
10730 l2b1_wr_q_loc4_3 = dram_Ch3_l2b1_wr_q[i];
10731 if ((dram_Ch3_l2b1_wr_que_wr_ptr[i] == 1'b1) && ((l2b1_wr_q_loc4_3[39] || l2b1_wr_q_loc4_3[40]) == 1'b1)) begin
10732 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
10733 finish_test(" WR Q : OverWriting to a valid WR Q location", 3);
10734 end
10735 end
10736end
10737end
10738
10739// ----- WR Q NOT VALID AND DATA READ ( RD_PTR FOR WR QUE ASSERTED ) -----
10740
10741 reg [40:0] l2b0_wr_q_loc6_0;
10742always @ (posedge (`MCU_CLK && enabled))
10743//always @ (dram_Ch0_l2b0_wr_que_rd_ptr)
10744begin
10745 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch0_l2b0_wr_que_rd_ptr = %x", $time, dram_Ch0_l2b0_wr_que_rd_ptr);
10746if (dram_rst_l) begin
10747 for(i=0;i<8;i=i+1) begin
10748 l2b0_wr_q_loc6_0 = dram_Ch0_l2b0_wr_q[i];
10749 if ((dram_Ch0_l2b0_wr_que_rd_ptr[i] == 1'b1) && (l2b0_wr_q_loc6_0[40] == 1'b0)) begin
10750 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch0_l2b0_wr_que_rd_ptr = %x", dram_Ch0_l2b0_wr_que_rd_ptr);
10751 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
10752 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 0);
10753 end
10754 end
10755end
10756end
10757 reg [40:0] l2b1_wr_q_loc6_0;
10758always @ (posedge (`MCU_CLK && enabled))
10759//always @ (dram_Ch0_l2b1_wr_que_rd_ptr)
10760begin
10761 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch0_l2b1_wr_que_rd_ptr = %x", $time, dram_Ch0_l2b1_wr_que_rd_ptr);
10762if (dram_rst_l) begin
10763 for(i=0;i<8;i=i+1) begin
10764 l2b1_wr_q_loc6_0 = dram_Ch0_l2b1_wr_q[i];
10765 if ((dram_Ch0_l2b1_wr_que_rd_ptr[i] == 1'b1) && (l2b1_wr_q_loc6_0[40] == 1'b0)) begin
10766 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch0_l2b1_wr_que_rd_ptr = %x", dram_Ch0_l2b1_wr_que_rd_ptr);
10767 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
10768 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 0);
10769 end
10770 end
10771end
10772end
10773 reg [40:0] l2b0_wr_q_loc6_1;
10774always @ (posedge (`MCU_CLK && enabled))
10775//always @ (dram_Ch1_l2b0_wr_que_rd_ptr)
10776begin
10777 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch1_l2b0_wr_que_rd_ptr = %x", $time, dram_Ch1_l2b0_wr_que_rd_ptr);
10778if (dram_rst_l) begin
10779 for(i=0;i<8;i=i+1) begin
10780 l2b0_wr_q_loc6_1 = dram_Ch1_l2b0_wr_q[i];
10781 if ((dram_Ch1_l2b0_wr_que_rd_ptr[i] == 1'b1) && (l2b0_wr_q_loc6_1[40] == 1'b0)) begin
10782 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch1_l2b0_wr_que_rd_ptr = %x", dram_Ch1_l2b0_wr_que_rd_ptr);
10783 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
10784 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 1);
10785 end
10786 end
10787end
10788end
10789 reg [40:0] l2b1_wr_q_loc6_1;
10790always @ (posedge (`MCU_CLK && enabled))
10791//always @ (dram_Ch1_l2b1_wr_que_rd_ptr)
10792begin
10793 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch1_l2b1_wr_que_rd_ptr = %x", $time, dram_Ch1_l2b1_wr_que_rd_ptr);
10794if (dram_rst_l) begin
10795 for(i=0;i<8;i=i+1) begin
10796 l2b1_wr_q_loc6_1 = dram_Ch1_l2b1_wr_q[i];
10797 if ((dram_Ch1_l2b1_wr_que_rd_ptr[i] == 1'b1) && (l2b1_wr_q_loc6_1[40] == 1'b0)) begin
10798 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch1_l2b1_wr_que_rd_ptr = %x", dram_Ch1_l2b1_wr_que_rd_ptr);
10799 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
10800 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 1);
10801 end
10802 end
10803end
10804end
10805 reg [40:0] l2b0_wr_q_loc6_2;
10806always @ (posedge (`MCU_CLK && enabled))
10807//always @ (dram_Ch2_l2b0_wr_que_rd_ptr)
10808begin
10809 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch2_l2b0_wr_que_rd_ptr = %x", $time, dram_Ch2_l2b0_wr_que_rd_ptr);
10810if (dram_rst_l) begin
10811 for(i=0;i<8;i=i+1) begin
10812 l2b0_wr_q_loc6_2 = dram_Ch2_l2b0_wr_q[i];
10813 if ((dram_Ch2_l2b0_wr_que_rd_ptr[i] == 1'b1) && (l2b0_wr_q_loc6_2[40] == 1'b0)) begin
10814 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch2_l2b0_wr_que_rd_ptr = %x", dram_Ch2_l2b0_wr_que_rd_ptr);
10815 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
10816 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 2);
10817 end
10818 end
10819end
10820end
10821 reg [40:0] l2b1_wr_q_loc6_2;
10822always @ (posedge (`MCU_CLK && enabled))
10823//always @ (dram_Ch2_l2b1_wr_que_rd_ptr)
10824begin
10825 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch2_l2b1_wr_que_rd_ptr = %x", $time, dram_Ch2_l2b1_wr_que_rd_ptr);
10826if (dram_rst_l) begin
10827 for(i=0;i<8;i=i+1) begin
10828 l2b1_wr_q_loc6_2 = dram_Ch2_l2b1_wr_q[i];
10829 if ((dram_Ch2_l2b1_wr_que_rd_ptr[i] == 1'b1) && (l2b1_wr_q_loc6_2[40] == 1'b0)) begin
10830 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch2_l2b1_wr_que_rd_ptr = %x", dram_Ch2_l2b1_wr_que_rd_ptr);
10831 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
10832 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 2);
10833 end
10834 end
10835end
10836end
10837 reg [40:0] l2b0_wr_q_loc6_3;
10838always @ (posedge (`MCU_CLK && enabled))
10839//always @ (dram_Ch3_l2b0_wr_que_rd_ptr)
10840begin
10841 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch3_l2b0_wr_que_rd_ptr = %x", $time, dram_Ch3_l2b0_wr_que_rd_ptr);
10842if (dram_rst_l) begin
10843 for(i=0;i<8;i=i+1) begin
10844 l2b0_wr_q_loc6_3 = dram_Ch3_l2b0_wr_q[i];
10845 if ((dram_Ch3_l2b0_wr_que_rd_ptr[i] == 1'b1) && (l2b0_wr_q_loc6_3[40] == 1'b0)) begin
10846 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch3_l2b0_wr_que_rd_ptr = %x", dram_Ch3_l2b0_wr_que_rd_ptr);
10847 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
10848 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 3);
10849 end
10850 end
10851end
10852end
10853 reg [40:0] l2b1_wr_q_loc6_3;
10854always @ (posedge (`MCU_CLK && enabled))
10855//always @ (dram_Ch3_l2b1_wr_que_rd_ptr)
10856begin
10857 //`PR_DEBUG("mcusat_cov_mon", `DEBUG, " at time %0d dram_Ch3_l2b1_wr_que_rd_ptr = %x", $time, dram_Ch3_l2b1_wr_que_rd_ptr);
10858if (dram_rst_l) begin
10859 for(i=0;i<8;i=i+1) begin
10860 l2b1_wr_q_loc6_3 = dram_Ch3_l2b1_wr_q[i];
10861 if ((dram_Ch3_l2b1_wr_que_rd_ptr[i] == 1'b1) && (l2b1_wr_q_loc6_3[40] == 1'b0)) begin
10862 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "dram_Ch3_l2b1_wr_que_rd_ptr = %x", dram_Ch3_l2b1_wr_que_rd_ptr);
10863 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
10864 finish_test(" WR Q : Clearing a WR Q location which is not valid ", 3);
10865 end
10866 end
10867end
10868end
10869
10870
10871// ---- MONITOR ALLOCATION AND DEALLOCATION TIME FOR EACH ENTRY IN THE WR Q ----
10872
10873reg [10:0] dram_Ch0_l2b0_wr_q_cntr [7:0];
10874wire [10:0] dram_Ch0_l2b0_wr_q_cntr_0 = dram_Ch0_l2b0_wr_q_cntr[0];
10875wire [10:0] dram_Ch0_l2b0_wr_q_cntr_1 = dram_Ch0_l2b0_wr_q_cntr[1];
10876wire [10:0] dram_Ch0_l2b0_wr_q_cntr_2 = dram_Ch0_l2b0_wr_q_cntr[2];
10877wire [10:0] dram_Ch0_l2b0_wr_q_cntr_3 = dram_Ch0_l2b0_wr_q_cntr[3];
10878wire [10:0] dram_Ch0_l2b0_wr_q_cntr_4 = dram_Ch0_l2b0_wr_q_cntr[4];
10879wire [10:0] dram_Ch0_l2b0_wr_q_cntr_5 = dram_Ch0_l2b0_wr_q_cntr[5];
10880wire [10:0] dram_Ch0_l2b0_wr_q_cntr_6 = dram_Ch0_l2b0_wr_q_cntr[6];
10881wire [10:0] dram_Ch0_l2b0_wr_q_cntr_7 = dram_Ch0_l2b0_wr_q_cntr[7];
10882
10883
10884always @ (posedge (`MCU_CLK && enabled))
10885begin
10886 if (~dram_rst_l)
10887 begin
10888 for(i=0;i<8;i=i+1) begin
10889 dram_Ch0_l2b0_wr_q_cntr[i] = 0;
10890 end
10891 end
10892 else
10893 begin
10894 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
10895 for(i=0;i<8;i=i+1) begin
10896 l2b0_wr_q_loc7_0 = dram_Ch0_l2b0_wr_q[i];
10897 dram_Ch0_l2b0_wr_q_cntr[i] <= (l2b0_wr_q_loc7_0[39] == 1'b1) ? dram_Ch0_l2b0_wr_q_cntr[i] + 1 : 0;
10898 if ( dram_Ch0_l2b0_wr_q_cntr[i] > MAX_TIME ) begin
10899 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
10900 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 0);
10901 end
10902 end
10903 end
10904 end
10905end
10906reg [10:0] dram_Ch0_l2b1_wr_q_cntr [7:0];
10907wire [10:0] dram_Ch0_l2b1_wr_q_cntr_0 = dram_Ch0_l2b1_wr_q_cntr[0];
10908wire [10:0] dram_Ch0_l2b1_wr_q_cntr_1 = dram_Ch0_l2b1_wr_q_cntr[1];
10909wire [10:0] dram_Ch0_l2b1_wr_q_cntr_2 = dram_Ch0_l2b1_wr_q_cntr[2];
10910wire [10:0] dram_Ch0_l2b1_wr_q_cntr_3 = dram_Ch0_l2b1_wr_q_cntr[3];
10911wire [10:0] dram_Ch0_l2b1_wr_q_cntr_4 = dram_Ch0_l2b1_wr_q_cntr[4];
10912wire [10:0] dram_Ch0_l2b1_wr_q_cntr_5 = dram_Ch0_l2b1_wr_q_cntr[5];
10913wire [10:0] dram_Ch0_l2b1_wr_q_cntr_6 = dram_Ch0_l2b1_wr_q_cntr[6];
10914wire [10:0] dram_Ch0_l2b1_wr_q_cntr_7 = dram_Ch0_l2b1_wr_q_cntr[7];
10915
10916
10917always @ (posedge (`MCU_CLK && enabled))
10918begin
10919 if (~dram_rst_l)
10920 begin
10921 for(i=0;i<8;i=i+1) begin
10922 dram_Ch0_l2b1_wr_q_cntr[i] = 0;
10923 end
10924 end
10925 else
10926 begin
10927 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
10928 for(i=0;i<8;i=i+1) begin
10929 l2b1_wr_q_loc7_0 = dram_Ch0_l2b1_wr_q[i];
10930 dram_Ch0_l2b1_wr_q_cntr[i] <= (l2b1_wr_q_loc7_0[39] == 1'b1) ? dram_Ch0_l2b1_wr_q_cntr[i] + 1 : 0;
10931 if ( dram_Ch0_l2b1_wr_q_cntr[i] > MAX_TIME ) begin
10932 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
10933 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 0);
10934 end
10935 end
10936 end
10937 end
10938end
10939reg [10:0] dram_Ch1_l2b0_wr_q_cntr [7:0];
10940wire [10:0] dram_Ch1_l2b0_wr_q_cntr_0 = dram_Ch1_l2b0_wr_q_cntr[0];
10941wire [10:0] dram_Ch1_l2b0_wr_q_cntr_1 = dram_Ch1_l2b0_wr_q_cntr[1];
10942wire [10:0] dram_Ch1_l2b0_wr_q_cntr_2 = dram_Ch1_l2b0_wr_q_cntr[2];
10943wire [10:0] dram_Ch1_l2b0_wr_q_cntr_3 = dram_Ch1_l2b0_wr_q_cntr[3];
10944wire [10:0] dram_Ch1_l2b0_wr_q_cntr_4 = dram_Ch1_l2b0_wr_q_cntr[4];
10945wire [10:0] dram_Ch1_l2b0_wr_q_cntr_5 = dram_Ch1_l2b0_wr_q_cntr[5];
10946wire [10:0] dram_Ch1_l2b0_wr_q_cntr_6 = dram_Ch1_l2b0_wr_q_cntr[6];
10947wire [10:0] dram_Ch1_l2b0_wr_q_cntr_7 = dram_Ch1_l2b0_wr_q_cntr[7];
10948
10949
10950always @ (posedge (`MCU_CLK && enabled))
10951begin
10952 if (~dram_rst_l)
10953 begin
10954 for(i=0;i<8;i=i+1) begin
10955 dram_Ch1_l2b0_wr_q_cntr[i] = 0;
10956 end
10957 end
10958 else
10959 begin
10960 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
10961 for(i=0;i<8;i=i+1) begin
10962 l2b0_wr_q_loc7_1 = dram_Ch1_l2b0_wr_q[i];
10963 dram_Ch1_l2b0_wr_q_cntr[i] <= (l2b0_wr_q_loc7_1[39] == 1'b1) ? dram_Ch1_l2b0_wr_q_cntr[i] + 1 : 0;
10964 if ( dram_Ch1_l2b0_wr_q_cntr[i] > MAX_TIME ) begin
10965 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
10966 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 1);
10967 end
10968 end
10969 end
10970 end
10971end
10972reg [10:0] dram_Ch1_l2b1_wr_q_cntr [7:0];
10973wire [10:0] dram_Ch1_l2b1_wr_q_cntr_0 = dram_Ch1_l2b1_wr_q_cntr[0];
10974wire [10:0] dram_Ch1_l2b1_wr_q_cntr_1 = dram_Ch1_l2b1_wr_q_cntr[1];
10975wire [10:0] dram_Ch1_l2b1_wr_q_cntr_2 = dram_Ch1_l2b1_wr_q_cntr[2];
10976wire [10:0] dram_Ch1_l2b1_wr_q_cntr_3 = dram_Ch1_l2b1_wr_q_cntr[3];
10977wire [10:0] dram_Ch1_l2b1_wr_q_cntr_4 = dram_Ch1_l2b1_wr_q_cntr[4];
10978wire [10:0] dram_Ch1_l2b1_wr_q_cntr_5 = dram_Ch1_l2b1_wr_q_cntr[5];
10979wire [10:0] dram_Ch1_l2b1_wr_q_cntr_6 = dram_Ch1_l2b1_wr_q_cntr[6];
10980wire [10:0] dram_Ch1_l2b1_wr_q_cntr_7 = dram_Ch1_l2b1_wr_q_cntr[7];
10981
10982
10983always @ (posedge (`MCU_CLK && enabled))
10984begin
10985 if (~dram_rst_l)
10986 begin
10987 for(i=0;i<8;i=i+1) begin
10988 dram_Ch1_l2b1_wr_q_cntr[i] = 0;
10989 end
10990 end
10991 else
10992 begin
10993 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
10994 for(i=0;i<8;i=i+1) begin
10995 l2b1_wr_q_loc7_1 = dram_Ch1_l2b1_wr_q[i];
10996 dram_Ch1_l2b1_wr_q_cntr[i] <= (l2b1_wr_q_loc7_1[39] == 1'b1) ? dram_Ch1_l2b1_wr_q_cntr[i] + 1 : 0;
10997 if ( dram_Ch1_l2b1_wr_q_cntr[i] > MAX_TIME ) begin
10998 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
10999 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 1);
11000 end
11001 end
11002 end
11003 end
11004end
11005reg [10:0] dram_Ch2_l2b0_wr_q_cntr [7:0];
11006wire [10:0] dram_Ch2_l2b0_wr_q_cntr_0 = dram_Ch2_l2b0_wr_q_cntr[0];
11007wire [10:0] dram_Ch2_l2b0_wr_q_cntr_1 = dram_Ch2_l2b0_wr_q_cntr[1];
11008wire [10:0] dram_Ch2_l2b0_wr_q_cntr_2 = dram_Ch2_l2b0_wr_q_cntr[2];
11009wire [10:0] dram_Ch2_l2b0_wr_q_cntr_3 = dram_Ch2_l2b0_wr_q_cntr[3];
11010wire [10:0] dram_Ch2_l2b0_wr_q_cntr_4 = dram_Ch2_l2b0_wr_q_cntr[4];
11011wire [10:0] dram_Ch2_l2b0_wr_q_cntr_5 = dram_Ch2_l2b0_wr_q_cntr[5];
11012wire [10:0] dram_Ch2_l2b0_wr_q_cntr_6 = dram_Ch2_l2b0_wr_q_cntr[6];
11013wire [10:0] dram_Ch2_l2b0_wr_q_cntr_7 = dram_Ch2_l2b0_wr_q_cntr[7];
11014
11015
11016always @ (posedge (`MCU_CLK && enabled))
11017begin
11018 if (~dram_rst_l)
11019 begin
11020 for(i=0;i<8;i=i+1) begin
11021 dram_Ch2_l2b0_wr_q_cntr[i] = 0;
11022 end
11023 end
11024 else
11025 begin
11026 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
11027 for(i=0;i<8;i=i+1) begin
11028 l2b0_wr_q_loc7_2 = dram_Ch2_l2b0_wr_q[i];
11029 dram_Ch2_l2b0_wr_q_cntr[i] <= (l2b0_wr_q_loc7_2[39] == 1'b1) ? dram_Ch2_l2b0_wr_q_cntr[i] + 1 : 0;
11030 if ( dram_Ch2_l2b0_wr_q_cntr[i] > MAX_TIME ) begin
11031 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
11032 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 2);
11033 end
11034 end
11035 end
11036 end
11037end
11038reg [10:0] dram_Ch2_l2b1_wr_q_cntr [7:0];
11039wire [10:0] dram_Ch2_l2b1_wr_q_cntr_0 = dram_Ch2_l2b1_wr_q_cntr[0];
11040wire [10:0] dram_Ch2_l2b1_wr_q_cntr_1 = dram_Ch2_l2b1_wr_q_cntr[1];
11041wire [10:0] dram_Ch2_l2b1_wr_q_cntr_2 = dram_Ch2_l2b1_wr_q_cntr[2];
11042wire [10:0] dram_Ch2_l2b1_wr_q_cntr_3 = dram_Ch2_l2b1_wr_q_cntr[3];
11043wire [10:0] dram_Ch2_l2b1_wr_q_cntr_4 = dram_Ch2_l2b1_wr_q_cntr[4];
11044wire [10:0] dram_Ch2_l2b1_wr_q_cntr_5 = dram_Ch2_l2b1_wr_q_cntr[5];
11045wire [10:0] dram_Ch2_l2b1_wr_q_cntr_6 = dram_Ch2_l2b1_wr_q_cntr[6];
11046wire [10:0] dram_Ch2_l2b1_wr_q_cntr_7 = dram_Ch2_l2b1_wr_q_cntr[7];
11047
11048
11049always @ (posedge (`MCU_CLK && enabled))
11050begin
11051 if (~dram_rst_l)
11052 begin
11053 for(i=0;i<8;i=i+1) begin
11054 dram_Ch2_l2b1_wr_q_cntr[i] = 0;
11055 end
11056 end
11057 else
11058 begin
11059 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
11060 for(i=0;i<8;i=i+1) begin
11061 l2b1_wr_q_loc7_2 = dram_Ch2_l2b1_wr_q[i];
11062 dram_Ch2_l2b1_wr_q_cntr[i] <= (l2b1_wr_q_loc7_2[39] == 1'b1) ? dram_Ch2_l2b1_wr_q_cntr[i] + 1 : 0;
11063 if ( dram_Ch2_l2b1_wr_q_cntr[i] > MAX_TIME ) begin
11064 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
11065 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 2);
11066 end
11067 end
11068 end
11069 end
11070end
11071reg [10:0] dram_Ch3_l2b0_wr_q_cntr [7:0];
11072wire [10:0] dram_Ch3_l2b0_wr_q_cntr_0 = dram_Ch3_l2b0_wr_q_cntr[0];
11073wire [10:0] dram_Ch3_l2b0_wr_q_cntr_1 = dram_Ch3_l2b0_wr_q_cntr[1];
11074wire [10:0] dram_Ch3_l2b0_wr_q_cntr_2 = dram_Ch3_l2b0_wr_q_cntr[2];
11075wire [10:0] dram_Ch3_l2b0_wr_q_cntr_3 = dram_Ch3_l2b0_wr_q_cntr[3];
11076wire [10:0] dram_Ch3_l2b0_wr_q_cntr_4 = dram_Ch3_l2b0_wr_q_cntr[4];
11077wire [10:0] dram_Ch3_l2b0_wr_q_cntr_5 = dram_Ch3_l2b0_wr_q_cntr[5];
11078wire [10:0] dram_Ch3_l2b0_wr_q_cntr_6 = dram_Ch3_l2b0_wr_q_cntr[6];
11079wire [10:0] dram_Ch3_l2b0_wr_q_cntr_7 = dram_Ch3_l2b0_wr_q_cntr[7];
11080
11081
11082always @ (posedge (`MCU_CLK && enabled))
11083begin
11084 if (~dram_rst_l)
11085 begin
11086 for(i=0;i<8;i=i+1) begin
11087 dram_Ch3_l2b0_wr_q_cntr[i] = 0;
11088 end
11089 end
11090 else
11091 begin
11092 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
11093 for(i=0;i<8;i=i+1) begin
11094 l2b0_wr_q_loc7_3 = dram_Ch3_l2b0_wr_q[i];
11095 dram_Ch3_l2b0_wr_q_cntr[i] <= (l2b0_wr_q_loc7_3[39] == 1'b1) ? dram_Ch3_l2b0_wr_q_cntr[i] + 1 : 0;
11096 if ( dram_Ch3_l2b0_wr_q_cntr[i] > MAX_TIME ) begin
11097 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
11098 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 3);
11099 end
11100 end
11101 end
11102 end
11103end
11104reg [10:0] dram_Ch3_l2b1_wr_q_cntr [7:0];
11105wire [10:0] dram_Ch3_l2b1_wr_q_cntr_0 = dram_Ch3_l2b1_wr_q_cntr[0];
11106wire [10:0] dram_Ch3_l2b1_wr_q_cntr_1 = dram_Ch3_l2b1_wr_q_cntr[1];
11107wire [10:0] dram_Ch3_l2b1_wr_q_cntr_2 = dram_Ch3_l2b1_wr_q_cntr[2];
11108wire [10:0] dram_Ch3_l2b1_wr_q_cntr_3 = dram_Ch3_l2b1_wr_q_cntr[3];
11109wire [10:0] dram_Ch3_l2b1_wr_q_cntr_4 = dram_Ch3_l2b1_wr_q_cntr[4];
11110wire [10:0] dram_Ch3_l2b1_wr_q_cntr_5 = dram_Ch3_l2b1_wr_q_cntr[5];
11111wire [10:0] dram_Ch3_l2b1_wr_q_cntr_6 = dram_Ch3_l2b1_wr_q_cntr[6];
11112wire [10:0] dram_Ch3_l2b1_wr_q_cntr_7 = dram_Ch3_l2b1_wr_q_cntr[7];
11113
11114
11115always @ (posedge (`MCU_CLK && enabled))
11116begin
11117 if (~dram_rst_l)
11118 begin
11119 for(i=0;i<8;i=i+1) begin
11120 dram_Ch3_l2b1_wr_q_cntr[i] = 0;
11121 end
11122 end
11123 else
11124 begin
11125 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
11126 for(i=0;i<8;i=i+1) begin
11127 l2b1_wr_q_loc7_3 = dram_Ch3_l2b1_wr_q[i];
11128 dram_Ch3_l2b1_wr_q_cntr[i] <= (l2b1_wr_q_loc7_3[39] == 1'b1) ? dram_Ch3_l2b1_wr_q_cntr[i] + 1 : 0;
11129 if ( dram_Ch3_l2b1_wr_q_cntr[i] > MAX_TIME ) begin
11130 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
11131 finish_test(" WR Q : Entry in write que for more that MAX_TIME clocks ", 3);
11132 end
11133 end
11134 end
11135 end
11136end
11137
11138
11139// ---- Monitor a case when the wr_req comes when the queue is full. Then q goes from full to not full and that read is taken ----
11140reg [1:0] dram_l2b0_wr_req_q_full_Ch0_wr_taken_state;
11141wire dram_l2b0_wr_q_full_Ch0_l2 = ((&dram_Ch0_l2b0_l2if_b0_wr_val) && (&dram_Ch0_l2b0_l2if_b1_wr_val));
11142always @ (posedge (cmp_clk && enabled))
11143begin
11144 if (~cmp_rst_l)
11145 begin
11146 dram_l2b0_wr_req_q_full_Ch0_wr_taken_state <= 2'b00;
11147 end
11148 else
11149 begin
11150
11151 case(dram_l2b0_wr_req_q_full_Ch0_wr_taken_state)
11152 2'b00 : begin
11153 if (dram_Ch0_l2b0_sctag_dram_wr_req && dram_l2b0_wr_q_full_Ch0_l2)
11154 dram_l2b0_wr_req_q_full_Ch0_wr_taken_state <= 2'b01;
11155 end
11156 2'b01 : begin
11157 if (dram_Ch0_l2b0_sctag_dram_wr_req && ~dram_l2b0_wr_q_full_Ch0_l2)
11158 dram_l2b0_wr_req_q_full_Ch0_wr_taken_state <= 2'b10;
11159 end
11160 2'b10 : begin
11161 if (~dram_Ch0_l2b0_sctag_dram_wr_req)
11162 dram_l2b0_wr_req_q_full_Ch0_wr_taken_state <= 2'b11;
11163 end
11164 2'b11 : begin
11165 dram_l2b0_wr_req_q_full_Ch0_wr_taken_state <= 2'b00;
11166 end
11167 default : begin
11168 dram_l2b0_wr_req_q_full_Ch0_wr_taken_state <= 2'b00;
11169 end
11170
11171 endcase
11172 end
11173end
11174reg [1:0] dram_l2b1_wr_req_q_full_Ch0_wr_taken_state;
11175wire dram_l2b1_wr_q_full_Ch0_l2 = ((&dram_Ch0_l2b1_l2if_b0_wr_val) && (&dram_Ch0_l2b1_l2if_b1_wr_val));
11176always @ (posedge (cmp_clk && enabled))
11177begin
11178 if (~cmp_rst_l)
11179 begin
11180 dram_l2b1_wr_req_q_full_Ch0_wr_taken_state <= 2'b00;
11181 end
11182 else
11183 begin
11184
11185 case(dram_l2b1_wr_req_q_full_Ch0_wr_taken_state)
11186 2'b00 : begin
11187 if (dram_Ch0_l2b1_sctag_dram_wr_req && dram_l2b1_wr_q_full_Ch0_l2)
11188 dram_l2b1_wr_req_q_full_Ch0_wr_taken_state <= 2'b01;
11189 end
11190 2'b01 : begin
11191 if (dram_Ch0_l2b1_sctag_dram_wr_req && ~dram_l2b1_wr_q_full_Ch0_l2)
11192 dram_l2b1_wr_req_q_full_Ch0_wr_taken_state <= 2'b10;
11193 end
11194 2'b10 : begin
11195 if (~dram_Ch0_l2b1_sctag_dram_wr_req)
11196 dram_l2b1_wr_req_q_full_Ch0_wr_taken_state <= 2'b11;
11197 end
11198 2'b11 : begin
11199 dram_l2b1_wr_req_q_full_Ch0_wr_taken_state <= 2'b00;
11200 end
11201 default : begin
11202 dram_l2b1_wr_req_q_full_Ch0_wr_taken_state <= 2'b00;
11203 end
11204
11205 endcase
11206 end
11207end
11208reg [1:0] dram_l2b0_wr_req_q_full_Ch1_wr_taken_state;
11209wire dram_l2b0_wr_q_full_Ch1_l2 = ((&dram_Ch1_l2b0_l2if_b0_wr_val) && (&dram_Ch1_l2b0_l2if_b1_wr_val));
11210always @ (posedge (cmp_clk && enabled))
11211begin
11212 if (~cmp_rst_l)
11213 begin
11214 dram_l2b0_wr_req_q_full_Ch1_wr_taken_state <= 2'b00;
11215 end
11216 else
11217 begin
11218
11219 case(dram_l2b0_wr_req_q_full_Ch1_wr_taken_state)
11220 2'b00 : begin
11221 if (dram_Ch1_l2b0_sctag_dram_wr_req && dram_l2b0_wr_q_full_Ch1_l2)
11222 dram_l2b0_wr_req_q_full_Ch1_wr_taken_state <= 2'b01;
11223 end
11224 2'b01 : begin
11225 if (dram_Ch1_l2b0_sctag_dram_wr_req && ~dram_l2b0_wr_q_full_Ch1_l2)
11226 dram_l2b0_wr_req_q_full_Ch1_wr_taken_state <= 2'b10;
11227 end
11228 2'b10 : begin
11229 if (~dram_Ch1_l2b0_sctag_dram_wr_req)
11230 dram_l2b0_wr_req_q_full_Ch1_wr_taken_state <= 2'b11;
11231 end
11232 2'b11 : begin
11233 dram_l2b0_wr_req_q_full_Ch1_wr_taken_state <= 2'b00;
11234 end
11235 default : begin
11236 dram_l2b0_wr_req_q_full_Ch1_wr_taken_state <= 2'b00;
11237 end
11238
11239 endcase
11240 end
11241end
11242reg [1:0] dram_l2b1_wr_req_q_full_Ch1_wr_taken_state;
11243wire dram_l2b1_wr_q_full_Ch1_l2 = ((&dram_Ch1_l2b1_l2if_b0_wr_val) && (&dram_Ch1_l2b1_l2if_b1_wr_val));
11244always @ (posedge (cmp_clk && enabled))
11245begin
11246 if (~cmp_rst_l)
11247 begin
11248 dram_l2b1_wr_req_q_full_Ch1_wr_taken_state <= 2'b00;
11249 end
11250 else
11251 begin
11252
11253 case(dram_l2b1_wr_req_q_full_Ch1_wr_taken_state)
11254 2'b00 : begin
11255 if (dram_Ch1_l2b1_sctag_dram_wr_req && dram_l2b1_wr_q_full_Ch1_l2)
11256 dram_l2b1_wr_req_q_full_Ch1_wr_taken_state <= 2'b01;
11257 end
11258 2'b01 : begin
11259 if (dram_Ch1_l2b1_sctag_dram_wr_req && ~dram_l2b1_wr_q_full_Ch1_l2)
11260 dram_l2b1_wr_req_q_full_Ch1_wr_taken_state <= 2'b10;
11261 end
11262 2'b10 : begin
11263 if (~dram_Ch1_l2b1_sctag_dram_wr_req)
11264 dram_l2b1_wr_req_q_full_Ch1_wr_taken_state <= 2'b11;
11265 end
11266 2'b11 : begin
11267 dram_l2b1_wr_req_q_full_Ch1_wr_taken_state <= 2'b00;
11268 end
11269 default : begin
11270 dram_l2b1_wr_req_q_full_Ch1_wr_taken_state <= 2'b00;
11271 end
11272
11273 endcase
11274 end
11275end
11276reg [1:0] dram_l2b0_wr_req_q_full_Ch2_wr_taken_state;
11277wire dram_l2b0_wr_q_full_Ch2_l2 = ((&dram_Ch2_l2b0_l2if_b0_wr_val) && (&dram_Ch2_l2b0_l2if_b1_wr_val));
11278always @ (posedge (cmp_clk && enabled))
11279begin
11280 if (~cmp_rst_l)
11281 begin
11282 dram_l2b0_wr_req_q_full_Ch2_wr_taken_state <= 2'b00;
11283 end
11284 else
11285 begin
11286
11287 case(dram_l2b0_wr_req_q_full_Ch2_wr_taken_state)
11288 2'b00 : begin
11289 if (dram_Ch2_l2b0_sctag_dram_wr_req && dram_l2b0_wr_q_full_Ch2_l2)
11290 dram_l2b0_wr_req_q_full_Ch2_wr_taken_state <= 2'b01;
11291 end
11292 2'b01 : begin
11293 if (dram_Ch2_l2b0_sctag_dram_wr_req && ~dram_l2b0_wr_q_full_Ch2_l2)
11294 dram_l2b0_wr_req_q_full_Ch2_wr_taken_state <= 2'b10;
11295 end
11296 2'b10 : begin
11297 if (~dram_Ch2_l2b0_sctag_dram_wr_req)
11298 dram_l2b0_wr_req_q_full_Ch2_wr_taken_state <= 2'b11;
11299 end
11300 2'b11 : begin
11301 dram_l2b0_wr_req_q_full_Ch2_wr_taken_state <= 2'b00;
11302 end
11303 default : begin
11304 dram_l2b0_wr_req_q_full_Ch2_wr_taken_state <= 2'b00;
11305 end
11306
11307 endcase
11308 end
11309end
11310reg [1:0] dram_l2b1_wr_req_q_full_Ch2_wr_taken_state;
11311wire dram_l2b1_wr_q_full_Ch2_l2 = ((&dram_Ch2_l2b1_l2if_b0_wr_val) && (&dram_Ch2_l2b1_l2if_b1_wr_val));
11312always @ (posedge (cmp_clk && enabled))
11313begin
11314 if (~cmp_rst_l)
11315 begin
11316 dram_l2b1_wr_req_q_full_Ch2_wr_taken_state <= 2'b00;
11317 end
11318 else
11319 begin
11320
11321 case(dram_l2b1_wr_req_q_full_Ch2_wr_taken_state)
11322 2'b00 : begin
11323 if (dram_Ch2_l2b1_sctag_dram_wr_req && dram_l2b1_wr_q_full_Ch2_l2)
11324 dram_l2b1_wr_req_q_full_Ch2_wr_taken_state <= 2'b01;
11325 end
11326 2'b01 : begin
11327 if (dram_Ch2_l2b1_sctag_dram_wr_req && ~dram_l2b1_wr_q_full_Ch2_l2)
11328 dram_l2b1_wr_req_q_full_Ch2_wr_taken_state <= 2'b10;
11329 end
11330 2'b10 : begin
11331 if (~dram_Ch2_l2b1_sctag_dram_wr_req)
11332 dram_l2b1_wr_req_q_full_Ch2_wr_taken_state <= 2'b11;
11333 end
11334 2'b11 : begin
11335 dram_l2b1_wr_req_q_full_Ch2_wr_taken_state <= 2'b00;
11336 end
11337 default : begin
11338 dram_l2b1_wr_req_q_full_Ch2_wr_taken_state <= 2'b00;
11339 end
11340
11341 endcase
11342 end
11343end
11344reg [1:0] dram_l2b0_wr_req_q_full_Ch3_wr_taken_state;
11345wire dram_l2b0_wr_q_full_Ch3_l2 = ((&dram_Ch3_l2b0_l2if_b0_wr_val) && (&dram_Ch3_l2b0_l2if_b1_wr_val));
11346always @ (posedge (cmp_clk && enabled))
11347begin
11348 if (~cmp_rst_l)
11349 begin
11350 dram_l2b0_wr_req_q_full_Ch3_wr_taken_state <= 2'b00;
11351 end
11352 else
11353 begin
11354
11355 case(dram_l2b0_wr_req_q_full_Ch3_wr_taken_state)
11356 2'b00 : begin
11357 if (dram_Ch3_l2b0_sctag_dram_wr_req && dram_l2b0_wr_q_full_Ch3_l2)
11358 dram_l2b0_wr_req_q_full_Ch3_wr_taken_state <= 2'b01;
11359 end
11360 2'b01 : begin
11361 if (dram_Ch3_l2b0_sctag_dram_wr_req && ~dram_l2b0_wr_q_full_Ch3_l2)
11362 dram_l2b0_wr_req_q_full_Ch3_wr_taken_state <= 2'b10;
11363 end
11364 2'b10 : begin
11365 if (~dram_Ch3_l2b0_sctag_dram_wr_req)
11366 dram_l2b0_wr_req_q_full_Ch3_wr_taken_state <= 2'b11;
11367 end
11368 2'b11 : begin
11369 dram_l2b0_wr_req_q_full_Ch3_wr_taken_state <= 2'b00;
11370 end
11371 default : begin
11372 dram_l2b0_wr_req_q_full_Ch3_wr_taken_state <= 2'b00;
11373 end
11374
11375 endcase
11376 end
11377end
11378reg [1:0] dram_l2b1_wr_req_q_full_Ch3_wr_taken_state;
11379wire dram_l2b1_wr_q_full_Ch3_l2 = ((&dram_Ch3_l2b1_l2if_b0_wr_val) && (&dram_Ch3_l2b1_l2if_b1_wr_val));
11380always @ (posedge (cmp_clk && enabled))
11381begin
11382 if (~cmp_rst_l)
11383 begin
11384 dram_l2b1_wr_req_q_full_Ch3_wr_taken_state <= 2'b00;
11385 end
11386 else
11387 begin
11388
11389 case(dram_l2b1_wr_req_q_full_Ch3_wr_taken_state)
11390 2'b00 : begin
11391 if (dram_Ch3_l2b1_sctag_dram_wr_req && dram_l2b1_wr_q_full_Ch3_l2)
11392 dram_l2b1_wr_req_q_full_Ch3_wr_taken_state <= 2'b01;
11393 end
11394 2'b01 : begin
11395 if (dram_Ch3_l2b1_sctag_dram_wr_req && ~dram_l2b1_wr_q_full_Ch3_l2)
11396 dram_l2b1_wr_req_q_full_Ch3_wr_taken_state <= 2'b10;
11397 end
11398 2'b10 : begin
11399 if (~dram_Ch3_l2b1_sctag_dram_wr_req)
11400 dram_l2b1_wr_req_q_full_Ch3_wr_taken_state <= 2'b11;
11401 end
11402 2'b11 : begin
11403 dram_l2b1_wr_req_q_full_Ch3_wr_taken_state <= 2'b00;
11404 end
11405 default : begin
11406 dram_l2b1_wr_req_q_full_Ch3_wr_taken_state <= 2'b00;
11407 end
11408
11409 endcase
11410 end
11411end
11412
11413
11414// ---- MONITOR FOR OBSERVING THE OLDEST RD/WR TO THE BANK IS PICKED ----
11415
11416reg [2:0] st_indx_rd_ch0_b0;
11417reg [2:0] st_indx_rd_tmp_ch0_b0;
11418reg [2:0] st_indx_wr_ch0_b0;
11419reg [2:0] st_indx_wr_tmp_ch0_b0;
11420reg [9:0] curr_bank_rd_ch0_b0;
11421reg [12:0] curr_bank_wr_ch0_b0;
11422reg flag_l2b0_rd_0;
11423reg flag_l2b0_wr_0;
11424reg [9:0] ltst_bank_l2b0_rd_0, curr_l2b0_rd_ent_0;
11425reg [12:0] ltst_bank_l2b0_wr_0, curr_l2b0_wr_ent_0;
11426
11427always @ (posedge (`MCU_CLK && enabled))
11428begin // {
11429 if (~dram_rst_l)
11430 begin
11431 end
11432 else begin // {
11433 //if (dram_Ch0_que_ras_bank_picked_en && dram_Ch0_que_b0_rd_picked && ~dram_Ch0_que_scrb_picked && ~dram_Ch0_que_b0_cmd_picked) begin
11434 // even when rd_picked is 0, when cmd is 0 , rd picked
11435// MAQ Removed this_ch_picked if (dram_Ch0_que_this_ch_picked && ~dram_Ch0_que_scrb_picked && ~dram_Ch0_que_b0_cmd_picked) begin
11436 if (dram_Ch0_que_b0_rd_picked && dram_ch0_drif_mclk_en) begin // {
11437 st_indx_rd_tmp_ch0_b0 = dram_Ch0_que_b0_index_picked;
11438 // from the index extract the bank info from the collps ques
11439 flag_l2b0_rd_0 = 0;
11440 for(i= 0;i<8;i=i+1) begin // {
11441 if(~flag_l2b0_rd_0) begin // {
11442 curr_l2b0_rd_ent_0 = dram_Ch0_l2b0_rd_colps_q[i];
11443 flag_l2b0_rd_0 = (dram_ch0_l2b0_drq_rd_queue_valid[i] && (curr_l2b0_rd_ent_0[5:3] == st_indx_rd_tmp_ch0_b0));
11444 curr_bank_rd_ch0_b0 = (flag_l2b0_rd_0) ? curr_l2b0_rd_ent_0 : 0;
11445 st_indx_rd_ch0_b0 = (flag_l2b0_rd_0) ? i : 7;
11446 end // } if
11447 end // } for
11448
11449 //curr_bank_rd_ch0_b0 = dram_Ch0_rd_colps_q[st_indx_rd_ch0_b0];
11450 for(i= st_indx_rd_ch0_b0-1;i>=0;i=i-1) begin
11451 ltst_bank_l2b0_rd_0 = dram_Ch0_l2b0_rd_colps_q[i];
11452 // chip select (phy bank) and logical bank should be same
11453
11454/*mb156858 if (({curr_bank_rd_ch0_b0[7:6], curr_bank_rd_ch0_b0[2:0]} == {ltst_bank_l2b0_rd_0[7:6], ltst_bank_l2b0_rd_0[2:0]}) && dram_ch0_l2b0_drq_rd_queue_valid[i]) begin // {
11455 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
11456 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch0_b0, i,dram_Ch0_que_b0_index_picked, ltst_bank_l2b0_rd_0);
11457 for(j= 0;j<8;j=j+1) begin
11458 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch0_l2b0_rd_colps_q[j]);
11459 end
11460 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 0);
11461 end */ // } if curr_bank
11462 end // } for st_indx
11463 end // } if rd_picked
11464
11465 //if (dram_Ch0_que_ras_bank_picked_en && dram_Ch0_que_b0_wr_picked && ~dram_Ch0_que_scrb_picked && dram_Ch0_que_b0_cmd_picked) begin
11466 // cmd picked = 1, wr picked
11467// MAQ removed this_ch_picked if (dram_Ch0_que_this_ch_picked && ~dram_Ch0_que_scrb_picked && dram_Ch0_que_b0_cmd_picked) begin
11468 if (dram_Ch0_que_b0_wr_picked && dram_ch0_drif_mclk_en) begin
11469 st_indx_wr_tmp_ch0_b0 = dram_Ch0_que_b0_index_picked;
11470 // from the index extract the bank info from the collps ques
11471 flag_l2b0_wr_0 = 0;
11472 for(i= 0;i<8;i=i+1) begin
11473 if(~flag_l2b0_wr_0) begin
11474 curr_l2b0_wr_ent_0 = dram_Ch0_l2b0_wr_colps_q[i];
11475 flag_l2b0_wr_0 = (dram_ch0_l2b0_wr_q_valids[i] && (curr_l2b0_wr_ent_0[5:3] == st_indx_wr_tmp_ch0_b0));
11476 curr_bank_wr_ch0_b0 = (flag_l2b0_wr_0) ? curr_l2b0_wr_ent_0 : 0;
11477 st_indx_wr_ch0_b0 = (flag_l2b0_wr_0) ? i : 7;
11478 end
11479 end
11480
11481 //curr_bank_wr_ch0_b0 = dram_Ch0_wr_colps_q[st_indx_wr_ch0_b0];
11482 for(i= st_indx_wr_ch0_b0-1;i>=0;i=i-1) begin
11483 ltst_bank_l2b0_wr_0 = dram_Ch0_l2b0_wr_colps_q[i];
11484
11485/*mb156858 if (({curr_bank_wr_ch0_b0[7:6], curr_bank_wr_ch0_b0[2:0]} == {ltst_bank_l2b0_wr_0[7:6], ltst_bank_l2b0_wr_0[2:0]}) && dram_ch0_l2b0_wr_q_valids[i] ) begin
11486 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
11487 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch0_b0, i,dram_Ch0_que_b0_index_picked);
11488 for(j= 0;j<8;j=j+1) begin
11489 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch0_l2b0_wr_colps_q[j]);
11490 end
11491 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch0_b0, i);
11492 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 0);
11493 end*/
11494 end
11495 end
11496
11497 end // } else
11498
11499end // } always
11500
11501reg [2:0] st_indx_rd_ch0_b1;
11502reg [2:0] st_indx_rd_tmp_ch0_b1;
11503reg [2:0] st_indx_wr_ch0_b1;
11504reg [2:0] st_indx_wr_tmp_ch0_b1;
11505reg [9:0] curr_bank_rd_ch0_b1;
11506reg [12:0] curr_bank_wr_ch0_b1;
11507reg flag_l2b1_rd_0;
11508reg flag_l2b1_wr_0;
11509reg [9:0] ltst_bank_l2b1_rd_0, curr_l2b1_rd_ent_0;
11510reg [12:0] ltst_bank_l2b1_wr_0, curr_l2b1_wr_ent_0;
11511
11512always @ (posedge (`MCU_CLK && enabled))
11513begin // {
11514 if (~dram_rst_l)
11515 begin
11516 end
11517 else begin // {
11518 //if (dram_Ch0_que_ras_bank_picked_en && dram_Ch0_que_b0_rd_picked && ~dram_Ch0_que_scrb_picked && ~dram_Ch0_que_b0_cmd_picked) begin
11519 // even when rd_picked is 0, when cmd is 0 , rd picked
11520// MAQ Removed this_ch_picked if (dram_Ch0_que_this_ch_picked && ~dram_Ch0_que_scrb_picked && ~dram_Ch0_que_b0_cmd_picked) begin
11521 if (dram_Ch0_que_b1_rd_picked && dram_ch0_drif_mclk_en) begin // {
11522 st_indx_rd_tmp_ch0_b1 = dram_Ch0_que_b0_index_picked;
11523 // from the index extract the bank info from the collps ques
11524 flag_l2b1_rd_0 = 0;
11525 for(i= 0;i<8;i=i+1) begin // {
11526 if(~flag_l2b1_rd_0) begin // {
11527 curr_l2b1_rd_ent_0 = dram_Ch0_l2b1_rd_colps_q[i];
11528 flag_l2b1_rd_0 = (dram_ch0_l2b1_drq_rd_queue_valid[i] && (curr_l2b1_rd_ent_0[5:3] == st_indx_rd_tmp_ch0_b1));
11529 curr_bank_rd_ch0_b1 = (flag_l2b1_rd_0) ? curr_l2b1_rd_ent_0 : 0;
11530 st_indx_rd_ch0_b1 = (flag_l2b1_rd_0) ? i : 7;
11531 end // } if
11532 end // } for
11533
11534 //curr_bank_rd_ch0_b1 = dram_Ch0_rd_colps_q[st_indx_rd_ch0_b1];
11535 for(i= st_indx_rd_ch0_b1-1;i>=0;i=i-1) begin
11536 ltst_bank_l2b1_rd_0 = dram_Ch0_l2b1_rd_colps_q[i];
11537 // chip select (phy bank) and logical bank should be same
11538
11539/*mb156858 if (({curr_bank_rd_ch0_b1[7:6], curr_bank_rd_ch0_b1[2:0]} == {ltst_bank_l2b1_rd_0[7:6], ltst_bank_l2b1_rd_0[2:0]}) && dram_ch0_l2b1_drq_rd_queue_valid[i]) begin // {
11540 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
11541 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch0_b1, i,dram_Ch0_que_b0_index_picked, ltst_bank_l2b1_rd_0);
11542 for(j= 0;j<8;j=j+1) begin
11543 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch0_l2b1_rd_colps_q[j]);
11544 end
11545 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 0);
11546 end */ // } if curr_bank
11547 end // } for st_indx
11548 end // } if rd_picked
11549
11550 //if (dram_Ch0_que_ras_bank_picked_en && dram_Ch0_que_b0_wr_picked && ~dram_Ch0_que_scrb_picked && dram_Ch0_que_b0_cmd_picked) begin
11551 // cmd picked = 1, wr picked
11552// MAQ removed this_ch_picked if (dram_Ch0_que_this_ch_picked && ~dram_Ch0_que_scrb_picked && dram_Ch0_que_b0_cmd_picked) begin
11553 if (dram_Ch0_que_b1_wr_picked && dram_ch0_drif_mclk_en) begin
11554 st_indx_wr_tmp_ch0_b1 = dram_Ch0_que_b0_index_picked;
11555 // from the index extract the bank info from the collps ques
11556 flag_l2b1_wr_0 = 0;
11557 for(i= 0;i<8;i=i+1) begin
11558 if(~flag_l2b1_wr_0) begin
11559 curr_l2b1_wr_ent_0 = dram_Ch0_l2b1_wr_colps_q[i];
11560 flag_l2b1_wr_0 = (dram_ch0_l2b1_wr_q_valids[i] && (curr_l2b1_wr_ent_0[5:3] == st_indx_wr_tmp_ch0_b1));
11561 curr_bank_wr_ch0_b1 = (flag_l2b1_wr_0) ? curr_l2b1_wr_ent_0 : 0;
11562 st_indx_wr_ch0_b1 = (flag_l2b1_wr_0) ? i : 7;
11563 end
11564 end
11565
11566 //curr_bank_wr_ch0_b1 = dram_Ch0_wr_colps_q[st_indx_wr_ch0_b1];
11567 for(i= st_indx_wr_ch0_b1-1;i>=0;i=i-1) begin
11568 ltst_bank_l2b1_wr_0 = dram_Ch0_l2b1_wr_colps_q[i];
11569
11570/*mb156858 if (({curr_bank_wr_ch0_b1[7:6], curr_bank_wr_ch0_b1[2:0]} == {ltst_bank_l2b1_wr_0[7:6], ltst_bank_l2b1_wr_0[2:0]}) && dram_ch0_l2b1_wr_q_valids[i] ) begin
11571 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
11572 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch0_b1, i,dram_Ch0_que_b0_index_picked);
11573 for(j= 0;j<8;j=j+1) begin
11574 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch0_l2b1_wr_colps_q[j]);
11575 end
11576 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch0_b1, i);
11577 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 0);
11578 end*/
11579 end
11580 end
11581
11582 end // } else
11583
11584end // } always
11585
11586reg [2:0] st_indx_rd_ch1_b0;
11587reg [2:0] st_indx_rd_tmp_ch1_b0;
11588reg [2:0] st_indx_wr_ch1_b0;
11589reg [2:0] st_indx_wr_tmp_ch1_b0;
11590reg [9:0] curr_bank_rd_ch1_b0;
11591reg [12:0] curr_bank_wr_ch1_b0;
11592reg flag_l2b0_rd_1;
11593reg flag_l2b0_wr_1;
11594reg [9:0] ltst_bank_l2b0_rd_1, curr_l2b0_rd_ent_1;
11595reg [12:0] ltst_bank_l2b0_wr_1, curr_l2b0_wr_ent_1;
11596
11597always @ (posedge (`MCU_CLK && enabled))
11598begin // {
11599 if (~dram_rst_l)
11600 begin
11601 end
11602 else begin // {
11603 //if (dram_Ch1_que_ras_bank_picked_en && dram_Ch1_que_b0_rd_picked && ~dram_Ch1_que_scrb_picked && ~dram_Ch1_que_b0_cmd_picked) begin
11604 // even when rd_picked is 0, when cmd is 0 , rd picked
11605// MAQ Removed this_ch_picked if (dram_Ch1_que_this_ch_picked && ~dram_Ch1_que_scrb_picked && ~dram_Ch1_que_b0_cmd_picked) begin
11606 if (dram_Ch1_que_b0_rd_picked && dram_ch1_drif_mclk_en) begin // {
11607 st_indx_rd_tmp_ch1_b0 = dram_Ch1_que_b0_index_picked;
11608 // from the index extract the bank info from the collps ques
11609 flag_l2b0_rd_1 = 0;
11610 for(i= 0;i<8;i=i+1) begin // {
11611 if(~flag_l2b0_rd_1) begin // {
11612 curr_l2b0_rd_ent_1 = dram_Ch1_l2b0_rd_colps_q[i];
11613 flag_l2b0_rd_1 = (dram_ch1_l2b0_drq_rd_queue_valid[i] && (curr_l2b0_rd_ent_1[5:3] == st_indx_rd_tmp_ch1_b0));
11614 curr_bank_rd_ch1_b0 = (flag_l2b0_rd_1) ? curr_l2b0_rd_ent_1 : 0;
11615 st_indx_rd_ch1_b0 = (flag_l2b0_rd_1) ? i : 7;
11616 end // } if
11617 end // } for
11618
11619 //curr_bank_rd_ch1_b0 = dram_Ch1_rd_colps_q[st_indx_rd_ch1_b0];
11620 for(i= st_indx_rd_ch1_b0-1;i>=0;i=i-1) begin
11621 ltst_bank_l2b0_rd_1 = dram_Ch1_l2b0_rd_colps_q[i];
11622 // chip select (phy bank) and logical bank should be same
11623
11624/*mb156858 if (({curr_bank_rd_ch1_b0[7:6], curr_bank_rd_ch1_b0[2:0]} == {ltst_bank_l2b0_rd_1[7:6], ltst_bank_l2b0_rd_1[2:0]}) && dram_ch1_l2b0_drq_rd_queue_valid[i]) begin // {
11625 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
11626 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch1_b0, i,dram_Ch1_que_b0_index_picked, ltst_bank_l2b0_rd_1);
11627 for(j= 0;j<8;j=j+1) begin
11628 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch1_l2b0_rd_colps_q[j]);
11629 end
11630 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 1);
11631 end */ // } if curr_bank
11632 end // } for st_indx
11633 end // } if rd_picked
11634
11635 //if (dram_Ch1_que_ras_bank_picked_en && dram_Ch1_que_b0_wr_picked && ~dram_Ch1_que_scrb_picked && dram_Ch1_que_b0_cmd_picked) begin
11636 // cmd picked = 1, wr picked
11637// MAQ removed this_ch_picked if (dram_Ch1_que_this_ch_picked && ~dram_Ch1_que_scrb_picked && dram_Ch1_que_b0_cmd_picked) begin
11638 if (dram_Ch1_que_b0_wr_picked && dram_ch1_drif_mclk_en) begin
11639 st_indx_wr_tmp_ch1_b0 = dram_Ch1_que_b0_index_picked;
11640 // from the index extract the bank info from the collps ques
11641 flag_l2b0_wr_1 = 0;
11642 for(i= 0;i<8;i=i+1) begin
11643 if(~flag_l2b0_wr_1) begin
11644 curr_l2b0_wr_ent_1 = dram_Ch1_l2b0_wr_colps_q[i];
11645 flag_l2b0_wr_1 = (dram_ch1_l2b0_wr_q_valids[i] && (curr_l2b0_wr_ent_1[5:3] == st_indx_wr_tmp_ch1_b0));
11646 curr_bank_wr_ch1_b0 = (flag_l2b0_wr_1) ? curr_l2b0_wr_ent_1 : 0;
11647 st_indx_wr_ch1_b0 = (flag_l2b0_wr_1) ? i : 7;
11648 end
11649 end
11650
11651 //curr_bank_wr_ch1_b0 = dram_Ch1_wr_colps_q[st_indx_wr_ch1_b0];
11652 for(i= st_indx_wr_ch1_b0-1;i>=0;i=i-1) begin
11653 ltst_bank_l2b0_wr_1 = dram_Ch1_l2b0_wr_colps_q[i];
11654
11655/*mb156858 if (({curr_bank_wr_ch1_b0[7:6], curr_bank_wr_ch1_b0[2:0]} == {ltst_bank_l2b0_wr_1[7:6], ltst_bank_l2b0_wr_1[2:0]}) && dram_ch1_l2b0_wr_q_valids[i] ) begin
11656 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
11657 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch1_b0, i,dram_Ch1_que_b0_index_picked);
11658 for(j= 0;j<8;j=j+1) begin
11659 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch1_l2b0_wr_colps_q[j]);
11660 end
11661 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch1_b0, i);
11662 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 1);
11663 end*/
11664 end
11665 end
11666
11667 end // } else
11668
11669end // } always
11670
11671reg [2:0] st_indx_rd_ch1_b1;
11672reg [2:0] st_indx_rd_tmp_ch1_b1;
11673reg [2:0] st_indx_wr_ch1_b1;
11674reg [2:0] st_indx_wr_tmp_ch1_b1;
11675reg [9:0] curr_bank_rd_ch1_b1;
11676reg [12:0] curr_bank_wr_ch1_b1;
11677reg flag_l2b1_rd_1;
11678reg flag_l2b1_wr_1;
11679reg [9:0] ltst_bank_l2b1_rd_1, curr_l2b1_rd_ent_1;
11680reg [12:0] ltst_bank_l2b1_wr_1, curr_l2b1_wr_ent_1;
11681
11682always @ (posedge (`MCU_CLK && enabled))
11683begin // {
11684 if (~dram_rst_l)
11685 begin
11686 end
11687 else begin // {
11688 //if (dram_Ch1_que_ras_bank_picked_en && dram_Ch1_que_b0_rd_picked && ~dram_Ch1_que_scrb_picked && ~dram_Ch1_que_b0_cmd_picked) begin
11689 // even when rd_picked is 0, when cmd is 0 , rd picked
11690// MAQ Removed this_ch_picked if (dram_Ch1_que_this_ch_picked && ~dram_Ch1_que_scrb_picked && ~dram_Ch1_que_b0_cmd_picked) begin
11691 if (dram_Ch1_que_b1_rd_picked && dram_ch1_drif_mclk_en) begin // {
11692 st_indx_rd_tmp_ch1_b1 = dram_Ch1_que_b0_index_picked;
11693 // from the index extract the bank info from the collps ques
11694 flag_l2b1_rd_1 = 0;
11695 for(i= 0;i<8;i=i+1) begin // {
11696 if(~flag_l2b1_rd_1) begin // {
11697 curr_l2b1_rd_ent_1 = dram_Ch1_l2b1_rd_colps_q[i];
11698 flag_l2b1_rd_1 = (dram_ch1_l2b1_drq_rd_queue_valid[i] && (curr_l2b1_rd_ent_1[5:3] == st_indx_rd_tmp_ch1_b1));
11699 curr_bank_rd_ch1_b1 = (flag_l2b1_rd_1) ? curr_l2b1_rd_ent_1 : 0;
11700 st_indx_rd_ch1_b1 = (flag_l2b1_rd_1) ? i : 7;
11701 end // } if
11702 end // } for
11703
11704 //curr_bank_rd_ch1_b1 = dram_Ch1_rd_colps_q[st_indx_rd_ch1_b1];
11705 for(i= st_indx_rd_ch1_b1-1;i>=0;i=i-1) begin
11706 ltst_bank_l2b1_rd_1 = dram_Ch1_l2b1_rd_colps_q[i];
11707 // chip select (phy bank) and logical bank should be same
11708
11709/*mb156858 if (({curr_bank_rd_ch1_b1[7:6], curr_bank_rd_ch1_b1[2:0]} == {ltst_bank_l2b1_rd_1[7:6], ltst_bank_l2b1_rd_1[2:0]}) && dram_ch1_l2b1_drq_rd_queue_valid[i]) begin // {
11710 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
11711 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch1_b1, i,dram_Ch1_que_b0_index_picked, ltst_bank_l2b1_rd_1);
11712 for(j= 0;j<8;j=j+1) begin
11713 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch1_l2b1_rd_colps_q[j]);
11714 end
11715 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 1);
11716 end */ // } if curr_bank
11717 end // } for st_indx
11718 end // } if rd_picked
11719
11720 //if (dram_Ch1_que_ras_bank_picked_en && dram_Ch1_que_b0_wr_picked && ~dram_Ch1_que_scrb_picked && dram_Ch1_que_b0_cmd_picked) begin
11721 // cmd picked = 1, wr picked
11722// MAQ removed this_ch_picked if (dram_Ch1_que_this_ch_picked && ~dram_Ch1_que_scrb_picked && dram_Ch1_que_b0_cmd_picked) begin
11723 if (dram_Ch1_que_b1_wr_picked && dram_ch1_drif_mclk_en) begin
11724 st_indx_wr_tmp_ch1_b1 = dram_Ch1_que_b0_index_picked;
11725 // from the index extract the bank info from the collps ques
11726 flag_l2b1_wr_1 = 0;
11727 for(i= 0;i<8;i=i+1) begin
11728 if(~flag_l2b1_wr_1) begin
11729 curr_l2b1_wr_ent_1 = dram_Ch1_l2b1_wr_colps_q[i];
11730 flag_l2b1_wr_1 = (dram_ch1_l2b1_wr_q_valids[i] && (curr_l2b1_wr_ent_1[5:3] == st_indx_wr_tmp_ch1_b1));
11731 curr_bank_wr_ch1_b1 = (flag_l2b1_wr_1) ? curr_l2b1_wr_ent_1 : 0;
11732 st_indx_wr_ch1_b1 = (flag_l2b1_wr_1) ? i : 7;
11733 end
11734 end
11735
11736 //curr_bank_wr_ch1_b1 = dram_Ch1_wr_colps_q[st_indx_wr_ch1_b1];
11737 for(i= st_indx_wr_ch1_b1-1;i>=0;i=i-1) begin
11738 ltst_bank_l2b1_wr_1 = dram_Ch1_l2b1_wr_colps_q[i];
11739
11740/*mb156858 if (({curr_bank_wr_ch1_b1[7:6], curr_bank_wr_ch1_b1[2:0]} == {ltst_bank_l2b1_wr_1[7:6], ltst_bank_l2b1_wr_1[2:0]}) && dram_ch1_l2b1_wr_q_valids[i] ) begin
11741 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
11742 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch1_b1, i,dram_Ch1_que_b0_index_picked);
11743 for(j= 0;j<8;j=j+1) begin
11744 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch1_l2b1_wr_colps_q[j]);
11745 end
11746 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch1_b1, i);
11747 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 1);
11748 end*/
11749 end
11750 end
11751
11752 end // } else
11753
11754end // } always
11755
11756reg [2:0] st_indx_rd_ch2_b0;
11757reg [2:0] st_indx_rd_tmp_ch2_b0;
11758reg [2:0] st_indx_wr_ch2_b0;
11759reg [2:0] st_indx_wr_tmp_ch2_b0;
11760reg [9:0] curr_bank_rd_ch2_b0;
11761reg [12:0] curr_bank_wr_ch2_b0;
11762reg flag_l2b0_rd_2;
11763reg flag_l2b0_wr_2;
11764reg [9:0] ltst_bank_l2b0_rd_2, curr_l2b0_rd_ent_2;
11765reg [12:0] ltst_bank_l2b0_wr_2, curr_l2b0_wr_ent_2;
11766
11767always @ (posedge (`MCU_CLK && enabled))
11768begin // {
11769 if (~dram_rst_l)
11770 begin
11771 end
11772 else begin // {
11773 //if (dram_Ch2_que_ras_bank_picked_en && dram_Ch2_que_b0_rd_picked && ~dram_Ch2_que_scrb_picked && ~dram_Ch2_que_b0_cmd_picked) begin
11774 // even when rd_picked is 0, when cmd is 0 , rd picked
11775// MAQ Removed this_ch_picked if (dram_Ch2_que_this_ch_picked && ~dram_Ch2_que_scrb_picked && ~dram_Ch2_que_b0_cmd_picked) begin
11776 if (dram_Ch2_que_b0_rd_picked && dram_ch2_drif_mclk_en) begin // {
11777 st_indx_rd_tmp_ch2_b0 = dram_Ch2_que_b0_index_picked;
11778 // from the index extract the bank info from the collps ques
11779 flag_l2b0_rd_2 = 0;
11780 for(i= 0;i<8;i=i+1) begin // {
11781 if(~flag_l2b0_rd_2) begin // {
11782 curr_l2b0_rd_ent_2 = dram_Ch2_l2b0_rd_colps_q[i];
11783 flag_l2b0_rd_2 = (dram_ch2_l2b0_drq_rd_queue_valid[i] && (curr_l2b0_rd_ent_2[5:3] == st_indx_rd_tmp_ch2_b0));
11784 curr_bank_rd_ch2_b0 = (flag_l2b0_rd_2) ? curr_l2b0_rd_ent_2 : 0;
11785 st_indx_rd_ch2_b0 = (flag_l2b0_rd_2) ? i : 7;
11786 end // } if
11787 end // } for
11788
11789 //curr_bank_rd_ch2_b0 = dram_Ch2_rd_colps_q[st_indx_rd_ch2_b0];
11790 for(i= st_indx_rd_ch2_b0-1;i>=0;i=i-1) begin
11791 ltst_bank_l2b0_rd_2 = dram_Ch2_l2b0_rd_colps_q[i];
11792 // chip select (phy bank) and logical bank should be same
11793
11794/*mb156858 if (({curr_bank_rd_ch2_b0[7:6], curr_bank_rd_ch2_b0[2:0]} == {ltst_bank_l2b0_rd_2[7:6], ltst_bank_l2b0_rd_2[2:0]}) && dram_ch2_l2b0_drq_rd_queue_valid[i]) begin // {
11795 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
11796 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch2_b0, i,dram_Ch2_que_b0_index_picked, ltst_bank_l2b0_rd_2);
11797 for(j= 0;j<8;j=j+1) begin
11798 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch2_l2b0_rd_colps_q[j]);
11799 end
11800 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 2);
11801 end */ // } if curr_bank
11802 end // } for st_indx
11803 end // } if rd_picked
11804
11805 //if (dram_Ch2_que_ras_bank_picked_en && dram_Ch2_que_b0_wr_picked && ~dram_Ch2_que_scrb_picked && dram_Ch2_que_b0_cmd_picked) begin
11806 // cmd picked = 1, wr picked
11807// MAQ removed this_ch_picked if (dram_Ch2_que_this_ch_picked && ~dram_Ch2_que_scrb_picked && dram_Ch2_que_b0_cmd_picked) begin
11808 if (dram_Ch2_que_b0_wr_picked && dram_ch2_drif_mclk_en) begin
11809 st_indx_wr_tmp_ch2_b0 = dram_Ch2_que_b0_index_picked;
11810 // from the index extract the bank info from the collps ques
11811 flag_l2b0_wr_2 = 0;
11812 for(i= 0;i<8;i=i+1) begin
11813 if(~flag_l2b0_wr_2) begin
11814 curr_l2b0_wr_ent_2 = dram_Ch2_l2b0_wr_colps_q[i];
11815 flag_l2b0_wr_2 = (dram_ch2_l2b0_wr_q_valids[i] && (curr_l2b0_wr_ent_2[5:3] == st_indx_wr_tmp_ch2_b0));
11816 curr_bank_wr_ch2_b0 = (flag_l2b0_wr_2) ? curr_l2b0_wr_ent_2 : 0;
11817 st_indx_wr_ch2_b0 = (flag_l2b0_wr_2) ? i : 7;
11818 end
11819 end
11820
11821 //curr_bank_wr_ch2_b0 = dram_Ch2_wr_colps_q[st_indx_wr_ch2_b0];
11822 for(i= st_indx_wr_ch2_b0-1;i>=0;i=i-1) begin
11823 ltst_bank_l2b0_wr_2 = dram_Ch2_l2b0_wr_colps_q[i];
11824
11825/*mb156858 if (({curr_bank_wr_ch2_b0[7:6], curr_bank_wr_ch2_b0[2:0]} == {ltst_bank_l2b0_wr_2[7:6], ltst_bank_l2b0_wr_2[2:0]}) && dram_ch2_l2b0_wr_q_valids[i] ) begin
11826 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
11827 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch2_b0, i,dram_Ch2_que_b0_index_picked);
11828 for(j= 0;j<8;j=j+1) begin
11829 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch2_l2b0_wr_colps_q[j]);
11830 end
11831 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch2_b0, i);
11832 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 2);
11833 end*/
11834 end
11835 end
11836
11837 end // } else
11838
11839end // } always
11840
11841reg [2:0] st_indx_rd_ch2_b1;
11842reg [2:0] st_indx_rd_tmp_ch2_b1;
11843reg [2:0] st_indx_wr_ch2_b1;
11844reg [2:0] st_indx_wr_tmp_ch2_b1;
11845reg [9:0] curr_bank_rd_ch2_b1;
11846reg [12:0] curr_bank_wr_ch2_b1;
11847reg flag_l2b1_rd_2;
11848reg flag_l2b1_wr_2;
11849reg [9:0] ltst_bank_l2b1_rd_2, curr_l2b1_rd_ent_2;
11850reg [12:0] ltst_bank_l2b1_wr_2, curr_l2b1_wr_ent_2;
11851
11852always @ (posedge (`MCU_CLK && enabled))
11853begin // {
11854 if (~dram_rst_l)
11855 begin
11856 end
11857 else begin // {
11858 //if (dram_Ch2_que_ras_bank_picked_en && dram_Ch2_que_b0_rd_picked && ~dram_Ch2_que_scrb_picked && ~dram_Ch2_que_b0_cmd_picked) begin
11859 // even when rd_picked is 0, when cmd is 0 , rd picked
11860// MAQ Removed this_ch_picked if (dram_Ch2_que_this_ch_picked && ~dram_Ch2_que_scrb_picked && ~dram_Ch2_que_b0_cmd_picked) begin
11861 if (dram_Ch2_que_b1_rd_picked && dram_ch2_drif_mclk_en) begin // {
11862 st_indx_rd_tmp_ch2_b1 = dram_Ch2_que_b0_index_picked;
11863 // from the index extract the bank info from the collps ques
11864 flag_l2b1_rd_2 = 0;
11865 for(i= 0;i<8;i=i+1) begin // {
11866 if(~flag_l2b1_rd_2) begin // {
11867 curr_l2b1_rd_ent_2 = dram_Ch2_l2b1_rd_colps_q[i];
11868 flag_l2b1_rd_2 = (dram_ch2_l2b1_drq_rd_queue_valid[i] && (curr_l2b1_rd_ent_2[5:3] == st_indx_rd_tmp_ch2_b1));
11869 curr_bank_rd_ch2_b1 = (flag_l2b1_rd_2) ? curr_l2b1_rd_ent_2 : 0;
11870 st_indx_rd_ch2_b1 = (flag_l2b1_rd_2) ? i : 7;
11871 end // } if
11872 end // } for
11873
11874 //curr_bank_rd_ch2_b1 = dram_Ch2_rd_colps_q[st_indx_rd_ch2_b1];
11875 for(i= st_indx_rd_ch2_b1-1;i>=0;i=i-1) begin
11876 ltst_bank_l2b1_rd_2 = dram_Ch2_l2b1_rd_colps_q[i];
11877 // chip select (phy bank) and logical bank should be same
11878
11879/*mb156858 if (({curr_bank_rd_ch2_b1[7:6], curr_bank_rd_ch2_b1[2:0]} == {ltst_bank_l2b1_rd_2[7:6], ltst_bank_l2b1_rd_2[2:0]}) && dram_ch2_l2b1_drq_rd_queue_valid[i]) begin // {
11880 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
11881 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch2_b1, i,dram_Ch2_que_b0_index_picked, ltst_bank_l2b1_rd_2);
11882 for(j= 0;j<8;j=j+1) begin
11883 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch2_l2b1_rd_colps_q[j]);
11884 end
11885 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 2);
11886 end */ // } if curr_bank
11887 end // } for st_indx
11888 end // } if rd_picked
11889
11890 //if (dram_Ch2_que_ras_bank_picked_en && dram_Ch2_que_b0_wr_picked && ~dram_Ch2_que_scrb_picked && dram_Ch2_que_b0_cmd_picked) begin
11891 // cmd picked = 1, wr picked
11892// MAQ removed this_ch_picked if (dram_Ch2_que_this_ch_picked && ~dram_Ch2_que_scrb_picked && dram_Ch2_que_b0_cmd_picked) begin
11893 if (dram_Ch2_que_b1_wr_picked && dram_ch2_drif_mclk_en) begin
11894 st_indx_wr_tmp_ch2_b1 = dram_Ch2_que_b0_index_picked;
11895 // from the index extract the bank info from the collps ques
11896 flag_l2b1_wr_2 = 0;
11897 for(i= 0;i<8;i=i+1) begin
11898 if(~flag_l2b1_wr_2) begin
11899 curr_l2b1_wr_ent_2 = dram_Ch2_l2b1_wr_colps_q[i];
11900 flag_l2b1_wr_2 = (dram_ch2_l2b1_wr_q_valids[i] && (curr_l2b1_wr_ent_2[5:3] == st_indx_wr_tmp_ch2_b1));
11901 curr_bank_wr_ch2_b1 = (flag_l2b1_wr_2) ? curr_l2b1_wr_ent_2 : 0;
11902 st_indx_wr_ch2_b1 = (flag_l2b1_wr_2) ? i : 7;
11903 end
11904 end
11905
11906 //curr_bank_wr_ch2_b1 = dram_Ch2_wr_colps_q[st_indx_wr_ch2_b1];
11907 for(i= st_indx_wr_ch2_b1-1;i>=0;i=i-1) begin
11908 ltst_bank_l2b1_wr_2 = dram_Ch2_l2b1_wr_colps_q[i];
11909
11910/*mb156858 if (({curr_bank_wr_ch2_b1[7:6], curr_bank_wr_ch2_b1[2:0]} == {ltst_bank_l2b1_wr_2[7:6], ltst_bank_l2b1_wr_2[2:0]}) && dram_ch2_l2b1_wr_q_valids[i] ) begin
11911 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
11912 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch2_b1, i,dram_Ch2_que_b0_index_picked);
11913 for(j= 0;j<8;j=j+1) begin
11914 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch2_l2b1_wr_colps_q[j]);
11915 end
11916 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch2_b1, i);
11917 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 2);
11918 end*/
11919 end
11920 end
11921
11922 end // } else
11923
11924end // } always
11925
11926reg [2:0] st_indx_rd_ch3_b0;
11927reg [2:0] st_indx_rd_tmp_ch3_b0;
11928reg [2:0] st_indx_wr_ch3_b0;
11929reg [2:0] st_indx_wr_tmp_ch3_b0;
11930reg [9:0] curr_bank_rd_ch3_b0;
11931reg [12:0] curr_bank_wr_ch3_b0;
11932reg flag_l2b0_rd_3;
11933reg flag_l2b0_wr_3;
11934reg [9:0] ltst_bank_l2b0_rd_3, curr_l2b0_rd_ent_3;
11935reg [12:0] ltst_bank_l2b0_wr_3, curr_l2b0_wr_ent_3;
11936
11937always @ (posedge (`MCU_CLK && enabled))
11938begin // {
11939 if (~dram_rst_l)
11940 begin
11941 end
11942 else begin // {
11943 //if (dram_Ch3_que_ras_bank_picked_en && dram_Ch3_que_b0_rd_picked && ~dram_Ch3_que_scrb_picked && ~dram_Ch3_que_b0_cmd_picked) begin
11944 // even when rd_picked is 0, when cmd is 0 , rd picked
11945// MAQ Removed this_ch_picked if (dram_Ch3_que_this_ch_picked && ~dram_Ch3_que_scrb_picked && ~dram_Ch3_que_b0_cmd_picked) begin
11946 if (dram_Ch3_que_b0_rd_picked && dram_ch3_drif_mclk_en) begin // {
11947 st_indx_rd_tmp_ch3_b0 = dram_Ch3_que_b0_index_picked;
11948 // from the index extract the bank info from the collps ques
11949 flag_l2b0_rd_3 = 0;
11950 for(i= 0;i<8;i=i+1) begin // {
11951 if(~flag_l2b0_rd_3) begin // {
11952 curr_l2b0_rd_ent_3 = dram_Ch3_l2b0_rd_colps_q[i];
11953 flag_l2b0_rd_3 = (dram_ch3_l2b0_drq_rd_queue_valid[i] && (curr_l2b0_rd_ent_3[5:3] == st_indx_rd_tmp_ch3_b0));
11954 curr_bank_rd_ch3_b0 = (flag_l2b0_rd_3) ? curr_l2b0_rd_ent_3 : 0;
11955 st_indx_rd_ch3_b0 = (flag_l2b0_rd_3) ? i : 7;
11956 end // } if
11957 end // } for
11958
11959 //curr_bank_rd_ch3_b0 = dram_Ch3_rd_colps_q[st_indx_rd_ch3_b0];
11960 for(i= st_indx_rd_ch3_b0-1;i>=0;i=i-1) begin
11961 ltst_bank_l2b0_rd_3 = dram_Ch3_l2b0_rd_colps_q[i];
11962 // chip select (phy bank) and logical bank should be same
11963
11964/*mb156858 if (({curr_bank_rd_ch3_b0[7:6], curr_bank_rd_ch3_b0[2:0]} == {ltst_bank_l2b0_rd_3[7:6], ltst_bank_l2b0_rd_3[2:0]}) && dram_ch3_l2b0_drq_rd_queue_valid[i]) begin // {
11965 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
11966 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch3_b0, i,dram_Ch3_que_b0_index_picked, ltst_bank_l2b0_rd_3);
11967 for(j= 0;j<8;j=j+1) begin
11968 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch3_l2b0_rd_colps_q[j]);
11969 end
11970 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 3);
11971 end */ // } if curr_bank
11972 end // } for st_indx
11973 end // } if rd_picked
11974
11975 //if (dram_Ch3_que_ras_bank_picked_en && dram_Ch3_que_b0_wr_picked && ~dram_Ch3_que_scrb_picked && dram_Ch3_que_b0_cmd_picked) begin
11976 // cmd picked = 1, wr picked
11977// MAQ removed this_ch_picked if (dram_Ch3_que_this_ch_picked && ~dram_Ch3_que_scrb_picked && dram_Ch3_que_b0_cmd_picked) begin
11978 if (dram_Ch3_que_b0_wr_picked && dram_ch3_drif_mclk_en) begin
11979 st_indx_wr_tmp_ch3_b0 = dram_Ch3_que_b0_index_picked;
11980 // from the index extract the bank info from the collps ques
11981 flag_l2b0_wr_3 = 0;
11982 for(i= 0;i<8;i=i+1) begin
11983 if(~flag_l2b0_wr_3) begin
11984 curr_l2b0_wr_ent_3 = dram_Ch3_l2b0_wr_colps_q[i];
11985 flag_l2b0_wr_3 = (dram_ch3_l2b0_wr_q_valids[i] && (curr_l2b0_wr_ent_3[5:3] == st_indx_wr_tmp_ch3_b0));
11986 curr_bank_wr_ch3_b0 = (flag_l2b0_wr_3) ? curr_l2b0_wr_ent_3 : 0;
11987 st_indx_wr_ch3_b0 = (flag_l2b0_wr_3) ? i : 7;
11988 end
11989 end
11990
11991 //curr_bank_wr_ch3_b0 = dram_Ch3_wr_colps_q[st_indx_wr_ch3_b0];
11992 for(i= st_indx_wr_ch3_b0-1;i>=0;i=i-1) begin
11993 ltst_bank_l2b0_wr_3 = dram_Ch3_l2b0_wr_colps_q[i];
11994
11995/*mb156858 if (({curr_bank_wr_ch3_b0[7:6], curr_bank_wr_ch3_b0[2:0]} == {ltst_bank_l2b0_wr_3[7:6], ltst_bank_l2b0_wr_3[2:0]}) && dram_ch3_l2b0_wr_q_valids[i] ) begin
11996 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
11997 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch3_b0, i,dram_Ch3_que_b0_index_picked);
11998 for(j= 0;j<8;j=j+1) begin
11999 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch3_l2b0_wr_colps_q[j]);
12000 end
12001 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch3_b0, i);
12002 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 3);
12003 end*/
12004 end
12005 end
12006
12007 end // } else
12008
12009end // } always
12010
12011reg [2:0] st_indx_rd_ch3_b1;
12012reg [2:0] st_indx_rd_tmp_ch3_b1;
12013reg [2:0] st_indx_wr_ch3_b1;
12014reg [2:0] st_indx_wr_tmp_ch3_b1;
12015reg [9:0] curr_bank_rd_ch3_b1;
12016reg [12:0] curr_bank_wr_ch3_b1;
12017reg flag_l2b1_rd_3;
12018reg flag_l2b1_wr_3;
12019reg [9:0] ltst_bank_l2b1_rd_3, curr_l2b1_rd_ent_3;
12020reg [12:0] ltst_bank_l2b1_wr_3, curr_l2b1_wr_ent_3;
12021
12022always @ (posedge (`MCU_CLK && enabled))
12023begin // {
12024 if (~dram_rst_l)
12025 begin
12026 end
12027 else begin // {
12028 //if (dram_Ch3_que_ras_bank_picked_en && dram_Ch3_que_b0_rd_picked && ~dram_Ch3_que_scrb_picked && ~dram_Ch3_que_b0_cmd_picked) begin
12029 // even when rd_picked is 0, when cmd is 0 , rd picked
12030// MAQ Removed this_ch_picked if (dram_Ch3_que_this_ch_picked && ~dram_Ch3_que_scrb_picked && ~dram_Ch3_que_b0_cmd_picked) begin
12031 if (dram_Ch3_que_b1_rd_picked && dram_ch3_drif_mclk_en) begin // {
12032 st_indx_rd_tmp_ch3_b1 = dram_Ch3_que_b0_index_picked;
12033 // from the index extract the bank info from the collps ques
12034 flag_l2b1_rd_3 = 0;
12035 for(i= 0;i<8;i=i+1) begin // {
12036 if(~flag_l2b1_rd_3) begin // {
12037 curr_l2b1_rd_ent_3 = dram_Ch3_l2b1_rd_colps_q[i];
12038 flag_l2b1_rd_3 = (dram_ch3_l2b1_drq_rd_queue_valid[i] && (curr_l2b1_rd_ent_3[5:3] == st_indx_rd_tmp_ch3_b1));
12039 curr_bank_rd_ch3_b1 = (flag_l2b1_rd_3) ? curr_l2b1_rd_ent_3 : 0;
12040 st_indx_rd_ch3_b1 = (flag_l2b1_rd_3) ? i : 7;
12041 end // } if
12042 end // } for
12043
12044 //curr_bank_rd_ch3_b1 = dram_Ch3_rd_colps_q[st_indx_rd_ch3_b1];
12045 for(i= st_indx_rd_ch3_b1-1;i>=0;i=i-1) begin
12046 ltst_bank_l2b1_rd_3 = dram_Ch3_l2b1_rd_colps_q[i];
12047 // chip select (phy bank) and logical bank should be same
12048
12049/*mb156858 if (({curr_bank_rd_ch3_b1[7:6], curr_bank_rd_ch3_b1[2:0]} == {ltst_bank_l2b1_rd_3[7:6], ltst_bank_l2b1_rd_3[2:0]}) && dram_ch3_l2b1_drq_rd_queue_valid[i]) begin // {
12050 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
12051 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x, rd_colps_q = %x", $time, st_indx_rd_ch3_b1, i,dram_Ch3_que_b0_index_picked, ltst_bank_l2b1_rd_3);
12052 for(j= 0;j<8;j=j+1) begin
12053 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch3_l2b1_rd_colps_q[j]);
12054 end
12055 finish_test(" OLD_ENTRY_PEND (RD Q) : Oldest pending entry in the Q not selected ", 3);
12056 end */ // } if curr_bank
12057 end // } for st_indx
12058 end // } if rd_picked
12059
12060 //if (dram_Ch3_que_ras_bank_picked_en && dram_Ch3_que_b0_wr_picked && ~dram_Ch3_que_scrb_picked && dram_Ch3_que_b0_cmd_picked) begin
12061 // cmd picked = 1, wr picked
12062// MAQ removed this_ch_picked if (dram_Ch3_que_this_ch_picked && ~dram_Ch3_que_scrb_picked && dram_Ch3_que_b0_cmd_picked) begin
12063 if (dram_Ch3_que_b1_wr_picked && dram_ch3_drif_mclk_en) begin
12064 st_indx_wr_tmp_ch3_b1 = dram_Ch3_que_b0_index_picked;
12065 // from the index extract the bank info from the collps ques
12066 flag_l2b1_wr_3 = 0;
12067 for(i= 0;i<8;i=i+1) begin
12068 if(~flag_l2b1_wr_3) begin
12069 curr_l2b1_wr_ent_3 = dram_Ch3_l2b1_wr_colps_q[i];
12070 flag_l2b1_wr_3 = (dram_ch3_l2b1_wr_q_valids[i] && (curr_l2b1_wr_ent_3[5:3] == st_indx_wr_tmp_ch3_b1));
12071 curr_bank_wr_ch3_b1 = (flag_l2b1_wr_3) ? curr_l2b1_wr_ent_3 : 0;
12072 st_indx_wr_ch3_b1 = (flag_l2b1_wr_3) ? i : 7;
12073 end
12074 end
12075
12076 //curr_bank_wr_ch3_b1 = dram_Ch3_wr_colps_q[st_indx_wr_ch3_b1];
12077 for(i= st_indx_wr_ch3_b1-1;i>=0;i=i-1) begin
12078 ltst_bank_l2b1_wr_3 = dram_Ch3_l2b1_wr_colps_q[i];
12079
12080/*mb156858 if (({curr_bank_wr_ch3_b1[7:6], curr_bank_wr_ch3_b1[2:0]} == {ltst_bank_l2b1_wr_3[7:6], ltst_bank_l2b1_wr_3[2:0]}) && dram_ch3_l2b1_wr_q_valids[i] ) begin
12081 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
12082 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d, index picked = %x", $time, st_indx_wr_ch3_b1, i,dram_Ch3_que_b0_index_picked);
12083 for(j= 0;j<8;j=j+1) begin
12084 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d collapsing fifo entry[%d] = %x", $time, j, dram_Ch3_l2b1_wr_colps_q[j]);
12085 end
12086 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d select index = %d and index = %d", $time, st_indx_wr_ch3_b1, i);
12087 finish_test(" OLD_ENTRY_PEND (WR Q) : Oldest pending entry in the Q not selected ", 3);
12088 end*/
12089 end
12090 end
12091
12092 end // } else
12093
12094end // } always
12095
12096
12097
12098// ---- Monitor Rd sequencing : when wr to same address pending , rd (same address as wr) should not be issued ----
12099
12100
12101reg [39:0] l2b0_rd_ent0_0;
12102always @(posedge dram_Ch0_l2b0_wr_q_0[39])
12103if (enabled)
12104begin
12105 for (i=0;i<8;i=i+1) begin
12106 l2b0_rd_ent0_0 = dram_Ch0_l2b0_rd_q[i];
12107// MAQ N2 if((dram_Ch0_l2b0_wr_q_0[35:0] == l2b0_rd_ent0_0[35:0]) && l2b0_rd_ent0_0[39]) begin
12108 if((dram_Ch0_l2b0_wr_q_0[35:0] == l2b0_rd_ent0_0[35:0]) &&
12109 l2b0_rd_ent0_0[39] &&
12110 dram_ch0_l2b0_rd_q_valids[i] &&
12111 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12112 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12113 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b0_rd_ent0_0[34:0]);
12114
12115 finish_test("RD/WR Sequencing violation ", 0);
12116 end
12117 end
12118end
12119
12120reg [39:0] l2b0_rd_ent0_1;
12121always @(posedge dram_Ch0_l2b0_wr_q_1[39])
12122if (enabled)
12123begin
12124 for (i=0;i<8;i=i+1) begin
12125 l2b0_rd_ent0_1 = dram_Ch0_l2b0_rd_q[i];
12126// MAQ N2 if((dram_Ch0_l2b0_wr_q_1[35:0] == l2b0_rd_ent0_1[35:0]) && l2b0_rd_ent0_1[39]) begin
12127 if((dram_Ch0_l2b0_wr_q_1[35:0] == l2b0_rd_ent0_1[35:0]) &&
12128 l2b0_rd_ent0_1[39] &&
12129 dram_ch0_l2b0_rd_q_valids[i] &&
12130 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12131 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12132 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b0_rd_ent0_1[34:0]);
12133
12134 finish_test("RD/WR Sequencing violation ", 0);
12135 end
12136 end
12137end
12138
12139reg [39:0] l2b0_rd_ent0_2;
12140always @(posedge dram_Ch0_l2b0_wr_q_2[39])
12141if (enabled)
12142begin
12143 for (i=0;i<8;i=i+1) begin
12144 l2b0_rd_ent0_2 = dram_Ch0_l2b0_rd_q[i];
12145// MAQ N2 if((dram_Ch0_l2b0_wr_q_2[35:0] == l2b0_rd_ent0_2[35:0]) && l2b0_rd_ent0_2[39]) begin
12146 if((dram_Ch0_l2b0_wr_q_2[35:0] == l2b0_rd_ent0_2[35:0]) &&
12147 l2b0_rd_ent0_2[39] &&
12148 dram_ch0_l2b0_rd_q_valids[i] &&
12149 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12150 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12151 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b0_rd_ent0_2[34:0]);
12152
12153 finish_test("RD/WR Sequencing violation ", 0);
12154 end
12155 end
12156end
12157
12158reg [39:0] l2b0_rd_ent0_3;
12159always @(posedge dram_Ch0_l2b0_wr_q_3[39])
12160if (enabled)
12161begin
12162 for (i=0;i<8;i=i+1) begin
12163 l2b0_rd_ent0_3 = dram_Ch0_l2b0_rd_q[i];
12164// MAQ N2 if((dram_Ch0_l2b0_wr_q_3[35:0] == l2b0_rd_ent0_3[35:0]) && l2b0_rd_ent0_3[39]) begin
12165 if((dram_Ch0_l2b0_wr_q_3[35:0] == l2b0_rd_ent0_3[35:0]) &&
12166 l2b0_rd_ent0_3[39] &&
12167 dram_ch0_l2b0_rd_q_valids[i] &&
12168 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12169 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12170 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b0_rd_ent0_3[34:0]);
12171
12172 finish_test("RD/WR Sequencing violation ", 0);
12173 end
12174 end
12175end
12176
12177reg [39:0] l2b0_rd_ent0_4;
12178always @(posedge dram_Ch0_l2b0_wr_q_4[39])
12179if (enabled)
12180begin
12181 for (i=0;i<8;i=i+1) begin
12182 l2b0_rd_ent0_4 = dram_Ch0_l2b0_rd_q[i];
12183// MAQ N2 if((dram_Ch0_l2b0_wr_q_4[35:0] == l2b0_rd_ent0_4[35:0]) && l2b0_rd_ent0_4[39]) begin
12184 if((dram_Ch0_l2b0_wr_q_4[35:0] == l2b0_rd_ent0_4[35:0]) &&
12185 l2b0_rd_ent0_4[39] &&
12186 dram_ch0_l2b0_rd_q_valids[i] &&
12187 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12188 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12189 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b0_rd_ent0_4[34:0]);
12190
12191 finish_test("RD/WR Sequencing violation ", 0);
12192 end
12193 end
12194end
12195
12196reg [39:0] l2b0_rd_ent0_5;
12197always @(posedge dram_Ch0_l2b0_wr_q_5[39])
12198if (enabled)
12199begin
12200 for (i=0;i<8;i=i+1) begin
12201 l2b0_rd_ent0_5 = dram_Ch0_l2b0_rd_q[i];
12202// MAQ N2 if((dram_Ch0_l2b0_wr_q_5[35:0] == l2b0_rd_ent0_5[35:0]) && l2b0_rd_ent0_5[39]) begin
12203 if((dram_Ch0_l2b0_wr_q_5[35:0] == l2b0_rd_ent0_5[35:0]) &&
12204 l2b0_rd_ent0_5[39] &&
12205 dram_ch0_l2b0_rd_q_valids[i] &&
12206 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12207 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12208 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b0_rd_ent0_5[34:0]);
12209
12210 finish_test("RD/WR Sequencing violation ", 0);
12211 end
12212 end
12213end
12214
12215reg [39:0] l2b0_rd_ent0_6;
12216always @(posedge dram_Ch0_l2b0_wr_q_6[39])
12217if (enabled)
12218begin
12219 for (i=0;i<8;i=i+1) begin
12220 l2b0_rd_ent0_6 = dram_Ch0_l2b0_rd_q[i];
12221// MAQ N2 if((dram_Ch0_l2b0_wr_q_6[35:0] == l2b0_rd_ent0_6[35:0]) && l2b0_rd_ent0_6[39]) begin
12222 if((dram_Ch0_l2b0_wr_q_6[35:0] == l2b0_rd_ent0_6[35:0]) &&
12223 l2b0_rd_ent0_6[39] &&
12224 dram_ch0_l2b0_rd_q_valids[i] &&
12225 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12226 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12227 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b0_rd_ent0_6[34:0]);
12228
12229 finish_test("RD/WR Sequencing violation ", 0);
12230 end
12231 end
12232end
12233
12234reg [39:0] l2b0_rd_ent0_7;
12235always @(posedge dram_Ch0_l2b0_wr_q_7[39])
12236if (enabled)
12237begin
12238 for (i=0;i<8;i=i+1) begin
12239 l2b0_rd_ent0_7 = dram_Ch0_l2b0_rd_q[i];
12240// MAQ N2 if((dram_Ch0_l2b0_wr_q_7[35:0] == l2b0_rd_ent0_7[35:0]) && l2b0_rd_ent0_7[39]) begin
12241 if((dram_Ch0_l2b0_wr_q_7[35:0] == l2b0_rd_ent0_7[35:0]) &&
12242 l2b0_rd_ent0_7[39] &&
12243 dram_ch0_l2b0_rd_q_valids[i] &&
12244 ~dram_ch0_l2b0_rd_q_addr_err[i]) begin
12245 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
12246 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b0_rd_ent0_7[34:0]);
12247
12248 finish_test("RD/WR Sequencing violation ", 0);
12249 end
12250 end
12251end
12252
12253reg [39:0] l2b1_rd_ent0_0;
12254always @(posedge dram_Ch0_l2b1_wr_q_0[39])
12255if (enabled)
12256begin
12257 for (i=0;i<8;i=i+1) begin
12258 l2b1_rd_ent0_0 = dram_Ch0_l2b1_rd_q[i];
12259// MAQ N2 if((dram_Ch0_l2b1_wr_q_0[35:0] == l2b1_rd_ent0_0[35:0]) && l2b1_rd_ent0_0[39]) begin
12260 if((dram_Ch0_l2b1_wr_q_0[35:0] == l2b1_rd_ent0_0[35:0]) &&
12261 l2b1_rd_ent0_0[39] &&
12262 dram_ch0_l2b1_rd_q_valids[i] &&
12263 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12264 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12265 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b1_rd_ent0_0[34:0]);
12266
12267 finish_test("RD/WR Sequencing violation ", 0);
12268 end
12269 end
12270end
12271reg [39:0] l2b1_rd_ent0_1;
12272always @(posedge dram_Ch0_l2b1_wr_q_1[39])
12273if (enabled)
12274begin
12275 for (i=0;i<8;i=i+1) begin
12276 l2b1_rd_ent0_1 = dram_Ch0_l2b1_rd_q[i];
12277// MAQ N2 if((dram_Ch0_l2b1_wr_q_1[35:0] == l2b1_rd_ent0_1[35:0]) && l2b1_rd_ent0_1[39]) begin
12278 if((dram_Ch0_l2b1_wr_q_1[35:0] == l2b1_rd_ent0_1[35:0]) &&
12279 l2b1_rd_ent0_1[39] &&
12280 dram_ch0_l2b1_rd_q_valids[i] &&
12281 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12282 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12283 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b1_rd_ent0_1[34:0]);
12284
12285 finish_test("RD/WR Sequencing violation ", 0);
12286 end
12287 end
12288end
12289
12290reg [39:0] l2b1_rd_ent0_2;
12291always @(posedge dram_Ch0_l2b1_wr_q_2[39])
12292if (enabled)
12293begin
12294 for (i=0;i<8;i=i+1) begin
12295 l2b1_rd_ent0_2 = dram_Ch0_l2b1_rd_q[i];
12296// MAQ N2 if((dram_Ch0_l2b1_wr_q_2[35:0] == l2b1_rd_ent0_2[35:0]) && l2b1_rd_ent0_2[39]) begin
12297 if((dram_Ch0_l2b1_wr_q_2[35:0] == l2b1_rd_ent0_2[35:0]) &&
12298 l2b1_rd_ent0_2[39] &&
12299 dram_ch0_l2b1_rd_q_valids[i] &&
12300 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12301 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12302 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b1_rd_ent0_2[34:0]);
12303
12304 finish_test("RD/WR Sequencing violation ", 0);
12305 end
12306 end
12307end
12308
12309reg [39:0] l2b1_rd_ent0_3;
12310always @(posedge dram_Ch0_l2b1_wr_q_3[39])
12311if (enabled)
12312begin
12313 for (i=0;i<8;i=i+1) begin
12314 l2b1_rd_ent0_3 = dram_Ch0_l2b1_rd_q[i];
12315// MAQ N2 if((dram_Ch0_l2b1_wr_q_3[35:0] == l2b1_rd_ent0_3[35:0]) && l2b1_rd_ent0_3[39]) begin
12316 if((dram_Ch0_l2b1_wr_q_3[35:0] == l2b1_rd_ent0_3[35:0]) &&
12317 l2b1_rd_ent0_3[39] &&
12318 dram_ch0_l2b1_rd_q_valids[i] &&
12319 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12320 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12321 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b1_rd_ent0_3[34:0]);
12322
12323 finish_test("RD/WR Sequencing violation ", 0);
12324 end
12325 end
12326end
12327
12328reg [39:0] l2b1_rd_ent0_4;
12329always @(posedge dram_Ch0_l2b1_wr_q_4[39])
12330if (enabled)
12331begin
12332 for (i=0;i<8;i=i+1) begin
12333 l2b1_rd_ent0_4 = dram_Ch0_l2b1_rd_q[i];
12334// MAQ N2 if((dram_Ch0_l2b1_wr_q_4[35:0] == l2b1_rd_ent0_4[35:0]) && l2b1_rd_ent0_4[39]) begin
12335 if((dram_Ch0_l2b1_wr_q_4[35:0] == l2b1_rd_ent0_4[35:0]) &&
12336 l2b1_rd_ent0_4[39] &&
12337 dram_ch0_l2b1_rd_q_valids[i] &&
12338 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12339 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12340 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b1_rd_ent0_4[34:0]);
12341
12342 finish_test("RD/WR Sequencing violation ", 0);
12343 end
12344 end
12345end
12346
12347reg [39:0] l2b1_rd_ent0_5;
12348always @(posedge dram_Ch0_l2b1_wr_q_5[39])
12349if (enabled)
12350begin
12351 for (i=0;i<8;i=i+1) begin
12352 l2b1_rd_ent0_5 = dram_Ch0_l2b1_rd_q[i];
12353// MAQ N2 if((dram_Ch0_l2b1_wr_q_5[35:0] == l2b1_rd_ent0_5[35:0]) && l2b1_rd_ent0_5[39]) begin
12354 if((dram_Ch0_l2b1_wr_q_5[35:0] == l2b1_rd_ent0_5[35:0]) &&
12355 l2b1_rd_ent0_5[39] &&
12356 dram_ch0_l2b1_rd_q_valids[i] &&
12357 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12358 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12359 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b1_rd_ent0_5[34:0]);
12360
12361 finish_test("RD/WR Sequencing violation ", 0);
12362 end
12363 end
12364end
12365
12366reg [39:0] l2b1_rd_ent0_6;
12367always @(posedge dram_Ch0_l2b1_wr_q_6[39])
12368if (enabled)
12369begin
12370 for (i=0;i<8;i=i+1) begin
12371 l2b1_rd_ent0_6 = dram_Ch0_l2b1_rd_q[i];
12372// MAQ N2 if((dram_Ch0_l2b1_wr_q_6[35:0] == l2b1_rd_ent0_6[35:0]) && l2b1_rd_ent0_6[39]) begin
12373 if((dram_Ch0_l2b1_wr_q_6[35:0] == l2b1_rd_ent0_6[35:0]) &&
12374 l2b1_rd_ent0_6[39] &&
12375 dram_ch0_l2b1_rd_q_valids[i] &&
12376 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12377 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12378 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b1_rd_ent0_6[34:0]);
12379
12380 finish_test("RD/WR Sequencing violation ", 0);
12381 end
12382 end
12383end
12384
12385reg [39:0] l2b1_rd_ent0_7;
12386always @(posedge dram_Ch0_l2b1_wr_q_7[39])
12387if (enabled)
12388begin
12389 for (i=0;i<8;i=i+1) begin
12390 l2b1_rd_ent0_7 = dram_Ch0_l2b1_rd_q[i];
12391// MAQ N2 if((dram_Ch0_l2b1_wr_q_7[35:0] == l2b1_rd_ent0_7[35:0]) && l2b1_rd_ent0_7[39]) begin
12392 if((dram_Ch0_l2b1_wr_q_7[35:0] == l2b1_rd_ent0_7[35:0]) &&
12393 l2b1_rd_ent0_7[39] &&
12394 dram_ch0_l2b1_rd_q_valids[i] &&
12395 ~dram_ch0_l2b1_rd_q_addr_err[i]) begin
12396 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
12397 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b1_rd_ent0_7[34:0]);
12398
12399 finish_test("RD/WR Sequencing violation ", 0);
12400 end
12401 end
12402end
12403
12404reg [39:0] l2b0_rd_ent1_0;
12405always @(posedge dram_Ch1_l2b0_wr_q_0[39])
12406if (enabled)
12407begin
12408 for (i=0;i<8;i=i+1) begin
12409 l2b0_rd_ent1_0 = dram_Ch1_l2b0_rd_q[i];
12410// MAQ N2 if((dram_Ch1_l2b0_wr_q_0[35:0] == l2b0_rd_ent1_0[35:0]) && l2b0_rd_ent1_0[39]) begin
12411 if((dram_Ch1_l2b0_wr_q_0[35:0] == l2b0_rd_ent1_0[35:0]) &&
12412 l2b0_rd_ent1_0[39] &&
12413 dram_ch1_l2b0_rd_q_valids[i] &&
12414 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12415 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12416 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b0_rd_ent1_0[34:0]);
12417
12418 finish_test("RD/WR Sequencing violation ", 1);
12419 end
12420 end
12421end
12422
12423reg [39:0] l2b0_rd_ent1_1;
12424always @(posedge dram_Ch1_l2b0_wr_q_1[39])
12425if (enabled)
12426begin
12427 for (i=0;i<8;i=i+1) begin
12428 l2b0_rd_ent1_1 = dram_Ch1_l2b0_rd_q[i];
12429// MAQ N2 if((dram_Ch1_l2b0_wr_q_1[35:0] == l2b0_rd_ent1_1[35:0]) && l2b0_rd_ent1_1[39]) begin
12430 if((dram_Ch1_l2b0_wr_q_1[35:0] == l2b0_rd_ent1_1[35:0]) &&
12431 l2b0_rd_ent1_1[39] &&
12432 dram_ch1_l2b0_rd_q_valids[i] &&
12433 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12434 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12435 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b0_rd_ent1_1[34:0]);
12436
12437 finish_test("RD/WR Sequencing violation ", 1);
12438 end
12439 end
12440end
12441reg [39:0] l2b0_rd_ent1_2;
12442always @(posedge dram_Ch1_l2b0_wr_q_2[39])
12443if (enabled)
12444begin
12445 for (i=0;i<8;i=i+1) begin
12446 l2b0_rd_ent1_2 = dram_Ch1_l2b0_rd_q[i];
12447// MAQ N2 if((dram_Ch1_l2b0_wr_q_2[35:0] == l2b0_rd_ent1_2[35:0]) && l2b0_rd_ent1_2[39]) begin
12448 if((dram_Ch1_l2b0_wr_q_2[35:0] == l2b0_rd_ent1_2[35:0]) &&
12449 l2b0_rd_ent1_2[39] &&
12450 dram_ch1_l2b0_rd_q_valids[i] &&
12451 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12452 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12453 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b0_rd_ent1_2[34:0]);
12454
12455 finish_test("RD/WR Sequencing violation ", 1);
12456 end
12457 end
12458end
12459reg [39:0] l2b0_rd_ent1_3;
12460always @(posedge dram_Ch1_l2b0_wr_q_3[39])
12461if (enabled)
12462begin
12463 for (i=0;i<8;i=i+1) begin
12464 l2b0_rd_ent1_3 = dram_Ch1_l2b0_rd_q[i];
12465// MAQ N2 if((dram_Ch1_l2b0_wr_q_3[35:0] == l2b0_rd_ent1_3[35:0]) && l2b0_rd_ent1_3[39]) begin
12466 if((dram_Ch1_l2b0_wr_q_3[35:0] == l2b0_rd_ent1_3[35:0]) &&
12467 l2b0_rd_ent1_3[39] &&
12468 dram_ch1_l2b0_rd_q_valids[i] &&
12469 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12470 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12471 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b0_rd_ent1_3[34:0]);
12472
12473 finish_test("RD/WR Sequencing violation ", 1);
12474 end
12475 end
12476end
12477reg [39:0] l2b0_rd_ent1_4;
12478always @(posedge dram_Ch1_l2b0_wr_q_4[39])
12479if (enabled)
12480begin
12481 for (i=0;i<8;i=i+1) begin
12482 l2b0_rd_ent1_4 = dram_Ch1_l2b0_rd_q[i];
12483// MAQ N2 if((dram_Ch1_l2b0_wr_q_4[35:0] == l2b0_rd_ent1_4[35:0]) && l2b0_rd_ent1_4[39]) begin
12484 if((dram_Ch1_l2b0_wr_q_4[35:0] == l2b0_rd_ent1_4[35:0]) &&
12485 l2b0_rd_ent1_4[39] &&
12486 dram_ch1_l2b0_rd_q_valids[i] &&
12487 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12488 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12489 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b0_rd_ent1_4[34:0]);
12490
12491 finish_test("RD/WR Sequencing violation ", 1);
12492 end
12493 end
12494end
12495reg [39:0] l2b0_rd_ent1_5;
12496always @(posedge dram_Ch1_l2b0_wr_q_5[39])
12497if (enabled)
12498begin
12499 for (i=0;i<8;i=i+1) begin
12500 l2b0_rd_ent1_5 = dram_Ch1_l2b0_rd_q[i];
12501// MAQ N2 if((dram_Ch1_l2b0_wr_q_5[35:0] == l2b0_rd_ent1_5[35:0]) && l2b0_rd_ent1_5[39]) begin
12502 if((dram_Ch1_l2b0_wr_q_5[35:0] == l2b0_rd_ent1_5[35:0]) &&
12503 l2b0_rd_ent1_5[39] &&
12504 dram_ch1_l2b0_rd_q_valids[i] &&
12505 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12506 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12507 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b0_rd_ent1_5[34:0]);
12508
12509 finish_test("RD/WR Sequencing violation ", 1);
12510 end
12511 end
12512end
12513reg [39:0] l2b0_rd_ent1_6;
12514always @(posedge dram_Ch1_l2b0_wr_q_6[39])
12515if (enabled)
12516begin
12517 for (i=0;i<8;i=i+1) begin
12518 l2b0_rd_ent1_6 = dram_Ch1_l2b0_rd_q[i];
12519// MAQ N2 if((dram_Ch1_l2b0_wr_q_6[35:0] == l2b0_rd_ent1_6[35:0]) && l2b0_rd_ent1_6[39]) begin
12520 if((dram_Ch1_l2b0_wr_q_6[35:0] == l2b0_rd_ent1_6[35:0]) &&
12521 l2b0_rd_ent1_6[39] &&
12522 dram_ch1_l2b0_rd_q_valids[i] &&
12523 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12524 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12525 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b0_rd_ent1_6[34:0]);
12526
12527 finish_test("RD/WR Sequencing violation ", 1);
12528 end
12529 end
12530end
12531reg [39:0] l2b0_rd_ent1_7;
12532always @(posedge dram_Ch1_l2b0_wr_q_7[39])
12533if (enabled)
12534begin
12535 for (i=0;i<8;i=i+1) begin
12536 l2b0_rd_ent1_7 = dram_Ch1_l2b0_rd_q[i];
12537// MAQ N2 if((dram_Ch1_l2b0_wr_q_7[35:0] == l2b0_rd_ent1_7[35:0]) && l2b0_rd_ent1_7[39]) begin
12538 if((dram_Ch1_l2b0_wr_q_7[35:0] == l2b0_rd_ent1_7[35:0]) &&
12539 l2b0_rd_ent1_7[39] &&
12540 dram_ch1_l2b0_rd_q_valids[i] &&
12541 ~dram_ch1_l2b0_rd_q_addr_err[i]) begin
12542 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
12543 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b0_rd_ent1_7[34:0]);
12544
12545 finish_test("RD/WR Sequencing violation ", 1);
12546 end
12547 end
12548end
12549reg [39:0] l2b1_rd_ent1_0;
12550always @(posedge dram_Ch1_l2b1_wr_q_0[39])
12551if (enabled)
12552begin
12553 for (i=0;i<8;i=i+1) begin
12554 l2b1_rd_ent1_0 = dram_Ch1_l2b1_rd_q[i];
12555// MAQ N2 if((dram_Ch1_l2b1_wr_q_0[35:0] == l2b1_rd_ent1_0[35:0]) && l2b1_rd_ent1_0[39]) begin
12556 if((dram_Ch1_l2b1_wr_q_0[35:0] == l2b1_rd_ent1_0[35:0]) &&
12557 l2b1_rd_ent1_0[39] &&
12558 dram_ch1_l2b1_rd_q_valids[i] &&
12559 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12560 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12561 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b1_rd_ent1_0[34:0]);
12562
12563 finish_test("RD/WR Sequencing violation ", 1);
12564 end
12565 end
12566end
12567reg [39:0] l2b1_rd_ent1_1;
12568always @(posedge dram_Ch1_l2b1_wr_q_1[39])
12569if (enabled)
12570begin
12571 for (i=0;i<8;i=i+1) begin
12572 l2b1_rd_ent1_1 = dram_Ch1_l2b1_rd_q[i];
12573// MAQ N2 if((dram_Ch1_l2b1_wr_q_1[35:0] == l2b1_rd_ent1_1[35:0]) && l2b1_rd_ent1_1[39]) begin
12574 if((dram_Ch1_l2b1_wr_q_1[35:0] == l2b1_rd_ent1_1[35:0]) &&
12575 l2b1_rd_ent1_1[39] &&
12576 dram_ch1_l2b1_rd_q_valids[i] &&
12577 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12578 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12579 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b1_rd_ent1_1[34:0]);
12580
12581 finish_test("RD/WR Sequencing violation ", 1);
12582 end
12583 end
12584end
12585reg [39:0] l2b1_rd_ent1_2;
12586always @(posedge dram_Ch1_l2b1_wr_q_2[39])
12587if (enabled)
12588begin
12589 for (i=0;i<8;i=i+1) begin
12590 l2b1_rd_ent1_2 = dram_Ch1_l2b1_rd_q[i];
12591// MAQ N2 if((dram_Ch1_l2b1_wr_q_2[35:0] == l2b1_rd_ent1_2[35:0]) && l2b1_rd_ent1_2[39]) begin
12592 if((dram_Ch1_l2b1_wr_q_2[35:0] == l2b1_rd_ent1_2[35:0]) &&
12593 l2b1_rd_ent1_2[39] &&
12594 dram_ch1_l2b1_rd_q_valids[i] &&
12595 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12596 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12597 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b1_rd_ent1_2[34:0]);
12598
12599 finish_test("RD/WR Sequencing violation ", 1);
12600 end
12601 end
12602end
12603reg [39:0] l2b1_rd_ent1_3;
12604always @(posedge dram_Ch1_l2b1_wr_q_3[39])
12605if (enabled)
12606begin
12607 for (i=0;i<8;i=i+1) begin
12608 l2b1_rd_ent1_3 = dram_Ch1_l2b1_rd_q[i];
12609// MAQ N2 if((dram_Ch1_l2b1_wr_q_3[35:0] == l2b1_rd_ent1_3[35:0]) && l2b1_rd_ent1_3[39]) begin
12610 if((dram_Ch1_l2b1_wr_q_3[35:0] == l2b1_rd_ent1_3[35:0]) &&
12611 l2b1_rd_ent1_3[39] &&
12612 dram_ch1_l2b1_rd_q_valids[i] &&
12613 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12614 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12615 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b1_rd_ent1_3[34:0]);
12616
12617 finish_test("RD/WR Sequencing violation ", 1);
12618 end
12619 end
12620end
12621reg [39:0] l2b1_rd_ent1_4;
12622always @(posedge dram_Ch1_l2b1_wr_q_4[39])
12623if (enabled)
12624begin
12625 for (i=0;i<8;i=i+1) begin
12626 l2b1_rd_ent1_4 = dram_Ch1_l2b1_rd_q[i];
12627// MAQ N2 if((dram_Ch1_l2b1_wr_q_4[35:0] == l2b1_rd_ent1_4[35:0]) && l2b1_rd_ent1_4[39]) begin
12628 if((dram_Ch1_l2b1_wr_q_4[35:0] == l2b1_rd_ent1_4[35:0]) &&
12629 l2b1_rd_ent1_4[39] &&
12630 dram_ch1_l2b1_rd_q_valids[i] &&
12631 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12632 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12633 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b1_rd_ent1_4[34:0]);
12634
12635 finish_test("RD/WR Sequencing violation ", 1);
12636 end
12637 end
12638end
12639reg [39:0] l2b1_rd_ent1_5;
12640always @(posedge dram_Ch1_l2b1_wr_q_5[39])
12641if (enabled)
12642begin
12643 for (i=0;i<8;i=i+1) begin
12644 l2b1_rd_ent1_5 = dram_Ch1_l2b1_rd_q[i];
12645// MAQ N2 if((dram_Ch1_l2b1_wr_q_5[35:0] == l2b1_rd_ent1_5[35:0]) && l2b1_rd_ent1_5[39]) begin
12646 if((dram_Ch1_l2b1_wr_q_5[35:0] == l2b1_rd_ent1_5[35:0]) &&
12647 l2b1_rd_ent1_5[39] &&
12648 dram_ch1_l2b1_rd_q_valids[i] &&
12649 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12650 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12651 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b1_rd_ent1_5[34:0]);
12652
12653 finish_test("RD/WR Sequencing violation ", 1);
12654 end
12655 end
12656end
12657reg [39:0] l2b1_rd_ent1_6;
12658always @(posedge dram_Ch1_l2b1_wr_q_6[39])
12659if (enabled)
12660begin
12661 for (i=0;i<8;i=i+1) begin
12662 l2b1_rd_ent1_6 = dram_Ch1_l2b1_rd_q[i];
12663// MAQ N2 if((dram_Ch1_l2b1_wr_q_6[35:0] == l2b1_rd_ent1_6[35:0]) && l2b1_rd_ent1_6[39]) begin
12664 if((dram_Ch1_l2b1_wr_q_6[35:0] == l2b1_rd_ent1_6[35:0]) &&
12665 l2b1_rd_ent1_6[39] &&
12666 dram_ch1_l2b1_rd_q_valids[i] &&
12667 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12668 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12669 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b1_rd_ent1_6[34:0]);
12670
12671 finish_test("RD/WR Sequencing violation ", 1);
12672 end
12673 end
12674end
12675reg [39:0] l2b1_rd_ent1_7;
12676always @(posedge dram_Ch1_l2b1_wr_q_7[39])
12677if (enabled)
12678begin
12679 for (i=0;i<8;i=i+1) begin
12680 l2b1_rd_ent1_7 = dram_Ch1_l2b1_rd_q[i];
12681// MAQ N2 if((dram_Ch1_l2b1_wr_q_7[35:0] == l2b1_rd_ent1_7[35:0]) && l2b1_rd_ent1_7[39]) begin
12682 if((dram_Ch1_l2b1_wr_q_7[35:0] == l2b1_rd_ent1_7[35:0]) &&
12683 l2b1_rd_ent1_7[39] &&
12684 dram_ch1_l2b1_rd_q_valids[i] &&
12685 ~dram_ch1_l2b1_rd_q_addr_err[i]) begin
12686 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
12687 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b1_rd_ent1_7[34:0]);
12688
12689 finish_test("RD/WR Sequencing violation ", 1);
12690 end
12691 end
12692end
12693reg [39:0] l2b0_rd_ent2_0;
12694always @(posedge dram_Ch2_l2b0_wr_q_0[39])
12695if (enabled)
12696begin
12697 for (i=0;i<8;i=i+1) begin
12698 l2b0_rd_ent2_0 = dram_Ch2_l2b0_rd_q[i];
12699// MAQ N2 if((dram_Ch2_l2b0_wr_q_0[35:0] == l2b0_rd_ent2_0[35:0]) && l2b0_rd_ent2_0[39]) begin
12700 if((dram_Ch2_l2b0_wr_q_0[35:0] == l2b0_rd_ent2_0[35:0]) &&
12701 l2b0_rd_ent2_0[39] &&
12702 dram_ch2_l2b0_rd_q_valids[i] &&
12703 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12704 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12705 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b0_rd_ent2_0[34:0]);
12706
12707 finish_test("RD/WR Sequencing violation ", 2);
12708 end
12709 end
12710end
12711
12712reg [39:0] l2b0_rd_ent2_1;
12713always @(posedge dram_Ch2_l2b0_wr_q_1[39])
12714if (enabled)
12715begin
12716 for (i=0;i<8;i=i+1) begin
12717 l2b0_rd_ent2_1 = dram_Ch2_l2b0_rd_q[i];
12718// MAQ N2 if((dram_Ch2_l2b0_wr_q_1[35:0] == l2b0_rd_ent2_1[35:0]) && l2b0_rd_ent2_1[39]) begin
12719 if((dram_Ch2_l2b0_wr_q_1[35:0] == l2b0_rd_ent2_1[35:0]) &&
12720 l2b0_rd_ent2_1[39] &&
12721 dram_ch2_l2b0_rd_q_valids[i] &&
12722 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12723 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12724 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b0_rd_ent2_1[34:0]);
12725
12726 finish_test("RD/WR Sequencing violation ", 2);
12727 end
12728 end
12729end
12730
12731reg [39:0] l2b0_rd_ent2_2;
12732always @(posedge dram_Ch2_l2b0_wr_q_2[39])
12733if (enabled)
12734begin
12735 for (i=0;i<8;i=i+1) begin
12736 l2b0_rd_ent2_2 = dram_Ch2_l2b0_rd_q[i];
12737// MAQ N2 if((dram_Ch2_l2b0_wr_q_2[35:0] == l2b0_rd_ent2_2[35:0]) && l2b0_rd_ent2_2[39]) begin
12738 if((dram_Ch2_l2b0_wr_q_2[35:0] == l2b0_rd_ent2_2[35:0]) &&
12739 l2b0_rd_ent2_2[39] &&
12740 dram_ch2_l2b0_rd_q_valids[i] &&
12741 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12742 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12743 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b0_rd_ent2_2[34:0]);
12744
12745 finish_test("RD/WR Sequencing violation ", 2);
12746 end
12747 end
12748end
12749
12750reg [39:0] l2b0_rd_ent2_3;
12751always @(posedge dram_Ch2_l2b0_wr_q_3[39])
12752if (enabled)
12753begin
12754 for (i=0;i<8;i=i+1) begin
12755 l2b0_rd_ent2_3 = dram_Ch2_l2b0_rd_q[i];
12756// MAQ N2 if((dram_Ch2_l2b0_wr_q_3[35:0] == l2b0_rd_ent2_3[35:0]) && l2b0_rd_ent2_3[39]) begin
12757 if((dram_Ch2_l2b0_wr_q_3[35:0] == l2b0_rd_ent2_3[35:0]) &&
12758 l2b0_rd_ent2_3[39] &&
12759 dram_ch2_l2b0_rd_q_valids[i] &&
12760 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12761 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12762 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b0_rd_ent2_3[34:0]);
12763
12764 finish_test("RD/WR Sequencing violation ", 2);
12765 end
12766 end
12767end
12768
12769reg [39:0] l2b0_rd_ent2_4;
12770always @(posedge dram_Ch2_l2b0_wr_q_4[39])
12771if (enabled)
12772begin
12773 for (i=0;i<8;i=i+1) begin
12774 l2b0_rd_ent2_4 = dram_Ch2_l2b0_rd_q[i];
12775// MAQ N2 if((dram_Ch2_l2b0_wr_q_4[35:0] == l2b0_rd_ent2_4[35:0]) && l2b0_rd_ent2_4[39]) begin
12776 if((dram_Ch2_l2b0_wr_q_4[35:0] == l2b0_rd_ent2_4[35:0]) &&
12777 l2b0_rd_ent2_4[39] &&
12778 dram_ch2_l2b0_rd_q_valids[i] &&
12779 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12780 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12781 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b0_rd_ent2_4[34:0]);
12782
12783 finish_test("RD/WR Sequencing violation ", 2);
12784 end
12785 end
12786end
12787
12788reg [39:0] l2b0_rd_ent2_5;
12789always @(posedge dram_Ch2_l2b0_wr_q_5[39])
12790if (enabled)
12791begin
12792 for (i=0;i<8;i=i+1) begin
12793 l2b0_rd_ent2_5 = dram_Ch2_l2b0_rd_q[i];
12794// MAQ N2 if((dram_Ch2_l2b0_wr_q_5[35:0] == l2b0_rd_ent2_5[35:0]) && l2b0_rd_ent2_5[39]) begin
12795 if((dram_Ch2_l2b0_wr_q_5[35:0] == l2b0_rd_ent2_5[35:0]) &&
12796 l2b0_rd_ent2_5[39] &&
12797 dram_ch2_l2b0_rd_q_valids[i] &&
12798 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12799 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12800 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b0_rd_ent2_5[34:0]);
12801
12802 finish_test("RD/WR Sequencing violation ", 2);
12803 end
12804 end
12805end
12806
12807reg [39:0] l2b0_rd_ent2_6;
12808always @(posedge dram_Ch2_l2b0_wr_q_6[39])
12809if (enabled)
12810begin
12811 for (i=0;i<8;i=i+1) begin
12812 l2b0_rd_ent2_6 = dram_Ch2_l2b0_rd_q[i];
12813// MAQ N2 if((dram_Ch2_l2b0_wr_q_6[35:0] == l2b0_rd_ent2_6[35:0]) && l2b0_rd_ent2_6[39]) begin
12814 if((dram_Ch2_l2b0_wr_q_6[35:0] == l2b0_rd_ent2_6[35:0]) &&
12815 l2b0_rd_ent2_6[39] &&
12816 dram_ch2_l2b0_rd_q_valids[i] &&
12817 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12818 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12819 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b0_rd_ent2_6[34:0]);
12820
12821 finish_test("RD/WR Sequencing violation ", 2);
12822 end
12823 end
12824end
12825
12826reg [39:0] l2b0_rd_ent2_7;
12827always @(posedge dram_Ch2_l2b0_wr_q_7[39])
12828if (enabled)
12829begin
12830 for (i=0;i<8;i=i+1) begin
12831 l2b0_rd_ent2_7 = dram_Ch2_l2b0_rd_q[i];
12832// MAQ N2 if((dram_Ch2_l2b0_wr_q_7[35:0] == l2b0_rd_ent2_7[35:0]) && l2b0_rd_ent2_7[39]) begin
12833 if((dram_Ch2_l2b0_wr_q_7[35:0] == l2b0_rd_ent2_7[35:0]) &&
12834 l2b0_rd_ent2_7[39] &&
12835 dram_ch2_l2b0_rd_q_valids[i] &&
12836 ~dram_ch2_l2b0_rd_q_addr_err[i]) begin
12837 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
12838 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b0_rd_ent2_7[34:0]);
12839
12840 finish_test("RD/WR Sequencing violation ", 2);
12841 end
12842 end
12843end
12844
12845reg [39:0] l2b1_rd_ent2_0;
12846always @(posedge dram_Ch2_l2b1_wr_q_0[39])
12847if (enabled)
12848begin
12849 for (i=0;i<8;i=i+1) begin
12850 l2b1_rd_ent2_0 = dram_Ch2_l2b1_rd_q[i];
12851// MAQ N2 if((dram_Ch2_l2b1_wr_q_0[35:0] == l2b1_rd_ent2_0[35:0]) && l2b1_rd_ent2_0[39]) begin
12852 if((dram_Ch2_l2b1_wr_q_0[35:0] == l2b1_rd_ent2_0[35:0]) &&
12853 l2b1_rd_ent2_0[39] &&
12854 dram_ch2_l2b1_rd_q_valids[i] &&
12855 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12856 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12857 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b1_rd_ent2_0[34:0]);
12858
12859 finish_test("RD/WR Sequencing violation ", 2);
12860 end
12861 end
12862end
12863
12864reg [39:0] l2b1_rd_ent2_1;
12865always @(posedge dram_Ch2_l2b1_wr_q_1[39])
12866if (enabled)
12867begin
12868 for (i=0;i<8;i=i+1) begin
12869 l2b1_rd_ent2_1 = dram_Ch2_l2b1_rd_q[i];
12870// MAQ N2 if((dram_Ch2_l2b1_wr_q_1[35:0] == l2b1_rd_ent2_1[35:0]) && l2b1_rd_ent2_1[39]) begin
12871 if((dram_Ch2_l2b1_wr_q_1[35:0] == l2b1_rd_ent2_1[35:0]) &&
12872 l2b1_rd_ent2_1[39] &&
12873 dram_ch2_l2b1_rd_q_valids[i] &&
12874 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12875 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12876 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b1_rd_ent2_1[34:0]);
12877
12878 finish_test("RD/WR Sequencing violation ", 2);
12879 end
12880 end
12881end
12882
12883reg [39:0] l2b1_rd_ent2_2;
12884always @(posedge dram_Ch2_l2b1_wr_q_2[39])
12885if (enabled)
12886begin
12887 for (i=0;i<8;i=i+1) begin
12888 l2b1_rd_ent2_2 = dram_Ch2_l2b1_rd_q[i];
12889// MAQ N2 if((dram_Ch2_l2b1_wr_q_2[35:0] == l2b1_rd_ent2_2[35:0]) && l2b1_rd_ent2_2[39]) begin
12890 if((dram_Ch2_l2b1_wr_q_2[35:0] == l2b1_rd_ent2_2[35:0]) &&
12891 l2b1_rd_ent2_2[39] &&
12892 dram_ch2_l2b1_rd_q_valids[i] &&
12893 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12894 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12895 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b1_rd_ent2_2[34:0]);
12896
12897 finish_test("RD/WR Sequencing violation ", 2);
12898 end
12899 end
12900end
12901
12902reg [39:0] l2b1_rd_ent2_3;
12903always @(posedge dram_Ch2_l2b1_wr_q_3[39])
12904if (enabled)
12905begin
12906 for (i=0;i<8;i=i+1) begin
12907 l2b1_rd_ent2_3 = dram_Ch2_l2b1_rd_q[i];
12908// MAQ N2 if((dram_Ch2_l2b1_wr_q_3[35:0] == l2b1_rd_ent2_3[35:0]) && l2b1_rd_ent2_3[39]) begin
12909 if((dram_Ch2_l2b1_wr_q_3[35:0] == l2b1_rd_ent2_3[35:0]) &&
12910 l2b1_rd_ent2_3[39] &&
12911 dram_ch2_l2b1_rd_q_valids[i] &&
12912 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12913 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12914 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b1_rd_ent2_3[34:0]);
12915
12916 finish_test("RD/WR Sequencing violation ", 2);
12917 end
12918 end
12919end
12920
12921reg [39:0] l2b1_rd_ent2_4;
12922always @(posedge dram_Ch2_l2b1_wr_q_4[39])
12923if (enabled)
12924begin
12925 for (i=0;i<8;i=i+1) begin
12926 l2b1_rd_ent2_4 = dram_Ch2_l2b1_rd_q[i];
12927// MAQ N2 if((dram_Ch2_l2b1_wr_q_4[35:0] == l2b1_rd_ent2_4[35:0]) && l2b1_rd_ent2_4[39]) begin
12928 if((dram_Ch2_l2b1_wr_q_4[35:0] == l2b1_rd_ent2_4[35:0]) &&
12929 l2b1_rd_ent2_4[39] &&
12930 dram_ch2_l2b1_rd_q_valids[i] &&
12931 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12932 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12933 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b1_rd_ent2_4[34:0]);
12934
12935 finish_test("RD/WR Sequencing violation ", 2);
12936 end
12937 end
12938end
12939
12940reg [39:0] l2b1_rd_ent2_5;
12941always @(posedge dram_Ch2_l2b1_wr_q_5[39])
12942if (enabled)
12943begin
12944 for (i=0;i<8;i=i+1) begin
12945 l2b1_rd_ent2_5 = dram_Ch2_l2b1_rd_q[i];
12946// MAQ N2 if((dram_Ch2_l2b1_wr_q_5[35:0] == l2b1_rd_ent2_5[35:0]) && l2b1_rd_ent2_5[39]) begin
12947 if((dram_Ch2_l2b1_wr_q_5[35:0] == l2b1_rd_ent2_5[35:0]) &&
12948 l2b1_rd_ent2_5[39] &&
12949 dram_ch2_l2b1_rd_q_valids[i] &&
12950 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12951 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12952 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b1_rd_ent2_5[34:0]);
12953
12954 finish_test("RD/WR Sequencing violation ", 2);
12955 end
12956 end
12957end
12958
12959reg [39:0] l2b1_rd_ent2_6;
12960always @(posedge dram_Ch2_l2b1_wr_q_6[39])
12961if (enabled)
12962begin
12963 for (i=0;i<8;i=i+1) begin
12964 l2b1_rd_ent2_6 = dram_Ch2_l2b1_rd_q[i];
12965// MAQ N2 if((dram_Ch2_l2b1_wr_q_6[35:0] == l2b1_rd_ent2_6[35:0]) && l2b1_rd_ent2_6[39]) begin
12966 if((dram_Ch2_l2b1_wr_q_6[35:0] == l2b1_rd_ent2_6[35:0]) &&
12967 l2b1_rd_ent2_6[39] &&
12968 dram_ch2_l2b1_rd_q_valids[i] &&
12969 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12970 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12971 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b1_rd_ent2_6[34:0]);
12972
12973 finish_test("RD/WR Sequencing violation ", 2);
12974 end
12975 end
12976end
12977
12978reg [39:0] l2b1_rd_ent2_7;
12979always @(posedge dram_Ch2_l2b1_wr_q_7[39])
12980if (enabled)
12981begin
12982 for (i=0;i<8;i=i+1) begin
12983 l2b1_rd_ent2_7 = dram_Ch2_l2b1_rd_q[i];
12984// MAQ N2 if((dram_Ch2_l2b1_wr_q_7[35:0] == l2b1_rd_ent2_7[35:0]) && l2b1_rd_ent2_7[39]) begin
12985 if((dram_Ch2_l2b1_wr_q_7[35:0] == l2b1_rd_ent2_7[35:0]) &&
12986 l2b1_rd_ent2_7[39] &&
12987 dram_ch2_l2b1_rd_q_valids[i] &&
12988 ~dram_ch2_l2b1_rd_q_addr_err[i]) begin
12989 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
12990 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b1_rd_ent2_7[34:0]);
12991
12992 finish_test("RD/WR Sequencing violation ", 2);
12993 end
12994 end
12995end
12996reg [39:0] l2b0_rd_ent3_0;
12997always @(posedge dram_Ch3_l2b0_wr_q_0[39])
12998if (enabled)
12999begin
13000 for (i=0;i<8;i=i+1) begin
13001 l2b0_rd_ent3_0 = dram_Ch3_l2b0_rd_q[i];
13002// MAQ N2 if((dram_Ch3_l2b0_wr_q_0[35:0] == l2b0_rd_ent3_0[35:0]) && l2b0_rd_ent3_0[39]) begin
13003 if((dram_Ch3_l2b0_wr_q_0[35:0] == l2b0_rd_ent3_0[35:0]) &&
13004 l2b0_rd_ent3_0[39] &&
13005 dram_ch3_l2b0_rd_q_valids[i] &&
13006 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13007 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13008 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b0_rd_ent3_0[34:0]);
13009
13010 finish_test("RD/WR Sequencing violation ", 3);
13011 end
13012 end
13013end
13014reg [39:0] l2b0_rd_ent3_1;
13015always @(posedge dram_Ch3_l2b0_wr_q_1[39])
13016if (enabled)
13017begin
13018 for (i=0;i<8;i=i+1) begin
13019 l2b0_rd_ent3_1 = dram_Ch3_l2b0_rd_q[i];
13020// MAQ N2 if((dram_Ch3_l2b0_wr_q_1[35:0] == l2b0_rd_ent3_1[35:0]) && l2b0_rd_ent3_1[39]) begin
13021 if((dram_Ch3_l2b0_wr_q_1[35:0] == l2b0_rd_ent3_1[35:0]) &&
13022 l2b0_rd_ent3_1[39] &&
13023 dram_ch3_l2b0_rd_q_valids[i] &&
13024 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13025 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13026 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b0_rd_ent3_1[34:0]);
13027
13028 finish_test("RD/WR Sequencing violation ", 3);
13029 end
13030 end
13031end
13032reg [39:0] l2b0_rd_ent3_2;
13033always @(posedge dram_Ch3_l2b0_wr_q_2[39])
13034if (enabled)
13035begin
13036 for (i=0;i<8;i=i+1) begin
13037 l2b0_rd_ent3_2 = dram_Ch3_l2b0_rd_q[i];
13038// MAQ N2 if((dram_Ch3_l2b0_wr_q_2[35:0] == l2b0_rd_ent3_2[35:0]) && l2b0_rd_ent3_2[39]) begin
13039 if((dram_Ch3_l2b0_wr_q_2[35:0] == l2b0_rd_ent3_2[35:0]) &&
13040 l2b0_rd_ent3_2[39] &&
13041 dram_ch3_l2b0_rd_q_valids[i] &&
13042 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13043 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13044 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b0_rd_ent3_2[34:0]);
13045
13046 finish_test("RD/WR Sequencing violation ", 3);
13047 end
13048 end
13049end
13050reg [39:0] l2b0_rd_ent3_3;
13051always @(posedge dram_Ch3_l2b0_wr_q_3[39])
13052if (enabled)
13053begin
13054 for (i=0;i<8;i=i+1) begin
13055 l2b0_rd_ent3_3 = dram_Ch3_l2b0_rd_q[i];
13056// MAQ N2 if((dram_Ch3_l2b0_wr_q_3[35:0] == l2b0_rd_ent3_3[35:0]) && l2b0_rd_ent3_3[39]) begin
13057 if((dram_Ch3_l2b0_wr_q_3[35:0] == l2b0_rd_ent3_3[35:0]) &&
13058 l2b0_rd_ent3_3[39] &&
13059 dram_ch3_l2b0_rd_q_valids[i] &&
13060 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13061 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13062 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b0_rd_ent3_3[34:0]);
13063
13064 finish_test("RD/WR Sequencing violation ", 3);
13065 end
13066 end
13067end
13068reg [39:0] l2b0_rd_ent3_4;
13069always @(posedge dram_Ch3_l2b0_wr_q_4[39])
13070if (enabled)
13071begin
13072 for (i=0;i<8;i=i+1) begin
13073 l2b0_rd_ent3_4 = dram_Ch3_l2b0_rd_q[i];
13074// MAQ N2 if((dram_Ch3_l2b0_wr_q_4[35:0] == l2b0_rd_ent3_4[35:0]) && l2b0_rd_ent3_4[39]) begin
13075 if((dram_Ch3_l2b0_wr_q_4[35:0] == l2b0_rd_ent3_4[35:0]) &&
13076 l2b0_rd_ent3_4[39] &&
13077 dram_ch3_l2b0_rd_q_valids[i] &&
13078 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13079 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13080 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b0_rd_ent3_4[34:0]);
13081
13082 finish_test("RD/WR Sequencing violation ", 3);
13083 end
13084 end
13085end
13086reg [39:0] l2b0_rd_ent3_5;
13087always @(posedge dram_Ch3_l2b0_wr_q_5[39])
13088if (enabled)
13089begin
13090 for (i=0;i<8;i=i+1) begin
13091 l2b0_rd_ent3_5 = dram_Ch3_l2b0_rd_q[i];
13092// MAQ N2 if((dram_Ch3_l2b0_wr_q_5[35:0] == l2b0_rd_ent3_5[35:0]) && l2b0_rd_ent3_5[39]) begin
13093 if((dram_Ch3_l2b0_wr_q_5[35:0] == l2b0_rd_ent3_5[35:0]) &&
13094 l2b0_rd_ent3_5[39] &&
13095 dram_ch3_l2b0_rd_q_valids[i] &&
13096 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13097 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13098 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b0_rd_ent3_5[34:0]);
13099
13100 finish_test("RD/WR Sequencing violation ", 3);
13101 end
13102 end
13103end
13104reg [39:0] l2b0_rd_ent3_6;
13105always @(posedge dram_Ch3_l2b0_wr_q_6[39])
13106if (enabled)
13107begin
13108 for (i=0;i<8;i=i+1) begin
13109 l2b0_rd_ent3_6 = dram_Ch3_l2b0_rd_q[i];
13110// MAQ N2 if((dram_Ch3_l2b0_wr_q_6[35:0] == l2b0_rd_ent3_6[35:0]) && l2b0_rd_ent3_6[39]) begin
13111 if((dram_Ch3_l2b0_wr_q_6[35:0] == l2b0_rd_ent3_6[35:0]) &&
13112 l2b0_rd_ent3_6[39] &&
13113 dram_ch3_l2b0_rd_q_valids[i] &&
13114 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13115 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13116 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b0_rd_ent3_6[34:0]);
13117
13118 finish_test("RD/WR Sequencing violation ", 3);
13119 end
13120 end
13121end
13122reg [39:0] l2b0_rd_ent3_7;
13123always @(posedge dram_Ch3_l2b0_wr_q_7[39])
13124if (enabled)
13125begin
13126 for (i=0;i<8;i=i+1) begin
13127 l2b0_rd_ent3_7 = dram_Ch3_l2b0_rd_q[i];
13128// MAQ N2 if((dram_Ch3_l2b0_wr_q_7[35:0] == l2b0_rd_ent3_7[35:0]) && l2b0_rd_ent3_7[39]) begin
13129 if((dram_Ch3_l2b0_wr_q_7[35:0] == l2b0_rd_ent3_7[35:0]) &&
13130 l2b0_rd_ent3_7[39] &&
13131 dram_ch3_l2b0_rd_q_valids[i] &&
13132 ~dram_ch3_l2b0_rd_q_addr_err[i]) begin
13133 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13134 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b0_rd_ent3_7[34:0]);
13135
13136 finish_test("RD/WR Sequencing violation ", 3);
13137 end
13138 end
13139end
13140reg [39:0] l2b1_rd_ent3_0;
13141always @(posedge dram_Ch3_l2b1_wr_q_0[39])
13142if (enabled)
13143begin
13144 for (i=0;i<8;i=i+1) begin
13145 l2b1_rd_ent3_0 = dram_Ch3_l2b1_rd_q[i];
13146// MAQ N2 if((dram_Ch3_l2b1_wr_q_0[35:0] == l2b1_rd_ent3_0[35:0]) && l2b1_rd_ent3_0[39]) begin
13147 if((dram_Ch3_l2b1_wr_q_0[35:0] == l2b1_rd_ent3_0[35:0]) &&
13148 l2b1_rd_ent3_0[39] &&
13149 dram_ch3_l2b1_rd_q_valids[i] &&
13150 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13151 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13152 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 0 ", $time, i, l2b1_rd_ent3_0[34:0]);
13153
13154 finish_test("RD/WR Sequencing violation ", 3);
13155 end
13156 end
13157end
13158reg [39:0] l2b1_rd_ent3_1;
13159always @(posedge dram_Ch3_l2b1_wr_q_1[39])
13160if (enabled)
13161begin
13162 for (i=0;i<8;i=i+1) begin
13163 l2b1_rd_ent3_1 = dram_Ch3_l2b1_rd_q[i];
13164// MAQ N2 if((dram_Ch3_l2b1_wr_q_1[35:0] == l2b1_rd_ent3_1[35:0]) && l2b1_rd_ent3_1[39]) begin
13165 if((dram_Ch3_l2b1_wr_q_1[35:0] == l2b1_rd_ent3_1[35:0]) &&
13166 l2b1_rd_ent3_1[39] &&
13167 dram_ch3_l2b1_rd_q_valids[i] &&
13168 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13169 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13170 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 1 ", $time, i, l2b1_rd_ent3_1[34:0]);
13171
13172 finish_test("RD/WR Sequencing violation ", 3);
13173 end
13174 end
13175end
13176reg [39:0] l2b1_rd_ent3_2;
13177always @(posedge dram_Ch3_l2b1_wr_q_2[39])
13178if (enabled)
13179begin
13180 for (i=0;i<8;i=i+1) begin
13181 l2b1_rd_ent3_2 = dram_Ch3_l2b1_rd_q[i];
13182// MAQ N2 if((dram_Ch3_l2b1_wr_q_2[35:0] == l2b1_rd_ent3_2[35:0]) && l2b1_rd_ent3_2[39]) begin
13183 if((dram_Ch3_l2b1_wr_q_2[35:0] == l2b1_rd_ent3_2[35:0]) &&
13184 l2b1_rd_ent3_2[39] &&
13185 dram_ch3_l2b1_rd_q_valids[i] &&
13186 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13187 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13188 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 2 ", $time, i, l2b1_rd_ent3_2[34:0]);
13189
13190 finish_test("RD/WR Sequencing violation ", 3);
13191 end
13192 end
13193end
13194reg [39:0] l2b1_rd_ent3_3;
13195always @(posedge dram_Ch3_l2b1_wr_q_3[39])
13196if (enabled)
13197begin
13198 for (i=0;i<8;i=i+1) begin
13199 l2b1_rd_ent3_3 = dram_Ch3_l2b1_rd_q[i];
13200// MAQ N2 if((dram_Ch3_l2b1_wr_q_3[35:0] == l2b1_rd_ent3_3[35:0]) && l2b1_rd_ent3_3[39]) begin
13201 if((dram_Ch3_l2b1_wr_q_3[35:0] == l2b1_rd_ent3_3[35:0]) &&
13202 l2b1_rd_ent3_3[39] &&
13203 dram_ch3_l2b1_rd_q_valids[i] &&
13204 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13205 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13206 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 3 ", $time, i, l2b1_rd_ent3_3[34:0]);
13207
13208 finish_test("RD/WR Sequencing violation ", 3);
13209 end
13210 end
13211end
13212reg [39:0] l2b1_rd_ent3_4;
13213always @(posedge dram_Ch3_l2b1_wr_q_4[39])
13214if (enabled)
13215begin
13216 for (i=0;i<8;i=i+1) begin
13217 l2b1_rd_ent3_4 = dram_Ch3_l2b1_rd_q[i];
13218// MAQ N2 if((dram_Ch3_l2b1_wr_q_4[35:0] == l2b1_rd_ent3_4[35:0]) && l2b1_rd_ent3_4[39]) begin
13219 if((dram_Ch3_l2b1_wr_q_4[35:0] == l2b1_rd_ent3_4[35:0]) &&
13220 l2b1_rd_ent3_4[39] &&
13221 dram_ch3_l2b1_rd_q_valids[i] &&
13222 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13223 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13224 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 4 ", $time, i, l2b1_rd_ent3_4[34:0]);
13225
13226 finish_test("RD/WR Sequencing violation ", 3);
13227 end
13228 end
13229end
13230reg [39:0] l2b1_rd_ent3_5;
13231always @(posedge dram_Ch3_l2b1_wr_q_5[39])
13232if (enabled)
13233begin
13234 for (i=0;i<8;i=i+1) begin
13235 l2b1_rd_ent3_5 = dram_Ch3_l2b1_rd_q[i];
13236// MAQ N2 if((dram_Ch3_l2b1_wr_q_5[35:0] == l2b1_rd_ent3_5[35:0]) && l2b1_rd_ent3_5[39]) begin
13237 if((dram_Ch3_l2b1_wr_q_5[35:0] == l2b1_rd_ent3_5[35:0]) &&
13238 l2b1_rd_ent3_5[39] &&
13239 dram_ch3_l2b1_rd_q_valids[i] &&
13240 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13241 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13242 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 5 ", $time, i, l2b1_rd_ent3_5[34:0]);
13243
13244 finish_test("RD/WR Sequencing violation ", 3);
13245 end
13246 end
13247end
13248reg [39:0] l2b1_rd_ent3_6;
13249always @(posedge dram_Ch3_l2b1_wr_q_6[39])
13250if (enabled)
13251begin
13252 for (i=0;i<8;i=i+1) begin
13253 l2b1_rd_ent3_6 = dram_Ch3_l2b1_rd_q[i];
13254// MAQ N2 if((dram_Ch3_l2b1_wr_q_6[35:0] == l2b1_rd_ent3_6[35:0]) && l2b1_rd_ent3_6[39]) begin
13255 if((dram_Ch3_l2b1_wr_q_6[35:0] == l2b1_rd_ent3_6[35:0]) &&
13256 l2b1_rd_ent3_6[39] &&
13257 dram_ch3_l2b1_rd_q_valids[i] &&
13258 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13259 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13260 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 6 ", $time, i, l2b1_rd_ent3_6[34:0]);
13261
13262 finish_test("RD/WR Sequencing violation ", 3);
13263 end
13264 end
13265end
13266reg [39:0] l2b1_rd_ent3_7;
13267always @(posedge dram_Ch3_l2b1_wr_q_7[39])
13268if (enabled)
13269begin
13270 for (i=0;i<8;i=i+1) begin
13271 l2b1_rd_ent3_7 = dram_Ch3_l2b1_rd_q[i];
13272// MAQ N2 if((dram_Ch3_l2b1_wr_q_7[35:0] == l2b1_rd_ent3_7[35:0]) && l2b1_rd_ent3_7[39]) begin
13273 if((dram_Ch3_l2b1_wr_q_7[35:0] == l2b1_rd_ent3_7[35:0]) &&
13274 l2b1_rd_ent3_7[39] &&
13275 dram_ch3_l2b1_rd_q_valids[i] &&
13276 ~dram_ch3_l2b1_rd_q_addr_err[i]) begin
13277 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13278 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d rd entry %d which is address = %x, has a match with incoming write entry at WR Q location 7 ", $time, i, l2b1_rd_ent3_7[34:0]);
13279
13280 finish_test("RD/WR Sequencing violation ", 3);
13281 end
13282 end
13283end
13284
13285
13286// --- MONITOR THAT NO RD/WR REQUEST COMES BEFORE THE PREVIOUS ONE HAS BEEN ACKED ---
13287
13288reg dram_Ch0_l2b0_rd_record;
13289reg dram_Ch0_l2b0_wr_record;
13290reg dram_Ch0_l2b0_wr_vld_record;
13291reg [7:0] dram_Ch0_l2b0_wr_vld_record_pipe;
13292always @ (posedge (cmp_clk && enabled))
13293begin
13294 if (~cmp_rst_l)
13295 begin
13296 dram_Ch0_l2b0_rd_record <= 1'b0;
13297 dram_Ch0_l2b0_wr_record <= 1'b0;
13298 dram_Ch0_l2b0_wr_vld_record <= 1'b0;
13299 dram_Ch0_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13300 end
13301 else begin
13302
13303 // Read Req and ack
13304 if (dram_Ch0_l2b0_sctag_dram_rd_req) dram_Ch0_l2b0_rd_record <= 1'b1;
13305 if (dram_Ch0_l2b0_dram_sctag_rd_ack) dram_Ch0_l2b0_rd_record <= 1'b0;
13306
13307 if (dram_Ch0_l2b0_rd_record && dram_Ch0_l2b0_sctag_dram_rd_req) begin
13308 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
13309 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 0);
13310 end
13311 if (~dram_Ch0_l2b0_rd_record && dram_Ch0_l2b0_dram_sctag_rd_ack) begin
13312 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
13313 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 0);
13314 end
13315
13316
13317 /****************************************************************************************
13318 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13319
13320 // Write Req and ack
13321 if (dram_Ch0_l2b0_sctag_dram_wr_req) dram_Ch0_l2b0_wr_record <= 1'b1;
13322 if (dram_Ch0_l2b0_dram_sctag_wr_ack) dram_Ch0_l2b0_wr_record <= 1'b0;
13323 if (dram_Ch0_l2b0_sctag_dram_data_vld && dram_Ch0_l2b0_wr_record && !dram_Ch0_l2b0_wr_vld_record) begin
13324 dram_Ch0_l2b0_wr_vld_record <= 1'b1;
13325 dram_Ch0_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13326 end
13327 if (dram_Ch0_l2b0_sctag_dram_data_vld && dram_Ch0_l2b0_wr_vld_record) dram_Ch0_l2b0_wr_vld_record_pipe <= {dram_Ch0_l2b0_wr_vld_record_pipe[6:0],1'b0};
13328 if (dram_Ch0_l2b0_wr_vld_record_pipe[6] && dram_Ch0_l2b0_sctag_dram_data_vld) begin
13329 dram_Ch0_l2b0_wr_record <= 1'b0;
13330 dram_Ch0_l2b0_wr_vld_record <= 1'b0;
13331 end
13332
13333 if ((dram_Ch0_l2b0_wr_record || dram_Ch0_l2b0_wr_vld_record) && dram_Ch0_l2b0_sctag_dram_wr_req) begin
13334 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
13335 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 0);
13336 end
13337 if (~dram_Ch0_l2b0_wr_record && dram_Ch0_l2b0_dram_sctag_wr_ack) begin
13338 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
13339 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 0);
13340 end
13341 if (~dram_Ch0_l2b0_wr_record && dram_Ch0_l2b0_sctag_dram_data_vld) begin
13342 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
13343 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 0);
13344 end
13345 ************************************************************************************************/
13346
13347
13348 end
13349end
13350
13351reg dram_Ch0_l2b1_rd_record;
13352reg dram_Ch0_l2b1_wr_record;
13353reg dram_Ch0_l2b1_wr_vld_record;
13354reg [7:0] dram_Ch0_l2b1_wr_vld_record_pipe;
13355always @ (posedge (cmp_clk && enabled))
13356begin
13357 if (~cmp_rst_l)
13358 begin
13359 dram_Ch0_l2b1_rd_record <= 1'b0;
13360 dram_Ch0_l2b1_wr_record <= 1'b0;
13361 dram_Ch0_l2b1_wr_vld_record <= 1'b0;
13362 dram_Ch0_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13363 end
13364 else begin
13365
13366 // Read Req and ack
13367 if (dram_Ch0_l2b1_sctag_dram_rd_req) dram_Ch0_l2b1_rd_record <= 1'b1;
13368 if (dram_Ch0_l2b1_dram_sctag_rd_ack) dram_Ch0_l2b1_rd_record <= 1'b0;
13369
13370 if (dram_Ch0_l2b1_rd_record && dram_Ch0_l2b1_sctag_dram_rd_req) begin
13371 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
13372 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 0);
13373 end
13374 if (~dram_Ch0_l2b1_rd_record && dram_Ch0_l2b1_dram_sctag_rd_ack) begin
13375 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
13376 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 0);
13377 end
13378
13379
13380 /****************************************************************************************
13381 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13382
13383 // Write Req and ack
13384 if (dram_Ch0_l2b1_sctag_dram_wr_req) dram_Ch0_l2b1_wr_record <= 1'b1;
13385 if (dram_Ch0_l2b1_dram_sctag_wr_ack) dram_Ch0_l2b1_wr_record <= 1'b0;
13386 if (dram_Ch0_l2b1_sctag_dram_data_vld && dram_Ch0_l2b1_wr_record && !dram_Ch0_l2b1_wr_vld_record) begin
13387 dram_Ch0_l2b1_wr_vld_record <= 1'b1;
13388 dram_Ch0_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13389 end
13390 if (dram_Ch0_l2b1_sctag_dram_data_vld && dram_Ch0_l2b1_wr_vld_record) dram_Ch0_l2b1_wr_vld_record_pipe <= {dram_Ch0_l2b1_wr_vld_record_pipe[6:0],1'b0};
13391 if (dram_Ch0_l2b1_wr_vld_record_pipe[6] && dram_Ch0_l2b1_sctag_dram_data_vld) begin
13392 dram_Ch0_l2b1_wr_record <= 1'b0;
13393 dram_Ch0_l2b1_wr_vld_record <= 1'b0;
13394 end
13395
13396 if ((dram_Ch0_l2b1_wr_record || dram_Ch0_l2b1_wr_vld_record) && dram_Ch0_l2b1_sctag_dram_wr_req) begin
13397 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
13398 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 0);
13399 end
13400 if (~dram_Ch0_l2b1_wr_record && dram_Ch0_l2b1_dram_sctag_wr_ack) begin
13401 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
13402 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 0);
13403 end
13404 if (~dram_Ch0_l2b1_wr_record && dram_Ch0_l2b1_sctag_dram_data_vld) begin
13405 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
13406 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 0);
13407 end
13408 ************************************************************************************************/
13409
13410
13411 end
13412end
13413
13414reg dram_Ch1_l2b0_rd_record;
13415reg dram_Ch1_l2b0_wr_record;
13416reg dram_Ch1_l2b0_wr_vld_record;
13417reg [7:0] dram_Ch1_l2b0_wr_vld_record_pipe;
13418always @ (posedge (cmp_clk && enabled))
13419begin
13420 if (~cmp_rst_l)
13421 begin
13422 dram_Ch1_l2b0_rd_record <= 1'b0;
13423 dram_Ch1_l2b0_wr_record <= 1'b0;
13424 dram_Ch1_l2b0_wr_vld_record <= 1'b0;
13425 dram_Ch1_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13426 end
13427 else begin
13428
13429 // Read Req and ack
13430 if (dram_Ch1_l2b0_sctag_dram_rd_req) dram_Ch1_l2b0_rd_record <= 1'b1;
13431 if (dram_Ch1_l2b0_dram_sctag_rd_ack) dram_Ch1_l2b0_rd_record <= 1'b0;
13432
13433 if (dram_Ch1_l2b0_rd_record && dram_Ch1_l2b0_sctag_dram_rd_req) begin
13434 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
13435 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 1);
13436 end
13437 if (~dram_Ch1_l2b0_rd_record && dram_Ch1_l2b0_dram_sctag_rd_ack) begin
13438 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
13439 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 1);
13440 end
13441
13442
13443 /****************************************************************************************
13444 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13445
13446 // Write Req and ack
13447 if (dram_Ch1_l2b0_sctag_dram_wr_req) dram_Ch1_l2b0_wr_record <= 1'b1;
13448 if (dram_Ch1_l2b0_dram_sctag_wr_ack) dram_Ch1_l2b0_wr_record <= 1'b0;
13449 if (dram_Ch1_l2b0_sctag_dram_data_vld && dram_Ch1_l2b0_wr_record && !dram_Ch1_l2b0_wr_vld_record) begin
13450 dram_Ch1_l2b0_wr_vld_record <= 1'b1;
13451 dram_Ch1_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13452 end
13453 if (dram_Ch1_l2b0_sctag_dram_data_vld && dram_Ch1_l2b0_wr_vld_record) dram_Ch1_l2b0_wr_vld_record_pipe <= {dram_Ch1_l2b0_wr_vld_record_pipe[6:0],1'b0};
13454 if (dram_Ch1_l2b0_wr_vld_record_pipe[6] && dram_Ch1_l2b0_sctag_dram_data_vld) begin
13455 dram_Ch1_l2b0_wr_record <= 1'b0;
13456 dram_Ch1_l2b0_wr_vld_record <= 1'b0;
13457 end
13458
13459 if ((dram_Ch1_l2b0_wr_record || dram_Ch1_l2b0_wr_vld_record) && dram_Ch1_l2b0_sctag_dram_wr_req) begin
13460 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
13461 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 1);
13462 end
13463 if (~dram_Ch1_l2b0_wr_record && dram_Ch1_l2b0_dram_sctag_wr_ack) begin
13464 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
13465 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 1);
13466 end
13467 if (~dram_Ch1_l2b0_wr_record && dram_Ch1_l2b0_sctag_dram_data_vld) begin
13468 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
13469 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 1);
13470 end
13471 ************************************************************************************************/
13472
13473
13474 end
13475end
13476
13477reg dram_Ch1_l2b1_rd_record;
13478reg dram_Ch1_l2b1_wr_record;
13479reg dram_Ch1_l2b1_wr_vld_record;
13480reg [7:0] dram_Ch1_l2b1_wr_vld_record_pipe;
13481always @ (posedge (cmp_clk && enabled))
13482begin
13483 if (~cmp_rst_l)
13484 begin
13485 dram_Ch1_l2b1_rd_record <= 1'b0;
13486 dram_Ch1_l2b1_wr_record <= 1'b0;
13487 dram_Ch1_l2b1_wr_vld_record <= 1'b0;
13488 dram_Ch1_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13489 end
13490 else begin
13491
13492 // Read Req and ack
13493 if (dram_Ch1_l2b1_sctag_dram_rd_req) dram_Ch1_l2b1_rd_record <= 1'b1;
13494 if (dram_Ch1_l2b1_dram_sctag_rd_ack) dram_Ch1_l2b1_rd_record <= 1'b0;
13495
13496 if (dram_Ch1_l2b1_rd_record && dram_Ch1_l2b1_sctag_dram_rd_req) begin
13497 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
13498 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 1);
13499 end
13500 if (~dram_Ch1_l2b1_rd_record && dram_Ch1_l2b1_dram_sctag_rd_ack) begin
13501 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
13502 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 1);
13503 end
13504
13505
13506 /****************************************************************************************
13507 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13508
13509 // Write Req and ack
13510 if (dram_Ch1_l2b1_sctag_dram_wr_req) dram_Ch1_l2b1_wr_record <= 1'b1;
13511 if (dram_Ch1_l2b1_dram_sctag_wr_ack) dram_Ch1_l2b1_wr_record <= 1'b0;
13512 if (dram_Ch1_l2b1_sctag_dram_data_vld && dram_Ch1_l2b1_wr_record && !dram_Ch1_l2b1_wr_vld_record) begin
13513 dram_Ch1_l2b1_wr_vld_record <= 1'b1;
13514 dram_Ch1_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13515 end
13516 if (dram_Ch1_l2b1_sctag_dram_data_vld && dram_Ch1_l2b1_wr_vld_record) dram_Ch1_l2b1_wr_vld_record_pipe <= {dram_Ch1_l2b1_wr_vld_record_pipe[6:0],1'b0};
13517 if (dram_Ch1_l2b1_wr_vld_record_pipe[6] && dram_Ch1_l2b1_sctag_dram_data_vld) begin
13518 dram_Ch1_l2b1_wr_record <= 1'b0;
13519 dram_Ch1_l2b1_wr_vld_record <= 1'b0;
13520 end
13521
13522 if ((dram_Ch1_l2b1_wr_record || dram_Ch1_l2b1_wr_vld_record) && dram_Ch1_l2b1_sctag_dram_wr_req) begin
13523 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
13524 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 1);
13525 end
13526 if (~dram_Ch1_l2b1_wr_record && dram_Ch1_l2b1_dram_sctag_wr_ack) begin
13527 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
13528 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 1);
13529 end
13530 if (~dram_Ch1_l2b1_wr_record && dram_Ch1_l2b1_sctag_dram_data_vld) begin
13531 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
13532 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 1);
13533 end
13534 ************************************************************************************************/
13535
13536
13537 end
13538end
13539
13540reg dram_Ch2_l2b0_rd_record;
13541reg dram_Ch2_l2b0_wr_record;
13542reg dram_Ch2_l2b0_wr_vld_record;
13543reg [7:0] dram_Ch2_l2b0_wr_vld_record_pipe;
13544always @ (posedge (cmp_clk && enabled))
13545begin
13546 if (~cmp_rst_l)
13547 begin
13548 dram_Ch2_l2b0_rd_record <= 1'b0;
13549 dram_Ch2_l2b0_wr_record <= 1'b0;
13550 dram_Ch2_l2b0_wr_vld_record <= 1'b0;
13551 dram_Ch2_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13552 end
13553 else begin
13554
13555 // Read Req and ack
13556 if (dram_Ch2_l2b0_sctag_dram_rd_req) dram_Ch2_l2b0_rd_record <= 1'b1;
13557 if (dram_Ch2_l2b0_dram_sctag_rd_ack) dram_Ch2_l2b0_rd_record <= 1'b0;
13558
13559 if (dram_Ch2_l2b0_rd_record && dram_Ch2_l2b0_sctag_dram_rd_req) begin
13560 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
13561 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 2);
13562 end
13563 if (~dram_Ch2_l2b0_rd_record && dram_Ch2_l2b0_dram_sctag_rd_ack) begin
13564 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
13565 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 2);
13566 end
13567
13568
13569 /****************************************************************************************
13570 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13571
13572 // Write Req and ack
13573 if (dram_Ch2_l2b0_sctag_dram_wr_req) dram_Ch2_l2b0_wr_record <= 1'b1;
13574 if (dram_Ch2_l2b0_dram_sctag_wr_ack) dram_Ch2_l2b0_wr_record <= 1'b0;
13575 if (dram_Ch2_l2b0_sctag_dram_data_vld && dram_Ch2_l2b0_wr_record && !dram_Ch2_l2b0_wr_vld_record) begin
13576 dram_Ch2_l2b0_wr_vld_record <= 1'b1;
13577 dram_Ch2_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13578 end
13579 if (dram_Ch2_l2b0_sctag_dram_data_vld && dram_Ch2_l2b0_wr_vld_record) dram_Ch2_l2b0_wr_vld_record_pipe <= {dram_Ch2_l2b0_wr_vld_record_pipe[6:0],1'b0};
13580 if (dram_Ch2_l2b0_wr_vld_record_pipe[6] && dram_Ch2_l2b0_sctag_dram_data_vld) begin
13581 dram_Ch2_l2b0_wr_record <= 1'b0;
13582 dram_Ch2_l2b0_wr_vld_record <= 1'b0;
13583 end
13584
13585 if ((dram_Ch2_l2b0_wr_record || dram_Ch2_l2b0_wr_vld_record) && dram_Ch2_l2b0_sctag_dram_wr_req) begin
13586 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
13587 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 2);
13588 end
13589 if (~dram_Ch2_l2b0_wr_record && dram_Ch2_l2b0_dram_sctag_wr_ack) begin
13590 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
13591 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 2);
13592 end
13593 if (~dram_Ch2_l2b0_wr_record && dram_Ch2_l2b0_sctag_dram_data_vld) begin
13594 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
13595 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 2);
13596 end
13597 ************************************************************************************************/
13598
13599
13600 end
13601end
13602
13603reg dram_Ch2_l2b1_rd_record;
13604reg dram_Ch2_l2b1_wr_record;
13605reg dram_Ch2_l2b1_wr_vld_record;
13606reg [7:0] dram_Ch2_l2b1_wr_vld_record_pipe;
13607always @ (posedge (cmp_clk && enabled))
13608begin
13609 if (~cmp_rst_l)
13610 begin
13611 dram_Ch2_l2b1_rd_record <= 1'b0;
13612 dram_Ch2_l2b1_wr_record <= 1'b0;
13613 dram_Ch2_l2b1_wr_vld_record <= 1'b0;
13614 dram_Ch2_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13615 end
13616 else begin
13617
13618 // Read Req and ack
13619 if (dram_Ch2_l2b1_sctag_dram_rd_req) dram_Ch2_l2b1_rd_record <= 1'b1;
13620 if (dram_Ch2_l2b1_dram_sctag_rd_ack) dram_Ch2_l2b1_rd_record <= 1'b0;
13621
13622 if (dram_Ch2_l2b1_rd_record && dram_Ch2_l2b1_sctag_dram_rd_req) begin
13623 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
13624 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 2);
13625 end
13626 if (~dram_Ch2_l2b1_rd_record && dram_Ch2_l2b1_dram_sctag_rd_ack) begin
13627 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
13628 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 2);
13629 end
13630
13631
13632 /****************************************************************************************
13633 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13634
13635 // Write Req and ack
13636 if (dram_Ch2_l2b1_sctag_dram_wr_req) dram_Ch2_l2b1_wr_record <= 1'b1;
13637 if (dram_Ch2_l2b1_dram_sctag_wr_ack) dram_Ch2_l2b1_wr_record <= 1'b0;
13638 if (dram_Ch2_l2b1_sctag_dram_data_vld && dram_Ch2_l2b1_wr_record && !dram_Ch2_l2b1_wr_vld_record) begin
13639 dram_Ch2_l2b1_wr_vld_record <= 1'b1;
13640 dram_Ch2_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13641 end
13642 if (dram_Ch2_l2b1_sctag_dram_data_vld && dram_Ch2_l2b1_wr_vld_record) dram_Ch2_l2b1_wr_vld_record_pipe <= {dram_Ch2_l2b1_wr_vld_record_pipe[6:0],1'b0};
13643 if (dram_Ch2_l2b1_wr_vld_record_pipe[6] && dram_Ch2_l2b1_sctag_dram_data_vld) begin
13644 dram_Ch2_l2b1_wr_record <= 1'b0;
13645 dram_Ch2_l2b1_wr_vld_record <= 1'b0;
13646 end
13647
13648 if ((dram_Ch2_l2b1_wr_record || dram_Ch2_l2b1_wr_vld_record) && dram_Ch2_l2b1_sctag_dram_wr_req) begin
13649 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
13650 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 2);
13651 end
13652 if (~dram_Ch2_l2b1_wr_record && dram_Ch2_l2b1_dram_sctag_wr_ack) begin
13653 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
13654 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 2);
13655 end
13656 if (~dram_Ch2_l2b1_wr_record && dram_Ch2_l2b1_sctag_dram_data_vld) begin
13657 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
13658 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 2);
13659 end
13660 ************************************************************************************************/
13661
13662
13663 end
13664end
13665
13666reg dram_Ch3_l2b0_rd_record;
13667reg dram_Ch3_l2b0_wr_record;
13668reg dram_Ch3_l2b0_wr_vld_record;
13669reg [7:0] dram_Ch3_l2b0_wr_vld_record_pipe;
13670always @ (posedge (cmp_clk && enabled))
13671begin
13672 if (~cmp_rst_l)
13673 begin
13674 dram_Ch3_l2b0_rd_record <= 1'b0;
13675 dram_Ch3_l2b0_wr_record <= 1'b0;
13676 dram_Ch3_l2b0_wr_vld_record <= 1'b0;
13677 dram_Ch3_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13678 end
13679 else begin
13680
13681 // Read Req and ack
13682 if (dram_Ch3_l2b0_sctag_dram_rd_req) dram_Ch3_l2b0_rd_record <= 1'b1;
13683 if (dram_Ch3_l2b0_dram_sctag_rd_ack) dram_Ch3_l2b0_rd_record <= 1'b0;
13684
13685 if (dram_Ch3_l2b0_rd_record && dram_Ch3_l2b0_sctag_dram_rd_req) begin
13686 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13687 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 3);
13688 end
13689 if (~dram_Ch3_l2b0_rd_record && dram_Ch3_l2b0_dram_sctag_rd_ack) begin
13690 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13691 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 3);
13692 end
13693
13694
13695 /****************************************************************************************
13696 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13697
13698 // Write Req and ack
13699 if (dram_Ch3_l2b0_sctag_dram_wr_req) dram_Ch3_l2b0_wr_record <= 1'b1;
13700 if (dram_Ch3_l2b0_dram_sctag_wr_ack) dram_Ch3_l2b0_wr_record <= 1'b0;
13701 if (dram_Ch3_l2b0_sctag_dram_data_vld && dram_Ch3_l2b0_wr_record && !dram_Ch3_l2b0_wr_vld_record) begin
13702 dram_Ch3_l2b0_wr_vld_record <= 1'b1;
13703 dram_Ch3_l2b0_wr_vld_record_pipe <= 8'b0000_0001;
13704 end
13705 if (dram_Ch3_l2b0_sctag_dram_data_vld && dram_Ch3_l2b0_wr_vld_record) dram_Ch3_l2b0_wr_vld_record_pipe <= {dram_Ch3_l2b0_wr_vld_record_pipe[6:0],1'b0};
13706 if (dram_Ch3_l2b0_wr_vld_record_pipe[6] && dram_Ch3_l2b0_sctag_dram_data_vld) begin
13707 dram_Ch3_l2b0_wr_record <= 1'b0;
13708 dram_Ch3_l2b0_wr_vld_record <= 1'b0;
13709 end
13710
13711 if ((dram_Ch3_l2b0_wr_record || dram_Ch3_l2b0_wr_vld_record) && dram_Ch3_l2b0_sctag_dram_wr_req) begin
13712 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13713 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 3);
13714 end
13715 if (~dram_Ch3_l2b0_wr_record && dram_Ch3_l2b0_dram_sctag_wr_ack) begin
13716 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13717 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 3);
13718 end
13719 if (~dram_Ch3_l2b0_wr_record && dram_Ch3_l2b0_sctag_dram_data_vld) begin
13720 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
13721 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 3);
13722 end
13723 ************************************************************************************************/
13724
13725
13726 end
13727end
13728
13729reg dram_Ch3_l2b1_rd_record;
13730reg dram_Ch3_l2b1_wr_record;
13731reg dram_Ch3_l2b1_wr_vld_record;
13732reg [7:0] dram_Ch3_l2b1_wr_vld_record_pipe;
13733always @ (posedge (cmp_clk && enabled))
13734begin
13735 if (~cmp_rst_l)
13736 begin
13737 dram_Ch3_l2b1_rd_record <= 1'b0;
13738 dram_Ch3_l2b1_wr_record <= 1'b0;
13739 dram_Ch3_l2b1_wr_vld_record <= 1'b0;
13740 dram_Ch3_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13741 end
13742 else begin
13743
13744 // Read Req and ack
13745 if (dram_Ch3_l2b1_sctag_dram_rd_req) dram_Ch3_l2b1_rd_record <= 1'b1;
13746 if (dram_Ch3_l2b1_dram_sctag_rd_ack) dram_Ch3_l2b1_rd_record <= 1'b0;
13747
13748 if (dram_Ch3_l2b1_rd_record && dram_Ch3_l2b1_sctag_dram_rd_req) begin
13749 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13750 finish_test(" Rd Ack Monitor : RD ack pending, new RD issued", 3);
13751 end
13752 if (~dram_Ch3_l2b1_rd_record && dram_Ch3_l2b1_dram_sctag_rd_ack) begin
13753 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13754 finish_test(" Rd Ack Monitor : RD REQ not pending, RD ack issued", 3);
13755 end
13756
13757
13758 /****************************************************************************************
13759 // COVERAGE OF THIS CHECKER THRU MCUL2_INTF_CHECKER.V (0IN) CONTRAINTS 5.1 - 5.5
13760
13761 // Write Req and ack
13762 if (dram_Ch3_l2b1_sctag_dram_wr_req) dram_Ch3_l2b1_wr_record <= 1'b1;
13763 if (dram_Ch3_l2b1_dram_sctag_wr_ack) dram_Ch3_l2b1_wr_record <= 1'b0;
13764 if (dram_Ch3_l2b1_sctag_dram_data_vld && dram_Ch3_l2b1_wr_record && !dram_Ch3_l2b1_wr_vld_record) begin
13765 dram_Ch3_l2b1_wr_vld_record <= 1'b1;
13766 dram_Ch3_l2b1_wr_vld_record_pipe <= 8'b0000_0001;
13767 end
13768 if (dram_Ch3_l2b1_sctag_dram_data_vld && dram_Ch3_l2b1_wr_vld_record) dram_Ch3_l2b1_wr_vld_record_pipe <= {dram_Ch3_l2b1_wr_vld_record_pipe[6:0],1'b0};
13769 if (dram_Ch3_l2b1_wr_vld_record_pipe[6] && dram_Ch3_l2b1_sctag_dram_data_vld) begin
13770 dram_Ch3_l2b1_wr_record <= 1'b0;
13771 dram_Ch3_l2b1_wr_vld_record <= 1'b0;
13772 end
13773
13774 if ((dram_Ch3_l2b1_wr_record || dram_Ch3_l2b1_wr_vld_record) && dram_Ch3_l2b1_sctag_dram_wr_req) begin
13775 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13776 finish_test(" Wr Ack Monitor : Wr ack/data valid pending, new Wr issued", 3);
13777 end
13778 if (~dram_Ch3_l2b1_wr_record && dram_Ch3_l2b1_dram_sctag_wr_ack) begin
13779 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13780 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr ack issued", 3);
13781 end
13782 if (~dram_Ch3_l2b1_wr_record && dram_Ch3_l2b1_sctag_dram_data_vld) begin
13783 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
13784 finish_test(" Wr Ack Monitor : Wr REQ not pending, Wr Data Valid issued", 3);
13785 end
13786 ************************************************************************************************/
13787
13788
13789 end
13790end
13791
13792
13793
13794// ----- MONITOR RD REQ TO RD DATA VLD ( DATA RETURN) LATENCY -----
13795
13796reg [13:0] dram_Ch0_l2b0_rd_req_ack_cntr [7:0];
13797wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_0 = dram_Ch0_l2b0_rd_req_ack_cntr[0];
13798wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_1 = dram_Ch0_l2b0_rd_req_ack_cntr[1];
13799wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_2 = dram_Ch0_l2b0_rd_req_ack_cntr[2];
13800wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_3 = dram_Ch0_l2b0_rd_req_ack_cntr[3];
13801wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_4 = dram_Ch0_l2b0_rd_req_ack_cntr[4];
13802wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_5 = dram_Ch0_l2b0_rd_req_ack_cntr[5];
13803wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_6 = dram_Ch0_l2b0_rd_req_ack_cntr[6];
13804wire [13:0] dram_Ch0_l2b0_rd_req_ack_cntr_7 = dram_Ch0_l2b0_rd_req_ack_cntr[7];
13805
13806reg [7:0] dram_Ch0_l2b0_rd_req_pend;
13807
13808
13809always @ (posedge (cmp_clk && enabled))
13810begin
13811 if (~cmp_rst_l)
13812 begin
13813 for(i=0;i<8;i=i+1) begin
13814 dram_Ch0_l2b0_rd_req_ack_cntr[i] = 0;
13815 end
13816 dram_Ch0_l2b0_rd_req_pend <= 0;
13817 end
13818 else
13819 begin
13820 if (dram_Ch0_l2b0_sctag_dram_rd_req && !dram_Ch0_l2b0_sctag_dram_rd_dummy_req) dram_Ch0_l2b0_rd_req_pend[dram_Ch0_l2b0_sctag_dram_rd_req_id] <= 1'b1;
13821 if (dram_Ch0_l2b0_dram_sctag_data_vld) dram_Ch0_l2b0_rd_req_pend[dram_Ch0_l2b0_dram_sctag_rd_req_id] <= 1'b0;
13822
13823 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
13824 for(i=0;i<8;i=i+1) begin
13825 dram_Ch0_l2b0_rd_req_ack_cntr[i] <= (dram_Ch0_l2b0_rd_req_pend[i] == 1'b1) ? dram_Ch0_l2b0_rd_req_ack_cntr[i] + 1 : 0;
13826 //if ( dram_Ch0_l2b0_rd_req_ack_cntr[i] > MAX_TIME ) begin
13827 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 0:l2b0 ");
13828 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 0);
13829 //end
13830 end // end for
13831 end // end if
13832
13833 // Monitor that if request to the same id has not yet got the data back and a
13834 // request with the same id is issued.
13835 if (dram_Ch0_l2b0_sctag_dram_rd_req) begin
13836 if (dram_Ch0_l2b0_rd_req_pend[dram_Ch0_l2b0_sctag_dram_rd_req_id] == 1'b1 ) begin
13837 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b0 ");
13838 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 0);
13839 end
13840 end
13841
13842 end // end of begin (else)
13843end // end always
13844reg [13:0] dram_Ch0_l2b1_rd_req_ack_cntr [7:0];
13845wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_0 = dram_Ch0_l2b1_rd_req_ack_cntr[0];
13846wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_1 = dram_Ch0_l2b1_rd_req_ack_cntr[1];
13847wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_2 = dram_Ch0_l2b1_rd_req_ack_cntr[2];
13848wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_3 = dram_Ch0_l2b1_rd_req_ack_cntr[3];
13849wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_4 = dram_Ch0_l2b1_rd_req_ack_cntr[4];
13850wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_5 = dram_Ch0_l2b1_rd_req_ack_cntr[5];
13851wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_6 = dram_Ch0_l2b1_rd_req_ack_cntr[6];
13852wire [13:0] dram_Ch0_l2b1_rd_req_ack_cntr_7 = dram_Ch0_l2b1_rd_req_ack_cntr[7];
13853
13854reg [7:0] dram_Ch0_l2b1_rd_req_pend;
13855
13856
13857always @ (posedge (cmp_clk && enabled))
13858begin
13859 if (~cmp_rst_l)
13860 begin
13861 for(i=0;i<8;i=i+1) begin
13862 dram_Ch0_l2b1_rd_req_ack_cntr[i] = 0;
13863 end
13864 dram_Ch0_l2b1_rd_req_pend <= 0;
13865 end
13866 else
13867 begin
13868 if (dram_Ch0_l2b1_sctag_dram_rd_req && !dram_Ch0_l2b1_sctag_dram_rd_dummy_req) dram_Ch0_l2b1_rd_req_pend[dram_Ch0_l2b1_sctag_dram_rd_req_id] <= 1'b1;
13869 if (dram_Ch0_l2b1_dram_sctag_data_vld) dram_Ch0_l2b1_rd_req_pend[dram_Ch0_l2b1_dram_sctag_rd_req_id] <= 1'b0;
13870
13871 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
13872 for(i=0;i<8;i=i+1) begin
13873 dram_Ch0_l2b1_rd_req_ack_cntr[i] <= (dram_Ch0_l2b1_rd_req_pend[i] == 1'b1) ? dram_Ch0_l2b1_rd_req_ack_cntr[i] + 1 : 0;
13874 //if ( dram_Ch0_l2b1_rd_req_ack_cntr[i] > MAX_TIME ) begin
13875 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 0:l2b1 ");
13876 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 0);
13877 //end
13878 end // end for
13879 end // end if
13880
13881 // Monitor that if request to the same id has not yet got the data back and a
13882 // request with the same id is issued.
13883 if (dram_Ch0_l2b1_sctag_dram_rd_req) begin
13884 if (dram_Ch0_l2b1_rd_req_pend[dram_Ch0_l2b1_sctag_dram_rd_req_id] == 1'b1 ) begin
13885 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b1 ");
13886 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 0);
13887 end
13888 end
13889
13890 end // end of begin (else)
13891end // end always
13892reg [13:0] dram_Ch1_l2b0_rd_req_ack_cntr [7:0];
13893wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_0 = dram_Ch1_l2b0_rd_req_ack_cntr[0];
13894wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_1 = dram_Ch1_l2b0_rd_req_ack_cntr[1];
13895wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_2 = dram_Ch1_l2b0_rd_req_ack_cntr[2];
13896wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_3 = dram_Ch1_l2b0_rd_req_ack_cntr[3];
13897wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_4 = dram_Ch1_l2b0_rd_req_ack_cntr[4];
13898wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_5 = dram_Ch1_l2b0_rd_req_ack_cntr[5];
13899wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_6 = dram_Ch1_l2b0_rd_req_ack_cntr[6];
13900wire [13:0] dram_Ch1_l2b0_rd_req_ack_cntr_7 = dram_Ch1_l2b0_rd_req_ack_cntr[7];
13901
13902reg [7:0] dram_Ch1_l2b0_rd_req_pend;
13903
13904
13905always @ (posedge (cmp_clk && enabled))
13906begin
13907 if (~cmp_rst_l)
13908 begin
13909 for(i=0;i<8;i=i+1) begin
13910 dram_Ch1_l2b0_rd_req_ack_cntr[i] = 0;
13911 end
13912 dram_Ch1_l2b0_rd_req_pend <= 0;
13913 end
13914 else
13915 begin
13916 if (dram_Ch1_l2b0_sctag_dram_rd_req && !dram_Ch1_l2b0_sctag_dram_rd_dummy_req) dram_Ch1_l2b0_rd_req_pend[dram_Ch1_l2b0_sctag_dram_rd_req_id] <= 1'b1;
13917 if (dram_Ch1_l2b0_dram_sctag_data_vld) dram_Ch1_l2b0_rd_req_pend[dram_Ch1_l2b0_dram_sctag_rd_req_id] <= 1'b0;
13918
13919 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
13920 for(i=0;i<8;i=i+1) begin
13921 dram_Ch1_l2b0_rd_req_ack_cntr[i] <= (dram_Ch1_l2b0_rd_req_pend[i] == 1'b1) ? dram_Ch1_l2b0_rd_req_ack_cntr[i] + 1 : 0;
13922 //if ( dram_Ch1_l2b0_rd_req_ack_cntr[i] > MAX_TIME ) begin
13923 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 1:l2b0 ");
13924 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 1);
13925 //end
13926 end // end for
13927 end // end if
13928
13929 // Monitor that if request to the same id has not yet got the data back and a
13930 // request with the same id is issued.
13931 if (dram_Ch1_l2b0_sctag_dram_rd_req) begin
13932 if (dram_Ch1_l2b0_rd_req_pend[dram_Ch1_l2b0_sctag_dram_rd_req_id] == 1'b1 ) begin
13933 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b0 ");
13934 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 1);
13935 end
13936 end
13937
13938 end // end of begin (else)
13939end // end always
13940reg [13:0] dram_Ch1_l2b1_rd_req_ack_cntr [7:0];
13941wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_0 = dram_Ch1_l2b1_rd_req_ack_cntr[0];
13942wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_1 = dram_Ch1_l2b1_rd_req_ack_cntr[1];
13943wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_2 = dram_Ch1_l2b1_rd_req_ack_cntr[2];
13944wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_3 = dram_Ch1_l2b1_rd_req_ack_cntr[3];
13945wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_4 = dram_Ch1_l2b1_rd_req_ack_cntr[4];
13946wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_5 = dram_Ch1_l2b1_rd_req_ack_cntr[5];
13947wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_6 = dram_Ch1_l2b1_rd_req_ack_cntr[6];
13948wire [13:0] dram_Ch1_l2b1_rd_req_ack_cntr_7 = dram_Ch1_l2b1_rd_req_ack_cntr[7];
13949
13950reg [7:0] dram_Ch1_l2b1_rd_req_pend;
13951
13952
13953always @ (posedge (cmp_clk && enabled))
13954begin
13955 if (~cmp_rst_l)
13956 begin
13957 for(i=0;i<8;i=i+1) begin
13958 dram_Ch1_l2b1_rd_req_ack_cntr[i] = 0;
13959 end
13960 dram_Ch1_l2b1_rd_req_pend <= 0;
13961 end
13962 else
13963 begin
13964 if (dram_Ch1_l2b1_sctag_dram_rd_req && !dram_Ch1_l2b1_sctag_dram_rd_dummy_req) dram_Ch1_l2b1_rd_req_pend[dram_Ch1_l2b1_sctag_dram_rd_req_id] <= 1'b1;
13965 if (dram_Ch1_l2b1_dram_sctag_data_vld) dram_Ch1_l2b1_rd_req_pend[dram_Ch1_l2b1_dram_sctag_rd_req_id] <= 1'b0;
13966
13967 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
13968 for(i=0;i<8;i=i+1) begin
13969 dram_Ch1_l2b1_rd_req_ack_cntr[i] <= (dram_Ch1_l2b1_rd_req_pend[i] == 1'b1) ? dram_Ch1_l2b1_rd_req_ack_cntr[i] + 1 : 0;
13970 //if ( dram_Ch1_l2b1_rd_req_ack_cntr[i] > MAX_TIME ) begin
13971 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 1:l2b1 ");
13972 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 1);
13973 //end
13974 end // end for
13975 end // end if
13976
13977 // Monitor that if request to the same id has not yet got the data back and a
13978 // request with the same id is issued.
13979 if (dram_Ch1_l2b1_sctag_dram_rd_req) begin
13980 if (dram_Ch1_l2b1_rd_req_pend[dram_Ch1_l2b1_sctag_dram_rd_req_id] == 1'b1 ) begin
13981 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b1 ");
13982 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 1);
13983 end
13984 end
13985
13986 end // end of begin (else)
13987end // end always
13988reg [13:0] dram_Ch2_l2b0_rd_req_ack_cntr [7:0];
13989wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_0 = dram_Ch2_l2b0_rd_req_ack_cntr[0];
13990wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_1 = dram_Ch2_l2b0_rd_req_ack_cntr[1];
13991wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_2 = dram_Ch2_l2b0_rd_req_ack_cntr[2];
13992wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_3 = dram_Ch2_l2b0_rd_req_ack_cntr[3];
13993wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_4 = dram_Ch2_l2b0_rd_req_ack_cntr[4];
13994wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_5 = dram_Ch2_l2b0_rd_req_ack_cntr[5];
13995wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_6 = dram_Ch2_l2b0_rd_req_ack_cntr[6];
13996wire [13:0] dram_Ch2_l2b0_rd_req_ack_cntr_7 = dram_Ch2_l2b0_rd_req_ack_cntr[7];
13997
13998reg [7:0] dram_Ch2_l2b0_rd_req_pend;
13999
14000
14001always @ (posedge (cmp_clk && enabled))
14002begin
14003 if (~cmp_rst_l)
14004 begin
14005 for(i=0;i<8;i=i+1) begin
14006 dram_Ch2_l2b0_rd_req_ack_cntr[i] = 0;
14007 end
14008 dram_Ch2_l2b0_rd_req_pend <= 0;
14009 end
14010 else
14011 begin
14012 if (dram_Ch2_l2b0_sctag_dram_rd_req && !dram_Ch2_l2b0_sctag_dram_rd_dummy_req) dram_Ch2_l2b0_rd_req_pend[dram_Ch2_l2b0_sctag_dram_rd_req_id] <= 1'b1;
14013 if (dram_Ch2_l2b0_dram_sctag_data_vld) dram_Ch2_l2b0_rd_req_pend[dram_Ch2_l2b0_dram_sctag_rd_req_id] <= 1'b0;
14014
14015 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
14016 for(i=0;i<8;i=i+1) begin
14017 dram_Ch2_l2b0_rd_req_ack_cntr[i] <= (dram_Ch2_l2b0_rd_req_pend[i] == 1'b1) ? dram_Ch2_l2b0_rd_req_ack_cntr[i] + 1 : 0;
14018 //if ( dram_Ch2_l2b0_rd_req_ack_cntr[i] > MAX_TIME ) begin
14019 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 2:l2b0 ");
14020 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 2);
14021 //end
14022 end // end for
14023 end // end if
14024
14025 // Monitor that if request to the same id has not yet got the data back and a
14026 // request with the same id is issued.
14027 if (dram_Ch2_l2b0_sctag_dram_rd_req) begin
14028 if (dram_Ch2_l2b0_rd_req_pend[dram_Ch2_l2b0_sctag_dram_rd_req_id] == 1'b1 ) begin
14029 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b0 ");
14030 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 2);
14031 end
14032 end
14033
14034 end // end of begin (else)
14035end // end always
14036reg [13:0] dram_Ch2_l2b1_rd_req_ack_cntr [7:0];
14037wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_0 = dram_Ch2_l2b1_rd_req_ack_cntr[0];
14038wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_1 = dram_Ch2_l2b1_rd_req_ack_cntr[1];
14039wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_2 = dram_Ch2_l2b1_rd_req_ack_cntr[2];
14040wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_3 = dram_Ch2_l2b1_rd_req_ack_cntr[3];
14041wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_4 = dram_Ch2_l2b1_rd_req_ack_cntr[4];
14042wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_5 = dram_Ch2_l2b1_rd_req_ack_cntr[5];
14043wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_6 = dram_Ch2_l2b1_rd_req_ack_cntr[6];
14044wire [13:0] dram_Ch2_l2b1_rd_req_ack_cntr_7 = dram_Ch2_l2b1_rd_req_ack_cntr[7];
14045
14046reg [7:0] dram_Ch2_l2b1_rd_req_pend;
14047
14048
14049always @ (posedge (cmp_clk && enabled))
14050begin
14051 if (~cmp_rst_l)
14052 begin
14053 for(i=0;i<8;i=i+1) begin
14054 dram_Ch2_l2b1_rd_req_ack_cntr[i] = 0;
14055 end
14056 dram_Ch2_l2b1_rd_req_pend <= 0;
14057 end
14058 else
14059 begin
14060 if (dram_Ch2_l2b1_sctag_dram_rd_req && !dram_Ch2_l2b1_sctag_dram_rd_dummy_req) dram_Ch2_l2b1_rd_req_pend[dram_Ch2_l2b1_sctag_dram_rd_req_id] <= 1'b1;
14061 if (dram_Ch2_l2b1_dram_sctag_data_vld) dram_Ch2_l2b1_rd_req_pend[dram_Ch2_l2b1_dram_sctag_rd_req_id] <= 1'b0;
14062
14063 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
14064 for(i=0;i<8;i=i+1) begin
14065 dram_Ch2_l2b1_rd_req_ack_cntr[i] <= (dram_Ch2_l2b1_rd_req_pend[i] == 1'b1) ? dram_Ch2_l2b1_rd_req_ack_cntr[i] + 1 : 0;
14066 //if ( dram_Ch2_l2b1_rd_req_ack_cntr[i] > MAX_TIME ) begin
14067 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 2:l2b1 ");
14068 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 2);
14069 //end
14070 end // end for
14071 end // end if
14072
14073 // Monitor that if request to the same id has not yet got the data back and a
14074 // request with the same id is issued.
14075 if (dram_Ch2_l2b1_sctag_dram_rd_req) begin
14076 if (dram_Ch2_l2b1_rd_req_pend[dram_Ch2_l2b1_sctag_dram_rd_req_id] == 1'b1 ) begin
14077 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b1 ");
14078 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 2);
14079 end
14080 end
14081
14082 end // end of begin (else)
14083end // end always
14084reg [13:0] dram_Ch3_l2b0_rd_req_ack_cntr [7:0];
14085wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_0 = dram_Ch3_l2b0_rd_req_ack_cntr[0];
14086wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_1 = dram_Ch3_l2b0_rd_req_ack_cntr[1];
14087wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_2 = dram_Ch3_l2b0_rd_req_ack_cntr[2];
14088wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_3 = dram_Ch3_l2b0_rd_req_ack_cntr[3];
14089wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_4 = dram_Ch3_l2b0_rd_req_ack_cntr[4];
14090wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_5 = dram_Ch3_l2b0_rd_req_ack_cntr[5];
14091wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_6 = dram_Ch3_l2b0_rd_req_ack_cntr[6];
14092wire [13:0] dram_Ch3_l2b0_rd_req_ack_cntr_7 = dram_Ch3_l2b0_rd_req_ack_cntr[7];
14093
14094reg [7:0] dram_Ch3_l2b0_rd_req_pend;
14095
14096
14097always @ (posedge (cmp_clk && enabled))
14098begin
14099 if (~cmp_rst_l)
14100 begin
14101 for(i=0;i<8;i=i+1) begin
14102 dram_Ch3_l2b0_rd_req_ack_cntr[i] = 0;
14103 end
14104 dram_Ch3_l2b0_rd_req_pend <= 0;
14105 end
14106 else
14107 begin
14108 if (dram_Ch3_l2b0_sctag_dram_rd_req && !dram_Ch3_l2b0_sctag_dram_rd_dummy_req) dram_Ch3_l2b0_rd_req_pend[dram_Ch3_l2b0_sctag_dram_rd_req_id] <= 1'b1;
14109 if (dram_Ch3_l2b0_dram_sctag_data_vld) dram_Ch3_l2b0_rd_req_pend[dram_Ch3_l2b0_dram_sctag_rd_req_id] <= 1'b0;
14110
14111 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
14112 for(i=0;i<8;i=i+1) begin
14113 dram_Ch3_l2b0_rd_req_ack_cntr[i] <= (dram_Ch3_l2b0_rd_req_pend[i] == 1'b1) ? dram_Ch3_l2b0_rd_req_ack_cntr[i] + 1 : 0;
14114 //if ( dram_Ch3_l2b0_rd_req_ack_cntr[i] > MAX_TIME ) begin
14115 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 3:l2b0 ");
14116 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 3);
14117 //end
14118 end // end for
14119 end // end if
14120
14121 // Monitor that if request to the same id has not yet got the data back and a
14122 // request with the same id is issued.
14123 if (dram_Ch3_l2b0_sctag_dram_rd_req) begin
14124 if (dram_Ch3_l2b0_rd_req_pend[dram_Ch3_l2b0_sctag_dram_rd_req_id] == 1'b1 ) begin
14125 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b0 ");
14126 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 3);
14127 end
14128 end
14129
14130 end // end of begin (else)
14131end // end always
14132reg [13:0] dram_Ch3_l2b1_rd_req_ack_cntr [7:0];
14133wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_0 = dram_Ch3_l2b1_rd_req_ack_cntr[0];
14134wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_1 = dram_Ch3_l2b1_rd_req_ack_cntr[1];
14135wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_2 = dram_Ch3_l2b1_rd_req_ack_cntr[2];
14136wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_3 = dram_Ch3_l2b1_rd_req_ack_cntr[3];
14137wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_4 = dram_Ch3_l2b1_rd_req_ack_cntr[4];
14138wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_5 = dram_Ch3_l2b1_rd_req_ack_cntr[5];
14139wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_6 = dram_Ch3_l2b1_rd_req_ack_cntr[6];
14140wire [13:0] dram_Ch3_l2b1_rd_req_ack_cntr_7 = dram_Ch3_l2b1_rd_req_ack_cntr[7];
14141
14142reg [7:0] dram_Ch3_l2b1_rd_req_pend;
14143
14144
14145always @ (posedge (cmp_clk && enabled))
14146begin
14147 if (~cmp_rst_l)
14148 begin
14149 for(i=0;i<8;i=i+1) begin
14150 dram_Ch3_l2b1_rd_req_ack_cntr[i] = 0;
14151 end
14152 dram_Ch3_l2b1_rd_req_pend <= 0;
14153 end
14154 else
14155 begin
14156 if (dram_Ch3_l2b1_sctag_dram_rd_req && !dram_Ch3_l2b1_sctag_dram_rd_dummy_req) dram_Ch3_l2b1_rd_req_pend[dram_Ch3_l2b1_sctag_dram_rd_req_id] <= 1'b1;
14157 if (dram_Ch3_l2b1_dram_sctag_data_vld) dram_Ch3_l2b1_rd_req_pend[dram_Ch3_l2b1_dram_sctag_rd_req_id] <= 1'b0;
14158
14159 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
14160 for(i=0;i<8;i=i+1) begin
14161 dram_Ch3_l2b1_rd_req_ack_cntr[i] <= (dram_Ch3_l2b1_rd_req_pend[i] == 1'b1) ? dram_Ch3_l2b1_rd_req_ack_cntr[i] + 1 : 0;
14162 //if ( dram_Ch3_l2b1_rd_req_ack_cntr[i] > MAX_TIME ) begin
14163 // `PR_ERROR("mcu_monitor", `ERROR, "In dram channel 3:l2b1 ");
14164 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 3);
14165 //end
14166 end // end for
14167 end // end if
14168
14169 // Monitor that if request to the same id has not yet got the data back and a
14170 // request with the same id is issued.
14171 if (dram_Ch3_l2b1_sctag_dram_rd_req) begin
14172 if (dram_Ch3_l2b1_rd_req_pend[dram_Ch3_l2b1_sctag_dram_rd_req_id] == 1'b1 ) begin
14173 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b1 ");
14174 finish_test(" L2-DRAM : Error Read Request ID in use and Rd with same ID issued ", 3);
14175 end
14176 end
14177
14178 end // end of begin (else)
14179end // end always
14180
14181
14182
14183// ---- MONITOR WR REQ TO WR ACK -----
14184
14185reg [10:0] dram_Ch0_l2b0_wr_req_ack_cntr;
14186
14187reg dram_Ch0_l2b0_wr_req_pend;
14188
14189
14190always @ (posedge (cmp_clk && enabled))
14191begin
14192 if (~cmp_rst_l)
14193 begin
14194 dram_Ch0_l2b0_wr_req_ack_cntr = 0;
14195 dram_Ch0_l2b0_wr_req_pend <= 0;
14196 end
14197 else
14198 begin
14199 if (dram_Ch0_l2b0_sctag_dram_wr_req) dram_Ch0_l2b0_wr_req_pend <= 1'b1;
14200 if (dram_Ch0_l2b0_dram_sctag_wr_ack) dram_Ch0_l2b0_wr_req_pend <= 1'b0;
14201
14202 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
14203 dram_Ch0_l2b0_wr_req_ack_cntr <= (dram_Ch0_l2b0_wr_req_pend == 1'b1) ? dram_Ch0_l2b0_wr_req_ack_cntr + 1 : 0;
14204 //if ( dram_Ch0_l2b0_wr_req_ack_cntr[i] > MAX_TIME ) begin
14205 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 0:l2b0 ");
14206 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 0);
14207 //end
14208 end
14209 end
14210end
14211reg [10:0] dram_Ch0_l2b1_wr_req_ack_cntr;
14212
14213reg dram_Ch0_l2b1_wr_req_pend;
14214
14215
14216always @ (posedge (cmp_clk && enabled))
14217begin
14218 if (~cmp_rst_l)
14219 begin
14220 dram_Ch0_l2b1_wr_req_ack_cntr = 0;
14221 dram_Ch0_l2b1_wr_req_pend <= 0;
14222 end
14223 else
14224 begin
14225 if (dram_Ch0_l2b1_sctag_dram_wr_req) dram_Ch0_l2b1_wr_req_pend <= 1'b1;
14226 if (dram_Ch0_l2b1_dram_sctag_wr_ack) dram_Ch0_l2b1_wr_req_pend <= 1'b0;
14227
14228 if (dram_Ch0_que_init_dram_done == 1'b1 ) begin
14229 dram_Ch0_l2b1_wr_req_ack_cntr <= (dram_Ch0_l2b1_wr_req_pend == 1'b1) ? dram_Ch0_l2b1_wr_req_ack_cntr + 1 : 0;
14230 //if ( dram_Ch0_l2b1_wr_req_ack_cntr[i] > MAX_TIME ) begin
14231 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 0:l2b1 ");
14232 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 0);
14233 //end
14234 end
14235 end
14236end
14237reg [10:0] dram_Ch1_l2b0_wr_req_ack_cntr;
14238
14239reg dram_Ch1_l2b0_wr_req_pend;
14240
14241
14242always @ (posedge (cmp_clk && enabled))
14243begin
14244 if (~cmp_rst_l)
14245 begin
14246 dram_Ch1_l2b0_wr_req_ack_cntr = 0;
14247 dram_Ch1_l2b0_wr_req_pend <= 0;
14248 end
14249 else
14250 begin
14251 if (dram_Ch1_l2b0_sctag_dram_wr_req) dram_Ch1_l2b0_wr_req_pend <= 1'b1;
14252 if (dram_Ch1_l2b0_dram_sctag_wr_ack) dram_Ch1_l2b0_wr_req_pend <= 1'b0;
14253
14254 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
14255 dram_Ch1_l2b0_wr_req_ack_cntr <= (dram_Ch1_l2b0_wr_req_pend == 1'b1) ? dram_Ch1_l2b0_wr_req_ack_cntr + 1 : 0;
14256 //if ( dram_Ch1_l2b0_wr_req_ack_cntr[i] > MAX_TIME ) begin
14257 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 1:l2b0 ");
14258 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 1);
14259 //end
14260 end
14261 end
14262end
14263reg [10:0] dram_Ch1_l2b1_wr_req_ack_cntr;
14264
14265reg dram_Ch1_l2b1_wr_req_pend;
14266
14267
14268always @ (posedge (cmp_clk && enabled))
14269begin
14270 if (~cmp_rst_l)
14271 begin
14272 dram_Ch1_l2b1_wr_req_ack_cntr = 0;
14273 dram_Ch1_l2b1_wr_req_pend <= 0;
14274 end
14275 else
14276 begin
14277 if (dram_Ch1_l2b1_sctag_dram_wr_req) dram_Ch1_l2b1_wr_req_pend <= 1'b1;
14278 if (dram_Ch1_l2b1_dram_sctag_wr_ack) dram_Ch1_l2b1_wr_req_pend <= 1'b0;
14279
14280 if (dram_Ch1_que_init_dram_done == 1'b1 ) begin
14281 dram_Ch1_l2b1_wr_req_ack_cntr <= (dram_Ch1_l2b1_wr_req_pend == 1'b1) ? dram_Ch1_l2b1_wr_req_ack_cntr + 1 : 0;
14282 //if ( dram_Ch1_l2b1_wr_req_ack_cntr[i] > MAX_TIME ) begin
14283 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 1:l2b1 ");
14284 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 1);
14285 //end
14286 end
14287 end
14288end
14289reg [10:0] dram_Ch2_l2b0_wr_req_ack_cntr;
14290
14291reg dram_Ch2_l2b0_wr_req_pend;
14292
14293
14294always @ (posedge (cmp_clk && enabled))
14295begin
14296 if (~cmp_rst_l)
14297 begin
14298 dram_Ch2_l2b0_wr_req_ack_cntr = 0;
14299 dram_Ch2_l2b0_wr_req_pend <= 0;
14300 end
14301 else
14302 begin
14303 if (dram_Ch2_l2b0_sctag_dram_wr_req) dram_Ch2_l2b0_wr_req_pend <= 1'b1;
14304 if (dram_Ch2_l2b0_dram_sctag_wr_ack) dram_Ch2_l2b0_wr_req_pend <= 1'b0;
14305
14306 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
14307 dram_Ch2_l2b0_wr_req_ack_cntr <= (dram_Ch2_l2b0_wr_req_pend == 1'b1) ? dram_Ch2_l2b0_wr_req_ack_cntr + 1 : 0;
14308 //if ( dram_Ch2_l2b0_wr_req_ack_cntr[i] > MAX_TIME ) begin
14309 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 2:l2b0 ");
14310 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 2);
14311 //end
14312 end
14313 end
14314end
14315reg [10:0] dram_Ch2_l2b1_wr_req_ack_cntr;
14316
14317reg dram_Ch2_l2b1_wr_req_pend;
14318
14319
14320always @ (posedge (cmp_clk && enabled))
14321begin
14322 if (~cmp_rst_l)
14323 begin
14324 dram_Ch2_l2b1_wr_req_ack_cntr = 0;
14325 dram_Ch2_l2b1_wr_req_pend <= 0;
14326 end
14327 else
14328 begin
14329 if (dram_Ch2_l2b1_sctag_dram_wr_req) dram_Ch2_l2b1_wr_req_pend <= 1'b1;
14330 if (dram_Ch2_l2b1_dram_sctag_wr_ack) dram_Ch2_l2b1_wr_req_pend <= 1'b0;
14331
14332 if (dram_Ch2_que_init_dram_done == 1'b1 ) begin
14333 dram_Ch2_l2b1_wr_req_ack_cntr <= (dram_Ch2_l2b1_wr_req_pend == 1'b1) ? dram_Ch2_l2b1_wr_req_ack_cntr + 1 : 0;
14334 //if ( dram_Ch2_l2b1_wr_req_ack_cntr[i] > MAX_TIME ) begin
14335 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 2:l2b1 ");
14336 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 2);
14337 //end
14338 end
14339 end
14340end
14341reg [10:0] dram_Ch3_l2b0_wr_req_ack_cntr;
14342
14343reg dram_Ch3_l2b0_wr_req_pend;
14344
14345
14346always @ (posedge (cmp_clk && enabled))
14347begin
14348 if (~cmp_rst_l)
14349 begin
14350 dram_Ch3_l2b0_wr_req_ack_cntr = 0;
14351 dram_Ch3_l2b0_wr_req_pend <= 0;
14352 end
14353 else
14354 begin
14355 if (dram_Ch3_l2b0_sctag_dram_wr_req) dram_Ch3_l2b0_wr_req_pend <= 1'b1;
14356 if (dram_Ch3_l2b0_dram_sctag_wr_ack) dram_Ch3_l2b0_wr_req_pend <= 1'b0;
14357
14358 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
14359 dram_Ch3_l2b0_wr_req_ack_cntr <= (dram_Ch3_l2b0_wr_req_pend == 1'b1) ? dram_Ch3_l2b0_wr_req_ack_cntr + 1 : 0;
14360 //if ( dram_Ch3_l2b0_wr_req_ack_cntr[i] > MAX_TIME ) begin
14361 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 3:l2b0 ");
14362 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 3);
14363 //end
14364 end
14365 end
14366end
14367reg [10:0] dram_Ch3_l2b1_wr_req_ack_cntr;
14368
14369reg dram_Ch3_l2b1_wr_req_pend;
14370
14371
14372always @ (posedge (cmp_clk && enabled))
14373begin
14374 if (~cmp_rst_l)
14375 begin
14376 dram_Ch3_l2b1_wr_req_ack_cntr = 0;
14377 dram_Ch3_l2b1_wr_req_pend <= 0;
14378 end
14379 else
14380 begin
14381 if (dram_Ch3_l2b1_sctag_dram_wr_req) dram_Ch3_l2b1_wr_req_pend <= 1'b1;
14382 if (dram_Ch3_l2b1_dram_sctag_wr_ack) dram_Ch3_l2b1_wr_req_pend <= 1'b0;
14383
14384 if (dram_Ch3_que_init_dram_done == 1'b1 ) begin
14385 dram_Ch3_l2b1_wr_req_ack_cntr <= (dram_Ch3_l2b1_wr_req_pend == 1'b1) ? dram_Ch3_l2b1_wr_req_ack_cntr + 1 : 0;
14386 //if ( dram_Ch3_l2b1_wr_req_ack_cntr[i] > MAX_TIME ) begin
14387 // `PR_ERROR("mcusat_cov_mon", `ERROR, "In dram channel 3:l2b1 ");
14388 // finish_test(" RD Q : Entry in read que for more that MAX_TIME clocks ", 3);
14389 //end
14390 end
14391 end
14392end
14393
14394// ----- Monitor to make sure that after refresh process has been initiatedall the CAS to same CS are cleared and no more RAS issued -----
14395
14396reg [1:0] dram_Ch0_refresh_all_clr_mon_state;
14397reg cas_valid_0;
14398reg dram_Ch0_que_ref_go_d1;
14399
14400initial
14401 begin
14402 dram_Ch0_refresh_all_clr_mon_state = 2'b00;
14403 dram_Ch0_que_ref_go_d1 = 1'b0;
14404 end
14405
14406always @ (posedge (`MCU_CLK && enabled))
14407begin
14408if ( ((($test$plusargs("RANK_DIMM")) || ($test$plusargs("STACK_DIMM"))) == 0) ) begin
14409 if (~dram_rst_l)
14410 begin
14411 dram_Ch0_refresh_all_clr_mon_state <= 2'b00;
14412 dram_Ch0_que_ref_go_d1 <= 1'b0;
14413 cas_valid_0 = 0;
14414 end
14415 else
14416 begin
14417 dram_Ch0_que_ref_go_d1 <= (dram_Ch0_que_ref_go || dram_Ch0_que_hw_selfrsh) && (dram_Ch0_que_pos == 5'h1);
14418
14419 case(dram_Ch0_refresh_all_clr_mon_state)
14420 2'b00 : begin
14421 if (dram_Ch0_que_ref_go_d1) begin
14422 dram_Ch0_refresh_all_clr_mon_state <= 2'b01;
14423 cas_valid_0 <= dram_Ch0_que_cas_valid | dram_Ch0_que_ras_picked; // MAQ Added Ras valid also.
14424 end
14425 end
14426 2'b01 : begin
14427 if (dram_Ch0_que_pos == 5'h3)
14428 dram_Ch0_refresh_all_clr_mon_state <= 2'b10;
14429 /*else begin
14430 // monitor that no new cas valid turns up, indicating RAS issued
14431 if (!cas_valid_0 && dram_Ch0_que_cas_valid) begin
14432 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b2 ");
14433 finish_test(" Refresh Monitor : RAS issued after refresh process started ", 0);
14434 end
14435 end*/
14436 end
14437 2'b10 : begin
14438 dram_Ch0_refresh_all_clr_mon_state <= 2'b00;
14439 // check that all the CAS to same CS issued
14440 /*if (dram_Ch0_que_cas_valid && (dram_Ch0_b_phy_bank_bits[0] == dram_Ch0_que_refresh_rank)) begin
14441 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b2 ");
14442 finish_test(" Refresh Monitor : CAS to same CS as refresh pending and refresh issued", 0);
14443 end*/
14444 end
14445 default : begin
14446 dram_Ch0_refresh_all_clr_mon_state <= 2'b00;
14447 end
14448
14449 endcase
14450 end
14451 end // testplus
14452end
14453reg [1:0] dram_Ch1_refresh_all_clr_mon_state;
14454reg cas_valid_1;
14455reg dram_Ch1_que_ref_go_d1;
14456
14457initial
14458 begin
14459 dram_Ch1_refresh_all_clr_mon_state = 2'b00;
14460 dram_Ch1_que_ref_go_d1 = 1'b0;
14461 end
14462
14463always @ (posedge (`MCU_CLK && enabled))
14464begin
14465if ( ((($test$plusargs("RANK_DIMM")) || ($test$plusargs("STACK_DIMM"))) == 0) ) begin
14466 if (~dram_rst_l)
14467 begin
14468 dram_Ch1_refresh_all_clr_mon_state <= 2'b00;
14469 dram_Ch1_que_ref_go_d1 <= 1'b0;
14470 cas_valid_1 = 0;
14471 end
14472 else
14473 begin
14474 dram_Ch1_que_ref_go_d1 <= (dram_Ch1_que_ref_go || dram_Ch1_que_hw_selfrsh) && (dram_Ch1_que_pos == 5'h1);
14475
14476 case(dram_Ch1_refresh_all_clr_mon_state)
14477 2'b00 : begin
14478 if (dram_Ch1_que_ref_go_d1) begin
14479 dram_Ch1_refresh_all_clr_mon_state <= 2'b01;
14480 cas_valid_1 <= dram_Ch1_que_cas_valid | dram_Ch1_que_ras_picked; // MAQ Added Ras valid also.
14481 end
14482 end
14483 2'b01 : begin
14484 if (dram_Ch1_que_pos == 5'h3)
14485 dram_Ch1_refresh_all_clr_mon_state <= 2'b10;
14486 /*else begin
14487 // monitor that no new cas valid turns up, indicating RAS issued
14488 if (!cas_valid_1 && dram_Ch1_que_cas_valid) begin
14489 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b2 ");
14490 finish_test(" Refresh Monitor : RAS issued after refresh process started ", 1);
14491 end
14492 end*/
14493 end
14494 2'b10 : begin
14495 dram_Ch1_refresh_all_clr_mon_state <= 2'b00;
14496 // check that all the CAS to same CS issued
14497 /*if (dram_Ch1_que_cas_valid && (dram_Ch1_b_phy_bank_bits[0] == dram_Ch1_que_refresh_rank)) begin
14498 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b2 ");
14499 finish_test(" Refresh Monitor : CAS to same CS as refresh pending and refresh issued", 1);
14500 end*/
14501 end
14502 default : begin
14503 dram_Ch1_refresh_all_clr_mon_state <= 2'b00;
14504 end
14505
14506 endcase
14507 end
14508 end // testplus
14509end
14510reg [1:0] dram_Ch2_refresh_all_clr_mon_state;
14511reg cas_valid_2;
14512reg dram_Ch2_que_ref_go_d1;
14513
14514initial
14515 begin
14516 dram_Ch2_refresh_all_clr_mon_state = 2'b00;
14517 dram_Ch2_que_ref_go_d1 = 1'b0;
14518 end
14519
14520always @ (posedge (`MCU_CLK && enabled))
14521begin
14522if ( ((($test$plusargs("RANK_DIMM")) || ($test$plusargs("STACK_DIMM"))) == 0) ) begin
14523 if (~dram_rst_l)
14524 begin
14525 dram_Ch2_refresh_all_clr_mon_state <= 2'b00;
14526 dram_Ch2_que_ref_go_d1 <= 1'b0;
14527 cas_valid_2 = 0;
14528 end
14529 else
14530 begin
14531 dram_Ch2_que_ref_go_d1 <= (dram_Ch2_que_ref_go || dram_Ch2_que_hw_selfrsh) && (dram_Ch2_que_pos == 5'h1);
14532
14533 case(dram_Ch2_refresh_all_clr_mon_state)
14534 2'b00 : begin
14535 if (dram_Ch2_que_ref_go_d1) begin
14536 dram_Ch2_refresh_all_clr_mon_state <= 2'b01;
14537 cas_valid_2 <= dram_Ch2_que_cas_valid | dram_Ch2_que_ras_picked; // MAQ Added Ras valid also.
14538 end
14539 end
14540 2'b01 : begin
14541 if (dram_Ch2_que_pos == 5'h3)
14542 dram_Ch2_refresh_all_clr_mon_state <= 2'b10;
14543 /*else begin
14544 // monitor that no new cas valid turns up, indicating RAS issued
14545 if (!cas_valid_2 && dram_Ch2_que_cas_valid) begin
14546 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b2 ");
14547 finish_test(" Refresh Monitor : RAS issued after refresh process started ", 2);
14548 end
14549 end*/
14550 end
14551 2'b10 : begin
14552 dram_Ch2_refresh_all_clr_mon_state <= 2'b00;
14553 // check that all the CAS to same CS issued
14554 /*if (dram_Ch2_que_cas_valid && (dram_Ch2_b_phy_bank_bits[0] == dram_Ch2_que_refresh_rank)) begin
14555 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b2 ");
14556 finish_test(" Refresh Monitor : CAS to same CS as refresh pending and refresh issued", 2);
14557 end*/
14558 end
14559 default : begin
14560 dram_Ch2_refresh_all_clr_mon_state <= 2'b00;
14561 end
14562
14563 endcase
14564 end
14565 end // testplus
14566end
14567reg [1:0] dram_Ch3_refresh_all_clr_mon_state;
14568reg cas_valid_3;
14569reg dram_Ch3_que_ref_go_d1;
14570
14571initial
14572 begin
14573 dram_Ch3_refresh_all_clr_mon_state = 2'b00;
14574 dram_Ch3_que_ref_go_d1 = 1'b0;
14575 end
14576
14577always @ (posedge (`MCU_CLK && enabled))
14578begin
14579if ( ((($test$plusargs("RANK_DIMM")) || ($test$plusargs("STACK_DIMM"))) == 0) ) begin
14580 if (~dram_rst_l)
14581 begin
14582 dram_Ch3_refresh_all_clr_mon_state <= 2'b00;
14583 dram_Ch3_que_ref_go_d1 <= 1'b0;
14584 cas_valid_3 = 0;
14585 end
14586 else
14587 begin
14588 dram_Ch3_que_ref_go_d1 <= (dram_Ch3_que_ref_go || dram_Ch3_que_hw_selfrsh) && (dram_Ch3_que_pos == 5'h1);
14589
14590 case(dram_Ch3_refresh_all_clr_mon_state)
14591 2'b00 : begin
14592 if (dram_Ch3_que_ref_go_d1) begin
14593 dram_Ch3_refresh_all_clr_mon_state <= 2'b01;
14594 cas_valid_3 <= dram_Ch3_que_cas_valid | dram_Ch3_que_ras_picked; // MAQ Added Ras valid also.
14595 end
14596 end
14597 2'b01 : begin
14598 if (dram_Ch3_que_pos == 5'h3)
14599 dram_Ch3_refresh_all_clr_mon_state <= 2'b10;
14600 /*else begin
14601 // monitor that no new cas valid turns up, indicating RAS issued
14602 if (!cas_valid_3 && dram_Ch3_que_cas_valid) begin
14603 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b2 ");
14604 finish_test(" Refresh Monitor : RAS issued after refresh process started ", 3);
14605 end
14606 end*/
14607 end
14608 2'b10 : begin
14609 dram_Ch3_refresh_all_clr_mon_state <= 2'b00;
14610 // check that all the CAS to same CS issued
14611 /*if (dram_Ch3_que_cas_valid && (dram_Ch3_b_phy_bank_bits[0] == dram_Ch3_que_refresh_rank)) begin
14612 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b2 ");
14613 finish_test(" Refresh Monitor : CAS to same CS as refresh pending and refresh issued", 3);
14614 end*/
14615 end
14616 default : begin
14617 dram_Ch3_refresh_all_clr_mon_state <= 2'b00;
14618 end
14619
14620 endcase
14621 end
14622 end // testplus
14623end
14624
14625// -------- MONITOR FOR READ WRITE WITH SAME ADDRESS, SCHMOO -------
14626
14627reg dram_Ch0_l2b0_rd_req_2a_addr_vld;
14628reg l2b0_req_2a_addr_0;
14629reg [39:0] samp_addr_l2b0_rd_q_loc_0;
14630
14631// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14632// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14633
14634always @( dram_Ch0_l2b0_rd_q_0 or dram_Ch0_l2b0_rd_q_1 or dram_Ch0_l2b0_rd_q_2 or dram_Ch0_l2b0_rd_q_3 or
14635 dram_Ch0_l2b0_rd_q_4 or dram_Ch0_l2b0_rd_q_5 or dram_Ch0_l2b0_rd_q_6 or dram_Ch0_l2b0_rd_q_7)
14636begin
14637 l2b0_req_2a_addr_0 = 0;
14638 for (i=0;i<8;i=i+1) begin
14639 samp_addr_l2b0_rd_q_loc_0 = dram_Ch0_l2b0_rd_q[i];
14640 l2b0_req_2a_addr_0 = (samp_addr_l2b0_rd_q_loc_0[39] && ({samp_addr_l2b0_rd_q_loc_0[35:32],samp_addr_l2b0_rd_q_loc_0[5],samp_addr_l2b0_rd_q_loc_0[28:14],samp_addr_l2b0_rd_q_loc_0[13:6],samp_addr_l2b0_rd_q_loc_0[31:29],samp_addr_l2b0_rd_q_loc_0[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr_0;
14641 end
14642
14643 dram_Ch0_l2b0_rd_req_2a_addr_vld <= l2b0_req_2a_addr_0;
14644
14645
14646end
14647
14648reg dram_Ch0_l2b0_wr_req_2a_addr_vld;
14649reg l2b0_req_2a_addr1_0;
14650reg [39:0] samp_addr_l2b0_wr_q_loc_0;
14651
14652// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14653// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14654
14655always @( dram_Ch0_l2b0_wr_q_0 or dram_Ch0_l2b0_wr_q_1 or dram_Ch0_l2b0_wr_q_2 or dram_Ch0_l2b0_wr_q_3 or
14656 dram_Ch0_l2b0_wr_q_4 or dram_Ch0_l2b0_wr_q_5 or dram_Ch0_l2b0_wr_q_6 or dram_Ch0_l2b0_wr_q_7)
14657begin
14658 l2b0_req_2a_addr1_0 = 0;
14659 for (i=0;i<8;i=i+1) begin
14660 samp_addr_l2b0_wr_q_loc_0 = dram_Ch0_l2b0_wr_q[i];
14661 l2b0_req_2a_addr1_0 = (samp_addr_l2b0_wr_q_loc_0[39] && ({samp_addr_l2b0_wr_q_loc_0[35:32],samp_addr_l2b0_wr_q_loc_0[5],samp_addr_l2b0_wr_q_loc_0[28:14],samp_addr_l2b0_wr_q_loc_0[13:6],samp_addr_l2b0_wr_q_loc_0[31:29],samp_addr_l2b0_wr_q_loc_0[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr1_0;
14662 end
14663
14664 dram_Ch0_l2b0_wr_req_2a_addr_vld <= l2b0_req_2a_addr1_0;
14665
14666
14667end
14668reg dram_Ch0_l2b1_rd_req_2a_addr_vld;
14669reg l2b1_req_2a_addr_0;
14670reg [39:0] samp_addr_l2b1_rd_q_loc_0;
14671
14672// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14673// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14674
14675always @( dram_Ch0_l2b1_rd_q_0 or dram_Ch0_l2b1_rd_q_1 or dram_Ch0_l2b1_rd_q_2 or dram_Ch0_l2b1_rd_q_3 or
14676 dram_Ch0_l2b1_rd_q_4 or dram_Ch0_l2b1_rd_q_5 or dram_Ch0_l2b1_rd_q_6 or dram_Ch0_l2b1_rd_q_7)
14677begin
14678 l2b1_req_2a_addr_0 = 0;
14679 for (i=0;i<8;i=i+1) begin
14680 samp_addr_l2b1_rd_q_loc_0 = dram_Ch0_l2b1_rd_q[i];
14681 l2b1_req_2a_addr_0 = (samp_addr_l2b1_rd_q_loc_0[39] && ({samp_addr_l2b1_rd_q_loc_0[35:32],samp_addr_l2b1_rd_q_loc_0[5],samp_addr_l2b1_rd_q_loc_0[28:14],samp_addr_l2b1_rd_q_loc_0[13:6],samp_addr_l2b1_rd_q_loc_0[31:29],samp_addr_l2b1_rd_q_loc_0[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr_0;
14682 end
14683
14684 dram_Ch0_l2b1_rd_req_2a_addr_vld <= l2b1_req_2a_addr_0;
14685
14686
14687end
14688
14689reg dram_Ch0_l2b1_wr_req_2a_addr_vld;
14690reg l2b1_req_2a_addr1_0;
14691reg [39:0] samp_addr_l2b1_wr_q_loc_0;
14692
14693// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14694// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14695
14696always @( dram_Ch0_l2b1_wr_q_0 or dram_Ch0_l2b1_wr_q_1 or dram_Ch0_l2b1_wr_q_2 or dram_Ch0_l2b1_wr_q_3 or
14697 dram_Ch0_l2b1_wr_q_4 or dram_Ch0_l2b1_wr_q_5 or dram_Ch0_l2b1_wr_q_6 or dram_Ch0_l2b1_wr_q_7)
14698begin
14699 l2b1_req_2a_addr1_0 = 0;
14700 for (i=0;i<8;i=i+1) begin
14701 samp_addr_l2b1_wr_q_loc_0 = dram_Ch0_l2b1_wr_q[i];
14702 l2b1_req_2a_addr1_0 = (samp_addr_l2b1_wr_q_loc_0[39] && ({samp_addr_l2b1_wr_q_loc_0[35:32],samp_addr_l2b1_wr_q_loc_0[5],samp_addr_l2b1_wr_q_loc_0[28:14],samp_addr_l2b1_wr_q_loc_0[13:6],samp_addr_l2b1_wr_q_loc_0[31:29],samp_addr_l2b1_wr_q_loc_0[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr1_0;
14703 end
14704
14705 dram_Ch0_l2b1_wr_req_2a_addr_vld <= l2b1_req_2a_addr1_0;
14706
14707
14708end
14709reg dram_Ch1_l2b0_rd_req_2a_addr_vld;
14710reg l2b0_req_2a_addr_1;
14711reg [39:0] samp_addr_l2b0_rd_q_loc_1;
14712
14713// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14714// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14715
14716always @( dram_Ch1_l2b0_rd_q_0 or dram_Ch1_l2b0_rd_q_1 or dram_Ch1_l2b0_rd_q_2 or dram_Ch1_l2b0_rd_q_3 or
14717 dram_Ch1_l2b0_rd_q_4 or dram_Ch1_l2b0_rd_q_5 or dram_Ch1_l2b0_rd_q_6 or dram_Ch1_l2b0_rd_q_7)
14718begin
14719 l2b0_req_2a_addr_1 = 0;
14720 for (i=0;i<8;i=i+1) begin
14721 samp_addr_l2b0_rd_q_loc_1 = dram_Ch1_l2b0_rd_q[i];
14722 l2b0_req_2a_addr_1 = (samp_addr_l2b0_rd_q_loc_1[39] && ({samp_addr_l2b0_rd_q_loc_1[35:32],samp_addr_l2b0_rd_q_loc_1[5],samp_addr_l2b0_rd_q_loc_1[28:14],samp_addr_l2b0_rd_q_loc_1[13:6],samp_addr_l2b0_rd_q_loc_1[31:29],samp_addr_l2b0_rd_q_loc_1[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr_1;
14723 end
14724
14725 dram_Ch1_l2b0_rd_req_2a_addr_vld <= l2b0_req_2a_addr_1;
14726
14727
14728end
14729
14730reg dram_Ch1_l2b0_wr_req_2a_addr_vld;
14731reg l2b0_req_2a_addr1_1;
14732reg [39:0] samp_addr_l2b0_wr_q_loc_1;
14733
14734// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14735// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14736
14737always @( dram_Ch1_l2b0_wr_q_0 or dram_Ch1_l2b0_wr_q_1 or dram_Ch1_l2b0_wr_q_2 or dram_Ch1_l2b0_wr_q_3 or
14738 dram_Ch1_l2b0_wr_q_4 or dram_Ch1_l2b0_wr_q_5 or dram_Ch1_l2b0_wr_q_6 or dram_Ch1_l2b0_wr_q_7)
14739begin
14740 l2b0_req_2a_addr1_1 = 0;
14741 for (i=0;i<8;i=i+1) begin
14742 samp_addr_l2b0_wr_q_loc_1 = dram_Ch1_l2b0_wr_q[i];
14743 l2b0_req_2a_addr1_1 = (samp_addr_l2b0_wr_q_loc_1[39] && ({samp_addr_l2b0_wr_q_loc_1[35:32],samp_addr_l2b0_wr_q_loc_1[5],samp_addr_l2b0_wr_q_loc_1[28:14],samp_addr_l2b0_wr_q_loc_1[13:6],samp_addr_l2b0_wr_q_loc_1[31:29],samp_addr_l2b0_wr_q_loc_1[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr1_1;
14744 end
14745
14746 dram_Ch1_l2b0_wr_req_2a_addr_vld <= l2b0_req_2a_addr1_1;
14747
14748
14749end
14750reg dram_Ch1_l2b1_rd_req_2a_addr_vld;
14751reg l2b1_req_2a_addr_1;
14752reg [39:0] samp_addr_l2b1_rd_q_loc_1;
14753
14754// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14755// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14756
14757always @( dram_Ch1_l2b1_rd_q_0 or dram_Ch1_l2b1_rd_q_1 or dram_Ch1_l2b1_rd_q_2 or dram_Ch1_l2b1_rd_q_3 or
14758 dram_Ch1_l2b1_rd_q_4 or dram_Ch1_l2b1_rd_q_5 or dram_Ch1_l2b1_rd_q_6 or dram_Ch1_l2b1_rd_q_7)
14759begin
14760 l2b1_req_2a_addr_1 = 0;
14761 for (i=0;i<8;i=i+1) begin
14762 samp_addr_l2b1_rd_q_loc_1 = dram_Ch1_l2b1_rd_q[i];
14763 l2b1_req_2a_addr_1 = (samp_addr_l2b1_rd_q_loc_1[39] && ({samp_addr_l2b1_rd_q_loc_1[35:32],samp_addr_l2b1_rd_q_loc_1[5],samp_addr_l2b1_rd_q_loc_1[28:14],samp_addr_l2b1_rd_q_loc_1[13:6],samp_addr_l2b1_rd_q_loc_1[31:29],samp_addr_l2b1_rd_q_loc_1[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr_1;
14764 end
14765
14766 dram_Ch1_l2b1_rd_req_2a_addr_vld <= l2b1_req_2a_addr_1;
14767
14768
14769end
14770
14771reg dram_Ch1_l2b1_wr_req_2a_addr_vld;
14772reg l2b1_req_2a_addr1_1;
14773reg [39:0] samp_addr_l2b1_wr_q_loc_1;
14774
14775// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14776// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14777
14778always @( dram_Ch1_l2b1_wr_q_0 or dram_Ch1_l2b1_wr_q_1 or dram_Ch1_l2b1_wr_q_2 or dram_Ch1_l2b1_wr_q_3 or
14779 dram_Ch1_l2b1_wr_q_4 or dram_Ch1_l2b1_wr_q_5 or dram_Ch1_l2b1_wr_q_6 or dram_Ch1_l2b1_wr_q_7)
14780begin
14781 l2b1_req_2a_addr1_1 = 0;
14782 for (i=0;i<8;i=i+1) begin
14783 samp_addr_l2b1_wr_q_loc_1 = dram_Ch1_l2b1_wr_q[i];
14784 l2b1_req_2a_addr1_1 = (samp_addr_l2b1_wr_q_loc_1[39] && ({samp_addr_l2b1_wr_q_loc_1[35:32],samp_addr_l2b1_wr_q_loc_1[5],samp_addr_l2b1_wr_q_loc_1[28:14],samp_addr_l2b1_wr_q_loc_1[13:6],samp_addr_l2b1_wr_q_loc_1[31:29],samp_addr_l2b1_wr_q_loc_1[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr1_1;
14785 end
14786
14787 dram_Ch1_l2b1_wr_req_2a_addr_vld <= l2b1_req_2a_addr1_1;
14788
14789
14790end
14791reg dram_Ch2_l2b0_rd_req_2a_addr_vld;
14792reg l2b0_req_2a_addr_2;
14793reg [39:0] samp_addr_l2b0_rd_q_loc_2;
14794
14795// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14796// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14797
14798always @( dram_Ch2_l2b0_rd_q_0 or dram_Ch2_l2b0_rd_q_1 or dram_Ch2_l2b0_rd_q_2 or dram_Ch2_l2b0_rd_q_3 or
14799 dram_Ch2_l2b0_rd_q_4 or dram_Ch2_l2b0_rd_q_5 or dram_Ch2_l2b0_rd_q_6 or dram_Ch2_l2b0_rd_q_7)
14800begin
14801 l2b0_req_2a_addr_2 = 0;
14802 for (i=0;i<8;i=i+1) begin
14803 samp_addr_l2b0_rd_q_loc_2 = dram_Ch2_l2b0_rd_q[i];
14804 l2b0_req_2a_addr_2 = (samp_addr_l2b0_rd_q_loc_2[39] && ({samp_addr_l2b0_rd_q_loc_2[35:32],samp_addr_l2b0_rd_q_loc_2[5],samp_addr_l2b0_rd_q_loc_2[28:14],samp_addr_l2b0_rd_q_loc_2[13:6],samp_addr_l2b0_rd_q_loc_2[31:29],samp_addr_l2b0_rd_q_loc_2[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr_2;
14805 end
14806
14807 dram_Ch2_l2b0_rd_req_2a_addr_vld <= l2b0_req_2a_addr_2;
14808
14809
14810end
14811
14812reg dram_Ch2_l2b0_wr_req_2a_addr_vld;
14813reg l2b0_req_2a_addr1_2;
14814reg [39:0] samp_addr_l2b0_wr_q_loc_2;
14815
14816// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14817// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14818
14819always @( dram_Ch2_l2b0_wr_q_0 or dram_Ch2_l2b0_wr_q_1 or dram_Ch2_l2b0_wr_q_2 or dram_Ch2_l2b0_wr_q_3 or
14820 dram_Ch2_l2b0_wr_q_4 or dram_Ch2_l2b0_wr_q_5 or dram_Ch2_l2b0_wr_q_6 or dram_Ch2_l2b0_wr_q_7)
14821begin
14822 l2b0_req_2a_addr1_2 = 0;
14823 for (i=0;i<8;i=i+1) begin
14824 samp_addr_l2b0_wr_q_loc_2 = dram_Ch2_l2b0_wr_q[i];
14825 l2b0_req_2a_addr1_2 = (samp_addr_l2b0_wr_q_loc_2[39] && ({samp_addr_l2b0_wr_q_loc_2[35:32],samp_addr_l2b0_wr_q_loc_2[5],samp_addr_l2b0_wr_q_loc_2[28:14],samp_addr_l2b0_wr_q_loc_2[13:6],samp_addr_l2b0_wr_q_loc_2[31:29],samp_addr_l2b0_wr_q_loc_2[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr1_2;
14826 end
14827
14828 dram_Ch2_l2b0_wr_req_2a_addr_vld <= l2b0_req_2a_addr1_2;
14829
14830
14831end
14832reg dram_Ch2_l2b1_rd_req_2a_addr_vld;
14833reg l2b1_req_2a_addr_2;
14834reg [39:0] samp_addr_l2b1_rd_q_loc_2;
14835
14836// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14837// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14838
14839always @( dram_Ch2_l2b1_rd_q_0 or dram_Ch2_l2b1_rd_q_1 or dram_Ch2_l2b1_rd_q_2 or dram_Ch2_l2b1_rd_q_3 or
14840 dram_Ch2_l2b1_rd_q_4 or dram_Ch2_l2b1_rd_q_5 or dram_Ch2_l2b1_rd_q_6 or dram_Ch2_l2b1_rd_q_7)
14841begin
14842 l2b1_req_2a_addr_2 = 0;
14843 for (i=0;i<8;i=i+1) begin
14844 samp_addr_l2b1_rd_q_loc_2 = dram_Ch2_l2b1_rd_q[i];
14845 l2b1_req_2a_addr_2 = (samp_addr_l2b1_rd_q_loc_2[39] && ({samp_addr_l2b1_rd_q_loc_2[35:32],samp_addr_l2b1_rd_q_loc_2[5],samp_addr_l2b1_rd_q_loc_2[28:14],samp_addr_l2b1_rd_q_loc_2[13:6],samp_addr_l2b1_rd_q_loc_2[31:29],samp_addr_l2b1_rd_q_loc_2[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr_2;
14846 end
14847
14848 dram_Ch2_l2b1_rd_req_2a_addr_vld <= l2b1_req_2a_addr_2;
14849
14850
14851end
14852
14853reg dram_Ch2_l2b1_wr_req_2a_addr_vld;
14854reg l2b1_req_2a_addr1_2;
14855reg [39:0] samp_addr_l2b1_wr_q_loc_2;
14856
14857// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14858// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14859
14860always @( dram_Ch2_l2b1_wr_q_0 or dram_Ch2_l2b1_wr_q_1 or dram_Ch2_l2b1_wr_q_2 or dram_Ch2_l2b1_wr_q_3 or
14861 dram_Ch2_l2b1_wr_q_4 or dram_Ch2_l2b1_wr_q_5 or dram_Ch2_l2b1_wr_q_6 or dram_Ch2_l2b1_wr_q_7)
14862begin
14863 l2b1_req_2a_addr1_2 = 0;
14864 for (i=0;i<8;i=i+1) begin
14865 samp_addr_l2b1_wr_q_loc_2 = dram_Ch2_l2b1_wr_q[i];
14866 l2b1_req_2a_addr1_2 = (samp_addr_l2b1_wr_q_loc_2[39] && ({samp_addr_l2b1_wr_q_loc_2[35:32],samp_addr_l2b1_wr_q_loc_2[5],samp_addr_l2b1_wr_q_loc_2[28:14],samp_addr_l2b1_wr_q_loc_2[13:6],samp_addr_l2b1_wr_q_loc_2[31:29],samp_addr_l2b1_wr_q_loc_2[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr1_2;
14867 end
14868
14869 dram_Ch2_l2b1_wr_req_2a_addr_vld <= l2b1_req_2a_addr1_2;
14870
14871
14872end
14873reg dram_Ch3_l2b0_rd_req_2a_addr_vld;
14874reg l2b0_req_2a_addr_3;
14875reg [39:0] samp_addr_l2b0_rd_q_loc_3;
14876
14877// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14878// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14879
14880always @( dram_Ch3_l2b0_rd_q_0 or dram_Ch3_l2b0_rd_q_1 or dram_Ch3_l2b0_rd_q_2 or dram_Ch3_l2b0_rd_q_3 or
14881 dram_Ch3_l2b0_rd_q_4 or dram_Ch3_l2b0_rd_q_5 or dram_Ch3_l2b0_rd_q_6 or dram_Ch3_l2b0_rd_q_7)
14882begin
14883 l2b0_req_2a_addr_3 = 0;
14884 for (i=0;i<8;i=i+1) begin
14885 samp_addr_l2b0_rd_q_loc_3 = dram_Ch3_l2b0_rd_q[i];
14886 l2b0_req_2a_addr_3 = (samp_addr_l2b0_rd_q_loc_3[39] && ({samp_addr_l2b0_rd_q_loc_3[35:32],samp_addr_l2b0_rd_q_loc_3[5],samp_addr_l2b0_rd_q_loc_3[28:14],samp_addr_l2b0_rd_q_loc_3[13:6],samp_addr_l2b0_rd_q_loc_3[31:29],samp_addr_l2b0_rd_q_loc_3[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr_3;
14887 end
14888
14889 dram_Ch3_l2b0_rd_req_2a_addr_vld <= l2b0_req_2a_addr_3;
14890
14891
14892end
14893
14894reg dram_Ch3_l2b0_wr_req_2a_addr_vld;
14895reg l2b0_req_2a_addr1_3;
14896reg [39:0] samp_addr_l2b0_wr_q_loc_3;
14897
14898// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14899// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14900
14901always @( dram_Ch3_l2b0_wr_q_0 or dram_Ch3_l2b0_wr_q_1 or dram_Ch3_l2b0_wr_q_2 or dram_Ch3_l2b0_wr_q_3 or
14902 dram_Ch3_l2b0_wr_q_4 or dram_Ch3_l2b0_wr_q_5 or dram_Ch3_l2b0_wr_q_6 or dram_Ch3_l2b0_wr_q_7)
14903begin
14904 l2b0_req_2a_addr1_3 = 0;
14905 for (i=0;i<8;i=i+1) begin
14906 samp_addr_l2b0_wr_q_loc_3 = dram_Ch3_l2b0_wr_q[i];
14907 l2b0_req_2a_addr1_3 = (samp_addr_l2b0_wr_q_loc_3[39] && ({samp_addr_l2b0_wr_q_loc_3[35:32],samp_addr_l2b0_wr_q_loc_3[5],samp_addr_l2b0_wr_q_loc_3[28:14],samp_addr_l2b0_wr_q_loc_3[13:6],samp_addr_l2b0_wr_q_loc_3[31:29],samp_addr_l2b0_wr_q_loc_3[4]} == SCHMOO_RD_WR_ADDR)) || l2b0_req_2a_addr1_3;
14908 end
14909
14910 dram_Ch3_l2b0_wr_req_2a_addr_vld <= l2b0_req_2a_addr1_3;
14911
14912
14913end
14914reg dram_Ch3_l2b1_rd_req_2a_addr_vld;
14915reg l2b1_req_2a_addr_3;
14916reg [39:0] samp_addr_l2b1_rd_q_loc_3;
14917
14918// (que_rd_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14919// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14920
14921always @( dram_Ch3_l2b1_rd_q_0 or dram_Ch3_l2b1_rd_q_1 or dram_Ch3_l2b1_rd_q_2 or dram_Ch3_l2b1_rd_q_3 or
14922 dram_Ch3_l2b1_rd_q_4 or dram_Ch3_l2b1_rd_q_5 or dram_Ch3_l2b1_rd_q_6 or dram_Ch3_l2b1_rd_q_7)
14923begin
14924 l2b1_req_2a_addr_3 = 0;
14925 for (i=0;i<8;i=i+1) begin
14926 samp_addr_l2b1_rd_q_loc_3 = dram_Ch3_l2b1_rd_q[i];
14927 l2b1_req_2a_addr_3 = (samp_addr_l2b1_rd_q_loc_3[39] && ({samp_addr_l2b1_rd_q_loc_3[35:32],samp_addr_l2b1_rd_q_loc_3[5],samp_addr_l2b1_rd_q_loc_3[28:14],samp_addr_l2b1_rd_q_loc_3[13:6],samp_addr_l2b1_rd_q_loc_3[31:29],samp_addr_l2b1_rd_q_loc_3[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr_3;
14928 end
14929
14930 dram_Ch3_l2b1_rd_req_2a_addr_vld <= l2b1_req_2a_addr_3;
14931
14932
14933end
14934
14935reg dram_Ch3_l2b1_wr_req_2a_addr_vld;
14936reg l2b1_req_2a_addr1_3;
14937reg [39:0] samp_addr_l2b1_wr_q_loc_3;
14938
14939// (que_wr_addr_picked[31:0] == {writeqbank0addr0[35], writeqbank0addr0[33:6],
14940// writeqbank0addr0[2:0]}) & writeqbank0vld0_arb |
14941
14942always @( dram_Ch3_l2b1_wr_q_0 or dram_Ch3_l2b1_wr_q_1 or dram_Ch3_l2b1_wr_q_2 or dram_Ch3_l2b1_wr_q_3 or
14943 dram_Ch3_l2b1_wr_q_4 or dram_Ch3_l2b1_wr_q_5 or dram_Ch3_l2b1_wr_q_6 or dram_Ch3_l2b1_wr_q_7)
14944begin
14945 l2b1_req_2a_addr1_3 = 0;
14946 for (i=0;i<8;i=i+1) begin
14947 samp_addr_l2b1_wr_q_loc_3 = dram_Ch3_l2b1_wr_q[i];
14948 l2b1_req_2a_addr1_3 = (samp_addr_l2b1_wr_q_loc_3[39] && ({samp_addr_l2b1_wr_q_loc_3[35:32],samp_addr_l2b1_wr_q_loc_3[5],samp_addr_l2b1_wr_q_loc_3[28:14],samp_addr_l2b1_wr_q_loc_3[13:6],samp_addr_l2b1_wr_q_loc_3[31:29],samp_addr_l2b1_wr_q_loc_3[4]} == SCHMOO_RD_WR_ADDR)) || l2b1_req_2a_addr1_3;
14949 end
14950
14951 dram_Ch3_l2b1_wr_req_2a_addr_vld <= l2b1_req_2a_addr1_3;
14952
14953
14954end
14955
14956// -------- Monitor scrub to the same address as wr read
14957// Scrub address asssumed valid from scrb read to write.
14958// We are xing between the scrub happening and a valid data
14959// to same address in rd/wr q ---------------
14960
14961reg dram_Ch0_scrb_req_vld;
14962wire dram_Ch0_scrb_req_2a_addr_vld;
14963
14964
14965always @(posedge (`MCU_CLK && enabled))
14966begin
14967 if (~dram_rst_l)
14968 begin
14969 dram_Ch0_scrb_req_vld <= 1'b0;
14970 end
14971 else begin
14972 if (dram_Ch0_que_scrb_picked && dram_Ch0_que_scrb_rd_picked && dram_Ch0_que_ras_bank_picked_en) begin
14973 dram_Ch0_scrb_req_vld <= 1'b1;
14974 end else if (dram_Ch0_que_scrb_write_req) begin
14975 dram_Ch0_scrb_req_vld <= 1'b0;
14976 end
14977 end
14978end
14979
14980
14981// MAQ assign dram_Ch0_scrb_req_2a_addr_vld = ({dram_Ch0_que_scrb_addr_picked[35], dram_Ch0_que_scrb_addr_picked[33:0]} == SCHMOO_SCRB_ADDR) && dram_Ch0_scrb_req_vld;
14982assign dram_Ch0_scrb_req_2a_addr_vld = (dram_Ch0_que_scrb_addr_picked[31:0] == SCHMOO_SCRB_ADDR) && (dram_Ch0_scrb_req_vld === 1'b1);
14983
14984reg dram_Ch1_scrb_req_vld;
14985wire dram_Ch1_scrb_req_2a_addr_vld;
14986
14987
14988always @(posedge (`MCU_CLK && enabled))
14989begin
14990 if (~dram_rst_l)
14991 begin
14992 dram_Ch1_scrb_req_vld <= 1'b0;
14993 end
14994 else begin
14995 if (dram_Ch1_que_scrb_picked && dram_Ch1_que_scrb_rd_picked && dram_Ch1_que_ras_bank_picked_en) begin
14996 dram_Ch1_scrb_req_vld <= 1'b1;
14997 end else if (dram_Ch1_que_scrb_write_req) begin
14998 dram_Ch1_scrb_req_vld <= 1'b0;
14999 end
15000 end
15001end
15002
15003
15004// MAQ assign dram_Ch1_scrb_req_2a_addr_vld = ({dram_Ch1_que_scrb_addr_picked[35], dram_Ch1_que_scrb_addr_picked[33:0]} == SCHMOO_SCRB_ADDR) && dram_Ch1_scrb_req_vld;
15005assign dram_Ch1_scrb_req_2a_addr_vld = (dram_Ch1_que_scrb_addr_picked[31:0] == SCHMOO_SCRB_ADDR) && (dram_Ch1_scrb_req_vld === 1'b1);
15006
15007reg dram_Ch2_scrb_req_vld;
15008wire dram_Ch2_scrb_req_2a_addr_vld;
15009
15010
15011always @(posedge (`MCU_CLK && enabled))
15012begin
15013 if (~dram_rst_l)
15014 begin
15015 dram_Ch2_scrb_req_vld <= 1'b0;
15016 end
15017 else begin
15018 if (dram_Ch2_que_scrb_picked && dram_Ch2_que_scrb_rd_picked && dram_Ch2_que_ras_bank_picked_en) begin
15019 dram_Ch2_scrb_req_vld <= 1'b1;
15020 end else if (dram_Ch2_que_scrb_write_req) begin
15021 dram_Ch2_scrb_req_vld <= 1'b0;
15022 end
15023 end
15024end
15025
15026
15027// MAQ assign dram_Ch2_scrb_req_2a_addr_vld = ({dram_Ch2_que_scrb_addr_picked[35], dram_Ch2_que_scrb_addr_picked[33:0]} == SCHMOO_SCRB_ADDR) && dram_Ch2_scrb_req_vld;
15028assign dram_Ch2_scrb_req_2a_addr_vld = (dram_Ch2_que_scrb_addr_picked[31:0] == SCHMOO_SCRB_ADDR) && (dram_Ch2_scrb_req_vld === 1'b1);
15029
15030reg dram_Ch3_scrb_req_vld;
15031wire dram_Ch3_scrb_req_2a_addr_vld;
15032
15033
15034always @(posedge (`MCU_CLK && enabled))
15035begin
15036 if (~dram_rst_l)
15037 begin
15038 dram_Ch3_scrb_req_vld <= 1'b0;
15039 end
15040 else begin
15041 if (dram_Ch3_que_scrb_picked && dram_Ch3_que_scrb_rd_picked && dram_Ch3_que_ras_bank_picked_en) begin
15042 dram_Ch3_scrb_req_vld <= 1'b1;
15043 end else if (dram_Ch3_que_scrb_write_req) begin
15044 dram_Ch3_scrb_req_vld <= 1'b0;
15045 end
15046 end
15047end
15048
15049
15050// MAQ assign dram_Ch3_scrb_req_2a_addr_vld = ({dram_Ch3_que_scrb_addr_picked[35], dram_Ch3_que_scrb_addr_picked[33:0]} == SCHMOO_SCRB_ADDR) && dram_Ch3_scrb_req_vld;
15051assign dram_Ch3_scrb_req_2a_addr_vld = (dram_Ch3_que_scrb_addr_picked[31:0] == SCHMOO_SCRB_ADDR) && (dram_Ch3_scrb_req_vld === 1'b1);
15052
15053
15054// Monitor Traffic on each CS
15055reg [10:0] dram_Ch0_cs0_bank_req_cntr [7:0];
15056wire [10:0] dram_Ch0_cs0_bank_req_cntr_0 = dram_Ch0_cs0_bank_req_cntr[0];
15057wire [10:0] dram_Ch0_cs0_bank_req_cntr_1 = dram_Ch0_cs0_bank_req_cntr[1];
15058wire [10:0] dram_Ch0_cs0_bank_req_cntr_2 = dram_Ch0_cs0_bank_req_cntr[2];
15059wire [10:0] dram_Ch0_cs0_bank_req_cntr_3 = dram_Ch0_cs0_bank_req_cntr[3];
15060wire [10:0] dram_Ch0_cs0_bank_req_cntr_4 = dram_Ch0_cs0_bank_req_cntr[4];
15061wire [10:0] dram_Ch0_cs0_bank_req_cntr_5 = dram_Ch0_cs0_bank_req_cntr[5];
15062wire [10:0] dram_Ch0_cs0_bank_req_cntr_6 = dram_Ch0_cs0_bank_req_cntr[6];
15063wire [10:0] dram_Ch0_cs0_bank_req_cntr_7 = dram_Ch0_cs0_bank_req_cntr[7];
15064reg [10:0] dram_Ch0_cs1_bank_req_cntr [7:0];
15065wire [10:0] dram_Ch0_cs1_bank_req_cntr_0 = dram_Ch0_cs1_bank_req_cntr[0];
15066wire [10:0] dram_Ch0_cs1_bank_req_cntr_1 = dram_Ch0_cs1_bank_req_cntr[1];
15067wire [10:0] dram_Ch0_cs1_bank_req_cntr_2 = dram_Ch0_cs1_bank_req_cntr[2];
15068wire [10:0] dram_Ch0_cs1_bank_req_cntr_3 = dram_Ch0_cs1_bank_req_cntr[3];
15069wire [10:0] dram_Ch0_cs1_bank_req_cntr_4 = dram_Ch0_cs1_bank_req_cntr[4];
15070wire [10:0] dram_Ch0_cs1_bank_req_cntr_5 = dram_Ch0_cs1_bank_req_cntr[5];
15071wire [10:0] dram_Ch0_cs1_bank_req_cntr_6 = dram_Ch0_cs1_bank_req_cntr[6];
15072wire [10:0] dram_Ch0_cs1_bank_req_cntr_7 = dram_Ch0_cs1_bank_req_cntr[7];
15073reg [10:0] dram_Ch0_cs2_bank_req_cntr [7:0];
15074wire [10:0] dram_Ch0_cs2_bank_req_cntr_0 = dram_Ch0_cs2_bank_req_cntr[0];
15075wire [10:0] dram_Ch0_cs2_bank_req_cntr_1 = dram_Ch0_cs2_bank_req_cntr[1];
15076wire [10:0] dram_Ch0_cs2_bank_req_cntr_2 = dram_Ch0_cs2_bank_req_cntr[2];
15077wire [10:0] dram_Ch0_cs2_bank_req_cntr_3 = dram_Ch0_cs2_bank_req_cntr[3];
15078wire [10:0] dram_Ch0_cs2_bank_req_cntr_4 = dram_Ch0_cs2_bank_req_cntr[4];
15079wire [10:0] dram_Ch0_cs2_bank_req_cntr_5 = dram_Ch0_cs2_bank_req_cntr[5];
15080wire [10:0] dram_Ch0_cs2_bank_req_cntr_6 = dram_Ch0_cs2_bank_req_cntr[6];
15081wire [10:0] dram_Ch0_cs2_bank_req_cntr_7 = dram_Ch0_cs2_bank_req_cntr[7];
15082reg [10:0] dram_Ch0_cs3_bank_req_cntr [7:0];
15083wire [10:0] dram_Ch0_cs3_bank_req_cntr_0 = dram_Ch0_cs3_bank_req_cntr[0];
15084wire [10:0] dram_Ch0_cs3_bank_req_cntr_1 = dram_Ch0_cs3_bank_req_cntr[1];
15085wire [10:0] dram_Ch0_cs3_bank_req_cntr_2 = dram_Ch0_cs3_bank_req_cntr[2];
15086wire [10:0] dram_Ch0_cs3_bank_req_cntr_3 = dram_Ch0_cs3_bank_req_cntr[3];
15087wire [10:0] dram_Ch0_cs3_bank_req_cntr_4 = dram_Ch0_cs3_bank_req_cntr[4];
15088wire [10:0] dram_Ch0_cs3_bank_req_cntr_5 = dram_Ch0_cs3_bank_req_cntr[5];
15089wire [10:0] dram_Ch0_cs3_bank_req_cntr_6 = dram_Ch0_cs3_bank_req_cntr[6];
15090wire [10:0] dram_Ch0_cs3_bank_req_cntr_7 = dram_Ch0_cs3_bank_req_cntr[7];
15091
15092
15093/*************************************************************************************************
15094always @ (posedge (`MCU_CLK && enabled))
15095begin
15096 if (~dram_rst_l)
15097 begin
15098 for(i=0;i<8;i=i+1) begin
15099 dram_Ch0_cs0_bank_req_cntr[i] = 0;
15100 dram_Ch0_cs1_bank_req_cntr[i] = 0;
15101 dram_Ch0_cs2_bank_req_cntr[i] = 0;
15102 dram_Ch0_cs3_bank_req_cntr[i] = 0;
15103 end
15104 end
15105 else
15106 begin
15107 if ( !dram_Ch0_RAS_L && dram_Ch0_CAS_L && dram_Ch0_WE_L ) begin
15108 case (dram_Ch0_CS_L)
15109 4'b1110 : dram_Ch0_cs0_bank_req_cntr[dram_Ch0_BA] = dram_Ch0_cs0_bank_req_cntr[dram_Ch0_BA] + 1;
15110 4'b1101 : dram_Ch0_cs1_bank_req_cntr[dram_Ch0_BA] = dram_Ch0_cs1_bank_req_cntr[dram_Ch0_BA] + 1;
15111 4'b1011 : dram_Ch0_cs2_bank_req_cntr[dram_Ch0_BA] = dram_Ch0_cs2_bank_req_cntr[dram_Ch0_BA] + 1;
15112 4'b0111 : dram_Ch0_cs3_bank_req_cntr[dram_Ch0_BA] = dram_Ch0_cs3_bank_req_cntr[dram_Ch0_BA] + 1;
15113 default : begin
15114 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch0:l2b2 ");
15115 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d CS_L = %x ", $time, dram_Ch0_CS_L);
15116 finish_test(" Wrong CS : CS_L should not have more that 1 device selected ", 0);
15117 end
15118
15119 endcase
15120 end
15121 end
15122end
15123***************************************************************************************************/
15124reg [10:0] dram_Ch1_cs0_bank_req_cntr [7:0];
15125wire [10:0] dram_Ch1_cs0_bank_req_cntr_0 = dram_Ch1_cs0_bank_req_cntr[0];
15126wire [10:0] dram_Ch1_cs0_bank_req_cntr_1 = dram_Ch1_cs0_bank_req_cntr[1];
15127wire [10:0] dram_Ch1_cs0_bank_req_cntr_2 = dram_Ch1_cs0_bank_req_cntr[2];
15128wire [10:0] dram_Ch1_cs0_bank_req_cntr_3 = dram_Ch1_cs0_bank_req_cntr[3];
15129wire [10:0] dram_Ch1_cs0_bank_req_cntr_4 = dram_Ch1_cs0_bank_req_cntr[4];
15130wire [10:0] dram_Ch1_cs0_bank_req_cntr_5 = dram_Ch1_cs0_bank_req_cntr[5];
15131wire [10:0] dram_Ch1_cs0_bank_req_cntr_6 = dram_Ch1_cs0_bank_req_cntr[6];
15132wire [10:0] dram_Ch1_cs0_bank_req_cntr_7 = dram_Ch1_cs0_bank_req_cntr[7];
15133reg [10:0] dram_Ch1_cs1_bank_req_cntr [7:0];
15134wire [10:0] dram_Ch1_cs1_bank_req_cntr_0 = dram_Ch1_cs1_bank_req_cntr[0];
15135wire [10:0] dram_Ch1_cs1_bank_req_cntr_1 = dram_Ch1_cs1_bank_req_cntr[1];
15136wire [10:0] dram_Ch1_cs1_bank_req_cntr_2 = dram_Ch1_cs1_bank_req_cntr[2];
15137wire [10:0] dram_Ch1_cs1_bank_req_cntr_3 = dram_Ch1_cs1_bank_req_cntr[3];
15138wire [10:0] dram_Ch1_cs1_bank_req_cntr_4 = dram_Ch1_cs1_bank_req_cntr[4];
15139wire [10:0] dram_Ch1_cs1_bank_req_cntr_5 = dram_Ch1_cs1_bank_req_cntr[5];
15140wire [10:0] dram_Ch1_cs1_bank_req_cntr_6 = dram_Ch1_cs1_bank_req_cntr[6];
15141wire [10:0] dram_Ch1_cs1_bank_req_cntr_7 = dram_Ch1_cs1_bank_req_cntr[7];
15142reg [10:0] dram_Ch1_cs2_bank_req_cntr [7:0];
15143wire [10:0] dram_Ch1_cs2_bank_req_cntr_0 = dram_Ch1_cs2_bank_req_cntr[0];
15144wire [10:0] dram_Ch1_cs2_bank_req_cntr_1 = dram_Ch1_cs2_bank_req_cntr[1];
15145wire [10:0] dram_Ch1_cs2_bank_req_cntr_2 = dram_Ch1_cs2_bank_req_cntr[2];
15146wire [10:0] dram_Ch1_cs2_bank_req_cntr_3 = dram_Ch1_cs2_bank_req_cntr[3];
15147wire [10:0] dram_Ch1_cs2_bank_req_cntr_4 = dram_Ch1_cs2_bank_req_cntr[4];
15148wire [10:0] dram_Ch1_cs2_bank_req_cntr_5 = dram_Ch1_cs2_bank_req_cntr[5];
15149wire [10:0] dram_Ch1_cs2_bank_req_cntr_6 = dram_Ch1_cs2_bank_req_cntr[6];
15150wire [10:0] dram_Ch1_cs2_bank_req_cntr_7 = dram_Ch1_cs2_bank_req_cntr[7];
15151reg [10:0] dram_Ch1_cs3_bank_req_cntr [7:0];
15152wire [10:0] dram_Ch1_cs3_bank_req_cntr_0 = dram_Ch1_cs3_bank_req_cntr[0];
15153wire [10:0] dram_Ch1_cs3_bank_req_cntr_1 = dram_Ch1_cs3_bank_req_cntr[1];
15154wire [10:0] dram_Ch1_cs3_bank_req_cntr_2 = dram_Ch1_cs3_bank_req_cntr[2];
15155wire [10:0] dram_Ch1_cs3_bank_req_cntr_3 = dram_Ch1_cs3_bank_req_cntr[3];
15156wire [10:0] dram_Ch1_cs3_bank_req_cntr_4 = dram_Ch1_cs3_bank_req_cntr[4];
15157wire [10:0] dram_Ch1_cs3_bank_req_cntr_5 = dram_Ch1_cs3_bank_req_cntr[5];
15158wire [10:0] dram_Ch1_cs3_bank_req_cntr_6 = dram_Ch1_cs3_bank_req_cntr[6];
15159wire [10:0] dram_Ch1_cs3_bank_req_cntr_7 = dram_Ch1_cs3_bank_req_cntr[7];
15160
15161
15162/*************************************************************************************************
15163always @ (posedge (`MCU_CLK && enabled))
15164begin
15165 if (~dram_rst_l)
15166 begin
15167 for(i=0;i<8;i=i+1) begin
15168 dram_Ch1_cs0_bank_req_cntr[i] = 0;
15169 dram_Ch1_cs1_bank_req_cntr[i] = 0;
15170 dram_Ch1_cs2_bank_req_cntr[i] = 0;
15171 dram_Ch1_cs3_bank_req_cntr[i] = 0;
15172 end
15173 end
15174 else
15175 begin
15176 if ( !dram_Ch1_RAS_L && dram_Ch1_CAS_L && dram_Ch1_WE_L ) begin
15177 case (dram_Ch1_CS_L)
15178 4'b1110 : dram_Ch1_cs0_bank_req_cntr[dram_Ch1_BA] = dram_Ch1_cs0_bank_req_cntr[dram_Ch1_BA] + 1;
15179 4'b1101 : dram_Ch1_cs1_bank_req_cntr[dram_Ch1_BA] = dram_Ch1_cs1_bank_req_cntr[dram_Ch1_BA] + 1;
15180 4'b1011 : dram_Ch1_cs2_bank_req_cntr[dram_Ch1_BA] = dram_Ch1_cs2_bank_req_cntr[dram_Ch1_BA] + 1;
15181 4'b0111 : dram_Ch1_cs3_bank_req_cntr[dram_Ch1_BA] = dram_Ch1_cs3_bank_req_cntr[dram_Ch1_BA] + 1;
15182 default : begin
15183 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch1:l2b2 ");
15184 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d CS_L = %x ", $time, dram_Ch1_CS_L);
15185 finish_test(" Wrong CS : CS_L should not have more that 1 device selected ", 1);
15186 end
15187
15188 endcase
15189 end
15190 end
15191end
15192***************************************************************************************************/
15193reg [10:0] dram_Ch2_cs0_bank_req_cntr [7:0];
15194wire [10:0] dram_Ch2_cs0_bank_req_cntr_0 = dram_Ch2_cs0_bank_req_cntr[0];
15195wire [10:0] dram_Ch2_cs0_bank_req_cntr_1 = dram_Ch2_cs0_bank_req_cntr[1];
15196wire [10:0] dram_Ch2_cs0_bank_req_cntr_2 = dram_Ch2_cs0_bank_req_cntr[2];
15197wire [10:0] dram_Ch2_cs0_bank_req_cntr_3 = dram_Ch2_cs0_bank_req_cntr[3];
15198wire [10:0] dram_Ch2_cs0_bank_req_cntr_4 = dram_Ch2_cs0_bank_req_cntr[4];
15199wire [10:0] dram_Ch2_cs0_bank_req_cntr_5 = dram_Ch2_cs0_bank_req_cntr[5];
15200wire [10:0] dram_Ch2_cs0_bank_req_cntr_6 = dram_Ch2_cs0_bank_req_cntr[6];
15201wire [10:0] dram_Ch2_cs0_bank_req_cntr_7 = dram_Ch2_cs0_bank_req_cntr[7];
15202reg [10:0] dram_Ch2_cs1_bank_req_cntr [7:0];
15203wire [10:0] dram_Ch2_cs1_bank_req_cntr_0 = dram_Ch2_cs1_bank_req_cntr[0];
15204wire [10:0] dram_Ch2_cs1_bank_req_cntr_1 = dram_Ch2_cs1_bank_req_cntr[1];
15205wire [10:0] dram_Ch2_cs1_bank_req_cntr_2 = dram_Ch2_cs1_bank_req_cntr[2];
15206wire [10:0] dram_Ch2_cs1_bank_req_cntr_3 = dram_Ch2_cs1_bank_req_cntr[3];
15207wire [10:0] dram_Ch2_cs1_bank_req_cntr_4 = dram_Ch2_cs1_bank_req_cntr[4];
15208wire [10:0] dram_Ch2_cs1_bank_req_cntr_5 = dram_Ch2_cs1_bank_req_cntr[5];
15209wire [10:0] dram_Ch2_cs1_bank_req_cntr_6 = dram_Ch2_cs1_bank_req_cntr[6];
15210wire [10:0] dram_Ch2_cs1_bank_req_cntr_7 = dram_Ch2_cs1_bank_req_cntr[7];
15211reg [10:0] dram_Ch2_cs2_bank_req_cntr [7:0];
15212wire [10:0] dram_Ch2_cs2_bank_req_cntr_0 = dram_Ch2_cs2_bank_req_cntr[0];
15213wire [10:0] dram_Ch2_cs2_bank_req_cntr_1 = dram_Ch2_cs2_bank_req_cntr[1];
15214wire [10:0] dram_Ch2_cs2_bank_req_cntr_2 = dram_Ch2_cs2_bank_req_cntr[2];
15215wire [10:0] dram_Ch2_cs2_bank_req_cntr_3 = dram_Ch2_cs2_bank_req_cntr[3];
15216wire [10:0] dram_Ch2_cs2_bank_req_cntr_4 = dram_Ch2_cs2_bank_req_cntr[4];
15217wire [10:0] dram_Ch2_cs2_bank_req_cntr_5 = dram_Ch2_cs2_bank_req_cntr[5];
15218wire [10:0] dram_Ch2_cs2_bank_req_cntr_6 = dram_Ch2_cs2_bank_req_cntr[6];
15219wire [10:0] dram_Ch2_cs2_bank_req_cntr_7 = dram_Ch2_cs2_bank_req_cntr[7];
15220reg [10:0] dram_Ch2_cs3_bank_req_cntr [7:0];
15221wire [10:0] dram_Ch2_cs3_bank_req_cntr_0 = dram_Ch2_cs3_bank_req_cntr[0];
15222wire [10:0] dram_Ch2_cs3_bank_req_cntr_1 = dram_Ch2_cs3_bank_req_cntr[1];
15223wire [10:0] dram_Ch2_cs3_bank_req_cntr_2 = dram_Ch2_cs3_bank_req_cntr[2];
15224wire [10:0] dram_Ch2_cs3_bank_req_cntr_3 = dram_Ch2_cs3_bank_req_cntr[3];
15225wire [10:0] dram_Ch2_cs3_bank_req_cntr_4 = dram_Ch2_cs3_bank_req_cntr[4];
15226wire [10:0] dram_Ch2_cs3_bank_req_cntr_5 = dram_Ch2_cs3_bank_req_cntr[5];
15227wire [10:0] dram_Ch2_cs3_bank_req_cntr_6 = dram_Ch2_cs3_bank_req_cntr[6];
15228wire [10:0] dram_Ch2_cs3_bank_req_cntr_7 = dram_Ch2_cs3_bank_req_cntr[7];
15229
15230
15231/*************************************************************************************************
15232always @ (posedge (`MCU_CLK && enabled))
15233begin
15234 if (~dram_rst_l)
15235 begin
15236 for(i=0;i<8;i=i+1) begin
15237 dram_Ch2_cs0_bank_req_cntr[i] = 0;
15238 dram_Ch2_cs1_bank_req_cntr[i] = 0;
15239 dram_Ch2_cs2_bank_req_cntr[i] = 0;
15240 dram_Ch2_cs3_bank_req_cntr[i] = 0;
15241 end
15242 end
15243 else
15244 begin
15245 if ( !dram_Ch2_RAS_L && dram_Ch2_CAS_L && dram_Ch2_WE_L ) begin
15246 case (dram_Ch2_CS_L)
15247 4'b1110 : dram_Ch2_cs0_bank_req_cntr[dram_Ch2_BA] = dram_Ch2_cs0_bank_req_cntr[dram_Ch2_BA] + 1;
15248 4'b1101 : dram_Ch2_cs1_bank_req_cntr[dram_Ch2_BA] = dram_Ch2_cs1_bank_req_cntr[dram_Ch2_BA] + 1;
15249 4'b1011 : dram_Ch2_cs2_bank_req_cntr[dram_Ch2_BA] = dram_Ch2_cs2_bank_req_cntr[dram_Ch2_BA] + 1;
15250 4'b0111 : dram_Ch2_cs3_bank_req_cntr[dram_Ch2_BA] = dram_Ch2_cs3_bank_req_cntr[dram_Ch2_BA] + 1;
15251 default : begin
15252 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch2:l2b2 ");
15253 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d CS_L = %x ", $time, dram_Ch2_CS_L);
15254 finish_test(" Wrong CS : CS_L should not have more that 1 device selected ", 2);
15255 end
15256
15257 endcase
15258 end
15259 end
15260end
15261***************************************************************************************************/
15262reg [10:0] dram_Ch3_cs0_bank_req_cntr [7:0];
15263wire [10:0] dram_Ch3_cs0_bank_req_cntr_0 = dram_Ch3_cs0_bank_req_cntr[0];
15264wire [10:0] dram_Ch3_cs0_bank_req_cntr_1 = dram_Ch3_cs0_bank_req_cntr[1];
15265wire [10:0] dram_Ch3_cs0_bank_req_cntr_2 = dram_Ch3_cs0_bank_req_cntr[2];
15266wire [10:0] dram_Ch3_cs0_bank_req_cntr_3 = dram_Ch3_cs0_bank_req_cntr[3];
15267wire [10:0] dram_Ch3_cs0_bank_req_cntr_4 = dram_Ch3_cs0_bank_req_cntr[4];
15268wire [10:0] dram_Ch3_cs0_bank_req_cntr_5 = dram_Ch3_cs0_bank_req_cntr[5];
15269wire [10:0] dram_Ch3_cs0_bank_req_cntr_6 = dram_Ch3_cs0_bank_req_cntr[6];
15270wire [10:0] dram_Ch3_cs0_bank_req_cntr_7 = dram_Ch3_cs0_bank_req_cntr[7];
15271reg [10:0] dram_Ch3_cs1_bank_req_cntr [7:0];
15272wire [10:0] dram_Ch3_cs1_bank_req_cntr_0 = dram_Ch3_cs1_bank_req_cntr[0];
15273wire [10:0] dram_Ch3_cs1_bank_req_cntr_1 = dram_Ch3_cs1_bank_req_cntr[1];
15274wire [10:0] dram_Ch3_cs1_bank_req_cntr_2 = dram_Ch3_cs1_bank_req_cntr[2];
15275wire [10:0] dram_Ch3_cs1_bank_req_cntr_3 = dram_Ch3_cs1_bank_req_cntr[3];
15276wire [10:0] dram_Ch3_cs1_bank_req_cntr_4 = dram_Ch3_cs1_bank_req_cntr[4];
15277wire [10:0] dram_Ch3_cs1_bank_req_cntr_5 = dram_Ch3_cs1_bank_req_cntr[5];
15278wire [10:0] dram_Ch3_cs1_bank_req_cntr_6 = dram_Ch3_cs1_bank_req_cntr[6];
15279wire [10:0] dram_Ch3_cs1_bank_req_cntr_7 = dram_Ch3_cs1_bank_req_cntr[7];
15280reg [10:0] dram_Ch3_cs2_bank_req_cntr [7:0];
15281wire [10:0] dram_Ch3_cs2_bank_req_cntr_0 = dram_Ch3_cs2_bank_req_cntr[0];
15282wire [10:0] dram_Ch3_cs2_bank_req_cntr_1 = dram_Ch3_cs2_bank_req_cntr[1];
15283wire [10:0] dram_Ch3_cs2_bank_req_cntr_2 = dram_Ch3_cs2_bank_req_cntr[2];
15284wire [10:0] dram_Ch3_cs2_bank_req_cntr_3 = dram_Ch3_cs2_bank_req_cntr[3];
15285wire [10:0] dram_Ch3_cs2_bank_req_cntr_4 = dram_Ch3_cs2_bank_req_cntr[4];
15286wire [10:0] dram_Ch3_cs2_bank_req_cntr_5 = dram_Ch3_cs2_bank_req_cntr[5];
15287wire [10:0] dram_Ch3_cs2_bank_req_cntr_6 = dram_Ch3_cs2_bank_req_cntr[6];
15288wire [10:0] dram_Ch3_cs2_bank_req_cntr_7 = dram_Ch3_cs2_bank_req_cntr[7];
15289reg [10:0] dram_Ch3_cs3_bank_req_cntr [7:0];
15290wire [10:0] dram_Ch3_cs3_bank_req_cntr_0 = dram_Ch3_cs3_bank_req_cntr[0];
15291wire [10:0] dram_Ch3_cs3_bank_req_cntr_1 = dram_Ch3_cs3_bank_req_cntr[1];
15292wire [10:0] dram_Ch3_cs3_bank_req_cntr_2 = dram_Ch3_cs3_bank_req_cntr[2];
15293wire [10:0] dram_Ch3_cs3_bank_req_cntr_3 = dram_Ch3_cs3_bank_req_cntr[3];
15294wire [10:0] dram_Ch3_cs3_bank_req_cntr_4 = dram_Ch3_cs3_bank_req_cntr[4];
15295wire [10:0] dram_Ch3_cs3_bank_req_cntr_5 = dram_Ch3_cs3_bank_req_cntr[5];
15296wire [10:0] dram_Ch3_cs3_bank_req_cntr_6 = dram_Ch3_cs3_bank_req_cntr[6];
15297wire [10:0] dram_Ch3_cs3_bank_req_cntr_7 = dram_Ch3_cs3_bank_req_cntr[7];
15298
15299
15300/*************************************************************************************************
15301always @ (posedge (`MCU_CLK && enabled))
15302begin
15303 if (~dram_rst_l)
15304 begin
15305 for(i=0;i<8;i=i+1) begin
15306 dram_Ch3_cs0_bank_req_cntr[i] = 0;
15307 dram_Ch3_cs1_bank_req_cntr[i] = 0;
15308 dram_Ch3_cs2_bank_req_cntr[i] = 0;
15309 dram_Ch3_cs3_bank_req_cntr[i] = 0;
15310 end
15311 end
15312 else
15313 begin
15314 if ( !dram_Ch3_RAS_L && dram_Ch3_CAS_L && dram_Ch3_WE_L ) begin
15315 case (dram_Ch3_CS_L)
15316 4'b1110 : dram_Ch3_cs0_bank_req_cntr[dram_Ch3_BA] = dram_Ch3_cs0_bank_req_cntr[dram_Ch3_BA] + 1;
15317 4'b1101 : dram_Ch3_cs1_bank_req_cntr[dram_Ch3_BA] = dram_Ch3_cs1_bank_req_cntr[dram_Ch3_BA] + 1;
15318 4'b1011 : dram_Ch3_cs2_bank_req_cntr[dram_Ch3_BA] = dram_Ch3_cs2_bank_req_cntr[dram_Ch3_BA] + 1;
15319 4'b0111 : dram_Ch3_cs3_bank_req_cntr[dram_Ch3_BA] = dram_Ch3_cs3_bank_req_cntr[dram_Ch3_BA] + 1;
15320 default : begin
15321 `PR_DEBUG("mcusat_cov_mon", `DEBUG, " : In dram channel Ch3:l2b2 ");
15322 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "At time %0d CS_L = %x ", $time, dram_Ch3_CS_L);
15323 finish_test(" Wrong CS : CS_L should not have more that 1 device selected ", 3);
15324 end
15325
15326 endcase
15327 end
15328 end
15329end
15330***************************************************************************************************/
15331
15332
15333// ----- MONITOR TO PRINT OUT L2-DRAM RD/WR AND RD RESPONSE --------
15334
15335
15336
15337reg [39:0] l2b0_this_addr_0;
15338reg l2b0_dvld_dly1_0;
15339reg l2b0_dvld_dly2_0;
15340reg l2b0_dvld_dly3_0;
15341reg [2:0] l2b0_rqid_dly1_0;
15342reg [2:0] l2b0_rqid_dly2_0;
15343reg [2:0] l2b0_rqid_dly3_0;
15344// MAQ reg [1:0] ch_0_l2b0;
15345
15346reg [2:0] l2b0_wr_data_cntr_0;
15347reg [511:0] l2b0_wr_data_0;
15348reg [39:0] l2b0_wr_addr_mon_0;
15349
15350reg [39:0] dram_Ch0_l2b0_addr_store [7:0];
15351
15352initial
15353begin
15354 l2b0_wr_data_cntr_0 = 0;
15355 l2b0_wr_data_0 = 0;
15356 l2b0_wr_addr_mon_0 = 0;
15357end
15358
15359always @ (posedge (cmp_clk && enabled))
15360begin
15361 if (cmp_rst_l) begin
15362
15363 l2b0_dvld_dly1_0 <= dram_Ch0_l2b0_dram_sctag_data_vld;
15364 l2b0_dvld_dly2_0 <= l2b0_dvld_dly1_0;
15365 l2b0_dvld_dly3_0 <= l2b0_dvld_dly2_0;
15366
15367 l2b0_rqid_dly1_0 <= dram_Ch0_l2b0_dram_sctag_rd_req_id;
15368 l2b0_rqid_dly2_0 <= l2b0_rqid_dly1_0;
15369 l2b0_rqid_dly3_0 <= l2b0_rqid_dly2_0;
15370
15371 l2b0_this_addr_0 = {dram_Ch0_l2b0_sctag_dram_addr, 5'b0};
15372 //l2b0_this_addr_0 = 34'd0;
15373
15374
15375 // Read Req
15376 if (dram_Ch0_l2b0_sctag_dram_rd_req && !dram_Ch0_l2b0_sctag_dram_rd_dummy_req) begin
15377 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 0,dram_Ch0_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_0);
15378 dram_Ch0_l2b0_addr_store[dram_Ch0_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_0;
15379 end
15380
15381 if (dram_Ch0_l2b0_sctag_dram_rd_req && dram_Ch0_l2b0_sctag_dram_rd_dummy_req) begin
15382 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 0,dram_Ch0_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_0);
15383 dram_Ch0_l2b0_addr_store[dram_Ch0_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_0;
15384 end
15385
15386 // Write Req
15387 if (dram_Ch0_l2b0_sctag_dram_wr_req ) begin
15388 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 0,l2b0_this_addr_0);
15389 l2b0_wr_addr_mon_0 = l2b0_this_addr_0;
15390 end
15391
15392 if (dram_Ch0_l2b0_sctag_dram_data_vld) begin
15393 l2b0_wr_data_0 = {l2b0_wr_data_0,dram_Ch0_l2b0_sctag_dram_wr_data};
15394 if ( l2b0_wr_data_cntr_0 == 3'b111 ) begin
15395 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 0, l2b0_wr_addr_mon_0, l2b0_wr_data_0);
15396 end
15397 l2b0_wr_data_cntr_0 = l2b0_wr_data_cntr_0 + 1;
15398 end
15399
15400 // Read Data
15401 if (l2b0_dvld_dly3_0 == 1'b1) begin
15402 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 0,l2b0_rqid_dly3_0,dram_Ch0_l2b0_addr_store[l2b0_rqid_dly3_0],dram_Ch0_dram_sctag_data);
15403 end
15404
15405 // MECC
15406 if ((l2b0_dvld_dly3_0 == 1'b1) && (dram_Ch0_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch0_l2b0_dram_sctag_pa_err != 1'b1)) begin
15407 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 0, l2b0_rqid_dly3_0,dram_Ch0_l2b0_addr_store[l2b0_rqid_dly3_0]);
15408 end
15409
15410 // MECC OOB
15411 if ((l2b0_dvld_dly3_0 == 1'b1) && (dram_Ch0_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch0_l2b0_dram_sctag_pa_err == 1'b1)) begin
15412 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 0, l2b0_rqid_dly3_0,dram_Ch0_l2b0_addr_store[l2b0_rqid_dly3_0]);
15413 end
15414
15415 // SECC
15416 if ((l2b0_dvld_dly3_0 == 1'b1) && (dram_Ch0_l2b0_dram_sctag_secc_err == 1'b1)) begin
15417 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 0,l2b0_rqid_dly3_0,dram_Ch0_l2b0_addr_store[l2b0_rqid_dly3_0]);
15418 end
15419
15420 if (dram_Ch0_l2b0_dram_sctag_scb_secc_err == 1'b1) begin
15421 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 0);
15422 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15423 finish_test(" Scrub error SECC detected", 0);
15424 end
15425 end
15426
15427 if (dram_Ch0_l2b0_dram_sctag_scb_mecc_err == 1'b1) begin
15428 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 0);
15429 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15430 finish_test(" Scrub error MECC detected", 0);
15431 end
15432 end
15433
15434 end
15435
15436end
15437
15438
15439
15440
15441reg [39:0] l2b1_this_addr_0;
15442reg l2b1_dvld_dly1_0;
15443reg l2b1_dvld_dly2_0;
15444reg l2b1_dvld_dly3_0;
15445reg [2:0] l2b1_rqid_dly1_0;
15446reg [2:0] l2b1_rqid_dly2_0;
15447reg [2:0] l2b1_rqid_dly3_0;
15448// MAQ reg [1:0] ch_0_l2b1;
15449
15450reg [2:0] l2b1_wr_data_cntr_0;
15451reg [511:0] l2b1_wr_data_0;
15452reg [39:0] l2b1_wr_addr_mon_0;
15453
15454reg [39:0] dram_Ch0_l2b1_addr_store [7:0];
15455
15456initial
15457begin
15458 l2b1_wr_data_cntr_0 = 0;
15459 l2b1_wr_data_0 = 0;
15460 l2b1_wr_addr_mon_0 = 0;
15461end
15462
15463always @ (posedge (cmp_clk && enabled))
15464begin
15465 if (cmp_rst_l) begin
15466
15467 l2b1_dvld_dly1_0 <= dram_Ch0_l2b1_dram_sctag_data_vld;
15468 l2b1_dvld_dly2_0 <= l2b1_dvld_dly1_0;
15469 l2b1_dvld_dly3_0 <= l2b1_dvld_dly2_0;
15470
15471 l2b1_rqid_dly1_0 <= dram_Ch0_l2b1_dram_sctag_rd_req_id;
15472 l2b1_rqid_dly2_0 <= l2b1_rqid_dly1_0;
15473 l2b1_rqid_dly3_0 <= l2b1_rqid_dly2_0;
15474
15475 l2b1_this_addr_0 = {dram_Ch0_l2b1_sctag_dram_addr, 5'b0};
15476 //l2b1_this_addr_0 = 34'd0;
15477
15478
15479 // Read Req
15480 if (dram_Ch0_l2b1_sctag_dram_rd_req && !dram_Ch0_l2b1_sctag_dram_rd_dummy_req) begin
15481 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 0,dram_Ch0_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_0);
15482 dram_Ch0_l2b1_addr_store[dram_Ch0_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_0;
15483 end
15484
15485 if (dram_Ch0_l2b1_sctag_dram_rd_req && dram_Ch0_l2b1_sctag_dram_rd_dummy_req) begin
15486 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 0,dram_Ch0_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_0);
15487 dram_Ch0_l2b1_addr_store[dram_Ch0_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_0;
15488 end
15489
15490 // Write Req
15491 if (dram_Ch0_l2b1_sctag_dram_wr_req ) begin
15492 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 0,l2b1_this_addr_0);
15493 l2b1_wr_addr_mon_0 = l2b1_this_addr_0;
15494 end
15495
15496 if (dram_Ch0_l2b1_sctag_dram_data_vld) begin
15497 l2b1_wr_data_0 = {l2b1_wr_data_0,dram_Ch0_l2b1_sctag_dram_wr_data};
15498 if ( l2b1_wr_data_cntr_0 == 3'b111 ) begin
15499 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 0, l2b1_wr_addr_mon_0, l2b1_wr_data_0);
15500 end
15501 l2b1_wr_data_cntr_0 = l2b1_wr_data_cntr_0 + 1;
15502 end
15503
15504 // Read Data
15505 if (l2b1_dvld_dly3_0 == 1'b1) begin
15506 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 0,l2b1_rqid_dly3_0,dram_Ch0_l2b1_addr_store[l2b1_rqid_dly3_0],dram_Ch0_dram_sctag_data);
15507 end
15508
15509 // MECC
15510 if ((l2b1_dvld_dly3_0 == 1'b1) && (dram_Ch0_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch0_l2b1_dram_sctag_pa_err != 1'b1)) begin
15511 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 0, l2b1_rqid_dly3_0,dram_Ch0_l2b1_addr_store[l2b1_rqid_dly3_0]);
15512 end
15513
15514 // MECC OOB
15515 if ((l2b1_dvld_dly3_0 == 1'b1) && (dram_Ch0_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch0_l2b1_dram_sctag_pa_err == 1'b1)) begin
15516 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 0, l2b1_rqid_dly3_0,dram_Ch0_l2b1_addr_store[l2b1_rqid_dly3_0]);
15517 end
15518
15519 // SECC
15520 if ((l2b1_dvld_dly3_0 == 1'b1) && (dram_Ch0_l2b1_dram_sctag_secc_err == 1'b1)) begin
15521 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 0,l2b1_rqid_dly3_0,dram_Ch0_l2b1_addr_store[l2b1_rqid_dly3_0]);
15522 end
15523
15524 if (dram_Ch0_l2b1_dram_sctag_scb_secc_err == 1'b1) begin
15525 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 0);
15526 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15527 finish_test(" Scrub error SECC detected", 0);
15528 end
15529 end
15530
15531 if (dram_Ch0_l2b1_dram_sctag_scb_mecc_err == 1'b1) begin
15532 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 0);
15533 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15534 finish_test(" Scrub error MECC detected", 0);
15535 end
15536 end
15537
15538 end
15539
15540end
15541
15542
15543
15544
15545reg [39:0] l2b0_this_addr_1;
15546reg l2b0_dvld_dly1_1;
15547reg l2b0_dvld_dly2_1;
15548reg l2b0_dvld_dly3_1;
15549reg [2:0] l2b0_rqid_dly1_1;
15550reg [2:0] l2b0_rqid_dly2_1;
15551reg [2:0] l2b0_rqid_dly3_1;
15552// MAQ reg [1:0] ch_1_l2b0;
15553
15554reg [2:0] l2b0_wr_data_cntr_1;
15555reg [511:0] l2b0_wr_data_1;
15556reg [39:0] l2b0_wr_addr_mon_1;
15557
15558reg [39:0] dram_Ch1_l2b0_addr_store [7:0];
15559
15560initial
15561begin
15562 l2b0_wr_data_cntr_1 = 0;
15563 l2b0_wr_data_1 = 0;
15564 l2b0_wr_addr_mon_1 = 0;
15565end
15566
15567always @ (posedge (cmp_clk && enabled))
15568begin
15569 if (cmp_rst_l) begin
15570
15571 l2b0_dvld_dly1_1 <= dram_Ch1_l2b0_dram_sctag_data_vld;
15572 l2b0_dvld_dly2_1 <= l2b0_dvld_dly1_1;
15573 l2b0_dvld_dly3_1 <= l2b0_dvld_dly2_1;
15574
15575 l2b0_rqid_dly1_1 <= dram_Ch1_l2b0_dram_sctag_rd_req_id;
15576 l2b0_rqid_dly2_1 <= l2b0_rqid_dly1_1;
15577 l2b0_rqid_dly3_1 <= l2b0_rqid_dly2_1;
15578
15579 l2b0_this_addr_1 = {dram_Ch1_l2b0_sctag_dram_addr, 5'b0};
15580 //l2b0_this_addr_1 = 34'd0;
15581
15582
15583 // Read Req
15584 if (dram_Ch1_l2b0_sctag_dram_rd_req && !dram_Ch1_l2b0_sctag_dram_rd_dummy_req) begin
15585 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 2,dram_Ch1_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_1);
15586 dram_Ch1_l2b0_addr_store[dram_Ch1_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_1;
15587 end
15588
15589 if (dram_Ch1_l2b0_sctag_dram_rd_req && dram_Ch1_l2b0_sctag_dram_rd_dummy_req) begin
15590 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 2,dram_Ch1_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_1);
15591 dram_Ch1_l2b0_addr_store[dram_Ch1_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_1;
15592 end
15593
15594 // Write Req
15595 if (dram_Ch1_l2b0_sctag_dram_wr_req ) begin
15596 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 2,l2b0_this_addr_1);
15597 l2b0_wr_addr_mon_1 = l2b0_this_addr_1;
15598 end
15599
15600 if (dram_Ch1_l2b0_sctag_dram_data_vld) begin
15601 l2b0_wr_data_1 = {l2b0_wr_data_1,dram_Ch1_l2b0_sctag_dram_wr_data};
15602 if ( l2b0_wr_data_cntr_1 == 3'b111 ) begin
15603 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 2, l2b0_wr_addr_mon_1, l2b0_wr_data_1);
15604 end
15605 l2b0_wr_data_cntr_1 = l2b0_wr_data_cntr_1 + 1;
15606 end
15607
15608 // Read Data
15609 if (l2b0_dvld_dly3_1 == 1'b1) begin
15610 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 2,l2b0_rqid_dly3_1,dram_Ch1_l2b0_addr_store[l2b0_rqid_dly3_1],dram_Ch1_dram_sctag_data);
15611 end
15612
15613 // MECC
15614 if ((l2b0_dvld_dly3_1 == 1'b1) && (dram_Ch1_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch1_l2b0_dram_sctag_pa_err != 1'b1)) begin
15615 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 2, l2b0_rqid_dly3_1,dram_Ch1_l2b0_addr_store[l2b0_rqid_dly3_1]);
15616 end
15617
15618 // MECC OOB
15619 if ((l2b0_dvld_dly3_1 == 1'b1) && (dram_Ch1_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch1_l2b0_dram_sctag_pa_err == 1'b1)) begin
15620 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 2, l2b0_rqid_dly3_1,dram_Ch1_l2b0_addr_store[l2b0_rqid_dly3_1]);
15621 end
15622
15623 // SECC
15624 if ((l2b0_dvld_dly3_1 == 1'b1) && (dram_Ch1_l2b0_dram_sctag_secc_err == 1'b1)) begin
15625 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 2,l2b0_rqid_dly3_1,dram_Ch1_l2b0_addr_store[l2b0_rqid_dly3_1]);
15626 end
15627
15628 if (dram_Ch1_l2b0_dram_sctag_scb_secc_err == 1'b1) begin
15629 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 2);
15630 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15631 finish_test(" Scrub error SECC detected", 1);
15632 end
15633 end
15634
15635 if (dram_Ch1_l2b0_dram_sctag_scb_mecc_err == 1'b1) begin
15636 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 2);
15637 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15638 finish_test(" Scrub error MECC detected", 1);
15639 end
15640 end
15641
15642 end
15643
15644end
15645
15646
15647
15648
15649reg [39:0] l2b1_this_addr_1;
15650reg l2b1_dvld_dly1_1;
15651reg l2b1_dvld_dly2_1;
15652reg l2b1_dvld_dly3_1;
15653reg [2:0] l2b1_rqid_dly1_1;
15654reg [2:0] l2b1_rqid_dly2_1;
15655reg [2:0] l2b1_rqid_dly3_1;
15656// MAQ reg [1:0] ch_1_l2b1;
15657
15658reg [2:0] l2b1_wr_data_cntr_1;
15659reg [511:0] l2b1_wr_data_1;
15660reg [39:0] l2b1_wr_addr_mon_1;
15661
15662reg [39:0] dram_Ch1_l2b1_addr_store [7:0];
15663
15664initial
15665begin
15666 l2b1_wr_data_cntr_1 = 0;
15667 l2b1_wr_data_1 = 0;
15668 l2b1_wr_addr_mon_1 = 0;
15669end
15670
15671always @ (posedge (cmp_clk && enabled))
15672begin
15673 if (cmp_rst_l) begin
15674
15675 l2b1_dvld_dly1_1 <= dram_Ch1_l2b1_dram_sctag_data_vld;
15676 l2b1_dvld_dly2_1 <= l2b1_dvld_dly1_1;
15677 l2b1_dvld_dly3_1 <= l2b1_dvld_dly2_1;
15678
15679 l2b1_rqid_dly1_1 <= dram_Ch1_l2b1_dram_sctag_rd_req_id;
15680 l2b1_rqid_dly2_1 <= l2b1_rqid_dly1_1;
15681 l2b1_rqid_dly3_1 <= l2b1_rqid_dly2_1;
15682
15683 l2b1_this_addr_1 = {dram_Ch1_l2b1_sctag_dram_addr, 5'b0};
15684 //l2b1_this_addr_1 = 34'd0;
15685
15686
15687 // Read Req
15688 if (dram_Ch1_l2b1_sctag_dram_rd_req && !dram_Ch1_l2b1_sctag_dram_rd_dummy_req) begin
15689 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 2,dram_Ch1_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_1);
15690 dram_Ch1_l2b1_addr_store[dram_Ch1_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_1;
15691 end
15692
15693 if (dram_Ch1_l2b1_sctag_dram_rd_req && dram_Ch1_l2b1_sctag_dram_rd_dummy_req) begin
15694 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 2,dram_Ch1_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_1);
15695 dram_Ch1_l2b1_addr_store[dram_Ch1_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_1;
15696 end
15697
15698 // Write Req
15699 if (dram_Ch1_l2b1_sctag_dram_wr_req ) begin
15700 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 2,l2b1_this_addr_1);
15701 l2b1_wr_addr_mon_1 = l2b1_this_addr_1;
15702 end
15703
15704 if (dram_Ch1_l2b1_sctag_dram_data_vld) begin
15705 l2b1_wr_data_1 = {l2b1_wr_data_1,dram_Ch1_l2b1_sctag_dram_wr_data};
15706 if ( l2b1_wr_data_cntr_1 == 3'b111 ) begin
15707 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 2, l2b1_wr_addr_mon_1, l2b1_wr_data_1);
15708 end
15709 l2b1_wr_data_cntr_1 = l2b1_wr_data_cntr_1 + 1;
15710 end
15711
15712 // Read Data
15713 if (l2b1_dvld_dly3_1 == 1'b1) begin
15714 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 2,l2b1_rqid_dly3_1,dram_Ch1_l2b1_addr_store[l2b1_rqid_dly3_1],dram_Ch1_dram_sctag_data);
15715 end
15716
15717 // MECC
15718 if ((l2b1_dvld_dly3_1 == 1'b1) && (dram_Ch1_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch1_l2b1_dram_sctag_pa_err != 1'b1)) begin
15719 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 2,l2b1_rqid_dly3_1,dram_Ch1_l2b1_addr_store[l2b1_rqid_dly3_1]);
15720 end
15721
15722 // MECC OOB
15723 if ((l2b1_dvld_dly3_1 == 1'b1) && (dram_Ch1_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch1_l2b1_dram_sctag_pa_err == 1'b1)) begin
15724 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 2, l2b1_rqid_dly3_1,dram_Ch1_l2b1_addr_store[l2b1_rqid_dly3_1]);
15725 end
15726
15727 // SECC
15728 if ((l2b1_dvld_dly3_1 == 1'b1) && (dram_Ch1_l2b1_dram_sctag_secc_err == 1'b1)) begin
15729 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 2,l2b1_rqid_dly3_1,dram_Ch1_l2b1_addr_store[l2b1_rqid_dly3_1]);
15730 end
15731
15732 if (dram_Ch1_l2b1_dram_sctag_scb_secc_err == 1'b1) begin
15733 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 2);
15734 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15735 finish_test(" Scrub error SECC detected", 1);
15736 end
15737 end
15738
15739 if (dram_Ch1_l2b1_dram_sctag_scb_mecc_err == 1'b1) begin
15740 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 2);
15741 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15742 finish_test(" Scrub error MECC detected", 1);
15743 end
15744 end
15745
15746 end
15747
15748end
15749
15750
15751
15752
15753reg [39:0] l2b0_this_addr_2;
15754reg l2b0_dvld_dly1_2;
15755reg l2b0_dvld_dly2_2;
15756reg l2b0_dvld_dly3_2;
15757reg [2:0] l2b0_rqid_dly1_2;
15758reg [2:0] l2b0_rqid_dly2_2;
15759reg [2:0] l2b0_rqid_dly3_2;
15760// MAQ reg [1:0] ch_2_l2b0;
15761
15762reg [2:0] l2b0_wr_data_cntr_2;
15763reg [511:0] l2b0_wr_data_2;
15764reg [39:0] l2b0_wr_addr_mon_2;
15765
15766reg [39:0] dram_Ch2_l2b0_addr_store [7:0];
15767
15768initial
15769begin
15770 l2b0_wr_data_cntr_2 = 0;
15771 l2b0_wr_data_2 = 0;
15772 l2b0_wr_addr_mon_2 = 0;
15773end
15774
15775always @ (posedge (cmp_clk && enabled))
15776begin
15777 if (cmp_rst_l) begin
15778
15779 l2b0_dvld_dly1_2 <= dram_Ch2_l2b0_dram_sctag_data_vld;
15780 l2b0_dvld_dly2_2 <= l2b0_dvld_dly1_2;
15781 l2b0_dvld_dly3_2 <= l2b0_dvld_dly2_2;
15782
15783 l2b0_rqid_dly1_2 <= dram_Ch2_l2b0_dram_sctag_rd_req_id;
15784 l2b0_rqid_dly2_2 <= l2b0_rqid_dly1_2;
15785 l2b0_rqid_dly3_2 <= l2b0_rqid_dly2_2;
15786
15787 l2b0_this_addr_2 = {dram_Ch2_l2b0_sctag_dram_addr, 5'b0};
15788 //l2b0_this_addr_2 = 34'd0;
15789
15790
15791 // Read Req
15792 if (dram_Ch2_l2b0_sctag_dram_rd_req && !dram_Ch2_l2b0_sctag_dram_rd_dummy_req) begin
15793 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 1,dram_Ch2_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_2);
15794 dram_Ch2_l2b0_addr_store[dram_Ch2_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_2;
15795 end
15796
15797 if (dram_Ch2_l2b0_sctag_dram_rd_req && dram_Ch2_l2b0_sctag_dram_rd_dummy_req) begin
15798 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 1,dram_Ch2_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_2);
15799 dram_Ch2_l2b0_addr_store[dram_Ch2_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_2;
15800 end
15801
15802 // Write Req
15803 if (dram_Ch2_l2b0_sctag_dram_wr_req ) begin
15804 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 1,l2b0_this_addr_2);
15805 l2b0_wr_addr_mon_2 = l2b0_this_addr_2;
15806 end
15807
15808 if (dram_Ch2_l2b0_sctag_dram_data_vld) begin
15809 l2b0_wr_data_2 = {l2b0_wr_data_2,dram_Ch2_l2b0_sctag_dram_wr_data};
15810 if ( l2b0_wr_data_cntr_2 == 3'b111 ) begin
15811 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 1, l2b0_wr_addr_mon_2, l2b0_wr_data_2);
15812 end
15813 l2b0_wr_data_cntr_2 = l2b0_wr_data_cntr_2 + 1;
15814 end
15815
15816 // Read Data
15817 if (l2b0_dvld_dly3_2 == 1'b1) begin
15818 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 1,l2b0_rqid_dly3_2,dram_Ch2_l2b0_addr_store[l2b0_rqid_dly3_2],dram_Ch2_dram_sctag_data);
15819 end
15820
15821 // MECC
15822 if ((l2b0_dvld_dly3_2 == 1'b1) && (dram_Ch2_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch2_l2b0_dram_sctag_pa_err != 1'b1)) begin
15823 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 1,l2b0_rqid_dly3_2,dram_Ch2_l2b0_addr_store[l2b0_rqid_dly3_2]);
15824 end
15825
15826 // MECC OOB
15827 if ((l2b0_dvld_dly3_2 == 1'b1) && (dram_Ch2_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch2_l2b0_dram_sctag_pa_err == 1'b1)) begin
15828 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 1,l2b0_rqid_dly3_2,dram_Ch2_l2b0_addr_store[l2b0_rqid_dly3_2]);
15829 end
15830
15831 // SECC
15832 if ((l2b0_dvld_dly3_2 == 1'b1) && (dram_Ch2_l2b0_dram_sctag_secc_err == 1'b1)) begin
15833 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 1,l2b0_rqid_dly3_2,dram_Ch2_l2b0_addr_store[l2b0_rqid_dly3_2]);
15834 end
15835
15836 if (dram_Ch2_l2b0_dram_sctag_scb_secc_err == 1'b1) begin
15837 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 1);
15838 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15839 finish_test(" Scrub error SECC detected", 2);
15840 end
15841 end
15842
15843 if (dram_Ch2_l2b0_dram_sctag_scb_mecc_err == 1'b1) begin
15844 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 1);
15845 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15846 finish_test(" Scrub error MECC detected", 2);
15847 end
15848 end
15849
15850 end
15851
15852end
15853
15854
15855
15856
15857reg [39:0] l2b1_this_addr_2;
15858reg l2b1_dvld_dly1_2;
15859reg l2b1_dvld_dly2_2;
15860reg l2b1_dvld_dly3_2;
15861reg [2:0] l2b1_rqid_dly1_2;
15862reg [2:0] l2b1_rqid_dly2_2;
15863reg [2:0] l2b1_rqid_dly3_2;
15864// MAQ reg [1:0] ch_2_l2b1;
15865
15866reg [2:0] l2b1_wr_data_cntr_2;
15867reg [511:0] l2b1_wr_data_2;
15868reg [39:0] l2b1_wr_addr_mon_2;
15869
15870reg [39:0] dram_Ch2_l2b1_addr_store [7:0];
15871
15872initial
15873begin
15874 l2b1_wr_data_cntr_2 = 0;
15875 l2b1_wr_data_2 = 0;
15876 l2b1_wr_addr_mon_2 = 0;
15877end
15878
15879always @ (posedge (cmp_clk && enabled))
15880begin
15881 if (cmp_rst_l) begin
15882
15883 l2b1_dvld_dly1_2 <= dram_Ch2_l2b1_dram_sctag_data_vld;
15884 l2b1_dvld_dly2_2 <= l2b1_dvld_dly1_2;
15885 l2b1_dvld_dly3_2 <= l2b1_dvld_dly2_2;
15886
15887 l2b1_rqid_dly1_2 <= dram_Ch2_l2b1_dram_sctag_rd_req_id;
15888 l2b1_rqid_dly2_2 <= l2b1_rqid_dly1_2;
15889 l2b1_rqid_dly3_2 <= l2b1_rqid_dly2_2;
15890
15891 l2b1_this_addr_2 = {dram_Ch2_l2b1_sctag_dram_addr, 5'b0};
15892 //l2b1_this_addr_2 = 34'd0;
15893
15894
15895 // Read Req
15896 if (dram_Ch2_l2b1_sctag_dram_rd_req && !dram_Ch2_l2b1_sctag_dram_rd_dummy_req) begin
15897 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 1,dram_Ch2_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_2);
15898 dram_Ch2_l2b1_addr_store[dram_Ch2_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_2;
15899 end
15900
15901 if (dram_Ch2_l2b1_sctag_dram_rd_req && dram_Ch2_l2b1_sctag_dram_rd_dummy_req) begin
15902 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 1,dram_Ch2_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_2);
15903 dram_Ch2_l2b1_addr_store[dram_Ch2_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_2;
15904 end
15905
15906 // Write Req
15907 if (dram_Ch2_l2b1_sctag_dram_wr_req ) begin
15908 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 1,l2b1_this_addr_2);
15909 l2b1_wr_addr_mon_2 = l2b1_this_addr_2;
15910 end
15911
15912 if (dram_Ch2_l2b1_sctag_dram_data_vld) begin
15913 l2b1_wr_data_2 = {l2b1_wr_data_2,dram_Ch2_l2b1_sctag_dram_wr_data};
15914 if ( l2b1_wr_data_cntr_2 == 3'b111 ) begin
15915 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 1, l2b1_wr_addr_mon_2, l2b1_wr_data_2);
15916 end
15917 l2b1_wr_data_cntr_2 = l2b1_wr_data_cntr_2 + 1;
15918 end
15919
15920 // Read Data
15921 if (l2b1_dvld_dly3_2 == 1'b1) begin
15922 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 1,l2b1_rqid_dly3_2,dram_Ch2_l2b1_addr_store[l2b1_rqid_dly3_2],dram_Ch2_dram_sctag_data);
15923 end
15924
15925 // MECC
15926 if ((l2b1_dvld_dly3_2 == 1'b1) && (dram_Ch2_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch2_l2b1_dram_sctag_pa_err != 1'b1)) begin
15927 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 1,l2b1_rqid_dly3_2,dram_Ch2_l2b1_addr_store[l2b1_rqid_dly3_2]);
15928 end
15929
15930 // MECC OOB
15931 if ((l2b1_dvld_dly3_2 == 1'b1) && (dram_Ch2_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch2_l2b1_dram_sctag_pa_err == 1'b1)) begin
15932 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 1,l2b1_rqid_dly3_2,dram_Ch2_l2b1_addr_store[l2b1_rqid_dly3_2]);
15933 end
15934
15935 // SECC
15936 if ((l2b1_dvld_dly3_2 == 1'b1) && (dram_Ch2_l2b1_dram_sctag_secc_err == 1'b1)) begin
15937 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 1,l2b1_rqid_dly3_2,dram_Ch2_l2b1_addr_store[l2b1_rqid_dly3_2]);
15938 end
15939
15940 if (dram_Ch2_l2b1_dram_sctag_scb_secc_err == 1'b1) begin
15941 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 1);
15942 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15943 finish_test(" Scrub error SECC detected", 2);
15944 end
15945 end
15946
15947 if (dram_Ch2_l2b1_dram_sctag_scb_mecc_err == 1'b1) begin
15948 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 1);
15949 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
15950 finish_test(" Scrub error MECC detected", 2);
15951 end
15952 end
15953
15954 end
15955
15956end
15957
15958
15959
15960
15961reg [39:0] l2b0_this_addr_3;
15962reg l2b0_dvld_dly1_3;
15963reg l2b0_dvld_dly2_3;
15964reg l2b0_dvld_dly3_3;
15965reg [2:0] l2b0_rqid_dly1_3;
15966reg [2:0] l2b0_rqid_dly2_3;
15967reg [2:0] l2b0_rqid_dly3_3;
15968// MAQ reg [1:0] ch_3_l2b0;
15969
15970reg [2:0] l2b0_wr_data_cntr_3;
15971reg [511:0] l2b0_wr_data_3;
15972reg [39:0] l2b0_wr_addr_mon_3;
15973
15974reg [39:0] dram_Ch3_l2b0_addr_store [7:0];
15975
15976initial
15977begin
15978 l2b0_wr_data_cntr_3 = 0;
15979 l2b0_wr_data_3 = 0;
15980 l2b0_wr_addr_mon_3 = 0;
15981end
15982
15983always @ (posedge (cmp_clk && enabled))
15984begin
15985 if (cmp_rst_l) begin
15986
15987 l2b0_dvld_dly1_3 <= dram_Ch3_l2b0_dram_sctag_data_vld;
15988 l2b0_dvld_dly2_3 <= l2b0_dvld_dly1_3;
15989 l2b0_dvld_dly3_3 <= l2b0_dvld_dly2_3;
15990
15991 l2b0_rqid_dly1_3 <= dram_Ch3_l2b0_dram_sctag_rd_req_id;
15992 l2b0_rqid_dly2_3 <= l2b0_rqid_dly1_3;
15993 l2b0_rqid_dly3_3 <= l2b0_rqid_dly2_3;
15994
15995 l2b0_this_addr_3 = {dram_Ch3_l2b0_sctag_dram_addr, 5'b0};
15996 //l2b0_this_addr_3 = 34'd0;
15997
15998
15999 // Read Req
16000 if (dram_Ch3_l2b0_sctag_dram_rd_req && !dram_Ch3_l2b0_sctag_dram_rd_dummy_req) begin
16001 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 3,dram_Ch3_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_3);
16002 dram_Ch3_l2b0_addr_store[dram_Ch3_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_3;
16003 end
16004
16005 if (dram_Ch3_l2b0_sctag_dram_rd_req && dram_Ch3_l2b0_sctag_dram_rd_dummy_req) begin
16006 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 3,dram_Ch3_l2b0_sctag_dram_rd_req_id,l2b0_this_addr_3);
16007 dram_Ch3_l2b0_addr_store[dram_Ch3_l2b0_sctag_dram_rd_req_id] <= l2b0_this_addr_3;
16008 end
16009
16010 // Write Req
16011 if (dram_Ch3_l2b0_sctag_dram_wr_req ) begin
16012 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 3,l2b0_this_addr_3);
16013 l2b0_wr_addr_mon_3 = l2b0_this_addr_3;
16014 end
16015
16016 if (dram_Ch3_l2b0_sctag_dram_data_vld) begin
16017 l2b0_wr_data_3 = {l2b0_wr_data_3,dram_Ch3_l2b0_sctag_dram_wr_data};
16018 if ( l2b0_wr_data_cntr_3 == 3'b111 ) begin
16019 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 3, l2b0_wr_addr_mon_3, l2b0_wr_data_3);
16020 end
16021 l2b0_wr_data_cntr_3 = l2b0_wr_data_cntr_3 + 1;
16022 end
16023
16024 // Read Data
16025 if (l2b0_dvld_dly3_3 == 1'b1) begin
16026 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 3,l2b0_rqid_dly3_3,dram_Ch3_l2b0_addr_store[l2b0_rqid_dly3_3],dram_Ch3_dram_sctag_data);
16027 end
16028
16029 // MECC
16030 if ((l2b0_dvld_dly3_3 == 1'b1) && (dram_Ch3_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch3_l2b0_dram_sctag_pa_err != 1'b1)) begin
16031 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 3,l2b0_rqid_dly3_3,dram_Ch3_l2b0_addr_store[l2b0_rqid_dly3_3]);
16032 end
16033
16034 // MECC OOB
16035 if ((l2b0_dvld_dly3_3 == 1'b1) && (dram_Ch3_l2b0_dram_sctag_mecc_err == 1'b1) && (dram_Ch3_l2b0_dram_sctag_pa_err == 1'b1)) begin
16036 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 3,l2b0_rqid_dly3_3,dram_Ch3_l2b0_addr_store[l2b0_rqid_dly3_3]);
16037 end
16038
16039 // SECC
16040 if ((l2b0_dvld_dly3_3 == 1'b1) && (dram_Ch3_l2b0_dram_sctag_secc_err == 1'b1)) begin
16041 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 3,l2b0_rqid_dly3_3,dram_Ch3_l2b0_addr_store[l2b0_rqid_dly3_3]);
16042 end
16043
16044 if (dram_Ch3_l2b0_dram_sctag_scb_secc_err == 1'b1) begin
16045 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 3);
16046 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
16047 finish_test(" Scrub error SECC detected", 3);
16048 end
16049 end
16050
16051 if (dram_Ch3_l2b0_dram_sctag_scb_mecc_err == 1'b1) begin
16052 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 3);
16053 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
16054 finish_test(" Scrub error MECC detected", 3);
16055 end
16056 end
16057
16058 end
16059
16060end
16061
16062
16063
16064
16065reg [39:0] l2b1_this_addr_3;
16066reg l2b1_dvld_dly1_3;
16067reg l2b1_dvld_dly2_3;
16068reg l2b1_dvld_dly3_3;
16069reg [2:0] l2b1_rqid_dly1_3;
16070reg [2:0] l2b1_rqid_dly2_3;
16071reg [2:0] l2b1_rqid_dly3_3;
16072// MAQ reg [1:0] ch_3_l2b1;
16073
16074reg [2:0] l2b1_wr_data_cntr_3;
16075reg [511:0] l2b1_wr_data_3;
16076reg [39:0] l2b1_wr_addr_mon_3;
16077
16078reg [39:0] dram_Ch3_l2b1_addr_store [7:0];
16079
16080initial
16081begin
16082 l2b1_wr_data_cntr_3 = 0;
16083 l2b1_wr_data_3 = 0;
16084 l2b1_wr_addr_mon_3 = 0;
16085end
16086
16087always @ (posedge (cmp_clk && enabled))
16088begin
16089 if (cmp_rst_l) begin
16090
16091 l2b1_dvld_dly1_3 <= dram_Ch3_l2b1_dram_sctag_data_vld;
16092 l2b1_dvld_dly2_3 <= l2b1_dvld_dly1_3;
16093 l2b1_dvld_dly3_3 <= l2b1_dvld_dly2_3;
16094
16095 l2b1_rqid_dly1_3 <= dram_Ch3_l2b1_dram_sctag_rd_req_id;
16096 l2b1_rqid_dly2_3 <= l2b1_rqid_dly1_3;
16097 l2b1_rqid_dly3_3 <= l2b1_rqid_dly2_3;
16098
16099 l2b1_this_addr_3 = {dram_Ch3_l2b1_sctag_dram_addr, 5'b0};
16100 //l2b1_this_addr_3 = 34'd0;
16101
16102
16103 // Read Req
16104 if (dram_Ch3_l2b1_sctag_dram_rd_req && !dram_Ch3_l2b1_sctag_dram_rd_dummy_req) begin
16105 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read :: ReqId = %x, Addr = %x ", 3,dram_Ch3_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_3);
16106 dram_Ch3_l2b1_addr_store[dram_Ch3_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_3;
16107 end
16108
16109 if (dram_Ch3_l2b1_sctag_dram_rd_req && dram_Ch3_l2b1_sctag_dram_rd_dummy_req) begin
16110 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Dummy Read :: ReqId = %x, Addr = %x ", 3,dram_Ch3_l2b1_sctag_dram_rd_req_id,l2b1_this_addr_3);
16111 dram_Ch3_l2b1_addr_store[dram_Ch3_l2b1_sctag_dram_rd_req_id] <= l2b1_this_addr_3;
16112 end
16113
16114 // Write Req
16115 if (dram_Ch3_l2b1_sctag_dram_wr_req ) begin
16116 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write :: Addr = %x ", 3,l2b1_this_addr_3);
16117 l2b1_wr_addr_mon_3 = l2b1_this_addr_3;
16118 end
16119
16120 if (dram_Ch3_l2b1_sctag_dram_data_vld) begin
16121 l2b1_wr_data_3 = {l2b1_wr_data_3,dram_Ch3_l2b1_sctag_dram_wr_data};
16122 if ( l2b1_wr_data_cntr_3 == 3'b111 ) begin
16123 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Write Data :: Addr = %x, Data = %x ", 3, l2b1_wr_addr_mon_3, l2b1_wr_data_3);
16124 end
16125 l2b1_wr_data_cntr_3 = l2b1_wr_data_cntr_3 + 1;
16126 end
16127
16128 // Read Data
16129 if (l2b1_dvld_dly3_3 == 1'b1) begin
16130 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Read Data :: ReqId = %x, Addr = %x, Data = %x ", 3,l2b1_rqid_dly3_3,dram_Ch3_l2b1_addr_store[l2b1_rqid_dly3_3],dram_Ch3_dram_sctag_data);
16131 end
16132
16133 // MECC
16134 if ((l2b1_dvld_dly3_3 == 1'b1) && (dram_Ch3_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch3_l2b1_dram_sctag_pa_err != 1'b1)) begin
16135 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> MECC Uncorr err :: ReqId = %x, Addr = %x", 3,l2b1_rqid_dly3_3,dram_Ch3_l2b1_addr_store[l2b1_rqid_dly3_3]);
16136 end
16137
16138 // MECC OOB
16139 if ((l2b1_dvld_dly3_3 == 1'b1) && (dram_Ch3_l2b1_dram_sctag_mecc_err == 1'b1) && (dram_Ch3_l2b1_dram_sctag_pa_err == 1'b1)) begin
16140 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> OOB - MECC Uncorr err :: ReqId = %x, Addr = %x", 3,l2b1_rqid_dly3_3,dram_Ch3_l2b1_addr_store[l2b1_rqid_dly3_3]);
16141 end
16142
16143 // SECC
16144 if ((l2b1_dvld_dly3_3 == 1'b1) && (dram_Ch3_l2b1_dram_sctag_secc_err == 1'b1)) begin
16145 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> SECC Corr err :: ReqId = %x, Addr = %x", 3,l2b1_rqid_dly3_3,dram_Ch3_l2b1_addr_store[l2b1_rqid_dly3_3]);
16146 end
16147
16148 if (dram_Ch3_l2b1_dram_sctag_scb_secc_err == 1'b1) begin
16149 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub SECC err Detected ", 3);
16150 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
16151 finish_test(" Scrub error SECC detected", 3);
16152 end
16153 end
16154
16155 if (dram_Ch3_l2b1_dram_sctag_scb_mecc_err == 1'b1) begin
16156 `PR_DEBUG("mcusat_cov_mon", `DEBUG, "L2_MCU_MON[%0d] -> Scrub MECC err Detected ", 3);
16157 if($test$plusargs("FINISH_ON_SCRB_ERR")) begin
16158 finish_test(" Scrub error MECC detected", 3);
16159 end
16160 end
16161
16162 end
16163
16164end
16165
16166
16167
16168// --------- task allows some more clocks and prints the error message with ERROR *string* --------
16169
16170task finish_test;
16171input [512:0] message;
16172input [2:0] id;
16173integer Failure_time;
16174
16175begin
16176 Failure_time =$time;
16177 `PR_ERROR("mcusat_cov_mon", `ERROR, "DRAM Channel %d %s", id, message);
16178 @(posedge clk);
16179 @(posedge clk);
16180 @(posedge clk);
16181end
16182endtask
16183
16184//-----------------------------------------
16185// Disable mcusat_cov_mon during Warm Reset
16186//-----------------------------------------
16187
16188always @ (posedge rst_wmr_protect)
16189begin
16190 if (!($test$plusargs("mcusat_cov_mon_disable")))
16191 enabled = 1'b0;
16192end
16193
16194always @ (negedge rst_wmr_protect)
16195begin
16196 if (!($test$plusargs("mcusat_cov_mon_disable")))
16197 enabled = 1'b1;
16198end
16199
16200endmodule
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