projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / n2_int.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_int.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_int();
36
37wire [145:0] cpx_spc0_data_cx2 = `CPU.cpx_spc0_data_cx2;
38wire [145:0] cpx_spc1_data_cx2 = `CPU.cpx_spc1_data_cx2;
39wire [145:0] cpx_spc2_data_cx2 = `CPU.cpx_spc2_data_cx2;
40wire [145:0] cpx_spc3_data_cx2 = `CPU.cpx_spc3_data_cx2;
41wire [145:0] cpx_spc4_data_cx2 = `CPU.cpx_spc4_data_cx2;
42wire [145:0] cpx_spc5_data_cx2 = `CPU.cpx_spc5_data_cx2;
43wire [145:0] cpx_spc6_data_cx2 = `CPU.cpx_spc6_data_cx2;
44wire [145:0] cpx_spc7_data_cx2 = `CPU.cpx_spc7_data_cx2;
45wire clk = `CPU.l2clk ;
46wire rst_l = `CPU.PWRON_RST_L;
47
48
49integer count_int_spc0t0;
50integer count_int_spc0t1;
51integer count_int_spc0t2;
52integer count_int_spc0t3;
53integer count_int_spc0t4;
54integer count_int_spc0t5;
55integer count_int_spc0t6;
56integer count_int_spc0t7;
57integer count_int_spc1t0;
58integer count_int_spc1t1;
59integer count_int_spc1t2;
60integer count_int_spc1t3;
61integer count_int_spc1t4;
62integer count_int_spc1t5;
63integer count_int_spc1t6;
64integer count_int_spc1t7;
65integer count_int_spc2t0;
66integer count_int_spc2t1;
67integer count_int_spc2t2;
68integer count_int_spc2t3;
69integer count_int_spc2t4;
70integer count_int_spc2t5;
71integer count_int_spc2t6;
72integer count_int_spc2t7;
73integer count_int_spc3t0;
74integer count_int_spc3t1;
75integer count_int_spc3t2;
76integer count_int_spc3t3;
77integer count_int_spc3t4;
78integer count_int_spc3t5;
79integer count_int_spc3t6;
80integer count_int_spc3t7;
81integer count_int_spc4t0;
82integer count_int_spc4t1;
83integer count_int_spc4t2;
84integer count_int_spc4t3;
85integer count_int_spc4t4;
86integer count_int_spc4t5;
87integer count_int_spc4t6;
88integer count_int_spc4t7;
89integer count_int_spc5t0;
90integer count_int_spc5t1;
91integer count_int_spc5t2;
92integer count_int_spc5t3;
93integer count_int_spc5t4;
94integer count_int_spc5t5;
95integer count_int_spc5t6;
96integer count_int_spc5t7;
97integer count_int_spc6t0;
98integer count_int_spc6t1;
99integer count_int_spc6t2;
100integer count_int_spc6t3;
101integer count_int_spc6t4;
102integer count_int_spc6t5;
103integer count_int_spc6t6;
104integer count_int_spc6t7;
105integer count_int_spc7t0;
106integer count_int_spc7t1;
107integer count_int_spc7t2;
108integer count_int_spc7t3;
109integer count_int_spc7t4;
110integer count_int_spc7t5;
111integer count_int_spc7t6;
112integer count_int_spc7t7;
113
114
115initial
116 begin
117 count_int_spc0t0 = 0;
118 count_int_spc0t1 = 0;
119 count_int_spc0t2 = 0;
120 count_int_spc0t3 = 0;
121 count_int_spc0t4 = 0;
122 count_int_spc0t5 = 0;
123 count_int_spc0t6 = 0;
124 count_int_spc0t7 = 0;
125 count_int_spc1t0 = 0;
126 count_int_spc1t1 = 0;
127 count_int_spc1t2 = 0;
128 count_int_spc1t3 = 0;
129 count_int_spc1t4 = 0;
130 count_int_spc1t5 = 0;
131 count_int_spc1t6 = 0;
132 count_int_spc1t7 = 0;
133 count_int_spc2t0 = 0;
134 count_int_spc2t1 = 0;
135 count_int_spc2t2 = 0;
136 count_int_spc2t3 = 0;
137 count_int_spc2t4 = 0;
138 count_int_spc2t5 = 0;
139 count_int_spc2t6 = 0;
140 count_int_spc2t7 = 0;
141 count_int_spc3t0 = 0;
142 count_int_spc3t1 = 0;
143 count_int_spc3t2 = 0;
144 count_int_spc3t3 = 0;
145 count_int_spc3t4 = 0;
146 count_int_spc3t5 = 0;
147 count_int_spc3t6 = 0;
148 count_int_spc3t7 = 0;
149 count_int_spc4t0 = 0;
150 count_int_spc4t1 = 0;
151 count_int_spc4t2 = 0;
152 count_int_spc4t3 = 0;
153 count_int_spc4t4 = 0;
154 count_int_spc4t5 = 0;
155 count_int_spc4t6 = 0;
156 count_int_spc4t7 = 0;
157 count_int_spc5t0 = 0;
158 count_int_spc5t1 = 0;
159 count_int_spc5t2 = 0;
160 count_int_spc5t3 = 0;
161 count_int_spc5t4 = 0;
162 count_int_spc5t5 = 0;
163 count_int_spc5t6 = 0;
164 count_int_spc5t7 = 0;
165 count_int_spc6t0 = 0;
166 count_int_spc6t1 = 0;
167 count_int_spc6t2 = 0;
168 count_int_spc6t3 = 0;
169 count_int_spc6t4 = 0;
170 count_int_spc6t5 = 0;
171 count_int_spc6t6 = 0;
172 count_int_spc6t7 = 0;
173 count_int_spc7t0 = 0;
174 count_int_spc7t1 = 0;
175 count_int_spc7t2 = 0;
176 count_int_spc7t3 = 0;
177 count_int_spc7t4 = 0;
178 count_int_spc7t5 = 0;
179 count_int_spc7t6 = 0;
180 count_int_spc7t7 = 0;
181
182 end
183
184always @(posedge clk) begin
185 if((cpx_spc0_data_cx2[145] == 1'b1) && (cpx_spc0_data_cx2[144:141] == 4'b0111))
186 begin
187 if (cpx_spc0_data_cx2[10:8] == 3'b000)
188 begin
189 count_int_spc0t0 = count_int_spc0t0 +1;
190 `PR_INFO("n2_int", `INFO, "count_int_spc0t0 = %d",
191 count_int_spc0t0);
192 end
193 else if (cpx_spc0_data_cx2[10:8] == 3'b001)
194 begin
195 count_int_spc0t1 = count_int_spc0t1 +1;
196 `PR_INFO("n2_int", `INFO, "count_int_spc0t1 = %d",
197 count_int_spc0t1);
198 end
199 else if (cpx_spc0_data_cx2[10:8] == 3'b010)
200 begin
201 count_int_spc0t2 = count_int_spc0t2 +1;
202 `PR_INFO("n2_int", `INFO, "count_int_spc0t2 = %d",
203 count_int_spc0t2);
204 end
205 else if (cpx_spc0_data_cx2[10:8] == 3'b011)
206 begin
207 count_int_spc0t3 = count_int_spc0t3 +1;
208 `PR_INFO("n2_int", `INFO, "count_int_spc0t3 = %d",
209 count_int_spc0t3);
210 end
211 else if (cpx_spc0_data_cx2[10:8] == 3'b100)
212 begin
213 count_int_spc0t4 = count_int_spc0t4 +1;
214 `PR_INFO("n2_int", `INFO, "count_int_spc0t4 = %d",
215 count_int_spc0t4);
216 end
217 else if (cpx_spc0_data_cx2[10:8] == 3'b101)
218 begin
219 count_int_spc0t5 = count_int_spc0t5 +1;
220 `PR_INFO("n2_int", `INFO, "count_int_spc0t5 = %d",
221 count_int_spc0t5);
222 end
223 else if (cpx_spc0_data_cx2[10:8] == 3'b110)
224 begin
225 count_int_spc0t6 = count_int_spc0t6 +1;
226 `PR_INFO("n2_int", `INFO, "count_int_spc0t6 = %d",
227 count_int_spc0t6);
228 end
229 else if (cpx_spc0_data_cx2[10:8] == 3'b111)
230 begin
231 count_int_spc0t7 = count_int_spc0t7 +1;
232 `PR_INFO("n2_int", `INFO, "count_int_spc0t7 = %d",
233 count_int_spc0t7);
234 end
235 end
236
237
238//--------------------------------------
239 if((cpx_spc1_data_cx2[145] == 1'b1) && (cpx_spc1_data_cx2[144:141] == 4'b0111))
240 begin
241 if (cpx_spc1_data_cx2[10:8] == 3'b000)
242 begin
243 count_int_spc1t0 = count_int_spc1t0 +1;
244 `PR_INFO("n2_int", `INFO, "count_int_spc1t0 = %d",
245 count_int_spc1t0);
246 end
247 else if (cpx_spc1_data_cx2[10:8] == 3'b001)
248 begin
249 count_int_spc1t1 = count_int_spc1t1 +1;
250 `PR_INFO("n2_int", `INFO, "count_int_spc1t1 = %d",
251 count_int_spc1t1);
252 end
253 else if (cpx_spc1_data_cx2[10:8] == 3'b010)
254 begin
255 count_int_spc1t2 = count_int_spc1t2 +1;
256 `PR_INFO("n2_int", `INFO, "count_int_spc1t2 = %d",
257 count_int_spc1t2);
258 end
259 else if (cpx_spc1_data_cx2[10:8] == 3'b011)
260 begin
261 count_int_spc1t3 = count_int_spc1t3 +1;
262 `PR_INFO("n2_int", `INFO, "count_int_spc1t3 = %d",
263 count_int_spc1t3);
264 end
265 else if (cpx_spc1_data_cx2[10:8] == 3'b100)
266 begin
267 count_int_spc1t4 = count_int_spc1t4 +1;
268 `PR_INFO("n2_int", `INFO, "count_int_spc1t4 = %d",
269 count_int_spc1t4);
270 end
271 else if (cpx_spc1_data_cx2[10:8] == 3'b101)
272 begin
273 count_int_spc1t5 = count_int_spc1t5 +1;
274 `PR_INFO("n2_int", `INFO, "count_int_spc1t5 = %d",
275 count_int_spc1t5);
276 end
277 else if (cpx_spc1_data_cx2[10:8] == 3'b110)
278 begin
279 count_int_spc1t6 = count_int_spc1t6 +1;
280 `PR_INFO("n2_int", `INFO, "count_int_spc1t6 = %d",
281 count_int_spc1t6);
282 end
283 else if (cpx_spc1_data_cx2[10:8] == 3'b111)
284 begin
285 count_int_spc1t7 = count_int_spc1t7 +1;
286 `PR_INFO("n2_int", `INFO, "count_int_spc1t7 = %d",
287 count_int_spc1t7);
288 end
289 end
290
291
292//--------------------------------------
293 if((cpx_spc2_data_cx2[145] == 1'b1) && (cpx_spc2_data_cx2[144:141] == 4'b0111))
294 begin
295 if (cpx_spc2_data_cx2[10:8] == 3'b000)
296 begin
297 count_int_spc2t0 = count_int_spc2t0 +1;
298 `PR_INFO("n2_int", `INFO, "count_int_spc2t0 = %d",
299 count_int_spc2t0);
300 end
301 else if (cpx_spc2_data_cx2[10:8] == 3'b001)
302 begin
303 count_int_spc2t1 = count_int_spc2t1 +1;
304 `PR_INFO("n2_int", `INFO, "count_int_spc2t1 = %d",
305 count_int_spc2t1);
306 end
307 else if (cpx_spc2_data_cx2[10:8] == 3'b010)
308 begin
309 count_int_spc2t2 = count_int_spc2t2 +1;
310 `PR_INFO("n2_int", `INFO, "count_int_spc2t2 = %d",
311 count_int_spc2t2);
312 end
313 else if (cpx_spc2_data_cx2[10:8] == 3'b011)
314 begin
315 count_int_spc2t3 = count_int_spc2t3 +1;
316 `PR_INFO("n2_int", `INFO, "count_int_spc2t3 = %d",
317 count_int_spc2t3);
318 end
319 else if (cpx_spc2_data_cx2[10:8] == 3'b100)
320 begin
321 count_int_spc2t4 = count_int_spc2t4 +1;
322 `PR_INFO("n2_int", `INFO, "count_int_spc2t4 = %d",
323 count_int_spc2t4);
324 end
325 else if (cpx_spc2_data_cx2[10:8] == 3'b101)
326 begin
327 count_int_spc2t5 = count_int_spc2t5 +1;
328 `PR_INFO("n2_int", `INFO, "count_int_spc2t5 = %d",
329 count_int_spc2t5);
330 end
331 else if (cpx_spc2_data_cx2[10:8] == 3'b110)
332 begin
333 count_int_spc2t6 = count_int_spc2t6 +1;
334 `PR_INFO("n2_int", `INFO, "count_int_spc2t6 = %d",
335 count_int_spc2t6);
336 end
337 else if (cpx_spc2_data_cx2[10:8] == 3'b111)
338 begin
339 count_int_spc2t7 = count_int_spc2t7 +1;
340 `PR_INFO("n2_int", `INFO, "count_int_spc2t7 = %d",
341 count_int_spc2t7);
342 end
343 end
344
345
346//--------------------------------------
347 if((cpx_spc3_data_cx2[145] == 1'b1) && (cpx_spc3_data_cx2[144:141] == 4'b0111))
348 begin
349 if (cpx_spc3_data_cx2[10:8] == 3'b000)
350 begin
351 count_int_spc3t0 = count_int_spc3t0 +1;
352 `PR_INFO("n2_int", `INFO, "count_int_spc3t0 = %d",
353 count_int_spc3t0);
354 end
355 else if (cpx_spc3_data_cx2[10:8] == 3'b001)
356 begin
357 count_int_spc3t1 = count_int_spc3t1 +1;
358 `PR_INFO("n2_int", `INFO, "count_int_spc3t1 = %d",
359 count_int_spc3t1);
360 end
361 else if (cpx_spc3_data_cx2[10:8] == 3'b010)
362 begin
363 count_int_spc3t2 = count_int_spc3t2 +1;
364 `PR_INFO("n2_int", `INFO, "count_int_spc3t2 = %d",
365 count_int_spc3t2);
366 end
367 else if (cpx_spc3_data_cx2[10:8] == 3'b011)
368 begin
369 count_int_spc3t3 = count_int_spc3t3 +1;
370 `PR_INFO("n2_int", `INFO, "count_int_spc3t3 = %d",
371 count_int_spc3t3);
372 end
373 else if (cpx_spc3_data_cx2[10:8] == 3'b100)
374 begin
375 count_int_spc3t4 = count_int_spc3t4 +1;
376 `PR_INFO("n2_int", `INFO, "count_int_spc3t4 = %d",
377 count_int_spc3t4);
378 end
379 else if (cpx_spc3_data_cx2[10:8] == 3'b101)
380 begin
381 count_int_spc3t5 = count_int_spc3t5 +1;
382 `PR_INFO("n2_int", `INFO, "count_int_spc3t5 = %d",
383 count_int_spc3t5);
384 end
385 else if (cpx_spc3_data_cx2[10:8] == 3'b110)
386 begin
387 count_int_spc3t6 = count_int_spc3t6 +1;
388 `PR_INFO("n2_int", `INFO, "count_int_spc3t6 = %d",
389 count_int_spc3t6);
390 end
391 else if (cpx_spc3_data_cx2[10:8] == 3'b111)
392 begin
393 count_int_spc3t7 = count_int_spc3t7 +1;
394 `PR_INFO("n2_int", `INFO, "count_int_spc3t7 = %d",
395 count_int_spc3t7);
396 end
397 end
398
399
400//--------------------------------------
401 if((cpx_spc4_data_cx2[145] == 1'b1) && (cpx_spc4_data_cx2[144:141] == 4'b0111))
402 begin
403 if (cpx_spc4_data_cx2[10:8] == 3'b000)
404 begin
405 count_int_spc4t0 = count_int_spc4t0 +1;
406 `PR_INFO("n2_int", `INFO, "count_int_spc4t0 = %d",
407 count_int_spc4t0);
408 end
409 else if (cpx_spc4_data_cx2[10:8] == 3'b001)
410 begin
411 count_int_spc4t1 = count_int_spc4t1 +1;
412 `PR_INFO("n2_int", `INFO, "count_int_spc4t1 = %d",
413 count_int_spc4t1);
414 end
415 else if (cpx_spc4_data_cx2[10:8] == 3'b010)
416 begin
417 count_int_spc4t2 = count_int_spc4t2 +1;
418 `PR_INFO("n2_int", `INFO, "count_int_spc4t2 = %d",
419 count_int_spc4t2);
420 end
421 else if (cpx_spc4_data_cx2[10:8] == 3'b011)
422 begin
423 count_int_spc4t3 = count_int_spc4t3 +1;
424 `PR_INFO("n2_int", `INFO, "count_int_spc4t3 = %d",
425 count_int_spc4t3);
426 end
427 else if (cpx_spc4_data_cx2[10:8] == 3'b100)
428 begin
429 count_int_spc4t4 = count_int_spc4t4 +1;
430 `PR_INFO("n2_int", `INFO, "count_int_spc4t4 = %d",
431 count_int_spc4t4);
432 end
433 else if (cpx_spc4_data_cx2[10:8] == 3'b101)
434 begin
435 count_int_spc4t5 = count_int_spc4t5 +1;
436 `PR_INFO("n2_int", `INFO, "count_int_spc4t5 = %d",
437 count_int_spc4t5);
438 end
439 else if (cpx_spc4_data_cx2[10:8] == 3'b110)
440 begin
441 count_int_spc4t6 = count_int_spc4t6 +1;
442 `PR_INFO("n2_int", `INFO, "count_int_spc4t6 = %d",
443 count_int_spc4t6);
444 end
445 else if (cpx_spc4_data_cx2[10:8] == 3'b111)
446 begin
447 count_int_spc4t7 = count_int_spc4t7 +1;
448 `PR_INFO("n2_int", `INFO, "count_int_spc4t7 = %d",
449 count_int_spc4t7);
450 end
451 end
452
453
454//--------------------------------------
455 if((cpx_spc5_data_cx2[145] == 1'b1) && (cpx_spc5_data_cx2[144:141] == 4'b0111))
456 begin
457 if (cpx_spc5_data_cx2[10:8] == 3'b000)
458 begin
459 count_int_spc5t0 = count_int_spc5t0 +1;
460 `PR_INFO("n2_int", `INFO, "count_int_spc5t0 = %d",
461 count_int_spc5t0);
462 end
463 else if (cpx_spc5_data_cx2[10:8] == 3'b001)
464 begin
465 count_int_spc5t1 = count_int_spc5t1 +1;
466 `PR_INFO("n2_int", `INFO, "count_int_spc5t1 = %d",
467 count_int_spc5t1);
468 end
469 else if (cpx_spc5_data_cx2[10:8] == 3'b010)
470 begin
471 count_int_spc5t2 = count_int_spc5t2 +1;
472 `PR_INFO("n2_int", `INFO, "count_int_spc5t2 = %d",
473 count_int_spc5t2);
474 end
475 else if (cpx_spc5_data_cx2[10:8] == 3'b011)
476 begin
477 count_int_spc5t3 = count_int_spc5t3 +1;
478 `PR_INFO("n2_int", `INFO, "count_int_spc5t3 = %d",
479 count_int_spc5t3);
480 end
481 else if (cpx_spc5_data_cx2[10:8] == 3'b100)
482 begin
483 count_int_spc5t4 = count_int_spc5t4 +1;
484 `PR_INFO("n2_int", `INFO, "count_int_spc5t4 = %d",
485 count_int_spc5t4);
486 end
487 else if (cpx_spc5_data_cx2[10:8] == 3'b101)
488 begin
489 count_int_spc5t5 = count_int_spc5t5 +1;
490 `PR_INFO("n2_int", `INFO, "count_int_spc5t5 = %d",
491 count_int_spc5t5);
492 end
493 else if (cpx_spc5_data_cx2[10:8] == 3'b110)
494 begin
495 count_int_spc5t6 = count_int_spc5t6 +1;
496 `PR_INFO("n2_int", `INFO, "count_int_spc5t6 = %d",
497 count_int_spc5t6);
498 end
499 else if (cpx_spc5_data_cx2[10:8] == 3'b111)
500 begin
501 count_int_spc5t7 = count_int_spc5t7 +1;
502 `PR_INFO("n2_int", `INFO, "count_int_spc5t7 = %d",
503 count_int_spc5t7);
504 end
505 end
506
507
508//--------------------------------------
509 if((cpx_spc6_data_cx2[145] == 1'b1) && (cpx_spc6_data_cx2[144:141] == 4'b0111))
510 begin
511 if (cpx_spc6_data_cx2[10:8] == 3'b000)
512 begin
513 count_int_spc6t0 = count_int_spc6t0 +1;
514 `PR_INFO("n2_int", `INFO, "count_int_spc6t0 = %d",
515 count_int_spc6t0);
516 end
517 else if (cpx_spc6_data_cx2[10:8] == 3'b001)
518 begin
519 count_int_spc6t1 = count_int_spc6t1 +1;
520 `PR_INFO("n2_int", `INFO, "count_int_spc6t1 = %d",
521 count_int_spc6t1);
522 end
523 else if (cpx_spc6_data_cx2[10:8] == 3'b010)
524 begin
525 count_int_spc6t2 = count_int_spc6t2 +1;
526 `PR_INFO("n2_int", `INFO, "count_int_spc6t2 = %d",
527 count_int_spc6t2);
528 end
529 else if (cpx_spc6_data_cx2[10:8] == 3'b011)
530 begin
531 count_int_spc6t3 = count_int_spc6t3 +1;
532 `PR_INFO("n2_int", `INFO, "count_int_spc6t3 = %d",
533 count_int_spc6t3);
534 end
535 else if (cpx_spc6_data_cx2[10:8] == 3'b100)
536 begin
537 count_int_spc6t4 = count_int_spc6t4 +1;
538 `PR_INFO("n2_int", `INFO, "count_int_spc6t4 = %d",
539 count_int_spc6t4);
540 end
541 else if (cpx_spc6_data_cx2[10:8] == 3'b101)
542 begin
543 count_int_spc6t5 = count_int_spc6t5 +1;
544 `PR_INFO("n2_int", `INFO, "count_int_spc6t5 = %d",
545 count_int_spc6t5);
546 end
547 else if (cpx_spc6_data_cx2[10:8] == 3'b110)
548 begin
549 count_int_spc6t6 = count_int_spc6t6 +1;
550 `PR_INFO("n2_int", `INFO, "count_int_spc6t6 = %d",
551 count_int_spc6t6);
552 end
553 else if (cpx_spc6_data_cx2[10:8] == 3'b111)
554 begin
555 count_int_spc6t7 = count_int_spc6t7 +1;
556 `PR_INFO("n2_int", `INFO, "count_int_spc6t7 = %d",
557 count_int_spc6t7);
558 end
559 end
560
561
562//--------------------------------------
563 if((cpx_spc7_data_cx2[145] == 1'b1) && (cpx_spc7_data_cx2[144:141] == 4'b0111))
564 begin
565 if (cpx_spc7_data_cx2[10:8] == 3'b000)
566 begin
567 count_int_spc7t0 = count_int_spc7t0 +1;
568 `PR_INFO("n2_int", `INFO, "count_int_spc7t0 = %d",
569 count_int_spc7t0);
570 end
571 else if (cpx_spc7_data_cx2[10:8] == 3'b001)
572 begin
573 count_int_spc7t1 = count_int_spc7t1 +1;
574 `PR_INFO("n2_int", `INFO, "count_int_spc7t1 = %d",
575 count_int_spc7t1);
576 end
577 else if (cpx_spc7_data_cx2[10:8] == 3'b010)
578 begin
579 count_int_spc7t2 = count_int_spc7t2 +1;
580 `PR_INFO("n2_int", `INFO, "count_int_spc7t2 = %d",
581 count_int_spc7t2);
582 end
583 else if (cpx_spc7_data_cx2[10:8] == 3'b011)
584 begin
585 count_int_spc7t3 = count_int_spc7t3 +1;
586 `PR_INFO("n2_int", `INFO, "count_int_spc7t3 = %d",
587 count_int_spc7t3);
588 end
589 else if (cpx_spc7_data_cx2[10:8] == 3'b100)
590 begin
591 count_int_spc7t4 = count_int_spc7t4 +1;
592 `PR_INFO("n2_int", `INFO, "count_int_spc7t4 = %d",
593 count_int_spc7t4);
594 end
595 else if (cpx_spc7_data_cx2[10:8] == 3'b101)
596 begin
597 count_int_spc7t5 = count_int_spc7t5 +1;
598 `PR_INFO("n2_int", `INFO, "count_int_spc7t5 = %d",
599 count_int_spc7t5);
600 end
601 else if (cpx_spc7_data_cx2[10:8] == 3'b110)
602 begin
603 count_int_spc7t6 = count_int_spc7t6 +1;
604 `PR_INFO("n2_int", `INFO, "count_int_spc7t6 = %d",
605 count_int_spc7t6);
606 end
607 else if (cpx_spc7_data_cx2[10:8] == 3'b111)
608 begin
609 count_int_spc7t7 = count_int_spc7t7 +1;
610 `PR_INFO("n2_int", `INFO, "count_int_spc7t7 = %d",
611 count_int_spc7t7);
612 end
613 end
614end // always @ (posedge clk)
615
616always @ (posedge tb_top.sim_status[0]) begin
617`ifndef RTL_NO_SPC0
618 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t0 = %d",
619 count_int_spc0t0);
620 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t1 = %d",
621 count_int_spc0t1);
622 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t2 = %d",
623 count_int_spc0t2);
624 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t3 = %d",
625 count_int_spc0t3);
626 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t4 = %d",
627 count_int_spc0t4);
628 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t5 = %d",
629 count_int_spc0t5);
630 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t6 = %d",
631 count_int_spc0t6);
632 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc0t7 = %d",
633 count_int_spc0t7);
634`endif // `ifndef RTL_NO_SPC0
635`ifndef RTL_NO_SPC1
636 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t0 = %d",
637 count_int_spc1t0);
638 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t1 = %d",
639 count_int_spc1t1);
640 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t2 = %d",
641 count_int_spc1t2);
642 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t3 = %d",
643 count_int_spc1t3);
644 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t4 = %d",
645 count_int_spc1t4);
646 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t5 = %d",
647 count_int_spc1t5);
648 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t6 = %d",
649 count_int_spc1t6);
650 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc1t7 = %d",
651 count_int_spc1t7);
652`endif // `ifndef RTL_NO_SPC1
653`ifndef RTL_NO_SPC2
654 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t0 = %d",
655 count_int_spc2t0);
656 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t1 = %d",
657 count_int_spc2t1);
658 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t2 = %d",
659 count_int_spc2t2);
660 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t3 = %d",
661 count_int_spc2t3);
662 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t4 = %d",
663 count_int_spc2t4);
664 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t5 = %d",
665 count_int_spc2t5);
666 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t6 = %d",
667 count_int_spc2t6);
668 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc2t7 = %d",
669 count_int_spc2t7);
670`endif // `ifndef RTL_NO_SPC2
671`ifndef RTL_NO_SPC3
672 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t0 = %d",
673 count_int_spc3t0);
674 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t1 = %d",
675 count_int_spc3t1);
676 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t2 = %d",
677 count_int_spc3t2);
678 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t3 = %d",
679 count_int_spc3t3);
680 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t4 = %d",
681 count_int_spc3t4);
682 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t5 = %d",
683 count_int_spc3t5);
684 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t6 = %d",
685 count_int_spc3t6);
686 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc3t7 = %d",
687 count_int_spc3t7);
688`endif // `ifndef RTL_NO_SPC3
689`ifndef RTL_NO_SPC4
690 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t0 = %d",
691 count_int_spc4t0);
692 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t1 = %d",
693 count_int_spc4t1);
694 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t2 = %d",
695 count_int_spc4t2);
696 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t3 = %d",
697 count_int_spc4t3);
698 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t4 = %d",
699 count_int_spc4t4);
700 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t5 = %d",
701 count_int_spc4t5);
702 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t6 = %d",
703 count_int_spc4t6);
704 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc4t7 = %d",
705 count_int_spc4t7);
706`endif // `ifndef RTL_NO_SPC4
707`ifndef RTL_NO_SPC5
708 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t0 = %d",
709 count_int_spc5t0);
710 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t1 = %d",
711 count_int_spc5t1);
712 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t2 = %d",
713 count_int_spc5t2);
714 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t3 = %d",
715 count_int_spc5t3);
716 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t4 = %d",
717 count_int_spc5t4);
718 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t5 = %d",
719 count_int_spc5t5);
720 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t6 = %d",
721 count_int_spc5t6);
722 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc5t7 = %d",
723 count_int_spc5t7);
724`endif // `ifndef RTL_NO_SPC5
725`ifndef RTL_NO_SPC6
726 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t0 = %d",
727 count_int_spc6t0);
728 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t1 = %d",
729 count_int_spc6t1);
730 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t2 = %d",
731 count_int_spc6t2);
732 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t3 = %d",
733 count_int_spc6t3);
734 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t4 = %d",
735 count_int_spc6t4);
736 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t5 = %d",
737 count_int_spc6t5);
738 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t6 = %d",
739 count_int_spc6t6);
740 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc6t7 = %d",
741 count_int_spc6t7);
742`endif // `ifndef RTL_NO_SPC7
743`ifndef RTL_NO_SPC7
744 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t0 = %d",
745 count_int_spc7t0);
746 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t1 = %d",
747 count_int_spc7t1);
748 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t2 = %d",
749 count_int_spc7t2);
750 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t3 = %d",
751 count_int_spc7t3);
752 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t4 = %d",
753 count_int_spc7t4);
754 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t5 = %d",
755 count_int_spc7t5);
756 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t6 = %d",
757 count_int_spc7t6);
758 `PR_INFO("n2_int", `INFO, "Number of interrupts sent to spc7t7 = %d",
759 count_int_spc7t7);
760`endif // `ifndef RTL_NO_SPC7
761end // always @ (posedge (tb_top.sim_status[0]))
762
763
764endmodule // n2_int
Full OpenSPARC design & verification tarball including full HDL.