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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / monitors / nb_crc_mon.v
CommitLineData
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: nb_crc_mon.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`timescale 1ps/1ps
36
37`ifdef MCUSAT
38 `include "mcu_dispmonDefines.vh"
39`else
40 `include "defines.vh"
41 `include "dispmonDefines.vh"
42`endif
43
44module nb_crc_mon();
45
46wire drl2clk = `MCU0.drl2clk;
47wire rst_wmr_protect = `CPU.rst_wmr_protect;
48
49wire fbdic_crc_error_0 = `MCU0.fbdic.fbdic_crc_error ;
50wire fbdic_crc_error_1 = `MCU1.fbdic.fbdic_crc_error ;
51wire fbdic_crc_error_2 = `MCU2.fbdic.fbdic_crc_error ;
52wire fbdic_crc_error_3 = `MCU3.fbdic.fbdic_crc_error ;
53
54wire fbdic_rddata_vld_0 = tb_top.cpu.mcu0.fbdic_rddata_vld;
55wire fbdic_rddata_vld_1 = tb_top.cpu.mcu1.fbdic_rddata_vld;
56wire fbdic_rddata_vld_2 = tb_top.cpu.mcu2.fbdic_rddata_vld;
57wire fbdic_rddata_vld_3 = tb_top.cpu.mcu3.fbdic_rddata_vld;
58
59wire mcu0_fbdird_crc_cmp0_0 = tb_top.cpu.mcu0.fbdird_crc_cmp0_0;
60wire mcu0_fbdird_crc_cmp0_1 = tb_top.cpu.mcu0.fbdird_crc_cmp0_1;
61wire mcu0_fbdird_crc_cmp1_0 = tb_top.cpu.mcu0.fbdird_crc_cmp1_0;
62wire mcu0_fbdird_crc_cmp1_1 = tb_top.cpu.mcu0.fbdird_crc_cmp1_1;
63
64wire mcu1_fbdird_crc_cmp0_0 = tb_top.cpu.mcu1.fbdird_crc_cmp0_0;
65wire mcu1_fbdird_crc_cmp0_1 = tb_top.cpu.mcu1.fbdird_crc_cmp0_1;
66wire mcu1_fbdird_crc_cmp1_0 = tb_top.cpu.mcu1.fbdird_crc_cmp1_0;
67wire mcu1_fbdird_crc_cmp1_1 = tb_top.cpu.mcu1.fbdird_crc_cmp1_1;
68
69wire mcu2_fbdird_crc_cmp0_0 = tb_top.cpu.mcu2.fbdird_crc_cmp0_0;
70wire mcu2_fbdird_crc_cmp0_1 = tb_top.cpu.mcu2.fbdird_crc_cmp0_1;
71wire mcu2_fbdird_crc_cmp1_0 = tb_top.cpu.mcu2.fbdird_crc_cmp1_0;
72wire mcu2_fbdird_crc_cmp1_1 = tb_top.cpu.mcu2.fbdird_crc_cmp1_1;
73
74wire mcu3_fbdird_crc_cmp0_0 = tb_top.cpu.mcu3.fbdird_crc_cmp0_0;
75wire mcu3_fbdird_crc_cmp0_1 = tb_top.cpu.mcu3.fbdird_crc_cmp0_1;
76wire mcu3_fbdird_crc_cmp1_0 = tb_top.cpu.mcu3.fbdird_crc_cmp1_0;
77wire mcu3_fbdird_crc_cmp1_1 = tb_top.cpu.mcu3.fbdird_crc_cmp1_1;
78
79wire [11:0] mcu0_act_crc00 = tb_top.cpu.mcu0.fbdird.crc_cmp0_0_actual;
80wire [11:0] mcu0_act_crc01 = tb_top.cpu.mcu0.fbdird.crc_cmp0_1_actual;
81wire [11:0] mcu0_act_crc10 = tb_top.cpu.mcu0.fbdird.crc_cmp1_0_actual;
82wire [11:0] mcu0_act_crc11 = tb_top.cpu.mcu0.fbdird.crc_cmp1_1_actual;
83
84wire [11:0] mcu1_act_crc00 = tb_top.cpu.mcu1.fbdird.crc_cmp0_0_actual;
85wire [11:0] mcu1_act_crc01 = tb_top.cpu.mcu1.fbdird.crc_cmp0_1_actual;
86wire [11:0] mcu1_act_crc10 = tb_top.cpu.mcu1.fbdird.crc_cmp1_0_actual;
87wire [11:0] mcu1_act_crc11 = tb_top.cpu.mcu1.fbdird.crc_cmp1_1_actual;
88
89wire [11:0] mcu2_act_crc00 = tb_top.cpu.mcu2.fbdird.crc_cmp0_0_actual;
90wire [11:0] mcu2_act_crc01 = tb_top.cpu.mcu2.fbdird.crc_cmp0_1_actual;
91wire [11:0] mcu2_act_crc10 = tb_top.cpu.mcu2.fbdird.crc_cmp1_0_actual;
92wire [11:0] mcu2_act_crc11 = tb_top.cpu.mcu2.fbdird.crc_cmp1_1_actual;
93
94wire [11:0] mcu3_act_crc00 = tb_top.cpu.mcu3.fbdird.crc_cmp0_0_actual;
95wire [11:0] mcu3_act_crc01 = tb_top.cpu.mcu3.fbdird.crc_cmp0_1_actual;
96wire [11:0] mcu3_act_crc10 = tb_top.cpu.mcu3.fbdird.crc_cmp1_0_actual;
97wire [11:0] mcu3_act_crc11 = tb_top.cpu.mcu3.fbdird.crc_cmp1_1_actual;
98
99wire [11:0] mcu0_rtl_exp_crc00 = tb_top.cpu.mcu0.fbdird.crc_cmp0_0_expected;
100wire [11:0] mcu0_rtl_exp_crc01 = tb_top.cpu.mcu0.fbdird.crc_cmp0_1_expected;
101wire [11:0] mcu0_rtl_exp_crc10 = tb_top.cpu.mcu0.fbdird.crc_cmp1_0_expected;
102wire [11:0] mcu0_rtl_exp_crc11 = tb_top.cpu.mcu0.fbdird.crc_cmp1_1_expected;
103
104wire [11:0] mcu1_rtl_exp_crc00 = tb_top.cpu.mcu1.fbdird.crc_cmp0_0_expected;
105wire [11:0] mcu1_rtl_exp_crc01 = tb_top.cpu.mcu1.fbdird.crc_cmp0_1_expected;
106wire [11:0] mcu1_rtl_exp_crc10 = tb_top.cpu.mcu1.fbdird.crc_cmp1_0_expected;
107wire [11:0] mcu1_rtl_exp_crc11 = tb_top.cpu.mcu1.fbdird.crc_cmp1_1_expected;
108
109wire [11:0] mcu2_rtl_exp_crc00 = tb_top.cpu.mcu2.fbdird.crc_cmp0_0_expected;
110wire [11:0] mcu2_rtl_exp_crc01 = tb_top.cpu.mcu2.fbdird.crc_cmp0_1_expected;
111wire [11:0] mcu2_rtl_exp_crc10 = tb_top.cpu.mcu2.fbdird.crc_cmp1_0_expected;
112wire [11:0] mcu2_rtl_exp_crc11 = tb_top.cpu.mcu2.fbdird.crc_cmp1_1_expected;
113
114wire [11:0] mcu3_rtl_exp_crc00 = tb_top.cpu.mcu3.fbdird.crc_cmp0_0_expected;
115wire [11:0] mcu3_rtl_exp_crc01 = tb_top.cpu.mcu3.fbdird.crc_cmp0_1_expected;
116wire [11:0] mcu3_rtl_exp_crc10 = tb_top.cpu.mcu3.fbdird.crc_cmp1_0_expected;
117wire [11:0] mcu3_rtl_exp_crc11 = tb_top.cpu.mcu3.fbdird.crc_cmp1_1_expected;
118
119wire [71:0] mcu0_bd00 = tb_top.cpu.mcu0.fbdird.bd00;
120wire [71:0] mcu0_bd01 = tb_top.cpu.mcu0.fbdird.bd01;
121wire [71:0] mcu0_bd10 = tb_top.cpu.mcu0.fbdird.bd10;
122wire [71:0] mcu0_bd11 = tb_top.cpu.mcu0.fbdird.bd11;
123
124wire [71:0] mcu1_bd00 = tb_top.cpu.mcu1.fbdird.bd00;
125wire [71:0] mcu1_bd01 = tb_top.cpu.mcu1.fbdird.bd01;
126wire [71:0] mcu1_bd10 = tb_top.cpu.mcu1.fbdird.bd10;
127wire [71:0] mcu1_bd11 = tb_top.cpu.mcu1.fbdird.bd11;
128
129wire [71:0] mcu2_bd00 = tb_top.cpu.mcu2.fbdird.bd00;
130wire [71:0] mcu2_bd01 = tb_top.cpu.mcu2.fbdird.bd01;
131wire [71:0] mcu2_bd10 = tb_top.cpu.mcu2.fbdird.bd10;
132wire [71:0] mcu2_bd11 = tb_top.cpu.mcu2.fbdird.bd11;
133
134wire [71:0] mcu3_bd00 = tb_top.cpu.mcu3.fbdird.bd00;
135wire [71:0] mcu3_bd01 = tb_top.cpu.mcu3.fbdird.bd01;
136wire [71:0] mcu3_bd10 = tb_top.cpu.mcu3.fbdird.bd10;
137wire [71:0] mcu3_bd11 = tb_top.cpu.mcu3.fbdird.bd11;
138
139wire [11:0] mcu0_exp_crc00 , mcu0_exp_crc01 , mcu0_exp_crc10 , mcu0_exp_crc11 ; // monitor expected
140wire [11:0] mcu1_exp_crc00 , mcu1_exp_crc01 , mcu1_exp_crc10 , mcu1_exp_crc11 ; // monitor expected
141wire [11:0] mcu2_exp_crc00 , mcu2_exp_crc01 , mcu2_exp_crc10 , mcu2_exp_crc11 ; // monitor expected
142wire [11:0] mcu3_exp_crc00 , mcu3_exp_crc01 , mcu3_exp_crc10 , mcu3_exp_crc11 ; // monitor expected
143
144reg enabled;
145
146initial
147begin
148 enabled = 1'b1;
149 if ($test$plusargs("nb_crc_mon_disable"))
150 enabled = 1'b0;
151end
152
153//-----------------------------------
154// Disable nb_crc_mon during Warm Reset
155//-----------------------------------
156
157always @ (posedge rst_wmr_protect)
158begin
159 enabled = 1'b0;
160end
161
162always @ (negedge rst_wmr_protect)
163begin
164 if (!($test$plusargs("nb_crc_mon_disable")))
165 enabled = 1'b1;
166end
167
168always @(posedge (drl2clk && enabled))
169begin
170
171if (fbdic_rddata_vld_0)
172begin
173 if (mcu0_exp_crc00 != mcu0_act_crc00)
174 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN00 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu0_act_crc00, mcu0_exp_crc00);
175 if (mcu0_exp_crc01 != mcu0_act_crc01)
176 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN01 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu0_act_crc01, mcu0_exp_crc01);
177 if (mcu0_exp_crc10 != mcu0_act_crc10)
178 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN10 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu0_act_crc10, mcu0_exp_crc10);
179 if (mcu0_exp_crc11 != mcu0_act_crc11)
180 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN11 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu0_act_crc11, mcu0_exp_crc11);
181
182 if (mcu0_exp_crc00 != mcu0_rtl_exp_crc00)
183 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN00 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu0_rtl_exp_crc00, mcu0_exp_crc00);
184 if (mcu0_exp_crc01 != mcu0_rtl_exp_crc01)
185 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN01 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu0_rtl_exp_crc01, mcu0_exp_crc01);
186 if (mcu0_exp_crc10 != mcu0_rtl_exp_crc10)
187 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN10 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu0_rtl_exp_crc10, mcu0_exp_crc10);
188 if (mcu0_exp_crc11 != mcu0_rtl_exp_crc11)
189 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN11 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu0_rtl_exp_crc11, mcu0_exp_crc11);
190
191 if (mcu0_fbdird_crc_cmp0_0 == 0)
192 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN00 mcu0_fbdird_crc_cmp0_0 is not asserted");
193 if (mcu0_fbdird_crc_cmp0_1 == 0)
194 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN01 mcu0_fbdird_crc_cmp0_1 is not asserted");
195 if (mcu0_fbdird_crc_cmp1_0 == 0)
196 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN10 mcu0_fbdird_crc_cmp1_0 is not asserted");
197 if (mcu0_fbdird_crc_cmp1_1 == 0)
198 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU0 CHN11 mcu0_fbdird_crc_cmp1_1 is not asserted");
199
200end
201
202if (fbdic_rddata_vld_1)
203begin
204 if (mcu1_exp_crc00 != mcu1_act_crc00)
205 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN00 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu1_act_crc00, mcu1_exp_crc00);
206 if (mcu1_exp_crc01 != mcu1_act_crc01)
207 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN01 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu1_act_crc01, mcu1_exp_crc01);
208 if (mcu1_exp_crc10 != mcu1_act_crc10)
209 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN10 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu1_act_crc10, mcu1_exp_crc10);
210 if (mcu1_exp_crc11 != mcu1_act_crc11)
211 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN11 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu1_act_crc11, mcu1_exp_crc11);
212
213 if (mcu1_exp_crc00 != mcu1_rtl_exp_crc00)
214 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN00 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu1_rtl_exp_crc00, mcu1_exp_crc00);
215 if (mcu1_exp_crc01 != mcu1_rtl_exp_crc01)
216 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN01 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu1_rtl_exp_crc01, mcu1_exp_crc01);
217 if (mcu1_exp_crc10 != mcu1_rtl_exp_crc10)
218 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN10 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu1_rtl_exp_crc10, mcu1_exp_crc10);
219 if (mcu1_exp_crc11 != mcu1_rtl_exp_crc11)
220 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN11 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu1_rtl_exp_crc11, mcu1_exp_crc11);
221
222 if (mcu1_fbdird_crc_cmp0_0 == 0)
223 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN00 mcu1_fbdird_crc_cmp0_0 is not asserted");
224 if (mcu1_fbdird_crc_cmp0_1 == 0)
225 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN01 mcu1_fbdird_crc_cmp0_1 is not asserted");
226 if (mcu1_fbdird_crc_cmp1_0 == 0)
227 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN10 mcu1_fbdird_crc_cmp1_0 is not asserted");
228 if (mcu1_fbdird_crc_cmp1_1 == 0)
229 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU1 CHN11 mcu1_fbdird_crc_cmp1_1 is not asserted");
230end
231
232if (fbdic_rddata_vld_2)
233begin
234 if (mcu2_exp_crc00 != mcu2_act_crc00)
235 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN00 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu2_act_crc00, mcu2_exp_crc00);
236 if (mcu2_exp_crc01 != mcu2_act_crc01)
237 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN01 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu2_act_crc01, mcu2_exp_crc01);
238 if (mcu2_exp_crc10 != mcu2_act_crc10)
239 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN10 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu2_act_crc10, mcu2_exp_crc10);
240 if (mcu2_exp_crc11 != mcu2_act_crc11)
241 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN11 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu2_act_crc11, mcu2_exp_crc11);
242
243 if (mcu2_exp_crc00 != mcu2_rtl_exp_crc00)
244 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN00 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu2_rtl_exp_crc00, mcu2_exp_crc00);
245 if (mcu2_exp_crc01 != mcu2_rtl_exp_crc01)
246 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN01 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu2_rtl_exp_crc01, mcu2_exp_crc01);
247 if (mcu2_exp_crc10 != mcu2_rtl_exp_crc10)
248 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN10 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu2_rtl_exp_crc10, mcu2_exp_crc10);
249 if (mcu2_exp_crc11 != mcu2_rtl_exp_crc11)
250 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN11 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu2_rtl_exp_crc11, mcu2_exp_crc11);
251
252 if (mcu2_fbdird_crc_cmp0_0 == 0)
253 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN00 mcu2_fbdird_crc_cmp0_0 is not asserted");
254 if (mcu2_fbdird_crc_cmp0_1 == 0)
255 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN01 mcu2_fbdird_crc_cmp0_1 is not asserted");
256 if (mcu2_fbdird_crc_cmp1_0 == 0)
257 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN10 mcu2_fbdird_crc_cmp1_0 is not asserted");
258 if (mcu2_fbdird_crc_cmp1_1 == 0)
259 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU2 CHN11 mcu2_fbdird_crc_cmp1_1 is not asserted");
260end
261
262if (fbdic_rddata_vld_3)
263begin
264 if (mcu3_exp_crc00 != mcu3_act_crc00)
265 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN00 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu3_act_crc00, mcu3_exp_crc00);
266 if (mcu3_exp_crc01 != mcu3_act_crc01)
267 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN01 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu3_act_crc01, mcu3_exp_crc01);
268 if (mcu3_exp_crc10 != mcu3_act_crc10)
269 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN10 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu3_act_crc10, mcu3_exp_crc10);
270 if (mcu3_exp_crc11 != mcu3_act_crc11)
271 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN11 CRC-12 Mismatch : ACT CRC == %h\tMON EXP CRC == %h",mcu3_act_crc11, mcu3_exp_crc11);
272
273 if (mcu3_exp_crc00 != mcu3_rtl_exp_crc00)
274 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN00 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu3_rtl_exp_crc00, mcu3_exp_crc00);
275 if (mcu3_exp_crc01 != mcu3_rtl_exp_crc01)
276 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN01 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu3_rtl_exp_crc01, mcu3_exp_crc01);
277 if (mcu3_exp_crc10 != mcu3_rtl_exp_crc10)
278 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN10 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu3_rtl_exp_crc10, mcu3_exp_crc10);
279 if (mcu3_exp_crc11 != mcu3_rtl_exp_crc11)
280 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN11 CRC-12 Mismatch : RTL EXP CRC == %h\tMON EXP CRC == %h",mcu3_rtl_exp_crc11, mcu3_exp_crc11);
281
282 if (mcu3_fbdird_crc_cmp0_0 == 0)
283 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN00 mcu3_fbdird_crc_cmp0_0 is not asserted");
284 if (mcu3_fbdird_crc_cmp0_1 == 0)
285 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN01 mcu3_fbdird_crc_cmp0_1 is not asserted");
286 if (mcu3_fbdird_crc_cmp1_0 == 0)
287 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN10 mcu3_fbdird_crc_cmp1_0 is not asserted");
288 if (mcu3_fbdird_crc_cmp1_1 == 0)
289 `PR_ERROR("nb_crc_mon", `ERROR, "NB MCU3 CHN11 mcu3_fbdird_crc_cmp1_1 is not asserted");
290end
291
292end
293
294`ifdef MCU_FAILOVER_MODE
295
296nbmon_gen_crc_fl mcu0_crc00_fl ( .d (mcu0_bd00), .crc_fl (mcu0_exp_crc00[5:0]) );
297nbmon_gen_crc_fl mcu0_crc01_fl ( .d (mcu0_bd01), .crc_fl (mcu0_exp_crc01[5:0]) );
298nbmon_gen_crc_fl mcu0_crc10_fl ( .d (mcu0_bd10), .crc_fl (mcu0_exp_crc10[5:0]) );
299nbmon_gen_crc_fl mcu0_crc11_fl ( .d (mcu0_bd11), .crc_fl (mcu0_exp_crc11[5:0]) );
300
301nbmon_gen_crc_fl mcu1_crc00_fl ( .d (mcu1_bd00), .crc_fl (mcu1_exp_crc00[5:0]) );
302nbmon_gen_crc_fl mcu1_crc01_fl ( .d (mcu1_bd01), .crc_fl (mcu1_exp_crc01[5:0]) );
303nbmon_gen_crc_fl mcu1_crc10_fl ( .d (mcu1_bd10), .crc_fl (mcu1_exp_crc10[5:0]) );
304nbmon_gen_crc_fl mcu1_crc11_fl ( .d (mcu1_bd11), .crc_fl (mcu1_exp_crc11[5:0]) );
305
306nbmon_gen_crc_fl mcu2_crc00_fl ( .d (mcu2_bd00), .crc_fl (mcu2_exp_crc00[5:0]) );
307nbmon_gen_crc_fl mcu2_crc01_fl ( .d (mcu2_bd01), .crc_fl (mcu2_exp_crc01[5:0]) );
308nbmon_gen_crc_fl mcu2_crc10_fl ( .d (mcu2_bd10), .crc_fl (mcu2_exp_crc10[5:0]) );
309nbmon_gen_crc_fl mcu2_crc11_fl ( .d (mcu2_bd11), .crc_fl (mcu2_exp_crc11[5:0]) );
310
311nbmon_gen_crc_fl mcu3_crc00_fl ( .d (mcu3_bd00), .crc_fl (mcu3_exp_crc00[5:0]) );
312nbmon_gen_crc_fl mcu3_crc01_fl ( .d (mcu3_bd01), .crc_fl (mcu3_exp_crc01[5:0]) );
313nbmon_gen_crc_fl mcu3_crc10_fl ( .d (mcu3_bd10), .crc_fl (mcu3_exp_crc10[5:0]) );
314nbmon_gen_crc_fl mcu3_crc11_fl ( .d (mcu3_bd11), .crc_fl (mcu3_exp_crc11[5:0]) );
315
316assign mcu0_exp_crc00[11:6] = 6'h0;
317assign mcu0_exp_crc01[11:6] = 6'h0;
318assign mcu0_exp_crc10[11:6] = 6'h0;
319assign mcu0_exp_crc11[11:6] = 6'h0;
320
321assign mcu1_exp_crc00[11:6] = 6'h0;
322assign mcu1_exp_crc01[11:6] = 6'h0;
323assign mcu1_exp_crc10[11:6] = 6'h0;
324assign mcu1_exp_crc11[11:6] = 6'h0;
325
326assign mcu2_exp_crc00[11:6] = 6'h0;
327assign mcu2_exp_crc01[11:6] = 6'h0;
328assign mcu2_exp_crc10[11:6] = 6'h0;
329assign mcu2_exp_crc11[11:6] = 6'h0;
330
331assign mcu3_exp_crc00[11:6] = 6'h0;
332assign mcu3_exp_crc01[11:6] = 6'h0;
333assign mcu3_exp_crc10[11:6] = 6'h0;
334assign mcu3_exp_crc11[11:6] = 6'h0;
335
336`else
337
338nbmon_gen_crc mcu0_crc00 ( .d (mcu0_bd00), .crc (mcu0_exp_crc00) );
339nbmon_gen_crc mcu0_crc01 ( .d (mcu0_bd01), .crc (mcu0_exp_crc01) );
340nbmon_gen_crc mcu0_crc10 ( .d (mcu0_bd10), .crc (mcu0_exp_crc10) );
341nbmon_gen_crc mcu0_crc11 ( .d (mcu0_bd11), .crc (mcu0_exp_crc11) );
342
343nbmon_gen_crc mcu1_crc00 ( .d (mcu1_bd00), .crc (mcu1_exp_crc00) );
344nbmon_gen_crc mcu1_crc01 ( .d (mcu1_bd01), .crc (mcu1_exp_crc01) );
345nbmon_gen_crc mcu1_crc10 ( .d (mcu1_bd10), .crc (mcu1_exp_crc10) );
346nbmon_gen_crc mcu1_crc11 ( .d (mcu1_bd11), .crc (mcu1_exp_crc11) );
347
348nbmon_gen_crc mcu2_crc00 ( .d (mcu2_bd00), .crc (mcu2_exp_crc00) );
349nbmon_gen_crc mcu2_crc01 ( .d (mcu2_bd01), .crc (mcu2_exp_crc01) );
350nbmon_gen_crc mcu2_crc10 ( .d (mcu2_bd10), .crc (mcu2_exp_crc10) );
351nbmon_gen_crc mcu2_crc11 ( .d (mcu2_bd11), .crc (mcu2_exp_crc11) );
352
353nbmon_gen_crc mcu3_crc00 ( .d (mcu3_bd00), .crc (mcu3_exp_crc00) );
354nbmon_gen_crc mcu3_crc01 ( .d (mcu3_bd01), .crc (mcu3_exp_crc01) );
355nbmon_gen_crc mcu3_crc10 ( .d (mcu3_bd10), .crc (mcu3_exp_crc10) );
356nbmon_gen_crc mcu3_crc11 ( .d (mcu3_bd11), .crc (mcu3_exp_crc11) );
357
358`endif
359
360endmodule
361
362module nbmon_gen_crc(d, crc);
363
364input [71:0] d;
365output [11:0] crc;
366
367assign crc[0] = d[71]^d[70]^d[68]^d[67]^d[66]^d[63]^
368 d[58]^d[56]^d[55]^d[54]^d[53]^d[52]^
369 d[49]^d[48]^d[46]^d[44]^d[42]^d[41]^
370 d[40]^d[39]^d[38]^d[37]^d[36]^d[35]^
371 d[34]^d[29]^d[26]^d[25]^d[22]^d[21]^
372 d[19]^d[18]^d[16]^d[12]^d[9]^d[8]^
373 d[7]^d[6]^d[3]^d[1]^d[0];
374
375assign crc[1] = d[70]^d[69]^d[66]^d[64]^d[63]^d[59]^
376 d[58]^d[57]^d[52]^d[50]^d[48]^d[47]^
377 d[46]^d[45]^d[44]^d[43]^d[34]^d[30]^
378 d[29]^d[27]^d[25]^d[23]^d[21]^d[20]^
379 d[18]^d[17]^d[16]^d[13]^d[12]^d[10]^
380 d[6]^d[4]^d[3]^d[2]^d[0];
381
382assign crc[2] = d[71]^d[70]^d[67]^d[65]^d[64]^d[60]^
383 d[59]^d[58]^d[53]^d[51]^d[49]^d[48]^
384 d[47]^d[46]^d[45]^d[44]^d[35]^d[31]^
385 d[30]^d[28]^d[26]^d[24]^d[22]^d[21]^
386 d[19]^d[18]^d[17]^d[14]^d[13]^d[11]^
387 d[7]^d[5]^d[4]^d[3]^d[1];
388
389assign crc[3] = d[70]^d[67]^d[65]^d[63]^d[61]^d[60]^
390 d[59]^d[58]^d[56]^d[55]^d[53]^d[50]^
391 d[47]^d[45]^d[44]^d[42]^d[41]^d[40]^
392 d[39]^d[38]^d[37]^d[35]^d[34]^d[32]^
393 d[31]^d[27]^d[26]^d[23]^d[21]^d[20]^
394 d[16]^d[15]^d[14]^d[9]^d[7]^d[5]^
395 d[4]^d[3]^d[2]^d[1]^d[0];
396
397assign crc[4] = d[70]^d[67]^d[64]^d[63]^d[62]^d[61]^
398 d[60]^d[59]^d[58]^d[57]^d[55]^d[53]^
399 d[52]^d[51]^d[49]^d[45]^d[44]^d[43]^
400 d[37]^d[34]^d[33]^d[32]^d[29]^d[28]^
401 d[27]^d[26]^d[25]^d[24]^d[19]^d[18]^
402 d[17]^d[15]^d[12]^d[10]^d[9]^d[7]^
403 d[5]^d[4]^d[2]^d[0];
404
405assign crc[5] = d[71]^d[68]^d[65]^d[64]^d[63]^d[62]^
406 d[61]^d[60]^d[59]^d[58]^d[56]^d[54]^
407 d[53]^d[52]^d[50]^d[46]^d[45]^d[44]^
408 d[38]^d[35]^d[34]^d[33]^d[30]^d[29]^
409 d[28]^d[27]^d[26]^d[25]^d[20]^d[19]^
410 d[18]^d[16]^d[13]^d[11]^d[10]^d[8]^
411 d[6]^d[5]^d[3]^d[1];
412
413assign crc[6] = d[71]^d[70]^d[69]^d[68]^d[67]^d[65]^
414 d[64]^d[62]^d[61]^d[60]^d[59]^d[58]^
415 d[57]^d[56]^d[52]^d[51]^d[49]^d[48]^
416 d[47]^d[45]^d[44]^d[42]^d[41]^d[40]^
417 d[38]^d[37]^d[31]^d[30]^d[28]^d[27]^
418 d[25]^d[22]^d[20]^d[18]^d[17]^d[16]^
419 d[14]^d[11]^d[8]^d[4]^d[3]^d[2]^
420 d[1]^d[0];
421
422assign crc[7] = d[71]^d[70]^d[69]^d[68]^d[66]^d[65]^
423 d[63]^d[62]^d[61]^d[60]^d[59]^d[58]^
424 d[57]^d[53]^d[52]^d[50]^d[49]^d[48]^
425 d[46]^d[45]^d[43]^d[42]^d[41]^d[39]^
426 d[38]^d[32]^d[31]^d[29]^d[28]^d[26]^
427 d[23]^d[21]^d[19]^d[18]^d[17]^d[15]^
428 d[12]^d[9]^d[5]^d[4]^d[3]^d[2]^d[1];
429
430assign crc[8] = d[69]^d[68]^d[64]^d[62]^d[61]^d[60]^
431 d[59]^d[56]^d[55]^d[52]^d[51]^d[50]^
432 d[48]^d[47]^d[43]^d[41]^d[38]^d[37]^
433 d[36]^d[35]^d[34]^d[33]^d[32]^d[30]^
434 d[27]^d[26]^d[25]^d[24]^d[21]^d[20]^
435 d[13]^d[12]^d[10]^d[9]^d[8]^d[7]^
436 d[5]^d[4]^d[2]^d[1]^d[0];
437
438assign crc[9] = d[70]^d[69]^d[65]^d[63]^d[62]^d[61]^
439 d[60]^d[57]^d[56]^d[53]^d[52]^d[51]^
440 d[49]^d[48]^d[44]^d[42]^d[39]^d[38]^
441 d[37]^d[36]^d[35]^d[34]^d[33]^d[31]^
442 d[28]^d[27]^d[26]^d[25]^d[22]^d[21]^
443 d[14]^d[13]^d[11]^d[10]^d[9]^d[8]^
444 d[6]^d[5]^d[3]^d[2]^d[1];
445
446assign crc[10] = d[68]^d[67]^d[64]^d[62]^d[61]^d[57]^
447 d[56]^d[55]^d[50]^d[48]^d[46]^d[45]^
448 d[44]^d[43]^d[42]^d[41]^d[32]^d[28]^
449 d[27]^d[25]^d[23]^d[21]^d[19]^d[18]^
450 d[16]^d[15]^d[14]^d[11]^d[10]^d[8]^
451 d[4]^d[2]^d[1]^d[0];
452
453assign crc[11] = d[71]^d[70]^d[69]^d[67]^d[66]^d[65]^
454 d[62]^d[57]^d[55]^d[54]^d[53]^d[52]^
455 d[51]^d[48]^d[47]^d[45]^d[43]^d[41]^
456 d[40]^d[39]^d[38]^d[37]^d[36]^d[35]^
457 d[34]^d[33]^d[28]^d[25]^d[24]^d[21]^
458 d[20]^d[18]^d[17]^d[15]^d[11]^d[8]^
459 d[7]^d[6]^d[5]^d[2]^d[0];
460
461endmodule
462
463module nbmon_gen_crc_fl(d, crc_fl);
464
465input [71:0] d;
466output [5:0] crc_fl;
467
468assign crc_fl[0] = d[69]^d[66]^d[65]^d[64]^d[63]^d[57]^
469 d[56]^d[54]^d[53]^d[52]^d[49]^d[48]^
470 d[44]^d[43]^d[42]^d[40]^d[38]^d[37]^
471 d[36]^d[35]^d[34]^d[33]^d[31]^d[30]^
472 d[28]^d[24]^d[19]^d[17]^d[16]^d[13]^
473 d[11]^d[9]^d[6]^d[3]^d[2]^d[1]^d[0];
474
475assign crc_fl[1] = d[70]^d[69]^d[67]^d[63]^d[58]^d[56]^
476 d[55]^d[52]^d[50]^d[48]^d[45]^d[42]^
477 d[41]^d[40]^d[39]^d[33]^d[32]^d[30]^
478 d[29]^d[28]^d[25]^d[24]^d[20]^d[19]^
479 d[18]^d[16]^d[14]^d[13]^d[12]^d[11]^
480 d[10]^d[9]^d[7]^d[6]^d[4]^d[0];
481
482assign crc_fl[2] = d[71]^d[70]^d[69]^d[68]^d[66]^d[65]^
483 d[63]^d[59]^d[54]^d[52]^d[51]^d[48]^
484 d[46]^d[44]^d[41]^d[38]^d[37]^d[36]^
485 d[35]^d[29]^d[28]^d[26]^d[25]^d[24]^
486 d[21]^d[20]^d[16]^d[15]^d[14]^d[12]^
487 d[10]^d[9]^d[8]^d[7]^d[6]^d[5]^d[3]^
488 d[2]^d[0];
489
490assign crc_fl[3] = d[71]^d[70]^d[69]^d[67]^d[66]^d[64]^
491 d[60]^d[55]^d[53]^d[52]^d[49]^d[47]^
492 d[45]^d[42]^d[39]^d[38]^d[37]^d[36]^
493 d[30]^d[29]^d[27]^d[26]^d[25]^d[22]^
494 d[21]^d[17]^d[16]^d[15]^d[13]^d[11]^
495 d[10]^d[9]^d[8]^d[7]^d[6]^d[4]^d[3]^
496 d[1];
497
498assign crc_fl[4] = d[71]^d[70]^d[68]^d[67]^d[65]^d[61]^
499 d[56]^d[54]^d[53]^d[50]^d[48]^d[46]^
500 d[43]^d[40]^d[39]^d[38]^d[37]^d[31]^
501 d[30]^d[28]^d[27]^d[26]^d[23]^d[22]^
502 d[18]^d[17]^d[16]^d[14]^d[12]^d[11]^
503 d[10]^d[9]^d[8]^d[7]^d[5]^d[4]^d[2];
504
505assign crc_fl[5] = d[71]^d[68]^d[65]^d[64]^d[63]^d[62]^
506 d[56]^d[55]^d[53]^d[52]^d[51]^d[48]^
507 d[47]^d[43]^d[42]^d[41]^d[39]^d[37]^
508 d[36]^d[35]^d[34]^d[33]^d[32]^d[30]^
509 d[29]^d[27]^d[23]^d[18]^d[16]^d[15]^
510 d[12]^d[10]^d[8]^d[5]^d[2]^d[1]^d[0];
511
512endmodule
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