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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / nas_car / nas.vh
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: nas.vh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef INC_NAS_DEFINE
36
37`else
38
39`define INC_NAS_DEFINE
40
41//----------------------------------------------------------
42// Paths and variables
43`define NASTOP `TOP.nas_top
44`define EXP_QUEUE `NASTOP.exp_queue
45`define ACT_QUEUE `NASTOP.act_queue
46`define EXP_STATUS `NASTOP.exp_status
47`define ACT_STATUS `NASTOP.act_status
48
49`define FRF0_EVEN `SPC0.fgu.frf.frf_array_e.data_array
50`define FRF0_ODD `SPC0.fgu.frf.frf_array_o.data_array
51`define IRF0_EXU0 `SPC0.exu0.irf.irf_array.active_window
52`define IRF0_EXU1 `SPC0.exu1.irf.irf_array.active_window
53
54`define FRF1_EVEN `SPC1.fgu.frf.frf_array_e.data_array
55`define FRF1_ODD `SPC1.fgu.frf.frf_array_o.data_array
56`define IRF1_EXU0 `SPC1.exu0.irf.irf_array.active_window
57`define IRF1_EXU1 `SPC1.exu1.irf.irf_array.active_window
58
59`define FRF2_EVEN `SPC2.fgu.frf.frf_array_e.data_array
60`define FRF2_ODD `SPC2.fgu.frf.frf_array_o.data_array
61`define IRF2_EXU0 `SPC2.exu0.irf.irf_array.active_window
62`define IRF2_EXU1 `SPC2.exu1.irf.irf_array.active_window
63
64`define FRF3_EVEN `SPC3.fgu.frf.frf_array_e.data_array
65`define FRF3_ODD `SPC3.fgu.frf.frf_array_o.data_array
66`define IRF3_EXU0 `SPC3.exu0.irf.irf_array.active_window
67`define IRF3_EXU1 `SPC3.exu1.irf.irf_array.active_window
68
69`define FRF4_EVEN `SPC4.fgu.frf.frf_array_e.data_array
70`define FRF4_ODD `SPC4.fgu.frf.frf_array_o.data_array
71`define IRF4_EXU0 `SPC4.exu0.irf.irf_array.active_window
72`define IRF4_EXU1 `SPC4.exu1.irf.irf_array.active_window
73
74`define FRF5_EVEN `SPC5.fgu.frf.frf_array_e.data_array
75`define FRF5_ODD `SPC5.fgu.frf.frf_array_o.data_array
76`define IRF5_EXU0 `SPC5.exu0.irf.irf_array.active_window
77`define IRF5_EXU1 `SPC5.exu1.irf.irf_array.active_window
78
79`define FRF6_EVEN `SPC6.fgu.frf.frf_array_e.data_array
80`define FRF6_ODD `SPC6.fgu.frf.frf_array_o.data_array
81`define IRF6_EXU0 `SPC6.exu0.irf.irf_array.active_window
82`define IRF6_EXU1 `SPC6.exu1.irf.irf_array.active_window
83
84`define FRF7_EVEN `SPC7.fgu.frf.frf_array_e.data_array
85`define FRF7_ODD `SPC7.fgu.frf.frf_array_o.data_array
86`define IRF7_EXU0 `SPC7.exu0.irf.irf_array.active_window
87`define IRF7_EXU1 `SPC7.exu1.irf.irf_array.active_window
88
89
90//----------------------------------------------------------
91`define EXU_INDEX 0
92`define FP_INDEX 1
93`define LSU_INDEX 2
94`define IMUL_INDEX 3
95`define IDIV_INDEX 4
96`define FDIV_INDEX 5
97`define TLU_INDEX 6
98`define ASI_INDEX 7
99
100`define MAX_FP_REG 4
101`define FEVN_INDEX 0
102`define FODD_INDEX 1
103`define MSK_EVN_INDEX 2
104`define MSK_ODD_INDEX 3
105`define FNUM_INDEX 4
106
107//----------------------------------------------------------
108`define INIT_Q 0
109`define PUSH_Q 1
110`define POP_Q 2
111`define STATUS_Q 3
112`define PR_INSTR_Q 4
113`define FLUSH_TH_Q 5
114
115
116// Number of registers in delta_Q
117`define NEXT_INDEX 0
118`define TIME_INDEX 1
119`define PC_INDEX 2
120`define GL_INDEX 3
121`define CWP_INDEX 4
122`define OPCODE_INDEX 5
123`define FIRST_INDEX 6
124`define MAX_INDEX `FIRST_INDEX+32
125
126`define G_TYPE 0
127`define W_TYPE 1
128`define F_TYPE 2
129`define C_TYPE 3
130
131`define CWP_DECR 0
132`define CWP_INCR 1
133
134`define FP_OFFSET 32
135`define CTL_OFFSET 100
136
137// Number of bits in delta reg arrays
138// 2 bits for type
139// 3 bits for window
140// 8 bits for regnum
141// 64 bits for value
142`define DELTA_WIDTH (2+3+8+64)-1
143
144//----------------------------------------------------------
145// Note: register indexes must be the same as simics
146
147// here's the order of regs in prev_reg
148// [0:7] - G [0-7]
149// [8-23] - W, [8-23]
150// [24-31] - W-1 [8-15]
151// [32-95] - F [0-63]
152// [132-224] - C [32-124]
153`define MAX_ID 224 // for prev_reg index
154
155`define PC 32
156`define NPC 33
157`define Y 34
158`define CCR 35
159`define FPRS 36
160`define FSR 37
161`define ASI 38
162`define TICK 39
163`define GSR 40
164`define TICK_CMPR 41
165`define STICK 42
166`define STICK_CMPR 43
167`define PSTATE 44
168`define TL 45
169`define PIL 46
170
171`define TPC1 47
172`define TPC2 48
173`define TPC3 49
174`define TPC4 50
175`define TPC5 51
176`define TPC6 52
177
178`define TNPC1 57
179`define TNPC2 58
180`define TNPC3 59
181`define TNPC4 60
182`define TNPC5 61
183`define TNPC6 62
184
185`define TSTATE1 67
186`define TSTATE2 68
187`define TSTATE3 69
188`define TSTATE4 70
189`define TSTATE5 71
190`define TSTATE6 72
191
192`define TT1 77
193`define TT2 78
194`define TT3 79
195`define TT4 80
196`define TT5 81
197`define TT6 82
198`define TBA 87
199`define VER 88
200`define CWP 89
201`define CANSAVE 90
202`define CANRESTORE 91
203`define OTHERWIN 92
204`define WSTATE 93
205`define CLEANWIN 94
206`define SOFTINT 95
207`define ECACHE_ERROR_ENABLE 96
208`define ASYNCHRONOUS_FAULT_STATUS 97
209`define ASYNCHRONOUS_FAULT_ADDRESS 98
210`define OUT_INTR_DATA0 99
211`define OUT_INTR_DATA1 100
212`define OUT_INTR_DATA2 101
213`define INTR_DISPATCH_STATUS 102
214`define IN_INTR_DATA0 103
215`define IN_INTR_DATA1 104
216`define IN_INTR_DATA2 105
217`define INTR_RECEIVE 106
218`define GL 107
219`define HPSTATE 108
220`define HTSTATE1 109
221`define HTSTATE2 110
222`define HTSTATE3 111
223`define HTSTATE4 112
224`define HTSTATE5 113
225`define HTSTATE6 114
226`define HTSTATE7 115
227`define HTSTATE8 116
228`define HTSTATE9 117
229`define HTSTATE10 118
230`define HTBA 119
231`define HINTP 120
232`define HSTICK_CMPR 121
233`define MID 122
234`define ISFSR 123
235`define DSFSR 124
236`define DSFAR 125
237`define CTXT_PRIM_0 126 // 21/8
238`define CTXT_SEC_0 127 // 21/10
239`define CTXT_PRIM_1 128 // 21/108
240`define CTXT_SEC_1 129 // 21/110
241`define LSU_CONTROL 130 // 45/0
242`define I_TAG_ACC 131 // 50/30
243`define CTXT_Z_TSB_CFG0 132 // 54/10
244`define CTXT_Z_TSB_CFG1 133 // 54/18
245`define CTXT_Z_TSB_CFG2 134 // 54/20
246`define CTXT_Z_TSB_CFG3 135 // 54/28
247`define CTXT_NZ_TSB_CFG0 136 // 54/30
248`define CTXT_NZ_TSB_CFG1 137 // 54/38
249`define CTXT_NZ_TSB_CFG2 138 // 54/40
250`define CTXT_NZ_TSB_CFG3 139 // 54/48
251`define I_DATA_IN 140 // 54
252`define D_TAG_ACC 141 // 58/30
253`define WATCHPOINT_ADDR 142 // 58/38
254`define D_DATA_IN 143 // 5c
255
256// Can't create control register at 155 because it will collide
257// with OPCODE at 255 since we add 100 to all control register IDs
258`define NAS_PIPE_RESERVED 155
259
260`define OPCODE 255
261`define END_INSTR 999
262//----------------------------------------------------------
263
264`endif
265//----------------------------------------------------------
266// END OF FILE
267//----------------------------------------------------------
Full OpenSPARC design & verification tarball including full HDL.